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Digital Lab7

This document is a submission for Course 111 Introduction to Digital Design Assignment #7 by four students. It includes sections on a clock divider, serial-in serial-out block, finite state machine encoder, and double bit serializer. The submission is to TA Mohamed Elshafey on November 11, 2023 and includes RTL code for the design and a test bench.

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Mostafa Khaled
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15 views

Digital Lab7

This document is a submission for Course 111 Introduction to Digital Design Assignment #7 by four students. It includes sections on a clock divider, serial-in serial-out block, finite state machine encoder, and double bit serializer. The submission is to TA Mohamed Elshafey on November 11, 2023 and includes RTL code for the design and a test bench.

Uploaded by

Mostafa Khaled
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COURSE 111 Introduction to Digital Design

Assignment #: 7

Section #: 16

Submitted by:
1. Ahmed Hafez El-Sayed, V23010322
2. Ahmed Gaber Mohamed, V23010611
3. Ahmed Mohamed Qorany, V23010564
4. Mostafa Khaled Fouad, V23010279

Submitted to TA: Mohamed Elshafey

Date: 11/11/2023
Convolu�onal Encoder

Our Code:

We separated our code into


individual blocks to make it easier
to read.

This is our top-level code and we


call all blocks in it.
1-Clock divider:

Its func�on is to divide our frequency by 2, it


means that every 2 clock cycle from our main
clock generate 1 clock cycle out of our divider

2-Serial in Serial out:

Here the serial data enter the SISO and stored in 4bit register called temp this happen in 4
clocks; the next clock make the data stored get out of SISO in also more 4 clocks.
Of course this happen if reset pin is disabled.
3-FSM Encoder
This FSM encode
our serial input
in a special way
as required.

4-Double bit serializer:

This block takes the 2 outputs from our


FSM then make them in serial form at its
output.
This happen as its running in double the
clock of FSM so it has �me to make the
output from first input and in the next
clock the output from second input
RTL of our design:

The Code of our Test Bench:


The Simula�on:

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