2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

Electronic Circuit and System Design using Python

and VHDL
Ian Grout
Department of Electronic and Computer Engineering
University of Limerick
Limerick, Ireland
[email protected]

Abstract—In electronic system design, there is typically a need and Verilog HDL [3] which allows a design description to be
to develop and simulate descriptions of the design in a suitable initially created and verified through simulation in a technology
language prior to any physical prototyping and production. neutral manner (i.e., not specific to a particular device) that can
Common design flows use one or more languages to achieve this. then be targeted to a specific device, and the same code also
More recently, the use of source-to-source compilers to translate a retargeted to a new device. More recently, the role of language
high-level design description from one language to another has translators (source-to-source compilers, transcompilers or
become a requirement and this approach can be seen in transpilers) has gained interest in that such translators allow a
applications such as hardware system design using the field designer to develop their design source code in a language of
programmable gate array (FPGA). In this paper, the role of the
choice other than VHDL or Verilog HDL and their design to be
Python open-source programming language is considered and the
translation of Python based algorithms to hardware descriptions
translated to HDL code automatically. Fig. 1 shows a simplified
in VHDL is discussed. The paper will discuss the modeling, design flow using a HDL and targeting the FPGA. From an
simulation and translation of design descriptions that are to be initial design description, simulation studies are performed
implemented within the FPGA targeting sensor input and digital which identify whether the design performs (in simulation) as
signal processing requirements. required or not. Any deviation from the required operation is
rectified at this stage. Once the design description is complete, it
Keywords— Python; VHDL; compiler; electronic systems is synthesized into a logic description and targeted to a particular
FPGA (place & route). Finally, the design in the form of
I. INTRODUCTION configuration data is downloaded into the FPGA and the FPGA
is then configured with the design. In addition to the standard
In electronic circuit based sensor system design undertaken design flow, Fig. 1 includes a design route using the Python
today, it is common to use a software programmable device such open-source programming language [4] where the designer can
as a microcontroller (µC), microprocessor (µP) or digital signal create and verify an algorithm in software before translating the
processor (DSP) to implement the required tasks such as sensor algorithm to an HDL for entry into the FPGA design flow.
sampling, data storage, data processing and communications.
However, the required functions that can be performed are based Design requirements
on architecture of the particular processor and sometimes, this
restricts the available performance due to factors such as
hardware speed (available clock frequency, maximum speed of
operation of the logic circuits used and the number of clock Design entry Design entry
cycles required to perform a particular function). More recently,
hardware configurable programmable logic devices (PLDs) such
as the simple programmable logic device (SPLD), complex
Code interface and

Simulation Simulation
translation set-up

programmable logic device (CPLD) and FPGA [1] have

replaced the software programmed processor due to the potential
performance improvements that devices such as the FPGA can Python code to HDL code
provide over the software programmed processors. The FPGA HDL code synthesis
is of particular usefulness due to the availability of translation
programmable logic, embedded memories, hardware multipliers
and embedded digital signal processing (DSP) blocks. This Place & Route
makes the FPGA of particular interest in applications such as Python language,
embedded sensor systems where high-speed sensor signal modules and tools
sampling is to be undertaken, sensor data is to be locally FPGA
processed and finally, sensor data and processed data values are HDL, vendor specific Electronic Design configuration
to be communicated to an external electronic system. In digital automation (EDA) tools and target FPGA
circuit design using the FPGA, it is typical to use a hardware
description language (HDL) such as VHDL (VHSIC HDL) [2] Fig. 1. FPGA design flow incorporating Python

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2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

In this paper, the role of the source-to-source compiler to implementation. This also requires the designer to have an
translate a description written in Python to a HDL equivalent in expertise in the device operation and language support in order
VHDL is considered. The system under consideration is a sensor to create systems that operate correctly and efficiently.
system where an FPGA acts as the digital hardware core. The However, no one device or language supports all possible
FPGA hardware functions are to be written in VHDL and design scenarios and so, increasingly, there is a need for the
synthesized into hardware to target the Xilinx Artix-7 [5] designer to have a working knowledge of multiple devices and
FPGA. The initial description of the sensor sampling, storage languages when working on design projects. More recently,
and processing operations are written in Python in such a manner interest has been gained in the ability to develop design
that the Python functions are readily translated into the required descriptions (both the software and hardware parts of a design)
VHDL description. This paper is structured as follows. Section in one particular language and to translate the design
II will discuss the design of electronic circuits and systems using description into another language, either a SPL or HDL.
the FPGA and a suitable HDL. Section III will consider the
A number of languages and toolsets have been developed to
translation of Python code to VHDL and section IV will discuss
support this idea. Table I identifies seven languages/tools that
requirements for a specific design written in Python to be
have been developed to translate software code into HDL.
translated to VHDL. A case study design will be presented and
discussed in section IV. Section V will conclude the paper.
TABLE I. EXAMPLE TRANSLATORS FOR HDLS
II. ELECTRONIC CIRCUIT AND SYSTEM DESIGN USING Tool Supplier
FPGAS AND HDLS SystemC [6] – now part of Catapult Mentor Graphics
High-Level Synthesis
Electronic circuits and systems today would be designed Handel-C [7] Mentor Graphics
and developed for a wide range of possible applications, and Catapult High-Level Synthesis (HLS) [8] Mentor Graphics
using a number of different circuit design approaches. In many Impulse C [9] Impulse Accelerated
cases, the design would be based on using a mix of hardware Technologies
and software to achieve a design that meets the required Nios® II C-to-Hardware Acceleration Altera
specifications. Such systems would be based on a (C2H) Compiler [10]
programmable (configurable) digital core with digital, analog MATLAB HDL Coder [11] The Mathworks
MyHDL [12] MyHDL Community
and mixed-signal peripherals. During an electronic system
LabVIEW FPGA Module [13] National Instruments
design project, the designer will encounter one or more design
languages where these languages can be categorised as either a
software programming language (SPL) or a HDL. Such The first five (SystemC, Handel-C, Catapult HLS, Impulse
languages are used for modelling, for simulation and in the final C and the Nios® II C-to-Hardware Acceleration (C2H)
application. A choice to make then would be which language or Compiler) are based on source code written using C language
set of languages is/are required or desired to be used. In circuits structures and these can be converted into an HDL description.
containing digital logic functions, from a few digital functions VHDL and Verilog HDL can be target outputs. SystemC and
to complex processors and memory, software programmed Handel-C were early developments in this area. More recently,
processors (µC, µP or DSP) have been the dominant devices in other source code languages have been targeted. For example,
programmable systems where a suitable software program is MATLAB descriptions can be translated to HDL and MyHDL
written to operate the processor hardware is an appropriate is a Python based HDL where a Python description is translated
manner. Both assembly code and the ANSI C language would to VHDL and Verilog HDL.
be the commonly used. More recently, PLDs such as the SPLD,
CPLD and FPGA, have been chosen due to their ability to allow III. PYTHON TO VHDL
the designer to create custom hardware which is optimised to a
particular requirement. The FPGA is particularly useful for In this section, consideration is given to the development of
applications requiring high-speed parallel processing VHDL code from a Python description. Python is a high-level
(concurrency) and embedded digital signal processing (DSP) object-oriented scripting language invented by Guido van
operations. The FPGA is of particular interest here as current Rossum. It first appeared in 1991 and has a wide range of
generation FPGAs have architectures which have been applications from system utility actions through Internet
developed for high-speed embedded DSP operations and scripting and database access. It is also widely used in the
contain hardware blocks such as embedded memory and engineering and scientific communities. Python is considered in
hardware multipliers. They can support complex DSP this work as the source code language due to its wide use and
operations such as the fast Fourier Transform (FFT) and digital language support for engineering. Given the wish to model
filtering. The designs can be created using VHDL or Verilog hardware functionality in Python and to translate this code to
HDL design descriptions and these descriptions can be VHDL (the focus of this work), then suitable knowledge of the
synthesized into logic for the chosen (target) FPGA. For language capabilities, language semantics and syntax are
implementing algorithms such as control, instrumentation and required. There is also a need to know what functions would
DSP, the possible hardware and software implementation need to be translated into hardware (the VHDL code), the target
choices to the designer are numerous. Using specific devices hardware and the intended use of the VHDL code. For example,
and SPL/HDL languages/toolsets, design flows have been the developed code should be capable of both simulation and
developed which guide the designer to using the devices and synthesis. Such a code translator would then consider the need
languages in a manner that optimises the resulting system to:

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2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

• Provide source code constructs (a sub-set of the overall FPGA capabilities where a target FPGA is specified), the output
Python language) that can be translated to an HDL target code is fully documented and the approach is easy to use. The
code equivalent. user requirements therefore need to be major translation toolset
design and implementation considerations given that the toolset
• Be intuitive to use for both the software coder and the would be used by a designer who would not necessarily have an
hardware circuit designer. in-depth knowledge of the FPGA design flow. Consider the
• Be traceable in that each translation step is fully design example shown in Fig. 2. This implements a two-input
documented and explained. multiplier where the input and output values would be signed
floating point numbers. This is the Python source code
• Support different target devices and clock frequencies. considered and consists of three parts:
• Generate, where appropriate, specific target device 1. The first part (multiplier_noreg) is a Python
project information (both operating system folder and function that implements the multiplier operation. It
file requirements) such as device pin user constraints. receives two inputs (x and y) and the function returns
• Allow the design operation to be verified using suitable a single value (result).
testbenches at both the source and target code levels. 2. The second part (main) is the main function and this
• Allow the code operation to be checked using suitable defines the variables (and their associated values) and
verification tools. calls the function multiplier_noreg. It also prints
the values to the display.
• Consider vendor specific HDL coding styles.
3. The third part only runs the main function if the module
• Generate code that is simulatable and synthesizable. name is __main__ . This is a typical approach to only
Choice of behavioral, RTL (register transfer level) or run the module if it is the module first called by the
structural level code output. Python interpreter.
• Adhere, where appropriate, to industry standards. #-------------------------------------------
• Follow a clear design hierarchy development approach. def multiplier_noreg(x, y):
print('Multiplier, unregistered I/O.')
• Be suitably supported, maintained and developed. result = (x * y)
return result
An example of an existing tool that generates HDL code
#-------------------------------------------
from a Python description is MyHDL [12] from the MyHDL
Community. This is a free, open-source package. MyHDL is a def main():
Python based HDL where a Python description is translated to
a = 10.0
both VHDL and Verilog HDL. The output HDL code to b = -5.0
describe the design and simulation (testbench / testfixture) code z = multiplier_noreg(a, b)
for test purposes. Within the limits of the tool functionality, it print('a = ', a, ' b = ', b, ' z = ', z)
allows a designer to: #-------------------------------------------

• Create a design description. if __name__ == '__main__':

print('Run.')
• Simulate the design operation. main()
else:
• Verify the design operation. print('Finish.')

#-------------------------------------------
• Convert the design description to VHDL or Verilog
HDL.
Fig. 2. Python source function: multiplier without registered I/O

IV. MODELLING SENSOR SYSTEM OPERATION IN PYTHON The output is shown in Fig. 3 for the Python script running
AND VHDL in Idle. This source function acts as the design code and the
In this section, an approach to translating Python code to simulation study testbench. For the input values of a and b, the
VHDL is considered which aims to target the FPGA as a digital multiplication function generates z. In logic, this multiplication
core within a sensor system arrangement. The FPGA would would appear as purely a combinational logic circuit or an
need to perform specific functions such as sensor data sampling, embedded hardware multiplier (and combinational logic) in that
storage and processing before communicating the results to an neither the inputs or outputs are registered (stored). The source
external electronic system. The different functions that would code does not account for a finite wordlength that would exist
be required can be considered in turn and the coding styles to in a hardware implementation. It however might also be useful
adopt for both the Python source code and the VHDL target in some situations to register the input, or the output, or both
code elaborated. It would however be important to consider that signals. In such a case, a clock and usually a master reset (or
the translation needs to be verifiable (the output code is set) signal would be required in the logic implementation to
functionally the same as the input code), the target FPGA provide the necessary control and the registered signals would
resources are effectively utilized (using prior knowledge of the be implemented using latches or flip-flops.

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2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

and this signal type would be used to connect VHDL modules

together. In this case, only one Python function is used and so
only one VHDL module representing the Python function is
created. Finally, for all arithmetic operations, the
NUMERIC_STD library is used. Fig. 5 shows a sample
simulation output for the multiplier design for different values
Fig. 3. Python script run in Idle
of inputs A and B.

For the multiplication function as presented, it would be

necessary to derive a suitable VHDL code equivalent which
would be capable of both simulation and synthesis into
hardware. How the Python source code as shown in Fig. 2 can
be represented in hardware would need to be carefully Fig. 5. Example VHDL testbench simulation results
considered and would need to take into account considerations
such as how such a function would be realised within an FPGA,
what coding styles would be recommended by the FPGA V. CONCLUSIONS
vendor and the synthesis capabilities of the target FPGA design This paper has considered the role of source-to-source
tools. In this work, Fig, 4 shows the chosen VHDL design compilers (translators) in the design of digital circuit and
description as a design module (entity and architecture). systems. A design description written in Python was translated
to a VHDL design description equivalent that could be simulated
LIBRARY IEEE; and synthesized into logic targeting the FPGA. The target
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; application was an electronic system design for sensor input and
digital signal processing based on an FPGA core. Needs for
ENTITY multiplier_noreg IS translation of a Python based description into VHDL were
PORT ( A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); identified and discussed. A case study based on a sensor signal
Z : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); processing (multiplication) was presented and elaborated.
Limit : OUT STD_LOGIC);
END ENTITY multiplier_noreg;

REFERENCES
ARCHITECTURE Design1 OF multiplier_noreg IS
[1] Xilinx Inc., Homepage Internet: https://www.xilinx.com/ [6th March
SIGNAL Z_Int : STD_LOGIC_VECTOR(63 DOWNTO 0); 2018]
BEGIN [2] Institute of Electrical and Electronics Engineers, IEEE Std 1076-2008 -
IEEE Standard VHDL Language Reference Manual, 26th January 2009,
Process1 : PROCESS(A, B, Z_Int)
Print ISBN: 978-0-7381-6853-1, Electronic ISBN: 978-0-7381-6854-8,
BEGIN DOI: 10.1109/IEEESTD.2009.4772740
Z_Int(63 DOWNTO 0) <= STD_LOGIC_VECTOR( [3] Institute of Electrical and Electronics Engineers, IEEE Std 1364-2001 -
SIGNED(A(31 DOWNTO 0)) * SIGNED(B(31 DOWNTO 0))); IEEE Standard Verilog Hardware Description Language, Print ISBN: 0-
7381-2826-0, Electronic ISBN: 0-7381-2827-9 DOI:
IF (SIGNED(Z_Int) > 2147483647) THEN
Z(31 DOWNTO 0) <= STD_LOGIC_VECTOR( 10.1109/IEEESTD.2001.93352
TO_SIGNED(2147483647, 32)); [4] Python.org, Python. Internet: [6th March 2018]
Limit <= '1';
ELSIF (SIGNED(Z_Int) < -2147483648) THEN [5] Xilinx, Artix-7 FPGA Family. Internet:
Z(31 DOWNTO 0) <= STD_LOGIC_VECTOR( https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html [6th
TO_SIGNED(-2147483648, 32));
Limit <= '1'; March 2018]
ELSE [6] Mentor Graphics, Mentor Graphics Catapult C Adds SystemC Synthesis
Z(31 DOWNTO 0) <= Z_Int(31 DOWNTO 0);
Limit <= '0'; and Expands Full-Chip Capabilities. Internet:
END IF; https://www.mentor.com/hls-lp/catapult-high-level-synthesis/c-systemc-
hls [6th March 2018]
END PROCESS Process1;
[7] Mentor Graphics, Handel-C Synthesis Methodology. Internet:
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[8] Mentor Graphics, Catapult High-Level Synthesis. Internet:
https://www.mentor.com/hls-lp/catapult-high-level-synthesis/ [6th March
Fig. 4. VHDL target design module (entity and architecture) 2018]
[9] Impulse Advanced Technolgies, Impulse C. Internet:
The VHDL module in Fig. 4 is based on specific design http://www.impulseaccelerated.com/tools.html [6th March 2018]
decisions. The first is that the digital design is based on a 32-bit [10] Altera, Nios® II C-to-Hardware Acceleration (C2H) Compiler. Internet:
bus so that the input and output signals are all 32 bits wide. As https://www.altera.com/en_US/pdfs/literature/ug/ug_nios2_c2h_compile
the multiplication would produce a 64-bit wide signal, to r.pdf [6th March 2018]
maintain the 32 bits then the result of the multiplication is then [11] The Mathworks Inc., HDL Coder. Internet:
limited to the negative and positive number limits allowed by https://www.mathworks.com/products/hdl-coder.html [6th March 2018]
32 bits. Such possible arithmetic conditions should be [12] myHDL, Python to VHDL or Verilog. Internet: http://www.myhdl.org/
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by the hardware. Secondly, signals are used at the module [13] National Instruments, LabVIEW FPGA Module. Internet:
http://sine.ni.com/nips/cds/view/p/lang/en/nid/11834 [6th March 2018]
inputs and outputs of STD_LOGIC_VECTOR enumerated type

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