IRF740

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Vishay Siliconix
Power MOSFET
D
FEATURES
• Dynamic dV/dt rating
TO-220AB Available
• Repetitive avalanche rated
• Fast switching Available

G • Ease of paralleling
• Simple drive requirements
S • Material categorization: for definitions of compliance
D
G S please see www.vishay.com/doc?99912
N-Channel MOSFET Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
PRODUCT SUMMARY Please see the information / tables in this datasheet for details
VDS (V) 400
RDS(on) (Ω) VGS = 10 V 0.55
DESCRIPTION
Qg max. (nC) 63 Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
Qgs (nC) 9.0
ruggedized device design, low on-resistance and
Qgd (nC) 32 cost-effectiveness.
Configuration Single The TO-220AB package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220AB contribute to its
wide acceptance throughout the industry.

ORDERING INFORMATION
Package TO-220AB
Lead (Pb)-free IRF740PbF
Lead (Pb)-free and halogen-free IRF740PbF-BE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 400
V
Gate-source voltage VGS ± 20
TC = 25 °C 10
Continuous drain current VGS at 10 V ID
TC = 100 °C 6.3 A
Pulsed drain current a IDM 40
Linear derating factor 1.0 W/°C
Single pulse avalanche energy b EAS 520 mJ
Repetitive avalanche current a IAR 10 A
Repetitive avalanche energy a EAR 13 mJ
Maximum power dissipation TC = 25 °C PD 125 W
Peak diode recovery dV/dt c dV/dt 4.0 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +150
d
°C
Soldering recommendations (peak temperature) For 10 s 300
10 lbf · in
Mounting torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 9.1 mH, Rg = 25 Ω, IAS = 10 A (see fig. 12)
c. ISD ≤ 10 A, dI/dt ≤ 120 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

S21-0853-Rev. D, 16-Aug-2021 1 Document Number: 91054

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA - 62
Case-to-sink, flat, greased surface RthCS 0.50 - °C/W
Maximum junction-to-case (drain) RthJC - 1.0

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 400 - - V
VDS temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.49 - V/°C
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 400 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS μA
VDS = 320 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 6.0 A b - - 0.55 Ω
Forward transconductance gfs VDS = 50 V, ID = 6.0 A b 5.8 - - S
Dynamic
Input capacitance Ciss VGS = 0 V, - 1400 -
Output capacitance Coss VDS = 25 V, - 330 - pF
Reverse transfer capacitance Crss f = 1.0 MHz, see fig. 5 - 120 -
Total gate charge Qg - - 63
ID = 10 A, VDS = 320 V,
Gate-source charge Qgs VGS = 10 V - - 9.0 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 32
Turn-on delay time td(on) - 14 -
Rise time tr VDD = 200 V, ID = 10 A - 27 -
ns
Turn-off delay time td(off) Rg = 9.1 Ω, RD = 20 Ω, see fig. 10 b - 50 -
Fall time tf - 24 -
Gate input resistance Rg f = 1 MHz, open drain 0.8 - 5.9 Ω
Between lead, D

Internal drain inductance LD 6 mm (0.25") from - 4.5 -

package and center of G
nH
Internal source inductance LS die contact - 7.5 -
S

Drain-Source Body Diode Characteristics

Continuous source-drain diode current IS MOSFET symbol D - - 10

showing the
integral reverse A
G

Pulsed diode forward current a ISM p - n junction diode S

- - 40

Body diode voltage VSD TJ = 25 °C, IS = 10 A, VGS = 0 Vb - - 2.0 V

Body diode reverse recovery time trr - 370 790 ns
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 3.8 8.2 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

S21-0853-Rev. D, 16-Aug-2021 2 Document Number: 91054

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

3.0

RDS(on), Drain-to-Source On Resistance

VGS ID = 10 A
Top 15 V VGS = 10 V
10 V 2.5
8.0 V
ID, Drain Current (A)

101
7.0 V
6.0 V 2.0

(Normalized)
5.5 V
5.0 V 1.5
Bottom 4.5 V

100 4.5 V 1.0

0.5
20 µs Pulse Width
TC = 25 °C
0.0
10-1 100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91054_01 VDS, Drain-to-Source Voltage (V) 91054_04 TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature

VGS 2500
VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
101 10 V Crss = Cgd
8.0 V 2000
Coss = Cds + Cgd
ID, Drain Current (A)

7.0 V
Capacitance (pF)

6.0 V
5.5 V 4.5 V 1500 Ciss
5.0 V
Bottom 4.5 V
1000
100
Coss
500
20 µs Pulse Width Crss
TC = 150 °C
0
10-1 100 101 100 101
91054_02 VDS, Drain-to-Source Voltage (V) 91054_05 VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20
ID = 10 A
VGS, Gate-to-Source Voltage (V)

VDS = 320 V
150 °C 16
101 VDS = 200 V
ID, Drain Current (A)

VDS = 80 V
25 °C 12

8
100

4
20 µs Pulse Width For test circuit
VDS = 50 V see figure 13
10-1 0
4 5 6 7 8 9 10 0 15 30 45 60 75

91054_03 VGS, Gate-to-Source Voltage (V) 91054_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage

S21-0853-Rev. D, 16-Aug-2021 3 Document Number: 91054

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

10
ISD, Reverse Drain Current (A)

150 °C
8
101

ID, Drain Current (A)

25 °C
6

100 4

VGS = 0 V
10-1 0
0.50 0.70 0.90 1.10 1.30 1.50 25 50 75 100 125 150

91054_07 VSD, Source-to-Drain Voltage (V) 91054_09 TC, Case Temperature (°C)

Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

RD
103 VDS
5
Operation in this area limited
2 VGS
by RDS(on) D.U.T.
ID, Drain Current (A)

102 RG
5
+
- VDD
10 µs
2

10 10 V
100 µs
5 Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
2
1 ms

1 10 ms
5
Fig. 10a - Switching Time Test Circuit
TC = 25 °C
2 TJ = 150 °C
Single Pulse VDS
0.1 2 5 2 5 2 5 2 5
0.1 1 10 102 103 90 %
91054_08 VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

10 %
VGS
td(on) tr td(off) tf

Fig. 10b - Switching Time Waveforms

10
Thermal Response (ZthJC)

1
0 - 0.5
PDM
0.2

0.1 0.1
t1
0.05 t2
0.02 Single Pulse Notes:
0.01 (Thermal Response) 1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10

91054_11 t1, Rectangular Pulse Duration (S)

S21-0853-Rev. D, 16-Aug-2021 4 Document Number: 91054

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Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L
VDS
VDS
Vary tp to obtain tp
required IAS
VDD
RG D.U.T +
V DD
- VDS
IAS
10 V
tp 0.01 Ω
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

1200
ID
Top 4.5 A
EAS, Single Pulse Energy (mJ)

1000 5.3 A
Bottom 10 A
800

600

400

200

VDD = 50 V
0
25 50 75 100 125 150

91054_12c Starting TJ, Junction Temperature (°C)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator
Same type as D.U.T.

QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

S21-0853-Rev. D, 16-Aug-2021 5 Document Number: 91054

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF740
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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91054.

S21-0853-Rev. D, 16-Aug-2021 6 Document Number: 91054

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 01-Jan-2023 1 Document Number: 91000