Introduction to Digital System Design

Z. Navabi

Topic 2

Gates and Timing

Zain Navabi

Slides prepared by Katayoon Basharkhah

Introduction to Digital System Design - Copyright Zainalabedin Navabi 1
Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 2

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 3

NMOS and PMOS Transistors
Transistor structure
Gate

Source Drain
Poly Poly
Sio2 Sio2
p+ p+ n+ n+
Vgs n-well
p substrate p substrate
- - -- - - - - - -

PMOS Channel
NMOS

G G
S D S D
Introduction to Digital System Design - Copyright Zainalabedin Navabi 4
NMOS and PMOS Transistors
Transistor structure
Gate

Source Drain
Poly
Sio2
n+ n+

p substrate
- - -- - - - - - -

Channel
G
S D • capacitance and resistance

Introduction to Digital System Design - Copyright Zainalabedin Navabi 5

NMOS and PMOS Transistors
Transistor structure
• We can spot a capacitance and resistance potentially in this
structure:
• The capacitance can be seen between the gate and the body.

• The resistance between the drain and source will stand out very
much when the channel doesn’t exist in the off state.

• When the transistor is on, a little resistance will remain between

the drain and source.

𝐶𝑔 ~ 𝐿 × 𝑊 𝑅𝑔 ~ 𝐿/𝑊

Introduction to Digital System Design - Copyright Zainalabedin Navabi 6

NMOS and PMOS Transistors
Build a model: Use resistors and capacitors?
4- Value logic

Value Level HW Condition

0 Logic zero, False
1 Logic one, True
X Unknown
Z High impedance

Introduction to Digital System Design - Copyright Zainalabedin Navabi 7

NMOS and PMOS Transistors
Unidirectional Transistor Verilog model
• Specify no delay
nmos (d, s, g)

• Specify rise, fall and turn off times

nmos # (To1, To0, ToZ) [instance_name] (d, s, g)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 8

NMOS and PMOS Transistors
Unidirectional Transistor Verilog model
• Specify no delay
nmos (d, s, g)

• Specify rise, fall and turn off times

nmos # (To1, To0, ToZ) [instance_name] (d, s, g)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 9

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
Inverter,Verilog, Testbench
Inverter timing, RC delay
NAND and NOR
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 10

Building Gates
Inverter
• Input “0” will make the PMOS transistor conduct and the NMOS one not
conduct, resulting in a “1” output
• Input “1” will have the output pulled down to “0” through the NMOS
transistor. Vdd

a w
a w
a w 0 1
1 0

𝑤 = ¬𝑎 = 𝑎 = ~𝑎 = 𝑁𝑂𝑇 𝑎 = 𝑎′
NOT gate: Logic, Boolean, Verilog, VHDL, Text
Introduction to Digital System Design - Copyright Zainalabedin Navabi 11
Building Gates
Inverter Verilog description

inport1 outport1

inport2 outport2

. . • Module is the building block

. . of any design
. . • Can be instantiated in other
modules
• Input and output ports
• Will be written inside a
connect the design to the
boundary (module and
outside environment
endmodule)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 12

Building Gates
Inverter Testbench

Like a real testbench

.w(ww), .a(aa)
• Instantiation by name

• Instantiation by position

Introduction to Digital System Design - Copyright Zainalabedin Navabi 13

Building Gates
Gate delay

a b c

vdd vdd
1 0 0 1 1 0

a c

Introduction to Digital System Design - Copyright Zainalabedin Navabi 14

Building Gates
Gate delay and noise margin
• The gate delay can be represented by a propagation delay:
𝑡𝑑 = (𝑡𝑃𝐿𝐻 + 𝑡𝑃𝐻𝐿 )/2 a b c

Logic high Logic high

output range input range
VOH NMH
Forbidden VIH
Zone
VIL
VOL NML
Logic low Logic low
output range input range

• If for some reason such as noise or faulty components, the receiver's input
fall in the forbidden zone between V,IL and VIH, the behavior of the gate is
unpredictable.
𝑁𝑀 = (𝑁𝑀𝐻 + 𝑁𝑀𝐿 )/2
Introduction to Digital System Design - Copyright Zainalabedin Navabi 15
Building Gates
Pull-Up, pulls
NAND gate the output of
the gate to
Vdd

Vdd
#(8,7,9) a b w
0 0 1
0 1 1
Pull-Down, 1 0 1
pulls the
a output of the 1 1 0
gate to gnd

#(6,7,8)
b

NAND gate: Logic, Boolean, Verilog, VHDL, Text

Introduction to Digital System Design - Copyright Zainalabedin Navabi 16

Building Gates
NAND gate Verilog description
Vdd
#(8,7,9)

#(6,7,8)
b

Introduction to Digital System Design - Copyright Zainalabedin Navabi 17

Building Gates
NOR gate
Vdd

a b w
0 0 1
0 1 0
w 1 0 0
1 1 0

a b

NOR gate: Logic, Boolean, Verilog, VHDL, Text

Introduction to Digital System Design - Copyright Zainalabedin Navabi 18
Building Gates
NOR gate - Verilog

Vdd

a b

Introduction to Digital System Design - Copyright Zainalabedin Navabi 19

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 20

Complex Gates
• Gate structures we have seen so far have only parallel or serial
wiring in each of their pull up or pull-down structures.

• In complex gates, these two types of wiring are mixed. In order to

maintain the complementary logic (CMOS), any series wiring in
the pull up structure must be parallel in the pull-down structure
and vice versa

Introduction to Digital System Design - Copyright Zainalabedin Navabi 21

Complex Gates
AOI (And OR Inv)
1
vdd b
c
a

a
w
2
b b
c
c a

W=a+b.c

𝑤 = 𝑎 + 𝑏. 𝑐

Introduction to Digital System Design - Copyright Zainalabedin Navabi 22

Complex Gates
Multiplexer

a
0
y

b 1
s

y = 𝑠. 𝑎 + 𝑠. 𝑏 b

Introduction to Digital System Design - Copyright Zainalabedin Navabi 23

Complex Gates
XOR gate

b
a
a w
b

y = 𝑎. 𝑏 + 𝑏. 𝑎

Introduction to Digital System Design - Copyright Zainalabedin Navabi 24

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 25

Example
Overflow Detector

a7 a0 b7 b0

A
B v
Adder S
OV

s7 s0

A
B
S V

v = 𝐴. 𝐵. 𝑆 + 𝑆. 𝐴. 𝐵

Introduction to Digital System Design - Copyright Zainalabedin Navabi 26

Example
Overflow Detector
A
B
S V

Introduction to Digital System Design - Copyright Zainalabedin Navabi 27

Example
Overflow detector Verilog description

Can be replaced by:

assign #40 v=(~a & ~b &s) | (a&b&~s);

Introduction to Digital System Design - Copyright Zainalabedin Navabi 28

Example
Overflow detector Verilog description

Introduction to Digital System Design - Copyright Zainalabedin Navabi 29

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 CMOS Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 30

Pass transistors
AND gate
B

Problem: The circuit doesn’t drive a

A Y logic low when the B input is logic
low
B

A Y • Only one transistor and one resistor

• Standard CMOS-inverter-based requires six
transistors.
• It does not reliably provide a low-resistance path to
ground.
• It dissipates static power whenever the output is logic
high
Introduction to Digital System Design - Copyright Zainalabedin Navabi 31
Pass transistors
AND gate, OR gate, MUX
B

B
A Y

B A Y

A Y

Introduction to Digital System Design - Copyright Zainalabedin Navabi 32

Pass transistors
AND gate, OR gate, MUX, AND, OR
B

B
A Y

B A Y

A Y

Introduction to Digital System Design - Copyright Zainalabedin Navabi 33

Pass transistors
AND gate, OR gate, XOR
B

B
A Y

B A Y

A Y

Introduction to Digital System Design - Copyright Zainalabedin Navabi 34

Pass transistors
NMOS pass transistor : strong 0 and weak 1

PMOS pass transistor : strong 1 and weak 0

Transmission gate : Combining these two generates a CMOS

pass gate that will pass a strong 0 and strong 1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 35

Transmission Gates
AND gate

Introduction to Digital System Design - Copyright Zainalabedin Navabi 36

Transmission gates
AND gate, OR gate, XOR

Introduction to Digital System Design - Copyright Zainalabedin Navabi 37

Outline

3-1 NMOS and PMOS transistors

3-2 Building Gates
3-3 Complex Structures
3-4 Examples
3-5 Pass transistors and Transmission gates
3-6 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 38

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 39

NMOS logic and CMOS power
Vdd

Introduction to Digital System Design - Copyright Zainalabedin Navabi 40

NMOS logic and CMOS power
Vdd

a b

Introduction to Digital System Design - Copyright Zainalabedin Navabi 41

Outline
3-1 NMOS and PMOS transistors
3-2 Building Gates
3-3 Complex Structures
3-4 Examples
3-5 Pass transistors and Transmission gates
3-6 NMOS logic and CMOS power
3-7 Simulation Model

Introduction to Digital System Design - Copyright Zainalabedin Navabi 42

Simulation Model
Simulation classification
HDL- based Simulation

• Event-based simulation

• Cycle-based simulation

• Event : change in the value of an input or output

• Evaluation takes place only if an input to a gate changes

Introduction to Digital System Design - Copyright Zainalabedin Navabi 43

Simulation Model
Event based simulation

a
c
D=2
b

e
D=1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 44

Simulation Model
4- Value logic

Value Level HW Condition

0 Logic zero, False
1 Logic one, True
X Unknown
Z High impedance

Introduction to Digital System Design - Copyright Zainalabedin Navabi 45

Conclusion
We have covered these topics:
• Transistor structures

• How to build primitive gates

• Gate delay and timing

• What are the complex gates

• Examples on Verilog description and testbenches

• Pass transistors and Transmission gates

• NMOS logic and CMOS power

• Event based simulation models

Introduction to Digital System Design - Copyright Zainalabedin Navabi 46