306 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO.

1, JANUARY 2005

Accurate Determination of Thermal

Resistance of FETs
Ali Mohamed Darwish, Andrew J. Bayba, and H. Alfred Hung

Abstract—The accurate determination of the channel tempera-

ture in field-effect transistors (FETs) and monolithic microwave
integrated circuits is critical for reliability. An original accurate
closed-form expression is presented for the thermal resistance of
multifinger FET structures. The model is based on the solution
of Laplace’s equations in prolate spheroidal coordinates and el-
liptical cylinder coordinates. The model’s validity is verified by
comparing the results with finite-element simulations, and exper-
imental observations from liquid-crystal measurements and spa-
tially resolved photoluminescence measurements. Very close agree-
ment is observed in all cases.
Index Terms—Field-effect transistors (FETs), power FETs,
thermal effects, thermal resistance, reliability.

I. INTRODUCTION Fig. 1. FET dimensions. Gate dimensions are L 2W .

T HE reliability and performance of field-effect transistors

(FETs) and monolithic microwave integrated circuits
(MMICs), particularly for power devices, depend critically
the MMIC designer. For these reasons, most designers rely
on straightforward back-of-the-envelope formulas to estimate
on the operating channel temperature. The maximum allowed the channel temperature. These simplified formulas relate the
channel temperature drives the design of the cooling system, device geometrical structure to the thermal resistance and are
device package, and maximum dc/RF power limitations. There- easy to understand and apply. The drawback of using these
fore, an accurate estimate of channel temperature is highly simple models is the inaccuracy of the result.
desirable during the device (or circuit) design phase. Generally, In this paper, we present a closed-form expression for
the temperature behavior is governed by the three-dimensional the channel temperature that is simple to use and is highly
(3-D) Laplace equation accurate (within 1%–2%) compared to the results of time-con-
suming and complex numerical analysis. It is excellent for
(1) visualization of temperature contours and gaining insight into
the heat-flow problem. The formula takes into account the
where is the temperature at any point in space. Only interaction of heat sources (i.e., gate fingers). The current
a few cases (e.g., concentric spheres, concentric cylinders, par- two-step approach closely mimics the actual heat/temperature
allel plates) can be solved analytically in closed form [1], [2]. propagation. Most MMICs are designed using model-based
The rest are either intractable or result in infinite series sum- microwave computer-aided design (CAD) programs such as
mations [2]. Hence, numerical solutions are more commonly Agilent Technologies’ ADS and Applied Wave Research’s
pursued and a number of simulators have been developed based Microwave Office. By presenting an accurate model, this study
on finite volume, finite difference, and finite-element techniques opens the door for the incorporation of accurate thermal cal-
[3]–[6]. culation into model-based CAD programs and allows for the
However, solving Laplace’s equation using numerical concurrent optimization of RF and thermal performance. This
methods is not practical for most circuit designers for several will accelerate the design cycle significantly.
reasons. First, they require great effort to define the problem To our knowledge, this is the first accurate closed-form ex-
and the boundary conditions; frequently, the solution does not pression for thermal resistance for FET structures. The expres-
converge. Second, they do not allow for device optimization sion predicts the hottest temperature on the device.
with regards to thermal resistance. Third, the simulators re-
quired are generally expensive and are often unavailable to
II. PROBLEM DEFINITION AND SOLUTION
Manuscript received December 22, 2003; revised May 19, 2004. Consider an FET with a constant highly localized heat source
The authors are with the Army Research Laboratory, Adelphi, MD (Fig. 1) on a substrate of thickness and constant thermal con-
20783 USA (e-mail: [email protected]; [email protected];
[email protected]). ductivity . The gate of the device represents a heat source with
Digital Object Identifier 10.1109/TMTT.2004.839916 length and width , and the gate–gate spacing is . The
0018-9480/$20.00 © 2005 IEEE
DARWISH et al.: ACCURATE DETERMINATION OF THERMAL RESISTANCE OF FETs 307

substrate area is assumed to be large enough that it has no ef-

fect (no constraining of heat) on the temperature, which is gen-
erally true in practice. The following boundary conditions are
assumed:
• constant heat flux over a surface area repre-
sents the dissipated power;
• all surfaces (except bottom of substrate ) are adia-
batic, no heat flux allowed. The bottom of the substrate is
an isothermal surface (constant temperature).
The goal is to calculate the thermal resistance and, hence,
find the maximum channel temperature (directly under the gate).
To define various parameters, lets consider a parallel plate (ca-
pacitor-like) structure with thickness , cross-sectional area , Fig. 2. Cross section of an FET. Each FET is composed of multiple gate
thermal conductivity , heat flux , and temperature drop fingers. Finger spacing (gate pitch) is s. Downward heat propagation is
considered through regions I and II.
across the plates. The thermal resistance is
(Fourier’s conduction law). The FET case is more complicated
than the one above. The classical most popular method for cal-
culating thermal resistance of an FET is an approximation based
on Fourier’s conduction law. This approach makes the oversim-
plifying assumption that heat transfer is confined to a 45 wedge
of material between the gate and base. The resulting equation is
as follows:

(2)

Although appreciated for its simplicity and ease of use, it has

been shown to lack accuracy. Several modifications have been
proposed to the above formula [7]–[9] to improve its accuracy
for different special cases (square, circular disk, etc.). However, Fig. 3. Temperature profile of an FET based on finite-element simulation.
the accuracy of the simple models, when applied to the FET Front and side views are shown. In the side view, the elliptical nature of
temperature contours is evident.
problem, remains an issue (percentage error 10%–50%) be-
cause the heat source is a thin long line, not a circle or a square.
An analytical solution for the rectangular patch on a substrate thermal model with an infinite number of fingers to the
and the circular patch on a cylinder is available in the form of right- and left-hand side [14]. For a 100- m-thick sub-
an infinite series summation [10]–[12]. The exact solution is strate and 40- m gate pitch, only two (or four) fingers on
the sum of three infinite series with the last term consisting of each side contribute heat to the center finger. The rest have
two nested infinite summations. After using the infinite series negligible effect.
solution for a few cases, one quickly realizes that convergence • Heat propagation can be divided into two regions I and II.
is very slow with tens of thousands of terms required to arrive at In region I, heat propagates in a radial direction producing
a reasonable answer, assuming numerical instabilities and errors isothermal lines such as and (Fig. 2). In region
are kept under control. Finally, earlier closed-form expressions II, heat propagates downward, producing isothermal lines
based on transmission-line analogies have yielded results with such as and . This is motivated by observation of nu-
10%–20% errors [13]–[15]. merically generated temperature contours from finite-ele-
Next, an accurate expression for the thermal resistance will be ment simulations (see Fig. 3). In region I, heat propagates
derived. In this study, detailed studies of the heat-flux behavior in an ellipsoidal manner. In region II, the propagation is
in FET structures were performed using finite-element simula- similar to the elliptic cylinders case. Fig. 4 shows a 3-D
tions [5]. The results have led to the following observations and view of the isothermal surfaces.
thermal model. The total thermal resistance equals the sum of the thermal
resistances of regions I and II as follows:
• For an FET having multiple fingers, the outer fingers are
the coolest. The fingers in the middle are the hottest. Since
the middle fingers are surrounded to the left- and right- (3)
hand side with numerous fingers, it is appropriate to assign
adiabatic surfaces between each finger and the next, as in- Now, consider the thermal resistance in region I. In the pro-
dicated by the dashed lines in Fig. 2. In reality, only the late spheroidal coordinates, Laplace’s equation has an exact so-
neighboring fingers positioned within one (or two) sub- lution. Namely, the thermal resistance between two half-plane
strate height contribute heat. This leads to an equivalent confocal ellipsoids: A, the inner, and B, the outer ellipsoid, with
308 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005

The remaining task is to relate to the gate spacing in light

of the geometry in Fig. 5. Clearly, if was selected,
then the thermal resistance would be underestimated. If
was selected, then the resistance would be overestimated. There-
fore, an appropriate estimate would be the geometric mean of
the two extremes . Thus,

Hence,

Substituting back into (4), we obtain

Fig. 4. 3-D view of isothermal surfaces for one gate finger. The ellipsoids
represent region I isothermals and the two lower cylinders represent region II
isothermals.

(5)
where

The equations have been rearranged and simplified.

Now consider the thermal resistance of region II. The tra-
ditional method of assuming 45 spreading is not sufficiently
accurate. From Fig. 3, it is observed that isothermal lines ap-
proach an elliptic cylinder shape. This suggests that elliptical
cylinder coordinates may be the most suitable (Fig. 6). Given
two half-plane confocal elliptical cylinders, i.e., and , with
Fig. 5. FET unit cell top view. Isothermal surfaces are modeled as ellipsoids. minor axes and , and major axes and , respec-
The gate is modeled as an ellipsoid with minor axis r and major axis r . tively, and length , the thermal resistance between them is

minor axes and , respectively, and major axes and (6)

, respectively, is where

(4)

where

provided

Again, relating and to the current case

is needed. From Fig. 4, it is reasonable to equate the dimensions
of the inner ellipse (of region II) to the outer prolate ellipsoid of
region I, and assign equal to
The critical task is to relate and to the cur-
rent case. From Fig. 5, it is appropriate to select the dimensions
of the inner ellipsoid, representing the heat source (i.e., gate
finger) as follows:

Hence,
Given that (e.g., 100 versus 0.25 m), can be
approximated by
Next, we can relate to the substrate thickness with re-
spect to the geometry in Fig. 6. It is expected that ,
DARWISH et al.: ACCURATE DETERMINATION OF THERMAL RESISTANCE OF FETs 309

Fig. 6. FET side view. Isothermal lines in region II may be modeled as

confocal elliptical cylinders.

where is a constant between 1 (an underestimate) and 2 (an

overestimate). To determine the proper value for , one can av-
erage the two extremes (leading to ) or
evaluate a number of cases using numerical analysis and deter-
mine empirically. Pursuing the second approach, it is found
that, to a good approximation, . Substituting back into Fig. 7. Temperature profile of isothermal surfaces.
(6), the thermal resistance is obtained as follows:
is important to understand how the temperature drops with dis-
(7) tance away from the channel. Consider the temperature profile
at the cross section of the device (see Fig. 7). The cross section
where shows isothermal surfaces and at displacements
and , respectively. Given a displacement
, it is straightforward to calculate temperature at
displacement from the source. The derived model above gives
as , where is the total dissipated power. It is evident
that
The equations have been rearranged and simplified. The above
results can be summarized to evaluate the total thermal resis- (9)
tance (3) as
where is the thermal resistance between the two
isothermal surfaces at and (see Fig. 7). If the dis-
placement from the heat source is less than (thus,
remaining in region I, Fig. 2), then can be calculated as

(8)
(10)
where
In the typical case, and and, hence, the
expression above, can be simplified as

(11)

This expression indicates that the temperature falls off log-

arithmically away from the source. Thus, if the temperature is
measured a few micrometers away from the gate, it will be sig-
nificantly different from that at the gate edge.
Finally, it should be pointed out that, in deriving the current
model, the following typical conditions were used and they need
Again, the equations have been rearranged and simplified. to be observed to ensure the accuracy of the result.
The expression above gives the temperature at the center (hottest • The heat source is long and thin, i.e., and
region) of the device. (this is true in practical FET geometry).
Experimentally, it is very difficult to measure the temperature • There are at least two gate fingers on each side of the
right at the channel (at gate edge) due to the infinitesimal size center gate finger in order to justify the adiabatic boundary
of the gate. Thus, it is often measured close to the channel. It conditions. Power FETs have multiple parallel fingers.
310 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005

Fig. 8. Dependence of thermal resistance on substrate thickness (t) for several

practical thicknesses. Fig. 10. Dependence of thermal resistance on gatewidth (W g ) for several
practical widths.

Fig. 9. Dependence of thermal resistance on substrate gate length (Lg ) for

several practical situations.
Fig. 11. Dependence of thermal resistance on gate pitch (s) for several
practical spacings assuming t = 50 m.
• The metal thickness of gate, drain, and source is thin
enough (less than 2 m) that heat conduction through
them can be ignored. This is typically the case.

III. VERIFICATION OF MODEL

The validity of the model will be verified using finite-element

simulations (here) and experimental data (in Section IV). Nu-
merical simulations have shown excellent agreement with ex-
periment [16] in calculating thermal resistance, heat flux, and
temperature. The widely used finite-element program ANSYS
will be employed. We begin by analyzing classical cases with
known exact solutions [17], [18] using ANSYS to verify the ac-
curacy of the result. The mesh element shape selected is tetra-
hedral, and highly refined meshing is chosen to ensure the accu- Fig. 12. Dependence of thermal resistance on gate pitch (s) for several
practical spacings assuming t = 100 m.
racy of the result (at the expense of computational speed).The
current model is compared with ANSYS for the case of a GaAs
FET structure (see Fig. 1). Very close agreement is observed that our model very closely mimics the actual heat flux and tem-
(within 1%) between ANSYS and the solutions from the cur- perature propagation in the structure. The default values used
rent model. in Figs. 8–12 (unless otherwise specified) are m,
Figs. 8–12 show the comparison of the thermal impedance m, m, W/cm K, and
as and are changed, respectively. Close observa- m. Based on Figs. 8–12, Table I summarizes the av-
tion of the curves shows that, on average, the error is within erage error, standard deviation of error, and maximum error ob-
only 1%. The overall excellent agreement observed suggests served (compared to ANSYS).
DARWISH et al.: ACCURATE DETERMINATION OF THERMAL RESISTANCE OF FETs 311

TABLE I • gatewidth (62.5 m);

ERROR STATISTICS FOR DIFFERENT METHODS OF ANALYSIS • number of gates (80);
• substrate thickness (100 m);
• base plate temperature (125 C);
• power input (0.0625 W/gate).
Using (8) and taking into account the temperature-dependent
nature of semiconductors (13), the resulting channel tempera-
ture equals K. The measured and calculated channel
temperatures (in Celsius) are as follows.
The thermal resistance predicted by [15]1 and [19] is also
plotted for reference. To produce a closed-form expression, [15] • Measured C
relied on a transmission-line analogy and [19] relied on ex- • Calculated C
tending the constant angle model (2). The approach used in [19] Remarkable agreement is observed. The predicted temperature
is based on amending a model that is too crude to yield accu- according to Cooke’s model [15] is C using the same
rate results. The transmission-line approach used in [15] suf- temperature dependent thermal conductivity. The prediction of
fers from several inaccuracies, including the approximation of the current model provides a closer match to the measured data.
the fringe capacitance, the averaging of temperature across the In addition to the above, [23] reported channel temperature
heat source, and the approximation of elliptic integrals with a measurements on GaAs “dense array” amplifiers with:
closed-form expression. • gate–gate spacing (26 m);
It should be pointed out that, in all of the analysis above, the • gate length (0.5 m);
thermal conductivity was assumed to be constant. In reality, • gatewidth (37.5 m);
is temperature dependent. This can be easily taken into account • number of gates (10);
analytically without any approximation using Kirchhoff’s trans- • substrate thickness (100 m);
formation [20] once the temperature-independent thermal resis- • base plate temperature (125 C);
tance is calculated using the model above. For example, con- • power input 0.8 W/mm (or 0.03 W/gate).
sider the case of GaAs where the thermal conductivity was curve The measured and our calculated channel temperatures are as
fitted from 300 to 600 K (with 0.8% to 1.3% error) as [21] follows.
W/cm K (12) • Measured C
• Calculated C
Once the thermal resistance is calculated from (8), then the tem- Very close agreement is observed. The predicted temperature
perature dependence of can be taken into account by applying according to Cooke’s model [15] is C using the
Kirchhoff’s transformation on (12), which gives same temperature dependent thermal conductivity. Again, the
prediction of the current model provides a closer match to the
(13) experimental results.

where is the base plate temperature in degrees kelvin. B. Spatially Resolved Photoluminescence Measurements
Consider the spatially resolved photoluminescence mea-
IV. COMPARISON WITH EXPERIMENT surements reported in [22] on GaAs pseudomorphic high
The submicrometer gate-length dimension makes it very electron-mobility transistor (pHEMT) devices. This is a rela-
challenging to accurately measure the temperature right at the tively accurate approach to measuring the channel temperature
channel (FET gate edge). Nonetheless, several measurements without perturbing the device. Basically, a laser is focused into
with varying spatial resolutions have been reported using a small spot (approximately 1 m in diameter) on the gate
spatially resolved photoluminescence [22] and liquid crystal finger. The resulting photoluminescence gives a direct measure
techniques [23]. In calculating the channel temperature, the of the bandgap of the material. Knowing the dependence of
nonlinearity of the thermal conductivity needs to be taken into the bandgap on temperature, the channel temperature can be
account to arrive at the correct answer. The semiconductor measured with great resolution. In this case, the laser was
material in the examples below is GaAs; however, the model focused approximately 0.75 m away from the gate finger. The
works equally well for silicon-based devices. following device parameters were used:
• gate–gate spacing (30 m);
A. Liquid-Crystal Measurements • gate length (0.25 m);
• gatewidth (50 m);
Consider the liquid-crystal measurements reported in [23].
• number of gates (4);
The parameters of the GaAs MESFET power amplifier are as
• substrate thickness (100 m);
follows:
• thermal conductivity (0.47 W/K cm);
• gate–gate spacing (20 m); • power input, variable.
• gate length (0.5 m);
Applying (13) with the above parameters and variable input
1It should be noted that there is a typo in [15, eq. (1)]. power, Fig. 13 is obtained. Equation (11) was applied with
312 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005

[6] FEMLAB 3.0, COMSOL Inc., Burlington, MA, 2003.

[7] A. Pacelli, P. Palestri, and M. Mastrapasqua, “Compact modeling of
thermal resistance in bipolar transistors on bulk and SOI substrates,”
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2002.
[8] R. Joy and E. S. Schlig, “Thermal properties of very fast transistors,”
IEEE Trans. Electron Devices, vol. ED-17, pp. 586–594, 1970.
[9] S. Song, S. Lee, and V. Au, “Closed-form equation for thermal constric-
tion/spreading resistances with variable resistance boundary condition,”
in Int. Electronics Packaging Soc. Conf., 1994, pp. 111–121.
[10] R. D. Linstead and R. J. Surty, “Steady state junction temperature of
semiconductor chips,” IEEE Trans. Electron Devices, vol. ED-19, no. 1,
pp. 41–44, Jan. 1972.
[11] D. Kennedy, “Spreading resistance in cylindrical semiconductor de-
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[12] R. David, “Computerized thermal analysis of hybrid circuits,” IEEE
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[13] H. F. Cooke, “FET’s and bipolars differ when the going gets hot,” Mi-
crowaves, pp. 55–61, 1978.
[14] J. V. DiLorenzo and D. D. Khandelwal, GaAs FET Principles and Tech-
Fig. 13. Comparison between calculated and measured channel temperature nology. Dedham, MA: Artech House, 1982.
increase [22]. The dashed line represents the model proposed by [15]. [15] H. F. Cooke, “Precise technique finds FET thermal resistance,” Mi-
crowaves RF, pp. 85–87, 1986.
[16] M. Kuball, J. M. Hayes, M. J. Uren, T. Martin, J. C. Birbeck, R. S.
m to account for the 0.75- m displacement from Balmer, and B. T. Hughes, “Measurement of temperature in active high-
the heat source. Again, close agreement is observed between power AlGaN/GaN HFETs using Raman spectroscopy,” IEEE Electron
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Technol. A, vol. 19, no. 4, pp. 539–545, Dec. 1996.
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simulations across various variables (substrate thickness, gate power GaAs field effect transistors using spatially resolved photolumi-
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ment Symp., 1991, pp. 131–139.
based on GaAs FETs. However, the formulation applies equally
well (this has been investigated by finite-element simulations)
to other semiconductor materials such as Si and SiGe. The
closed-form model can be readily used by device and MMIC
designers to optimize the device geometry and configuration
to achieve the desired electrical and thermal performance
without invoking complex, time-consuming, and often non-
converging numerical techniques. Incorporating the result into
Ali Mohamed Darwish was born in Manhattan, KS,
model-based CAD programs can be easily done (as equations), in 1969. He received the B.Sc. and M.S. degrees (with
thereby allowing the concurrent optimization of RF and thermal honors) in electrical engineering from the University
of Maryland at College Park, in 1990 and 1992, re-
performance and accelerating the design cycle. spectively, and the Ph.D. degree from the Massachu-
setts Institute of Technology (MIT), Cambridge, in
1996.
In 1990, he joined COMSAT Laboratories, where
REFERENCES he conducted the experimental work for his M.S.
thesis. In 1992, he was a Research Assistant with
the Optics and Quantum Electronics Group, MIT.
[1] R. Remsburg, Thermal Design of Electronic Equipment. New York: In 1997, he cofounded Amcom Communications Inc., a leading supplier of
CRC, 2001. high-power microwave devices. In May 2003, he joined the RF Electronics Di-
[2] J. C. Jaeger and H. S. Carslaw, Conduction of Heat in Solids, 2nd vision, Army Research Laboratory, Adelphi, MD, where he currently conducts
ed. Oxford, U.K.: Oxford Univ. Press, 1959. research on wide-bandgap materials (GaN), thermal analysis of active devices,
[3] WinTherm 7.0, ThermoAnalytics Inc., Calumet, MI, 2002. and novel MMIC concepts.
[4] Thermal Analysis System 6.1, Harvard Thermal Inc., Harvard, MA, 1997. Dr. Darwish was the recipient of a National Science Foundation (NSF)
[5] ANSYS 7.0, ANSYS Inc., Canonsburg, PA, 2002. Fellowship.
DARWISH et al.: ACCURATE DETERMINATION OF THERMAL RESISTANCE OF FETs 313

Andrew J. Bayba received the B.S. degree from the H. Alfred Hung received the S.B. degree in elec-
University of Arizona, Tucson, in 1985, and the Mas- trical engineering from the Massachusetts Institute of
ters degree from The Johns Hopkins University, Bal- Technology (MIT), Cambridge, in 1968, and the M.S.
timore, MD, in 1992, both in mechanical engineering. and Ph.D. degrees from Cornell University, Ithaca,
For over 18 years, he has been a Mechanical Engi- NY, in 1970 and 1974, respectively.
neer with the Army Research Laboratory, Adelphi, He is currently with the Army Research Labo-
MD, where, for the last five years, he has focused ratory, Adelphi, MD, where he is involved with the
on packaging and heat removal of high-power-den- development of new electronic devices, sensors,
sity RF Devices. and multifunction RF subsystems. His research
Mr. Bayba is a Professional Engineer in the state of interests include wide-bandgap and compound
Maryland. He is a member of the American Society semiconductors and RF microelectromechanical sys-
of Mechanical Engineers (ASME). tems (MEMS) technologies for millimeter-wave and mixed-signal integrated
circuits. He is the Army lead in a number of research programs. He previously
held various research, functional, and program management positions with
General Technical Services, TRW, Raytheon, and COMSAT Laboratories.
He was also an Adjunct Professor with the George Washington University.
He has been involved in the areas of GaAs and InP HEMTs and HBTs, related
MMICs, and subsystems integration, as well as optical/microwave techniques
for wireless and radar systems, and terrestrial and satellite communications.
He has authored or coauthored over 100 publications in journals, book chapters,
and conference proceedings. He is on the Editorial Boards of technical journals.
Dr. Hung has also been active with IEEE conference technical committees.