Vlsi Lab Maual 20-21 Finalized

AMC
ENGINEERING COLLEGE
(Approved by AICTE, New Delhi & affiliated to VTU, Belagavi)
18th Km, Bannerghatta road, Bengaluru-560083)
DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING
2018 SCHEME:VLSI LAB MANUAL
(Academic year: 2020-21)
LAB CODE/NAME: 18ECL77/VLSI DESIGN LAB
SEMESTER: VII
Student name:
USN:
Year:
1
INDEX TABLE
S. no. Description Page no.
I Vision and Mission statement 5
II PO and PSO statement 6
III CO statement with mapping 7
IV Syllabus 8
V Rubrics 9
VI Introduction 10
crea
List of Experiments
Exp. Bloom’s
Exp. Name CO PO PSO
No. cognitive level
Part-A
Design a Schematic and layout 4, 5
1. Create 2,3, 5 1,2
diagram of Inverter with DC,AC
Analysis.
Design a Schematic and layout Create 4 ,5 2,3, 5 1,2
diagram of NAND with DC,AC
2. Analysis
Design a Schematic and layout Create 4,5 2,3, 5 1,2
3. diagram of Common Sourcs (CS)
with DC,AC Analysis
4 Design a Schematic and layout Create 4,5 2,3,5 1,2
diagram of Opamp with DC,AC
Analysis
Part-B
1. Design a Verilog code for the Flip- Apply 1 2,3,5,10 1,2
flops and Latches and perform
Simulation and Synthesizes
2. Design a Verilog code for the 4- bit Apply 2 2,3,5,10 1,2
counter and perform Simulation and
Synthesizes
3. Design a Verilog code for the Apply 2 2,3,5,10 1,2

Asynchronous adder and perform
Simulation sand Synthesizes
Design a Verilog code for the 32- 3
4. Apply 2,3,5,10 1,2
bit ALU and perform Simulate and
Synthesizes
Design a Verilog code for the Apply 3 2,3,5,10 1,2
5. URAT and perform Simulation and
Synthesizes.
CONTENTS BEYOUND SYLLABUS
Design a Verilog code for the APPLY 2,3,5,10 1,2
6. BOOTH MULTIPLEXER(RADIX-
4) and perform Simulation and
Synthesizes.
I. VISION MISSION AND PROGRAM EDUCATIONAL OBJECTIVES
STATEMENT
INSTITUTE VISION
To be a leader in imparting value based Technical Education and Research for the benefit of society.
INSTITUTE MISSION
 To provide state of the art Infrastructure facilities.
 To implement modern pedagogical methods in delivering the academic programs with
experienced and committed faculty.
 To create a vibrant ambience that promotes Learning, Research, Invention and Innovation.
 To undertake manpower and skill development programmes for Academic Institutions and
Industries.
 To enhance Institute Industry Interface through Collaborative Research and Consultancy
 To generate and disseminate knowledge through training
programme/workshops/seminars/conferences/publications.
 To be a more comprehensive college in terms of the number of programs offered.
 To relentlessly pursue professional excellence with ethical and moral values.
DEPARTMENT VISION
To develop outstanding Electronics and Communication Engineers to meet the ever changing
Social and Technological needs of the Society.
DEPARTMENT MISSION
MoD1 To provide State-of-the-Art infrastructure in Electronics and Communication Engineering.
To disseminate strong theoretical and practical exposure to meet the emerging trends in the
MoD2 industry.
MoD3 To promote a free thinking environment with innovative teaching-learning pedagogy.
To develop value based socially responsible professionals for the betterment of the
MoD4
Society.
PROGRAM EDUCATIONAL OBJECTIVES (PEO)

Develop and excel in their chosen profession on technical front and/or progress towards
PEO1
advanced continuing education, Inter-disciplinary Research and Entrepreneurship.
Become reputed and innovative solution provider to complex system design problems or
PEO2
challenges relevant to Electronics and Communication.
Progress as effective team members and achieve a leadership position with trust, mutual
PEO3
respect and professional ethics.
Become responsible and pro-active citizens for the overall welfare and progress of the
PEO4
Society.
II. PO AND PSO STATEMENT
Engineering knowledge: Apply the knowledge of mathematics, science, engineering

PO1 fundamentals, and an engineering specialization to the solution of complex engineering
problems.
Problem analysis: Identify, formulate, review research literature, and analyze complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Design/development of solutions: Design solutions for complex engineering problems and
PO3
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
Conduct investigations of complex problems: Use research-based knowledge and
PO4 research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modelling to complex
engineering activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
Environment and sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
PO8
norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a member or
PO9
leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
PO10
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
Project management and finance: Demonstrate knowledge and understanding of the
PO11 engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the preparation and ability to engage
PO12
in independent and life-long learning in the broadest context of technological change.
Develop the components for analog and digital systems, communication systems, control
PSO1 and signal processing systems using acquired knowledge of basic skills and various design
tools.
Formulate the solution for interdisciplinary problems through acquired programming
PSO2
knowledge in the respective domain by complying real-time constraints.
III. CO STATEMENT WITH MAPPING
Course outcomes Bloom’s

CO. No. After completing the course the Cognitive Level
student will be able to:
Design stimulate and synthesize the
CO407.1 sequential circuits using flip-flops, Apply
Latches, counters.
Design stimulate and synthesize the

CO407.2 combinational circuit using adder. Apply
Design stimulate synthesize using

CO407.3 Apply
ALU &URAT
Design a schematic diagram for
CO407.4 Create
INV,NAND , CS and Opamp.
Design a layout for INV,NAND ,CS

CO407.5 and Opamp. Create
Strength of CO Mapping to PO/PSOs:
CO. PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO

No. 1 2 3 4 5 6 7 8 9 10 11 12 1 2
C208.1 3 - - - - - - - - - - - 2 2
C208.2 - - 3 - - - - - - - - - 2 2
C208.3 - - 3 - - - - - - - - 2 -
C208.4 - - 3 - - - - - - - - - 2
C208.5 - - 1 - - - - - 1 - - 1 1 1
3: Strong, 2: Medium, 1: Weak

VII-SYLLABUS
B. E. EC / TC
Choice Based Credit System (CBCS) and Outcome Based Education (OBE)
SEMESTER – III
VLSI DESIGN LABORATORY
Laboratory Code 18ECL77 IA Marks 40
02Hr Tutorial (Instructions)
Number of Lecture Hours/Week Exam Mark 60
+ 02 Hours Laboratory
CREDITS 02 Exam Hour 03
Course objectives:This laboratory course enables students to get practical experience in design,
verification , synthesis ,schematic and layout of
 Flip-Flops,Latches,Adders,Counter ALU and URAT Programs.
 Schematic of Inverter, NANA, Common Source(CS).
 Layout formation of Inverter, NANA, Common Source(CS).
NOTE:
For stimulate we use tool Mentogaphics.
For synthesis we use tool oyasis.
For schematic we use tool S-edit.
For layout we use tool T-edit softwares
Part-A
Design the Schematic diagram for the followings with their Layout.
Inverter(INV)
NAND
Common Source(CS)
Opamp
Part-B
Perform stimulation and synthesis for below programs.
(i)Flip-flops and Latches.
(ii)4-bit counter
(iii)Asynchronous adder
(iv)32- bit ALU
(v)URAT
Conduction of program beyond syllabus
(vi)Booth multiplexer(Radix-4)
Conduct of Practical Examination:
 All laboratory experiments are to be included for practical examination.
 Students are allowed to pick one experiment from the lot.
 Strictly follow the instructions as printed on the cover page of answer script for breakup of
marks.
 Change of experiment is allowed only once and 15% Marks allotted to the procedure
part to be made zero.
IV. RUBRICS
S.no. Description( IA 1) Marks allotted
1 Write-up 15
2 Execution 70
3 Viva 15
Total Marks 100
S.no. Description (IA 2) Marks allotted
1 Write-up 15
2 Execution 70
3 Viva 15
Total Marks 100
S. no. Description Marks allotted
1 Observation Note Book 12
2 Record Book 12
3 Average of Two Internal Assessment 16
Total CIE Marks 40

Tanner S – edit - Create new library
Add generic libraries for schematic design

Add generic libraries for schematic design
Create new schematic cell

Draw inverter schematic design
Inverter wire connection

Schematic design check
Generate inverter symbol
Create inverter testbench

Draw inverter testbench
Add input and output ports

Adding vdc sources
Add vpulse source

Add Gnd and wire connections
Design check inverter Testbench

Save T Spice file
Inverter testbench simulation general settings

Inverter testbench simulation Transient settings
Run simulation
Tanner L – edit – create new design
Click File -> New -> Design
Browse design path and select Open Access referenced
libraries option in Technology reference
Click OK
Add generic libraries

Click OK
• Add technology libraries and click OK

Create new layout cell
Type cell name similar to s-edit to access SDL navigator
Select view type as layout
Click OK
Load T-spice netlist

• Click Load net list icon in SDL navigator window.
• Browse T-spice netlist file and select file format as T-
spice.
Netlist Layout settings
• Select Metal1 drawing as Layer
• Click OK
Layout design
• Use Poly layer and Metal1 layer to establish
connection between nmos and pmos
•
Layout design
• Use Cnt_Poly from library to connect vin at poly layer
• Vin cannot be directly connected to poly layer
Layout design
• Complete layout design through metal1 layer
connection and place vdd, vss and vout in their
respective places
• Use ctrl+c and ctrl+v to copy metal1 layers
PART-A
EXPERIMENT NO.1
INVERTER
INVERTER schematic
INVERTER test bench schematic

Waveforms
Transient analysis
LAYOUT:
EXPERIMENT NO.2
2-BIT NAND GATE
NAND schematic
NAND test bench schematic

Waveforms
Transient analysis
Layout:
EXPERIMENT NO.3
COMMON SOURCE AMPLIFIER
Cs amplifier with pmos current mirror schematic
Cs amplifier testbench schematic
Waveforms
Transient analysis
Layout:
EXPERIMENT NO.4
OPAMP
Schematic
Testbench Schematic
Waveforms
Transient analysis
Layout:
PART-B
Stepsto –QuestaSim.
• To start QuestaSim GUI in Linux following commandsare use

• cshcommand invokes the Cshell
• Cshell is an interactive commandinterpreter
• Sourceis a shell built-in command which is used to read and execute the content of a file, passedasan argument in the current shell
script
• Vsim command invokes QuestaSim
Create and map library

• Changeto current working directory eg:questa_sample
• Createvlib work directory through command – vlib work
• Map the library through command – vmap workwork
• ClickFile -> source -> Verilog
•
Create and map library
• Changeto current working directory eg:questa_sample

• Createvlib work directory through command – vlib work
• Map the library through command – vmap work work
• ClickFile -> source -> Verilog
Create verilogprogram
4 bit up counter program is created with active high reset
Clicksaveicon in toolbar to saveverilog program file
3
Compileverilogprogram
• ClickCompile -> compile to check syntax errors in the program
• Select the verilog file and click Compilebutton.
Compilation results
• Compilation results will be displayed in the Transcriptwindow
• Errors and warnings details will bedisplayed
• vlog command is an alternative foe the GUIcompilation processwhich is used
Functional simulation
• ClickSimulate -> Start Simulation

• Select module name cnt in work directory.
• Enableoptimization
• Click OK.
• vsim command canbe used to do
simulation.
4
Addwave
• Right click on module name cnt in library and clickAdd wave (Ctrl +W)
• add wave * is the command to add wave through transcript
Forceinputs reset and clock
• Clickrst -> Forcegive values1 or 0 and click OK

• Clickclk -> Clockgive values and click OK
Click run icon
Steps to synthesis using Oasys
• Runshell with csh command
• Initiate cshrc file through command –source filepath.cshrc
• Use oasys command to open oasystool
16
RunOasysscript
• Run oasys synthesis script through command – source filepath.tcl
17
Start oasysGUI
• After scripts execution completed successfully type command start_gui tostart oasys application GUI.
• If there is any error, itwill be displayed by stopping scripts execution and design data won’t be exported to outputdirectory
18
Oasys source
• Start_gui command opens the oasys-RTLtool and verilog code of our program will be displayed in sourcetab.
• In the givenexample 4 bit

countercode
is displayed insource
window
19
Oasysnetlist
• Netlist window canbe viewed through clicking Netlist button
• SI-scan input SE-scan

enable SO-scanoutput
20
Oasysnetlist
• Detailed gate level netlist structure canbe seenby zoomin through continuous double clicks
• In the given example standard Half Adder, NOR,ANDandAOIare used
21
Oasysnetlist
• In Netlist window we canalso seewhich procedural block isused

• Following picture shows that always block is used for this example
22
Oasysnetlist
• Following picture givesthe detailed view of the always block is used for thisexample
• Dflip flop is used to achieve the behavior which is shown inpic
23
Oasysnetlist
• Following picture shows the schematic of four flip flops which are used to achieve the requirement for thisexample
Oasysoutput:
module adder(a, b, cin, sum, carry);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]sum;
output carry;
wire n_0_0_0;
wire n_0_0_1;
wire n_0_0_2;
wire n_0_0_3;
wire n_0_0_4;
wire n_0_0_5;
wire n_0_0_6;
wire n_0_0_7;
wire n_0_0_8;
wire n_0_0_9;
wire n_0_0_10;
wire n_0_0_11;
wire n_0_0_12;
wire n_0_0_13;
wire n_0_0_14;
NOR2_X1 i_0_0_17 (.A1(b[2]), .A2(a[2]), .ZN(n_0_0_12));

OAI21_X1 i_0_0_15 (.A(b[0]), .B1(cin), .B2(a[0]), .ZN(n_0_0_10));
INV_X1 i_0_0_14 (.A(n_0_0_10), .ZN(n_0_0_9));
AOI21_X1 i_0_0_13 (.A(n_0_0_9), .B1(a[0]), .B2(cin), .ZN(n_0_0_8));
NAND2_X1 i_0_0_16 (.A1(b[1]), .A2(a[1]), .ZN(n_0_0_11));
NAND2_X1 i_0_0_12 (.A1(n_0_0_8), .A2(n_0_0_11), .ZN(n_0_0_7));
OAI21_X1 i_0_0_11 (.A(n_0_0_7), .B1(a[1]), .B2(b[1]), .ZN(n_0_0_6));
NAND2_X1 i_0_0_18 (.A1(b[2]), .A2(a[2]), .ZN(n_0_0_13));
AOI21_X1 i_0_0_10 (.A(n_0_0_12), .B1(n_0_0_6), .B2(n_0_0_13), .ZN(n_0_0_5));
XNOR2_X1 i_0_0_1 (.A(b[3]), .B(a[3]), .ZN(n_0_0_0));
XNOR2_X1 i_0_0_0 (.A(n_0_0_5), .B(n_0_0_0), .ZN(sum[3]));
OR2_X1 i_0_0_3 (.A1(n_0_0_13), .A2(n_0_0_6), .ZN(n_0_0_1));
AOI22_X1 i_0_0_2 (.A1(n_0_0_5), .A2(n_0_0_1), .B1(n_0_0_12), .B2(n_0_0_6),
.ZN(sum[2]));
XOR2_X1 i_0_0_5 (.A(b[1]), .B(a[1]), .Z(n_0_0_2));
XNOR2_X1 i_0_0_7 (.A(cin), .B(a[0]), .ZN(n_0_0_3));
XNOR2_X1 i_0_0_6 (.A(b[0]), .B(n_0_0_3), .ZN(sum[0]));
NAND2_X1 i_0_0_19 (.A1(b[3]), .A2(a[3]), .ZN(n_0_0_14));
OAI21_X1 i_0_0_9 (.A(n_0_0_5), .B1(a[3]), .B2(b[3]), .ZN(n_0_0_4));
NAND2_X1 i_0_0_8 (.A1(n_0_0_14), .A2(n_0_0_4), .ZN(carry));
Endmodule
VLSI Lab Manual
EXPERIMENT NO.1
FLIP FLOPS SIMULATION AND SYNTHESIS
(i) SR-Flip Flop
Aim: Design and simulate SR Flip Flop in one of the following modeling styles
(Behavioral, Data flow or Structural) using Verilog.
Block Diagram Truth Table
Program
module rs_ff(rs, clock,rest q, qb);

input [1:0] rs ;
input clock ,rest;
output q, qb;
reg q, qb;
always @ (posedge clock)
begin
if(rest)
q=1’b0;
else
case (rs)
2'b00 : q = q ;
2'b01 : q = 1'b1 ;
2'b10 : q = 1'b0 ;
2'b11 : q = 1'dZ ;
endcase
qb =~ q;
end
endmodule
Dept. of ECE, AMCEC Page 1

VLSI Lab Manual
Test Bench
module rs_ff_tb;
reg [1:0] rs;
reg clock,rest;
wire q, qb;
rs_ff rs_ffuut(rest,clock,rs,q,qb);
initial
clock=1'b1;
rest=1’b0;
end
always #5 clock=~clock;
always #20 rest=~rest;
initial
begin
rs=2'b00;
#20 rs =2'b01;
#20 rs =2'b10;
#20 rs =2'b11;
end
initial
$monitor ($time, "rs=%b, clock=%b ,rest=%b,q=%b, qb=%b ", rs, q, qb);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module srff(sr, clock, q, qb);
input [1:0]sr;
input clock;
output q;
output qb;
wire n_1_0;
wire n_1_1;
wire n_1_2;
wire n_1_1_0;
wire n_1_3;
wire n_1_1_1;
wire n_1_1_2;
NOR2_X1 i_1_1_4 (.A1(sr[0]), .A2(n_1), .ZN(n_1_1_1));

NOR2_X1 i_1_1_3 (.A1(sr[1]), .A2(n_1_1_1), .ZN(n_1_3));
SDFF_X1_LVT q_reg (.D(n_1_3), .SE(1'b0), .SI(n_1), .CK(clock), .Q(n_1), .QN());
INV_X1 i_1_1_5 (.A(sr[1]), .ZN(n_1_1_2));
OAI21_X1 i_1_1_2 (.A(n_1_1_2), .B1(n_1_0), .B2(sr[0]), .ZN(n_1_1_0));
OAI21_X1 i_1_1_1 (.A(n_1_1_0), .B1(n_1_1_2), .B2(sr[0]), .ZN(n_1_2));
SDFF_X1_LVT i_1_8 (.D(n_1_2), .SE(1'b0), .SI(n_1_0), .CK(clock), .Q(n_1_0),
.QN());
INV_X1 i_1_0 (.A(n_1_0), .ZN(n_0));
TBUF_X1 i_0 (.A(n_1), .EN(n_0), .Z(q));
OAI21_X1 i_1_1_0 (.A(n_1_1_2), .B1(q), .B2(sr[0]), .ZN(n_1_1));
SDFF_X1_LVT qb_reg (.D(n_1_1), .SE(1'b0), .SI(qb), .CK(clock), .Q(qb), .QN());
endmodule
Result:

VLSI Lab Manual
(ii) D Flip Flop

Aim: Design and simulate D FLIP FLOP in one of the following modeling styles (Behavioral
Data flow or Structural) using Verilog.
Program
module dff (reset, clock, d, q, qb);

input reset, clock, d;
output q, qb;
reg q;
begin
if (reset)
q<=1'b0;
else
q<=d;
end
assign qb=~q;
endmodule

VLSI Lab Manual
Test Bench
module dff_tb;
reg clock, reset, d;
wire q, qb;
dff uut (reset, clock, d, q, qb);
Initial
Begin
clock=1'b1;
reset=1'b0;
d=1`b0;
End
always#5 clock=~clock;
always#40 reset=~reset;
Initial
Begin
#20 d =1'b1;
#20 d =1'b0;
#20 d =1'b1;
#50 d =1'b0;
end
initial
begin
$monitor ($time, "reset=%b clock=%b d=%b q=%b qb=%b", reset, clock, d, q, qb);
end
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module dff(rst, clk, d, q, qb, SE, SI, SO);
input rst;
input clk;
input d;
output q;
output qb;
input SE;
input SI;
output SO;
wire n_0_0_0;
wire n_0_0;
INV_X1 i_0_0_0 (.A(d), .ZN(n_0_0_0));

NOR2_X1 i_0_0_1 (.A1(n_0_0_0), .A2(rst), .ZN(n_0_0));
SDFF_X1_LVT q_reg (.D(n_0_0), .SE(SE), .SI(SI), .CK(clk), .Q(q), .QN(SO));
Endmodule
Result:

VLSI Lab Manual
(iii) JK Flip Flop
Aim: Design and simulate JK Flip Flop in one of the following modelingstyles (Behavioral,
Data flow or Structural) using Verilog.
Program:
module JK_FF (JK, clock, rest,q, qb);

input [1:0] JK;
input clock,rest;
output q, qb;
reg q, qb;
begin
if(rest)
q=1’b0;
else
case (JK)
2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
2'b11 : q =~ q;
endcase
qb =~ q;
end
endmodule

VLSI Lab Manual
Test Bench
module JK_ff_tb;
reg [1:0] JK;
reg clock,rest;
wire q, qb;
JK_FF uut(JK,rest, clock, q, qb);
initial
clock=1'b1;
always #20 rest=~rest;
initial
begin
JK=2'b00; #20;
JK=2'b01; #20;
JK=2'b10; #20;
JK=2'b11; #50;
end initial
$monitor ($time, "JK=%b ,rest=%b,q=%b ,qb=%b ", JK,clock,rest, q, qb);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module jkff(jk, clk, q, qb, SE, SI, SO);
input [1:0]jk;
input clk;
output q;
output qb;
input SE;
input SI;
output SO;
wire n_0_0;
wire n_0_0_0;
wire n_0_2;
wire n_0_1;
NOR2_X1 i_0_0_1 (.A1(q), .A2(jk[1]), .ZN(n_0_0_0));

AOI21_X1 i_0_0_0 (.A(n_0_0_0), .B1(jk[0]), .B2(q), .ZN(n_0_0));
SDFF_X1_LVT q_reg (.D(n_0_0), .SE(SE), .SI(SI), .CK(clk), .Q(q), .QN(n_0_2));
INV_X1 i_0_4 (.A(n_0_0), .ZN(n_0_1));
SDFF_X1_LVT qb_reg (.D(n_0_1), .SE(SE), .SI(n_0_2), .CK(clk), .Q(qb),
.QN(SO));
endmodule
Result:

VLSI Lab Manual
EXPERIMENT NO.2
LATHCHES SIMULATION AND SYNTHESIS
(i) SR-Latches
Aim: Design and simulate SR Latches in one of the following modeling styles
Block Diagram
Truth Table
S q S R en q qb
0 0 0 x x
en 0 1 1 0 1
R qb
1 0 1 1 0
b
1 1 1 0 0
Program:
module rs_ff(rs,enable,q,qb);
input[1:0]rs;
input enable;
output q,qb;
reg q,qb;
always@(posedge enable)
begin
case(rs)
2'b00:q=q;
2'b01:q=1'b1;
2'b10:q=1'b0;
2'b11:q=1'dz;
endcase
qb=~q;
end
endmodule

VLSI Lab Manual
Test Bench
module rs_ff_tb;
reg[1:0]rs;
reg enable;
wire q,qb;
rs_ff uut(rs,enable,q,qb);
initial
enable=1'b1;
always#5 enable=~enable;
initial
begin
rs=2'b00;
#20 rs=2'b01;
#20 rs=2'b10;
#20 rs=2'b11;
end
initial
$monitor($time,"rs=%b q=%b qb=%b",rs,q,qb);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module srl(rs, enable, q, qb);
input [1:0]rs;
input enable;
output q;
output qb;
wire n_1_0;
wire n_1_1;
wire n_1_2;
wire n_1_1_0;
wire n_1_3;
wire n_1_1_1;
wire n_1_1_2;
NOR2_X1 i_1_1_4 (.A1(rs[0]), .A2(n_1), .ZN(n_1_1_1));

NOR2_X1 i_1_1_3 (.A1(rs[1]), .A2(n_1_1_1), .ZN(n_1_3));
SDFF_X1_LVT q_reg (.D(n_1_3), .SE(1'b0), .SI(n_1), .CK(enable), .Q(n_1),
.QN());
INV_X1 i_1_1_5 (.A(rs[1]), .ZN(n_1_1_2));
OAI21_X1 i_1_1_2 (.A(n_1_1_2), .B1(n_1_0), .B2(rs[0]), .ZN(n_1_1_0));
OAI21_X1 i_1_1_1 (.A(n_1_1_0), .B1(n_1_1_2), .B2(rs[0]), .ZN(n_1_2));
SDFF_X1_LVT i_1_8 (.D(n_1_2), .SE(1'b0), .SI(n_1_0), .CK(enable), .Q(n_1_0),
.QN());
INV_X1 i_1_0 (.A(n_1_0), .ZN(n_0));
TBUF_X1 i_0 (.A(n_1), .EN(n_0), .Z(q));
OAI21_X1 i_1_1_0 (.A(n_1_1_2), .B1(q), .B2(rs[0]), .ZN(n_1_1));
SDFF_X1_LVT qb_reg (.D(n_1_1), .SE(1'b0), .SI(qb), .CK(enable), .Q(qb), .QN());
endmodule
Result:

VLSI Lab Manual
(ii) JK-Latches
Aim: Design and simulate JK-Latches in one of the following modeling styles
J q J K en q qb
0 0 0 x x
en
0 1 1 0 1
1 0 1 1 0
K qb 1 1 1 0 0
Program:
module jkl(jk,enable,q,qb);
input[1:0]jk;
input enable;
output q,qb;
reg q,qb;
always@(enable)
begin
case(jk)
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

VLSI Lab Manual
Test Bench:
module jkl_tb;
reg [1:0]jk;
reg enable;
wire q,qb;
jkl uut(jk,enable,q,qb);
initial
enable=1'b1;
initial
begin
#20 jk=2'b00;
#20 jk=2'b01;
#20 jk=2'b10;
#20 jk=2'b11;
end
initial
$monitor($time,"enable=%b,jk=%b,q=%b,qb=%b",enable,jk,q,qb);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module jkl(jk, enable, q, qb);
input [1:0]jk;
input enable;
output q;
output qb;
wire n_0_1;
wire n_0_0;
wire n_0_0_0;
INV_X1 i_0_0_3 (.A(jk[1]), .ZN(n_0_0_0));

AOI21_X1 i_0_0_0 (.A(n_0_0_0), .B1(q), .B2(jk[0]), .ZN(n_0_1));
OR2_X1 i_0_0_1 (.A1(jk[0]), .A2(jk[1]), .ZN(n_0_0));
DLH_X1 q_reg (.D(n_0_1), .G(n_0_0), .Q(q));
INV_X1 i_0_0_2 (.A(q), .ZN(qb));
endmodule
Result:

VLSI Lab Manual
(iii) D-Latches
Aim: Design and simulate D-Latche in one of the following modeling styles
D q D en q qb
0 0 x x
en
0 1 0 1
qb
1 1 1 0
1 1 0 0
Program:
module dl(d,enable,q,qb);
input d,enable;
output q,qb;
reg q,qb;
always @(enable)
begin
if(enable)
q<=1'b0;
else
q<=d;
end
assign qb=~q;
endmodule

VLSI Lab Manual
Test Bench:
module dl_tb;
reg d,enable;
wire q,qb;
dl uut(d,enable,q,qb);
initial
enable=1'b1;
initial
begin
#20 d=1'b1;
#20 d=1'b0;
#20 d=1'b1;
#20 d=1'b0;
end
initial
$monitor($time,"d=%b,enable=%b,q=%b,qb=%b",d,enable,q,qb);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module dl(en, d, q);
input en;
input d;
output q;
output qb;
DLH_X1 q_reg (.D(d), .G(en), .Q(q));
INV_X1 1-0-0-0(.A(q), .ZN(/qb));
endmodule
Result:

VLSI Lab Manual
EXPERIMENT NO.2
4BIT-ADDER DESIGN AND SIMULATION
Aim: Design a 4-Bit adder in one of the following modeling styles (Behavioral, Data flow or
Structural) using Verilog.
Block Diagram
sum[3] sum[2] sum[1] sum[0]
Sum sum sum sum

fa3 cin w3 fa2 cin w2 fa1 cin w1 fa0 cin
Cin
carry carry carry carry
a b a b a b a b
a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0]
Program
(i) full_adder
module full_adder (a, b, cin, sum,carry);

input a, b, cin;
output sum, carry;
assign sum=a ^ b^ cin;
assign carry= (a & b)| (b & cin) | (cin & a);
endmodule

VLSI Lab Manual
(ii) 4bit_serial_full_adder
module fa_serial_4bit (a, b, cin, sum, carry);
input [3:0] a,b;
input cin;
output [3:0] sum;
output carry;
wire [3:1] w;
[[
full_adder fa0(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.carry(w[1]));
full_adder fa1(.a(a[1]),.b(b[1]),.cin(w[1]),.sum(sum[1]),.carry(w[2]));
full_adder fa2(.a(a[2]),.b(b[2]),.cin(w[2]),.sum(sum[2]),.carry(w[3]));
full_adderfa3(.a(a[3]),.b(b[3]),.cin(w[3]),.sum(sum[3]),.carry(carry));
endmodule
Test Bench
module fa_serial_4bit_tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum; wire carry;
fa_serial_4bit uu1(a, b, cin, sum, carry);
initial
begin
a=4'b0111; b=4'b0100; cin=1'b0;#10;
a=4'b1011; b=4'b0110; cin=1'b1;
end
initial
$monitor ($time, "a=%b b=%b cin=%b sum=%b carry=%b", a, b, cin, sum, carry);
endmodule
Expected Waveforms:

VLSI Lab Manual
Synthesis Output:
module adder(a, b, cin, sum, carry);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]sum;
output carry;
wire n_0_0_0;
wire n_0_0_1;
wire n_0_0_2;
wire n_0_0_3;
wire n_0_0_4;
wire n_0_0_5;
wire n_0_0_6;
wire n_0_0_7;
wire n_0_0_8;
wire n_0_0_9;
wire n_0_0_10;
wire n_0_0_11;
wire n_0_0_12;
wire n_0_0_13;
wire n_0_0_14;
NOR2_X1 i_0_0_17 (.A1(b[2]), .A2(a[2]), .ZN(n_0_0_12));

OAI21_X1 i_0_0_15 (.A(b[0]), .B1(cin), .B2(a[0]), .ZN(n_0_0_10));
INV_X1 i_0_0_14 (.A(n_0_0_10), .ZN(n_0_0_9));
AOI21_X1 i_0_0_13 (.A(n_0_0_9), .B1(a[0]), .B2(cin), .ZN(n_0_0_8));
NAND2_X1 i_0_0_16 (.A1(b[1]), .A2(a[1]), .ZN(n_0_0_11));
NAND2_X1 i_0_0_12 (.A1(n_0_0_8), .A2(n_0_0_11), .ZN(n_0_0_7));
OAI21_X1 i_0_0_11 (.A(n_0_0_7), .B1(a[1]), .B2(b[1]), .ZN(n_0_0_6));
NAND2_X1 i_0_0_18 (.A1(b[2]), .A2(a[2]), .ZN(n_0_0_13));
AOI21_X1 i_0_0_10 (.A(n_0_0_12), .B1(n_0_0_6), .B2(n_0_0_13), .ZN(n_0_0_5));
XNOR2_X1 i_0_0_1 (.A(b[3]), .B(a[3]), .ZN(n_0_0_0));
OR2_X1 i_0_0_3 (.A1(n_0_0_13), .A2(n_0_0_6), .ZN(n_0_0_1));
AOI22_X1 i_0_0_2 (.A1(n_0_0_5), .A2(n_0_0_1), .B1(n_0_0_12), .B2(n_0_0_6),
.ZN(sum[2]));
XOR2_X1 i_0_0_5 (.A(b[1]), .B(a[1]), .Z(n_0_0_2));
XNOR2_X1 i_0_0_7 (.A(cin), .B(a[0]), .ZN(n_0_0_3));
XNOR2_X1 i_0_0_6 (.A(b[0]), .B(n_0_0_3), .ZN(sum[0]));
NAND2_X1 i_0_0_19 (.A1(b[3]), .A2(a[3]), .ZN(n_0_0_14));
OAI21_X1 i_0_0_9 (.A(n_0_0_5), .B1(a[3]), .B2(b[3]), .ZN(n_0_0_4));
NAND2_X1 i_0_0_8 (.A1(n_0_0_14), .A2(n_0_0_4), .ZN(carry));
Endmodule
Result:

VLSI Lab Manual
EXPERIMENT NO.3
COUNTER DESIGN AND SIMULATION
Asynchronous Counter
Aim: Design an Asynchronous counter in the behavioral modeling styles using Verilog.
Block Diagram
Program
(i) T_Flip Flop
module t_ff (clock, reset, T, q);

input clock, reset, T;
output q;
reg q;
begin
if(reset)
q<=1'b0;
else if (T)
q<=~q;
else
q<=q;
end
endmodule
Dept.of ECE,AMCEC Page 22

VLSI Lab Manual
(ii) 4bit-counter
module asyn_counter (clock, reset, count);

input clock, reset;
output [3:0] count;
t_ff T1(.clock(clock), .reset(reset),.T(1'b1),.q( count[0]));

t_ff T2(.clock(~count[0]), .reset(reset),.T(1'b1),.q(count[1]));
t_ff T3(.clock(~count[1]), .reset(reset),.T(1'b1),.q( count[2]));
t_ff T4(.clock(~count[2]), .reset(reset),.T(1'b1),.q( count[3]));
endmodule
Test Bench
module asyn_counter_tb;
reg clock, reset;
wire [3:0] count;
asyn_counter uut(clock, reset, count);
initial clock=1'b0;
initial
begin
#20; reset=1'b1; #20; reset=1'b0;
end
initial
$monitor( $time, " reset=%b count = %b" ,reset, count);
endmodule
Expected Waveforms

VLSI Lab Manual
Synthesis Output:
module counter(clk, reset, count, SE, SI, SO);
input clk;
input reset;
output [3:0]count;
input SE;
input SI;
output SO;
assign SO = SI;
tff_bbox T1 (.clk(clk), .reset(reset), .T(1'b1), .q(count[0]));

INV_X1 i_0_0_0 (.A(count[0]), .ZN(n_0));
tff_bbox_0 T2 (.clk(n_0), .reset(reset), .T(1'b1), .q(count[1]));
INV_X1 i_0_1_0 (.A(count[1]), .ZN(n_1));
INV_X1 i_0_2_0 (.A(count[2]), .ZN(n_2));
endmodule
Result :

VLSI Lab Manual
EXPERIMENT NO.4
32-Bit ALU DESIGN AND SIMULATION
Aim: Design an 32-Bit ALU in the behavioral modeling styles using Verilog.
Opcode-3bit
Block Diagram
a-32bit
32-Bit ALU
Op-32
b-32bit
Program
module alu (op,a,b,opcode);

output reg[31:0]op;
input [31:0]a,b;
input[3:0]opcode;
always@(*)
begin
case(opcode)
4'b0000:begin op=a+b;
$display("Addition");
end
4'b0001:begin op=a-b;
$display("subtraction");
end
4'b0010:begin op=a*b;
$display("Multiplication");
end
4'b0011:begin op=a/b;
$display("Division");
end
4'b0100:begin op=a%b;
$display("Mod division");
end
VLSI Lab Manual
4'b0101:begin op=a&b;
$display("Bit wise AND");
end
4'b0110:begin op=a|b;
$display("Bit wise OR");
end
4'b0111:begin op=a&&b;
$display("Logical AND");
end
4'b1000:begin op=a^b;
$display("Bitwise XOR");
end
4'b1001:begin op=a||b;
$display("Logical OR");
end
4'b1010:begin op=~a;
$display("Bitwise Inverter");
end
4'b1011:begin op=!a;
$display("Logical Invert");
end
4'b1100:begin op=a>>1;
$display("Right Shift");
end
4'b1101:begin op=a<<1;
$display("Left shift");
end
4'b1110:begin op=a+1;
$display("Increment");
end
4'b1111:begin op=a-1;
$display("Decrement");
end
default:op=32'h00000000;
endcase
end
endmodule

VLSI Lab Manual
Test Bench
module alut_tb;
reg [31:0]a,b;
reg [3:0]opcode;
wire [31:0]op;
alu uut(op,a,b,opcode);
initial
begin
a=32'h98765432;
b=32'h12345689;
opcode=4'b0000;
end
always#50 opcode=opcode+1;
endmodule
Expected Waveforms
Result :

VLSI Lab Manual
EXPERIMENT NO.5
UART DESIGN AND SIMULATION
Aim: Design an URAT in the behavioral modeling styles using Verilog.
Program
RECIVER
module uart_rx #(parameter CLKS_PER_BIT=87)(input i_Clock,input i_Rx_Serial,output

o_Rx_DV,output[7:0]o_Rx_Byte);
parameter s_IDLE=3'b000;
parameter s_RX_START_BIT=3'b001;
parameter s_RX_DATA_BITS=3'b010;
parameter s_RX_STOP_BIT=3'b011;
parameter s_CLEANUP=3'b100;
reg r_Rx_Data_R=1'b1;
reg r_Rx_Data=1'b1;
reg[7:0]r_Clock_Count = 0;
reg[2:0]r_Bit_Index = 0;
reg[7:0]r_Rx_Byte = 0;
reg r_Rx_DV= 0;
reg[2:0] r_SM_Main= 0;
always@(posedge i_Clock)
begin
r_Rx_Data_R<= i_Rx_Serial;
r_Rx_Data<= r_Rx_Data_R;
end
always@(posedge i_Clock)
begin
VLSI Lab Manual
case(r_SM_Main)
s_IDLE:
begin
r_Rx_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if(r_Rx_Data == 1'b0)
r_SM_Main <= s_RX_START_BIT;
else
r_SM_Main <= s_IDLE;
end
s_RX_START_BIT :
begin
if(r_Clock_Count== (CLKS_PER_BIT-1)/2)
begin
if(r_Rx_Data== 1'b0)
begin
r_Clock_Count<= 0;
r_SM_Main<= s_RX_DATA_BITS;
end
else
r_SM_Main<= s_IDLE;
end
else
begin
r_Clock_Count<= r_Clock_Count + 1;
r_SM_Main<= s_RX_START_BIT;
end
end
s_RX_DATA_BITS :
begin
if (r_Clock_Count<CLKS_PER_BIT-1)
begin
r_Clock_Count<=r_Clock_Count + 1;
r_SM_Main<=s_RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_DATA_BITS;

VLSI Lab Manual
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_RX_STOP_BIT;
end
end
end
s_RX_STOP_BIT :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
end
end
s_CLEANUP :
begin
r_Rx_DV <= 1'b0;
end
default :
endcase
end
assign o_Rx_DV = r_Rx_DV;
assign o_Rx_Byte = r_Rx_Byte;
endmodule
TRANSMITTER
module uart_tx #(parameter CLKS_PER_BIT=87)(input i_Clock,input i_Tx_DV,input [7:0] i_Tx_Byte,output

o_Tx_Active,output reg o_Tx_Serial,output o_Tx_Done);
parameter s_IDLE = 3'b000;
parameter s_TX_START_BIT = 3'b001;
parameter s_TX_DATA_BITS = 3'b010;

VLSI Lab Manual
parameter s_TX_STOP_BIT = 3'b011;

parameter s_CLEANUP = 3'b100;
reg[2:0] r_SM_Main = 0;
reg[7:0] r_Clock_Count = 0;
reg[2:0] r_Bit_Index = 0;
reg[7:0] r_Tx_Data = 0;
reg r_Tx_Done = 0;
reg r_Tx_Active = 0;
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
o_Tx_Serial <= 1'b1;// Drive Line High for Idle
r_Tx_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_Tx_DV == 1'b1)
begin
r_Tx_Active <= 1'b1;
r_Tx_Data <= i_Tx_Byte;
r_SM_Main <= s_TX_START_BIT;
end
else
end // case: s_IDLE
// Send out Start Bit. Start bit = 0
s_TX_START_BIT :
begin
o_Tx_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
begin
r_SM_Main <= s_TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= s_TX_DATA_BITS;

VLSI Lab Manual
end
end // case: s_TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
s_TX_DATA_BITS :
begin
o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
begin
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_TX_STOP_BIT;
end
end
end // case: s_TX_DATA_BITS
// Send out Stop bit. Stop bit = 1
s_TX_STOP_BIT :
begin
o_Tx_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
begin
r_SM_Main <= s_TX_STOP_BIT;
end
else
begin
r_Tx_Done <= 1'b1;

VLSI Lab Manual
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
r_Tx_Active <= 1'b0;
end
end // case: s_Tx_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_Tx_Done <= 1'b1;
end
default :
endcase
end
assign o_Tx_Active = r_Tx_Active;
assign o_Tx_Done = r_Tx_Done;
endmodule
Test Bench
module uart_tb ();

// Testbench uses a 10 MHz clock
// Want to interface to 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 100;
parameter c_CLKS_PER_BIT = 87;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_Tx_DV = 0;
wire w_Tx_Done;
reg [7:0] r_Tx_Byte = 0;
reg r_Rx_Serial = 1;
wire v;
wire [7:0] w_Rx_Byte;
// Takes in input byte and serializes it
/*task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
// Send Start Bit
r_Rx_Serial <= 1'b0;
VLSI Lab Manual
#(c_BIT_PERIOD);
#1000;
// Send Data Byte
for (ii=0; ii<8; ii=ii+1)
begin
r_Rx_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
// Send Stop Bit
r_Rx_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask // UART_WRITE_BYTE*/
uart_rx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_INST
(.i_Clock(r_Clock),.i_Rx_Serial(v),.o_Rx_DV(),.o_Rx_Byte(w_Rx_Byte));
uart_tx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_INST
(.i_Clock(r_Clock),.i_Tx_DV(r_Tx_DV),.i_Tx_Byte(r_Tx_Byte),.o_Tx_Active(),.o_Tx_Serial(v),.o_Tx_Done(w_Tx_Do
ne));
always#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
// Main Testing:
initial
begin
// Tell UART to send a command (exercise Tx)
@(posedge r_Clock);
@(posedge r_Clock);
r_Tx_DV <= 1'b1;
r_Tx_Byte <= 8'hAB;
@(posedge r_Clock);
r_Tx_DV <= 1'b0;
@(posedge w_Tx_Done);
// Send a command to the UART (exercise Rx)
//@(posedge r_Clock);
//UART_WRITE_BYTE(8'h3F);
@(posedge r_Clock);
// Check that the correct command was received
if (w_Rx_Byte == 8'hAB)
$display("Test Passed - Correct Byte Received");
else
$display("Test Failed - Incorrect Byte Received");
end
endmodule

VLSI Lab Manual
Expected Waveforms
Result:

VLSI Lab Manual
EXPERIMENT NO.6
BOOTH MULTIPLICATION(RADIX-4) AND SIMULATION
Aim: Design an Booth Multiplication (Radix-4) in the behavioral modeling styles using Verilog
Program
module booth_mul( m,n,reset,clk,result);
input [4:0] m,n;
input reset;
input clk;
output [8:0] result;
reg [8:0] result;
wire [9:0]a,s,p;
wire [4:0]cm;
wire [9:0] p1,p2;
reg [2:0] count;
reg [9:0] reg_p;
reg [9:0] reg_a;
reg [9:0] reg_s;
assign cm= ~m+1;
assign a={m,5'b00000};
assign s={cm,5'b00000};
assign p={4'b0000,n,1'b0};
assign p1=(reg_p+reg_a);
assign p2=(reg_p+reg_s);
always @(posedge clk or posedge reset)
begin
if(reset)
begin
reg_p <=0;
count <=0;
reg_a <= 0;
reg_s <= 0;
result<=0;
end
else if(count == 0)
begin
reg_p <= p;
count <= count + 1;
reg_a <= a;
VLSI Lab Manual
reg_s <= s;
end
else if(count>0 && count<=4)
case (reg_p[1:0])
0:
begin
reg_p <={reg_p[9],reg_p[9:1]};
count <=count+1;
end
1:
begin
reg_p <={p1[9],p1[9:1]};
count <=count+1;
end
2:
begin
reg_p <={p2[9],p2[9:1]};
count<=count+1;
end
3: begin
reg_p <={reg_p[9],reg_p[9:1]};
count <=count+1;
end
default:reg_p<=reg_p;
endcase
else
begin
count <= 0;
result <= reg_p[9]?(reg_p[9:1]-1):reg_p[9:1];
end
end
endmodule

VLSI Lab Manual
Test Bench
module boothmul_test_4bit;
reg [4:0]a,b;
reg clk,reset;
wire [8:0]result;
booth_mul d1(a,b,reset,clk,result);
always
#5 clk=~clk;
initial
begin
clk = 0;
reset = 1;
a =0;
b = 0;
#40 reset=1'b0;
#50 a=5'b01011; b=5'b11101;
#120 a=5'b00100; b=5'b00010;
#120 reset=1'b0;
#120 a=5'b01010; b=5'b00000;
#120 a=5'b01010; b=5'b11010;
#120 a=5'b00110; b=5'b11011;
#100
$stop;
$finish;
end
endmodule

VLSI Lab Manual
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AMC

DEPARTMENT OF ELECTRONICS AND

2018 SCHEME:VLSI LAB MANUAL

(Academic year: 2020-21)

LAB CODE/NAME: 18ECL77/VLSI DESIGN LAB

S. no. Description Page no.

I Vision and Mission statement 5

II PO and PSO statement 6

III CO statement with mapping 7

3. Design a Verilog code for the Apply 2 2,3,5,10 1,2

PROGRAM EDUCATIONAL OBJECTIVES (PEO)

Engineering knowledge: Apply the knowledge of mathematics, science, engineering

Course outcomes Bloom’s

Design stimulate and synthesize the

Design stimulate synthesize using

Design a layout for INV,NAND ,CS

Strength of CO Mapping to PO/PSOs:

CO. PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO

3: Strong, 2: Medium, 1: Weak

Total Marks 100

S.no. Description (IA 2) Marks allotted

Total Marks 100

S. no. Description Marks allotted

1 Observation Note Book 12

3 Average of Two Internal Assessment 16

Total CIE Marks 40

Add generic libraries for schematic design

Create new schematic cell

Inverter wire connection

Create inverter testbench

Add input and output ports

Add vpulse source

Design check inverter Testbench

Inverter testbench simulation general settings

Add generic libraries

• Add technology libraries and click OK

Load T-spice netlist

• Vin cannot be directly connected to poly layer

INVERTER test bench schematic

NAND test bench schematic

Cs amplifier with pmos current mirror schematic

Cs amplifier testbench schematic

• To start QuestaSim GUI in Linux following commandsare use

Create and map library

• Changeto current working directory eg:questa_sample

• ClickSimulate -> Start Simulation

• Clickrst -> Forcegive values1 or 0 and click OK

• Run oasys synthesis script through command – source filepath.tcl

• In the givenexample 4 bit

• Netlist window canbe viewed through clicking Netlist button

• SI-scan input SE-scan

• In Netlist window we canalso seewhich procedural block isused

NOR2_X1 i_0_0_17 (.A1(b[2]), .A2(a[2]), .ZN(n_0_0_12));

(i) SR-Flip Flop

(Behavioral, Data flow or Structural) using Verilog.

Block Diagram Truth Table

module rs_ff(rs, clock,rest q, qb);

Dept. of ECE, AMCEC Page 1

Dept. of ECE, AMCEC Page 2

NOR2_X1 i_1_1_4 (.A1(sr[0]), .A2(n_1), .ZN(n_1_1_1));