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ECEG-3163 Comp Arch Course Outline

This document outlines the course syllabus for ECEG-3163: Computer Architecture and Organization, a 5 credit course offered at Addis Ababa University. The course is divided into 4 parts that cover an overview of computer systems, the central processing unit, the control unit, and memory and I/O technologies. The course objectives are to understand computer system architecture and organization and design a basic computer. Students will be evaluated through continuous assessment of assignments, tests, and a final exam.

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54 views2 pages

ECEG-3163 Comp Arch Course Outline

This document outlines the course syllabus for ECEG-3163: Computer Architecture and Organization, a 5 credit course offered at Addis Ababa University. The course is divided into 4 parts that cover an overview of computer systems, the central processing unit, the control unit, and memory and I/O technologies. The course objectives are to understand computer system architecture and organization and design a basic computer. Students will be evaluated through continuous assessment of assignments, tests, and a final exam.

Uploaded by

Ephraim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Addis Ababa University

Addis Ababa Institute Of Technology


School of Electrical and Computer Engineering
ECEG-3163: Computer Architecture and Organization: 5 (2, 3, 0)
Course Instructors: - Eyoel Getahun & Menore Tekeba
Course Assistants: - Meleake S. , Bruik T. & Dagmawi E.
Course Objectives
 Understanding the architecture and organization of a computer system and its components.
 To design and simulate a basic computer.
Course Outline:
Part I – Overview of Computer Systems [2 Weeks] (chapters 1 - 3 of [1])
1. Introduction
1.1 Organization and Architecture
1.2 Structure and Function
2. Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Performance Assessment
3. A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
Part II - The Central Processing Unit [5.5 Weeks] (chapters 9 - 14 of [1])
4. Computer Arithmetic
4.1 The Arithmetic and Logic Unit (ALU)
4.2 Integer Representation
4.3 Integer Arithmetic
4.4 Floating-Point Representation
4.5 Floating-Point Arithmetic
 Test I covering chapters 1 – 4 , Administered by the end 4th week
5. Instruction Sets and Addressing Modes
5.1 Machine Instruction Characteristics
5.2 Types of Operands
5.3 Types of Operations
5.4 Addressing
5.5 Instruction Formats
5.6 Assembly Language
6. Processor Structure and Organization
6.1 Processor Organization
6.2 Register Organization
6.3 The Instruction Cycle
6.4 Instruction Pipelining
7. Pipelining: Basic and Intermediate Concepts (Appendix A of [2])
7.1 Introduction
7.2 Pipeline Hazards
7.3 Pipeline Implementation
8. Reduced Instruction Set Computer
8.1 Instruction Execution Characteristics

Course Syllabus Page 1 of 2 AAiT, SECE, ECEG 3163


8.2 The Use of a Large Register File
8.3 Compiler-Based Register Optimization
8.4 Reduced Instruction Set Architecture
8.5 RISC Pipelining
8.6 The RISC versus CISC Controversy
Part III – The Control Unit [2 weeks] (chapters 15, 16 of [1])
9. Control Unit Operation
9.1 Micro-operations
9.2 Control of the Processor
9.3 Hardwired Implementation
10. Micro-programmed Control
10.1 Basic Concepts
10.2 Microinstruction Sequencing
10.3 Microinstruction Execution
 Test II covering chapters 5 – 10, Administered by the end 10th week
Part IV Memory and I/O Technologies [3.5 Weeks] (chapters 4 -7 of [1])
11. Cache Memory
11.1 Computer Memory System Overview
11.2 Cache Memory Principles
11.3 Elements of Cache Design
12. Internal Memory
12.1 Semiconductor Main Memory
12.2 Error Correction
12.3 Advanced DRAM Organization
13. External Memory
13.1 Magnetic Disk
13.2 RAID
13.3 Optical Memory
13.4 Magnetic Tape
14. Input/output
14.1 External Devices
14.2 I/O Modules
14.3 Programmed I/O
14.4 Interrupt-Driven I/O
14.5 Direct Memory Access
14.6 I/O Channels and Processors

Prerequisite: Digital Logic Design


Evaluation System: Continuous Assessment
Assignments and Tests (50 %),
Final exam (50%)

Textbook:
[1] William Stallings: Prentice Hall 2010, Computer Organization and Architecture 8th Edition
References:
[2] David A Patterson: John L. Hennessy: Computer Architecture A Quantitative Approach 4th Edition
[3] M. M. Mano: Computer System Architecture
[4] Barry Wilkinson: Computer Architecture Design and Performance
Teaching & Learning Methods: Lectures supported by tutorials.

Attendance Requirements: 75%lecture attendance

Course Syllabus Page 2 of 2 AAiT, SECE, ECEG 3163

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