3CS3-04:

DIGITAL ELECTRONICS

UNIT – 3
Digital Logic Gate
Characteristics
 Digital Logic Gate Characteristics
TTL Logic Gate Characteristics
Theory & Operation of TTL NAND Gate
Circuitry
Open Collector TTL
Three State Output Logic
TTL Subfamilies
MOS & CMOS Logic Families
Realization of Logic Gates in RTL, DTL, ECL,
CMOS & MOSFET
 Characteristics Of Digital ICs
There are various logic families and the
selections of the family for a particular
application based on its characteristics.
Real time application demand high speed logic
families and hence it is necessary to study the
characteristics of digital ICs.

Digital IC technology has advanced rapidly

from integrations which can 1 million or more
gates.
 Characteristics Of Digital ICs
ICs pack more circuitry in a small package, so
overall size of almost any system is reduced.
– Cost is reduced because of the economies of
mass-producing large volumes of similar devices.

ICs have made digital systems more reliable

by reducing the number of external
interconnections from one device to another.
– Protected from poor soldering, breaks or shorts
in connecting paths on a circuit board, and other
physical problems.
 Characteristics Of Digital ICs
 ICs cannot handle very large currents or voltage.
– Heat generated in such small spaces would cause
temperatures to rise beyond acceptable limits.
– For higher power levels, an interfacing circuit will be
needed—typically of components or special power
ICs.

 ICs can’t easily implement certain devices such

as inductors, transformers, and large capacitors.
– Principally used to perform low-power circuit
operations.
 Various logic families differ in major components
in their circuitry.
– TTL and ECL use bipolar transistors as their
major circuit element.

– PMOS, NMOS, and CMOS use unipolar

MOSFET transistors.
 Characteristics Of Digital ICs
The parameters used to compare the
performance of digital ICs are shown below:
 Speed of Operation
 Power Dissipation
 Figure of merit
 Fan-out
 Fan-in
 Current and Voltage Parameters
 Noise Immunity
 Power Supply Requirement
 Operating Temperature
Resistor–Transistor logic (RTL)
Resistor–transistor logic (RTL) (sometimes
also transistor–resistor logic (TRL)) is a class
of digital circuits built using resistors as the
input network and bipolar junction
transistors (BJTs) as switching devices.

RTL is the earliest class of transistorized

digital logic circuit used.
Resistor–Transistor logic (RTL)
Resistor-Transistor Logic, or RTL, refers to the
obsolete technology for designing and
fabricating digital circuits that employ logic
gates consisting of nothing but transistors and
resistors.

RTL gates are now seldom used, if at all, in

modern digital electronics design because it
has several drawbacks, such as bulkiness, low
speed, limited fan-out, and poor noise margin.
Resistor–Transistor logic (RTL)
A basic understanding of what RTL is,
however, would be helpful to any engineer
who wishes to get familiarized with TTL,
which for the past many years has become
widely used in digital devices such as logic
gates, latches, buffers, counters, and the like.
A simple N-input RTL NOR Gate
 N-input RTL NOR Gate
 Figure given below shows an example of an N-input
RTL NOR gate.
 It consists of N transistors, whose collectors are all tied
up to Vcc through a common resistor, and whose
emitters are all grounded.
 Their bases individually act as inputs for input voltages
Vi (i = 1,2,...,N), which represent input logic levels.
 The output Vo is taken across the collector- resistor
node and ground.
 Vo is only 'high' if the inputs to the bases of all the
transistors are 'low'.
2-Input RTL NOR Gate
 Operation of 2-Input RTL NOR Gate
 Inputs to the NOR gate shown above are ‘input1’
& ‘input2’.
 The inputs applied at these terminals represent
either logic level HIGH (1) or LOW (0).
 The logic level LOW is the voltage that drives
corresponding transistor in cut-off region, while
logic level HIGH drives it into saturation region.
 If both the inputs are LOW, then both the
transistors are in cut-off i.e. they are turned-off.
Thus, voltage Vcc appears at output I.e. HIGH.
 If either transistor or both of them are applied
HIGH input, the voltage Vcc drops across Rc and
output is LOW.
 Operation Table of 2 input RTL

Input 1 Input 2 T1 T2 Output

Logic 0 Logic 0 Cutoff Cutoff Logic 1

Logic 0 Logic 1 Cutoff Saturation Logic 0

Logic 1 Logic 0 Saturation Cutoff Logic 0

Logic 1 Logic 1 Saturation Saturation Logic 0

 Diode-Transistor Logic (DTL)
Diode-Transistor Logic, or DTL, refers to the
technology for designing and fabricating
digital circuits wherein logic gates employ
both diodes and transistors.

DTL offers better noise margins and greater

fan-outs than RTL, but suffers from low speed,
especially in comparison to TTL.
 Diode-Transistor Logic (DTL)
RTL allows the construction of NOR gates
easily, but NAND gates are relatively more
difficult to get from RTL.

DTL, however, allows the construction of

simple NAND gates from a single transistor,
with the help of several diodes and resistors.
A simple 3-input DTL NAND Gate
 3-input DTL NAND Gate
Figure shows an example of an 3-input DTL
NAND gate.

It consists of a single transistor Q configured

as an inverter, which is driven by a current that
depends on the inputs to the three input diodes
D1-D3.
 3-input DTL NAND Gate
 In the NAND gate in Figure, the current through
diodes DA and DB will only be large enough to
drive the transistor into saturation and bring the
output voltage Vo to logic '0' if all the input
diodes D1-D3 are 'off', which is true when the
inputs to all of them are logic '1'.

 This is because when D1-D3 are not conducting,

all the current from Vcc through R will go
through DA and DB and into the base of the
transistor, turning it on and pulling Vo to near
ground.
 3-input DTL NAND Gate
 However, if any of the diodes D1-D3 gets an
input voltage of logic '0', it gets forward-biased
and starts conducting.

 This conducting diode 'shunts' almost all the

current away from the reverse-biased DA and DB,
limiting the transistor base current.

 This forces the transistor to turn off, bringing up

the output voltage Vo to logic '1'.
3 Input NAND Gate Truth Table
Input 1 Input 2 Input 3 Output
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
 TTL Families
 RTL(Resistor Transistor Logic)
 DTL(Diode Transistor Logic)
 TTL(Transistor-Transistor Logic)
1. TTL Passive Pull Up
2. TTL Open Collector
3. TTL Totem Pole (Active Pull Up)
 ECL(Emitter Coupled Logic)
 CMOS(Complementary Metal Oxide
Semiconductor Logic)
 TTL (Transistor Transistor Logic)
NAND gate with Totem Pole Output
 Operation Table of NAND gate with
Totem Pole Output
Input T1 T2 & T3 T4 Output

A B Emitter Emitter B
A
Logic 0 Logic 0 FB FB Cutoff Saturati Logic 1
on
Logic 0 Logic 1 FB RB Cutoff Saturati Logic 1
on
Logic 1 Logic 0 RB FB Cutoff Saturati Logic 1
on
Logic 1 Logic 1 RB RB Saturatio Cutoff Logic 0
n
Active Pull Up
TTL Passive Pull UP
 Operation Table of NAND gate with
Passive Pull Up
Input Q1 Q2 Q3 Output

A B Emitter A Emitter B

Logic 0 Logic 0 FB FB Cutoff Cutoff Logic 1

Logic 0 Logic 1 FB RB Cutoff Cutoff Logic 1

Logic 1 Logic 0 RB FB Cutoff Cutoff Logic 1

Logic 1 Logic 1 RB RB Saturati Saturati Logic 0

on on
TTL Open Collector

R1 R2

R3
 Operation Table of TTL Open
Collector
Input T1 T2 T3 Output

A B Emitter A Emitter B

Logic 0 Logic 0 FB FB Cutoff Cutoff Logic 1

Logic 0 Logic 1 FB RB Cutoff Cutoff Logic 1

Logic 1 Logic 0 RB FB Cutoff Cutoff Logic 1

Logic 1 Logic 1 RB RB Saturati Saturati Logic 0

on on
 Tristate Output Device
 Tri-state output (three-state output) An electronic
output stage consisting of a logic gate, commonly
an inverter or buffer, that exhibits three possible
logic states, namely logic 1, logic 0, and an
inactive (high-impedance or open-circuit) state.

 A tri-state buffer is a logic inverter or a non-

inverting buffer with a tri-state output stage.

 The four possible configurations are shown in

Figure in next slide and the truth table for the type
in Figure is also shown in next slide.
Figure: Tri-state buffers
(a) Inverting, active high enable with truth table
(b) Non-inverting, active high enable
(c) Inverting, active low enable
(d) Non-inverting, active low enable
Tri State Device
 Tristate Output Device
 The input denoted E can be regarded as an enable line, which may
require either an active low or active high input signal, and when
activated it will allow the gate to output either the true or inverted
data.

 When the enable line is not activated the buffer output stage has a
high output impedance and transmission of data is prevented.

 An active high enable input is also sometimes referred to as the

Chip-Select input, or CS (mainly in the case of VLSI chips having
this input).

 In the case of gates or chips where the Enable input is active low, it
is sometimes referred to as an Inhibit input, I, as, when taken high, it
inhibits the gate operation.
 TTL Subfamilies
 The speed-power product is an important parameter for
comparing the basic gates.
 It is defined as the product of propagation delay and power
dissipation measured in picojoules (pJ).
 Value of this parameter indicates that, a given propagation
delay can be achieved without excessive power dissipation.
 This product is also referred to as figure of merit for the logic
family.
 Depending upon the value of figure of merit, a minor
variation in the standard TTL family is implemented using
components with either a less power dissipation or a high
speed.
 TTL Subfamilies
Standard TTL
Low Power TTL(L TTL)
High Speed TTL(H TTL)
Schottky TTL(S TTL)
Low Power Schottky TTL(LS TTL)
 Standard TTL
The standard TTL was the first gate in TTL
family.
The gate was constructed using different
resistor values to produce gates with lower
dissipation or high speed.
The propagation delay of a saturated logic
family depends largely on two factors: storage
time and RC time constants.
Reducing storage time reduces the RC time
constant and decreases the propagation delay.
 Low Power TTL(L TTL)
The low power TTL gate has resistor
values higher than those in standard TTL
so as to reduce power dissipation and
increased propagation delay.
 High Speed TTL(H TTL)
In high speed TTL the resistor values are
lowered to reduce the propagation delay
but power dissipation is increased.
 Schottky TTL(S TTL)
 The schottky TTL removes the storage time of transistors by
preventing them from going into saturation.
 In this way, the speed of operation increases without excessive
increase in power dissipation from Schottky TTL.
 Basic TTL family has a speed limitation due to turn off delays of
transistors which are caused by transition from saturation to cutoff.
This limitation can be removed by replacing the transistors of TTL
gate by Schottky transistors.
 These transistors are prevented from entering the saturation and
hence there is saving in turn-off time. The propagation delay of
shottky TTL is of the order of 2 ns.
 In comparison, the propagation delay for standard TTL is 10 ns.
 The Schottky TTL therefore is a non- saturating bipolar logic.
 Low Power Schottky TTL(LS
TTL)
The low power schottky TTL sacrifices speed
for a reduced power dissipation.

It has the same propagation delay as standard

TTL, but the power dissipation is reduced to a
1/5th that of standard TTL.

It is the most popular version of in new digital

circuit system design
 TTL subfamilies
TTL versions are available in SSI, MSI and
LSI packages.
As mentioned earlier, the TTL versions do not
vary functionally; they vary in terms of the
values of resistors used and the type of
transistors that the basic gate uses.
These subfamilies are compared on the basis
of figure merit as shown in the Table in next
slide.
 Comparison of TTL subfamilies
Name Power Abbreviation Propagation Dissipation Figure of
delay (ns) (mW) merit Speed
power
product (PJ)

Standard TTL TTL 10 10 100

Low power L TTL 33 1 33
TTL

High speed H TTL 9 22 132

TTL

Schottky TTL S TTL 3 19 57

Low power LS TTL 9.5 2 19
schottky TTL
 Characteristics of TTL Family
 TTL 5400/7400 series is the most popular and
commonly used series in digital ICs.
 7400 devices are used for commercial applications
whereas, the 5400 devices are used for military
applications.
 The only difference in two series is in the temperature
range and power supply range.
 The temperature range for 7400 series is 0o C to 70o C,
and that for 5400 series is -55o C to 125o C.
 The supply voltage range is 5±0.25V for 7400 and is
5±0.5V for 5400 series. There are five categories of
TTL ICs.
 TTL subfamilies

Name Power Prefix Example

Standard TTL 74- 7402,74193

High power TTL 74H- 74H02, 74H193
Low power TTL 74L- 74L02, 74L193
Schottky TTL 74S- 74S02,74S193
Low power 74LS- 74LS02,74LS193
schottky TTL
ECL (Emitter - Coupled Logic)
OR/NOR Gate
ECL (Emitter - Coupled Logic)
OR/NOR Gate
 ECL (Emitter - Coupled Logic)
OR/NOR Gate
Input Transistor Transistor Output

A B T’1 T1 T2 T3 T4 Y1 Y2

Logic 0 Logic 0 Cutoff Cutoff Active Cutoff Active Logic 0 Logic 1

Logic 0 Logic 1 Cutoff Active Cutoff Active Cutoff Logic 1 Logic 0

Logic 1 Logic 0 Active Cutoff Cutoff Active Cutoff Logic 1 Logic 0

Logic 1 Logic 1 Active Active Cutoff Active Cutoff Logic 1 Logic 0

MOSFET
MOSFET
CMOS NAND Gate
Operation Table of CMOS NAND
Gate
A B Q1 Q2 Q3 Q4 Op

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 1

1 0 OFF ON ON OFF 1

1 1 OFF OFF ON ON 0
CMOS NAND Gate
Operation of CMOS NAND Gate
CMOS NOR GATE
 Operation of NOR Gate
A B Q1 Q2 Q3 Q4 O/P

0 0 ON ON OFF OFF 1

0 1 ON OFF ON OFF 0

1 0 OFF ON OFF ON 0

1 1 OFF OFF ON ON 0
CMOS Inverter

Q1

Q2
 Operation of CMOS Inverter

Input Q1 Q2 Output

0 ON OFF 1

1 OFF ON 0
Thank You