1988 Intel Embedded Controller Handbook Volume I 8-Bit
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Gokul S1988 Intel Embedded Controller Handbook Volume I 8-Bit
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Gokul Sinter
Intel the Microcomputer Company:
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microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
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EMBEDDED CONTROLLER
HANDBOOK
1988
Intel Corporation makes .no warranty. for .the use of its products and assumes no responsibility for any errors
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Table of Contents
Alphanumeric Index .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
8·BIT PRODUCTS
MCS®·48 FAMILY
Chapter 1
MCS®-48 Single Component System ........................................ 1-1
Chapter 2
MCS®-48 Expanded System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Chapter 3
MCS®-48 Instruction Set.. . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . 3-1
Chapter 4
DATA SHEETS
8243 MCS®~48InputlOutput Expander. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 4-1
P87 48H/P87 49H/8048AH/8035AH L/8049AH/8039AHLl8050AH/8040AHL
HMOS Single-Component 8-Bit Production Microcontroller ........ . . . . . . . . . . . 4-8
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . .. . .. . . . . . 4-21
MCS®-48 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MCS®-48 INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
MCS®·51 FAMILY
Chapter 5
MCS®-51 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . .. . .. . .. . . . . . 5-1
Chapter 6
Hardware Description of the 8051,8052 and 80C51 ........................... 6-1
Chapter 7
Hardware Description of the 83C51 FA (83C252) ............................. ; 7-1
Chapter 8
Hardware Description of the 83C152 .................................. ; . . . . . . 8-1
Chapter 9
MCS®-51 Programmer's Guide and Instruction Set. .. . . . . .. . . . .. . . . . . . . . . . . . . . 9-1.
Chapter 10
DATA SHEETS
8031/8051 /8031AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS
and HMOS EPROM Microcontrollers....................................... 10-1
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM .. . . . . . . . . .. 10-15
8031 AH/8051AH/8032AH/8052AH/8751 H/8751 H~8 Express. . . . . . . . . . .. . . .. .. 10-25
8751 BH 8-Bit HMOS EPROM Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-27
8032BH/8052BH 8-Bit HMOS Microcontrollers .............................. ; 10-38
8752BH 8-Bit HMOS EPROM Microcontroller................................. 10-46
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers ........................... 10-57
80C31 BH/80C51 BH Express ................. : ............................. 10-69
87C51 8-Bit CHMOS EPROM Microcontroller................................. 10-71
87C51 Express ........................................................... 10-84
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller . . . . . . . . . . . . . . . . . •. 10-87
83C152A180C152A Universal Communications Controller ....... '............ ; .. 10-102
80C152JAl83C152JAl80C152JB Universal Communications Controller ......... 10-117
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ........ 10-133
87C257 256K'(32K x 8) CHMOS UV Erasable PROM .......................... 10-146
UPITM-452 CHMOS Programmable I/O Processor ............................. 10-157
APPLICATION NOTES
AP-70 Using the Intel MCS®-51 Boolean Processing Capabilities ................ 10-211
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments .... 10-256
AP-155 Oscillators for Microcontrollers ....................................... 10-278
v
Table of Contents (Continued)
AP-252 Designing with the 80C51 BH ........................................ 10-310
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........•............ 10-334
ARTICLE REPRINTS
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable
Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-354
AR-517 Using the 8051 Microcontroller with Resonant Transducers ............. 10-359
DEVELOPMENT SUPPORT TOOLS
8051 Software Packages. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . . . . 10-364
iDCX 51 Distributed Control Executive ....................................... 10-372
ICETM 5100/252 In-Circuit Emulator for the MCS@-51 Family ................... 10-380
MCS@-51 INDEX ................................................... ; ........ 10-390
80C152 INDEX .................................•............................ 10-392
THE RUPITM FAMILY
Chapter 11
The RUPITM-44 Family..................................................... 11-1
Chapter 12
8044 Architecture ........................................... , . . . . . . . . . . . . . 12-1
Chapter 13
8044 Serial Interface ...................................................... 13-1
Chapter 14
8044 Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Chapter 15
DATA SHEET
8044AH/8344AH/8744H High Performance 8-Bit Microcontrollerwith On-Chip
Serial Communication Controller.......................................... 15-1
APPLICATION NOTE
AP-283 Flexibility in Frame Size with the 8044. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-27
ARTICLE REPRINT
AR-307 Microcontroller with Integrated High Performance Communications
Interface .........................'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-57
DEVELOPMENT SUPPORT TOOLS .
ICETM51 00/044 In-Circuit Emulator for the RUPITM-44 Family. . . . . . . . . . . . . . . . . .. 15-66
MCS®-80/85 FAMILY
. Chapter 16
DATA SHEETS
8080A/8080A-1 /80BOA-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . .. . . . . . . . 16-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . .. 16-11
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and
Timer. .. . . . . .. .. .. . . . .. . . .. .. . .. . . . . .. . . . .. . . . . . .. . . . .• . . . . . . . . . . .. .... 16-31
8185/8185-21024 x 8-Bit Static RAM for MCS@-85. ... . .. . . . .. . . . . .•. .. . .. .... 16-45
8224 Clock Generator and Driver for 8080A CPU ........... ~ ............. '. . . .. 16-50
8228 System Controller and Bus Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . .. 16-55
8755A 16,384-Bit EPROM with I/O.......................................... 16-59
16-BIT PRODUCTS
MCS®-96 FAMILY
Chapter 17
MCS@-96 Architectural Overview. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
Chapter 18 ,
MCS@-96InstructionSet................................................... 18-1
Chapter 19
MCS@-96 Hardware Design Information. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 19-1
vi
Table of Contents (Continued)
Chapter 20
80C196KA Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
Chapter 21
DATA SHEETS
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus....................... 21-1
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus . . . . . . .. 21-44
809X-90, 839X-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . .. 21-59
809XBH/839XBH/879XBH Express......................................... 21-78
809X-90, 839X-90 Express. . . . . . . . . . . . . . . . . . . .. . . .. .. .. . ... . . . . . . . . . . . . . . .. 21-87
80C196KA 16-Bit High Performance.CHMOS Microcontroller ................... 21-92
APPLICATION NOTES .
AP-248 Using the 8096 .................................................... 21-119
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines
and Examples· .......................................................... 21-222
DEVELOPMENT SUPPORT TOOLS
MCS®-96 Software Development Packages .................................. 21-297
iDCX 96 Distributed Control Executive ....................................... 21-307
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 .... 21-315
VLSICETM-96 In-Circuit Emulator for the MCS®-96 ............................. 21-323
ICETM-196 Real-Time Transparent 80C196 In-Circuit Emulator .................. 21-333
!'v1CS®-96 INDEX ............................................................ 21-335
80C196 INDEX ............................................................... 21-341
80186 FAMILY
Chapter 22
DATA SHEETS
80186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
80C186 High Integration 16TBit Microprocessor . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. 22-53
80188 High Integration 16-Bit Microprocessor ................................. 22-111
80C188 High Integration 16-Bit Microprocessor ............................... 22-165
82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors ....... 22-225
APPLICATION NOTES
AP-186 Introduction to the 80186 Microprocessor ............................. 22-241
AP-258 High Speed Numerics with the 80186,80188 and 8087 ................. 22-316
AP-286 80186/188 Interface to Intel Microcontrollers .......................... 22-332
DEVELOPMENT SUPPORT TOOLS
8086/80186 Software Packages ............................................ 22-362
VAXIVMS Resident 8086/8088/80186 Software Development Packages ........ 22-383
8087 Support Library ...................................................... 22-391
80287 Support Library ..................................................... 22-395
iPAT Performance Analysis Tool ............................................ 22-399
12 1CETM Integrated Instrumentation and In-Circuit Emulation System ............. 22-412
ICETM-186 In-Circuit Emulator .............................................. 22-424
vii
Alphanumeric Index
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ............... 10-133
80C152JAl83C152JAl80C152JB Universal Communications Controller ............ , ... 10-117
80C186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22-53
80C188 High Integration 16-Bit Microprocessor ...................................... 22-165
80C196KA Architectural Overview ................................................. 20-1
80C196KA 16-Bit High Performance CHMOS MiGrocontrolier . . . . . . . . . . . . . . . . . . . . . . . . .. 21-92
80C31 BH/80C51 BH Express ...................................................... 10-69
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 10-57
80186 High Integration 16-Bit Microprocessor....................................... 22-1
80188 High Integration 16-Bit Microprocessor ....................................... 22-111
80287 Support Library ..................... '....................................... 22-395
8031/8051 /8031AH/8051AH/S032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS and HMOS
EPROM Microcontrollers ...................................... '. . . . . . . .. . . . . . . . . . 1O~ 1
8031 AH/8051 AH/8032AH/8052AH/8751 H/8751 H-8 Express .... . . . . . . . . . . . . . . . . . . .. 10-25
8032BH/8052BH 8-Bit HMOS Microcontrollers ....................... : . . . . . . . . . . . . .. 10-38
8044 Application Examples ...................................... ,................ 14-1
8044 Architecture. ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
8044 Serial Interface ............................ ~ . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
8044AH/8344AH/8744H High Performance 8-Bit Microcontroller with On-Chip Serial
Communication Controller ...................................................... 15-1
8051 Software Packages ............ '............................................. 10-364
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM. . . . . . . . . . . . . . . . . .. 10-15
8080Al8080A-1 /8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 16-11
8086/80186 Software Packages .................................................. ; 22-362
8087 Support Library ................... '.......................................... 22-391
809X-90, 839X-90 ...................................... ;........................ 21-59
809X-90, 839X-90 Express ...... : ...... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21-87
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus. . . . . . . .. . . . ... 21-44
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus.............................. 21-1
809XBH/839XBH/879XBH Express ................................................ 21-78
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer.. 16-31
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ........ . . . . . . . . . . . . . . . . . . . . . . . . .. 16-45
82188 Integrated Bus Controller for 8086,8088,80186,80188 Processors .............. 22-225
8224 Clock Generator and Driver for 8080A CPU. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ... 16-50
8228 System Controller and Bus Driver for 8080A CPU ............................... 16-55
8243 MCS®-48 Input/Output Expander. .. . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 4-1
83C152A180C152A Universal Communications Controller ............................ 10-102
87C257 256K (32K x 8) CHMOS UV Erasable PROM ................................. 10-146
87C51 Express .. ; .....................................................'. . ..... . . . .. 10-84
87C51 8-Bit CHMOS EPROM Microcontroller ..................................... ,.. 10-71
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller ......................... 10-87
8751 BH 8-Bit HMOS EPROM Microc~mtroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-27
8752BH 8-Bit HMOS EPROM Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-46
8755A 16,384-Bit EPROM with I/O. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-59
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines and
Examples ...................... -......' ................................ '......... 21-222
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments .......... 10-256
AP-155 Oscillators for Microcontrollers .......................................... , .. 10-278
AP-186 Introduction to the 80186 Microprocessor ................................... 22-241
AP-248 Using the 8096 ........................................................... 21-119
AP-252 Designing with the 80C51 BH ............................................... 10-310
AP-258 High Speed Numerics with the 80186, 80188 and 8087 ........................ 22-316
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........................... 10-334
viii
Alphanumeric Index (Continued)
AP-283 Flexibility in Frame Size with the 8044 ....................................... 15-27
AP-286 80186/188 Interface to Intel Microcontrollers ................................. 22-332
AP-70 Using the Intel MCS®"51 Boolean Processing Capabilities ....................... 10-211
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable Computer .... 10-354
AR-307 Microcontroller with Integrated High Performance Communications Interface. . . .. 15-57
AR-517 Using the 8051 Microcontroller with Resonant Transducers .................... 10-359
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . . . . . . . . . . . . . . . . . 4-21
Hardware Description of the 8051, 8052 and 80C51 .................................. 6-1
Hardware Description of the 83C152 ............................................... 8-1
Hardware Description of the 83C51 FA (83C252) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 7-1
12 1CETM Integrated Instrumentation and In-Circuit Emulation System .................... 22-412
iDCX 51 Distributed Control Executive .............................................. 10-372
iDCX 96 Distributed Control Executive .............................................. 21-307
iPAT Performance Analysis Tool ................................................... 22-399
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 ........... 21-315
ICETM 5100/252 In-Circuit Emulator for the MCS®-51 Family .......................... 10-380
ICETM-186 In-Circuit Emulator ..................................................... 22-424
ICErM-196 Real-Time Transparent 80C196 In-Circuit Emulator ......................... 21-333
ICETM51 001044 In-Circuit Emulator for the RUPITM-44 Family ......................... 15-66
MCS®-48 Expanded System ...................................................... 2-1
MCS®-48 Express ........................ , ..... ,., .. , ........ , ............. ,..... 4-33
MCS®-48 Instruction Set",·,',.".,"", .. " .. " .. ,',.,",." .. ,',.".,.,',., ... ,. 3-1
MCS®-48 Single Component System .. , ........ , .. , .. , . , ... , ..... , , . , .. , , . . . . . . . . . . 1-1
MCS®-51 Architectural Overview"" ... " .. " .. ,' .. ",.,", ...... ,"',.,." .. ,..... 5-1
MCS®-96 Architectural Overview ., .. , ... " .. , .. , .... ,., .. "." .. " ... ,., .. "...... 17-1
MCS®-96 Hardware Design Information",.", .. ,"",., ..... ".,", .. ".,., ... , •. ,' 19-1
MCS®-96 Instruction Set. .... , ... ,.,.............................................. 18-1
MCS®-96 Software Development Packages, .... , ... , .... , ... , ... , ............ , ..... 21-297
P8748H/P87 49H/8048AH/8035AHL/8049AH/8039AHLl8050AH/8040AHL HMOS
Single-Component 8-Bit Production Microcontroller ,."', ... , ....... , ... ,, ...... ,.. 4-8
The RUPITM-44 Family , .... , .. " ... ,.,"""""',.,',.,.,',.,"',.,', .. ".,"'" 11-1
UPITM-452 CHMOS Programmable I/O Processor .. , ......... , .. , , •.. , ... , ........ , .. 10-157
VAXIVMS Resident 8086/8088/80186 Software Development Packages, ........... , , . 22-383
VLSICETM-96 In-Circuit Emulator for the MCS®-96 " " " " " , .. , , .. , . , , , . , . , ..... , ... 21-323
ix
CUSTOMER SUPPORT
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x
Preface
PREFACE
Computer systems can be characterized as being. "re- data storage onboard. The maximum program size is
programmable" or "embedded". Reprogrammable sys- 4 Kbytes. .
tems are those that look and behave like computers to
the ultimate user. An obvious example is the personal MCS@-51: Designed for advanced 8-bit sequential con-
computer. These systems contain some form of mass trol applications. These parts are similar to the
storage device which stores a number o( different com- MCS@-48 family parts but operate from 2 to 5 times
puter programs that the user may call up and use as faster and include more on-board peripherals. A unique
required. The input and output devices attached to feature of the MCS@-51 family is a built in Boolean
these systems are there to communicate with the user. processor which performs calculations on Boolean (one
Embedded systems, as the name implies, are contained bit) variables. The maximum program size is
within a final product which inay not look or feel like a 64 Kbytes. .
computer to the end user. An example here is a com-
puter which controls the ubiquitous office copier ma- MCS@-96: Designed for advanced 16-bit closed loop
chine. These systems rarely contain mass storage; the control applications. These parts include a processor
programs are stored in ROM or EPROM devices. The capable of high performance integer arithmetic and 232
input and output devices attached are not limited to bytes of general purpose registers which can be used for
communication with the user (e.g. the control panel); byte, word, or double-word operands. A separate sub-
they also monitor and control mechanisms and process- system manages timer functions. Versions are available
es within the device (e.g. the paper feed mechanism). with on-board A/D conversion and 8 Kbytes of on-
board program memory. A unique feature of the newer
Embedded control applications can be broken into (BH) members of the family is dynamic bus sizing
three broad categories; sequential control, closed loop which allows the parts to operate on both 8-bit and 16-
control, and data control. Sequential control deals with bit busses. The maximum program size is 64 Kbytes.
the control and monitoring of a system as a sequence of
events; activate the paper feed roller, wait for the paper 80186/80188: These parts are highly integrated ver-
feed indicator then activate the drum mechanism. sions of the 8086 microprocessor intended for data con-
Closed loop control involves closely monitoring the trol applications. They combine 15 to 20 of the most
output of process or device and altering its inputs to common 8086.system components onto one device. In-
achieve the desired output; if the feed roller motor is cluded with the CPU is the clock generator, an inter-
turning too slowly or is decelerating then increase the rupt controller; timers, DMA channels and chip. select
drive to the motor to compensate. These two categories logic. The 80186 operates on a 16-bit bus and the 80188
involve fixed programs that interface directly with the operates on an 8-bit bus. Both parts operate on a 16-bit
,outside world. The data structures involved are normal- bus internally. . .
ly small and simple. The third category of embedded
control (data control) still runs fixed programs but the Part of the motivation for combining all of these prod-
interface to the outside word becomes more indirect ucts into one handbook was the realization that,
and the data structures become larger and more com- although the categorization of embedded control appli-
plex. A high end copier might digitize an image and cations into the three segments (sequential, closed loop,
then use image processing techniques to enhance con- and data control) is useful for conceptualizing applica-
trast and then scale and rotate the image to fit the pa- tion requirements, real applications of these parts
per being used. contain attributes from all three categories. Combining
these product lines into one handbook will make it easi-
Intel has consolidated four of its product families in- er for customers involved with embedded applications
tended for embedded control applications into the Em- to find the information they require.
bedded Control Operation.
The remainder of this chapter will give a very brief
MCS@-48: Designed for general purpose 8-bit sequen- overview of each of the four products discussed. The
tial control applications. Versions of these parts are remainder of this book is intended to provide detailed
available with program storage and up to 256 bytes of technical information on Intel's embedded control
product line.
xiii
intJ PREFACE
MCS®-48 MICROCONTROLLERS MCS®-S1 MICROCONTROLLERS
Intel's MCS-48 family of 8-bit microcontrollers has be- Intel's MCS-5l family is the Industry standard for 8-bit
come a world standard and has been in production for high performancemicrocontrollers. The -family archi-
10 years. They are available in several versions: with on tecture is optimized for sequential real-time control ap-
board ROM, on board EPROM, or CPU only, to better plications. They are available in several versions -with
fit specific application needs. MCS-48 products are now on-board ROM, on-board EPROM, l!lld CPU only to
fabricated. on advanced HMOS processes offering high- better -fit specific application needs. MCS-51- products
er performance and reliability with less power con- are available on adv~riced HMOS and CHMOS pro-
sumption. cesses.
Features common to all members of this family are: Features common to all members of this family are:
• 8-bit CPU with 1.36 microsecond instruction cycle • 8-bit CPU optimized for control applications
• 27 I/O lines • ,Extensive Boolean processing (single-bit logic) capa-
• 8-bit bit timer/counter bilities
• 2 interrupts • 32 bidirectional and individually addressable I/O
lines -
• 4 Kbyte maximum program size
• Fuil-Duplex UART
• 256 byte maximum on-board RAM size
• 5 source interrupt structure with 2 priority levels (6
• 256 -byte maximum off-board RAM size sources on parts with 3 timer/counters)
Intel has over ten years of experience in manufacturing • 64 Kbyte maximum program size
both the EPROM and ROM versions of this chip. It • 256 byte maximum on-board RAM size
provides a low cost solution to applications such as key- • 64 Kbyte maximum off-board RAM size
boards, low end printers, and electronic carburator con-
trol. • Po~er gown/Idle modes forCHMOS parts
Table 1. MCS®·48 Microcontrollers
Device ROMless EPROM ROM RAM
Name Version Version Bytes Bytes
8048AH 8035AHL 8748H 1K _64
8049AH 8039AHL 8749H 2K 128
8050AH 8040AHL - 4K 256
270253-1
Figure 1. MCS®·48 Block Diagram
xiv
inter PREFACE
The MCS-51 family has found wide acceptance capability. The 80C51FA contains, in addition to the
throughout a wide range of applications, ranging from standard timer counters, a programmable counter array
those slightly more complex than a typical MCS-48 ap- (PCA) capable of measuring and generating pulse infor-
plication through medical instrumentation and anti- mation on five I/O pins.
skid braking modules for automobiles.
This year Intel added two new base products to the MSC®-51 FAMILY DEVELOPMENT
MCS-51 family, the 80C152 and the 80C51FA. The TOOLS
80C152 contains, in addition to a UART, a Global
Serial Channel capable of CSMA/CD and SDLC syn- ICETM-5100 emulators give design engineers full-
chronous communication. It also has two DMA chan- speed, real-time, nonintrusive control over 8051 family
nels, the first member of the MCS-51 to have such system debugging at clock speeds up to 16 MHz. Each
Table 2. Advanced 8-Bit Microcontrollers
Device ROMless EPROM ROM RAM 16-Bit Circuit
Name Version Version Bytes Bytes Timers Type
B051 B031 (B751) 4K 12B 2 HMOS
B051AH B031AH B751H 4K 12B 2 HMOS
B052AH B032AH B752BH BK 256 3 HMOS
BOC51BH BOC31BH B7C51 4K .128 2 CHMOS
83C152 80C152 BK 256 2 CHMOS
83C51FA 80C51FA 87C51FA 8K 256 4 CHMOS
i -- -----.
,,, ,,
,, ,,
,,
,,
, ,,
EXTERNAL
8K ROM
IN 8052 ;--_ • • • • • , ,-------.
TIMER 2 I
:~:::)1 ,~- --]
INTERRUPTS
,,
I
'
'
' COUNTER
256 RAM
4K
IN 8052 INPUTS'
ROM
TXD RXD
PO P2 Pl P3
ADDRESS/DATA
270253-2
Figure 2. Block Diagram of the 8051/8052AH
intJ PREFACE
emulator lets the user view and modify system activity Features common to all members of this family are:
at a symbolic, high-level language' level, speeding and • 16-bit timer (Timerl)
simplifying the development and debug phases of mi-
crocontroller system design, All of the ICE-5100 emu- • 16-bit counter (Timer2)
lators can be hosted on IBM PC Ars or compatibles, • Full-Duplex UART with independent baud-rate
or Intellec® Series III/IV development systems. Three generator
versions of ICE-5tOO are available today. ICE-5100- • Watchdog timer
252 supports HMOS and CHMOS versions of the fol-
lowing components: 8031, 8051, 8751, 8032, 8052, • 8-bit resolution Pulse Width Modulator (PWM)
8752, 80C31, 80C51, 87C51, 83C51FA, 80C51FA, and • 48 I/O lines (33 for 48-pin parts)
87C51FA. ICE-5100/452 supports: 80C452, 83C452, '. HSIO unit
87C452. The ICE 5100/044 supports: 8344, 8044, 8744,
and BITBUSTM components. The HSIO (High Speed Input/Output) unit is an inde-
pendent timer subsystem which manages Timer1 and
Available for the 51 family, ASM-51 and PL/M-51 Timer2 for the programmer. Events (e.g. setting an I/O
both contain a relocation and linkage utility and are pin) can be scheduled to occur automatically when ei-
available for the IBM PC and Intel Microcomputer De- ther of the two timers reaches a preset value. External
velopment Systems running either iNDX or ISIS oper- events can be recorded in a FIFO along with the value
ating systems. of Timerl when the event occurred. The HSIO is con-
nected to eight pins on the 8096 and can generate and
This complete, integrated design-in solution for the monitor events with a 2 microsecond resolution (12
MCS-51 family of microcontrollers speeds product de- MHz crystal).
velopment, and improves design team productivity.
In addition to an EPROM version, the 8X9XBH offer
several improvements over the non BH parts:
MCS®-96 MICROCONTROLLERS
• Dynamic selection of 8-/16-bit bus operation (versus
The MCS-96 Family of microcontrollers was designed fixed 16-bit bus)
for applications which combine high performance 16- • Programmable READY logic
bit fixed-point arithmetic with an immediate interface
• Sample and Hold input to the AID converter
to real world devices and events. The architecture is
based on a single 64 Kbyte address space. In addition to During 1987 Intel added a new series to the MCS-96
. being accessable as memory, the first 256 bytes of this family, the 80C196KA. This part is implemented on a
space are also' directly addressable as registers. These high performance CMOS process and offers significant-
locations are on-chip for high performance and can be ly more performance and reduced power levels. The
treated as byte, word, or double-word, operands by the design also includes many detail improvements while
programme!'. Twenty-four bytes of these registers are sti11 retaining compatibility with the NMOS versions of
used to control the on-board peripherals; the remaining the MCS-96 family.
232 bytes are usuable by the programmer as general
purpose registers. The combination of a register file, on- The MCS-96 family is being used now in a wide variety
board I/O, and a high performance 16-bit CPU .makes of complex control tasks such as robotics, motor con-
the MCS-96 family well matched to closed loop control
applications.
Table 3 Advanced i6-Bit Microcontrollers
Device ROMless EPROM ROM RAM I/O A/D
Name Version Version Bytes Bytes Pins Channels
8395 8095 - 8K 232 29 4
8396 8096 - 8K 232 48
8397 8097 . - 8K 232 40 8
8395BH 8095BH 8795BH 8K 232 29 4
8396BH 8096BH 8796BH 8K 232 48
8397BH 8097BH 8797BH 8K 232 40 8
83C196KB 80C196KA 87C196KB 8K 232 48 8
• AT is a registered trademark of IBM Corporation.
xvi
intJ PREFACE
VREF ANGND
POWER
DOWN
m___ __ m~
FREQUENCY
REFERENCE
CLOCK
GEN
-t 8
Uu:_~- Uj
ROM OR EPROM I
(OPTIONAL):
....."T"--r...... :
I
I CONTROL
SIGNALS
PORTO PORT 1 PORT 2 HSI HSO
ALT FUNCTIONS
270253-3
'Sample and Hold is only present on BX9XBH devices.
Figure 3. MCS®-96 Block Diagram
trol, hard disk mechanisms, printers, modems, automo- cations. Six of the most often used functions of an 8086
tive engine control and high performance anti-skid system have been integrated <into a single chip. Along
braking applications. with higher integration, the 80186 offers higher per-
formance than the standard 8086 via detailed improve-
ments to the design. The 80186 family consists of two
MCS®-96 FAMILY DEVELOPMENT processors; the 80186 and the 80188. These processors
TOOLS have identical capabilities except that the 80186 oper-
ates on a 16-bit bus while the 80188 operates on an
Intel offers a variety of development tools to support 8-bit bus. The 80186 offers higher system performance
the MCS-96 family of microcontrollers. The iSBE-96, a with its 16-bit bus; the 80188 offers lower system cost
low-cost single board emulator, emulates the 8X9X mi- with its 8-bit bus. Both processors operate internally
crocontrollers. VLSiCE-96 provides complete in-Circuit with a 16-bit bus and generates a 20-bit address to give
emulation of the 80C196KC microcontroller. The a total address space of 1 Megabyte.
ICETM-196PCIn-Circuit emulator provides real-time,
transparent emulation of the 80C196KA microcontrol- Although these parts are object code compatible with
ler. All three emulators are efficient and versatile tools the 8086, most of the instructions complete in fewer
for developing, debugging and testing real-time MCS- clock cycles because of enhanced CPU and bus control
96 applications. logic. In addition, many new instructions have been in-
cluded to simplify assembly language programs and to
Software for the MCS-96 family includes macroassem- enhance operation with high level languages. These
bier (ASM-96) which is available along with PL/M-96 new instructions have been included in the 80286 and
and C-96 compilers: Each software package includes 80386 high performance microprocessors.
relocation/linkage utility, library creation utility, and
FPAL-96, a 32-bit floating-point utility. Software runs Besides the processor itself, the major features of the
on IBM PC and Intellec Series III/IV. 80186 and 80188 include:
• 2 Channel DMA (Direct Memory Access) unit
80186 HIGH INTEGRATION • 3 16-bit timer/counters
MICROPROCESSOR
The 80186 family of microprocessors was designed to
bring the 8086 architecture to embedded control appli-
xvii
inter PREFACE
• Interrupt controller During 1987 Intel introduced CMOS versions of the
• Clock generator 80188 and 80186. In addition to lower power these
parts offer increased performance (16 MHz vs 10 MHz
• Chip select logic for the NMOS parts) and two new features: power save
• Ready control logic and DRAM refresh.
Unlike the other embedded control products, the 80186
is intended for applications which need relatively large 80186 FAMI'LY DEVELOPMENT
amounts of program storage and require large and com- TOOLS
plex data structures. Since it is impra<;tical to integrate
the amount of memory required for typical applications Intel offers a full line of development tools to support
onto the processor chip, no attempt is made to incorpo- the 80186 and 80188 ·families of microprocessors.
rate memory on board. On the other hand, and for the I2ICETM emulates the 80186 and 80188 microproces-
same reasons, the architecture incorporates more ele- sorsat 8 MHz and 10 MHz and Intel's new ICE 186
gent and powerful addressing modes than do the other emulates the 80CI86 to 12.5 MHz. Both emulators are
products offered by the Embedded Control Operation. versatile, efficient tools for developing, debugging and
The bus structure offered by the 80186 is also more testing real-time applications for their respective micro-
powerful and flexible. processors.
The 80186 processors are used in high end printers, Software support for the 80186 family consists of Ii
data concentrators, robotics, and many other applica- macroassembler, which also includes linker, locator,
tions which require the high performance of a 16-bit mapper, numerics library, and librarian. High level lan-
microprocessor along with the cost-effectiveness of a guages include PL/M, C, Fortran, and Pascal compil-
highly integrated computer system. Because it has ob- ers with full source code display. Hosts include IBM
ject code compatibility with the industry standard 8086 PC, VAX/VMS', and Intel Development Systems. In-
processor, a wide variety of support is readily available. tel's software tools have been designed to provide opti-
These range from simple programs written to run under mal performance when used with an PICE or Intel's
MS-DOS' to complex operating systems such as ICE-186.
iRMX®-86 and XENIX·.
INT3IiIifAi
INT2IIIITllI
CLKOUT Vee GND
INT1
ExECUTION uNiiJ
I
1S-B1T I
.AW PROGRAMMABLE
I INtERRUPT
I CONTROLLER MAX COUNT
REGISTER ..
I
I CONTROL REGISTERS
I
L...-.,.--..l.-i
r----I-ORao
ORQ1
BHOY
AROV
2I).II1T
'!!IT DESTINATION
HOLD POINTERS
HLOA ,8·11T
lin TRANSFER COUNT
RESET
CONTROL
REOISTERS
270253-4
Figure 4. 80186/80188 Block Dlagram-A CPU Board On a Single Silicon Chip
'VAXIVMS is a registered trademark of Digital Equipment Corporation. .
'MS-DOS and XENIX are trademarks of Microsoft Corporation.
xviii
MCS® ..48 Single Component 1
System
THE SINGLE COMPONENT MCS®-48 SYSTEM
1.0 INTRODUCTION • Add With or Without Carry
• AND, OR, Exclusive OR
Sections 2 through 5 describe in detail the, func- • Increment/Decrement
tional characteristics of the 8748H and 8749H EPROM, • Bit Complement
8048AH/8049AH/8050AH ROM, and 8035AHL! • Rotate Left, Right
8039AHL/8040-AHL CPU only single component micro- • Swap Nibbles
computers. Unless otherwise noted, details within these • BCD Decimal Adjust
sections apply to all versions. This chapter is limited to
If the operation performed by the ALU results in a value
those functions useful in single-chip implementations of
represented by more than 8 bits (overflow of most sig-
the MCS®-48. The Chapter on the Expanded MCS®-48 .
nificant bit), a Carry Flag is set in the Program Status
System discusses functions which allow expansion of
Word.
program memory, data memory, and input output capa-
bility.
ACCUMULATOR
2.0 ARCHITECTURE
The accumulator is the single most important data register
The following sections break the MCS-48 Family into in the processor, being one of the sources of input to the
functional blocks and describe each in detail. The follow- ALU and often the destination of the result of operations
ing description will use the 8048AH as the representative performed in the ALU. Data to and from I/O ports and
product for the family. See Figure I. memory also normally passes through the accumulator.
2.1 Arithmetic Section 2.2 Program Memory
The arithmetic section of the processor contains the basic Resident program memory consists of 1024,2048, or 4096
data manipulation functions of the 8048AH and can be words eight bits wide which are addressed by the program
divided into the following blocks: counter. In the 8748H and the 8749H this memory is user
programmable and erasable EPROM; in the 8048AH/
• Arithmetic Logic Unit (ALU) 8049AHl8050AH the memory is ROM which is mask
programmable at the factory. The 8035AHL/8039AHL/
• Accumulator 8040AHL has no internal program memory and is used
with external memory devices. Program code is com-
• Carry Flag pletely interchangeable among the various versions. To
access the upper 2K of program memory in the 8050AH,
• Instruction Decoder , and other MCS-48 devices, a select memory bank and a
JUMP or CALL instruction must be executed to cross the'
,In a typical operation data stored in the accumulator is 2K boundary.
combined in the ALU with data from another source on
the internal bus (such as a register or 110 port) and the There are three' locations in Program Memory of special
result is stored in the accumulator or another register. importance as shown in Figure 2.
The following is more detailed description of the function , , LOCATION 0
of each block. 'Activating the Reset line of the processor causes the first
instruCtion to be fetched from location O. ,
INSTRUCTION DECODER
LOCATION 3
The operation code (op code) portion of each program Activating the Interrupt input, line of the processor (if
instruction is stored in the Instruction Decoder and con- interrupt is enabled) causes a jump to' subroutine at lo-
verted to outputs which control the function of each of' cation 3.
the blocks of the Arithmetic Section. Tbese lines control
the source of data and the destination register as well as LOCATION 7
the function performed in the ALU. A timer/counter interrupt resulting' from timer counter
overflow (if enabled) causes a jump to subroutine at loca-
ARITHMETIC LOGIC UNIT tion 7.
The ALU accepts 8-bit data words from one or two sources Therefore, the first instruction to be executed after ini-
and generates an 8-bit result under control cif the Instruc- tialization is stored in location 0, the first word of an
tion Decoder. The ALU can perform the following external interrupt service subroutine is stored in location
functions: 3, and the first word of a timer/counter service routines
EXPANSION TO
MORE 110 AND
MEMORY
RESIDENT
EPROM ROM
"11
cac
Cil ~
:- Z
CXI C)
~ r-
CXI m
:J:
CD o
o
PORT 1
BUS
o
~
CXI
BUFFER s::
:J:
AND "C
LATCH
o
~ Z
m
~ Z
~
'" CD
o
UI
REGISTER
REGISTER
REGISTER
-I
s::
o
~
U)
TEST 0 REGISTER ®
:J: I
REGISTER ~
ID TEST 1 CCI
g
t
REGISTER U)
INT
w
..:'
C
FLAG 0
c
c
0
REGISTER
~
vee .. PROGRAM SUPPLY w REGISTER -I
iii"
ea POWER V ,....._-'-_ _, FLAG 1 C m
iii
SUPPLY ~ +5V (LOW POWER STA.NDBY) i
TIMER
8 LEVEL STACK
(VARIABLE LENGTH) s::
~GND
FLAG
3 CARRY
OPTIONAL SECOND
REGISTER BANK
Ace
DATA STORE
ACCBIT
TEST
RESIDENT
RAM ARRAY
INTERRUPT I PROMI . CPU! OSCILLATOR ADDRESS PROGRAM SINGLE READ
EXPANDER MEMORY XTAL LATCH MEMORY STEP WRITE
STROBE SEPARATE STROBe ENABLE STROBES
CYCLE
INITIALIZE
CLOCK
SINGLE COMPONENT MCS®-48 SYSTEM
is stored in location 7. Program memory can be used to registers in place of locations 0--7 and are then directly
store constants as well as program instructions. Instruc- addressable. Th,is second bank of working registers may
tions such as MOVP and MOVP3 allow easy access to be used as an extension of the first bank or reserved for
data "lookup" tables. use during interrupt service subroutines allowing the reg-
isters of Bank 0 used in the main program to be instantly
"saved" by a Bank Switch. Note that if this second bank
-D
is not used, locations 24-31 are still addressable as general
purpose RAM. Since the two RAM pointer Registers RO
and RI are a part of the working register array, bank
switching effectively creates two more pointer registers
(ROland Rlf) which can be used with RO and Rl to easily
access up to four separate working areas in RAM at one
time. RAM locations (8-23) also serve a dual role in that
2 0 4 S L = : J . . l .SEL. MB1 they contain the program counter stack as explained in
2047~ j SELMBO Section 2.6. These locations are addressed by the Stack
Pointer during subroutine calls as well as by RAM Pointer
Registers RO and R i. If the level of subroutine nesting is
1024 ~ less than 8, all stack registers are not required and can be
1023
used as general purpose RAM locations. Each level of
subroutine nesting not used provides the user with two
additional RAM locations.
LOCATION 7-
8
7
6
- TIMER INTERRUPT
VECTORS
PROGRAM HERE
63_-----_
(127)
5 «255»
4 LOCATION 3- USER RAM
EXTERNAL 32 x 8
3 4f- INTERRUPT (96 x 8)
2 VECTORS
PROGRAM HERE «224 x 8»
1
r-
o 716151413121110 RESET VECTORS ~~~----B-A-N-K--1-----t I
ADDRESS PROGRAM HERE WORKING DIRECTLY
REGISTERS ADDRESSABLE
8 xS WHEN BANK 1
-----Rl'- - - - IS SELECTED
24 ----liO'---- I
. Figure 2. Program Memory Map 23
2.3 Data Memory 8 LEVEL STACK
OR
ADDRESSED
INDIRECTLY
USER RAM THROUGH
Resident data memory is organized as 64, 128, or 256 by 16 x 8 R1 OR RO
8-bits wide in the 8048AH, 8049AH and 8050AH. All (RO' OR R1')
locations are indirectly addressable through either of two
~~-----B-A-NK--O-----t
RAM Pointer Registers which reside at address 0 and I
of the register array. In addition, as shown in Figure 3, WORKING DIRECTLY
I
REGISTERS ADDRESSABLE
the first 8 locations (0--7) of the array are designated as 8x8 WHEN BANK 0
working registers and are directly addressable by several
instructions. Since these registers are more easily ad- O~
1--=--=-.:-=
____ :'RI:':-::
~R~O ____ ~
IS SE~ECTEr
dressed, they are usually used to store frequently accessed
intermediate results. The DJNZ instruction makes very
efficient use of the working registers as program loop IN ADDITION RO OR R1 (RO' OR R1')
MAY BE USED TO ADDRESS 256 ( ) 8049AH, 8749H,
counters by allowing the programmer to decrement and WORDS OF EXTERNAL RAM. « » 8050AH
test the register in a single instruction.
By executing a Register Bank Switch instruction (SEL
RB) RAM locations 24-31 are designated as the working Figure 3. Data Memory Map
1-3
SINGLE COMPONENT MCS®-48 SYSTEM
VCC
VCC
Q
INTERNAL
BUS D
D 1/0
FLIP PIN
FLOP PORT 1
LOW AND 2
IMPEDANCE
PULLDOWN
CLK Q
WRITE
PULSE
-
IN
MAX
-500
-400
10H -300 ~_ ___
(~A) -200
OV 2V 4V
VOL
LOW IMPEDANCE PULLUP . HIGH IMPEDANCE PULLUP LOW IMPEDANCE PULLDOWN
These graphs are lor inlormational purposes only and are not guaranteed minimums or maximums.
Figure 4. "Quasi-bidirectional" port Structure
1-4
SINGLE COMPONENT MCS®-48 SYSTEM
2.4 Input/Output statically latched output port or non-latching input port.
Input and output lines on this port cannot be mixed
The 8048AH has 27 lines which can be used for input or however.
output functions. These lines are grouped as 3 ports of 8
lines each which serve as either inputs, outputs or bidi- As a static port, data is written and latched using the OUTL
rectional ports and 3 "test" inputs which can alter pro- instruction and inputted using the INS instruction. The
gram sequences when tested by conditional jump INS and OUTL instructions generate pulses on the cor-
instructions. responding RD and WR output strobe lines; however, in
the static port mode they are generally not used. As a
PORTS 1 AND 2 bidirectional port the MOVX instructions are used to read
and write the port. A write to the port generates a pulse
Ports I and 2 are each 8 bits wide and have identical on the WR out~ line and output data is valid at the
characteristics. Data written to these ports is statically trailing edge of WR. A read of the port generates a pulse
latched and remains unchanged until rewritten. As input on the RD output line and input data must be valid at the
ports these lines are non-latching, i.e., inputs must be trailing edge of RD. When not being written or read, the
present until read by an input instruction. Inputs are fully BUS lines are in a high impedance state. See also sections
TIL compatible and outputs will drive one standard TIL 7 and 8 in the Expanded MCS-48 System chapter.
load.
2.5 Test and INT Inputs
The lines of ports I and 2 are called quasi-bidirectional Three pins serve as inputs and are testable with the~
because of a special output circuit structure which allows' ditional jump instruction. These are TO, TI, and INT.
ellch line to serve as an input, and output, or both even These pins allow inputs to cause program branches without
though outputs are statically latched. Figure 4 shows the necessity to load an input port into the accumulator.
the ciI'cuit configuration in detail. Each line is continu- The TO, TI, and INT pins have other possible functions
ously pulled up to VCC through a resistive device of as well. See the pin description in Section 3.
relatively high impedance.
2.6 Program Counter and Stack
This pullup is sufficient to provide the source current for
a TIL high level yet can be pulled low by a standard TIL The Program Counter is an independent counter while the
gate thus allowing the same pin to be used for both input Program Counter Stack is implemented suing pairs of reg-
and output. To provide fast switching times in a "0" to isters in the Data Memory Array. Only 10, 11, or 12 bits
"I" transition a relatively low impedance device is of the Program Counter are used to address the 1024,
switched in momentarily ("" 115 of a machine cycle) when- 2048, or 4096 words of on-board program memory of the
ever a "I" is written to the line. When a "0" is written 8048AH, 8049AH, or 8050AH, while the most significant
to the line a low impedance device overcomes the light bits can be used for external Program Memory fetches.
pullup and provides TIL current sinking capability. Since See Figure 5. The Program Counter is initialized to
the pulldown transistor is a low impedance device a "1" zero by activating the Reset line. -
must first be written to any line which is to be used as an
input. Reset initializes all lines to the high impedance' 'I ' ,
state.
It is important to note that the ORL and the ANL are read! 1~IAwl~I~I~I~I~I~I~I~I~I~1
, ,
write operations. When executed, the f.LC "reads" the i
port, modifies the data according to the instruction, then Conventional Program Counter
"writes" the data back to the port. The "writing" (es- • Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
sentially an OUTL instruction) enables the low impedance
pull-up momentarily again even if the data was unchanged
from a "1." This specifically applies to configurations
that have inputs and outputs mixed together on the same Figure 5. Program Counter
port. See also section 8 in the Expanded MCS-48 System
chapter.
An interrupt or CALL to a subroutine causes the contents
BUS
of the program counter to be stored in one of the 8 register
Bus is also an 8-bit port which is a true bidirectional port pairs of -the Program Counter Stack as shown in Figure
with associated input and output strobes. If the bidirec- 6. The pair to be used is determined by a 3-bit Stack
tional feature is not needed, Bus can serve as either a Pointer which is part of the Program Status Word (PSW).
1-5
SINGLE COMPONENT MCS®-48 SYSTEM
the word. The Program Status Word is actually a collection
of flip-flops throughout the machine Which can be read or
POIN TER
111 · R23
22
written as a whole. The ability to write to PSW allows
for easy restoration of machine status, after a power down
sequence.
21
, 110
20 SAVED IN STACK STACK POINTER
101
· 19
I I
1S
17
100 --'L MSB LSB
: 16 CY
AC
CARRY
AUXILIARY CARRY
: 15 FO FLAG 0
··
011 BS REGISTER BANK SELECT
14
; 13
010
·: 12
11
Figure 7. Program Status Word (PSW)
The upper four bits of PSW are stored in the Program
001
: 10 Counter Stack with every call to subroutine or interrupt
vector and, are optionally restored upon return with the
000
PSW
~ PCS-11 9
RETR instruction. The RET return instruction does not
PC4-7 .~ ,PCO-3 RS update PSW.
MSB LSB
The PSW bit definitions are as follows:
Bits 0--2: Stack Pointer bits (So, S), S2)
Figure 6•. Program Counter Stack
Bit 3: Not used (" 1" level when read)
Data RAM locations 8-23 are available as stack registers
and are used to store the Program Counter and 4 bits of Bit 4: Working Register Bank Switch Bit (BS)
PSW as shown in Figure 6. The Stack Pointer .when o = Bank 0
initialized to 000 points to RAM locations 8 and 9. The '1 = Bank 1
first subroutine jump or interrupt results in the program
counter contents being transferred to locations 8 and 9 of Bit 5: Flag 0 bit (PO) user controlled flag which can
the RAM array. The stack pointer is then incremented by be complemented or cleared, and tested with
'one to point to locations 10 and 11 in anticipation of the conditional jump instruction JFO.
another CALL. Nesting of subroutines wihtin subroutines
can continue up to 8 times without overflowing the stack. Bit 6: Auxiliary Carry (AC) carry bit generated by
If overftow does occur the deepest address stored (ioca- an ADD instruction and used by the decimai
tions 8 and 9) will be overwritten and lost since the stack -adjust instruction DA A.
pointer overflows from III to 000. It also underflows from
000 to 111. Bit 7: ' Carry (CY) carry flag which indicates that the
previous operation has resulted in overflow of
The end of a subroutine, which is signalled by a return the accumulator.
instruction (RET or RETR), causes the Stack Pointer to
be decremented and the contents of the resulting register 2.8 Conditional Branch Logic
pair to be transferred to the Program Counter.
The conditional branch logic within the processsor enables
2.7 Program Status Word several conditions internal and external to the processor
to be tested-by the users program. By using the conditional
An 8-bit. status word which can be loaded to and from the jump instruction the conditions that are listed in Table
accumulator exists called the Program Status Word 1 can effect a change in the sequence of the program
(pSW). Figure 7 shows the information available in execution:
1-6
SINGLE COMPONENT MCS®-48 SYSTEM
Table 1
abled by the users program. An interrupt request must be
Jump Conditions removed before the RETR instruction is executed upon
Device Testable (Jum On) return from the service routine otherwise the processor
will re-enter the service routine immediately. Many pe-
not all ripheral devices prevent this situation by resetting their
Accumulator All zeros zeros interrupt request line whenever the processor accesses
Accumulator Bit - I (Reads or Writes) the peripherals data buffer register. If
Carry Flag 0 1 the interrupting device does not require access by the
User Flags (FO, Fl) - 1 processor, one output line of the 8048AH may be des-
Timer Overflow Flag - 1 ignated as an "interrupt acknowledge" which is activated
Test Inputs (TO,-I.!) 0 1 by the service subroutine to reset the interrupt request.
Interrupt Input (INT) 0 - The INT pin may also be tested using the conditional jump
instruction IN!. This instruction may be used to detect the
2.9 Interrupt presence of a pending interrupt before interrupts are en-
abled. If interrupt is left disabled, INT may be used as
An interrupt sequence is initiated by applying a low "0" another test input like TO and Tl.
level input to the INT pin. Interrupt is level triggered and
active low to allow "WIRE ORing" of several interrupt 2.10 Timer/Counter
sources at the input pin. Figure 8 shows the interrupt
logic.of the 8048AH. The Interrupt line is sampled every The 8048AH contains a counter to aid the user in counting
instruction cycle and when detected causes a "call to external events and generating accurate time delays with-
subroutine" at location 3 in program memory as soon as out placing a burden on the processor for these functions.
all cycles of the current instruction are complete. On 2- In both modes the counter operation is the same, the only
cycle instructions the interrupt line is sampled on the 2nd difference being the source of the input to the counter.
cycle only. !NT must be held low for at least 3 machine The timer/event counter is shown in Figure 9.
-cycles to ensure proper interrupt operations. As in any
CALL to subroutine, the Program Counter and Program COUNTER
Status word are saved in the stack. For a description of
this operation see the previous section, Program Counter The 8-bit binary counter is presettable and readable with
and Stack. Program Memory location 3 usually contains two MOV instructions which transfer the contents of the
an unconditional jump to an interrupt service subroutine accumulator to the counter and vice versa. The counter
elsewhere in program memory. The end of an interrupt content may be affected by Reset and should be initialized
service subroutine is signalled by the execution of a Return by software. The counter is stopped by a Reset or STOP
and Restore Status instruction RETR. The interrupt system TCNT instruction and remains stopped until started as a
is single level in that once an interrupt is detected all timer by a START T instruction or as an event counter
further interrupt requests are ignored until execution of an by a START CNT instruction. Once started the counter
RETR reenables the interrupt input logic. This _occurs at will increment to this maximum count (FF) and overflow
the beginning of the second cycle of the RETR instruction. to zero continuing its count until stopped by a STOP TCNT
This sequence holds true also for an internal interrupt instruction or Reset.
generated by timer overflow. If an internal timer/counter
generated interrupt and an external interrupt are detected The increment from maximum count to zero (overflow)
at the same time, the external source will be recognized. results in the setting of an overflow flag flip-flop and in
See the following Timer/Counter section for a-description the generation of an interrupt request. The state of the
of timer interrupt. If needed, a second external interrupt overflow flag is testable with the conditional jump instruc-
can be created by enabling the timer/counter interrupt, tion JTF. The flag is reset by executing a JTF or by Reset.
loading FFH in the Counter (ones less than terminal The interrupt request is stored in a latch and then ORed
count), and enabling the event counter mode. A "I" to with the external interrupt input INT. The timer interrupt
"0" transition on the Tl input will then cause an interrupt may be enabled or disabled independently of external in-
vector to location 7. terrupt by the EN TCNTI and DIS TCNTI instructions.
If enabled, the counter overflow will cause a subroutine
INTERRUPT TIMING call to location 7 where the timer or counter service routine
may be stored.
The interrupt input may be enabled or disabled under
Program Control using the EN I and DIS I instructions. If timer and external interrupts occur simultaneolisly, the
Interrupts are disabled by Reset and remain so until en- external source will be recognized and the Call will be to
1-7
SINGLE COMPONENT MCS®-48 SYSTEM
CONDITIONAL
S
JUMP LOGIC
TIMER
FLAG INTERRUPT
JTF CALL
EXECUTED-~1r~~~~~R EXECUTED
RESET--"1L._
CLR EXTERNAL
...-------ID Q INTERRUPT
RECOGNIZED.
TIMER ------...--4S Q
OVERFLOW
TIMER·
OVERFLOW TIMER
FF INTERRUPT
TIMER INT
RECOGNIZED
RECOGNIZED'-;:::~-\-_ _~R
EXECUTED
RESET
>---4S
~-,~, INTERRUPT
IN '.
PROGRESS'
EN TCNTI
EXECUTED
-------4 S. Q FF
TIMER R
INT
ENABLE
DIS TCNT!' --lr"'\~~--I
EXECUTED R Q
RESET
INTcr-------4 D
PIN
INT RESET
FF
RETR
EXECUTED
CLK
·ALE.~~r-~___~:::]
, ~~~~;;CLE._-t._'
ENI ----Is
EXECUTED
1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET
INT ALL FURTHER INTERRUPTS ARE LOCKED OUT
ENABLE INDEPENDENT OF STATE OF EITHER INTERRUPT
DISI
EXECUTED--l~~_-I R . ENABLE FLIP-FLOP.
RESET 2. WH!LE TI~ER INTERRUPTS ARE DISABLED TIMER
OVERFLOW III WILL NOT STORE ANY OVERFLOW
'THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER ..
Figure 8. Interrupt Logic
1-8
SINGLE COMPONENT MCS®-48 SYSTEM
PRESCALER
XTAL + 15 - +32
LOAD OR READ
I
CLEARED ON START TIMER
JUMP ON
TIMER FLAG
r------..... START
COUNTER
EDGE 8BITTIMERI
DETECTOR EVENT COUNTER
o OVERFLOW
STOPT FLAG
INT
ENABLE--------~___ '
Figure 9. Timer/Event Counter
location 3. Since the timer interrupt is latched it will re- olution less than I count an external clock can be applied
main pending until the external device is serviced and to. the TI input and the counter operated in the event
immediately be recognized upon return from the service counter'mode. ALE divided by 3 or more can serve as
routine. The pending timer interrupt is reset by the Call this external clock. Very small delays or "fine tuning"
to location 7 or may be removed by executing a DIS of larger delays can be easily accomplished. by software
TCNT! instruction. delay loops. .
AS AN EVENT COUNTER Often a serial link is desirabl~ ill an MCSA8 family mem~
ber..Thble 2 lists the timer counts and cycles needed
Execution of a START CNT instruction connects the T! for a specific baud rate given a crystal frequency.
input pin to the counter input and enables the counter.
The T! input is sampled at the beginning of state 3 or in 2.11 Clock and Timing Circuits
later MCS-48 devices in state time 4. Subsequent high to
low transitions on TI will cause the counter to increment. Timing generation for the 8048AH is completely selfcon-
T! must be held low for at least I machine cycle to insure tained with the exeception of a frequency reference which
it won't be missed. The maximum rate at which the can be XTAL, ceramic resonator, or external clock source.
counter may be incremented is once per three instruction The Clock and Timing circuitry can be divided into the
cycles (every 5.7 f.Lsec when using an 8 MHz crystal)-- following functional blocks.
there is no minimum frequency. TI input must remain
high for at least 1/5 machine cycle after each transition. OSCILLATOR
The on-board oscillator is a high' gain piiU'aUel resonant
AS A TIMER circuit with a frequency range of I to 11 MHz .. The XI
external pin is the input to the amplifier stage \:yhile X2
Eexcution of a START T instruction connects an internal is the output. A crystal or ceramic resonator connected
clock to the counter input and enables the counter. The between XI and X2 provides the feedback and phase shift
internal clock is derived bypassing the basic machine cycle required for oscillation. If an accurate frequency reference
clock through a + 32 prescaler. The prescaler is reset is not required, ceramic resonator may be used in place
during the START T instruction. The resulting clock in- of the crystal. .
crements the counter every 32 machine cycles. Various
delays from I to 256 counts can be obtained by presetting For accurate clocking, a crystal should be used. An ex-
the counter and detecting overflow. Times longer than 256 ternally generated clock may also be applied to XI-X2
counts may be achieved by accumulating multiple over- as the frequency source. See the data sheet for more
flows in a register under software control. For time res- infermation.
1-9
SINGLE COMPONENT MCS®-48 SYSTEM
Table 2. Baud Rate Generation
Frequency Tey TO Prr(1/5 Tey) Timer Presealer
(MHz) (32 Tey)
4 3.751LS 750ns 120ILS
6 2.501LS 500ns 801LS
8 1.881LS 375ns 60.21LS
11 1.361LS 275ns 43.51LS
Baud 4 MHz 6 MHz 8 MHz 11 MHz
Rate Timer Counts + Timer Counts + Timer Counts + Timer Counts +
Instr. Cycles Instr. Cycles Instr. Cycles Instr. Cycles
110 75 + 24 Cycles 113 + 20 Cycles 151 + 3 Cycles 208 + 28 Cycles
.01% Error .01% Error .01% Error .01% Error
300 27 + 24 Cycles 41 + 21 Cycles 55 + 13 Cycles 76 + 18 Cycles
.1% Error .03% Error .01% Error .04% Error
1200 6 + 30 Cycles 10 + 13 Cycles 12 + 27 Cycles 19 + 4 Cycles
.1% Error .1% Error .06% Error .12% Error
1800 4 + 20 Cycles 6 + 30 Cycles 9 + 7 Cycles 12 + 24 Cycles
.1% Error .1% Error ;17% Error .12% Error
2400 3 + 15 Cycles 5 + 6 Cycles 6 + 24 Cycles 9 + 18 Cycles
.1% Error .4% Error .29% Error .12% Error
4800 1 + 23 Cycles 2 + 19 Cycles 3 + 14 Cycles 4 + 25 Cycles
1.0% Error .4% Error .74% Error .12% Error
STATE COUNTER power supply is within tolerance. Only 5 machine cycles
(6.8 !J.S @ 11 MHz) are required if power is already on
The output of the oscillator is divided by 3 in the State and the oscillator has stabilized. ALE and PSEN (if EA
Counter to create a clock which defines the state times of = 1) are active while in Reset.
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction. Reset performs -the following functions:
The output of CLK on TO is disabled by Reset of the
processor. 1) Sets program counter to zero.
CYCLE COUNTER 2) Sets stack pointer to zero.
CLK is then divided by 5. in the Cycle Counter to pro- 3) Selects register bank O.
vide a clock which defines a machine cycle consisting
of 5 machine states as sho",on in Figure 10. Figure 11 4) Selects memory bank O.
shows the different internal operations as divided into
the machine states. This clock is called Address Latch ·5) Sets BUS to high impedance state (except when
Enable (ALE) because of its function in MCS-48. sys- EA = 5V).
tems with external memory. It is provided continuous-
lyon the ALE output pin. 6) Sets Ports 1 and 2 to input mode.
2.12 Reset 7) Disables interrupts (timer and external).
The reset input provides a means for initialization for the 8) Stops timer.
processor. This Schmitt-trigger input has an internal pull-
up device which in combination with an external 1 !J. fd 9) Clears timer flag.
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure 10) Clears FO and Fl.
12. If the reset pulse is generated externally the RESET
pin must be held low for at least 10 milliseconds after the 11) Disables clock output from TO.
1-10
SINGLE COMPONENT MCS®-48 SYSTEM
JUMP ON
TEST = 1 OR 0
XTAL2 . - - - - - . ,
11 +3
MHzCJ STATE .273 ~sec (3.67 MHz)
COUNTER
XTAL 1 L..._ _ _ _..I
DIAGRAM OF 8048AH CLOCK UTILITIES
. 1.36 ~sec CYCLE .
55 51
INPUT DECODE
52 53
I 54 55 51
EXECUTION INPUT
I NST.
OUTPUT
INC. PC
ADDRESS
I ~ I I I
INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)
PREVIOUS CYCLE-"'~'f-o.
__- - - 1 S T CYCLE----I.......,.... ~1
_ - - - 2 N D CYCLE----l...
STATE TIME:
52 I 53 I 54 I 55 I 51 I 52 I 53 I 54 55 I 51 55 I 51 I 52
(02)"TO
ALE ~~--------~~----------~~--------
PSEN' - _ _ _ __,
RD,WR _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ __, '-------'I
PROG - - - - - - - - - - - - - - - - - - ,
'EXTERNAL MODE
"IF ENABLED
8048AH/8049AH TIMING
Figure 10. MCS®-48 Timing Generation and Cycle Timing
2.13 Single-Step half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
This feature,· as pictured in Figure 13, provides the showing the interaction between output ALE and input
user with a debug capability in that the processor can be SS, is shown. The BUS buffer contents are lost during
stepped through the program one instruction at a time. single step; however, a latch may be added to reestablish
While stopped, the address of the next instruction to be the lost I/O capability if needed. Data is valid at the leading
fetched is available concurrently on BUS and the lower edge of ALE.
1-11
CYCLE 1 CYCLE 2
INSTRUCTION S1 ~)2 S3 54 S5 S1 S2 S3 54 55 !
INA,P
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
- - READ
PORT - ·- -
OUTL P,A
-
FETCH INCRIEMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
OUTPUT
TO PORT
- - - ·- -
ANLP,=DATA
FETCH INCRleMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA - INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
-
"II
ORL P,= DATA
FETCH INCReMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA - INCREMENT
PROGRAM COUNTER
'OlirPUT
TO PORT
- UI
I£i
c INSA,BUS
FETCH INCReMENT
INSTRUCTION PROGRAM COUNTER
- INCREMENT
TIMER
- - READ
PORT - · - - Z
...:-"
iiJ
OUTL BUS, A
FETCH INCReMENT
INSTRUCTION PROGRAM COUNTER
- INCREMENT
TIMER
OUTPUT
TO PORT
- - - .. - -
C)
r-
m
o
CD
...
0 ANL BUS, = DATA
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
- 'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE. DATA - INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
-
I o
i:
~ ORL BUS, = DATA
FETCH INCREMENT
- 'INCREMENT READ PORT
FETCH
- INCREMENT 'OUTPUT
- "U
% INSTRUCTION PROGRA'. COUNTER TIMER IMMEDIATE DATA PROGRAM COUNTER TO PORT
oZ
....
CD
...
0 MOVX@R,A
FETCH INCREMENT
INSTRUCTION PROGRAII COUNTER
OUTPUT RAM
ADDRESS
INCREMENT
TIMER
OUTPUT·
DATA TO RAM
- - - ·- - m
Z
~ ~ MOVXA,@R
FETCH INCREMENT OUTPUT RAM INCREMENT
- - READ
- ·- - -t
% INSTRUCTION PROGRAII COUNTER ADDRESS TIMER DATA
i:
..
5'
!!I.
MOVDA,PI
FETCH INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
- - READP2
LOWER
- ·- - tl
·-
@
-....
c - - -
FETCH INCREMENT OUTPUT INCREMENT OUTPUT DATA
-
n .~
MOVDPI,A
INSTRUCTION PROGRAM COUNTER OPCODE/ADDRESS TIMER TOP2LOWER
0" FETCH INCREMENT OUTPUT INCREMENT OUTPUT
- - - ·- -
~
:::s ANLDP,A
INSTRUCTION PROGRAM COU·NTER OPCODE/ADDRESS TIMER DATA
3"
5'
ORLDP,A
FETCH INCR:EMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODEIADDRESS
INCREMENT
TIMER
. OUTPUT
DATA
- - - ·- -
m
ICI
C
J(CONDITIONAL) FETCH INCR:EMENT
INSTRUCTION PROGRAM COUNTER
SAMPLE
CONDITION
'INCREMENT
SAMPLE - FETCH
IMMEDIATE DATA - UPDATE
PROGRAM COUNTER · - - i:
iii"
ICI
iii
STRTT
STRTCNT
FETCH INCFIEMENT
INSTRUCTION PROGRAM COUNTER
- · - START
COUNTER
:I STOP TCNT
FETCH INCFIEMENT
INSTRUCTION PROGRAM COUNTER
- · - STOP
COUNTER
ENI
FETCH INCFIEMENT
INSTRUCTION PROGRA'M COUNTER
- • ENABLE
INTERRUPT
- ·VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
DISI
FETCH INCFlEMENT
INSTRUCTION PROGRAM COUNTER
- • DISABLE.
INTERRUPT - BEING ACCESSED.
(1) IN LATER MC5-48 DEVICES T1 IS SAMPLED IN S4.
FETCH INCIIEMENT • ENABLE
ENTOCLK
INSTRUCTION PROGRAM COUNTER CLOCK
-
L- ___ ------
SINGLE COMPONENT MCS®-4B SYSTEM
clear input. ALE should be buffered since the clear input
EXTERNAL RESET
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
is initiated by clocki!!g a "1" into the flip-flop. This "1"
Vcc
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the pro-
cessor be~s an instruction fetch which brings ALE low
ACTIVE resetting SS through the clear input and causing the pro-
PULLUP
cessor to again enter the stopped state.
2.14 Power Down Mode
POWER ON RESET (B048AH, B049AH, 8050AH,
B039AHL, 8035AHL, B040AHL)
Extra circuitry has been added to the 8048AHl8049AHI
.J:L 1K 8050AH ROM version to allow power to be removed from
f all but the data RAM array for low power standby oper~
ation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.
Figure 12. Vee serves as the 5V supply pin for the bulk of circuitry
while the VDD pin supplies only the RAM array. In normal
operation both pins are a 5V while in standby, Vee is at
TIMING ground and VDD is maintained at its standby value. Ap-
plying Reset to the processor through the RESET pin
The 8048AH operates in a single-step mode as follows: inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
I) The processor is requested to stop by applying a low power is removed from Vcc.
level on SS.
A typical power down sequence (Figure 14) occurs as
2) The processor responds by stopping during the address follows:
fetch portion of the next instruction. -If a double cycle
instruction is in' progress when the single step com- 1) Imminent power supply failure is detected by user de-
mand is received, both cycles will be completed before fined circuitry. Signal must be early enough to allow
stopping. 8048AH to save all necessary data before Vee falls
3) The proc~ssor acknowledges it has entered the stopped below normal operating limits.
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruc- 2) Power fail signal is used to interrupt processor and
tion to be fetched is present on BUS and the lower vector it to a power fail service routine.
half of port 2.
4) ss is then raised high to bring the processor out of the 3) Power fail routine saves all important data and machine
stopped mode allowing it to fetch the next instruction. status in the internal data RAM array. Routine may
The exit from stop is indicated by the processor bring- also initiate transfer of backup supply to the VDD pin
ing ALE low. and indicate to external circuitry that power fail routine
is complete.
5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS 4) Reset is applied to. guarantee data will not be altered
is left high the processor remains in a "Run" mode, as the power supply falls out of limits. Reset must be
A. diagram for implementing the single-step function of held low until Vee is at ground level.
the 8748H is shown in Figure 13. D.:!}'pe flip-flop with
preset and clear is used to generate SS. In the run mode Recovery from the Power Down mode can occur as any
SS is held high by keeping the flip-flop preset (preset has other power-on sequence with an external capacitor on
precedence over the clear input). To enter single step, the Reset input providing the necessary delay. See the
preset is removed allowing ALE to bring SS low via the previous section on Reset.
1-13
SINGLE COMPONENT MCS®-48 SYSTEM
+5V
+5V SINGLE 10K
MOMENTARY
PUSHBUTTON 10K
~u~PN--~-----------'
PRESET
+5V D Q
+5V
,..--------(> CLOCK
10K
DEBOUNCE
LATCH
1/27400
ALE
SINGLE STEP CIRCUIT
1 S3 1 54 1 S5 I S1 1 S2 1 S3 1 • • ·IS3154IS51 1 S2 1
ALE~
SS
n
BUS PCD-7
: : C
P2D-23 1/0 PC 8-11
SINGLE STEP TIMING
S : 1/0
Figure 13. Single Step Operation
1·14
SINGLE COMPONENT MCS®-48 SYSTEM
reset the prescaler and time state generators. TO may then
be brought down with the rising edge of Xl. Two clock
cycles later, with the rising edge of X I, the device enters
into Time State 1, Phase 1, SS' is then brought down to
POWER~
SUPPLY PROCESSOR; "---
5 volts 4 clocks later after TO. RESET' is allowed to go
INTE~RUPTED I :
high 5 tCY (75 clocks) later for nonnal execution of code.
POWER ~ I I NORMAL
See Figure 15.
SUPPLY ·_ _ _' _ _ I_ _ _ POWERON
FAIL SIGNAL I I I SEQUENCE
I I FOLLOWS
RESET : LJ ___ _
i i
DATA SAVE ACCESS TO
ROUTINE DATA RAM
EXECUTED INHIBITED
Figure 14. Power Down Sequence
2.15 External Access Mode
Nonnally the first IK (8048AH), 2K (8049AH), or 4K
(8050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to effectively disable internal
program memory by forcing all program memory fetches
to reference external memory. The following chapter ex-
plains how access to external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
applications program and substitute an external program
of his choice - a diagnostic routine for instance. In ad- .
dition, the date sheet shows how internal program mem-
ory can be read externally, independent of the processor:
A "1" level on EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.
2.16 Sync Mode
The 8048AH, 8049AH, 8050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of mUltiple controller circuits by allowing the de-
signer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchro-
nizing between the tester and the OUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X I clock cycles to fully
1-15
SINGLE COMPONENT MCS®-48 SYSTEM
X1
PHASE 1- - - - - -- - - --"'-:""
PHASE 2- - - - - - - - - - - - -
TIME STATE 2 3 4
SS 1~~----.J
OV
5V
TO OV--------------------~
5V
5V
ALE OV--------------------------------------------------~
RESET OV--------------------------------------------~------~---------------
SYNC MODE TIMING
Figure 15. Sync Mode Timing
3.0 PIN DESCRIPTION
The MCS-48 processors are packaged iii 40 pin Dual In-
Line Packages (DIP's). Thble 3 is a summary of the
functions of each pin. Figure 16 is the logic symbol
PORT for the 8048AH product family. Where it exists, the sec-
8
#1 ond paragraph describes each pin's function in an ex-
RESET panded MCS-48 system. Unless ·otherwise specified, each
PORT input is TIL compatible and each output will drive one
SINGLE STEP 8 #2 standard TIL load. .
EXTERNAL B048AH
MEM B049AH
BOSOAH READ
TEST {
WRITE
PROGRAM
INTERRUPT
STORE ENABLE
ADDRESS
BUS 8 LATCH ENABLE
Figure 16. 8048AH and 8049AH Logic Symbol
1-16
SINGLE COMPONENT MCS®-48 SYSTEM
Table 3. Pin Description
Pin
Designation Number* Function
Vss 20 Circuit OND potential
VDD 26 Programming power supply; 2lV during program for the 8748H/8749H; + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AH/8050AH ROM versions.
Vee 40 Main power supply; +5V during operation and during 8748H and 8749H pro-
gramming.
PROG 25 Program pulse; + 18V input pin during 8748H /8749H programming. Output strobe
for 8243 I/O expander.
PIO-PI7 27-34 8-bit quasi-bidirection,aI port. (Inte~nal Pullup= 50KH)
(Port I)
P20-P27 21-24 8-bit quasi-bidirectional port. (Internal Pullup = 50KH)
(Port 2) 35-38
P20-P23 contain the four high order program counter bits during an external pro-
gram memory fetch and serve as a 4-bit I/O expander bus for 8243.
DO-D7 12-19 True bidirectional port which can be, written or read synchronously using the RD.
(BUS) WR strobes. The port can also be statically latched.
Contains the 810w 'order program counter bits during an external program mem-
ory fetch. and receives the addressed instruction under the control of PSEN. Also
, contains the address and data during, an external RAM data store instruction.
, under ,control of ALE, RD, and WR.
TO I Input pin testable using the conditional transfer instructions JTO and JNTO. TO
can be designated as a clock output using ENTO CLK instruction. TO is also used
during programming and sync mode.
TI 39 Input pin testable using the JT I, and JNTI 'instructions. Can be design~ted the
event counter input using the STRT CNT instruction., (See Section 2.10).
IN'f 6 Interrupt input. Initiates an in'terrupt' if interrupt is enabled. Interrupt is disabled
after a reset. (Active low)
Interrupt must remain low for at least 3 machine cycles to ensure proper operation.
--
RD 8 Output strobe activated during a BUS read. Can be used to enable data onto the
BUS from an external device. (Active low)
Used as a Read Strobe to External Data Memory.
RESET 4 Input which is used, to initialize the processor. Also used during EPROM programming
and verification. (Active low) (Internal pullup =80K fi)
WR 10 Output strobe during a BUS write. (Active low) Used llS write strobe to external
data memory.
ALE II Address 'Latch Enable. This signal occurs once during each cycle and is useful as
a clock output.
The negative edge of A LE strobes address into external data and program memory.
1-17
SINGLE COMPONENT MCS®-48 SYSTEM'
lllble 3. 'Pin Description (Continued)
Pin
Designation Number· Function
- -
PSEN 9 Program Store Enable. This output 'occurs only during a fetch to external program
memory. (A~tive low)
SS 5 Single step input cari be used i~ c~njunction with ALE to "single step" the processor
=
through each instruCiion. (Active low) (Internal imllup 300Kn) +12V for sync
modes (See 2.16).
EA 7 External Access input which forces all program memory fetches to reference ex-
ternal memory. Useful for emulation and debug; and essential for testing and pro-
gram verification. (Active high) +12V for8048AH/8049AH/8050AH program
xerification and +18V for 8748H/8749H program verification (Internal pullup =
IOMn on 8048AH/8049AH/8035AHL/8039AHL/8050AH/8040AHL)
XTALI 2 , One side of cryst~1 input for internal oscillator. Also input for external source.
XTAL2 3 Other side of crystal/external source input. ;
'Unless otherwise stated, inputs dO,not have internal pullup resistors. 8048AH, 8748H, 8049AH, 8050AH, 8040AHL
4.0 PROGRAMMING, VERIFYING AND 8748H AND 8749H ERASURE
'ERASING EPROM ,,CHARACTERISTICS
The internal Pmliram Memory of the 8748H and the The erasure characteristics of the 8748H and 8749H are
8749H may be erased and reprogrammed by the user as such that erasure begl.ns'to occur when exposed to light
explained in the following sections. See also the 8748H with wavelengths shorter than approximately 4000 Angs"
and 8749H data sheets. troms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
4.1 ProgrammlngNerlflcatlon 3000-4000A range. Data show that constant exposure to
room level fluorescent: lighting could erase the typical
In brief, the programming process consists of: activating 8748H'and 8749H in approximately 3 years while it would
the program mode, applying an address, latching the ad- take approxima1l1ly I week to cause erasure when exposed
dress, applying data, and applying a programming pulse. to direct sunlight. If the 8748H or 8749H is to be exposed
This programming algorithm applies to both the 8748H to these types, of lighting conditions for extended periods
and 8749H. Each word is programmed completely before of time,' opaque labels should be placed over the 8748H
mOv1-!!g on to the next and is followed by a verificatiQn windo,: to prevent unintentional erasure.
step. The following is a list of the pins used for program~
ming and a descsription of their functions: When erased, bits of the 8748H and 8749H Program Mem-
ory are in the logic "0" state.
Pin Function
XTAL 1 Clock Input (3 to 4 MHz) , ,The 'recommended erasure procedure for the 8748H and
Reset Initialization and Address Latching 8749H is exposure to shortwave ultraviolet light which
Test 0 Selection of Program (OV) or Verify has a wavelength of 2537 Angstroms (A). The integrated
(5V) Mode ' dose (i.e., UV intensitY X exposure time) for erasure
EA Activation of Program/Verify Modes should be, a minimum of 15W-sec/cm2 • The erasure time
BUS Address and Data Input Data' Output with this dosage is approximately IS to 20 minutes'using
During Verify an ultraviolet lamp with a 12000p'w/cm2 power rating.
P20-1 Address Input for 8748H The 8748H ,and 8749H should be placed within one inch
P20-2 Address Input for 8749H from the lamp tubes during erasure. Some lamps have a
Voo Programming Power Supply filter in their tubes ,and this filter should be removed before
PROG Program Pulse Input erasure.
PIO-Pll Tied to ground (8749H only)
1·18
SINGLE COMPONENT MCS-48 SYSTEM
COMBINATION PROGRAMIVERIFY MODE (EPROM. ONLY)
lav /
EA 5V _ _ _ _- J
I--------PROGRAM--------!---VERIFY---!-----PROGRAM-
ITW--
TO
tww-----,---
RESET
tAW+---t-~+- tWA
~ r-~D~AT~A~T~O~BE~~
DBO-DB7 --F - - PROGRAMMED VALID
LAST NEXT
P20-P22 ADDRESS ADDRESS
tVDDWffttvD?H
+21 _ WT
vDD
+5-------------- ------------------------------
PROG+:: ____________ ~:£V____\tt~W: __
+0 -- - - - - - =--,.:-"'. . _---
, VERIFY MODE (ROM/EPROM)
EA
_-oJ/
*TO,
RESET ~'-____________---.JI \ . . . ._ _---JI
DBO-DB7 J-- ADDRESS
(0-7) VALID
__ -< NEXT X
~,__.;..A;;;;D.;;;D.;..R.;;;E,;;,SS;;......J.
I\IEXT DATA)- __ _
. OUT VALID.
P20-P22 ADDRESS (8-10) VALID NEXT ADDRESS VALID
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.E., "" leV).
"TO ON EPROM ONLY.
Figure 17. Pl'9gramlVerify Sequence for 8749H18748H
1·19
MCS®,.48 Expanded System 2
EXPANDED MCS®-48 SYSTEM
1'.0 INTRODUCTION 1) The contents of the 12-bit program counter will be
output on BUS and the lower half of port 2.
If the capabilities resident on the single-chip S04SAHI
2) Address Latch Enable (ALE) will indicate the time at
S74SH/S035AHUS049AH/S749H/S039AHL are not suf- which address is valid. The' trailing edge of ALE is
ficieflt for your system requirements, special on-board cir- used to latch the address externally.
cuitry allows the addition of a wide variety of external
memory, 110, or special peripherals you may require. The 3) Program Store Enable (PSEN) indicates that an exter-
processors can be directly and simply expanded in the nal instruction fetch is in progress and serves to enable
foilowing areas: the external memory device.
• Program Memory to 4K words 4) BUS reverts to input (floating) mode and the processor
accepts its 8-bit contents as im instruction word.
• Data Memory to 320 words (3S4 words with
S049AH)
• 110' by unlimited amount
• Special Functions uSingSOSO/SOS5AH peripherals ALE J L
By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later PSEN
in the chapter. Expansion is accomplished in two ways:
FLOATING
~FLOATINGO FLOATING
1) Expander 110 - A special 110 Expander circuit, the
BUS
S243 , provides for the addition of four 4-bit Input!
Output ports with the sacrifice of only the lower half ADDRESS INSTRUCTION
(4-bits) of port 2 for inter-device communication. Mul-
tiple S243's may be added to this 4-bit bus by gen-
erating the required .. chip select" lines. Figure 1. Instruction Fetch from
2) Standard SOS5 Bus - One port of the S04SAHI External Program Memory
S049AH is like the S-bit bidirectional data bus of the
: SOS5 microcomputer system allowing interface to the All inStruction fetches, including internal addresses, caD. be
numerous standard memories and peripherals of the forced to be external by activating the EA pin of the 8048AH1
MCS@-SO/S5 microcomputer family. 8049AH18050AH. The 8035AHU8039AHUS04OAHL pro-
cessors without program memory always operate in the ex-
MCS-4S systems can be configured using either or both ternal program memory mode (EA = 5V).
of these expansion features to optimize system capabilities
to the application. 2.2 Extended. Program Memory
AddreSSing (Beyond 21<)
Both expander devices and standard memories and pe-
ripherals can be added in virtually any number and com- For programs of 2K words or less, the 8048AH/8049AH
bmation required. addresses program memory in the conventional manner.
, . Addresses beyond 2047 can be reached by executing a
'. 2.0 EXPANSION OF PROGRAM MEMORY program memory bank switch instruction (SEL MBO, SEL
MBI) followed by a branch instruction (JMP or CALL).
Program Memory is expanded beyond the resident IK or The bank switch feature extends the range of branch in-
2K words by using the SOS5 BUS feature of the MCS@- structions beyond their normal 2K range and at the same
48. All program memory fetches from the addresses less time prevents the user from inadvertently crossing the 2K
. than 1024 on the S04SAH and less than 204S on the boundary ..
. S049AH occur internally with no external signals being
generated (except ALE which is always present). At ad- PROGRAM MEMORY BANK SWITCH
dress 1024 on the S04SAH, the processor automatically
initiates external program memory fetches. The switching of 2K program memory banks is accom-
plished by directly setting or resetting the most significant
2.1 Instruction Fetch Cycle (External) bit 'of the program counter (bit 11); see Figure 2. Bit
II is not altered by nQrmal incrementing of the program
As shown in Figure 1, for all insinicti~n fetches from counter but is loaded with the contents of a special flip-
addresses of 1024 (2048) or greater, the following will flop each time a JMP or CALL instruction is executed.
occur: This special flip-flop is set by executing an SEL MBI
2-1
EXPANDED MCS®-48 SYSTEM
instruction and reset by SEL MBO. Therefore, the SEL counter is held at "0" during the interrupt service routine.
MB instruction may be executed at any time prior to the The end of the service routine is signalled by the execution
actiJal bank switch which occurs during the next branch of an RETR instruction. Interrupt service routines should
instruction encountered. Since all twelve bits of the pro- therefore be contained entirely in the lower 2K words of
gram counter; including bit 11, are stored in the. stack, program memory. The execution of a SEL MBO or SEL
when a Call is executed, the user may jump·to subroutines MB I instruction within an interrupt routine is nOt rec-
across the 2K boundary and the proper bank will be re- ommended since it will not alter PCII while in the routine,
stored upon return. However, the bank switch flip-flop but will change the internal flip-flop~
will not' be altered on return.
2.3 Restoring 110 Port Information
,Although the lower half of Port 2 is u~ to output the
IAnIAwl~I~I~I~I~I~I~I~I~I~1
C
four most significant bits of address during an external
Conventional pr~gram Counter
program memory fetch, the 110 information is still oot-
'
• Counts OOOH to 7FFH puted during certain portions of each machine cycle. 110
• Overflows 7FFH to OOOH information is always present on Port 2's lower 4 bits at
JMP or CALL Instructions transfer contents the rising edge of ALE and can be sampled or latched at
ofinternallllpflop.to A11
this time.
• Flipflop set by SEL MB1
• Flipflop reset by SEL MBO
or by RESET
2.4, Expansion Examples
During interrupt service routine
A11 i. forced to "0"
All 12 bits are saved in stack Shown in Figure 3 is the addition· of 2K words of
program memory using an 2716A 2K x 8 ROM to give
a total of 3K words of program mem0!I:...!!!.'this case no
Figure 2. Program Counter chip select decoding is required and PSEN enables the
memory directly through the chip select input. If the sys-
INTERRUPT ROUTINES tem requires only 2K of progra!ll memory, the same con-
figuration can be used with an 803SAHL substituted for
. Interrupts always vector the program counter tO'location the. S04SAH. The 8049AH would provide 4K of program
3 or 7 iii 'the first 2K bank, 'and bit II of the program memory with the same configuration.
II
~.,
8048AH ALE
,74LS373
"
n) ADDRESS
v
A
BUS r'--8
,irV LATCH
DATA
OUT
2718
EPROM
PSEN CiS
.'
USING 2K x 8 EPROM
Figure 3. Expa~ding MCSC!l~48 Program Memory Using Standard Memory Products
2-2
EXPANDED MCS®-48 SYSTEM
Figure 4 shows how the 8755/8355 EPROM/ROM with
lio interfaces directly to the 8048AH without the need
ALE
for an address latch. The 8755/8355 contains an internal
RD 8-bit address latch eliminating the need for an 8212 latch.
In addition to a 2K x 8 program memory. the 8755/8355
lOW 2K x 8 also contains 16 110 lines addres.sable as two 8-bit ports.
8048AH lOR ROMI
EPROM These ports are addressed as external RAM; therefore the
8049AH
WITH 1/0 RD and WR outputs of the 8048AH are required. See the
AlDO_7 8~~1 following section on data memory expansion for more
8755 detail. The subsequent section on 110 expansion explains
the operation of the 16 I/O lines .
.A8-Al0. CS
3.0 EXPANSION OF DATA MEMORY
Data Memory is expanded beyond the resident 64 words
3
by using the 8085AH type bus feature of the MCS®-48.
TEST 1/0 3.1 Read/Write Cycle
INPUTS
All address and data is transferred over the 8 lines of
BUS. As shown in Figure 5, a read or write cycle
Figure 4. External Program Memory Interface occurs as follows:
ALE J. L
I
BUS FLOATING XADDRESSX 7' ~___FL_O_A_TI_N_G_ __
FLOATING
READ FROM EXTERNAL DATA MEMORY
ALE J L
I
BUS FLOATING FLOATING
WRITE TO EXTERNAL DATA MEMORY
Figure 5. External Data Memory Timings
2-3
EXPANDED MCS®-48 SYSTEM
I) The contents of register RO or RI is outputed on BUS. 4.0 EXPANSION OF INPUT/OUTPUT
2) Address Latch Enable (ALE) indicates addre.sss is
valid. The· trailing edge of ALE is used to latch the There are four possible modes of II() expansion with the
address externally. 8048AH: one using a special low-cost expander, the 8243;
another using standard MCS~80/85110 devices; and a third
3) A read (RD) or write (WR) pulse on the corresponding using the combination memory 110 expander devices the
output pms of the 8048AH indicates the type of data 8155, 8355, and 8755. It is also possible to expand using
memory access ~gress. Output data is valid at the standard TTL devices.
trailing edge of WR and input data must be valid at
the trailing edge of RD; ·4.1 I/O Expander Device
4) Oat (8 bits) is transferred in or out over BUS.
The most efficient means of 110 expansion for small sys-
3.2 Addressing External Data Memory tems is the 8243 110 Expander Device which requires only
ExternBI Data Memory is accessed with its own two-cycle 4 port lines (lower half of Port 2) for communication with
move instructions. MOVXA, @R and MOVX@R, A, the 8048AH. The 8243 contains four 4-bit 110 ports which
which transfer 8 bits of data between the accumulator and serve as an extension of the on-chip 110 and are addressed
the external memory location addressed by the. contents . as ports #4-7 (see Figure 13-7). The following operations
of one of the RAM Pointer Registers RO and RI. This may be performed on these ports:
allows 256 locations to be addressed in addition to the
resident locations. Additional pages may be added by' • Transfer Accumulator to Port
"bank switching" with extra output lines of the 8048AH. • Transfer Port to Accumulator·
• AND Accumulator to Port
3.3 Examples of Data Memory Expansion
• OR Accumulator to Port
Figure 6 shows how the 8048-AH can be expanded
using the 8155 memory and 110 expanding device. Since A 4-bit transfer from a port to the lower half of the Ac-
the 8155 has an internal8-bit address latch, it can interface cumulator sets the most significant four bits to zero. All
directly to the 8048AH without the use of an external communication between the 8048AH and the 8243 occurs
latch. The 8155 provides an additional 256 words ofstatic over Port 2 lower (P20-P23) with timing provided by an
data memory and also includes 22 110 lines and a 14-bit output pulse on the PROG pin of the processor. Each trans-
timer. See the following section on 110 expansion and the fer consists of two 4-bit nibbles: The first containing the
8155 data sheet for more details on these additional "op code'.'and port address, and t\le second containing
features. the actual 4 bits of data ..
Busk'------;;8,-----~
v
ADO_7
ALE
"
ALE 8155
22 1/0
256x8
8048AH WR ViR RAM TIMER IN
AD iii> TIMER OUT
PORT 101M
TEST
3
INPUTS
18 1/0
Figure 6. 8048AH Interface to 256 x8 Standard Memories
··2-4
EXPANDED MCS®-48 SYSTEM
fl
-=- CHIP SELECT CONNECTIO NIFMORE
THAN ONE EXPANDER IS USED
~I/O CS
P4 4 1/0
" V or
PROG PROG
A
P5 4 1/0
2
8050AH J i::JTS 8243
v
8049AH
8048AH
" t-.
P6 4 1/0
"- v
P20-P23 4. DATA IN
v P2
" P7 4
v
1/0
EXPANDER INTERFACE
BITS 0, 1 BITS 2, 3
PROG \ ' - . _ _ _- - I/
00}
01 PORT 01
OO} READ
WRITE
10 ADDRESS 10 OR
P20-P23 --<'-___X'-_____),..--- 11 11 AND
ADDRESS DATA (4-BITS)
ANDOPCODE
(4-BITS)
OUTPUT EXPANDER TIMING
Figure 7. 8243 Expander I/O Interface
Nibble I Nibble 2 4.2 1/0 Expansion with Standard
3 2 I 0 3 2 I 0 Peripherals
I I I I IA IA I I did IdId I Standard MCS-80/85 type 110 devices may be added to
the MCSIII>-48 usinl!; the same bus and timinl!; used for Data
Instruction Port data
Code Address
Memory expansion. Figure 8 shows an example of how
an 8048AH can be connected to an MCS-85 peripheral.
II AA 110 devices reside on the Data Memory bus and in the
data memory address space and are accessed with the same
00 Read 00 - Port #4
01 Write 01 - Port #5 MOVX instructions. (See the previous section on data
10 OR 10- Port #6 memory expansion for a description of timing.) The fol-
II AND II-Port#7 lowing are a few 9f the Standard MCS-80 devices which
are very useful in MCSIII>-48 systems:
• 8214 Priority Interrupt Encoder
A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates • 8251 Serial Communications Interface
the presence of data. Additional 8243's may be added to • 8255 General Purpose Programmable 110
the four-bit bus and chip selected using additional output • 8279 Keyboard/Display In~erface
lines from the 8048AH/8748H. • 8254 Interval Timer
1/0 PORT CHARACTERISTICS 4.3 Combination Memory and
110 Expanders
Each of the four4-bit ports of the 8243 can serve as either As mentioned in the sections on program and data memory
input or output and can provide high drive capability in expansion, the 8355/8755 and 8155 expanders also contain
both the high and low state. I/O capability;
2-5
EXPANDED MCS®-48 SYSTEM
8 KEYBOARD
INPUTS
INT INT
P20 c/o
8279
KEYBOARD SCAN
8048AH DISPLAY OUTPUTS
RD RD
(A) DISPLAY
WR WR OUTPUT
DATA (B) DISPLAY
BUS 8
BUS OUTPUT
Cs
-
Figure 8. Keyboard/Display Interface
8355/8755: These two parts of ROM and EPROM equiv- port. These three registers and aControllStatus register
alents and therefore contain the same 110 structure. 110 are accessible as external data memory with the MOVX
eonsists of two 8-bit ports which nonnally reside in the instructions. The contents of the control register deter-
external data memory address space and are accessed with mines the mode of the three ports. The ports can be pro-
MOVX instructions. Associated with each port is an 8- grammed as input or output with or without associated
"it Data Direction Register which defines each bit in the handshake communication lines. In the handshake mode,
port as either an input or an output. The data direction lines of the six-bit port become input and output strobes
registers are directly addressable, thereby allowing the' for the two 8-bit ports. Also included in the 8155 is a
user to define under software control each individual bit 14-bit programmable timer. The clock input to the timer
of the ports as either input or output. All outputs. are and the timer overflow output are available on external
statiCally latched and double buffered. Inputs are not pins. The timer can be programmed to stop on tenninal
latched. count or to continuously reload itself. A square wave or
8155/8156: 110 on the 815518156 is configured 'as two pulse output on terminal count can also be specified.
8-bit programmable 1/0 ports and one 6-bit programmable
Figure 9. Low Cost 110 Expansion
2-6
EXPANDED MCS®-48 SYSTEM
1/0 EXPANSION EXAMPLES Figure 10 shows the 8048AH interface to a standard
MCS®-80 peripheral; in this case, the 8255 Programmable
Figure 9 shows the expansion of 110 using multiple Peripheral Interface, a 40-pin part which provides three
8243's. The only difference from a single 8243 system is 8-bit programmable I/O ports. The 8255 bus interface is
the addition of chip selects provided by additional8048AH typical of programmable MCS®-80 peripherals with an
output lines: Two output liens and a decoder could also 8-bit bidirectional data bus, a RD and WR input for Read/
be used to address the four chips. Large numbers of 8243' s Write control, a CS (chip select) input used to enable the
would require a chip select decoder chip such as the 8205 Read/Write control logic and the address inputs used to
to save I/O pins. select various internal registers.
AD 8255 P20 Ao 8255
A1 PROGRAM- PORT P21 A1 PROGRAM- PORT
MABLE A MABLE A
PERIPHERAL PERIPHERAL
PORT PORT
8048AH ALE INTERFACE 8048AH _ INTERFACE
B
RO B RO RO
PORT WR Wii PORT
C C
BUS 8 00-7
CS CS
OPTION #1 -= OPTION #2 -=
Figure 10. Interface to MCS®-BO Peripherals
Interconnection to the 8048AH is very straightforward addressing of the various memories and 110 ports. Note
with BUS, RD, and WR connecting directly to the cor- that in this configuration address lines A 10 and A 11 have
responding pins on the 8255. The only design consider- been ORed to chip select the 8355. This ensures that the
ation is the way in which the internal registers of the 8255 chip is active for all external program memory fetches in
are to be addressed. If the registers are to be addressed the lK to 3K range and is disabled for all other addresses.
as external data memory using the MOVX instructions, This gating has been added to allow the 110 port of the
the appropriate number of address bits (in this case, 2) 8355 to be used. If the chip was left selected all the time,
must be latched on BUS using ALE as described in the there would be conflict between these ports and the RAM
section on external data memories. If only a single device and I/O of the 8156. The NOR gate could be eliminated
is connected to BUS, the 8255 may be continuously se- and Al1 connected directly to the CE (instead of CE) input
lected by grounding CS. If multiple 8255's are used, ad- ofthe 8355; however, this would create a lK word "hole"
ditional address bits can be latched and used as chip' in the program memory by causing the 8355 to be active
selects. in the 2K and 4K range instead of the normal lK to 3K
range.
A second addressing method eliminates external latches
and chip select decoders by using output port lines as ad- In this system the various locations are addressed as
dress and chip select lines dircctly.r'his method. of follows:'
course, requires the setting oran output port with address • Data RAM - Addresses 0 to 255 when Port 2 Bit
information prior to executing a MOVX instruction. o has been previously set = 1 and Bit I' set = 0
• RAM 110 - Addresses 0 to 3 when Port 2 Bit 0 =
5.0 MULTI-CHIP MCS®-48 SYSTEMS 1 and Bit 1 = 1
Figure 11 shows the addition of two memory expanders • ROM I/O - Addresses 0 to 3 when Port 2 Bit 2 or
Bit 3 = 1
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The mirin consideration in designing such a system is the See the memory map in Figure 12.
2-7
EXPANDED MCS®-48 SYSTEM
8156/8355
A8-10
PORT
83551
8755
ROM
EPROM
PORT
ALE 8 ADO-7
PSEN 101M
8048AH RD
WR -=-
8 PORT
BUS A
PORT
8156 B
RAM
A9 PORT
101M
c
Figure 11. The Three-Component MCS®-48 System
6.0 MEMORY BANK SWITCHING Jumping to subroutines across the boundary should be
avoided when possible since the programmer must keep
Certain systems may require more than the 4K words of track of which bank to return to after completion of the
program memory which are directly addressable by the subroutine. If these subroutines are to be nested and ac-
program counter or more than the 256 data memory and cessed from either bank, a software "stack" should be
110 locations directly addressable by the pointer registers implemented to save the bank switch bit just as if it were
RO and Rl. These systems can be achieved using "bank another bit of the program counter.
switching" techniques. Bank switching is merely the se-
lection of vari()US blocks of "banks" of memory using From a hardware standpoint bank switching is very
dedicated output port lines from the processor. In the case straightforward and involves only the connection of an
of the 8048AH, program memory is selected in blocks of 110 line or lines as bank enable signals. These enables are
4K words at a time, while data memory and 110 are en- ANDed with normal memory and 110 chip select signals
. abled 256 words at a time. to activate the proper bank.
The most important consideration in implementing two or
more banks is the software required to cross the bank 7.0 CONTROL SIGNAL SUMMARY
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output port Table 1 summarizes the instructions which activate the
before accessing memory or 110 in the new bank. If pro- various control outputs of the MCS®-48 processors. Dur-
gram memory is being switched, programs should be or- ing all other' instructions these outputs are driven to the
ganized to keep boundary crossings to a minimum. active state.
2-8
EXPANDED MCS®·48 SYSTEM
Table 1. MCS®-48 Control Signals
The latched mode (INS, OUTL) is intended for use in the
Control single-chip configuration where BUS is not begin used as
Signal When Active an expander port. OUTL and MOVX instructions can be
RD During MOVX, A, @R or INs Bus mixed if necessary. However, a previously latched output
will be· destroyed by executing a MOVX instruction and
WR During MOVX @R, A or OUTL Bus BUS will be left in the high impedance state. INS does
ALE Every Machine Cycle not put the BUS in a high impedance state. Therefore,
PSEN During Fetch of external program mem- the use of MOVX after OUTL to put the BUS in a high
ory (instruction or immediate data) impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the pre-
PROG During MOVD, A,P ANLD P,A MOVD viously latched value).
P,AORLDP,A
OUTL should· never be used in a system with external
8.0 PORT CHARACTERISTICS program memory, since latching BUS can cause the next
instruction, if external, to be fetched improperly.
8.1 BUS Port Operations·
The BUS port can operate in three different modes: as a 8.2 Port 2 Operations
latched 110 port, as a bidirectional bus port, or as a pro-
gram memory address output when external memory is The lower half of Port 2 can be used in three different
used. The BUS port lines are either active high, active ways: as a quasi-bidirectional static port, as an 8243 ex-
low, or high impedance (floating). pander port, and to adddress external program memory.
PROGRAM MEMORY
SPACE
.-----'BFFH
I
I
MB1
:
I
8355 :
(2K) I
I
I
I
I EXTERNAL DATA
: MEMORY SPACE
MBO I - - - - - j 400H I I ~~5
RESIDENT
I
- - - - - - - - 300H
I
I8155
I 10
--(1K)-- 200H I -______---i RESIDENT DATA
MEMORY
- - - - - - - - 100H ~--'-"":""-! (64)
' - - - - - - ' OOOH 1--:-------1
SECTION ADDRESS DESIGNATION
PROG.MEM OOO-BFF
DATAMEM 100-IFF
8155 PORTS 300 CMD/STATUS
301 PORTA
302 PORTB
303 PORTC
304 TIMER LOW
8355 PORTS 305 TIMER HI
400 PORTA
401 PORTB
402 DORA
403 DDR B
Figure 12. Memory Map for Three-Component MCS®-48 Family
2-9
EXPANDED MCSIiil-48 SYSTEM
In all c,ases' outputs are driven low by an active device viously latched will be automatically removed temporarily
and,driven high momentarily by a low impedance device 'while address is present, then retored when the fetch is
and held high bY a high impedan~ device to vee. complete. However, if lower Port 2 is used to commu-
nicate with ,iIIi 8243, previously latched 110 information
The port may contain latched 110 data prjor to its use in , will be removed and not restored. After an input from th~
another mode without affecting operation of either:, If 8243~ P20-3 will be left in the input mode (ftoating).After
lower, ,Port 2 (P20-3) is IIsed ,to output address for an an output to the 8243, P20-3 will contain the value written,
external program memory fetch. the 110 information pre- AN~, or ORed' to the 8243 port.
1/0 1/0
8749H
8049AH'
8048AH
8748H
8035AHL
8039AHL
D
D
Figure 13. MCSC!l~8 Expansion Capability
2·10
MCS®..,48 Instruction Set 3
MCS®-48 INSTRUCTION SET
1.0 INTRODUCTION 1.1 Data Transfers
The MCS®-48 instruction set is extensive for a machine As can be seen in Figure I the 8-bit accumulator is
of its size and has been tailored to be straightforward and the central point for all data transfers within the 8048.
very efficient in its use of program memory. All instruc- Data can be transferred between the 8 registers of each .
tions are either one or two bytes in length and over 80% working register bank and the accumulator directly, Le.,
are only one byte long. Also, all instructions execute in the source or destination register is specified by the in-
either one or two cycles and over 50% of all instructions struction. The remaining locations of the internal RAM
execute in a single cycle. Double cycle instructions in- array are referred to as Data Memory and are addressed
clude all immediate instructions, and all 110 instructions. indirectly via an address stored in either RO or R I of the
active register bank. RO and RI are also used to indirecly
The MCS-48 microcomputers have been designed to han- address external data memory when it is present. Transfers
dle arithmetic operations efficiently in both binary and to and from internal RAM require one cycle; while trans-
BCD as well as handle the single-bit operations required fers to external RAM require two. Constants stored in
in control applications. Special instructions have also been Program Memory can be loaded directly to the accumu-
included to simplify loop counters, table look-up routines, lator and to the 8 working registers. Data can also be
and N-way branch routines. transferred directly between the accumulator and the on-
r----------l
I PROGRAM
MEMORY
DATA
MEMORY
I
I (#DI\.TA) MOV
WORKING REG
I
I ADD
MOV
MOV
ADD
I
MOVP ANL
I MOVP3
ANL
ORL
XRL
I
ORL XCH
XRL
EXPANDER /111-_=---'-', ,....:>"-''----------....:..'-----....:..'-, EXTERNAL
1/0 PORTS /,:=:-=,.-1-"" MEMORY
4-7 ~_ _ _~~_ _~~---~---~~cr-~~r</ ~;~PHERALS
8749H
ANL
ORL 8048AH
8049AH
8748H
8035AHL'
I'NO PROGRAM
8039AHL' I MEMORY
~ _ _ _ _ _ _ --.J
Figure 1. Data Transfer Instructions
3-1
MCS®-48 INSTRUCTION SET
board timer counter or the accumulator and the Program 1.4 Flags
Status word (PSW). Writing to the PSW alters machine
status accordingly and provides a means of restoring status There are four user-accessible flags in the 8048AH: Carry,
after an interrupt or of altering the stack pointer if Auxiliary Carry, FO and F 1. Carry indicates overflow of
necessary. the accumulator, and Auxiliary Carry is used to indiate
overflow between BCD digits and is used during decimal-
1.2 Accumulator Operations adjust operation. Both Carry and Auxiliary Carry are ac-
cessible as part Of the program status word and are stored
Immediate data,. data memory, or the working registers on the stack during subroutines. FO and FI are undedicated
can be added with or without carry to the accumulator. general-purpose flags to be used as tire programmer de-
These sources can also be ANDed, ORed, or Exclusive sires. Both flags can be cleared or complemented and
ORed to the accumulator. Data may be moved to or from tested by conditional jump instructions. FO is also acces-
the accumulator and working registers or data memory. sible via the Program Status word and is stored on the
The two values can also be exchanged in a single stack' with the carry flags.
operation.
1.5 Branch Instructions
In addition, the lower 4 bits of the accumulator can be
exchanged with the lower 4-bits of any of the internal The unconditional jump instruction is two bytes and allows
RAM locations. This instruction, along with an instruction jumps anywhere in the firs! 2K words of program memory.
which swaps the upper and lower 4-bit halves of the ac- Jumps to the second 2K of memory (4K words are directly
cumulator, provides for easy handling of 4-bit quantities, addressable) are made first by executing a select memory
including BCD numbers. To facilitate BCD arithmetic, a bank instruction, then executing the jump instruction. The
Decimal Adjust instruction is included. This instruction 2K boundary can only be crossed via a jump or subroutine
is used to correct the result of the binary addition of two call instruction, i.e., the bank switch does not occur until
2-digit BCD numbers. Performing a decimal adjust on the a jump is executed. Once a memory bank has been selected
result in the accumulator produces the required BCD all subsequent jumps will be to the selected bank until
result. another select memory bank instruction is executed. A
subroutine in the opposite bank can be accessed by a select
Finally, the accumulator can be incremented, decre- memory bank instruction followed by a call instruction.
mented, cleared, or complemented and can be rotated left Upon completion of the subroutine, execution will auto-
or right I bit at a time with or without carry. matically return to the original bank; however, unless the
original bank is reselected, the next jump instruction en-
Although there is no subtract instruction in the 8048AH, countered will again transfer execution to the opposite
this operation can be easily implemented with three single- bank.
byte single-cycle instructions.
Conditional jumps can test the following inputs and ma-
A value may be subtracted from the accumulator with the chine status:
result in the accumulator by:
• TO Input Pin
• Complementing the accumulator • TI Input Pin
• Adding ine vaiue io ine accumuiaior e INT Input Pin
• Complementing the accumulator • Accumulator Zero
• Any bit of Accumulator
1.3 Register Operations • Carry Flag
The working registers can be accessed via the accumulator • FO Flag
as explained above, or can be loaded immediate with • FI Flag
constants from program memory. In addition, they can be
incremented or decremented or used as loop counters using Conditional jumps allow a branch to any address within
the decrement and jump, if not zero instruction, as ex- the current page (256 words) of execution. The conditions
plained under branch instructions. tested are the instantaneous values at the time the con-
ditional jump is executed. For instance, the jump on ac-
All Data Memory including working registers can be ac- cumulator zero instruction tests the accumulator itself, not
cessed with indirect instructions via RO and RI and can an intermediate zero flag.
be incremented.
3-2
MCS®-48 INSTRUCTION SET
The decrement register and jump if not zero instruction The working register bank switch instructions allow the
combines a decrement and a branch instruction to create programmer to immediately substitute a second 8-register
an instruction very useful in implementing a loop counter. working register bank for the one in use. This effectively
This instruction can designate anyone of the 8 working provides 16 working registers or it can be used as a means
registers as a counter and can effect a branch to any address of quickly saving the contents of the registers in response
within the current page of execution. to an interrupt. The user has the option to switch or not
to switch banks on interrupt. However, if the banks are
A single-byte indirect jump instruction allows the program switched, the original bank will be automatically restored
to be vectored to anyone of several different locations upon execution of a return and restore status instruction
based on the contents of the accumulator. The contents at the end of the interrupt service routine.
of the accumulator points to a location in program memory
which contains the jump address. The 8-bit jump address A special instruction enables an internal clock, which is
refers to the current page of execution. This instruction the XTAL frequency divided by three to be output on pin
could be used, for instance, to vector to anyone of several TO. This clock can be used as a general-purpose clock in
routines based on an ASCII character which has been the user's system. This instruction should be used only to
loaded in the accumulator. In this way ASCII key inputs initialize the system since the clock output can be disabled
can be used to initiate various routines. only by application of system reset.
1.6 Subroutines 1.9 Input/Output Instructions
Subroutines are entered by executing a call instruction. Ports 1 and 2 are 8-bit static I/O ports which can be loaded
Calls can be made like unconditional jumps to any address to and from the accumulator. Outputs are statically latched
in a 2K word bank, and jumps across the 2K boundary but inputs are not latched and must be read while inputs
are executed in the same manner. Two separate return are present. In addition, immediate data from program
instructions determine whether or not status (upper 4-bits memory can be ANDed or ORed directly to Port 1 and
of PSW) is restored upon return from the subroutine. Port 2 with the result remaining on the port. This allows
"masks" stored in program memory to selectively set or
The return and restore status instruction also signals the reset individual bits of the I/O ports. Ports 1 and 2 are
end of an interrupt service routine if one has been in configured to allow input on a given pin by first writing
progress. a "1" out to the pin.
1.7 Timer Instructions An 8-bit port called BUS can also be accessed via the
accumulator and can have statically latched outputs as
The 8-bit on board timer/counter can be loaded or read well. It too can have immediate data ANDed or ORed
via the accumulator while the counter is stopped or while directly to its outputs, however, unlike ports I and 2, all
counting. The counter can be started as a timer with an eight lines of BUS must be treated as either input or output
internal clock source or an event counter or timer with an at anyone time. In addition to being a static port, BUS
external clock applied to the Tl input pin. The instruction can be used as a true synchronous bi-directional port using
executed determines which clock source is used. A single the Move External instructions used to access external
instruction stops the counter whether it is operating with data memory. When these instructions are executed, a
an internal or an external clock source. In addition, two corresponding READ or WRITE pulse is generated and
instructions allow the timer interrupt to be enabled or data is valid only at that time. When data is not being
disabled. transferred, BUS is in a high impedance state. Note that
the OUTL, ANL, and the ORL instructions for the BUS
1.8 Control Instructions are for use with internal program memory only.
Two instructions allow the external interrupt source to be. The basic three on-board I/O ports can be expanded via
enabled or disabled. Interrupts are initially disabled and a 4-bit expander bus using half of port 2. I/O expander
are automatically disabled while an interrupt service rou- devices on this bus consist of four 4-bit ports which are
tines is in progress and re-enabled afterward. addressed as ports 4 through 7. These ports have their
own AND and OR instructions like the on-board ports as
There are four memory bank select instructions, two to well as move instructions to transfer data in or out. The
designate the active working register bank and two to expander AND and OR instructions, however, combine
control program memory banks. The operation of the pro- the contents of accumulator with the selected port rather
gram memory bank switch is explained in Section 2.2 than immediate data as is done with the on-board ports.
in the Expandeq MCS-48 System chapter..
3-3
MCS®-48 INSTRUCTION SET
liD devices can also be added externally using the BUS The alphabetical listing includes the following
port as the expansion bus. In .this case the liD ports become information.
"memory mapped", i.e., they are addressed in the same
• Mnemonic
way as external data memory and exist in the external
data memory address space addressed by pointer register • Machine Code
RO or Rl. • Verbal Description
• Symbolic Description
• Assembly Language Example
The machine code is represented with the most significant
2.0 INSTRUCTION SET DESCRIPTION bit (7) to the left and two byte instructions are represented
with the first byte ,on the left.. The assembly language
The following pages describe the MCS®-48 instruction set
examples are formulated as follows:
in detail. The instruction set is first summarized with in-
structions grouped functionally. This summary page is Arbitrary
followed by a detailed description listed alphabetically by Label: Mnemonic, Operand;
mnemo~ic opcode.
Descriptive Comment
3-4
MCS®-48 INSTRUCTION SeT
S04SAH/S74SH/S049AH/S050AH/S749H
Instruction Set Summary
Mnemonic Description Bytes Cycle Mnemonic Description Bytes Cycles
Accumulator Registers
ADD A, R Add register to A 1 1 INCR Increment register 1 1
ADDA,@R Add data memory to A 1 1 INC@R Increment data memory 1 1
ADD A, # data Add immediate to A 2' 2 DECR Decrement register 1 1
AD DC A, R Add register with carry 1 1
Branch
ADDC":-, Add data memory 1 1
@R with carry JMP addr Jump unconditional 2 2
AD DC A, Add immediate 2 2 JMPP@A Jump indirect 1 2
# data with carry DJNZ R, addr Decrement register 2 2
ANLA, R And register to A 1 1 and jump
ANLA,@R And data memory to A 1 1 JC addr Jump on carry = 1 2 2
ANLA, # data And immediate to A 2 2 JNC addr Jump on carry = 0 2 2
ORL A, R Or register to A 1 1 JZ addr Jump on A Zero 2 2
ORLA@R Or data memory to A 1 1 JNZ addr Jump on A not Zero 2 2
ORL A, # data Or immediate to A 2 2 JTO addr Jump on TO =1 2 2
XRL A, R ExClusive Or register 1 1 JNTO addr Jump on TO =0 2 2
toA JT1 addr Jump on T1 =1 2 2
XRLA,@R Exclusive or data 1 1 JNT1 addr Jump on T1 =0 2 2
memory to A JFO addr Jump on FO =1 2 2
XRL, A, # data Exclusive or 2 2 JF1 addr Jump on F1 = 1 2 2
immediate to A
JTF addr Jump on timer flag =1 2 2
INCA Increment A 1 1
JNI addr Jump on INT = 0 2 2
DEC A Decrement A 1 1
JBb addr Jump on Accumulator 2 2
CLRA Clear A 1 1 Bit
CPLA Complement A 1 1
DAA Decimal adjust A 1 1 Subroutine
SWAP A Swap nibbles of A 1 1 CALL addr Jump to subroutine 2 2
RLA Rotate A left 1 1 RET Return 1 2
RLCA Rotate A left 1 1 RETR Return and restore 1 2
through carry status
RRA Rotate A right 1 1
Flags
RRCA Rotate A right 1 1
through carry CLR C Clear Carry 1 1
CPLC Complement Carry 1 1
Input/Output
CLR FO Clear Flag 0 1 1
INA, P Input port to A 1 2 CPL FO Complement Flag 0 1 1
OUTL P, A Output A to port 1 2 CLR F1 Clear Flag 1 1 1
ANL P, # data And immediate to port 2 2 CPL F1 Complement Flag 1 1 1
ORL P, # data Or immediate to port 2 2
"INS A, BUS Input BUS to A 1 2 Data Moves
"OUTL BUS, A Output A to BUS 1 2 MOVA, R Move register to A 1 1
"ANL BUS, And immediate to BUS 2 2 MOVA,@R Move data memory 1 1
# data toA
"ORL BUS, Or immediate to BUS 2 2 MOVA, # data Move immediate to A 2 2
# data MOVR,A Move A to register 1 1
MOVDA, P Input Expander port 1 2 MOV@R,A Move A to data 1 1
toA memory
MOVD P, A Output A to Expander 1 2 MOV R, # data Move immediate 2 2
port to register
ANLD P,A And A to Expander port 1 2 MOV@R, Move immediate to 2 2
ORLD P, A Or A to Expander port 1 2 # data data memory
MOVA, PSW Move PSWtoA 1 1
MOVPSW,A MoveAtoPSW 1 1
Mnemonics copyright Intel Corporation 1983.
"For use with internal memory only.
3-5
MCS®-48 INSTRUCTION SET
804IAH/8741H/1049AH/105OAH/8749H
Instruction Set Summary (Con't)
Mnemonic Description Bytes Cycle Mnemonic' Description Bytes Cycle
Data Moves Control
(Cont'd) ENI Enable external 1 1
XCH A, R Exchange A and 1 1 Interrupt
register .. DISI Disable external 1 1.
XCHA,@R Exchimge A and 1 1 Interrupt
data memory SEL RBO Select register bank 0 1 1
XCHDA,@R, Exchange nibble of.A 1 1 SEL RBl Select register bank 1 1 1
and register , SEL MBO Select memory ban,k 0 1 -1
MOVXA,@R Move external data 1 2 SEL MBl Select memorY,bank 1 1 1
memory to A'
ENTOCLK Enable clock output 1 1
MOVX@R,A Move A to external ' 1 2 onTO
data memory
. MOVPA,@A Move to A from 1 2 NOP No Operation 1 1
current page
MOVP3A,@A Move to A from Page 3 1 2
Timer/Counter
'MOVA, T Read Timer/Counter 1 1
MOVT,A Load Timer/Counter 1 1'
STRTT Start Timer "
1 1
STRTCNT Start Counter 1 1
STOP TCNT Stop Timer/Counter 1 ,1
EN TCNTI Enable Timer/Counter 1 1
Interrupt
DIS TCNTI Disable Timer/Couriter 1 1
Interrupt
Mnemonics copyright Intel Corporation 1983.
3-6
MCS®-48 INSTRUCTION SET
Symbols and Abbreviations Used
A Accumulator
AC Auxiliary Carry
addr 12-Bit Program Memory Address
Bb Bit Designator(b = 0-7)
BS Bank Switch
BUS BUS Port"
C Carry
ClK Clock
, CNT EventCounter
CRR Conversion Result Register
D Mnemonic for 4-Bit Digit (Nibble)
data 8-Bit Number or Expression
DBF Memory Bank Flip-Flop
Fa, F1 Flag 0, Flag 1
I Interrupt
P Mnemonic for "in-page" Operation'
PC Program Counter
Pp Port Designator (p = 1, 2 or' 4-7)
PSW Program Status Word
Ri Data memory Pointer (i = 0, or 1)
Rr Register Designator (r = 0-7)
SP Stack Pointer '
T Timer
TF Timer Flag
TO, T1 Test 0, Test 1
X Mnemonic for External RAM
# Immediate Data Prefix
@ Indirect Address Prefix
$ Currerit Value of Program Counter
(X) Contents of X
((X)) Contents of location Addre~sed QY X
- Is Replaced by ,
Mnemonics copyright Intel Corporatiqn 1983,
3-7
MCS@)-48 INSTRUCTION SET
ADD A'~r Add Register Contents to Accumulator
Encoding: I0 1 1 0 I 1 r r r I .,:
Description: The content~ of r~gister 'r' ,are added to the accllmulator. Carry is
affected.' ' "
Operation: (A) - (A) + (Rr) r =0-7
Example: ADDREG: ADD A,RS ;ADD REG S CONTENTS
;TOACC
ADD A,@R1 Add Data Memory Con~ents ,to Accumulator
Encoding; I0 1 I
1 0 0 0 0 i I SOH-S1H '
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5.... are added to the accumulator. Carry is affected.
Operation: (A) - (A) + ((Ri)) i =0-1 ,
Example: ADDM: MOV RO, #01 FH";MOVE ',1 F' HEX TO REG 0
ADD A, @R~;ADD VALUE OF LOCATION
;3,1,TOACC
ADD A,#data Add Immediate Data, to 'Accumulator
Encoding: I 0 0 00 I 0 0 l' 1 I I d7 dS dS (14 "d3 d2 d1 dO I 03H
Description: This is a 2-cycle instruction. The specified data is added to the accumulator.
Carry is affected. ,,' ," " '
Operation: (A) -(A) + data
Example: ADDID: ADD A,#ADDER;, ;ADD VALUE OF SYMBOL
;ADDER' TO ACC
ADDC A,R r Add Carry and Register Contents to ,Accumulator
Encoding: I0 1 1 1 I 1 r r r I 78H-7FH
Descripiion: The content of the cBiry bit is a~ded to a~cumulator location 0 arid the carry
bit cleared. The contents of register 'r' are then added to the accumulator.
Carry is affected. '
Operation: (A) - (A) + (Rr) + (C) r = 0-7
Example: ADDRGC: ADDC A,'R4; ,;ADD CARRY AND REG 4
;CONTENTS TO ACC
··0-5 iii 8048AHl8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-8
MCS®-48 INSTRUCTION SET
ADDC A,@R,i Add Carry and Data Memory Contents to Accumulator
Encoding: I0 1 1 1 I0 0 0 i I 70H-71H
Description: The content of the carry bit is added to accumulator location a and the carry bit
cleared. Then the contents of the resident data memory location addressed by
register 'i' bits 0-5** are added to the accumulator. Carry is affected.
Operation: (A) - (A) + ((Ai)) + (C) i = 0-1
Example: ADDMC: MOV A1,#40 ;MOVE '40' DEC TO AEG 1
ADDCA,@A1 ;ADD CAAAY AND LOCATION 40
;CONTENTS TO ACC
ADDC A,@data Add Carry and Immediate Data to Accumulator
I
Encoding: 10 0 0 1 0 0 1 1 I Id7 d6 dS d4 Id3 d2 d1 dO I 13H
Description: This is a 2-cycle instruction. The content of the carry bit is added to·
accumulator location 0 and the carry bit cle~red. Then the specified data is
added to the accumulator. Carry is affected.
Operation: (A) - (A) + data + (C)
Example: AD DC A,#22S ;ADD CAAAY AND '22S' DEC
;TO ACC
ANL A,R r Logic~1 AND Accumulator with Register Mask
Encoding: 10 1 0 1 11 r r r I S8H-SFH
Description: Data in the accumulator is logically ANDed with the mask contained in
working register 'r'.
Operation: (A) - (A) AND (Rr) r = 0-7
Example: ANDAEG: ANL A,A3 ;'AND' ACC CONTENTS WITH MASK
;IN REG 3
ANL A,@Rj Logical AND Accumulator with memory Mask
Encoding: I0 1 0 1 I0 0 0 i I SOH-S1H
Description: Data in the accumulator is logically ANDed with the mask contained in the
data memory location referenced by register 'i' bits O-S**.
Operation: (A) - (A) AND ((Ai)) i = 0-1
Example: ANDDM: MOV AO,#03FH ;MOVE '3F' HEX TO AEG 0
ANL A,@AO ;'AND' ACC CONTENTS WITH
;MASK IN LOCATION 63
··0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-9
MCS®-48 INSTRUCTION SET
ANL A,#data Logical AND Accumulator with Immediate Mask
Encoding: [0 1 0 1 1 0 0 1 1 1 53H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ANDed
with an immediately-specified mask.
Operation: (A) - (A) AND data
Examples: ANDID: ANL A,#OAFH ;'AND' ACC CONTENTS
;WITH MASK 10101111
ANL A,#3 + X/Y ;'AND' ACC CONTENTS
;WITH VALUE OF EXP
;'3 + Xy/y'
ANL BUS,#data* Logical AND BUS with Immediate Mask
Encoding: 11 0 0 1 11 0 0 0 1 98H
Description: This is a 2~cycle instruction. Data on the BUS port is logically ANDed .
with an immediately-specified mask. This instruction assumes prior
specification of an 'OUTL BUS, A' instruction.
Operation: (BUS) - (BUS) AND data
Example: ANDBUS: ANL BUS,#MASK ;'AND' BUS CONTENTS
;WITH MASK EQUAL VALUE
;OF SYMBOL 'MASK'
ANL Pp,#data Logical AND Port 1-2 with Immediate Mask
Encoding: 11 0 0 1 11 0 P P 1 99H-9AH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with an
immediately-specified mask. .
Operation: (Pp) - (Pp) AND DATA p = 1-2
C_~ __ I ... IIl\lnO?· AI\II O? Hnl=nl-l
. . A . . . . . . ..., . . . . " I ........ ~. "''1_ I _,"""I VI I ;'AND' PORT 2 CONTENTS
;WITH MASK 'FO' HEX
;(CLEAR P20-23)
• For use with internal program memory ONLY.
MCS®-48 INSTRUCTION SET
ANLD Pp,A Logical AND Port 4-7 with Accumulator Mask
Encoding: 11 0 0 1 11 1 P P I 9CH-9FH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) - (Pp) AND (AO-3) P = 4-7
Note: The mapping of port 'p' to opcode bits 0-1 is as follows:
1 0 Port
00 4
01 5
10 6
11 7
Example: ANDP4: ANLD P4,A ;'AND' PORT 4 CONTENTS
;WITH ACC BITS 0-3
CALL address Subroutine Call
Encoding: Ia10 a9 as 1 I0 1 001 la7 a6 a5 a41 a3 a2 a1 aO I
Page Hex Op Code
o 14
1 34
2 54
3 74
4 94
5 B4
6 04
7 F4
Description: This is a 2-cycle instruction. The program counter and PSW bits 4-7 are
saved in the stack. The stack pointer (PSW bits 0-2) is updated. Program
control is then passed to the location specified by 'address'. PC bit 11 is
determined by the most recent SEL MB instruction.
A CALL cannot begin in locations 2046-2047 or 4094-4095. Execution
continues at the instruction following the CALL upon return from the
subroutine.
Operation: ((SP)) - (PC), (PSW4-7)
(SP) - (SP) + 1
(PCS- 10) - (addrS-10)
( PC O-7) - (addrO_7)
(PC11) - DBF
3-11
MCS®·48 INSTRUCTION SET
Example: Add three groups of two numbers. Put subtotals in locations 50,51 and
total in location 52.
MOV RO,#50 ;MOVE '50' DEC TO ADDRESS
;REGO
BEGADD: MOV A,R1 ;MOVE CONTENTS OF REG 1
;TO ACC
. ADD A,R2 ;ADD REG 2 TO ACC
CALL SUBTOT ;CALL SUBROUTINE'SUBTOr
AD DC A R3 ;ADD REG 3 TO ACC
ADDCA,R4 ;ADD REG 4 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOr
ADDC A,R5 ;ADD .REG 5 TO ACC
ADDCA,R6 ;ADD REG 6 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOr
SUBTOT: MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION ADDRESSED BY
;REGO
INCRO ;INCREMENT REG 0
RET ;RETURN TO MAIN PROGRAM
CLR A Clear Accumul'ator
Encoding: I0 0 1 0 I 0 1 1 1 I 27H
Description: The contents of the accumulator are cleared to zero.
Operation: A - 0
CLR C Clear Carry Bit
Encoding: 11 0 0 1 1 0 1 11 97H
Description: During normal program execution, the carry bit can be set to one by the
ADD, ADDC, RLC, CPL C, RRC, and DAA insructions. This instruction
resets the carry bit to zero.
Operation: C - 0
CLR F1 Clear Flag 1
Encoding: 11 0 1 0 I 0 1 0 1 I . ASH
Description: Flag 1 is cleared, to zero.
Operation: (F1) - 0
3-12
MCS®-48 INSTRUCTION SET
CLR FO Clear Flag 0
Encoding: 11 0 0 0 10 1 0 1 1 85H
Description: Flag 0 is cleared to zero.
Operation: (FO) - 0
CPL A Complement Accumulator
Encoding: 10 0 1 1 10 1 1 1 1 37H
Description: The contents of the accumulator are cort:1plemented. This is strictly a one's
complement. Each one is changed to zero and vice-versa.
Operation: (A) - NOT (A)
Example: Assume accumulator contains 01101010.
CPLA: CPL A ;ACCCONTENTS ARE COMPLE-
;MENTED TO 10010101
CPL C Complement Carry Bit
Encoding: 11 0 1 0 1 0 1 1 1 1 A 7H
Description: The setting of the carry bit is complemented; one is changed to zero, and
zero is changed to one.
Operation: (C) - NOT (C)
Example: Set C to one; current setting is unknown.
CT01: CLR C ;C IS CLEARED TO ZERO
CPL C ;C IS SET TO ONE
CPL FO Complement Flag 0
Encoding: 11 0 0 1 1 0 1 0 11 95H
Description: The setting of flag 0 is complemented; one is changed to zero, and zero is
changed to one. .
Operation: FO - NOT (FO)
CPL F1 Complement Flag 1
Encoding: 11 0 1 1 10 1 0 11 85H
Description: The setting of flag 1 is complemented; one is changed to zero, and zero is
changed to one.
Operation: (F1) - NOT (F1)
3·13
MCS®~48 INSTRUCTION SET
DA A Decimal Adjust Accumulator
Encoding: I0 1 0 1 I0 1 1 1 I 57H
Description: The 8-bit accumulator value is adjusted to form two 4-bit Binary Coded
Decimal (BCD) digits following the binary addition of eCD numbers.
The carry bit C is affected. If the contents of bits 0-3 are greater than nine,
or if AC is one, the accumulator is incremented by six.
The four high-order bits are then checked. If bits 4-7 exceed nine, or if
C is one, these bits are increased by six. If an overflow occurs, C is set
to one.
Example: Assume accumulator contains 10011011.
DA A ;ACC Adjusted to 00000001
;WITH CSET
C AC 7 4 3 0
o 0 100 1 1 011
00000 1 1 0 ADD SIX TO BITS 0-7
o 10100001
o1 1 0 ADD SIX TO BITS 4-7
o 0000000 OVERFLOW TO C
DEC A Decrement Accumulator
Encoding: \ 0 0 0 0 I0 1 1 1 I 07H
Description: The contents of the accumulator are decremented by one. The carry flag
is not affected.
Operation: (A) - (A) -1
Example: Decrement contents of external data memory location 63.
MOV RO,#3FH ;MOVE '3F' HEX TO REG,O
MOVX A, @RO ;MOVE CONTENTS OF;
;LOCATION 63 TO ACC
DEC A ;DECREMENT ACC
MOVX @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 63 IN EXPANDED
;MEMORY
DEC Rr Decrement Register '
Encoding: 11 1 0 0 \1 r r r 1 C8H-CFH
Description: The contents of working register 'r' are decremented by one.
Operation: (Rr) - (Rr) -1 r = 0-7
Example: DECR1: DEC Rl ;DECREMENT CONTENTS OF REG 1
3-14
MCS®-48 INSTRUCTION SET
DIS I External Interrupt
Encoding: I 0 0 0 1 10 1 0 1 1 15H
Description: . External interrupts are disabled. A low signal on the interrupt input pin has
no effect.
DIS TCNTI Disable Timer/Counter Interrupt
I
Encoding: 10 0 1 1 0 1 0 1 1 35H
Description: Timer/counter interrupts are disabled. Any pending timer interrupt request
is cleared. The interrupt sequence is not initiated by an overflow, but the
timer flag is set and time accumulation continues.
DJNZ Rr• address Decrement Register and Test
Encoding: 11 1 1 0 11 r r r 1 E8H-EFH
Description: This is a 2-cycle instruction. Register 'r' is decremented, then tested for
zero. If the register contains all zeros, program control falls through to the
next instruction. If the register contents are not zero, control jumps to the
specified 'address'.
The address in this case must evaluate to 8-bits, that is, the jump must be
to a location within the current 256-location page.
Example: (Rr) - (Rr) -1 .. r =0-7
IfRrnotO
(PCO-7) - addr
Note: A 12-bit address specification does not cause an error if the
DJNZ instruction and the jump target are on the same page. If the DJNZ
instruction begins in location 255 of a page, it must jump to a target
address on the following page.
Example: Increment values in data memory locations 50-54.
MOV RO,#50 ;MOVE '50' DEC TO ADDRESS
;REGO
MOV R3,#5 ;MOVE '5' DEC TO COUNTER
;REG3
INCRT: INC @RO ;INCREMENT CONTENTS OF
;LOCATION ADDRESSED BY
;REGO
INC RO ;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT ;DECREMENT REG 3 - JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT - ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO
3-15
MCS®-48 INSTRUCTION SET
EN I Enable External Interrupt
Encoding: 10 0 0 0 101 0 1 1 05H
Description: External interrupts are enabled. A low signal on the interrupt input pin
initiates the interrupt sequence.
EN TCNTI Enable Timer/Counter Interrupt
I
Encoding: 10 0 1 0 0 1 0 1 I 25H
Description: Timer/counter interrupts are enabled. An overflow of thetimer/counter
initiates the interrupt sequence.
ENTO ClK Enable Clock Output
I
Encoding: 10 1 1 1 0 1 0 1 I 75H
Description: The test 0 pin is enabled to act as the clock output. This function is
disabled by a system reset.
Example: EMTSTO: ENTO ClK ;ENABlE TO AS CLOCK OUTPUT
IN A,Pp Input Port or Data to Accumulator
Encoding: 10 0 0 0 11 0 P pi 09H-OAH
Description: This is a 2-cycle instruction; Data present on port 'p' is
transferred (read) to the accumulator.
Operation: (A) - (Pp) p = 1-2
INP12: IN A,P1 ;INPUT PORT 1 CONTENTS TO ACC
MOVR6,A ;MOVE ACC CONTENTS TO REG 6
INA,P2 ;INPUT PORT 2 CONTENTS TO ACC
MOV R7,A ;MOVE ACC CONTENTS TO REG 7
INC A Increment Accumulator
Encoding: 10 0 0 1 1 0 1 1 11 1.7H
Description: The contents of the accumulator are incremented by one. Carry is not
affected.
Operation. (A) -,.. (A) +1
3-16
MCS®-48 INSTRUCTION SET
Example: Increment contents of location 100 in external data memory.
INCA: MOV RO,#100 ;MOVE '100' DEC TO ADDRESS REG 0
MOVX A,@RO ;MOVE CONTENTS OF LOCATION
;100TO ACC
INC A ;INCREMENT A
MOVX @RO,A ;MOVE ACC CONTENTS TO
;LOCATION 101
INC Rr Increment Register
Encoding: /0 0 0 1 /1 r r r / ' 18H-1 FH
Description: The contents of working register 'r' are incremented by one.
Operation: (Rr) - (Rr) + 1 r = 0-7
Example: INCRO: INC RO ;INCREMENT CONTENTS OF REG 0
INC @R1 Increment Data Memory Location
Encoding: I0 0 0 1 / 0 0 0 i / 10H-11H
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are incremented by one.
Operation: ((Ri)) - ((Ri)) + 1 i = 0-1
Example: INCDM: MOV R1,#03FH ;MOVE ONES TO REG 1
/ INC @R1 ;INCREMENT LOCATION 63
INS A,BUS· Strobed Input of BUS Data to Accumulator
Encoding: 10 0 0 0 /1 0 0 0 I 08H
Description: This is a 2-cycle instruction. Data present on the BUS port is transferred
(read) to the accumulator when the RD pulse is'dropped. (Refer to section
on programming memory expansion for details.)
Operation: (A) - (BUS)
Example: INPBUS: INS A,BUS ;INPUT BUS CONTENTS TO ACC
. • For use with internal program memory ONLY.
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-17
MCS®-48 INSTRUCTION SET
JBb address Jump If Accumulator Bit Is Set
Accumulator Bit Hex Op Code
o 12
1 32
2 52
3 72
4 92
5 B2
6 02
7 F2
Description: This is a 2,-cycle instruction, Control passes to the specified address if
accumulator bit 'b' is set to one.
Operation: b = 0-7
(PCO-7) - addr If Bb = 1
(PC) = (PC) + 2 If Bb =0
Example: JB4IS1: JB4 NEXT ;JUMP TO 'NEXT' ROUTINE'
;IF ACC BIT 4 = 1
JC address Jump If Carry Is Set
Encoding: 11 1 1 1 1 0 1 1 0 1 1a7 a6 a5 a4 1a3 a2 a1 aO 1 F6H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
carry bit is set to one.
Operation: (PCO- 7) - addr If C= 1
(PC) = (PC) + 2 If C = 0
Example: JC1: JC OVFLOW ;JUMP TO 'OVFLOW' ROUTINE
;IF C = 1
JFO address Jump If Flag 0 Is Set
Encoding: 11 0 1 1 I 0 1 1 0 I Ia7 a6 a5 a4·1 a3 a2 a1 aO I B6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 0 is set to one.
Operation: (PC O- 7) - addr If FO = 1
(PC) =(PC) + 2 If FO = 0
Example: JFOIS1: JFO TOTAL ;JUMPTO 'TOTAL' ROUTINE IF FO = 1
3-18
MCS®-48 INSTRUCTION SET
JF1 address Jump If Flag 1 Is Set
Encoding: 10 1 1 1 1 0 1 1 0 1 1a7 a6 a5 a4 1a3 a2 a1 aO 1 76H
Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 1 is set to one.
Operation: (PCO-7) - addr If F1 = 1
(PC) =(PC + 2) If F1 = 0
Example: JF1IS1: JF1 FILBUF ;JUMP TO 'FILBUF'
;ROUTINE IF F1 = 1
JMP address Direct Jump within 2K Block
Encoding: 1a10 a9 a8 01 0 1 0 01
Page Hex Op Code
o 04
1 24
2 44
3 64
4 84
5 A4
6 C4
7 E4
Description: This is a 2-cycle instruction. Bits 0-10 of the program counter are replaced
with the directly-specified address. The setting of PC bit 11 is
determined by the most recent SELECT MB instruction.
Operation: (PC8-10) - addr 8-10
(PCO-7) - addr 0-7
(PC11) - DBF
Example: JMP SUBTOT ;JUMP TO SUBROUTINE 'SUBTOT
JMP $-6 ;JUMP TO INSTRUCTION SIX
;LOCATIONS\BEFORE CURRENT
;LOCATION
JMP 2FH ;JUMP TO ADDRESS '2F' HEX
JMPP @A Indirect Jump within Page
Encoding: 11 0 1 1 10 0 1 1 I B3H
Description: This is a 2-cyc!e insruction. The contents of the program memory location
pointed to by the accumulator are substituted for the 'page' portion of the
program counter (PC bits 0-7).
3-19
MCS®-48 INSTRUCTION SET
Operation: (PCO-7) - «A))
Example: Assume accumulator contains OFH.
JMPPAG: JMPP@A ;JUMP TO ADDRESS STORED IN
;LOCATION 151N CURRENT PAGE
JNC address Jump If Carry Is Not Set
Encoding: 11 1 1.0 1 0 1 1 0 1 ESH
Description: This is a 2-cycle instruction. Controi passes to the specified address if
the carry bit is not set, that is, equals zero.
Operation: (PCO-7) - addr If C = 0
(PC) = (PC) + 2 If C = 1
Example: JCO: JNC NOVFLO ;JUMP TO 'NOVFLO' ROUTINE
;IF C = 0
JNI address Jump If Interrupt Input Is Low
Encoding: 11 0 0 0.1 0 1 1 0 1 1a7 as a5 a4 1 a3 a2 a1 aO 1 8SH
Description: This is a 2-cycle instruction. Control passes to the specified address if the
interrupt input signal is low (= 0), that is, an external interrupt has been
signaled. (This signal initiates an interrupt service sequence if the external
interrupt is enabled.)
Operation: (PCO-7) - addr If 1= 0
(PC) = (PC) + 2 If I = 1
Example: 'LOC 3: JNI EXTINT ;JUMP TO 'EXTINT' ROUTINE
;IF I = 0
JNTO address Jump If Test 0 is Low
Encoding: I0 0 1 0 I0 1 1 0 I Ia7
I '
at::U a"
...,
aA
---y
I a<t
I """
a?
-
a1. an- I
I
2SH
Description: This is a 2.,.cycle instruction. Control passes to the specified address, if the
test O' signal is low.
Operation: (PC O- 7) - addr IfTO = 0
(PC) = (PC) + 2 If TO = 1
Example: JTOLOW: JNTO SO ;JUMP TO LOCATION SO DEC
;IF TO = 0
3-20
MCS®-48 INSTRUCTION SET
JNT1 address Jump If Test 1 Is Low
Encoding: I0 1 0 0 I0 1 1 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO I 46H
Description: This is a 2-cycle instruction. Control passes to the specified address, if
the test 1 signal is low.
Operation: (PCO-7) - addr If T1 =0
(PC) = (PC) + 2 IfT1 =1
JNZ Address Jump If Accumulator Is Not Zero
Encoding: 11 0 0 1 1 0 1 1 0 I 1a7 a6 a5 a4 1a3 a2 a1 aO 1 96H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
accumulator contents are nonzero at the time this instruction is executed.
Operation: (PC O- 7) - addr IfA¢ 0
(PC) = (PC) + 2 If A = 0
Example: JACCNO: JNZ OABH ;JUMP TO LOCATION 'AB' HEX
;IF ACC VALUE IS NONZERO
JTF address Jump If Timer Flag Is Set
Encoding: I0 0 0 1 I 0 1 1 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO I 16H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
timer flag is set to one, that is, the timer/counter register has overflowed.
Testing the timer flag resets it to zero. (This overflow initiates an interrupt
service sequence if the timer-overflow interrupt is enabled.)
Operation: (PCO":7)- addr If TF = 1
(PC) = (PC) + 2 . If TF =0
Example: JTF1: JTF TIMER ;JUMP TO 'TIMER' ROUTINE
;IF TF = 1
JTO address Jump If Test 0 Is High
I
Encoding: 10 0 1 1 0 1 1 01 1a7 a6 a5 a41 a3 a2 a1 aO 1 36H
Description: This is a 2-cycle instruction. Control passes to t~e specified address if
the test 0 signal is high (= 1).
Operation: (PCO-7) - addr If TO = 1
(PC) = (PC) + 2 If TO =0
Example: JTOHI: JTO 53 ;JUMP TO LOCATION 53 DEC
;IF TO = 1
3-21
MCS®-48 INSTRUCTION SET
JT1 address Jump If Test 1 Is High
Encoding: 1 0 1 0 1 1 0 1 1 0 1 56H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
test 1 signal is high (= 1).
Operation: (PC O- 7) - addr IfT1 = 1
(PC) = (PC) + 2 IfT1 = 0
Example: JT1 HI: JT1 COUNT ;JUMP TO 'COUNT' ROUTINE
;IF T1 = 1
JZ address Jump If Accumulator Is Zero
Encoding: 11 .1 0 0 1 0 1·1 0 1 1a7 a 6 a5 a4\ a3 a2 a1 aO I C6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the accumulator contains all zeros at the time this instruction is executed.
Operation: (PCO-7) - addr If A = O. .
(PC) = (PC) + 2 If A# 1
Example: JACCO: JZ OA3H ;JUMP TO LOCATION 'A3' HEX
;IF ACC VALUE ISZERO
MOV A,#data Move Immediate Data to Accumulator
, Encoding: 1 0 0 1 0 I0 0 1 1 I 23H
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is loaded
in the accumulator.
Operation: (A) - data
Example: MOV A,#OA3H ;MOVE 'A3' HEX TO ACe
MOV A,PSW Move PSW Contents to Accumulator
Encoding: 11 1 0 0 I0 1 1 1 I C7H
Description: The contents of the program status word are moved tothe accumulator.
Operation: (A) - (PSW)
Example: Jump to 'RB1SET' routine if PSW bank switch, bit 4, is set .
. BSCHK: MOV A,PSW ;MOVE PSW CONTENTS TO ACC
JB4 RB1SET ;JUMP TO 'RB1SET' IF Acc BIT 4 = 1
3-22
MCS®-48 INSTRUCTION SET
MOV A,R r Move Register Contents to Accumulator .
Encoding: 11 1 1 1 11 r r r 1 F8H-FFH
Description: 8-bits of data are removed from working register 'r' into the accumulator.
Operation: (A) - (Rr) r = 0-7
Example: MAR: MOV A,R3 ;MOVE CONTENTS OF REG 3 TO ACC
MOV A,@Ri Move Data Memory Contents to Accumulator
Encoding 11 1 1 1 10 0 0 i I FOH-F1H
Description: The contents of the resident data memory location addressed by bits 0-5** of
register 'i' are moved to the accumulator. Register 'i' contents are unaffected.
Operation: (A) - ((Ri)) i = 0-1
Example: Assume R1 contains 00110110.
MADM: MOV A,@R1 ;MOVE CONTENTS OF DATA MEM
;LOCATION 54 TO ACC
MOV A,T Move Timer/Counter Contents to Accumulator
Encoding: I0 1 0 0 1 0 0 1 0 I 42H
Description: The contents of the timer/event-counter register are moved to the
accumulator.
Operation: (A) - (T)
Example: Jump to "EXIT" routine when timer reaches '64', that is, when bit 6 set-
assuming initialization 64,
TIMCHK: MOV A,T ;MOVE TIMER CONTENTS TO ACC
JB6 EXIT ;JUMP TO 'EXIT' IF ACC BIT 6 = 1
MOV PSW,A Move Accumulator Contents to PSW
I
Encoding: 11 1 0 1 0 1 1 1 I D7H
Description: The contents of the accumulator are moved into the progam status word.
All condition bits and the stack.pointer are affected by this move.
Operation: (PSW) - (A)
Example: Move up stack pointer by two memory locations, that is, increment the
pointer by one.
INCPTR: MOV A,PSW ;MOVE PSW CONTENTS TO ACC
INC A ;INCREMENT ACC BY ONE
MOV PSW,A ;MOVE ACC CONTENTS TO PSW
··0-5 in B04BAH/B74BH
0-6 in B049AH/B749H
0-7 in B050AH
3-23
MCS®~48 INSTRUCTION SET
MOV Rr,A Move Accumulator Contents to Register
Encoding: 11 0 1 0 11 r r r 1 A8H-AFH
Description: The contents of the accumulator are moved to register 'r'.
Operation: (Rr) - (A) r = 0-7
Example: MRA: MOV RO,A ;MOVE CONTENTS OF ACC TO REG 0
MOV Rr,#data Move Immediate Data to Register
B8H-BFH
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved to
register'r'.
Operation: (Rr) - data r = 0-7
Examples: MIR4: MOV R4,#HEXTEN ;THE VALUE OF THE SYMBOL
;'HEXTEN' IS MOVED INTO REG 4
MIR 5: MOV R5,#PI*(R*R) ;THE VALUE OF THE EXPRESSION
;'PI*(R*R)' IS MOVED INTO REG 5
MIR 6: MOV R6, #OADH ;'AD' HEX IS MOVED INTO REG 6
MOV @ RI,A' Move Accumulator Contents to Data Memory
Encoding: 11 0 1 0 10 0 0 i 1 AOH-A1H
Description: The contents of the accumulator are moved to the resident data memory
location whose address is specified by bits 0-5** of register 'i'. Register 'i'
contents are unaffected.
Operation: ((Ri)) - (A) i = 0-1
Example: Assume RO.contains 00000111.
MDMA: MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 7 (REG 7)
MOV @ Rj,#data Move Immediate Data to Data memory
Encoding: 11 0 1 1 1 0 0 0 i l l d7 d6 d5 d4 1 d3 d2 d1 dO 1 BOH-B1H
Description: This is a 2-cycle instruction. The 8-bit value specifi~d by 'data' is moved
to the resident data memory location addressed by register 'i', bits 0-5**.
Operation: ((Ri)) - data i = 0-1
Examples: Move the hexadecimal value AC3F to locations 62-63.
MIDM: MOV RO,#62 ;MOVE '62' DEC TO AD DR REG 0
MOV @RO,#OACH ;MOVE 'AC' HEX TO LOCATION 62
INC.RO ;INCREMENT REG 0 to '63'
MOV @RO,#3FH ;MOVE '3F' HEKTO LOCATION 63
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-24
MCS®-48 INSTRUCTION SET
MOV T,A Move Accumulator Contents to Timer/Counter
Encoding: I 0 1 1 0 10 0 10 1 62H
Description: The contents of the accumulator are moved to the timer/event-counter
register.
Operation: (T) - (A)
Example: Initialize and start event counter.
INITEC: CLR A ;CLEAR ACC TO ZEROS
MOVT,A ;MOVE ZEROS TO EVENT COUNTER
START CNT ;START COUNTER
MOVD A,Pp Move Port 4-7 Data to Accumulator
Encoding: 10 0 0 0 11 1 P P 1 OCH-OFH
Description: This is a 2-cycle instruction. Data on 8243 port 'p' is moved (read) to
accumulator bits 0-3. Accumulator bits 4-7 are zeroed.
Operation: (0-3) - (Pp) p = 4-7
(4-7) - 0
Note: Bits 0-7 of the opcode are used to represent ports 4-7. If you are
coding in binary rather than assembly language, the mapping is as
follows:
Bits 1 0 Port
00 4
01 S
106
11 7
Example: INPPTS: MOVD A,PS ;MOVE PORT S DATA TO ACC
;BITS 0-3, ZERO ACC BITS 4-7
MOVD Pp,A Move Accumulator Data to Port 4-7
Encoding: I0 0 1 1 11 1 P p 1 3CH-3FH
Descripiion: This is a 2-cycle instruction. Data in accumulator bits 0-3 is moved
(written) to 8243 port 'p'.. Accumulator bits 4-7 are unaffected. (See NOTE
above regarding port mapping.)
Operation: (Pp) - (AO-3) P =4-7
Example: Move data in accumulator to ports 4 and S.
OUTP4S: MOVD P4,A ;MOVE ACC BITS 0-3 TO PORT 4
SWAP A ;EXCHANGE ACC BITS 0-3 and 4-7
MOVD PS,A ;MOVE ACC BITS 0-3 TO PORT S
3-25
MCS®-48 INSTRUCTION SET
MOVP A,@A Move Current Page Data to Accumulator
Encoding: 11 a 1 a 1a a 1 11 A3H
Description: The contents of the program memory location addressed by the
accumulator are moved to the accumulator. Only bits 0-7 of the program
counter are affected, limiting the program memory reference to the
current page. The program counter is restored following this operation.
Operation: (PCO.-7) - (A)
(A) - ((PC))
Note:· This is a 1-byte, 2-cycle instruction. If it appears in location 255 of a
program memory page, @A addresses a location in the following page.
Example: MOV12S: MOV A,#12S ;MOVE '12S' DEC TO ACC
MOVPA,@A ;CONTENTS OF 129th LOCATION IN
;CURRENT PAGE ARE MOVED TO ACC
MOVP3 A,@A Move Page 3 Data to Accumulator
Encoding: 11 1 1 a 1a a 1 11 E3H
Description: This is a 2-cycle instruction. The contents of the· program memory location
(within page 3) addressed by the accumulator are moved to the
accumulator. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(PCS-11) - 0011
(A) - ((PC))
Example: Look up ASCII equivalent of hexadecimal code in table contained at the
beginning of page 3. Note that ASCII characters are designated by a
7-bit code; the eighth bit is always reset.
TABSCH: MOV A,#OBSH ;MOVE 'BS' HEX TO ACC (10111000)
ANL A,#7FH ;LOGICAL AND ACC TO MASK BIT
;7 (00111000)
MOVP3 A,@A ;MOVE CONTENTS OF LOCATION '3S'
;HEX IN PAGE 3 TO ACC (ASCII'S')
Access contents of location in page 3 labelled TAB1.
Assume current program location is not in page 3.
TABSCH: MOV A,#LOW TAB 1 ;ISOLATE BITS 0-7 OF LABEL
;ADDRESS VALUE
MOVP3 A,@A ;MOVE CONTENTS OF PAGE 3
;LOCATION LABELED 'TAB1' TO ACC
3-26
MCS®-48 INSTRUCTION SET
MOVX A,@Ri Move External-Data-Memory Contents to Accumulator
Encoding: 11 0 0 0 1 0 0 0 i 1 80H-81H
Description: This is a 2-cycle instruction. The contents of the external data memory
location addressed by register 'i' are moved to the accumulator. Register 'i'
contents are unaffected. A read pulse is generated.
Operation: (A) +- ((Ri)) i = 0-1
Example: Assume R1 contains 01110110.
MAXDM: MOVX A,@R1 ;MOVE CONTENTS OF LOCATION
;118 TO ACC
MOVX @Rj,A Move Accumulator Contents to External Data Memory
Encoding: 11 0 0·1 1 0 0 0 i 1 90H-91H
Description: This is a 2-cycle instruction. The contents of the accumulator are moved to
the external data memory location addressed by register 'i'. Register 'i'
contents are unaffected. A write pulse is generated.
Operation: ((Ri)) +- A i = 0-1
Example: Assu me RO contai ns 11000111.
MXDMA: MOVX @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 1991N EXPANDED
;DATA MEMORY
NOP The NOP Instruction
Encoding: 10 0 0 0 1 0 0 0 0 1 OOH
Description: No operation is performed. Execution continues with the following
instruction.
ORL A,R r Logical OR Accumulator With Register Mask
Encoding: 10 1 0 0 11 r r r 1 48H-4FH
Description: Data in the accumulator is logically ORed with the mask contained in
working register 'r'.
Operation: (A) +- (A) OR (Rr) r = 0-7
Example: ORREG: ORL A,R4 ;'OR' ACC CONTENTS WITH
;MASK IN REG 4
3-27
MCS®-48 INSTRUCTION SET
ORL A,@RI· Logical OR Accumulator With Memory Mask
Encoding: 10 1 0 0 10 0 0 i I 40H-41H
Description: Data in the accumulator is logically ORed with the mask contained in the
. resident data memory location referenced by register "i", bits 0-:-5**,
Operation: (A) - (A) OR ((Ri)) i = 0-1
Example: ORDM: MOV RO,#3FH ;MOVE '3F' HEX TO REG 0
ORL A,@RO ;'OR' AC CONTENTS WITH MASK
;IN LOCATION 63
ORL A,#data Logical OR Accumulator With Immediate Mask
Encoding: 10 1 0 0 10 0 1 1 1 1d7 d6 d5 d4 1 d3 d2 d1 dO 1 43H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ORed with
an immediately-specified mask.
Operation: (A) - (A) OR data
Example: ORID: ORL A,#'X' ;'OR' ACC CONTENTS WITH MASK
;01011000 (ASCII VALUE OF 'X')
ORL BUS,#data* Logical OR BUS With Immediate Mask
Encoding: 1.1 0 0 0 11. 0 0 0 I 88H
Description: This is a 2-cycle instruction. Data on the BUS port is logically ORed with an
immediately-specified mask. This instruction assumes prior specification
on an 'OUTL BUS,A' instruction.
Operation: (BUS) - (BUS) OR data
Example: ORBUS: ORL ~US,#HEXMSK :'OR' BUS CONTENTS WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXMSK'
ORL Pp, #data Logical OR Port lor 2 With immediate Mask
Encoding: 11 0 0 0 11 O. P pi Id7 d6 d5 d4 1 d3 d2 d1 dO 1 89H-8AH
'Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with an
immediately-specified mask.
Operation: (Pp) - (P'p) OR data p = 1-2
Example: ORP1: ORL P1, #OFFH ;'OR' PORT 1 CONTENTS WITH MASK
;'FF' HEX (SET PORT 1 TO ALL ONES)
* For use with internal program memory ONLY,
** 0-5 in 8048AH/874BH
0-6 in 8049AH/8749H
0-7 in 8050AH
3-28
MCS®-48 INSTRUCTION SET
ORlD Pp,A logical OR Port 4-7 With Accumulator Mask
Encoding: 11 0 0 0 11 1 P P 1 8CH-8FH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with the
digit mask contained in accumulator bits 0-3. .
Operation: (Pp) - (Pp) OR (AO-3) p = 4-7
Example: ORP7: ORlD P7,A ;'OR' PORT 7 CONTENTS WITH ACC
;BITS 0-3
OUTl BUS,A· Output Accumulator Data to BUS
Encoding: 10 0 0 0 1 0 0 1 0 1 02H
Description: This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to the BUS port and
latched. The latched data remains valid until altered by
another OUTl instruction. Any other instructiol'] requiring
use of the BUS port (except INS) destroys the contents of
the BUS latch. This includes expanded memory operations
(such as the MOVX instruction). logical operations on
BUS data (AND, OR) assume the OUTl BUS,A instruction
has been issued previously.
Operation: (BUS) - (A)
Example: OUTlBP: OUTl BUS, A ;OUTPUT ACC CONTENTS TO BUS
OUTl Pp,A Output Accumulator Data to Port 1 or 2
Encoding: I0 0 1 1 11 0 P pi 39H-3AH
Description: This is a 2-cycle instruction. Data residing in the accumulator is transferred
(written) to port 'p' and latched.
Operation: (Pp) - (A) p = 1-2
Example: OUTlP: MOV A,R7 ;MOVE REG 7 CONTENTS TO ACC
OUTl P2,A ;OUTPUT ACC CONTENTS TO PORT 2
MOVA, R6 ;MOV REG 6 CONTENTS TO ACC
OUTl P1,A ;OUTPUT ACC CONTENTS TO PORT 1
• For use with internal program memory ONLY.
3-29
MCS®-48 INSTRUCTION SET
RET Return Without PSW Restore
Encoding: 11 0 0 0 1 0 0 1 1/ 83H
Description: This is a.2-cycle instruction. The .stack pointer (pSW bits 0-2) is
decremented. The program counter is. then restored from the stack. PSW
bits 4-7 are not restored. .
Operation: (SP) - (SP)-1
(PC) -((SP»
RETR Return with PSW Restore
Encoding: 11 0 0 1 1 0 0 1 11 93H
Description: This is a 2-cycle instruction. The stack pointer is decremented. The
program counter .and bits 4-7 of the PSW are then restored from the stack.
Note that RETR should be used to return from an interrupt, .but should
not be used within the interrupt service routine as it signals the end of an
interrupt routine by resetting the Interrupt in Progress flip-flop.
Operation: (SP) - (SP)-1
(PC) - ((SP»
(PSW 4,..7) - .((SP})
3-30
MCS®-48 INSTRUCTION SET
RL A Rotate Left without Carry
Encoding: 11 1 1 0 1 0 1 1 1 1 E7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 is rotated
into the bit 0 position.
Operation: (An + 1) - (An)
(AO) - (A7) n = 0-6
Example: Assume accumulator contains 10110001.
RLNC: RL A ;NEW ACC CONTENTS ARE 01100011
RLC A Rotate Left through Carry
Encoding: 11 1 1 1 1 0 1 1 1 1 F7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 replaces the
carry bit; the carry bit is rotated into the bit 0 position.
Operation: (An + 1) - (An)
n = 0-6
(AO)- (C)
(C)-(A7)
Example: Assume accumulator contains a 'signed' number; isolate sign without
changing value
RL TC: CLR C ;CLEAR CARRY TO ZERO
RLC A ;ROTATE ACC LEFT, SIGN
;BIT(7) IS PLACED IN CARRY
RR A ;ROTATE ACC RIGHT - VALUE
;(BITS 0-6) IS RESTORED,
;CARRY UNCHANGED, BIT 7
;ISZERO
RR A Rotate Right without Carry
Encoding: 10 1 1 1 1 0 1 1 1 1 77H
Description: The contents of the accumulator are rotated right one bit. Bit 0 is rotated
into the bit 7 position.
Operation: (An) - (An + 1) n =0-6
(A7) - (AO)
Example: Assume accumulator contains 10110001.
RRNC: RR A ;NEW ACC CONTENTS ARE 11011000
3-31
MCS®-48 INSTRUCTION SET
RRC A Rotate Right through Carry
Encoding: 10 1 1 0 10 1 1 1 1 67H
Description: The contents of the accumulator are rotated right one bit. Bit 0 replaces the
carry bit; the carry bit is rotated into the bit 7 position.
Operation: (An) +- (An + 1) n = 0~6
(A7) +- (C)
(C) +- (AO)
Example: Assume carry is not set and accumulator contains 10110001.
RRTC: RRC A ;CARRY IS SET AND ACC
;CONTAINS 01011000
SEL MBO Select Memory Bank 0
Encoding: 11 1 1 0 1 0 1 0 1 1 E5H
Description: PC bit 11 is set to zero on next JMP or CALL instruction. All references to
program memory addresses fall within the range 0-2047.
Operation: (OBF) +- 0
Example: Assume program counter contains 834 Hex.
SEL MBO ;SELECT MEMORY BANK 0
JMP $+20 ;JUMP TO LOCATION 58 HEX
SEL MB1 Select Memory Bank 1
Encoding: 11 1 1 1 1 0 1 0 1 1 F5H
Description: PC bit 11 is set to one on next JMP or CALL instruction. All references to
program memory addresses fall within the range 2048-4095.
Operation: (OBF) - 1
3-32
MCS®-48 INSTRUCTION SET
SEL RBO Select Register Bank 0
Encoding: 11 1 0 0 10 1 0 1 I C5H
Description: PSW bit 4 is set to zero. References to working registers 0-7 address data
memory locations 0-7. This is the recommended setting for normal
program execution.
Operation: (BS) - 0
SEL RB1 Select Register Bank 1
Encoding: 11 1 0 1 I0 1 0 1 I D5H
Description: PSW bit 4 is set to one. References to working registers 0-7 address data
memory locations 24-31. This is the recommended setting for interrupt service
routines, since locations 0-7 are left intact. The setting of PSW bit 4 in
effect at the time of an interrupt is restored by the RETR instruction when
the interrupt service routine is completed.
Operation: (BS) - 1
Example: Assume an external interrupt has occurred, control has passed to program
memory location 3, and PSW bit 4 was zero before the interrupt.
Operation: LOC3: JNI INIT ;JUMP TO ROUTINE 'INIT' IF
;INTERRUPT INPUT IS ZERO
INIT: MOV R7,A ;MOVE ACC CONTENTS TO
;LOCATION 7
SEL RB1 ;SELECT REG BANK 1
MOV R7,#OFAH ;MOVE 'FA' HEX TO LOCATION 31
SEL RBO ;SELECT RE~ BANK 0
MOV A,R7 ;RESTORE ACC FROM LOCATION 7
RETR ;RETURN - RESTORE PC AND PSW
STOP TCNT Stop Timer/Event-Counter·
Encoding: I0 1 1 0 I O. 1 0 1 I 65H
Description: This instruction is used to stop both time accumulation and event counting.
3-33
MCS®-48 INSTRUCTION SET
Example: Disable interrupt, but jump to interrupt routine after eight overflows and
stop timer. Count overflows in register 7.
START: DIS TCNTI ;DISABLE TIMJ;:R INTERRUPT'
CLRA ;CLEAR ACC TO ZEROS
MOVT,A ;MOVE ZEROS TO TIMER
MOV R7,A ;MOVE ZEROS TO REG 7
STRTT ;START TIMER
MAIN: JTF COUNT ;JUMP TO ROUTINE 'COUNT'
;IF TF = 1 AND CLEAR TIMER FLAG
JMP MAIN ;CLOSE LOOP
COUNT: INC R7 ;INCREMENT REG 7
MOVA,R7 ;MOVE REG 7 CONTENTS TO ACC
JB31NT ;JUMP TO ROUTINE 'INT' IF ACC
;BIT 3 IS SET (REG 7 = 8)
JMP MAIN ;OTHERWISE RETURN TO ROUTINE
;MAIN
INT: STOP TCNT ;STOP TIMER
JMP7H ;JUMP TO LOCATION 7 (TIMER)
;INTERRUPT ROUTINE
STRT CNT Start Event Conter
Encoding: 10 1 0 0 I0 1 0 1 I 45H
Description: The test 1 (T1) pin is enabled as the event-counter input and the counter
is started. The event-counter register is incremented with each high-to-Iow
transition on the Ti pin.
Example: Initialize and start event counter. Assume overflow is desired with first T1
input.
STARTC: EN TCNTI .;ENABLE COUNTER INTERRUPT
MOV A,#OFFH ;MOVE 'FF'HEX (ONES) TO ACC
MOV T,A ;MOVES ONES TO COUNTER
STRTCNT ~ENABLET1ASCOUNTER
;INPUT AND START
3-34
MCS®-48 INSTRUCTION SET
STRT T Start Timer
Encoding: Ia 1 a 1 I a 1 a 1 I 55H
Description: Timer accumulation is initiated in the timer register. The register is
incremented every 32 instruction cycles. The prescaler which counts the
32 cycles is cleared but the timer register is not.
Example: Initialize and start timer.
STARTT: CLR A ;CLEAR ACC TO ZEROS
MOVT,A ;MOVE ZEROS TO TIMER
EN TCNTI ;ENABLE TIMER INTERRUPT
STRTT ;START TIMER
SWAP A Swap Nibbles within Accumulator
Encoding: 10 1 a a 1a 1 1 11 47H
Description: Bits 0-3 of the accumulator are swapped with bits 4-7 of the accumulator.
Operation: (A4-7)!:; (AO-3)
Example: Pack bits 0-3 of locations 50-51 into location 50.
PCKDIG: MOV RO, #50 :MOVE '50' DEC TO REG a
MOV R1, #51 ;MOVE '51' DEC TO REG 1
XCHD A,@RO ;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 50
SWAP A ;SWAP BITS 0-3 AND 4-7 OF ACC
XCHD A,@R1 ;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 51
MOV @RO,A ;MOVE CONTENTS OF ACC TO
;LOCATION 50
XCH A,R r Exchange Accumulator-Register Contents
Encoding: 1a a 1 0 11 r r r J 28H-2FH
Description: The contents of the accumulator and the contents of working register 'r'
are exchanged.
Operation: (A)!:; (Rr) r = 0-7
Example: Move PSW contents to Reg 7 withol:Jt losing accumulator contents.
XCHAR7: XCH A,R7 ;EXCHANGE CONTENTS OF REG 7
;AND ACC
MOV A, PSW ;MOVE PSW CONTENTS TO ACC
XCH A,R7 ;EXCHANGE CONTENTS OF REG 7
'AND ACC AGAIN
3·35
MCS~-48 INSTRUCTION SET
XCH A,@Ri Exchange Accumulator, and Data Memory Contents
Encoding: 10 0 1 0 10 0 0 i 1 20H-21H
Descripti.on: The contents of the accumulator and the contents of the resident data
memory location addressed by bits 0-5** of register 'i' are exchanged.
Register 'i' contents are unaffected. '
Operation: (A) ~ ((Ri)) i = 0-1
Example: Decrement contents of location 52.
DEC52: MOV RO,#52 ;MOVE '52' DEC TO ADDRESS REG 0
XCH A,@RO ;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52
DECA ;DECREMENT ACC CONTENTS
XCH A,@RO ;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52 AGAIN
XCHD A,@Ri Exchange Accumulator and Data Memory 4-Bit Data
Encoding: 10 0 1 1 1 0 0 0 i 1 30H-31H
Description: This instruction exchanges bits 0-3 oUhe accumulator with bits 0-3 of
the data memory location addressed by bits 0-5** of register 'i'. Bits 4-7 of
the accumulator, bits 4-7 of the data memory location, and the contents of
register 'i' are unaffected. -
Operation: (AO-3) ~ ((RiO-3)) i = 0-1
Example: Assume program counter contents have been stacked in locations 22-23.
, .
XCHNIB: MOV RO,#23 ;MOVE '23' DEC TO REG 0
CLR A ;CLEAR ACC TO ZEROS
XCHDA,@RO ;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 23 (BTS 8-11 OF PC ARE
;ZEROED, ADDRESS REFERS
:TO PAGE 0)
XRL A,R r Logical XOR Accumulator With Register Mask
Encoding: 11 1 0 1 11 r r r 1 D8H-DFH
Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in
working register 'r'..
Operation: (A) - (A) XOR (Rr) r =0-7
_Example: XORREG:. XRL A,R5 ;'XOR' ACC CONTENTS WITH
;MASK IN REG 5
•• 0-5 in S04SAH/S74SH
0-6 in S049AH/S749H
0-7 in S050AH
3-36
MCS®-48 INSTRUCTION SET
XRL A,@Ri Logical XOR Accumulator With Memory Mask
Encoding: 11 1 0 1 1 0 0 0 i 1 DOH-D1H
Description: Data'in the accumulator is EXCLUSIVE ORed with the mask contained in the
data memory location addressed by register 'i', bits 0-5,*"
Operation: (A) - (A) XOR ((Ri)) i =0-1
Example: XORDM: MOV R1,#20H ;MOVE '20' HEX TO REG 1
XRL A,@R1 ;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32
XRL A,#data Logical XOR Accumulator With Immediate Mask
Encoding: 11 1 0 1 1 0 0 1 1 1 1d7 d6 dS d4 I d3 d2 d 1 dO 1 D3H
Description: 'This is a 2-cycle instruction. Data in the accumulator is EXCLUSIVE ORed
with an immediately-specified mask.
Operation: (A) - (A) XOR data
Example: XORID: XOR A,#HEXTEN ;XOR CONTENTS OF ACC WITH MASK
;EQUAL VALUE OF SYMBOL :HEXTEN'
** 0-5 in B04BAH/B74BH
0-6 in B049AH/B749H
0-7 in B050AH
3-37
MCS® . .48 Data Sheets
and Index
4
8243
MCS®-48 INPUTIOUTPUT EXPANDER
• O°C TO 70°C Operation
PORTO
P50 vee
PolO P51
PORT5
,..1 P52
Pt2 P53
PORT Z Pt3 P60
CS Pll
·PROG P62
P23 Pl3
PORT6 P22 P73
P21 P72
P20 P71
GND P70
270161-2
PORT 7
Figure 2. 8243 Pin
Configuration
270161-1
Figure 1.8243 Block Diagram
October 1986
4-1 Order Number: 270161-001
8243
Table 1. Pin Description
Symbol Pin No. Function
PROG 7 Clock Input. A high to low transition on PROG signifies that address
and control are available on P20-P23, and a low to high transition
signifies that data is available on P20'-P23.
CS 6 Chip Select Input. A high on CS inhibits any change of output or
internal status.
P20-P23 11-8 Four (4) bit bi-directional port contains the address and control bits on
a high to low transition of PROG. During a low to high transition, P2
contains the data for a selected output port if a write operation, or the
data from a selected port before the low to high transition if a read
operation.
GND 12 OVsupply.
P40-P43 2-5 Four (4) bit bi-directionalllO ports.
P50-P53 1,23-21 May be programmed to be input (during read), low impedance latched
P60-P63 20-17 output (after write), or a tri-state (after read). Data on pins P20-P23
P70-P73 13-16 may be directly written, ANDed or ORed with previous data.
Vee 24 +5Vsupply.
fUNCTIONAL DESCRIPTION either high or low when power is applied. The first
high to low transition of PROG causes the device to
exit power on mode. The power on sequence is ini-
General Operation tiated if Vee drops below W.
The 8243 contains four 4-bit I/O ports which serve P21 P20 Address P23 P22 Instruction
as an extension of the on-chip I/O and are ad- Code Code
dressed as Ports 4-7. The following operations may o o Port 4 o o Read
be performed on these ports: o 1 Port 5 o 1 Write
• Transfer Accumula.tor to Port. 1 o Port 6 1 o ORLD
• Transfer Port to Accumulator. 1 1 Port 7 1 1 ANLD
• AND Accumulator to Port.
• OR Accumulator to Port. Write Modes
All communication between the 8048 and the 8243 The device has three write modes. MOVD Pi, A di-
occurs over Port 2 (P20-P23) with timing provided rectly writes new data into the selected port and old
by an output pulse on the FROG pin of the piOces- data is lost. ORlD Pi, A takes nety data, OR's it with
sor. Each transfer consists of two 4-bit nibbles: the old data and then writes it to the port. ANLD Pi,
A takes new data, AND's it with the old data and
The first containing the "op code" and port address then writes it to the port. Operation code and port
and the second containing the actual 4-bits of data. address are latched from the input Port 2 on the high
A high to low transition of the PROG line indicates to low transition of the PROG pin. On the low to high
that address is present while a low to high transition transition of PROG data on PQrt 2 is transferred to
indicates the presence of data. Additional 8243's the logic block of the specified output port.
may be added to the 4-bit bus and chip selected
using additional output lines from the After the logic manipulation is performed, the data is
8048/8748/8035. latched and outputed. The old data remains latched
until new valid outputs are entered. .
Power On Initialization
Read Mode
Initial application of power to the device forces in-
put/output Ports 4, 5, 6, and 7 to the tri-state and The device has one read mode. The operation code
Port 2 to the input mode. The PROG pin may be and port address are latched from the input Port 2
4-2
intJ 8243
on the high to low transition of the PROG pin. As Normally, a port will be in an output (write mode) or
soon as the read operation and port address are· input (read mode). If modes are changed during op-
decoded, the appropriate outputs are tri-stated, and eration, the first read following a write should be ig-
the input buffers switched on. The read operation is nored; all following reads are valid. This is to allow
terminated by a low to high transition of the PROG the external driver on the port to settle after the first
pin. The port (4, 5, 6 or 7) that was selected is read instruction removes the low impedance drive
switched to the tri-stated mode while Port 2 is re- from the 8243 output. A read of any port will leave
turned to the input mode. that port in a high impedance state.
ABSOLUTE MAXIMUM RATINGS*
• Notice: Stresses above those listed under "Abso-
Ambient Temperature Under Bias .. '.' .. O°C to 70°C lute Maximum Ratings" may cause permanent dam-
Storage Temperature .......... - 65°C to + 150°C age to the device. This is a stress rating only and
Voltage on Any Pin functional operation of the device at these or any
with Respect to Ground .......... - 0.5V to + 7V other conditions above those indicated in the opera-
Power Dissipation ........................ 1 Watt tional sections of this specification is not implied Ex-
posure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. CHARACTERISTICS T A = O°C to 70°C, Vee = 5V ± 10%
Test
Symbol Parameter Min Typ Max Units
Conditions
Vil Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee + 0.5 V
VOL1 Output Low Voltage Ports 4-7 0.45 V IOl = 4.5 rnA'
VOl2 Output Low Voltage Port 7 1 V IOl = 20 rnA
VOH1 Output High Voltage Ports 4-7 2.4 V IOH = 240 p.A
IIl1 Input Leakage Ports 4-7 -10 20 p.A Vin = Vee to OV
11L2 Input Leakage Port 2, CS, PROG -10 10 p.A Vin = Vee toOV
VOl3 Output Low Voltage Port 2 0.45 V IOl = 0.6 rnA
Icc Vee Supply Current 10 20 rnA (Note 1)
VOH2 Output Voltage Port 2 2.4 IOH = 100 p.A
IOl Sum of AlilOl From 16 Outputs 72 rnA 4.5 rnA Each Pin
.. ..
'Refer to Figure 3 for additional sink current capability.
4-3
inter 8243
A.C. CHARACTERISTICS TA = 0·Cto70·C, vcc = 5V ± 10%
Symbol Parameter Min Max Units Test Conditions
tA Code Valid before PROG 50 ns BOpF Load
tB Code Valid after PROG 60 ns 20pF Load
tc Data Valid before PROG 200 ns BOpF Load
tD Data Valid after PROG 20 ns 20pF Load
tH Floating after PROG 0 150 ns 20pF Load
tK PROG Negative Pulse Width 700 ns
tcs CS Valid before/after PROG 50 ns
tpo Ports 4-7 Valid after PROG 700 ns 100 pF Load
tLP1 Ports 4-7 Valid before/after PROG 100 ns
tACC Port 2 Valid after PROG 650 ns BOpF Load
NOTE:
1. Icc (-40·C to 85·C EXPRESS options) 15 mA typical/25 mA maximum.
_---IX:~ > -,,~~. <::X
2.4 - - - . . . . , . ,...._ _ _ _ _ _ _ _ _ _ _ __
0.45 " ' . - -_ _
270161-3
A.C. Testing: Inputs are driven at 2.4V fora Logic "1" and 0.45V for a logic "0". Output timing measurements are made at2.0V for logic "1"
and O.BV for a logic "0".
4·4
inter 8243
WAVEFORMS
PROG
~~ ______________ IK ________________ ~
PORT2 FLOAT FLOAT
PORT 2
IpO
PORTS 4·7 PREVIOUS OUTPUT VALlO OUTPUT
VALID
lIP
PORTS 4·7 INPUT VALlO
ICS ICS
270161-4
4-5
inter 8243
125
100
C
!
:;
5}
~ 75
...Z
III
"'.
'"'" GUARANTEED WORST CASE
..
U
Z
50
CURRENT SINKING CAPABILITIES
OF ANY 1/0 PORT PIN YO. TOTAL
...iii SINK CURRENT OF ALI. PINS
~
...0
25
4 10 11 12 13
MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 101. WORST CASE PIN (mA)
270161-5
Figure 3. 8243 Current Sink Capability
Sink Capability . NOTE:
A 10 to 50 Kn pullup resistor to + 5V should be
The 8243 can sink 5 rnA @ 0.45V on each of its 16 added to 8243 outputs when driving to 5V CMOS
liD lines simultaneously. If, however, all lines are directly.
not sinking simultaneously or all lines are not fully Example: This example shows how the use of the
loaded, the drive capability of any individual line in- 20 rnA sink capability of Port 7 affects the
creases as is shown by the accompanying curve. sinking capability of the. other liD lines.
For example, if only 5 of the 16 lines are to sink An 8243 will drive the following loads
CUii6nt at one time, the cur.;e ShO\NS that· each of
simultaneously.
those 5 lines is capable of sinking 9 rnA @ 0.45V (if 2 loads-20 rnA @ 1V (Port 7 only)
any lines are to sink 9 rnA the total IOL must not 8 10ads-4 rnA @ 0.45V
exceed 45 rnA or five 9 rnA loads). .
6 loads-3.2 rnA @ 0.45V
Example: How many pins can drive 5 TIL loads
(1.6 rnA) assuming remaining pins are un~ Is this within the specified limits?
,loaded? EIOL = (2 X 20) + (8 x 4) + (6 x 3.2)
IOL = 5 x 1.6 rnA = 8 rnA = 91.2 rnA.
From the curve': for loi. = 4 rnA, EIOL ~
EIOL = 60 rnA from curve
93 rnA. Since 91.2 rnA < 93 rnA the loads
# pins = 60 rnA -7- 8 rnA/pin = 7.5 = 7 are within specified limits.
In this case, 7 lines can sink 8 rnA for a Although the 20 rnA @ 1V loads are used
total of 56 rnA. This leaves 4 rnA sink cur- in calculating eIOL' it is the largest current
rent capability which can be divided in any . required @ 0.45V which determines the
way among the remaining 8 liD lines of maximum allowable eIOL.
the 8243.
4-6
inter 8243
-=-
CS
liD
P4 110
PROG PROG
TEST P5 110
INPUTS
8048 8243
P6 4 110
P20-P23 DATA IN
P2
P7 110
270161-6
Figure 4. Expander Interface
BITS 3,2 BITS 1,0
00 } READ 00
01 WRITE 01 } PORT
10 OR 10 ADDRESS
P20·P23 ~'-_---JX'--- __--J)>--- 11 AND 11
ADDRESS (4·8ITSI DATA (4·8ITSI
270161-7
Figure 5. Output Expander Timing
PORT 1
0048
PORT2
PROG~--------------+---------------~--------~------~--------------~
270161-8.
Figure 6. Using Multiple 8243'5
4-7
P8748H/P8749H
8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
PRODUCTION MICROCONTROLLER
• High Performance HMOS II
• Easily
Programmable ROMs Using 21V
• Interval Time/Event Counter
• Up to 1Expandable Memory and I/O
• Two Single Level Interrupts
• Instructions 1 or 2 Cycles
~36
IJ-s Instruction Cycle All
• Single 5-Volt Supply
• Over 96 Instructions; 90% Single Byte
The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and ROMless versions as well as a neW version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of-requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
,times and code risks. '
These microcomputers are d,esigned to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly, single byte instructions and no instruc-
tions over 2 bytes in length. '
Device Internal Memory RAM STANDBY
B050AH 4KxBROM 256xBRAM yes
B049AH 2KxBROM 12BxBRAM yes
B04BAH 1KxBROM 64xBRAM yes
B040AHL None 256xBRAM yes
B039AHL None 12BxBRAM yes
B035AHL None 64xBRAM yes
PB749H 2K x B Programmable ROM 12BxBRAM no
PB74BH 1K x B Programmable ROM 64xBRAM no
• CLOCK I I PROGRAM I, DATA r~Po.RT
XTALt P ,
270053-1
Figure 1. Block Diagram
270053-2
Figure 2. Logic Symbol
November 1987
4-8 Order Number: 270053-002
intJ MCS®-48
I~ ~ ~
I~ wee
en a:: 0 0z u
....
0
- ~
> ~
r--
~ a..
~ D-~
CD II)
TO , Vee
XTAL 1 T1
XTAL2
RESET'
P27
P26 iNT • P2.4
SS P2S EA PL7
INT P2' Rii B049AH/B039AHL
PI.6
EA PI7 PSEN B050AH/B040AHl PI.S
AD P'6
PSEN p,s WR 44- PIN PI.4
Plee
WR Ne Ne
ALE
DBO ALE PI.3
DB, 090 PI.2
DB2 091 PI.I
Top View
DB3 looking down on PC Boord
092 PCO
DB.
DBS 093 VOO
DB6
DB7
VSS " - _ - - - ' ' ' '
270053-3
270053-14
Figure 3. Pin Configuration Figure 4. Pad Configuration
Table 1. Pin Description
Pin
Symbol Function Device
No.
VSS 20 Circuit GND potential. All
VDD 26 + 5V during normal operation. All
low power standby pin. 8048AH
8035AHl
8049AH
8039AHl
8050AH
8040AHl
Programming power supply (+ 21 V). P8748H
P8749H
Vee 40 Main power supply; + 5V during operation and programming. All
PROG 25 Output strobe for 8243 110 expander. All
Program pulse ( + 18V) input pin During Programming. P8748H
P8749H
P10-P17 27-34 8-bit quasi-bidirectional port. All
Port 1
P20-P23 21-24 8-bit quasi-bidirectional port. P20-P23 contain the four high order All
P24-P27 35-38 program counter bits during an external program memory fetch and
Port 2 serve as a 4-bit 1/0 expander bus for 8243.
DBO-DB7 12-19 True 'bidirectional port which can be written or read synchronously All
BUS using the RD, WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction under
the control of PSEN. Also contains the address and data during an
external RAM data store instruction, under control of ALE, RD, and
WR.
TO 1 Input pin testable using the conditional transfer instruction JTO and All
JNTO. TO can be designated as a clock output using ENTO ClK
instruction.
Used during programming. P8748H
P8749H
4-9
intJ MCS®·48
Table 1. Pin Description (Continued)
Pin
Symbol Function Device
No.
T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be All
designated the timer/counter input !,Ising the STRT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is All
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
RD S Output strobe activated during a BUS read. Can be used to enable All
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
RESET 4 Inputwhich is used to initialize the processor. (Active low) (Non TTL All
VIH)
Used during power down. S04SAH
S035AHL
S049AH
I. S039AHL
. S050AH
S040AHL
Used during programming. PS74SH
PS749H
Used during ROM verification. S04SAH
PS74SH
S049AH
PS749H
S050AH
WR 10 Output strobe during a bus write. (Active low) All
Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is All
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
PSEN 9 Program store enable. This output occurs only during a fetch to All
external program memory. (Active low)
SS 5 Single step input can be used in conjunction with ALE to "single step" All
the processor through each instruction.
(Active low) Used in sync mode. S04SAH
8035AHL
S049AH
S039AHL
S050AH
S040AHL
EA 7 External access input which forces all program memory fetches to All
reference external memory. Useful for emulation and debug. (Active
high)
Used during (1SV) programming. PS74SH
PS749H
Used during ROM verification (12V). S04SAH
S049AH
S050AH
XTAL1 2 One side of crystal input for internal 'oscillator. Also input for external All
source. (Non TTL VIH)
XTAL2 3 Other side of crystal input. All
4-10
MCS®-48
Table 2. Instruction Set
Accumulator Input/Output
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ADDA,R Add register to A 1 1 INA,P Input port to A 1 2
ADDA,@R Add data memory 1 1 OUTLP,A Output A to port 1 2
toA f.NL P, #data And immediate to 2 2
ADD A, #data Add immediate to A 2 2 port
AD DC A, R Add register with 1 1 ORL P, #data Or immediate to 2 2
carry port
AD DC A, @R Add data memory 1 1 INS A, BUS Input BUS to A 2
with carry OUTLBUS,A Output Ato BUS 2
ADDC A, # data Add immediate with 2 2 ANL BUS, #data And immediate to 2 2
carry BUS
ANLA, R And register to A 1 1 ORL BUS, # data Or immediate to 2 2
ANLA,@R And data memory 1 1 BUS
toA MOVDA, P Input expander port 2
ANLA, #data And immediate to A 2 2 toA
ORLA, R Or register to A 1 1 MOVDP,A Output A to 2
ORLA,@R Or data memory 1 1 expander port
toA ANLD P,A And A to expander 2
ORLA, #data Or immediate to A 2 2 port
XRLA, R Exclusive or register 1 1 ORLDP,A Or A to expander 2
toA port
XRLA, @R Exclusive or data 1 1
memory to A
XRLA, #data Exclusive or 2 2 Registers
immediate to A
Mnemonic Description Bytes Cycles
INCA IncrementA 1 1
DECA Decrement A 1 1 INCR Increment register 1 1
CLRA Clear A 1 1 INC@R Increment data memory
CPLA Complement A 1 1 DECR Decrement register
DAA Qecimal adjust A 1 1
SWAP A Swap nibbles of A 1 1 Branch
RLA Rotate A .left 1 1
RLCA Rotate A left 1 1 Mnemonic Description Bytes Cycles
through carry
RRA Rotate A right 1
JMP addr Jump unconditional 2 2
1
JMPP@A Jump indirect 1 2
RRCA Rotate A right 1 1 DJNZ R, addr Decrement register 2 2
through carry
and skip
JCaddr Jump on carry = 1 2 2
JNC addr Jump on carry = 0 2 2
JZaddr Jump on A zero 2 2
JNZaddr Jump on A not zero 2 2
JTO addr Jump on TO = 1 2 2
JNTO addr Jump on TO = 0 2 2
JT1 addr Jump on T1 = 1 2 2
JNT1 addr JumponT1 = 0 2 2
JFO addr· Jump on FO = 1 2 2
JF1 addr Jump on F1 = 1 2 2
JTF addr Jump on timer flag 2 2
JNI addr Jump on INT = 0 2 2
JBb addr Jump on accumulator 2 2
bit
4-11
MCS®-48
Table 2. Instruction Set (Continued)
.-----~------~------------------~ r--------------------------------~
Subroutine Timer/Counter
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
CALLaddr Jump to subroutine 2 2 MOVA, T Aead timer/counter 1 1
RET Return 1 2 MOVT,A Load timer/counter 1 1
RETR Return and restore 1 2 STATT Start timer 1 1
status STATCNT Start counter 1 1
STOP TCNT Stop timer/counter 1 1
EN TCNTI Enable timer/
Flags counter interrupt
DIS TCNTI Disable timer/
Mnemonic Description Bytes Cycles counter interrupt
CLRC Clear carry . 1 1
CPLC Complement carry 1 1
CLRFO Clear flag 0 Control
1 1
CPLFO , Complement flag 0 1 1
CLR F1 Clear flag 1 Mnemonic Description Bytes Cycles
1 1
CPLF1 Complement flag 1 1 1 EN I Enable external 1 1
. interrupt
DISI Disable external
Data Moves interrupt
Mnemonic Description Bytes Cycles SELABO Select register bank 0
SELAB1 Select register bank 1
MOVA,A Move register to A 1 1 SELMBO Select memory bank 0
MOVA,@R Move data memory 1 1 SELMB1 Select memory bank 1
toA
MOVA, #data Move immediate to ENTOCLK Enable clock output
2 2
A onTO
MOVA,A Move A to register
MOV@A,A Move A to data Mnemonic Description Bytes Cycles
memory
MOVR, #data Move immediat~ to 2 2 NOP No operation 1 1
register
MOV @A, #data Move immediate to 2 2
data memory
MOVA,PSW MovePSWtoA
MOVPSW,A MoveAtoPSW
XCHA, A Exchange A and
register
XCHA,@R. Exchange A and
data memory
XCHDA,@A Exchange nibble of
A and data memory
MOVXA,@A Move external data. 2
memoiytoA
MOVX@A,A Move A to external 2
data memory
MOVPA,@A Move to A from 2
current page
MOVP3A,@A Move to A from 1. 2
page 3
4-12
MCS®·48
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Case Temperature Under Bias ...•..• O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .•.•..•... - 65°C to + 150·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on any Pin with Respect
tional sections of this specification is not implied. Ex-
to Ground ...................... - 0.5V to + 7V posure to absolute maximum rating conditions for
Power Dissipation .............•.....•...... 1.5W extended periods may affect device reliability.
NOTICE: Specifications contained within the'
following tables are subject to change.
D.C. CHARACTERISTICS TA = O·C to + 70·C; Vee = Voo = 5V ± 10%; Vss = OV
limits
Symbol Parameter Unit Test Conditions Device
Min Typ Max
VIL Input Low Voltage (All -0.5 0.8 V All
Except RESET, X1, X2)
VIL1 Input Low Voltage -5 0.6 V All
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V All
(All Except XTAL 1,
XTAL2, RESET)
VIH1 Input High Voltage 3.8 Vee V All
(X1, X2, RESET)
VOL Output Low Voltage 0.45 V IOL = 2.0 rnA All
(BUS)
VOL1 Output Low Voltage 0.45 V IOL = 1.8 rnA All
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0.45 V IOL = 1.0 rnA All
(PROG)
VOL3 Output Low Voltage 0.45 V IOL = 1.6 rnA All
(All Other Outputs)
VOH Output High Voltage 2.4 V IOH = - 400 /LA All
(BUS)
VOH1 Output High Voltage 2.4 V IOH = -100 !LA All
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40/LA All
(All Other Outputs)
4-13
inter MCS®-48
D.C. CHARACTERISTICS TA = 0·Cto+70·C;Vee = Voo = 5V ±10%;Vss= OV(Continued)
Limits
Symbol Parameter Unit, Test Conditions Device
Min Typ Max
ILl Leakage Current ±10 p.A Vss s VINs Vee All
(T1,INT) , ,
IUl Input Leakage Current -500 p.A Vss + 0.45 s VIN s Vee All
(P10-P17, P20-P27,
EA, SS) ,
IU2 Input Leakage Current -10 -SOO p.A Vss s VIN s S.B All
RESET
ILO Leakage Current ±10 p.A Vsss VIN sVee All
(BUS, TO) (High
Impedance State)
100 Voo Supply Current S 5 ,mA' B04BAH
(RAM Standby) BOS5AHL
4 7 mA 8049AH
BOS9AHL
5 10 mA .,;
8050AH
B040AHL
100 + Total Supply Current" SO 65 mA B048AH
lee BOS5AHL
35 70 mA B049AH
BOS9AHL
40 BO mA B050AH
B040AHL
SO 100 mA PB74BH
50 110 mA PB749H
Voo RAM Standby Voltage , ,2.2 5.5 V Standby Mode Reset B04BAH
sVILl 8035AH
2.2 5.5 V B049AH
BOS9AH
\I
2.2 5.5 v 8050AH
I I B040AHL I
'Icc + 100 are measured with all outputs in their high impedance state; RESET low; 11 MHz crystal applied; INT, 55, and EA floating.
intJ MCS®-48
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = voo = 5V ±10%;Vss = ov
f (t) 11 MHz Conditions
Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1 /xtal freq 90.9 1000 ns (Note 3)
tLL ALE Pulse Width 3.5t-170 150 ns
tAL Addr Setup to ALE 2t-110 70 ns (Note 2)
tLA Addr Hold from ALE t-40 50 ns
tCC1 Control Pulse Width (RD, WR) 7.5t-200 480 ns
tCC2 Control Pulse Width (PSEN) 6t-200 350 ns
tow Data Setup before WR 6.5t-200 390 ns
two Data Hold after WR t-50 40 ns
tOR Data Hold (RD, PSEN) 1.5t-30 0 110 ns
tR01 RD to Data in 6t-170 375 ns
tR02 PSEN to Data in 4.5t-170 240 ns
tAW Addr Setup to WR 5t-150 300 ns'
tA01 Addr Setup to Data (RD) 10.5t-220 730 ns
tA02 Addr Setup to Data (PSEN) 7.5t-200 460 ns
tAFC1 Addr Float to RD, WR 2t-40 140 ns (Note 2)
tAFC2 Addr Float to PSEN 0.5t-40 10 ns (Note 2)
tLAFC1 ALE to Control (RD, WR) 3t-75 200 ns
tLAFC2 ALE to Control (PSEN) 1.5t-75 60 ns
tCA1 Control to ALE (RD, WR, PROG) t-65 25 ns
tCA2 Control to ALE (PSEN) 4t-70 290 ns
tcp Port Control Setup to PROG 1.5t-80 50 ns
tpc Port Control Hold to PROG 4t-260 100 ns
tpR PROG to P2 Input Valid 8.5t-120 650 ns
tpF Input Data Hold from PROG 1.5t 0 140 ns
top Output Data Setup 6t-290 250 ns
tpo Output Data Hold 1.5t-90 40 ns
tpp PROG Pulse Width 10.5t-250 700 ns
tpL Port 2 110 Setup to ALE 4t-200 160 ns
tLP Port 2 110 Hold to ALE 0.5t-30 15 ns
tpv Port Output from ALE 4.5t+ 100 5.0 ns
tOPRR TO Rep Rate 3t 270 ns
tCY Cycle Time 15t 1.36 15.0 p.s
NOTES:
1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crYstal input.
4-15
inter MCS®·48
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY
MEMORY
-..j .LAFC1r-
ALE
RD
'DR
FLOAT.NG
270053-5
WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS
2.4Y -----X~.Q TEST
OA5V----J. .0.8""
... POINTSt'2.0~
.... 0 . 8 " - - - -
270053-7
A.C. testing inputs are driven at 2.4V lor a logic "1" and 0,45V lor
a logic "0". Output timing measurements are made at 2.0V lor a
logic "1" and 0.8V lor a logic "0".
270053-6
PORT 1/PORT 2 TIMING
ALE
PSEN
I
I
P2~-23 r-----P-~~R-T-~-~--i-O-A--'A--~\lr-h-·E-W-·F-.U----~-O-A-~~--
OUTPUT
P24-21
~ __ PCH
~----------J
P10-17 PORT 24-21. PORT 10-17 DATA NEW PORT 9ATA
OUTPUT
'LP ---l '-'CA1
I~
EXPANDER
PORT
I
··LA---...........- ,'DP-----r1
OUTPUT
,..----'------->.1 r------;,
PCH
;--------
I OUTPUT DATA
I
' -_ _ _ _ _ _...J
I i---
I~'
'PF
EXPANDER
PORT
~--PC-H--~I
I "
r-~-~
'PR~
'NPUT
j-.cp+.PC.j ' - - _ . J I I
PROG ---.,.--------------....,~r-.PP_r_
270053-8
4-16
MCS®-48
CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE
Cl Cl
~,-C_2_--,-
L, ,- -"-_~_~_!- -:2:-1
f------""""""f"---=2'-l
~(
XTALl
1-11
-:b
__ XTALl
XTAL2
J- C""""~ ~ XTAL2
C3 C3
270053-9 270053-10
Cl = 5 pF ±% pF + (STRAY < 5 pF)
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20 pF ±1 pF + (STRAY < 5 pF)
Crystal series resistance should be less than 3011 at 11 MHz; less
than 7511 at 6 MHz; less than 18011 at 3.6 MHz.
DRIVING FROM EXTERNAL SOURCE
+SV
47011
»-.----'=-1 XTAL1
+5V
TTL OPEN
COLLECTOR
GATES 47011
'----..L---;;1 XTAL2
270053-11
For XTALl and XTAL2 define "high" as voltages above 1.6V and
"low" as vOltages below 1.6V. The duty cycle requirements for
externally driving XTAL 1 and XTAL2 using the circuits shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.
4-17
inter MCS®-48
PROGRAMMING AND VERIFYING THE WARNING:
P8749H/48H PROGRAMMABLE ROM An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
Programming Verification of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
In brief, the programming process consists of: acti- used to disable the programmer.
vating the program mode, applying an address,
latching the address, applying data, and applying a The ProgramlVerify sequence is:
programming pulse. Each word is programmed com- 1. Voo = 5V, Clock applied or internal oscillator
pletely before moving on to the next and is followed operating, RESET = OV, TO = SV, EA = SV,
by a verification step. The following is a list of the BUS and PROG floating. P10 and P11 must be
pins used for programming and a description of their tied to ground.
functions:
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)
Pin Function
4. EA = 18V (activate program mode)
XTAL1 Clock Input (3 to 4.0 MHz)
S. Address applied to BUS and P20-22
XTAL2
RESET 6. RESET = SV (latch address)
Initialization and Address Latching
.... ...
,
TO Selection of Program or Verifying Mode 7. Data applied to BUS
EA Activation of ProgramlVerify Modes 8. Voo = 21V (programming power)
BUS Address and Data Input 9. PROG = Vee or float followed by one SO ms
'Data Output During Verify pulse to 18V
P20-P22 Address Input 10. Voo = 5V
Voo Programming Power Supply
Program Pulse Input
11. TO = SV (verify mode)
PROG
12. Read and verify data on BUS
13. TO = OV
14. RESET = OV and repeat from step S
1S. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.
NOTE:
Once programmed the P8749H/48H cannot be
erased.
4-18
MCS®-48
A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
TA = 25°C ±5°C; VCC = 5V ±5%; VOO = 21 ±0.5V
Symbol Parameter Min Max Unit Test Conditions
tAW Address Setup Time to RESET 4tCY
tWA Address Hold Time After RESET 4tcy
tow Data in Setup Time to PROG 4tCY
two Data in Hold Time After PROG 4tCY
tpH RESET Hold Time to Verify 4tCY
tVOOW Voo Hold Time Before PROG 0 1.0 ms
tvoOH Voo Hold Time After PROG 0 1.0 ms
tpw Program Pulse Width 50 60 ms
trw TO Setup Time for Program Mode 4tCY
tWT TO Hold Time After Program Mode 4tcy
too TO to Data Out Delay 4tCY
tww RESET Pulse Width to Latch Address 4tcy
tr, tl Voo and PROG Rise and Fall Times 0.5 100 J.Ls
tCY CPU Operation Cycle Time 3.75 5 J.Ls
tRE RESET Setup Time before EA 4tCY
NOTE:
II Test 0 is high, too can be triggered by RESET.
D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
TA = 25°C ±5°C; Vcc = 5V ±5%; Voo = 21 ±0.5V
Symbol Parameter Min Max Unit Test Conditions
VOOH Voo Program Voltage High Level 20.5 21.5 V
VOOL Voo Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High Level 17.5 18.5 V
VPL PROG Voltage Low Level 4.0 Vcc V
VEAH EA Program or Verify Voltage High Level 17.5 18.5 V
100 Voo High Voltage Supply Current 20.0 rnA
IpROG PROG High Voltage Supply Current 1.0 rnA
lEA EA High Voltage Supply Current 1.0 rnA
4-19
MCS®·48
SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE SUBSEQUENT ROM DUMP CYCLES
ALE
(NOTE 1)
E« ....:J.
I
: (INPUT)
I
I
I ,,
DB----i ADDRESS H
.....-(~IN:-::P::-U':':T::-)---'
ROM DATA
(OUTPUT)
H
I
ADDRESS
~----------------
, (INPUT) (OUTPUT)'
I
RESET _ _ _ _ _ _....
,
~,
I
(INPUT) .
. ! - - i-
,,
- -
PZ~PZ3---_L_ _ _ _A_DD_R_E_S_S_ _ _~~~---A-D-D-RE-S-S----Jr--____________
: (INPUT)
270053-12
50H Vee = Veo = +5V
Al0 ADDR Vss = OV
All ADDR
NOTE:
ALE is function of X1, X2 inputs.
COMBINATION PROGRAM/VERII=Y MODE (PROGRAMMABLE ROMS ONLY)
VEAH
EA
Vee ---+---'
I_ _ _ _ _ _ _ PROGRAM--------II--~VERIFY-~~---PROGRAM-
Vee
TO
VIL1
Vee
RESET
VIL1
iAw-+i--t--i-1 twA - -tcc~
DBa-DB7 J --. DATA TO BE
PROGRAMMED VALID
LAST NEXT
ADDRESS ADDRESS
VDDH - - - - - - - - - - - -
VDD
.Vee------------
lOw
VPH -----------------+-t-i--_\.
PROG
VPL--------------- ------,-- --.------------
270053-13
4-20
inter D8748H/D8749H
HMOS-E SINGLE-COMPONENT 8-BIT MICROCOMPUTER
• High Performance HMOS-E
• Compatible with 8080/8085 Peripherals
• Two Single Level Interrupts
Interval Timer/Event Counter
• Up to 1.35 p,s Instruction Cycle;
Easily Expandable Memory and 110
• Single 5-Volt Supply • All Instructions 1 or 2 Cycles
• Over 96 Instructions; 90% Single Byte
•
The Intel D8749H/D8748H are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS-E process.
The family contains 27 I/O lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/clock circuits.
For systems that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no instruc-
tions over 2 bytes in length.
Device Internal Memory
D8749H ' 2Kx8 EPROM I 128 x8 RAM
D8748H 1Kx8 EPROM I 64x8 RAM
PORT
I
D8748H PORT
2
D87-49H
READ
WRITE
PROGRALi
STORE
ENABLE
ADDRESS
LATCH
. ENABLE
PORT
EXPANDER
210983-1 STROBE
Figure 1. 210983-2
Block Diagram
Figure 2.
Logic Symbol
October 1987
4-21 Order Number: 210983-003
D8748H/D8749H
Vee
Tl
P27
RESET P26
55 P25
P2.
P17
Ro P16
PSEN P15
Wi! P14
P13
08. P12
DB, P11
08 2 Pl.
DB. VOO
PROG
P23
P22
DB7 P21
VSS
210983-3
Figure 3. Pin Configuration
. Table 1. Pin Description (40-Pin DIP)
Symbol Pin No. Function
Vss 20 Circuit GND potential.
VDD 26 + 5V during normal operation.
Programming power supply (+ 21 V).
Vee 40 Main power supply; + 5V during operation and programming.
PROG '25 Output strobe for 8243 I/O expander.
Program pulse ( + 18V) input pin during programming.
P10-P17 27-34 8·bit quasi·bidirectional port.
Port 1
P20-P23 21-24 8·bit quasi-bidirectional port. P20-P23 contain the four high order program
counter bits during an external program memory fetch and serve as a 4·bit
I/O expander bus for 8243.
P24-P27 35-38
Port 2
DBO-DB7 ·12-19 True bidirectional port which can be written or read synchronously using the
~II""
OUi:) RD, 'yAJR stiobes. The port can also be statically !atc.hed. Contains the 8 !O\&,
order program counter bits during an eXternal program memory tetch, and
receives the addressed instruction under the control of PSEN. Also contains
the address and data du~ an external RAM data store instruction, under
control of ALE, RD; and WR.
TO 1 Input pin tesliible using the conditional transfer instructions JTO and JNTO.
TO can be designated as a clock output using ENTO CKL instruction.
Used during programming.
T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be designated
the timer/counter input using the STRT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction. (Active
low) interrupt must remain low for at least 3 machine cycles for proper
operation.
RD 8 Output strobe activated during a BUS read. Can be used to enable data onto
the bus from an external device.
Used as a read strobe to external data memory. (Active low)
4·22
intJ D8748H/D8749H
Table 1 Pin Description (40-Pin DIP) (Continued)
Symbol Pin No. Function
RESET 4 Input which is used to initialize the processor. (Active low) (Non TTL VI H)
Used during programming.
WR 10 Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.
PSEN 9 Program store enable. This output occurs only during a fetch to external
program memory. (Active low.)
SS 5 Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.
EA 7 .External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high.)
Used during (1 BV) programming.
XTAL1 2 One side of crystal input for internal oscillator. Also input for external source.
(Non TTL VIH.)
XTAL2 3 Oth~r side of crystal input.
Table 2. Instruction Set
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ACCUMULATOR ACCUMULATOR (Continued)
ADD A, R Add register to A INCA IncrementA
ADDA,@R Add data DECA Decrement A
memory to A GLRA Clear A
ADDA, #data Add immediate 2 2 GPLA Compleinent A
toA DAA Decimal adjust A
ADDCA,R Add register with SWAP A Swap nibbles of
carry A
ADDCA,@R Add data RLA Rotate A left
memory with RLCA Rotate A left
carry through carry
ADDC A, #data Add immediate 2 2 RRA Rotate A right
with carry RRGA Rotate A right
ANLA,R And register to A through carry
ANLA,@R And data
memory to A INPUTIOUTPUT
ANLA, #data And immediate 2 2 INA,P Input port to A 1 2
toA OUTLP, A Output A to port 1 2
ORLA, R Or register to A ANLP, #data And immediate 2 2
ORLA,@R Or data memory to port
toA ORLP, #data Or immediate to 2 2
ORLA, #data Or immediate to 2 2 port
A INSA,BUS Input BUS to A 1 2
XRLA, R Exclusive or OUTLBUS,A Output A to BUS 1 2
ANL BUS, #data And immediate 2 2
register to A
XRLA,@R Exclusive or to BUS
ORL BUS, #data Or immediate to 2 2
data memory to
A BUS
XRLA, #data MOVDA, P Input expander 2
Exclusive or 2 2
imniediate to A port to A
4-23
inter D8748H/D8749H ~OOjgILOIMIOOO£OOW
Table 2. Instruction Set (Continued)
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
INPUTIOUTPUT (Continued) DATA MOVES (Continued)
MOVDP,A Output A to 2 MOVR,A Move A to register
expander port .MOV@R,A Move A to data
ANLDP,A And A to expander 2 memory
port MOVR, #data Move immediate to 2 2
ORLDP,A Or A to expander 1. 2 register
port MOV @R, "'data Move immediate to 2 2
data memory
REGISTERS MOVA,PSW MovePSWtoA
INCR Increment register MOVPSW,A MoveAtoPSW
INC@R Increment data XCHA, R Exchange A and
memory register
DECR Decrement register XCHA,@R Exchange A and
BRANCH data memory
JMPaddr Jump unconditional 2 2 XCHDA,@R Exchange nibble
JMPP@A Jump indirect 1 2 of A and register
DJNZR,addr Decrement register 2 2 MOVXA,@R Move external 2
and skip data memory to A
JCaddr Jump on carry = 1 2 2 MOVX@R,A Move A to external 2
JNCaddr Jump on carry = 0 2 2 data memory
JZaddr Jump on A zero 2 2 MOVPA,@A Move to A from 2
JNZaddr Jump ·on A not zero 2 2 current page
JTOaddr Jump onTO = 1 2 2 MOVP3A,@A Move to A from 2
JNTOaddr Jump on TO = 0 2 2 page 3
JT1 addr JumponT1 = 1 2 2
TIMER/COUNTER
JNT1 addr JumponT1 = 0 . 2 2
MOVA,T Read
JFOaddr Jump on FO = 1 2 2
timer/counter
JF1 addr JumponF1 = 1 2 2 MOVT,A Load
JTFaddr Jump on timer flag 2 2 timer/counter
JNI addr Jump on INT = 0 2 2 STRTT Start timer
JBb addr Jump on 2 2 STRTCNT Start counter
accumulator bit STOP TCNT Stop timer/counter
EN TCNTI Enable timer/
SUBROUTINE counter interrupt
CALLaddr Jump to subroutine 2 2 DIS TCNTI Disable timer!
RET Return 1 2 counter interrupt
RETR Return and restore 1 2
CONTROL
status
ENI Enable external
interrupt
FLAGS D!S! Disable external
CLRC Clear carry interrupt
CPLC Complement carry SELRBO Select register
CLRFO Clear flag 0 bank 0
CPLFO Complement flag 0 1 SELRB1 Select register
CLRF1 Clear flag 1 1 bank 1
CPLFI Complement flag 1 1 SELMBO Select memory
DATA MOVES bank 0
MOVA,R Move register to A SELMB1 Select memory
MOVA,@R Move data memory bank 1
toA ENTOCLK Enable clock
MOVA, "'data Move immediate 2 2 output on TO
toA NOP No operation
4-24
inter 087 48H/087 49H
ABSOLUTE MAXIMUM RATINGS* 'Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O°C to + 70°C age to the device. This is a stress rating only and
Storage Temperature .......... - 65°C to + 150°C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage On Any Pin With Respect
tional sections of this specification is not implied Ex-
to Ground ...................... - 0.5V to + 7V
posure to absolute maximum rating conditions for
Power Dissipation ....................... 1.0 Watt extended periods may affect device reliability.
NOTICE Specifications contained within the
fol/owing tables are subject to change.
D.C. CHARACTERISTICS TA = O°C to + 70°C·, Vee = Voo = 5V+ 10%·, Vss
- = OV
Limits
Symbol Parameter Unit Test Conditions Device
Min Typ Max
VIL Input Low Voltage (All -0.5 0.8 V All
Except RESET, X1, X2)
VIL1 Input Low Voltage -0.5 0.6 V All
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V All
(All Except XTAL1,
XTAL2, RESET
VIH1 Input High Voltage 3.8 Vee V All
(X1, X2, RESET)
VOL Output Low Voltage (BUS) 0.45 V IOL = 2.0mA All
Vou ~ut Low Voltage 0.45 V IOL = 1.8 mA All
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0.45 V IOL = 1.0 mA All
(PROG)
VOL3 Output Low Voltage 0.45 V IOL = 1.6 mA All
(All Other Outputs)
VOH Output High Voltage (BUS) 2.4 V IOH = -400 p.A All
VOH1 ~ut High Voltage 2.4 V IOH = -100 p.A All
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40 p.A All
(All Other Outputs)
lu Leak~ Current ±10 p.A Vss S; VIN S; Vee All
(T1,INT)
IU1 Input Leakage Current -500 /A-A Vss + 0.45 .:::; VIN S; Vee All
(P10-P17, P20-P27,
EA,SS)
IU2 Input Leakage Current -10 -300 /A-A Vss S; VIN S; 3.8V All
RESET
ILO Leakage Current ±10 /A-A Vss S; VIN S; Vee All
(BUS, TO) (High
Impedance State)
100 + lee Total Supply Current' 80 100 mA 8748H
95 110 mA 8749H
NOTE:
'Icc + IDD is measured with all outputs disconnected; ss, RESET, and INT equal '0 Vee; EA equal to Vss.
4-25
intJ D8748H/D8749H
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = voo = 5V ±10%;Vss = OV
f(t) 11 MHz Conditions
Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1/xtal freq 90.9 1000 ns (Note 3)
tLL ALE Pulse Width 3.5t - 170 150 ns
tAL Addr Setup to ALE 2t - 110 70 ns (Note 2)
tLA Addr Hold from ALE t - 40 50 ns
tCC1 Control Pulse Width (RD, WR) 7.5t - 200 480 ns
tcC2 Control Pulse Width (PSEN) 6t - 200 350 ns
tow Data Setup before WR 6.5t - 200 390 ns
two Data Hold after WR t - .50 40 ns
tOR Data Hold (RD, PSEN) 1.5t - 30 0 110 ns
tR01 RDto Data In 6t - 170 375 ns
tR02 PSEN to Data In 4.5t - 170 240 ns
tAW Addr Setup to WR 5t - 150 300 ns
tA01 Addr Setup to Data (RD) 10.5t - 220 730 ns
tA02 Addr Setup to Data (PSEN) 7.5t - 200 460 ns
tAFC1 Addr Float to RD, WR 2t - 40 140 ns (Note 2)
tAFC2 Addr Float to PSEN 0.5t - 40 10 ns (Note 2)
tLAFC1 ALE to Control (RD, WR) 3t - 75 200 ns
tLAFC2 ALE to Control (PSEN) 1.5t - 75 60 ns
tCA1 Control to ALE (RD, WR, PROG) t - 65 25 ns
tcA2 Control to ALE (PSEN) 4t - 70 290 ns
tcp Port Control Setup to PROG 1.5t - 80 50 ns
tpc Port Control Hold to PROG 4t - 260 100 ns
tpR PROG to P2 Input Valid 8.5t - 120 650 ns
tpF Input Data Hold from PROG 1.5t 0 140 ns
Output Data Setup C:+ _ ')on 250 ns
top VL "'''''''
tpo Output Data Hold 1.5t - 90 40 ns
tpp PROG Pulse Width 10.5t - 250 700 ns
tpL Port 2 1/0 Setup to ALE 4t - 200 160 ns
tLP Port 2 1/0 Hold to ALE 0.5t - 30 15 ns
tpv Port Output from ALE 4.5t + 100 510 ns
IoPRR TO Rep Rate 3t 270 ns
tcv Cycle Time 15t 1.36 15.0 /los
NOTES:
1. Control outputs CL = 80 pF; BUS outputs CL = 150 pF.
2. BUS High Impedance Load 20 pF.
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.
4-26
inter D8748H/D8749H
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY WRITE TO EXTERNAL DATA MEMORY
1== --I ILAFcl~IY
ILL '1
ALE. J L________~I~--~L .
ALE J L
IAFd2 1- ICC2 --l f- ICA2
PSEN
ADDRESS
210983-6
210983-4
READ FROM EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS
--/tLAFC1L
ALE Jr-----,IL...----:1_ _ _ _-' l 2.4V - - - - - . . , - -_ _
tCA11- O.45V _ _ _ ----'X~:~: TEST POtNTS::~:~X,-_ _ __
RD
210983-7
A.C. testing inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Output timing measurements are made at 2.0V
for a Logic "I" and 0.8V for a Logic "0."
210983-5
4-27
D8748H/D8749H
PORT 1/PORT 2 TIMING
I~.IPL --l- I· CYCLE
2ND
ALE
1
PSEN
P20-23 I
OUTPUT PCH P,?RT 20-23 DATA NEW P20-23 DATA I PCH
'-------~I
P24-27 -t--'------'--'------------7----.-!.--____
P10-17 PORT 24-27, PORT 10-17 DATA NEW PORT DATA
OUTPUT. -t---~-----------~-------f~-------~I---
ILP
--1 I-ICA1
~ . IIPD
~IDP
EXPANDER "-IPL~
- 1 - - - - I L A - - - " + '..
PORT
OUTPUT
~ _ _ _ _ _ _ _- J
PCH 1 rp-O-R-T-20--2-3-D-A-TA-;'1 I PORT CONTROL OUTPUT DATA I
"'" "'
I
I I, I;)
EXPANDER , IPR -----I"~I Fl
PORT
INPUT PCH
r------,. 'I I"
PROG
210983-8
CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE
C1
~_-r-_----1_ _---j2 XTAL1
~
. I 11-11
C2 :::;o~-::,:: c!:3HZ
=- L--.jl
II T I 31 XTA!..:!
C3
210983-9
Cl = S pF ±% pF + (STRAY < S pF)
C2 = (CRYSTAL + STRAY) < 8 pF 210983-10
C3 = 20 pF ±1 pF (STRAY < S pF)
Crystal series resistance should be less than 301l at 11 MHz; less
than 7SIl at 6 MHz; less than 1801l at 3.6 MHz.
4-28
inter D8748H/D8749H
DRIVING FROM EXTERNAL SOURCE WARNING
An attempt to program a missocketed 8749H
+5V
(8748H) will result in severe damage to the part. An
47011 indication of a properly socketed part is the appear-
2 XTAL1
)0-+----=-1 ance of the ALE clock output. The lack of this clock
may be used to disable the programmer.
47011 The ProgramlVerify sequence is:
'-----'--,3;;-1 XTAL2 1) Voo = 5V, Clock applied or internal oscillator op-
210983-11
erating. RESET = OV, TEST 0 = 5V, EA = 5V,
For XTAL1 and XTAL2 define "high" as voltages above 1.6Vand BUS and PROG floating. P10 and P11 must be
"low" as voltages below 1.6V. The duty cycle requirements for tied to ground. . .
externally driving XTAL1 and XTAL2 using the circuit shown
above are as follows: XTAL1 must be high 35-65% of the period 2) Insert 8749H (8748H) in programming socket.
and XTAL2 must be high 36-65% of the period. Rise and fall
times must be faster than 20 ns. 3) TEST 0 = OV (select program mode)
4) EA = 18V (activate program mode)
5) Address applied to BUS and P20-22
PROGRAMMING, VERIFYING AND 6) RESET = 5V (latch address)
ERASING THE 8749H (8748H) EPROM 7) Data applied to BUS
8) Voo = 21V (programming power)
Programming Verification 9) PROG = Vee or float followed by one 50 ms
pulse to 18V
In brief, the programming process consists of: acti-
10) Voo = 5V
vating the program mode, applying an address,
latching the address, applying data, and applying a 11) TEST 0 = 5V (verify mode)
programming pulse. Each word is programmed com- 12) Read and verify data on BUS
pletely before moving on to the next and is followed 13) TEST 0 = OV
by a verification step. The following is a list of the
pins used for programming and a description of their 14) RESET = OV and repeat from step 5
functions: 15) Programmer should be at conditions of step 1
when 8749H (8748H) is removed from socket.
Pin Function
XTAL 1 Clock Input (3 to 4.0 MHz)
XTAL2
RESET Initialization and Address Latching
TEST 0 Selection of Program or Verify Mode
EA Activation of ProgramlVerify Modes
BUS Address and Data Input
Data Output During Verify
P20-P22 Address Input
Voo· Programming Power Supply
PROG Program Pulse Input
4-29
D8748H/D8749H
A.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA= 25°C ±5°C; VCC = 5V ±5%; VOO = 21V ±0.5V
Symbol Parameter Min Max Unit Test Conditions
tAW Address Setup Time to RESET t 4tCY
tWA Address Hold Time after RESET t 4tCY
tow Data in Setup Time to PROG t 4tCY
two Data il"! Hold Time after PROG J.. . 4tCY
tpH RESET Hold Time to Verify 4tCY
tvoow Voo Hold Time before PROG t 0 1.0 ms
tVOOH Voo Hold Time after PROG J.. 0 1.0 ms
tpw Program Pulse Width 50 60 ms
tTW TEST 0 Setup Time for Program Mode 4tCY
twr TEST 0 Hold Time after Program Mode 4tCY
too TEST 0 to Data Out Delay 4tCY·
tww RESET Pulse Width to Latch Address 4tCY
t r• tl Voo and PROG Rise and Fall Times 0.5 100 /ks
tCY CPU Operation Cycle Time 3.75 5 /ks
tRE RESET Setup Time before EA t 4tCY
..
NOTE:
If TEST 0 is high, too can be triggered by RESET· t .
D.C. SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA = 25°C ±5°C; Vcc = 5V ±5%; Voo = 21V ±0.5V
Symbol Parameter Min Max Unit Test Conditions
VOOH Voo Program Voltage High Level 20.5 21.5 V
VOOL VOO Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High Level 17.5 . 18.5 V
VPL PROG Voltage Low Level 4.0 Vcc V
VEAH EA Program or Verify Voltage High Level 17.5 18.5 V
100 VOO High Voltage Supply Current 20.0 mA
IpROG PROG High Voltage Supply Current 1.0 mA
lEA EA High Voltage Supply Current 1.0 mA
4-30
intJ D8748H/D8749H
WAVEFORMS
COMBINATION PROGRAM/VERIFY'MODE (EPROMs ONLY)
VEAH
EA
Vee __+_J
I-------PROGRAM-------t--VERIFY--t----PROGRAM-
Vee
TO
VIL1
Vee
RESET
VIL1
IAW+----r~+IWA
DBO-DB7 ==>--- DATA TO BE
PROGRAMMED VALID
__ -{NEXT AODRX=
VALID
LAST NEXT
ADDRESS ADDRESS
V;:'DH tyDDW~r~~
VDDL----------~~ I I ~--------------------------------
PRoi:: _ _ _ - _______ :~EV__TI~: __________________. 210983-12
VERIFY MODE
\~ __--J/ \~-
DBO-DB7 ==>--- ADDRESS
(0-7) VALID - - -< ,-_ _
NI:XT X
A_DD_R...;.E",;S;,;;S_J
NEXT DATA)-
OUT VALID
____-J)('-____ A_D_D_RE_S_S_(_8-_9_)V_A_L_ID_ _ _ ~)(~_ _ _ _ _N_E_X_T_A_D_D_R_E_SS_V_A_L_ID_ __
210983-13
4·31
intJ D8748H/D8749H
SUGGESTED EPROM VERIFICATION ALGORITHM FOR HMOS-E DEVICE ONLY
INITIAL.EPROM DUMP CYCLE SUBSEQUENT EPROM DUMP CYCLES
ALE
,(NOTE1) : (OUTPUT)
,
+18V I ,
EA-----.J : (INPUT) I
,,
,I ,,,
DB----I ADDRESS H
L....--'("'"IN"'"P""UT=-)-..1
ROM DATA
(OUTPUT)
H,
ADDRESS
(INPUT)
~-~-------
(OUTPUT):
I
, TO, RESET - - - - - - - - ' , (INPUT)
,,
P20·P23 ---i.____A_D_D_R_ES_S_ _ _--4Hl__--=A::DD:R:E::S:S_'_~..t-----~--
: (INPUT)
210983-14
48H 49B Vee = Vee = +5V
Vss = OV
A10 o ADDR
A11 o o
NOTE:
ALE is function of X1. X2 inputs.
4-32
MCS®-48
EXPRESS
• O°C to 70°C Operation
• - 40°C to + 85°C Operation
• 168 Hr. Burn-In
• 8048AH/8035AHL • 8748H
• 8049AH/8039AHL • 8243
• 8050AH/8040AHL • 8749H
The new Intel EXPRESS family of single-component 8-bit microcomputers offers enhanced processing options
to the familiar 8048AH/8035AHL. 8748H. 8049AH/8039AHL. 8749H. 8050AH/8040AHL Intel components.
These EXPRESS products are designed to meet the needs of those applications whose operating require-
ments exceed commercial standards. but fall short of military conditions.
The EXPRESS options include the commercial standard and -40·C to + 85°C operation with or without 168
±8 hours of dynamic burn-in at 125·C per MIL-STD-883. method 1015. Figure 1 summarizes the option
marking designators and package selections.
For a complete description of 8048AH/8035AHL. 8748H. 8049AH/8309AHL. 8749H. 8040AHL and 8050AH
features and operating characteristics, refer to the respective standard commercial grade data sheet. This
document highlights only the electrical specifications which differ from the respective commercial part.
I Temp Range ·C 0-70 -40-+85 0-70 -40-+85
I Burn In OHrs OHrs 168 Hrs 168 Hrs
P8048AH TP8048AH QP8048AH LP8048AH
D8048AH TD8048AH QD8048AH LD8048AH
D8748H TD8748H QD8748H LD8748H
P8035AHL TP8035AHL QP8035AHL LP8035AHL
D8035AHL TD8035AHL QD8035AHL LD8035AHL
P8049AH TP8049AH QP8049AH LP8049AH
D8049AH TD8049AH QD8049AH LD8049AH
D8749H TD8749AH QD8749H LD8749AH·
P8039AHL TP8039AHL QP8039AHL LP8039AHL
D8039AHL TD8039AHL QD8039AHL LD8039AHL
P8050AH TP8050AH QP8050AH LP8050AH
D8050AH TD8050AH QD8050AH LD8050AH
P8040AHL TP8040AHL QP8040AHL LP8040AHL
D8040AHL TD8040AHL QD8040AHL LD8040AHL
P8243 TP8243 QP8243 -
D8243 TD8243 QD8243 LD8243
• Commercial Grade
P Plastic Package
o Cerdip Package
September 1987
4-33 Order Number: 270225-002
MCS@·48 EXPRESS
Extended Temperature ElectrIcal Specification Deviations·
TP8048AH/TP8035AHL/LP8048AH/LP8035AHL
TD8048AH/TDB035AHL/LD8048AH/LD8035AHL
D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo = sv ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL1, XTAL2, RESEn
100 Voo Supply Current 4 8 rnA
100 + Icc Total Supply Current 40 80 rnA
TP8049AH/TP8039AHL/LP8049AH/LP8039AHL
TD8049AH/TD8039AHL/LD8049AH/LD8039AHL
D.C. CHARACTERISTICS TA = -40·Cto +8S·C; Vee = Voo = SV ±10%; Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL 1, )ITAL2, RESET)
100 Voo Supply Current S 10 rnA
100 + Icc Total Supply Current SO 100 rnA
. TP8050AH/TP8040AHL/LP8050AHL/LP8040AHL
TD8050AH/TD8040AHL/LD8050AH/LD8040AHL
D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL1, XTAL2, RESEn
100 Voo Supply Current 10 20 rnA
100 + Icc Total Supply Current 7S 120 rnA
4-34
MCS®-48 EXPRESS
Extended Temperature Electrical Specification Deviations'
TD8748H/LD8748H
D.C. CHARACTERISTICS TA = -40·Cto + 85·C; vee = voo = 5V ±10%;Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL1, XTAL2, RESET)
100 + lee Total Supply Current 50 130 mA
TD8749H/LD8749H·
D.C. CHARACTERISTICS TA = -40·C to + 85·C; Vee = Voo = 5V ± 10%; Vss = OV
Limits
Symbol Parameter Unit Test Conditions
Min Typ Max
VIH Input High Voltage (All Except 2.2 Vee V
XTAL 1, XTAL2, RESET)
100 + lee Total Supply Current 75 150 mA
TP8743/TD8243/LD8243
D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = OV
limits
Symbol Parameter Unit Test Conditions
Min I Typ I Max
lee
. ..
Vee Supply Current I 15 I
..
• Refer to ind,v,dual commercIal grade data sheet for complete operatIng characteristIcs.
25 rnA
4-35
MCS®-48 INDEX
8
8243 Expander, 2-4 I/O Expander Device (8243), 2-4
8243 Port Characteristics, 2-5 I/O Expansion, 2-4; 2-5
I/O Port Characteristics,.2-5
I/O Port Restore, 2-2
A Instruction Decoder, 1-1
Instruction Fetch (External), 2-1
Accumulator, 1-1 INT, 1-17
Addressing Beyond 2K, 2-1 Interrupt, 1-5, 1-7
Addressing External Data Memory, 2-4 Interrupt Routines, 2-2
ALE, 1-17,2-9 'Interrupt Timing, 1-7
ALU, 1-1
Arithmetic Logic Unit, 1-1
M
B Memory Bank Switch, 2-1
Memory Bank Switching, 2-8
Bus, 1-5, 1-17, 2-9 Memory Expansion; 2-5
Multi-Chip Systems, 2-7
c
o
Clock Circuits, 1-9
Conditional Branches, .1-6 Oscillator, 1-9
Control Signals, 2-8
Counter, 1-7
Cycle Counter, 1-10 p
Pin Description, 1-16
D Port 1, 1-5, 1-17
Port 2, 1-5, 2-9
Data Memory, 1-3 Port Characteristics, 2-9
Power Down, 1-13
PROG, 1-17,2-9
E Program Counter, 1-5
Program Memory, 1-1
EA, 1-15 Program Status Word; i-6
Erasing EPROM, 1-18 Programming EPROM, 1-18
Erasure Characteristics, 1-18 PSEN,2-9
Event Counter, 1-9 PSW, 1-6
Expansion of Data Memory, 2-3
Expansion of I/O, 2-4
Expansion of Program Memory, 2-1 R
Extended Addressing, 2-1
External Access Mode, 1-15 RD, 1-17, 2-9
External Data Memory Addressing, 2-4 Read Cycle, 2-3
External Instruction Fetch, 2-1 Reset, 1-10, 1-17
Restoring I/O Ports, 2-2
4-36
s v
Single Step, 1-11, 1-14 Vee, 1-17
Stack, 1-5 VDD,I-17
State Counter, 1-10 Verifying EPROM, 1-18
Sync Mode, 1-15 VSS, 1-17
T W
TO, 1-5, 1-17 WR, 1-17,2-9
TI, 1-5, 1-17 Write Cycle, 2-3
Test Inputs, 1-5
Timer, 1-7, 1-9
Timing, 1-13
Timing Circuits, 1-9
4-37
MCS® . . 51 Architectural
Overview
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ARCHITECTURAL OVERVIEW
OF THE MCS®-S1 FAMILY OF MICROCONTROLLERS
MEMBERS OF THE FAMILY
The MCS®-Sl family of microcontrollers consists of the devices listed in Table 1. The basic architectural structure of
these devices is shown in Figure 1. .
i-------.
I I
I I
I I
I I
I I
I I
I I
I I
EXTERNAL
8K ROM
IN 8052 j-·------I 1-------·
INTERRUPTS I
I I (8052)
TIMER2 ~~----l
I
I
256 BYTES COUNTER
4K RAM IN 8052 TIMER 1 INPUTS
ROM
128 BYTES
RAM TIMER 0
TXD RXD
ADDRESS/DATA
270251-1
Figure 1. Block Diagram of the 8051/8052AH
Table 1. The MCS®-51 Family of Microcontrollers
Device ROMless EPROM ROM RAM 16-Bit Ckt
Name Version Version Bytes Bytes Timers Type
8051 8031 (8751) 4K 128 2 HMOS
8051AH 8031AH 8751H 4K 128 2 HMOS
8052AH 8032AH 8752BH 8K 256 3 HMOS
80C51BH 80C31BH 87C51 4K 128 2 CHMOS
83C51FA 80C51FA 87C51FA 8K 256 4 CHMOS
83C152 80C152 87C152 8K 256 2 CHMOS
5-1
intJ MCS®·51 ARCHITECTURAL OVERVIEW
8051 80C51BH
The 8051 is the original member of the MCS-51 Fami- The 80C51BH is the CHMOS verSion of the 8051.
ly, and has been in production since 1981. Among the Functionally, it is fully compatible with the 8051, but
features of the 8051 are: being CMOS it draws less current than its HMOS
• 8-bit CPU optimized for control applications counterpart. To further exploit the power savings avail-
able in CMOS circuitry, two reduced power modes are
• Extensive Boolean processing (single-bit logic) added:
capabilities
• Software-invoked Idle Mode, during which the CPU
• 32 bidirectional and individually addressable I/O is turned off while the RAM and other. on-chip
lines peripherals continue operating. In this mode, cur-
• 128 bytes of on-chip Data RAM rent draw is reduced to about 15% of the current
• Two 16-bit timer/counters drawn when the device is fully active.-
• Full duplex UART • Software-invoked Power Down Mode, during which
all on-chip activities are suspended. The on-chip
• 5-source interrupt structure with 2 priority levels RAM continues to hold its data. In this mode the
• On-chip clock oscillator device typically draws less than 10 p.A.
• 4K bytes of on-chip Program Memory
Although the 80C51BH is functionally compatible with
• 64K Program Memory address space its HMOS counterpart, specific differences between the
• 64K Data Memory address space two types of devices must be considered in the design of
an application circuit if one wishes to ensure complete
The 8031 differs from the 8051 in not having the on- interchangeability between the HMOS and .CHMOS
chip Program ROM. Instead, the 8031 fetches all in- devices. These considerations are discussed in the Ap-
structions from external memory. plication Note AP-252, "Designing with the
8OC51BH".
The EPROM version of the 8051, the 8751, is no longer
in production. It has been superseded by the 8751H. The ROMIess version of the 80C5IBH is the
80C3IBH. The EPROM version is the 87C51.
8051AH
83C51FA
The 8051AH is identical to the 8051, but is fabricated
The 83C51FA is an enhanced version of the 80C51BH
with HMOS II technology. It is pin-for-pin compatible
with the 8051. and is backwards compatible with the 80C51BH. The
new features which have been incorporated are as fol-
The ROMless version of the 8051AH is the 8031AH. lows:
The EPROM version is the 8751H. • Programmable Counter Array with
Compare/Capture
High Speed Output
8052AH Pulse Width Modulator
Watchdog Timer
~ The 8052AH is an enhanced 8051. It is fabricated with • Programmable Serial Channel
HMOS II technology, and is backwards compatible Automatic Address Recognition
with the 8051. Its enhancements over the 8051 are as Framing Error Detection
follows:
• Enhanced Power Down Mode
• 256 bytes of on-chip Data RAM
• Up/down timer/counter
• Three timer/counters
• 8 Kbytes of on-chip Program ROM
• 6-source interrupt structure
• 256 bytes of on-chip Data RAM
• 8K bytes of on-chip Program ROM
• 7-source interrupt structure
The ROMless version of the 8052AH is the 8032AH.
The EPROM version is the 8752BH. For further information on these new features, refer to
the "Hardware Description of the 83C51FA" chapter.
A separate product, the 8052AH-BASIC, is an
8052AH with a full BASIC interpreter in the on-chip The ROMless version of the 83C51FA is the80c51FA.
ROM. . The EPROM version is the 87C51FA.
5-2
inter MCS®-51 ARCHITECTURAL OVERVIEW
PROGRAM MEMORY
(READ ONLY) ________ _ DATA MEMORY __ ______ _
'<~~2~~~T:t
.------------------------
FFFFH: ...---., FFFFH:
EXTERNAL
EXTERNAL
INTERNAL
FFH.tp------
,,
"
EA=O
EXTERNAL
EA=1
INTERNAL
,,
1-"""2:--'+- 0000 -+L-_ _..1 00 0000 L...,..---r...J
.--.--~-------------------
270251-2
Figure 2. MCS®·51 Memory Structure
83C152 The ROMless version of the 83ClS2 is the 80ClS2.
There is no EPROM version for the 83ClS2 but a ver-
The 83C152 is an enhanced version of the 80CSIBH sion is offered which has an additional two ports which
and is 100% compatible with code written for the can be connected to an EPROM for ROM develop-
80CSIBH. Some of the new features which have been ment.
incorporated are:
• Global Serial Channel (GSC)-
A high speed serial communication link capable of MEMORY ORGANIZATION IN
transmitting data in excess of 2 Mbps in either MCS®·51 DEVICES
HDLC or CSMA/CD protocols.
• Two DMA Channels- Logical Separation of Program and
Each DMA channel is capable of transferring Data Memory
64 Kbytes of data. Options include: automatic ad·
dressing, automatic servicing of the GSC or UART, All MCS-Sl devices have separate address spaces for
alternate cycle transfers, and burst data transfers. Program and Data Memory, as shown in Figure 2. The
The source andlor destination can be internal logical separation of Program and Data Memory allows
RAM, external RAM, or SFR memory space. Most the Data Memory to be accessed by 8-bit addresses,
DMA transfers take 1 machine cycle to complete. which can be more quickly stored and manipulated by
• Port 4-:- an 8-bit CPU. Nevertheless, 16-bit Data Memory ad-
The 83ClS2 has added an additional port called dresses .can also be generated through the DPTR regis·
port 4. Because of the added port, the 83ClS2 is ter.
available in 48·pin DIP or 68·pin PLCC packages.
• 8 Kbytes of on-chip program ROM Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory. In
• 2S6 bytes of on-chip data RAM the 80S1, 80S1AH,80C5IBH, and their EPROM ver-
• 11 interrupt vectors sions, the lowest 4K bytes of Program Memory are on·
chip. The 80S2AH, 83CSIFA, and .83ClS2 provide 8
For more information oli the 83ClS2 please refer to the Kbytes of on-chip Program Memory storage. In the
"Hardware Description" chapter on this product.
5-3
MCS®-51 ARCHITECTURAL OVERVIEW
ROMless versions all Program Memory is' external. The lowest 4K (or 8K, in the 8052AH, 83C51FA and
The read strobe for external Program Memory is the 83CI5~) bytes of Program Memory can be either in the
signal PSEN (Program Store Enable). on-chip ROM or in an external ROM. This selection is
made by strapping the EA (External Access) pin to
Data Memory occupies a separate address space from either Vee or Vss.
Program Memory. Up to 64K bytes of external RAM
can be addressed in the external Data Memo~ace. In the 8051 and its derivatives, if the EA pin is strapped
The CPU generates read and write signals, RD and to Vco then program fetches' to addresses OOOOH
WR, as needed during external Data Memory accesses. through OFFFH are directed to the internal ROM. Pro-
gram fetches to addresses l000H through FFFFH are
External Program Memory and external Data Memory directed to external ROM.
may be combined if desired by applying the RD and
PSEN signals to the inputs of an AND gate and using In the 8052AH and the other 8K ROM parts, EA =
the output of the gate as the read strobe to the external Vee selects addresses OOOOH through lFFFH to be in-
Program/Data memory. ternal, and addresses 2000H through FFFFH to be ex-
ternai.
Program Memory If the EA pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMless
Figure 3 shows a map of the lower part ofthe Program parts (8031, 8032AH, etc.) must have this pin external-
Memory. After reset, the CPU begins execution from ly strapped to Vss to enable them to execute from ex-
location OOOOH. ternal Program Memory.
As shown in Figure 3, each interrupt is assigned a fixed The read strobe to external ROM, PSEN, is used for all
location in Program Memory. The interrupt causes the, external program fetches. PSEN is not activated for in-
CPU to jump to that location, where it commences exe- ternal program fetches.
cution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External In-
terrupt 0 is going to be used, its service routine must
begin at location 0003H. If the interrupt is not going to EPROM
be used, its service location is available as general pur-
pose Program Memory.
LATCH
(0033H) P2~=====:;)f
002BH
iJ
270251-4
0023H
INTERRUPT 00' BH Figure 4. Executing from External
LOCATIONS [ :::::=t 8
BYTES
Program Memory
The hardware configuration for external program exe-
cution is shown in Fignre 4. Note that 16 I/O lines
, 0003H
(Ports 0 and 2) are dedicated to bus functions during
RESET , OOOOH
external Program Memory fetches., Port 0 (pO in Figure
270251-3 4) serves as a multiplexed' address/data bus. It emits
the low byte of the Program Counter (PCL) as an ad-
Figure 3. MCS®-51 Program Memory dress, and then goes into a float state awaiting the arriv-
al of the code byte from the Program Memory. During
The interrupt service locations are spaced at 8--byte in- the time that the low byte of the Program Counter is'
tervals: 0003H for External Interrupt 0, OOOBH for valid on PO, the signal ALE (Address Latch Enable)
Timer 0, OO13H for External Interrupt 1, 001BH for clocks this byte into an address latch. Meanwhile, Port
Timer 1, etc. If an interrupt service routine is short 2 (P2 in Figure 4) emits the high byte of the Program
enough (as is often the case in control applications), it Counter (pCR). Then PSEN strobes the EPROM and
can reside entirely within that 8-byte interval. Longer the code byte is read into the microcontroller. '
service routines can use it jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
5-4
MCS®-51 ARCHITECTURAL OVERVIEW
Program Memory addresses are always 16 bits wide, Internal Data Memory is mapped in Figure 6. The
even though the actual amount of Program Memory memory space is shown divided into three blocks,
used may be less than 64K bytes. External program which are generally referred to as the Lower 128, the
execution sacrifices two of the 8-bit ports, PO and P2, to Upper 128, and SFR space.
the function of addressing the Program Memory.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
Data Memory However, the addressing modes for internal RAM can
in fact accommodate 384 bytes, using a simple trick.
The right half of Figure 2 shows the internal and exter- Direct addresses higher than 7FH access one memory
nal Data Memory spaces available to the MCS-51 user. space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Up-
Figure 5 shows a hardware configuration for accessing per 128 and SFR space occupying the same block of
up to 2K bytes of external RAM. The CPU in this case addresses, 80H through FFH, although they are physi-
is executing from internal ROM. Port 0 serves as a cally separate entities.
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during exter- 7FH
nal RAM accesses.
BANK 2FH
SELECT T-ADDRESSABLE SPACE
BITS IN } BI
,...------./1 DATA (B IT ADDRESSES 0-7F)
PSW~ 20H
11{ 18H
lFH
17H
10{ 4 BANKS OF
10H
8 REGISTERS
OFH
01 { R0-R7
08H
00 {
0
07H - RESET VALUE OF
STACK POINTER
270251-7
270251-5 Figure 7. The Lower 128 Bytes of Internal RAM
Figure 5. Accessing External Data Memory. The Lower 128 bytes of RAM are present in all
If the Program Memory Is Internal, the Other MeS-51 devices as mapped in Figure 7. The lowest 32
Bits of P2 are Available as 110. bytes are grouped into 4 banks of 8 registers. Program
instructions callout these registers as RO through R7.
There can be up to 64K bytes of external Data Memo- Two bits in the Program Status Word (PSW) select
ry. External Data Memory addresses can be either 1 or which register bank is in use. This allows more efficient
2 bytes wide. One-byte addresses are often used in con- use of code space, since register instructions are shorter
junction with one or more other I/O lines to page the than instructions that use direct addressing.
RAM, as shown in Figure 5. Two-byte addresses can
also be used, in which case the high address byte is
emitted at Port 2. FFH
FFHP--------r----., FFH NO BIT-ADDRESSABLE
: ACCESSIBLE ACCESSIBLE SPACES
UPPER I BY INDIRECT BY DIRECT
128 I ADDRESSING ADDRESSING AVAILABLE AS STACK
80H: ONLY SPACE IN 8052AH.
80H 83C51 FA. 83C152
7FH ACCESSIBLE
LOWER BY DIRECT
~ SPECIAL } PORTS NOT IMPLEMENTED IN 8051
FUNCTION STATUS AND
128 AND INDIRECT
REGISTERS CONTROL BITS
ADDRESSING
OL-_ _- - ' TIMER
REGISTERS
STACK POINTER 80H
ACCUMULATOR 270251-8
(ETC.)
270251-6 Figure 8. The Upper 128 Bytes of Internal RAM
Figure 6. Internal Data Memory
5·5
inter MCS®-51 ARCHITECTURAL OVERVIEW
I CY I AC I Fa I RSll RSO I ov I Ip I
PSW 7 ,J L PSW 0
CARRY FLAG RECEIVES CARRY OUT PARITY OF ACCUMULATOR SET
FROM BIT 1 OF ALU OPERANDS BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0
PSW 6i - - PSW 1
AUXILIARY CARRY FLAG RECEIVES USER DEFINABLE FLAG
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW 5 PSW 2
GENERAL PURPOSE STATUS FLAG OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS
, PSW 4 PSW 3
REGISTER BANK SELECT BIT 1 REGISTER BANK SELECT BIT 0
270251-10
Figure 10, PSW (Program Status Word) Register in MCS®·51 Devices
The next 16 bytes above the register banks form a block Sixteen addresses in SFR space are both byte- and bit-
of bit-addressable memory space. The MCS-51 instruc- addressable. The bit-addressable SFRs are those whose
tion set includes a wide selection of single-bit instruc- address ends in OOOB. The bit addresses in this area are
tions, and the 128 bits in this area can be directly ad- 80H through FFH.
dressed by these instructions. The bit addresses in this
area are OOH through 7FH.
THE MCS®·51 INSTRUCTION SET
All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128 All members of the MCS-51 family execute the same
(Figure 8) can only be accessed by indirect addressing. instruction set. The MCS-51 instruction set is opti-
The Upper 128 bytes of RAM are not implemented in mized for 8-bit control applications. It provides a vari-
the 8051, but are in the 8052AH, 83C51FA, and ety of fast addressing modes for accessing the internal
83C152. RAM to facilitate byte operations on smaIl data struc-
tures. The instruction set provides extensive support for
Figure 9 gives a brief look at the Special Function Reg- one-bit variables as a separate data type, allowing direct
ister (SFR) space. SFRs include the Port latches, tim- bit manipulation in control and logic systems that re-
ers, peripheral controls, etc. These registers can only be quire Boolean processing.
accessed by direct addressing. In general, all MCS-51
microcontrollers have the same SFRs as the 8051, and An overview of the MCS-51 instruction set is presented
at the same addresses in SFR space. However, enhance- below, with a brief description of how certain instruc-
ments to the, 8051 have additional SFRs that are not tions might be used. References to "the assembler" in
present in the 8051, nor perhaps in other proliferations this discussion are to Intel's MCS-51 Macro Assembler,
of the family. ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler Us-
er's Guide (Order No. 9800937 for ISIS Sysiems, Ordet
rrH ,, No. 122752 for DOS Systems).
REGISTER-MAPPED PORTS
EOH ACC
ADDRESSES THAT END IN Program Status Word
, OH OR 8H ARE ALSO
BIT-ADDRESSABLE '
The Program Status Word (pSW) ,contains several
BOH PORT 3
status bits that reflect the current state of the CPU. The
, -PORT PINS
-ACCUMULATOR PSW, shown in Figure 10, resides in SFR space. It con-
-PSW tains the Carry bit, the Auxiliary Carry (for BCD oper-
AOH PORT 2 '(ETC.)
ations), the two register bank select bits, the Overflow
90H PORT 1
flag, a Parity bit, and two user-defmable status flags.
I The Carry bit, other than serving the functions of a
SOH PORT 0
Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.
270251-9
Figure 9. SFR Space
5-6
MCS®-51 ARCHITECTURAL OVERVIEW
The bits RSO and RSI are used to select one of the four IMMEDIATE CONSTANTS
register banks shown in Figure 7. A number of instruc-
tions refer to these RAM locations as RO through R7. The value of a constant can follow the opcode in Pro-
The selection of which of the four banks is being re- gram Memory. For example,
ferred to is made on the basis of the bits RSO and RS 1
at execution time. MOV A, #100
The Parity bit reflects the number of Is in the Accumu- loads the Accumulator with the decimal number 100.
lator: P = 1 if the Accumulator contains an odd num- The same number could be specified in hex digits as
ber of Is, and P = 0 if the Accumulator contains an 64H.
even number of Is. Thus the number of Is in the Accu-
mulator plus P is always even.
INDEXED ADDRESSING
Two bits in the PSW are uncommitted and may be used Only Program Memory can be accessed with indexed
as general purpose status flags. addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Addressing Modes Program Counter) points to the base of the table, an.d
The addressing modes in the MCS-51 instruction set the Accumulator is set up with the table entry number.
are as follows: The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.
DIRECT ADDRESSING
Another type of indexed addressing is used in the "case
In direct addressing the operand is specified by an 8-bit jump" instruction. In this case the destination address
address field in the instruction. Only internal Data of a jump instruction is computed as the sum of the
RAM and SFRs can be directly addressed. base pointer and the Accumulator data.
INDIRECT ADDRESSING
Arithmetic Instructions
In indirect addressing the instruction specifies a register
which contains the address of the operand. Both inter- The menu of arithmetic instructions is listed in Table 2.
nal and external RAM can be indirectly addressed. The table indicates the addressing modes that can be
used with each instruction to access the <byte> oper-
The address register for 8-bit addresses can be RO or and. For example, the ADD A, <byte> instruction can
RI of the selected register bank, or the Stack Pointer. be written as:
The address register for 16-bit addresses can only be the
16-bit "data pointer" register, DPTR. ADD A,7FH (direct addressing)
ADD A,@RO (indirect addressing)
ADD A,R7 (register addressing)
REGISTER INSTRUCTIONS ADD A,#127 (immediate constant)
The register banks, containing registers RO through R7, The execution times listed in Table 2 assume a 12 MHz
can be accessed by certain instructions which carry a clock frequency. All of the arithmetic instructions exe-
3-bit register specification within the opcode of the in- cute in 1 ,""S except the INC DPTR instruction, which
struction. Instructions that access the registers this way takes 2 '""~, and the Multiply and Divide instructions,
are code efficient, since this mode eliminates an address which take 4 ,""s.
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four Note that any byte in the internal Data Memory space
banks is selected at execution time by the two bank can be incremented or decremented without going
seleCt bits in the PSW. through the Accumulator.
One of the INC instructions operates on the 16-bit
REGISTER-5PECIFIC INSTRUCTIONS
Data Pointer. The Data Pointer is used to generate
Some instructions are specific to a certain register. For 16-bit addresses for external memory, so being able to
example, some instructions always operate on the Ac- increment.it in one 16-bit operation is a useful feature.
cumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. In- The MUL AB instruction multiplies the Accumulator
structions that refer to the Accumlator as A assemble by the data in the B register and puts the 16-bit product
as accumulator-specific opcodes. into the concatenated B and Accumulator registers.
5-7
intJ MCS®-51 ARCHITECTURAL OVERVIEW
Table 2. A Li~t of the MCS®-51 Arithmetic Instructions
Addressing Modes Execution
Mnemonic Operation
Olr Ind Reg Imm Time (/Ls)
ADD A,<byte> A = A + <byte> X X X X 1
ADDC A, < byte> A = A + <byte> + C X X X X 1
SUBB A, <byte> A = A - <byte> - C X X X X 1
INC A A=A+1 Accumulator only 1
INC <byte> <byte> = <byte> + 1 X X X 1
INC DPTR DPTR = DPTR + 1 Data POinter only 2
DEC A A=A-1 Accumulator only 1
DEC <byte> <byte> = <byte> - 1 X X X 1
MUL AB B:A = BxA ACC and B only 4
DIV AB A = Int [AlB] 4
ACC and B only
B = Mod [AlB]
DA A Decimal Adjust Accumulator only 1
The DIV AB instruction divides the Accumulator by completes the shift in 4 /Ls and leaves the B register
the data in the B register and leaves the 8-bit quotient holding the bits that were shifted out.
in the Accumulator, and the 8-bit remainder in the B
register. The DA A instruction is for BCD arithmetic opera-
tions. In BCD arithmetic, ADD and ADDC instruc-
Oddly enough, DIV AB finds less use in arithmetic tions should always be followed by a DA A operation,
"divide" routines than in radix conversions and pro-· to ensure that the result is also in BCD. Note that DA
grammable shift operations. An example of the use of A will not convert a binary number to BCD. The DA
DIV AB in a radix conversion will be given later. In A operation produces a meaningful result only as the
shift operations, dividing a number by 2n shifts its n second step in the addition of two BCD bytes.
bits to the right. Using DIV AB to perform the division
Table 3. A List of the MCS®-51 Logical Instructions
Addressing Modes Execution
Mnemonic Operation
Oir Ind Reg Imm Time (/Ls)
ANL A,<byte> A = A .AND. <byte> X X X X 1
ANL <byte> ,A <byte> = <byte> .AND. A X 1
ANL <byte>,#data <byte> = <byte> .AND. #data X 2
A _ A '"'0 .......... .+ ...........
ORL A, <byle> 1"\ - n .vn ........ uy ..' C ' X X X X 1
ORL <byte> ,A <byte> = <byte> .OR. A )( 1
ORL <byte> ,#data <byte> = <byte> .OR. #data X 2
XRL A,<byte> A = A .XOR. <byte> X X X X .1
XRL <byte> ,A <byte> = <byte>.XOR.A X 1
XRL < byte> , # data <byte> = <byte> .XOR. #data X 2
CRL A A = OOH Accumulator only 1
CPL A A = .NOT.A Accumulator only 1
RL A Rotate ACC Left 1 bit Accumulatoronly 1
RLC A Rotate Left through Carry Accumulator only 1
RR A Rotate ACC Right 1 bit Accumulator only· 1
RRC A Rotate Right through Carry Accumulator only 1 ..
SWAP A Swap Nibbles in A Accumulator only. 1
5-8
inter MCS®-51 ARCHITECTURAL OVERVIEW
Logical Instructions The SWAP A instru.:;tion interchanges the high and
low nibbles within the Accumulator. This is a useful
Table 3 shows the list of MCS-51 logical instructions. operation in BCD manipulations. For example, if the
The instructions that perform Boolean operations Accumulator contains a binary number which is known
(AND, OR, Exclusive OR, NOT) on bytes perform the to be less than 100, it can be quickly converted to BCD
operation on a bit-by-bit basis. That is, if the Accumu- by the following code:
lator contains OOllOlOlB and <byte> contains
OlOlOOllB, then MOY B,#l0
DIY AB
ANL A, <byte> SWAP A
ADD A,B
will leave the Accumulator holding OOOlOOOlB.
Dividing the number by 10 leaves the tens digit in the
The addressing modes that can be used to access the low nibble of the Accumulator, and the ones digit in the
<byte> operand are listed in Table 3. Thus, the ANL B register. The SWAP and ADD instructions move the
A, <byte> instruction may take any of the forms tens digit to the high nibble of the Accumulator, and
the ones digit to the low nibble.,
ANL A,7FH (direct addressing)
ANL A,@RI (indirect addressing)
ANL A,R6 (register addressing) Data Transfers
ANL A,#53H (immediate constant)
INTERNAL RAM
All of the logical instructions that are Accumulator-
specific execute in I/Ls (using a 12 MHz clock). The Table 4 shows the menu of instructions that are avail-
others take 2 /Ls. able for moving data around within the internal memo-
ry spaces, and the addressing modes that can be used,
Note that Boolean operations can be performed on any with each one. With a 12 MHz dock, all of these in-
byte in the internal Data Memory space without going structions execute in either I or 2 /Ls.
through the Accumulator. The XRL <byte>, #data
instruction, for example, offers a quick and easy way to The MOY <dest>, <src> instruction allows data to
invert port bits, as in be transferred between any two internal RAM or SFR
locations without going through the Accumulator. Re-
XRL PI,#OFFH member the Upper 128 byes of data RAM can be ac-
cessed only by indirect addressing, and SFR space only
If the operation is in response to an interrupt, not using by direct addressing.
the Accumulator saves the time and effort to stack it in
the service routine. Note that in all MCS-51 devices, the stack resides in
, on-chip RAM, and grows upwards. The PUSH instruc-
The Rotate instructions (RL A, RLC A, etc.) shift the tion first increments the Stack Pointer (SP), then copies
Accumulator 1 bit to the left or right. For a left rota- the byte into the stack. PUSH and POP use only direct
tion, the MSB rolls into the LSB position. For a right 'addressing to identify the byte being saved or restored,
rotation, the LSB rolls into the MSB position.
Table 4. A List of the MCS®-S1 Data Transfer Instructions that Access Internal Data Memory Space
Addressing Modes Execution
Mnemonic Operation
Dir Ind Reg Imm Time (/Ls)
MOV A, <src> - A"C <src> X X X X 1
MOV <dest>,A <dest> = A X X X 1
MOV <dest>, <src> <dest> = <src> X X X X 2
MOV DPTR,#data16 DPTR = 16-bit immediate constant. X 2
PUSH <src> INC SP: MOV "@SP",<src> X 2
POP <dest> MOV <dest>, "@SP" : DEC SP X 2
XCH A, <byte> ACC and <by1e> exchange data X X X 1
XCHD A,@Ri ACC and @Ri exchange low nibbles X 1
5-9
inter MCS®-51 ARCHITECTURAL OVERVIEW
but the stack itself is accessed by indirect addressing After the routine has been executed, the Accumulator
using the SP register. This means the stack can go into contains the two digits that were shifted out on the
the Upper 128, if they are implemented, but not into right. Doing the routine with direct MOYs uses 14 code
SI:R space. bytes and 9 ,""S of execution time (assuming a 12 MHz
clock). The same operation with XCHs uses less code
The Upper 128 are not implemented in the 8051, and executes almost twice as fast.
8051AH, or 8OC51BH, nor in their ROMless or
EPROM counterparts. With these devices, if the SP To right-shift by an odd number of digits, a one-digit
points to the Upper 128, PUSHed bytes are lost, and shift must be executed. Figure 12 shows a sample of
POPped bytes are indeterminate. code that will right-shift a BCD number one digit, us-
ing the XCHD instruction. Again, the contents of the
The Data Transfer instructions include a 16-bit MOY registers holding the number and of the Accumulator
that can be used to initialize the Data Pointer (DPTR) are shown alongside each instruction.
for look-up tables in Program Memory, or for 16-bit
external Data Memory accesses.
The XCH A, <byte>, instruction causes the Accumu- MOV R1.#2EH
lator and addressed byte to exchange data. The XCHD MOV RO.#2DH
A,@Ri instruction is similar, but only the low nibbles loop for R1 = 2EH:
are involved in the exchange. LOOP: MOV A.@R1 00 12 34 56 78 78
XCHD A.@RO 00 12 34 58 7876
To see how XCH and XCHD can be used to facilitate SWAP A 00 12 34 58 78 67
data manipulations, consider first the problem of shift- MOV @R1;A 00 12 34 58 67 67
ing an 8-digit BCD number two digits to the right. Fig- DEC R1 00 12 34 58, 67 67
ure 11 shows how this can be done using direct MOYs, DEC RO 00 12 34 58 67 67
and for comparison how it can be done using XCH CJNE R1.#2AH.LOOP
instructions. To aid in understanding how the code loop for R1 = 2DH:
works, the contents of the registers that are holding the loop for R1 = 2CH: 00112138145167145
100 18 23 45 67 23
BCD number and the content of the Accumulator are loop for R1 = 28H: 08 01 23 45 67 01
shown alongside each instruction to indicate their
status after the instruction has been executed.
CLR A
XCH A.2AH I
081 01 1231451671 00
00 01 23 45 67 08
Figure 12. Shifting a BCD Number
2A 28 2C 20 2E ACC One Digit to the Right
MOV A,2EH 00 12 34 56 78 78
MOV 2EH,2DH 00 12 34 56 56 78 First, pointers Rl and RO are set up to point to the two
MOV 2DH,2CH 00 12 34 34 56 78 bytes containing the last four BCD digits. Then a loop
MOV 2CH,28H 00 12 12 34 56 78 is executed which leaves the last byte, location 2EH.
MOV 28H,#0 00 00 12 34 56 78
holding the last two digits of the shifted nuthber. The
(a) Using direct MOVs: 14 bytes, 9 p.s pointers are decremented, and the loop is repeated for
I 2A I 28 I 2C I 20 I 2E I ACC location 2DH. The CJNE instruction (Compare and
CLR
XCH
A I 00 112 1 34 1 56 1 78 I 00
12
Jump if Not Equal) is a loop control that will be de-
scribed later.
XCH A.2BH I 00
A.2CH 00 I 00
00 1 34
12 55 1 78
56 78 I 34
XCH A.2DH 00 00 12 1 34 78 56 The loop is executed from LOOP to CJNE for Rl =
XCH A.2EH 00 00 12 34 56 78 2EH, 2DH, 2CH and 2BH. At that point the digit that
(b) Using XCHs: 9 bytes. 5 p.s was originally shifted out on the right has propagated
to location 2AH. Since that location should be left with
Figure 11. Shifting a BCD Number Os, the lost digit is moved to the Accumulator.
Two Digits to the Right
5-10
MCS®-51 ARCHITECTURAL OVERVIEW
EXTERNAL RAM Table 6. The MCS®-51 Lookup
Table Read Instructions
Table 5 shows a list of the Data Transfer instructions Execution
that access external Data Memory. Only indirect ad- Mnemonic Operation
Time (ILS)
dressing can be used. The choice is whether to use a
MOVC A,@A+DPTR Read Pgm Memory 2
one-byte address, @Ri, where Ri can be either RO or aI(A+DPTR)
Rl of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using l6-bit addresses if MOVC A,@A+PC Read Pgm Memory 2
at (A+PC)
only a few K bytes of external RAM are involved is
that l6-bit addresses use all 8 bits of Port 2 as address
bus. On the other hand, 8-bit addresses allow one to The first MOVC instruction in Table 6 can accommo-
address a few K bytes of RAM, as shown in Figure 5, date a fable of up to 256 entries, numbered 0 through
without having to sacrifice all of Port 2. 255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
All of these instructions execute in 2 /Ls, with a beginning of the table. Then
12 MHz clock.
Table 5. A List of the MCS®-51 Data MOVC A,@A+DPTR
Transfer Instructions that Access
copies the desired table entry into the Accumulator.
External Data Memory Space
Address
Mnemonic Operation
Execution The other MOVC instruction works the same way, ex-
Width Time (ILS) cept the Program Counter (PC) is used as the table
8 bits MOVXA,@Ri
Read external
2
base, and the table is accessed through a subroutine.
RAM@Ri First the number of the desired entry is loaded into the
Write external Accumulator, and the subroutine is called:
8 bits MOVX@Ri,A 2
RAM@Ri
Read external MOV A,ENTRY_NUMBER
16 bits MOVX A,@DPTR 2 CALL TABLE
RAM@DPTR
Write external
16 bits MOVX @DPTR,A 2 The subroutine "TABLE" would look like this:
RAM@DPTR
TABLE: MOVC A,@A + PC
Note that in all external Data RAM accesses, the Ac- RET
cumulator is always either the destination or source of
the data. The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
The read and write strobes to external RAM are acti- have up to 255 entries, numbered 1 through 255. Num-
vated only during the execution of a MOVX instruc- ber 0 can not be used, because at the time the MOVC
tion. Normally these signals are inactiye, and in fact if instruction is executed, the PC contains the address of
they're not going to be used at all, their pins are avail- the RET instruction. An entry numbered 0 would be
able as extra 110 lines. More about that later. the RET opcode itself.
LOOKUP TABLES
Boolean Instructions
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since MCS-51 devices contain a complete Boolean (single-bit)
thesC1 instructions access only Program Memory, the processor. The internal RAM contains 128 addressable
lookup tables can only be read, not updated. The mne- bits, and the SFR space can support up to 128 other
monic is MOVC for "move constant". addressable bits. AIl of the port lines are bit-address-
able, and each one can be, treated as a separate single-
'If the table access is to external Program Memory, then bit port. The instructions that access these bits are not
the read strobe is PSEN. just conditional branches, but a complete menu of
move, set, clear, complement, OR, and AND instruc-
tions. These kinds of bit operations are not easily ob-
tained in other architectures with any amount of byte-
oriented software.
5-11
MCS®-51 ARCHITECTURAL OVERVIEW
Table 7. A List of the MCS®-S1 Note that the Boolean instruction set includes ANL
Boolean Instructions and ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
Execution software. Suppose, for example, it is required to form
Mnemonic Operation
Time (,....s) the Exclusive OR of two bits:
ANL C,bit C = C .AND. bit 2
C = bit! .xRL. bit2
ANL C,/bit C = C .AND .. NOT. bit 2
ORL C,bit C = C.OR. bit 2 The software to do that could be as follows: -
ORL C,/bit C = C .OR. .NOT. bit 2
MOV C,bitl
MOV C,bit C = bit '1 JNB bit2,OVER
MOV bit,C bit = C 2 CPL C
OVER: (continue)
CLR C C=O 1
CLR bit bit = 0 1 First, bit! is moved to the Carry. If bit2 = 0, then _C
SETS C C=1 1 now contains the correct result. That is, bit! .xRL. bit2
= bit! if bit2 = O. On the other hand, if bit2 = 1 C
SETS bit bit = 1 1 now contains the complement of the correct result. I(
CPL C C = .NOT.C 1 need only be inverted (CPL C) to complete the opera-
tion;
CPL bit bit = .NOT. bit 1
JC rei JumpifC =1 2 This code uses the JNB instruction, one of -a series of
JNC rei JumpifC = 0 2 bit-test instructions which execute a jump if the ad-
dressed bit is set (JC, JB, JBC) or if the addressed bit is
JB bit,rel Jump if bit =1 2 not set (JNC, JNB). In the above case, bit2 is being
JNS bit, rei Jump if bit =0 2 tested, and if bit2 = 0 the CPL C instruction is jumped
JSC bit,rel Jump if bit = 1; CLR bit 2 over.
JBC executes the jump if the addressed bit is set, and
The instruction set for the Boolean processor is shown also clears the bit. Thus a flag can be tested and cleared
in Table 7. All bit accesses are by direct addressing. Bit in one operation.
addresses OOH through 7FH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space. All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
Note how easily an internal flag can be moved to a port available to the bit-test instructions.
pin:
MOV C,FLAG RELATIVE OFFSET
MOV P1.0,C
The destination address for these jumps is specified to
In this example, FLAG is the name of any addressable the assembler by a label or by an actual address in
bit in the Lower 128 or SFR space. An 110 line (the Program Memory.' However, the destination address
LSB of Port 1, in this case) is set or cleared depending aSSembleS to a relative offSet byte. This is a signed
on whether the flag bit is 1 or O. (two's complement) offset byte which is added to the
PC in two's complement arithmetic if the jump is exe-
The Carry bit in the PSW is used as the single-bit Accu- cuted.
mulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carrycspecific The range of the jump is therefore -128 to + 127 Pro-
instructions (CLR C, etc). The Carry bit also has a gram Memory bytes relative to the first byte following
direct address, since it resides in the PSW register, the instruction.
which is bit-addressable.
5-12
intJ MCS®-51 ARCHITECTURAL OVERVIEW
Jump Instructions the Accumulator. Typically, DPTR is set up with the
address of a jump table, and the Accumulator is given
Table 8 shows the list of unconditional jumps. an index to the table. In a 5-way branch, for example,
an integer 0 through 4 is loaded into the Accumulator.
Table 8. Unconditional Jumps The code to be executed might be as follows:
in MCS®-S1 Devices
Execution MOY DPTR,#JUMP_TABLE
Mnemonic Operation Time (p.s) MOY A,INDE~NUMBER
RL A
JMP addr Jump to addr 2 , JMP @A+DPTR
JMP @A+DPTR Jump to A+ DPTR 2
CALL addr Call subroutine at addr 2 The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
RET Return from subroutine 2 because each entry in the jump table is 2 bytes long:
RETI Return from interrupt 2
NOP No operation 1 JUMP_TABLE:
AJMP CASE_O
AJMP CASE_I
The Table lists a single "JMP addr" instruction, but in AJMP CASE~
fact there are three-SJMP, UMP and AJMP-which AJMP CASE..;...3
differ in the format of the destination address. JMP is a AJMP CASE_4
generic mnemonic which can be used if the program-
mer does not care which way the jump is encoded. Table 8 shows a single "CALL addr" instruction, but
there are two of them-LCALL and ACALL-which
The SJMP instruction encodes the destination address differ in the format in which the subroutine address is
as a relative offset, as described above. The instruction given to the CPU. CALL is a generic mnemoni~ which
is 2 bytes long, consisting of the opcode and the relative can be used ifthe programmer does not care which way
offset byte. The jump distance is limited to a range of the address is encoded.
-128 to + 127 bytes relative to the instruction follow-
ing the SJMP. The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Pro-
The UMP instruction encodes the destination address gram Memory space. The ACALL'instruction uses the
as a 16-bit constant. The instruction' is 3 bytes long, II-bit format, and the subroutine must be in the same
consisting of the opcode and two address bytes. The 2K block as the instruction following the ACALL.
destination address can be anywhere in the 64K Pro-
gram Memory space. In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or
The AJMP instruction encodes the destination address as a 16-bit constant. The assembler will put the address
as an ll-bit constant. The instruction is 2 bytes long, into the correct forinat for the given instructions.
consisting of the opcode, which itself contains 3 of the
II address bits, followed by another byte containing the Subroutines should end with a RET instruction, which'
low 8 bits of the destination address. When the instruc- returns execution to the instruction following the
tion is executed, these II bits are simply substituted for CALL.
the low II bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K RETI is' used to return from an interrupt service rou-
block as the instruction following the AJMP. tine. The only difference between RET and RETI is
that RET! tells the interrupt control system that the
In all cases the programmer specifies the destination interrupt in progress is done. If there is no interrupt in
address to the assembler in the same way: as a label or progress at the time RETI is executed, then the RET!
as a 16-bit constant. The assembler will put the destina- is functionally identical to RET.
tion address into the correct format for the given in-
struction. If the format required by the instru,<tion will Table 9 shows the list of conditional jumps available to
not support the distance to the specified destination ad- the MCS-51 user. All of these jumps specify the desti-
dress, a "Destination out of range" message is written nation address by the relative offset method, and so are
into the List file. liInited to a jump distance of -128 to + 127 bytes from
the instruction following the conditional jump instruc-
The JMP @A + DPTR instruction supports case tion. Important to note, however, the user specifies to
jumps. The destination address is computed at execu- the assembler the actual destination address the same
tion time as the sum of the 16-bit DPTR register and way as the other jumps: as a label or a 16-bit constant.
5-13
inter MCS®-S1 ARCHITECTURAL OVERVIEW
Table 9. Conditional Jumps In MCS®-51 Devices
Addressing Modes Execution
Mnemonic Operation
Dir Ind Reg Imm Time (,...s)
JZ rei Jump if A = 0 Accumulator only 2
jNZ rei Jump if A "* 0 Accumulator only 2
DJNZ <byte> ,rei Decrement and jump if not zero X X 2
CJNE A, < byte> ,rei Jump if A"* <byte> X X 2
CJNE < byte> , # data,rel Jump if <byte> "* #data X X 2
There is no Zero bit in the PSW. The, JZ and JNZ
instructions test the Accumulator data for that condi- Ill>
IICS -51
tion. HIIOS
OR CHIIOS
.....-t---jXTAL2
The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loop N times, QUA~~ ~~~~~ ' ....
RESONATOR
load a counter byte with N and terminate the loop with '--~-+-I XTAL 1
a DJNZ to the beginning, of the loop, as shown below
VSS
for N = 10:
-= '-----...,J
270251-11
MOY COUNTER,# 10
LOOP: (begin loop) Figure 13. Using the On-Chip OSCillator
•
Ill>
(end loop) IICS -51
HIIOS
DJNZ COUNTER,LOOP OR CHIIOS
(continue) XTAL2
The CJNE instruction (Compare and Jump if Not EXTERNAL
Equal) can also be used for loop control as in Figure 12. CLOCK
SIGNAL
XTAL1
Two bytes are speCified in the operand field of the in- VSS
struction. The jump is 'executed only if the two bytes
are not equal. In the example of Figure 12, the two 270251-12
bytes were the data in RI and the constant 2AH. The A. HMOS or CHMOS
initial data in RI was 2EH. Every time the loop was
executed, RI was decremented, and the looping was to
~
IICS":.'51
continue until the RI data reached 2AH. ' HIIOS
EXTERNAL ONLY
, CLOCK XTAL2
Another application of this instruction is in "greater SIGNAL,
than, less than" comparisons. The two bytes in the op-
erand fieid are iaken as unsigned iniegers. If the first is
less than the second, then the Carry bit is se~ (I). If the
frrst is greater than or equal to the second, then the
Carry bit is cleared. 270251-13
B.HMOSOnly
CPU TIMING Ill>
IICS -51
CHIIOS
All MCS-51 microcontrollers have an on-chip oscillator ONLY
which can be used, if desired as the clock source for the , (NC) XTAL2
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALl and XTAL2 EXTERNAL
pins of the microcontroller, and Capacitors to ground as CLOCK XTAL1
SIGNAL
shown in Figure 13. VSS
,270251-14
C. CHMOS Only
Figure 14. Using an External Clock
5-14
inter MCS®~51 ARCHITECTURAL OVERVIEW
Examples of how to drive the clock with an external Machine Cycles
oscillator are shown in Figure 14. Note that in the
HMOS devices (8051, etc.) the signal at the XTAL2 pin A machine cycle consists' of a sequence of 6 states,
actually drives the internal clock generator. In the numbered SI through S6. Each state time lasts for two
CHMOS devices (80C51BH, etc.) the signal at the oscillator periods. Thus a machine cycle takes 12 oscil-'
XTALl pin drives the internal clock generator. If only lator periods or 1 JLs if the oscillator frequency is
one pin is going to be driven with the external oscillator 12 MHz.
signal, make sure it is the right pin.
Each state is divided into a Phase 1 half and a'Phase 2
The internal clock generator defines the sequence of half. Figure 15 shows the fetch/execute sequences in
states that make up the MCS-51 machine cycle.
OSC.
I Sl 1 S21 S3 I I
~~~~~~~~~~~~~~~~~~~~~~~~~~
54 S5 1 56 1 Sl I I S2 53 1 54 I I
55 S6 1 Sl 1
(XTAL2)
ALE
_[ _R:~D NEXT OPCODE AGAI,!,
-- - - - - .----I~--r---r-..L.-._-,r---,
______ ~~_-L_~_~~~~
(A) 1-byle. 1-cyclelnstruc"on. e.g., INC A.
I
I READ OPCODE.
I
: _ [_R:~D NEXT OPCODE.
--------~~-~-_r~.--r_~
________ L-:..:.....J--=:......L.~-'- _ _'___'----j
(8) 2-byte, 1-cycle Instruction, e.g" ADD A, #data
READ OPCODE.
READ NEXT
OPCODE (DISCARD),
(C) 1-byle, 2-cyclolnatuctlon, •.g.,.INC DPTR.
I
READOPCODE
(MOYX). . NO
READ NEXT OPCODE AGAIN. D
I
NO FETCH, I
l I ____ _
______ L-~_~_~_~~~~ _ _'__ _'___~~--~--~------
DATA
(D) MOYX (l-byle, 2-cycle)
ACCESS EXTERNAL MEMORY
270251-15
Figure 15. State Sequences in MCS®-51 Devices
5-15
intJ MCS®·51 ARCHITECTURAL OVERVIEW
states and phases for various kinds of instructions. Nor- The fetch/execute sequences are the same whether the
mally two program fetches are generated during each Program Memory is internal or external ,to the chip.
machine cycle, even if the instruction being executed Execution· times do not depend on whether the Pro-
doesn't require it. If the instruction being executed gram Memory is internal or external.
doesn't need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incre- Figure 16 shows the signals an~ timing involved in pro-
mented. gram fetches when the Program Memory is external. If
Program Memory is external, then the Program Memo-
Execution of a one-cycle instruction (Figure l5A and ry read strobe PSEN is normally activated twice per
B) begins during State 1 ofthe machine cycle, when the machine cycle, as shown in Figure 16(A).
opcode is latched into the Instruction Register. A sec-
ond fetch occurs during S4 of the same machine cycle. If an access to external Data Memory occurs, as shown
Execution is complete at the end of State 6 of this ma- in. Figure 16(B), two PSENs are skipped, because the
chine cycle. address and data bus are being used for the Data Mem-
ory access.
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the sec- Note that a Data Memory bus cycle takes twice as
ond cycle of a MOVX instruction. This is the only time much time as a Program Memory bus cycle. Figure 16
program fetches are skipped. The fetch/execute se- shows the relative timing of the addresses being emitted
quence for MOVX instructions is shown in Figure at Ports'O and 2, and of ALE and PSEN. ALE is used
15(D). to latch the low address byte from PO into the address
latch.
ALE
PsEN
(A)
AD -------+----------~---------4----------~----~----~--- WITHOUT A
MOVX.
PCHOUT X PCHOUT
X PCHOUT
X PCHOUT
PO
, I
I
I I
I
tPCLOUT bCLouT lpCLOUT lpCLOUT
VALID VALID VALID VALID
CYCLE 1 -------"""1.------, CYCLE 2, . "'
1~lulas ~1~1~1~lulasl~1
ALE
PSEN
AD -------+-----------l-----, (8)
WITH A
MOVX.
270251-16
Figure 16. Bus Cycles In MCS@·51 Devices Executing from External Pr~gram Memory
5-16
inter MCS®-S1 ARCHITECTURAL OVERVIEW
When the CPU is executing from internal Program named IE (Interrupt Enable). This register also con-
Memory, PSEN is not activated, and program address- tains a global disable bit, which can be cleared to dis-
es are not emitted. However, ALE continues to be acti- able all interrupts at once. Figure 17 shows the IE reg-
vated twice per machine cycle and so is available as a ister for the 8052AH.
clock output signal. Note, however, that one ALE is
skipped during the execution of the MOVX instruction.
INTERRUPT PRIORITIES
Each interrupt source can also be individually pro-
Interrupt Structure grammed to one of two priority levels by setting or
cl~aring a bit in the SFR named IP (Interrupt Priority).
The 8051, 8051AH, and 80C51BH, and their ROMless
and EPROM versions, provide 5 interrupt sources: 2 Figure 18 shows the IP register in the 8052AH.
external interrupts, 2 timer interrupts, and the serial
p.ort i!lterrupt. The 8052AH provides these 5 plus a A low-priority interrrupt can be interrupted by a high-
Sixth mterrupt that is associated with the third timer! priority interrupt, but not by another low-priority inter- '
counter which is present in this device. Additional in- rupt. A high-priority interrupt can't be interrupted by
terrupts are available on the 83C51FA and 83C152. any other interrupt source.
Refer to the appropriate chapters on these devices for
further information on their interrupts. If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
What follows is an overview of the interrupt structure level is serviced. Ifinte~rupt requests of the same priori-
for these devices. More detailed information for specific ty level are received simultaneously, an internal polling
members .of the MCS-51 family is provided in the chap- sequence determines which request is serviced. Thus
ters of thiS handbook that describe the specific devices. within each priority level there is a second priority
structure determined by the polling sequence.
INTERRUPT ENABLES Figure 19 shows, for the 8052AH, how the IE and IP
registers and the polling sequence work to determine
Each of the interrupt sources can be individually en- which if any interrupt will be serviced.
abled or disabled by setting or clearing a bit in the SFR
(MSB) (LSB)
(MSB) (LSB)
IEA I-I ET2 I ES I ETI I EXI I ETO I EXO I I-I -I PT2 I PS I PTt I PXl I PTO I PXO I
Symbol Position Function
Symbol Position Function
IP.7 reserved
EA IE.7 disables all interrupts. If EA = O. no
IP.6 reserved
interrupt will be acknowledged. If EA
PT2 IP.5 defines the Timer 2 interrupt priority
= 1. each interrupt source is
level. PT2 = 1 programs it to the
individually enabled or disabled by
higher priority level.
setting or clearing its enable bit.
PS IP.4 defines the Serial Port interrupt
IE.6' reserved
priority level. PS = 1 programs it to
ET2 IE5 enables or disables the Timer 2
the higher priority level.
overflow or capture interrupt. If ET2
PTt IP.3 defines the Timer 1 interrupt priority
= O. the Timer 2 interrupt is disabled.
level. PTI = 1 programs it to the
ES lEA enables m disables the Serial Port
higher priority level.
interrupt. If ES = 0, the Serial Port
PXl IP.2 defines the Exlernai Interrupt 1
interrupt is disabled.
priority level. pxi = t programs it to
ETI IE.3 enables or disables the Timer 1
the higher priority level.
Overflow interrupt. If ETI = O. the
, PTO IP.l defines the Timer 0 interrupt priority
Timer 1 interrupt is disabled.
level. PTO = 1 programs it to the
EXI IE.2 enables or disables External Interrupt
higher priority level.
1. If EXI = 0, Exlernal Interrupt t is
PXO IP.O defines the Exlernal Interrupt 0
disabled.
priority level. PXO = 1 programs it to
ETO lEI enables or disables the Timer 0
the higher priority level.
Overflow interrupt If ETO = O. the
Timer 0 interrupt is disabled.
Figure 18. IP(lnterrupt Priority)
EXO lEO enables or disables Exlernal Interrupt
O. If EXO = 0, Exlernal Interrupt 0 is Register in the 8052AH
disabled.
Figure 17. IE (Interrupt Enable)
Register In the 8052AH
5-17
inter MCS@·51 ARCHITECTURAL OVERVIEW
HIGH PRIORITY
IP REGISTER INTERRUPT
I
I
I
I
T F O - - - - -......t-CI"" ~>t-I-<>-~_l_--+-+I INTERRUPT
POLLING
I SEQUENCE
I
I
O-o%c>t--r~-I--++I
I
I
I
I
T f 1 - - - - - -....... *'"""0' ~>t--jO-c,..-l---41
I
I
I
I
~>t--r~-l--W
RI
TI ").---"*-0'
Tf2
EXf2 (8052 ONLY)
INDIVIDUAL GLOBAL LOW PRIORITY
ENABLES DISABLE INTERRUPT
270251-17
Figure 19. 8052 Interrupt Control System
In operation, all the interrupt flags are latched into the pleted in less time than it takes other architectures to
interrupt control system during State 5 of every ma- commence them.
chine cycle. Th~ samples are polled during ~he follo~
ing machine cycle. If the flag for an enabled mterrupt IS
found to be set (I), the interrupt system generates an SIMULATING A THIRD PRIORITY LEVEL IN
LCALL to the appropriate location in Program Memo- SOFTWARE
ry, unless some other condition blocks the interrupt. Some appli~ations require more than the two priority
Several conditions can block an interrupt, among them levels that are provided by on-chip hardware in
that an interrupt of equal or higher priority level is MCS-SI devices. In these cases, relatively simple soft-:
already in progress. I
ware can be written to produce the same effect as a
third priority leveL
The hardware-generated LCALL causes the contents of
the Program Counter to be pushed onto the stack, a~d First, interrupts that are to have higher priority ~ha~ 1
reloads the PC with the beginning address of the service are assigned to priority 1 in the IP (Interrupt Pnonty)
routine. As previously noted (Figure 3), the service rou-. register. The service routines for priority 1 interrupts
tine for each interrupt begins at a fixed location. that are supposed" to be interruptible by "priority 2"
interrupts are written to include the following code:
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Hav- PUSH IE
ingonly the PC be automatically saved allows the p~o MOV IE,#MASK
grammer to deCide how much time to spend savmg CALL . LABEL
which other registers. This enhances the interrupt re- ._ •••• *
sponse time, albeit at the expense of increasing the pro- (execute service routine)
grammer's burden of responsibility. As a result, many •••••••
interrupt functions that are typical in control applica- POP IE
tions--':'toggling a port pin, for example, or reloading a RET
timer, or unloading a serial buffer--can often be com- LABEL: RET!
5-18
MCS®-51 ARCHITECTURAL OVERVIEW
As soon as any priority 1 interrupt is acknowledged, POPping IE restores the original enable byte. Then a
the IE (Interrupt Enable) register is re-defined so as to normal RET (rather than another RET!) is used to
disable all but "priority 2" interrupts. Then, a CALL to terminate the service routine. The additional software
LABEL executes the RETI instruction, which clears adds 10 ,...S ~at 12 MHz) to priority 1 interrupts.
the priority 1 interrupt-in-progress flip-flop. At this
point any priority 1 interrupt that is enabled can be
serviced, but only "priority 2" interrupts are enabled.
5-19
Hardware Description of the 6
8051,8052 and 80e51
intJ HARDWARE DESCRIPTION
OF THE 8051, 8052 AND 80C51
INTRODUCTION • The EPROM versions of the 80SIAH, 80S2AH,
and 80CSIBH
This chapter presents a comprehensive description of
the on-chip hardware features of the MCS®-SI micro- The devices under consideration are listed in Table 1.
controllers. Included in this description are As it becomes unwieldy to be constantly referring to
"each of these devices by their individual names, we will
• The port drivers and how they function both as
adopt a convention of referring to them generically as
ports and, for Ports 0 and 2, in bus operations
80S Is and 80S2s, unless a specific member of the group
• The Timer/Counters is being referred to, in which case it will be specifically
• The Serial Interface named. The "80S Is" include the 8051, 8051AH, and"
80CSlBH, and their ROMless and EPROM versions.
• The Interrupt System
The "80S2s" are the 80S2AH, 8032AH, and 87S2BH.
• Reset
• The Reduced Power Modes in the CHMOS devices Figure I shows a functional block diagram of the 80SIs
and 8052s.
Table 1. The MCS-51 Family of Microcontrollers
Device ROM less EPROM ROM RAM 16-bit Ckt
Name Version Version Bytes Bytes Timers Type
8051 8031 " (8751) 4K 128 2 HMOS
8051AH 8031AH 8751H 4K 128 2 HMOS
8052AH 8032AH 8752BH 8K 256 3 HMOS
80C51BH 80C31BH 87C51 4K 128 2 CHMOS
SpeCial Function Registers /
A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the 8052s but not in the 80S Is.
~
,--------
r
....
..
AU;
·R ....... lnIQUJID32on1'.
270252-1
Figure 1. MCS-51 Architectural Block Diagram
6-1
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
8 Bytes
F8 FF
FO B F7
E8 EF
EO ACC E7
08 OF
DO PSW 07
C8 (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2) CF
co C7
B8 IP BF
BO P3 B7
A8 IE AF
AO P2 .. A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOO TLO Tl1 THO TH1 8F
80 PO SP OPL OPH PCON 87
Figure 2. SFR Map. ( ... ) Indicates Resident in 8052s, not in 8051s
Note that not all of the addresses are occupied. Unoc- to hold a 16-bit address. It may be manipulated as a
cupied addresses are not implemented on the chip. 16-bit register or as two independent 8-bit registers.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect. PORTS 0 T03
User software should not write Is to these unimple- PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2
mented locations, since they may be used in future and 3, respectively.
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always SERIAL DATA BUFFER
be 0, and their active values will be 1.
The Serial Data Buffer is actually two separate regis-
The functions of the SFRs are outlined below. ters, a transmit buffer and a receive· buffer register.
When data is moved to SBUF, it goes to the transmit
ACCUMULATOR buffer where it is held for serial transmission. (Moving
ACC is the Accumulator register. The mnemonics for . a byte to SBUF is what initiates the transmission.)
Accumulator-Specific instructions, however, refer to When data is moved from SBUF, it comes from the
the Accumulator simply as A. receive buffer.
B REGISTER TIMER REGISTERS
The B register is used during mUltiply and divide oper- Register pairs (THO, TLO), (THI, TLI), and (TH2,
ations, For other instructions it can be treated as anoth- TL2) are the 16-bit Counting registers for Timer/Coun-
er scratch pad register. ters 0, I, and 2, respectively.
PROGRAM STATUS WORD CAPTURE REGISTERS
The PSW register contains program status information The register pair (RCAP2H, RCAP2L) are the. Cap-
as detailed in Figure 3. ture registers for the Timer 2 "Capture Mode." In this
mode, in response to a transition at the 8052's T2EX
STACK POINTER pin, TH2 and TL2 are copied into RCAP2H and
The Stack Pointer Register is 8 bits wide. It is incre- RCAP2L. Timer 2 also has a 16-bit auto-reload mode,
mented before data is stOred during PUSH and CALL and RCAP2H and RCAP2L hold the reload value for
executions. While the stack may reside anywhere in on- this mode. More about Timer 2's features in a later
chip RAM, the Stack Pointer is initialized to 07H after section.
a reset. This causes the stack to begin at location 08H.
CONTROL REGISTERS
DATA POINTER
Special Function Registers IP, IE, TMOD, TCON,
The Data Pointer (DPTR) consists of a high byte T2CON, SOON, and PCON contain control and status
(DPH) and a low byte (DPL). Its intended function is bits for the interrupt system, the Timer/Counters, and
the seri?-, port. They are described in later sections.
6-2
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
(MSB) (LSB)
CY AC FO RSI RSO OV P
Symbol Position Name and Significance Symbol Position Name and Significance
CY PSW.7 Carryllag. OV PSW.2 Overflow flag.
AC PSW.6 Auxiliary Carry flag. PSW.I User definable lIag.
(For BCD operations.) P PSW.O Parity flag.
FO PSW.5 Flag 0 Sell cleared by hardware each
(Available to the user for general instruction cycle to indicate an odd/
purposes.) even number of "one" bits in the
RSI PSW.4 Register bank select control bits I & Accumulator, i.e., even parity.
RSO PSW.3 O. Sellcleared by software to NOTE:
determine working register bank (see The contents of (RSI, RSO) enable the working register banks as
follows:
Note).
(O.O)-Bank 0 (00H-07H)
(0.1 )-Bank I (OBH-OFH)
(I.O)-Bank 2 (IOH-17H)
(I. I)-Bank 3 (IBH-IFH)
Figure 3. PSW: Program Status Word Register
ADDR/DATA READ
VCC .LATCH
CONTROL
INT. ",BU::.::S,--+~ WRITE
TO
WRITE LATCH
TO
LATCH
READ
READ PIN
PIN
270252-3
270252-2
B. Port 1 Bit
A. PortO Bit ALTERNATE
OUTPUT
FUNCTION
ADDR
READ
READ LATCH
LATCH
INT. BUS
INT. BUS WRITE
TO
WRITE LATCH
TO
LATCH
READ
PIN
ALTERNATE
INPUT
FUNCTION
270252-4
270252-5
C. Port 2 Bit
D. Port 3 Bit
Figure 4. 8051 Port Bit Latches and 1/0 Buffers
'See Figure 5 for details of the internal pullup.
PORT STRUCTURES AND external memory address, time-multiplexed with the
OPERATION byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
All four, ports in the 8051 are bidirectional. Each eon-' bits wide. Otherwise the Port 2 pins continue to emit
sists of a latch (Special Function Registers PO through the P2 SFR content.
P3), an output driver, and an input buffer.
All the Port 3 pins, and (in the 8052) two Port 1 pins
The output drivers of Ports 0 and 2, and the input buff- are multifunctional. They are not only port pins, but
ers of Port 0, are used in accesses to external memory. also serve the functions of various special features as
In this application, Port 0 outputs the low byte of the listed on the following page.
6·3
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Port Pin Alternate Function ADDR/DATA BUS). To be used as an input, the port
·Pl.0 T2 (Timer/Counter 2 bit latch must contain a I, which tums off the output
external input) driver PET. Then, for Ports I, 2, and 3, the pin is
·P1.l T2EX (Timer/Counter 2 pulled high by the internal pullup, but can be pulled
low by an external source.
Capture/Reload trigger)
P3.0 RXD (serial input port) Port 0 differs in not having internal pull ups. The pullup
P3.l TXD (serial output port) FET in the PO output driver (see Figure 4) is used only
P3.2 INTO (external interrupt) when the Port is emitting Is during external memory
P3.3 INT1 (external interrupt) accesses. Otherwise the pullup PET is off. Consequent-
P3.4 TO (Timer/Counter 0 external ly PO lines that are being used as output port lines are
input) open drain. Writing a 1 to the bit latch leaves both
P3.5 Tl (Timer/Counter 1 external output PETs off, so the pin floats. In that condition it
input) can be used a high-impedance input.
P3.6 WR (external Data Memory
Because Ports 1, 2, and 3 have fixed internal pullups
write strobe) they are sometimes called "quasi-bidirectional" ports.
P3.7 RD (external Data Memory When configured as inputs they pull high and will
read strobe) source current (ilL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
·Pl.O and P1.l serve these alternate functions only on "true" bidirectional, because when configured as an in-
the 8052. put it floats.
The alternate functions can only be activated if the cor- All the port latches in the 8051 have Is written to them
responding bit ,latch in the port SFR,contains a 1. Oth- by the reset function. If a 0 is subsequently written to a
erwise the porl pin is stuck at O. port latch, it can be reconfigured as an input by writing
altoit.
1/0 Configurations
Writing to a Port
Figure 4 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit In the execution of an instruction that changes the val-
latch (one bit in the port's SFR) is represented as a ue in a port latch, the new value arrives at the latch
Type D flip-flop, which will clock in a value from the during S6P2 of the final cycle of the instruction. How-
internal bus in response to a "write to latch" signal ever, port latches are in fact sampled by their output
from the CPU. The Q output of the flip-flop is placed buffers only during Phase 1 of any clock period. (Dur-
on the internal bus in response to a "read latch" signal ing Phase 2 the output buffer holds the value it saw
from the CPU. The level of the port pin itself is placed during the previous Phase 1). Consequently, the new
on the internal bus in response to a "read pin" signal value in the port latch won't actually appear at the
from the CPU. Some instructions that read a port acti- output pin until the next Phase I, which will be at SIPI
vate the "read latch"signal, and others activate the of the next machine cycle.
"read pin" signal. More about that later.
If the change requires a O-to-l transition in Port I, 2, or
As shown in Figure 4, the output drivers of Ports 0 and 3, an additional puiiup is turned on during SiPi and
2 are switchable to an internal ADDR and ADDR/ SIP2 of the cycle in which the transition occurs. This is
DATA bus by an internal CONTROL signal for use in done to increase the transition speed. The extra pullup
external memory accesses. During external memory ac- can source about 100 times the current that the normal
cesses, the P2 SFR remains unchanged, but the PO SFR pullup can. It should be noted thaf the internal pull ups
gets Is written to it: are field-effect transistors, not linear resistors. The pull-
up arrangements are shown in Figure 5.
Also shown in Figure 4, is that if a P3 bit latch contains
a I, then the output level is controlled by the signal In HMOS versions of the 8051, the fixed part of the
labeled "alternate output function." The actual P3.x pullup is a depletion-mode transistor with the gate
pin level is always available to the pin's alternate input wired to the source. This transistor will allow the pin to
function, if any. source about 0.25 mA when shorted to ground. In
parallel with the fixed pullup is an enhancement-mode
Ports 1,2, and 3 have internal pullups. Port 0 has open transistor, which is activated during SI whenever the
drain outputs. Each I/O line can be independently used port bit does a O-to-I transition. During this interval, if
as an' input or an output. (Ports 0 and 2 may not be the port pin is shorted to ground, this extra transistor
used as general purpose I/O when being used as the will allow the pin to source an additional 30 mAo
6-4
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
VCC
2 OSC. PERIODS ENHANCEMENT MODE FET
aD ~
270252-6
A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 osc. periods after Q makes a 1-to-0 transition.
Vcc Vcc Vcc
a
FROM PORT
LATCH
READ
PORT PIN
270252-7
B. CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q
makes a 1-to-0 transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch which holds the 1. pFET 2 is also on.
Figure 5. Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Except That It Holds The Strong Pull up On While Emitting
1s That Are Address Bits. (See Text, "Accessing External Memory".)
In the CHMOS versions, the pullup consists of three Port Loading and Interfacing
pFETs. It should be noted that an n-channel FET
(nFEl) is turned on when a logical 1 is applied to its The output buffers of Ports 1,2, and 3 can each drive 4
gate, and is turned off when a logical 0 is applied to its LS TIL inputs. These ports on HMOS versions can be
gate. A p-channel FET (PFET) is the opposite: it is on driven in a normal manner by any TIL or NMOS cir-
when its gate sees a 0, and off when its gate sees a 1. cuit. Both HMOS and CHMOS pins can be driven by
open-collector and open-drain outputs, but note that 0-
pFETl in Figure 5 is the transistor that is turned on for to-1 transitions will not be fast. In the HMOS device, if
2 oscillator periods after a 0-to-1 transition in the port the pin is driven by an open-collector output, a 0-tO-1
latch. While it's on, it turns on pFET3 (a weak pull- transition will have to be driven by the relatively weak
up), through the inverter. This inverter and pFET form depletion mode FET in Figure 5(A). In the CHMOS
a latch which hold the 1. device, an input 0 turns off pullup pFET3, leaving only
the very weak pullup pFET2 to drive the transition.
Note that ifthe pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3, Port 0 output buffers can each drive 8 LS TIL inputs.
causing the pin to go into a float state. pFET2 is a very They do, however, require external pullups to drive
weak pullup which is on whenever the nFET is off, in NMOS inputs, except when being used as the
traditional CMOS style. It's only about Y,0 the strength ADDRESS/DATA bus.
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.
6-5
HARDWARE DESCRIPTION OFTHE 8051, 8052 AND 80C51
Read-Modify-Write Feature Whenever a 1'6-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
Some instructions that read a port read the latch and duration of the read or write cycle. Note that the Port 2
others read the pin. Which ones do which? The instruc- drivers use the strong pullups during the entire time
tions that read the latch rather than the pin are the ones that they are emitting address bits that are Is. This is
that read a value, possibly change it, and then rewrite it during the execution of a MOVX @DPTR instruction.
to the latch. These are called "read-modify-write" in- During this time the Port 2 latch (the Special Function'
structions. The instructions listed below are read-mod- Register) does not have to contain Is, and the contents
ify-write instructions. When the destination operand is of the Port 2 SFR are not modified. If the external
a port, or a port bit, these instructions read the latch memory cycle is not immediately followed by another
rather than the pin: external memory cycle, the undisturbed contents of the
ANL (logical AND, e.g., ANL.PI, A) Port ~ SFR will reappear in the next cycle.
ORL (logical OR, e.g., ORL P2, A) If an 8-bit address is being used (MOVX @Ri), the
XRL (logical EX-OR, e.g., XRL P3, A) contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facili-
JBC (jump if bit = I and clear bit, e.g., tate paging.
JBC Pl.l, LABEL)
CPL (complement bit, e.g., CPL P3.0) In any case, the low byte of the address is time-multi-
plexed with the data byte on Port O. The ADDR/
INC (increment, e.g., INC P2) DATA signal drives both FETs in the Port 0 output
DEC (decrement, e.g., DEC P2) buffers. Thus, in this application the Port 0 pins are not
DJNZ (decrement and jump if not zero, e.g., open-drain outputs, and do' not require external pull-
DJNZ P3, LABEL) ups. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an extemallatch.
MOV, PX.Y, C (move carry bit to bit-Y of Port X) The address byte is valid at the negative transition of
CLR PX. Y (clear bit Y of Port X) ALE. Then, in a write cycle, the data byte to be written
SETB PX. Y (set bit Y of Port X) appears on Port 0 just before WR is ·activated, and re-
mains there until after WR is deactivated. In a read
It is not obvious that the last three instructions in this
cycle, the incoming byte is accepted at Port 0 just be-
list are read-modify-write instructions, but they are. fore the read strobe is deactivated.
They read the port byte, all 8 bits, modify the addressed During any access to external memory, the CPU writes
bit, then write the new byte back to the latch. OFFH to the Port 0 latch (the Special Function Regis-
ter), thus obliterating whatever information the Port 0
The reason that read-modify-write instructions are di- SFR may have been holding.
rected to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the External Program Memory is accessed under two con-
pin. For example, a port bit might be used to drive the ditions:
base of a transistor. When a 1 is written to the bit, the • 1) Whenever signal EA is· active; or
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the 2) Whenever the program counter (PC) contains a
base voltage of the transistor and interpret it as a O. number that is larger than OFFFH (IFFFH for the
Reading the latch rather than the pin will return the 8052).
correct value of 1. ' . This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K for the 8032) program
bytes to be fetched from external memory.
ACCESSING EXTERNAL MEMORY
When the CPU is executing out of external Program
Accesses to external memory are of two types: accesses Memory, all 8 bits of Port 2 are dedicated to an output
to external Program Memory and accesses to external function and may not be used for general purpose I/O.
Data Memory. Accesses to external Program Memory During external program fetches they output the high
use signal PSEN (program store enable) as the read byte of the PC. During this time the Port 2 drivers use
strobe. AccesseS to external Data Memory use RD or the strong pullups to emit PC bits that are Is.
WR (alternate functions of P3.7 and P3.6) to strobe the
memory..
TIMER/COUNTERS
Fetches from external Program Memory always use a The 8051 has two 16-bit Timer/Counter registers: Tim-
16-bit address. Accesses to external Data Memory can er 0 and Timer 1. The 8052 has these two plus one
use either a 16-bit address (MOVX @DPTR) or an mOt;"e: Timer 2. All three can be configured to operate
8-bit address (MOVX @Ri). either as timers or event counters.
6-6
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
In the "Timer" function, the register is incremented MODE 0
every machine cycle. Thus, one can think of it as count-
ing machine cycles. Since a !llachine cycle consists of 12 Putting either Timer into Mode 0 makes it look like an
oscillator periods, the count rate is '112 of the oscillator 8048 Timer, which is an 8-bit Counter with a divide-by-
frequency. 32 prescaler. Figure 7 shows the Mode 0 operation as it
applies to Timer 1.
, In the "Counter" function, the register is incremented
in response to a I-to-O transition at its corresponding In this mode, the Timer register is configured as a
external input pin, TO, TI or (in the 8052) T2. In this 13-Bit register. As the count rolls over from allis to all
function, the external input is sampled during S5P2 of Os, it sets the Timer interrupt flag TF1. The counted
every machine cycle. When the samples show a high in input is enabled to the Timer when TRI = I and either
one cycle and a low in the next cycle, the count is incre- GATE = 0 or INTI = 1. (Setting GATE = I allows
mented. The new count value appears in the register the Timer to be controlled by external input INTI, to
during S3PI of the cycle following the one in which the facilitate pulse width measurements.) TRI is a control
transition was detected. Since it takes 2 machine cycles bit in the Special Function Register TeON (Figure 8).
(24 oscillator periods) to recognize a I-to-O transition, GATE is in TMOD.
the maximum count rate is '1.4 of the oscillator fre-
quency. There are no restrictions on the duty cycle of The 13-Bit register consists of all 8 bits ofTHI and the
the external input signal, but to ensure that a given lower 5 bits of TL1. The upper 3 bits of TLI are inde-
level is sampled at least once before it changes, it terminate and should be ignored. Setting the run flag
should be held for at least one full machine cycle. (TR I) does not clear the registers.
In addition to the "Timer" or "Counter" selection, Mode 0 operation is the same for Timer 0 as for Timer
Timer 0 and Timer I have four operating modes from 1. Substitute TRO, TFO and INTO for the correspond-
which to select. Timer 2, in the 8052, has three modes ing Timer I signals in Figure 7. There are two different
of operation: "Capture," "Auto-Reload" and "baud GATE bits, one for Timer I (TMOD.7) and one for
rate generator." Timer 0 (TMOD.3).
Timer 0 and Timer 1 MODE 1
These Timer/Counters are present in both the 8051 and Mode I is the same as Mode 0, except that the Timer
the 8052. The "Timer" or "Counter" function is select- register is being run with all 16 bits.
ed by control bits ciT in the Special Function Register
TMOD (Figure 6). These two Timer/Counters have MODE 2
four operating modes, which are selected by bit-pairs
(MI, MO) in TMOD. Modes 0, I, and 2 are the same Mode 2 configures the Timer register as an 8-bit Coun-
for both Timer/Counters. Mode 3 is different. The four ter (TLJ) with automatic reload, as shown in Figure 9.
operating modes are described in the following text. Overflow from TLI not only sets TFI, but also reloads
(MSB) (LSB)
l GATE CIT Ml MO 1 GATE CIT
T
Ml MO J
Timer 1 Timer 0
GATE Gating control when set. Timer /CoUl;ter '"x'" is enabled Ml MO Operating Mode
only while '"INTx'" pin is high and '"TRx'" control pin is o o MCS-48 Timer '"TLx" serves as 5-bit prescaler.
set. When cleared Timer '"x" is enabled whenever o IS-bit Timer/Counter '"THx" and '"TLx" are
'"TRx'" control bit is set. cascaded; there is no prescaler.
cli' Timer or Counter Selector cleared for Timer operation o 8-bit auto-reload Timer/Counter '"THx'" holds a
(input from internal system clock). Set for Counter value which is to be reloaded into '"TLx" each
operation (input from '"Tx" input pin). time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter
controlled by the standard Timer 0 control bits.
THO is an 8-bittimer only controlled by Timer 1
control bits. )
(Timer 1) Timer/Counter 1 stopped.
Figure 6. TMOD: Timer/Counter Mode Control Register
6-7
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
cif= 0
INTERRUPT
__ ---,___---'t clf =1 CONTROL
Tt PIN -
GATE
270252-9
Figure 7. Timer/Counter 1 Mode 0: 13-Blt Counter
(MSB) (LSB)
TFI TRI TFO TRO lEI ITt lEO ITO
Symbol Position Name and Significance Symbol Position Name,and Significance
TFI TCON.7 Timer I overflow Flag. Set by lEI TCON.3 Interrupt I Edge flag. Set by hardware
hardware on TImer/Counter overflow. when external interrupt edge
Cleared by hardware lNhen processor detected. Cleared when interrupt
vectors to inter!'IJpt routine. processed.
TRI TCON.6 Timer I Run control bit. Sell cleared ITt TCON.2 Interrupt I Type control bit. Sell
by software to turn Timer/Counter on/ cleared by soltware to specify falling
off. edge/low level triggered external
interrupts.
TFO TCON.5 Timer 0 overflow Flag. Set by
hardware on Timer/Counter overflow. lEO TCON.I Interrupt 0 Edge lIag. Set by hardware
Cleared by hardware when processor when external Interrupt edge
vectors to interrupt routine. detected. Cleared when interrupt
TRO TCON.4 Timer 0 Run control bit. Set/cleared processed.
by software to turn Timer/Counter on/ ITO TCON.O Interrupt 0 Type control bit. Set!
off. cleared by software to specify falling
edge/low level triggered external
interrupts.
Figuie a.TeON: Timer/Counter Centro! Register
TLl with the contents ofTHI, which is preset by soft- CIT, GATE, TRO, INTO, and TFO. THO is locked into
ware. The reload leaves THI unchanged. a timer function (counting machine cycles) and takes
over the use ofTRI and TFI from Timer 1. Thus, THO
Mode 2 operation is the same for Timer/Copnter O. now controls the "Timer I" interrupt.
Mode 3 is provided for applications requiring an extra
MODE 3 8-bit timer or counter. With Timer 0 in Mode 3, an
Timer I in Mode 3 simply holds its count. The effect is 8051 can look like it has three Timer/Counters, and an
the same as setting TRI = O. 8052, like it has four. When Timer 0 is in Mode 3,
Timer 1'can be turned on and offby switching it out of
Timer 0 in Mode 3 establishes TLO and THO as two and into its own Mode 3, or can still be used by the
separate counters. The logic for Mode 3 on Timer 0 is serial port as a baud rate generator, or in fact, in any
shown in Figure 10. TLO uses the Tinier 0 control bits: application not requiring an interrupt.
6-8
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
INTERRUPT
270252-10
Figure 9. Timer/Counter 1 Mode 2: a-Bit Auto-Reload
osc ~B- 1112 lose
1/12 lose - - - - - - - ,
INTERRUPT
TO PIN-----~
CONTROL
1112 lose --------'-'--:---+1---<1
_ __ ~____~=ieoNTRoL
I· L.1_(_~_I_~) HL._TF_1-.1~'INTERRUPT
.....
'TR1 -
270252-1,1
Figure 10. Timer/Counter 0 Mode 3: Two a-Bit Counters
Timer 2
Table 2. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052. Like Timers 0 and I, it can operate RCLK + TCLK CP/RL2 TR2 Mode
either as a timer or as an event counter. This is selected . 0 0 1 16-bit Auto~Reload
by bit C/T2 in the Special Function Register T2CON 1 16-bit Capture
0 1
(Figure 11). It has three operating modes: "capture,"
"auto-load" and, "baud rate generator," which are se- 1 X 1 Baud Rate Generator
lected by bits in T2CON as shown in Table 2. X X 0 (off)
6-9
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
(MSB) (LSB)
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 cPlFi1:2
Symbol Position Name and Significance
TF2 T2CON.7 TImer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when eHher RCLK = 1 or TCLK = 1.
EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload Is caused by a negative
transition on T2EX and EXEN2 = 1. When TImer 2 Interrupt is enabled, EXF2 = 1
will cause the CPU to vector to the TImer 2 Interrupt routine. EXF2 must be
cleared by software.
RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock In Modes 1 and 3. RCLK = 0 causes TImer 1 overflow
to be used for the receive clock.
TCLK T2CON.4 TransmH clock fleg. When set, causes the serial port to use TImer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.
EXEN2 T2CON.3 TImer 2 external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX nTimer 2 is not being used to clock the
serial port. EXEN2 = 0 causes TImer 2 to Ignore events at T2.EX.
TR2 T2CON.2 Start/stop control for TImer 2. A logic 1 starts the timer.
C/T2 T2CON.1 Timer or counter select. (TImer 2)
o = Internal timer (OSC/12)
1 = External event counter (falling edge triggered) ..
CP/RL2 T2CON.O Capture/Reload flag. When set captures will occur on negatiVe transitions at
T2EX,if EXEN2 = 1. When cleared, auto-reloads will occur either with TImer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = 1, this bit Is ignored and the timer Is forced to auto-reload on
TImer 2 overflow.
FIgure 11. T2CON: TImer/Counter 2 Control RegIster
In the Capture Mode there are two options which are added feature that a 1-to-0 transition at external input
selected by bit EXEN2 in T2CON. If EXEN2 = 0, T2EX.will also trigger the 16"bit reload and set EXF2.
then Timer 2 is a 16-bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, The auto-reload mode is illustrated in Figure 13.
which can be used to generate an interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the The baud rate generator mode is selected by RCLK =
added feature that a 1-to-O transition at external input 1 andlor TCLK = 1. It will be described in conjunc-
T2EX causes the current value in the Timer 2 registers, tion with the serial port.
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. (RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In SERIAL INTERFACE
addition, the transition at T'2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an The serial port is full duplex, meaning it can transmit
interrupt. .and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
The Capture Mode is illustrated in Figure 12. before a previously received byte has been read from
the receive register. (However, if the first byte still
In the auto-reload mode there are again two options, hasn't been read by the time reception of the second
which are selected by bit EXEN2 in T2CON. If byte is complete, one of the bytes will be lost). The
EXEN2 = 0, then when Timer 2 rolls over it not only serial port receive and transmit registers are both ac-
sets TF2 but also causes the Timer 2 registers to be cessed at Special Function Register SBUF. Writing to
reloaded with the 16-bit value in registers RCAP2L SBUF loads the transmit register, and reading SBUF
and RCAP2H, which are preset by software. IfEXEN2 accesses a physically separate receive register.
= I, then Timer 2 still does the above, but with the
6-10
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
nMER2
INTERRUPT
EXEN2
270252-12
Figure 12. Timer 2 in Capture Mode
The serial port can operate in 4 modes: Multiprocessor Communications
Mode 0: Serial data enters and exits through RXD. Modes 2 and 3 have a special provision for multipro-
TXD outputs the shift clock. 8 bits are transmitted/re- cessor communications. In these modes, 9 data bits are
ceived: 8 data bits (LSB first). The baud rate is fixed at received. The 9th one goes into RB8. Then comes a
1/12 the oscillator frequency. stop bit. The port can be programmed such that when
the stop bit is received, the serial port interrupt will be
Mode 1: 10 bits are transmitted (through TXD) or re- activated only if RB8 = 1. This feature is enabled by
ceived (through RXD): a start bit (0), 8 data bits (LSB setting bit SM2 in SCON. A way to use this feature in
first), and a stop bit (1). On receive, the stop bit goes multiprocessor systems is as follows.
into RB8 in Special Function Register SCON. The
baud rate is variable. When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an ad-
Mode 2: 11 bits are transmitted (through TXD) or re- dress byte which identifies the target slave. An address
ceived (throughRXD): a start bit (0), 8 data bits (LSB byte differs from a data byte in that the 9th bit is 1 in an
first), a programmable 9th data bit, and a stop bit (1). address byte and 0 in a data byte. With SM2 = 1, no
On Transmit, the 9th data bit (TB8 in SCON) can be slave will be interrupted by a data byte. An address
assigned the value of 0 or 1. Or, for example, the parity byte, however, will interrupt all slaves, so that each
bit (p, in the PSW) could be moved into TB8. On re- slave can examine the received byte and see if it is being
ceive, the 9th data bit goes into RB8 in Special Functon addressed. The addressed slave will clear its SM2 bit
Register SCON, while the stop bit is ignored. The baud and prepare to receive the data bytes that will be com-
rate is programmable to either '132 or '164 the oscillator ing. The slaves that weren't being addressed leave their
frequency. SM2s set and go on about their business, ignoring the
coming data bytes.
Mode 3: 11 bits are transmitted (through TXD) or re- SM2 has no effect in Mode 0, and in Mode 1 can be
ceived (through RXD): a start bit (0), 8 data bits (LSB used to check the validity of the stop bit. In a Mode 1
first), a programmable 9th data bit and a stop bit (1). In reception, if SM2 = 1, the receive interrupt will not be
fact, Mode 3 is the same as Mode 2 in all respects activated unless a valid stop bit is received.
except the baud rate. The baud rate in Mode 3 is vari-
able.
Serial Port Control Register
In all four modes, transmission is initiated by any in-
struction that uses SBUF as a destination register. Re- The serial port control and status register is the Special
ception is initiated in Mode 0 by the condition RI = 0 Function Register SCON, shown in Figure 14. This
and REN = 1. Reception is initiated in the other register contains not orily the mode selection bits, but
modes by the incoming start bit if REN = 1. also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
6-11
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 2
INTERRUPT
EXEN2
270252-13
Figure 13. Timer 2 in Auto-Reload Mode
(MSB) (LSB)
SMO SMI I SM2 REN TB8 RB8 TI RI
Where SMO, SMI specify the serial port mode, as follows: • TB8 is the 9th data bit that will be
transmitted in Modes 2 and 3. Set or
SMO
0
0
SMI
0
0
Mode
0
1
2
Description
shift register
8·bitUART
9-bitUART
Baud Rate
fose/12
variable
. RB8
clear by software as desired.
In Modes 2 and 3, is the 9th data bit
that was received. In Mode I, if SM2
fose/64
= 0, RB8 is the stop bit that was
or
• SM2
3
fose/32
9-bit UART variable
enables the multiprocessor
. TI
received. In Mode 0, RBS is not used.
is transmit interrupt flag. Set by
hardware at the end of the Sth bit time
communication feature in Modes In Mode 0, or at the beginning of the
2 and 3. In Mode 2 or 3, if 8M2 Is stop bit in the other modes, in any
setto 1 then RI will no! be serial transmission. Must be cleared
activated if the received 9th data by software.
bit (RBS) is O. In Mode I, if 8M2
• RI is receive interrupt flag. Set by
= 1 then RI will not be activated
if a valid stop bit was not hardware at the end of the 8th bit time
received. In Mode 0, 8M2 should in Mode 0, or halfway through the stop
beO. bn time in the other modes, in any
• REN enables serial receotion. Set bv serial reception (except see 8M2).
software to enable reception. . Must be cleared by software.
Clear by software to disable
reception.
Figure 14. SCON: Serial Port Control Register
Baud Rates
The baud rate in Mode 0 is fixed: 2 SMOD
Mode 2 Baud Rate = 64X (Oscillator Frequency)
Oscillator Frequency
Mode 0 Baud Rate = ---'._---''---'-
12 In the 8051, the'baud rates in Modes 1 and 3 are deter-
mined by the Timer 1 overflow rate. In the 8052, these
The baud rate in Mode 2 depends on the value of bit baud rates can be determined by Timer 1, or by Timer
SMOD in Special Function Register peON. If SMOD 2, or by both (one for transmit and the other for re-
= 0 (which is the value on reset), the baud rate %4 the ceive).
oscillator frequency. If SMOD 1, the baud rate is
'1.2 the oscillato.r frequency.
6-12
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Using Timer 1 to Generate Baud Rates mode (high nibble of TMOD = OOIOB). In that case,
the baud rate is given by the formula
When Timer 1 is used as the baud rate generator, the
baud rates in Modesl and 3 are determined by the Modes 1, 3 2SMOD Oscillator Frequency
Timer 1 overflow rate and the value of SMOD as fol~ Baud Rate = - - - X - - - - - - - - ' ' - - - - : = -
32 12x [256 - (THl)l
lows:
Modes 1,3 2SMOD One can achieve very low baud rates with Timer 1 by
Baud Rate = ----n-
X (Timer 1 Overflow Rate) leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a l6-bit timer (high nibble of
TMOD = OOOlB), and using the Timer 1 interrupt to
The Timer 1 interrupt should be disabled in this appli- do a 16-bit software reload.
cation. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3 Figure 15 lists various commonly used baud rates and
. running modes. In the most typical applications, it is how they can be obtained from Timer 1.
configured for "timer" operation, in the auto-reload
Timer 1
Baud Rate fosc SMOD Reload
clf Mode
Value
Mode 0 Max: 1 MHZ 12MHZ X X X X
Mode 2 Max: 375K 12MHZ 1 X X X
Modes 1, 3: 62.5K 12MHZ 1 0 2 FFH
19.2K 11.059 MHZ 1 a 2 FDH
9.6K 11.059 MHZ a a 2 FDH
4.8K 11.059 MHZ a a 2 FAH
2.4K 11.059 MHZ a a 2 F4H
1.2K 11.059 MHZ a a 2 E8H
137.5K 11.986 MHZ a a 2 1DH
110K 6MHZ a a 2 72H
110K 12MHZ a a 1 FEEBH
Figure 15. Timer 1 Generated Commonly Used Baud Rates
Using Timer 2 to Generate Baud Rates 11). Note then the' baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or
In the 8052, Timer 2 is selected as the baud rate genera- TCLK puts Timer 2 into its baud rate generator mode,
tor by setting TCLK and/or RCLK in T2CON (Figure as shown in Figure 16.
nMER 1
OVERFLOW
AX CLOCK
TXCLOCK
T2EX PIN "TIMER 2"
INTERRUPT
EX""
L NOTE AYAILAIIU.rTY OF ADDmoNAL EXTERNAL INTERRUPT
270252-14
Figure 16. Timer 2 in Baud Rate Generator Mode
6-13
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
The baud rate generator mode is similar to the auto-re- Transmission is initiated by any instruction that uses
load mode, in that a rollover in TH2 causes the Timer 2 SBUF as a destination register. The "write to SBUF"
registers to be reloaded with the 16-bit value in registers signal at S6P2 also loads a I into the 9th position ofthe
RCAP2H and RCAP2L, which are preset by software. transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such
Now, the baud rates in Modes I and 3 are determined that one full machine cycle will elapse between "write
by Timer 2's overflow rate as follows: to SBUF," and activation of SEND.
Timer 2 Overflow Rate SEND enables the output of the shift register to the
Modes I, 3 Baud Rate = 16" alternate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
The Timer can be configured for either "timer" or P3.1. SHIFT CLOCK is low during S3, S4, and S5 of
"counter" operation. In the most typical applications, it every machine cycle, and high during S6, SI and S2. At
is configUred for "timer" operation (C/T2 = 0). "Tim- S6P2 of every machine cycle in which SEND is active,
er" operation is a little different for Timer 2 when it's the contents of the transmit shift register are shifted to
'being used as a baud rate generator. Normally, as a the right one position.
timer it would increment every machine cycle (thus at As data bits shift out to the right, zeroes come in from
'112 the oscillator frequency). As a baud rate generator, the left. When the MSB of the data byte is at the output
however, it increments every state time (thus at '!. the position of the shift register, then the I that was initial-
oscillator frequency). In that case the baud rate is given ly loaded into the 9th position, is just to the left of the
by the formula MSB, and all positions to the left ofthat contain zeroes.
Modes I, 3 Oscillator Frequency This condition flags the TX Control block to do one
last shift and then deactivate SEND and set TI. Both of
Baud Rate = 32x [65536 - (RCAP2H, RCAP2L)1 these actions occur at SIPI of the 10th machine cycle
after "write to SBUF."
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2J:, taken as a 16-bit unsigned in- Reception is initiated by the condition REN = I and
teger. Rl. = O. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
Timer 2 as a baud rate generator is shown in Figure 16. shift register, and in the next clock phase activates RE-
This Figure is valid only if RCLK + TCLK = I in CEIVE.
T2CON. Note that a rollover in TH2 does not setTF2,
and will not generate an interrupt. Therefore, the Timer RECEIVE enables SHIFT CLOCK to the alternate
2 interrupt does not have to be disabled when Timer 2 output function line of P3.1. SHIFT CLOCK makes
is in the baud rate generator mode. Note too" that if transitions at S3Pl and S6Pl of every machine cycle.
EXEN2 is set, a I-to-O transition in T2EX will set At S6P2 of every machine cycle in which RECEIVE is
EXF2 but will not cause a reload from (RCAP2H, active, the contents of the receive shift register are shift-
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use ed to the left one position. The value that comes in
as ,a baud rate generator, T2EX can be used as an extra from the right is the value that was sampled at the P3.0
external interrupt, if desired. pin at S5P2 of the same machine cycle. '
As data bits come in from the right, Is shift out to the
It should be noted that when Timer 2 is running (TRZ left. When the 0 that was initially loaded into the right-
= I) in "timer" function in the baud rate generator
most position arrives at the leftmost position in the shift
mode, one should not try to read or write TH2 or TL2. register, it flags the RX Control block to do one last
Under these conditions the Timer is being incremented shift and load SBUF. At SIP I of the 10th machine
every state time, and the results of a read or write may cycle after the write to SCON that cleared RI, RE-
not be accurate. The RCAP registers may be read, but CEIVE is cleared and'RI is set.
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or More About Mode '1
RCAP registers, in this case. Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSD first),
More About Mode 0 and a stop bit (1), On receive, the stop bit goes into
RB8 in SCON. In the 8051 the'baud rate is determined
Serial data enters and exits through RXD. TXD out- by the Timer 1 overflow rate. In the 8052 it is deter-
puts the shift clock. 8 bits are transmitted/received: 8 mined either by the Timer 1 overflow rate, or the Timer
data bits (LSB first). The baud rate is fixed at 1/12 the 2 overflow rate, or both (one for transmit and the other
oscillator frequency. for receive).
Figure 17 shows a simplified functional diagram of the Figure 18 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing. serial port in Mode 1, and associated timings for trans-
mit receive.
6-14
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
SBUF
TO ---'--=~~~r:--~~----1---------r-, RXD
P3.0ALT
OUTPUT
FUNCTION
56.-_.------1
TXD
P3.1 ALT
OUTPUT
FUNCTION
' - - - - - I RX CLOCK
RX CONTROL SHIFT
REN--...r--l--_ _.j START
Ri-"'~ L..._--i........,...-.-T""'!,......,-i---.J RXD
P3.0ALT
INPUT
FUNCTION
READ
SBUF
ALE
4WRITE TO SBUF
SEND 88P2' I
SHIFT
RXD (DATA OUT) \ TRANSMIT
TXD (SHIFT CLOCK)
n
-1l WRITE TO SCON (CLEAR RI)
~RIi~~~==j=::::::::::::::::::::::::::::::::::::::::::::::::::::~r----
'!!'CEIVE L-
RECEIVE
SHIFT
RXD (DATA IN)---.....,[}':'~---{}.!'r.!----o=-----[i=----LJ='''-----[}''~--o=-----[F-
TXD (SHIFT CLOCK)
270252-15
Figure 17. Serial Port Mode 0
inter HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
TIMER 1 TIM·ER2
OVERFLOW OVERFLOW
WRIT~E-r-:=jrot:m::;r~;""'~~_":-'"~_-r"""'\~;.....r-,
TO
SBUF
TXD
RECEIVE
..
! R";~LOC fiTART BITI
tilT DETECTOR SAMPLE TIMES
SHIFT '
DO
0' 62
___________________________________________________
~R~I
oj D4 .. DI D)
STOP BIT
~r----
270252-16
Figure 18. Serial Port Mode 1. TCLK, RCLK and timer 2 are Present in the 8052/8032 Only.
Transmission is initiated by any instruction that uses times are synchronized to the divide-by-16 counter, not
SBUF as a destination register. The "write to SBUF" to the "write to SBUF" signal).
signal also loads a 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit The tra:!lsinission begins with activation of SEND,
that a transmission is requested. Transmission actually which puts the start bit at TXD. One bit time later,
commences at SIPI of the machine cycle following the DATA is activated, which enables the output bit· of the
next rollover in the divide-by-16 counter. (Thus, the bit transmit shift register to TXD. The first shift pulse oc-
curs one bit time after that.
6-16
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits shift out to the right, zeroes are clocked in mit, the 9th data bit (TB8) can be assigned the value of
from the left. When the MSB of the data byte is at the o or 1. On receive, the 9th data bit goes into RB8 in
output position of the shift register, then the 1 that was SCON. The baud rate is programmable to either Yo. or
initially loaded into the 9th position is just to the left of '164 the oscillator frequency in Mode 2. Mode 3 may
the MSB, and all positions to the left of that contain have a variable baud rate generated from either Timer 1
zeroes. This condition flags the TX Control unit to do or 2 depending on the state of TCLK and RCLK.
one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after Figures 19 and 20 show a functional diagram of the
"write to SBUF." serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode I: The transmit portion
Reception is initiated by a detected I-to-O transition at differs from Mode 1 only in the 9th bit of the transmit
RXD. For this purpose RXD is sampled at a rate of 16 shift register.
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is imme- Transmission is initiated by any instruction that uses
diately reset, and IFFH is written into the input shift SBUF as a destination register. The "write to SBUF"
register. Resetting the divide-by-16 counter aligns its signal also loads TB8 into the 9th pit position of the
rollovers with the boundaries of the incoming bit times. transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission com-
The 16 states of the counter divide each bit time into mences at SIPl of the machine cycle following the next
16ths. At the 7th, 8th, and 9th counter states of each bit rollover in the divide-by-16 counter. (Thus, the bit
time, the bit detector samples the value of RXD. The times are synchronized to the divide-by-16 counter, not
value accepted is the value that was seen in at least 2 of to the "write to SBUF" signal.)
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the The transmission begins with activation of SEND,
receive circuits are reset and the unit goes back to look- which puts the start bit at TXD. One bit time later,
ing for another I-to-O transition. This is to provide re- DATA is activated, which enables the output bit of the
jection of false start bits. If the start bit proves valid, it transmit shift register to TXD. The first shift pulse oc-
is shifted into the input shift register, and reception of curs one bit time after that. The first shift clocks a 1
the rest of the frame will proceed. (the stop bit) into the 9th bit position of the shift regis-
ter. Thereafter, only zeroes are clocked in. Thus, as
As data bits come in from the right, Is shift out to the data bits shift out to the right, zeroes are clocked in
left. When the start bit arrives at the leftmost position from the left. When TB8 is at the output position of the
in the shift register, (which in mode 1 is a 9-bit regis- shift register, then the stop bit is just to the left of TB8,
ter), it flags the RX Control block to do one last shift, and all positions to the left of that contain zeroes. This
load SBUF and RB8, and set RI. The signal to load condition flags the TX Control unit to do one last shift
SBUF and RB8, and to set RI, will be generated if, and and then deactivate SEND and set TI. This occurs at
only if, the following conditions are met at the time the the lIth divide-by-16 rollover after "write to SBUF."
final shift pulse is generated.
Reception is initiated by a detected I-to-O transition at
1) RI = 0, and RXD. For this purpose RXD is sampled at a rate of 16
2) Either 5M2 = 0, or the received stop bit = 1 times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is imme-
If either of these two conditions is not met, the received diately reset, and IFFH is written to the input shift
frame is irretrievably lost. If both conditions are met, register.
the stop bit goes into RB8, the 8 data bits go into
SBUF, and RI is activated. At this time, whether the At the 7th, 8th and 9th counter states of each bit time,
above conditions are met or not, the unit goes back to the bit detector samples the value of RXD. The value-
looking for a 1-to-0 transItion in RXD. accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit goes
More About Modes 2 and 3 back to looking for another I-to-O transition. If the
start bit proves valid, it is shifted into the input shift
Eleven bits are transmitted (through TXD), or received register, and reception of the rest of the frame will pro-
(throughRXD): a start bit (0),8 data bits (LSB first), a ceed. . .
programmable 9th data bit, and a stop bit (1). On trans-
6-17
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
TO
SBUF
TXD
PHASE 2 CLOCK
('hfosc)
MODE2
TI
SMOD=l SERIAL
PORT
INTERRUPT
(SMOD IS PCON.7) 1..-_--....
LOAD
SBUF
RXD
READ _ _......"
SBUF
:~~T~XD~}~T}A~RT~.~IT/~P~D~==~=~==~=~=~:;:;~:;~:;~C:::: )\TRANSMIT
TI
~------~------------------------------ ____________~r---
270252-17
Figure 19. Serial Port Mode 2
6-18
infef HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER" TIMER 2
OVERFLOW OVERFLOW
TXD
TCLK -
SEND
LOAD
SBUF
SHIFT 1------...,
RXD
TX
~FLOC~~~~~=-~L-~L--IL--~L-~L-~I--JL--~L-~L-~.L--
---A WRITE TO SBUF
~ SEND
DATA L S1P1 I
SHIFT TRANSMIT
----riD\'TARTBIT/ DO
TI
I
STOP BIT GEN
RX
CLOCK
RXD BIT DETECTORI START BIT /
RECEIVE SAMPLE TIMES
SHIFT ~ __~'L__~L_ _~L_ _"L_~L-_~L_ _~L___JL-__~L-_ _ _
~RI~_______________________________ ~r-----
270252-18
Figure 20. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 8052/8032 Only.
6-19
, intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits come in from the right, Is shift out to the was transition-activated. If the interrupt was level-acti-
left. When the start bit arrives at the leftmost position vated, then the external requesting source is what con-
in the shift register (which in Modes 2 and 3 is a 9-bit trols the request flag, rather than the on-chip hardware.
register), it flags the RX Control block to do one last
shift, load SBUF and RB8, and set RI. The signal to The Timer 0 and Timer 1 Interrupts are generated by
load SBUF and RB8, and to set RI, will be generated if, TFO and TFI, which are set by a rollover in theirre-
and only if, the following conditions are met at the time spective Timer/Counter registers (except see Timer 0 in
the final shift pulse is generated: Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
1) RI = 0, and when the service routine is vectored to.
2) Either 5M2 = 0 or the received 9th data bit =1
.The Serial Port Interrupt is generated by the logical OR
If either of these conditions is not met, the received of RI and TI. Neither of these flags is Cleared by hard-
frame is irretrievably lost, and RI is not set. If both ware when the service routine is vectored to. In fact,
conditions are met, the received 9th data bit goes into the service routine will normally have to determine
RB8, and the first 8 data bits go into SBUF. One bit whether it was RI or TI that generated the interrupt,
time later, whether the above conditions were met or and the bit will have to be Cleared in software.
not, the unit goes back to looking for a I-to-O transition
at the RXD input. In the 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
Note that the value of the received stop bit is irrelevant Cleared by hardware when the service routine is vec-.
to SBUF, RB8, or RI. tored to. In fact, the service routine may have to deter-
mine whether it was TF2 or EXF2 that generated the
interrupt, and the -bit will have to be cleared in 80ft-
INTERRUPTS ware.
The 8051 provides 5 interrupt sources. The 8052 pro- All of the bits that generate interrupts can be set or
vides 6. These are shown in Figure 21. Cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
The External Interrupts INTO and INTI can each be can be generated or pending interrupts can be canceled
either level-activated or transition-activated, depending in software.
on bits ITO and ITI in Register TCON. The flags that
actually generate these interrupts are bits lEO and lEI (MSB) (LSB)
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when 1~1-1~1~lml~I~I~1
the service routine is vectored to only if the interrupt Symbol Position Function
~ IE.7 disables all interrupts. If EA = 0, no
interrupt will be acknowledged. .If EA
= 1. each interrupt source Is
individually enabled or disabled by
selling or clearing its enable bH.
IE.6 reserved.
ET2 IE.5 enables or disables the Timer 2
TFO'---------· Overflow or caoture interruot. If ET2
= 0, the Timer 2 Interrupt is disabled.
ES IE.4 enables or disables the Serial Port
interrupt. If ES = O. the Serial Port
INTERRUPT interrupt is disabled.
SOURCES
ETI IE.3 enables or disables the Timer 1
Overflow interrupt. If En = O. the
Timer 1 interrupt Is disabled:
~,--------~~ EXI IE.2 enables. or disables External Interrupt
1. If EXI = O. External Interrupt 1 is
disabled.
ETO IE.l enables or disables the Timer 0
Overflow interrupt. If ETO = 0, the
Timer 0 interruptis disabled.
EXO lE.O enables or disables External Interrupt
O. If EXO = 0, External Interrupt 0 is
disabled.
User sdftware should never write 1s to unimplemented bits,
270252-19 since they [!lay be used in future MC5-51 products.
Figure 21. MCS®·51 Interrupt Sources
Figure 22. IE: Interrupt Enable Register
6-20
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Each of these interrupt sources can be individually en- If two requests of different priority levels are received
abled or disabled by setting or clearing a bit in Special simultaneously, the request of higher priority level is
Function Register IE (Figure 22). IE contains also a serviced. If requests of the same priority level are re-
global disable bit, EA, which disables all interrupts at ceived simultaneously, an internal polling sequence de-
once. termines which request is serviced. Thus within each
priority level there is a second priority structure deter-
Note in Figure 23 that bit position IE.6 is unimple- mined by the polling sequence, as follows:
mented. In the 805 Is, bit position IE.5 is also unimple-
mented. User software should not write Is to these bit Source Priority Within Level
positions, since they may be used in future MCS-51 1. lEO (highest)
products. 2. TFO
3. IE1
4. TF1
Priority Level Structure 5. RI +TI
Each interrupt source can also be individually pro- 6. TF2 + EXF2 (lowest)
grammed to one of two priority levels by setting or
clearing a bit in Special Function Register IP (Figure Note that the "priority within level" structure is only
23). A low-priority interrupt can itself be interrupted used to resolve simultaneous requests of the same priori-
by a high-priority interrupt, but not by another low-pri- ty leveL
ority interrupt. A high-priority interrupt can't be inter-
rupted by any other interrupt source. The IP register contains a number of unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s, and in the
8051s these and IP.5 are vacant. User software should
(MSB) (LSB)
not write Is to these bit positions, since they may be
1-1-1~1~lrnl~I~I~1 used in future MCS-51 products.
Symbol Position Function
IP.7 reserved
How Interrupts Are Handled
IP.6 reserved
PT2 IP.5 defines the Timer 2 interrupt priority
The interrupt flags are sampled at S5P2 of every ma-
level. PT2 = 1 programs it to the chine cycle. The samples are polled during the follow-
higher priOrity level. ing machine cycle. If one of the flags was in a set condi-
PS IP.4 defines the Serial Port interrupt priority tion at S5P2 of the preceding cycle, the polling cycle
level. PS = 1 programs it to the will find it and the interrupt system will generate an
higher priority level.
LCALL to the appropriate service routine, provided
PTl IP.3 defines the Timer 1 interrupt priority this hardware-generated LCALL is not blocked by any
level. PTl = 1 programs it to the
of the following conditions:
higher priority level.
PTO IP.l defines the Timer 0 interrupt priority
1. An interrupt of equal or higher priority level is al-
level. PTO = 1 programs it to the ready in progress.
higher priority level.
2. The cUrrent (polling) cycle is not the final cycle in
PXO IP.O defines the External Interrupt 0 priority the execution of the instruction in progress.
level. PXO = 1 programs it to the
higher priority level. 3. The instruction in progress is RET! or any write to
User software should never write 1s to unimplemented bits, the IE or IP registers.
since they may be used in future MCS·51 products.
Any of these three conditions will block the generation
Figure 23. IP: Interrupt Priority Register of the LCALL to the interrupt service routine. Condi-
tion 2 ensures that the instruction in progress will be
· · · · · · · · - - C l -...._1" ' - - C 2 - -••+I---C3--~I".--C4--'_1. - - C 5 - - · · · ..
IS5P21 5&
········~'\---'-----=l.llli---L---l'l:l-----L----
INTERRUPT
f'7'tINTERRUPT
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR AOORESS
INTERRUPT ROUTIN.E
GOES LATCHEO
ACTIVE
270252-20
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
Figure 24. Interrupt Response Timing Diagram
6-21
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
completed before vectoring to any service routine. Con- External Interrupts
dition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more The external sources can be programmed to be level-ac-
instruction will be executed before any interrupt is vec- tivated or transition-activated by setting or clearing bit
tored to. ITt or ITO in Register TCON. If ITx = 0, external
interrupt x is triggered by a detected low at the INTx
The polling cycle is repeated with each machine cycle, pin. If ITx = 1, external interrupt x is edge-triggered.
and the values polled are the values that were present at In this mode if successive samples of the INTx pin
S5P2 of the previous machine cycle. Note then that if show a high in one cycle and a low in the next cycle,
an interrupt flag is active but not being responded to for interrupt request flag lEx in TCON is set. Flag bit lEx
one of the above conditions, if the flag is not still active then requests the interrupt.
when the blocking condition is removed, the denied in-
terrupt will not be serviced. In other words, the fact Since the external interrupt pins are sampled once each
that the interrupt flag was once active but not serviced machine cycle, an input high or low should hold for at
is not remembered. Every polling cycle is new. least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
The polling cycle/LCALL sequence is illustrated in source has to hold the request pin high for at least one
Figure 24. cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt re-
Note that if an interrupt of higher priority level goes quest flag lEx will be set. lEx wiil be automatically
active prior to S5P2 of the machine cycle labeled C3 in cleared by the CPU when the service routine is called.
Figure 24, then in accordance with the above rules it
will be vectored to during C5 and C6, without any in- If the external interrupt is level-activated, the external
struction of the lower priority routine having been exe- source has to hold the request active until the requested
cuted. ' interrupt is actually generated. Then it has to deacti-
vate the request before the interrupt service routine is
Thus the processor acknowledges an interrupt request completed, or else another interrupt will be generated.
by executing a hardware-generated LCALL to the ap-
propriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases Response Time
it doesn't. It never clears the Serial Pcirt or Timer 2
flags. This has to be done in the user's software. It The INTO and INTI levels are inverted and latched
clears an external interrupt flag (lEO or lEI) only if it into lEO and lEI at S5P2 of every machine cycie. The
was transition-activated. The hardware-generated values are not actually polled by the circuitry until the
LCALL pushes the contents of the Program Counter next machine cycle. If a request is active and conditions
onto the stack (but it does not,save the PSW) and re- are right for it to be acknowledged, a, hardware subrou-
loads the PC with an address that depends on the tine call to the requested service routine will be the next
source of the interrupt being vectored to, as shown be- instruction to be executed. The call itself takes two cy-
low. ' cles. Thus, a minimum of three complete machine cy-
Vector cles elapse between activation of an external interrupt
Source request and the beginning of execution of the first in-
Address
lEO 0003H struction of the service routine. Figure 24 shows inter-
TFO OOOBH rupt response timings.
IE1 0013H
A longer response time would result if the request is
TF1 001BH blocked by one of the 3 previously listed conditions. If
RI + TI 0023H an interrupt of equal or higher priority level is already
. TF2 + EXF2 002BH in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
Execution proj::eeds from that location until the RET! the instruction in progress is not in its final cycle, the
instruction is encountered. The RETI instruction in-' additional'wait time cannot be more than 3 cycles, since
forms the processor that this interrupt routine is no the longest instructions (MUL and DIY) are OIily 4
longer in progress, then pops the top two bytes from the cycles long, and if the instruction in progress is RET!
stack and reloads the Program Counter. Execution of or an access to IE or IP, the additional wait time can-
the interrupted program continues from where it left not be inore than 5 cycles (a maximum of one more
otT. cycle to complete the instruction in progress, plus 4
cycles to complete the next instruction if the instruction
Note that a simple RET instruction would also have is MUL or DIY).
returned execution to the interrupted program, but it
would have left the interrupt control system thinking Thus, in a single-interrupt system, the response time is
an interrupt was still in progress. always more than 3 cycles and less than 9 cycles.
6-22
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
SINGLE-STEP OPERATION RESET
The 8051 interrupt structure allows single-step execu- The reset input is the RST pin, which is the input to a
tion with very little software overhead. As previously Schmitt Trigger.
noted, an interrupt request will not be responded to
while an interrupt of equal priority level is still in prog- A reset is accomplished by holding the RST pin high
ress, nor will it be responded to after RET! until at for at least two machine cycles (24 oscillator periods),
least one other instruction has been executed. Thus, while the oscillator is running. The CPU responds by
once an interrupt routine has been entered, it cannot be generating an internal reset, with the timing shown in
re-entered until at least one instruction of the interrupt- Figure 25.
ed program is executed. One way to use this feature for
single-stop operation is to program one of the external The external reset signal is asynchronous to the internal
interrupts (say, INTO) to be level-activated. The service clock. The RST"pin is sampled during State 5 Phase 2
routine for the interrupt will terminate with the follow- of every machine cycle. The port pins will maintain
ing code: their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pin; that is, for 19
JNB P3.2,$ ;Wait Here Till INTO Goes High to 31 oscillator periods after the external reset signal
"JB P3.2,$ ;Now Wait Here Till it Goes Low has been applied to the RST pin.
RETI :Go Back and Execute One Instruction While the RST pin is high, ALE and PSEN are weakly
pulled high. After RST is pulled low, it will take 1 to 2
Now if the INTO pin, which is also the P3.2 pin, is held
machine cycles for ALE and PSEN to start clocking.
normally low, the CPU will go right into the External For this reason, other devices can not be synchronized
Interrupt 0 routine and stay there until INTO is pulsed
to the internal timings of the 8051.
(from low to high to low). Then i~ will execute RET!,
go back to the task program, execute one instruction, The internal reset algorithm writes Os to all the SFRs
and immediately re-enter the External Interrupt 0 rou- except the port latches, the Stack Pointer, and SBUF.
tine to await the next pulsing of P3.2. One step of the The port latches are initialized to FFH, the Stack
task program is executed each time P3.2 is pulsed. Pointer to 07H, and SBUF is+indeterminate. Table 3
lists the SFRs and their reset values.
The internal RAM is not affected by reset. On power
up the RAM content is indeterminate.
1---12 05C. PERIOD5 ---I
1 55 1 56 1 51 1 52 1 53 1 54 1 55 1 56 1 51 1 52 1 53 -1 54 1 55 1 561 51 1 52 1 53 1 541
R5T:
~L IIIIIIIII /~ CINTERNAL RE5ET 51GNAL
,
5AMPLE R5T ,
5AMPLE R5T -
P5EN:
po:
,
- - 1 1 05C. PERIOD5 - ........, ...- - - - - 1 9 05C. PERIOD5 -----<....,
270252-33
Figure 25. Reset Timing
6-23
intJ HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Table 3 Reset Values of the SFRs POWER-ON RESET
SFRName Reset Value An automatic reset can be obtained when VCC is
PC OOOOH turned on by connecting the RST pin to VCC through a
10 /Lf capacitor and to VSS through an 8.2 Kn resistor,
ACC OOH
providing the VCC risetime does not exceed a millisec-
B OOH ond and the oscillator start-up time does not exceed 10
PSW OOH milliseconds. This power-on reset circuit is shown in
SP
Figure 26. The CHMOS devices do not require the
07H
8.2K pulldown resistor, although its presence does no
DPTR OOOOH harm.
PO-P3 FFH
When power is turned on the circuit holds the RST pin
IP (8051) XXXOOOOOB high for an amount of time that depends on the value of
IP (8052) XXOOOOOOB the capacitor and the rate at which it charges. To en-
IE (8051) OXXOOOOOB
sure a good, reset the RST pin must be high long
enough to allow the oscillator time to start up (normal-
IE (8052) oxOOqOOOB ly a few msec) plus two machine cycles.
TMOD OOH
Note that the port pins will be in a random state until the
TCON OOH oscillator has started and the internal reset algorithm
THO OOH has written Is to them.
TLO OOH With this circuit, reducing VCC quickly to 0 causes the
TH1 OOH RSTpin voltage to momentarily fall below OV. Howev-
TL1
, er, this voltage is internally limited, and will not harm
OOH
the device.
TH2 (8052) DOH
TL2 (8052)' OOH
POWER-SAVING MODES OF
RCAP2H (8052) OOH OPERATION
RCAP2L (8052) OOH For appiications where power consumption is critical
SCON OOH the CHMOS version provides power reduced modes of
'SBUF Indeterminate operation as a standard feature. The power down mode
in HMOS devices is no longer it standard feature and is.
PCON (HMOS) OXXXXXXXB being phased out.
PCON(CHMOS) OXXXOOOOB
CHMOS Power Reduction Modes
CHMOS versions' have two power-reducing modes,
Idle and Pciwer Down. The input through which back-
up power is supplied during these operations is VCC.
Figure 27 shows the internal circuitry which imple-
lllents these featureS. In the Idle mode (IDL = 1), the
oscillator continues to run and the Interrupt, Serial
Port, and Timer blocks continue to be clocked, but the
clock signal is gated off to the CPU. In Power Down
8051
(PD = I), the oscillator is frozen. The Idle and Power
Down modes are activated by setting bits in Special
.---,--1 RST Function Register PCON. The address of this register
is 87H. Figure 26 details its contents.
8.2Kll
In the HMOS devices the PCON register only contains
SMOD. The other four bits are implemented only in
~---;VSS
the CHMOS devices. User software should never write
Is to unimplemented bits, since they may be used in
future MCS-51 products.
270252-21
Figure 26. Power on ResetClrcult IDLE MODE
An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
6-24
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
mode. In the Idle mode, the internal clock signal is The flag bits GFO and GFI can be used to give an
gated off to the CPU, but not to the Interrupt, Timer, indication if an interrupt occurred during normal oper-
and Serial Port functions. The CPU status is preserved ation or during an Idle. For example, an instruction
in its entirety: the Stack Pointer, Program Counter, that activates Idle can also set one or both flag bits.
Program Status Word, Accumulator, and all other reg- When Idle is terminated by an interrupt, the interrupt
isters maintain their data during Idle. The port pins service routine can examine the flag bits.
hold the logical states they had at the time Idle was
activated. ALE and PSEN hold at logic high levels. The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still run-
There are two ways to terminate the Idle. Activation of ning, the hardware reset needs to be held active for only
any enabled interrupt will cause PCON.O to be cleared two machine cycles (24 oscillatoi- periods) to complete
by hardware, terminating the Idle mode. The interrupt the reset.
will be serviced, and following RETI the next instruc- The signal at the RST pin clears the IDL bit directly
tion to' be executed will be the one following the in- and asynchronously. At this time the CPU resumes
struction that put the device into Idle. program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
~
cycles of program execution may take place before the
internal reset algorithm takes control. On-chip hard-
ware inhibits access to the internal RAM during this
XTAL 2 = XTAL 1 time, but access to the port pins is not inhibited. To,
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
INTERRUPT,
i-r-C>SERIAL PORT,
Idle should not be one that writes to a port pin or to
TIMER BLOCKS external Data RAM.
CPU
POWER DOWN MODE
An instruction that sets PCON.l causes that to be the
last instruction executed' before going into the Power
270252-22 Down mode: In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all func-
Figure 27. Idle and Power Down Hardware
tions are stopped, but the on-chip RAM and Special
Function Registers are. held. The port pins output the
(MSB) (LSB) values held by their respective SFRs. ALE and PSEN
SMOD GF1 GFO PD IDL
output lows.
The only exit from Power Down for the 80C5l is a
Symbol Posltlo'n Name and Function
hardware reset. Reset redefines all. the SFRs, but does
SMOD PCON.7 Double Baud rate bit. When set to a 1
not change the on-chip RAM.
and Timer 1 is used to generate baud
rate, and the Serial Port is used in In the Power Down mode of operation, VCC can be
modes 1, 2, or 3. reduced to as low as 2V. Care must be taken, however,
PCON.S (Reserved) to ensure that VCC is not reduced before the Power
PCON.5 (Reserved) Down mode is invoked, and that VCC is restored to its
PCON.4 (Reserved)
normal operating level, before the Power Down mode is
terminated. The reset that terminates Power Down also
GF1 PCON.3 General-purpose flag bit.
frees the' oscillator. The reset should not be activated
GFO PCON.2 General-purpose flag bit. before VCC is restored to its normal ,operating level,
PD PCON.1 Power Down bit. Setting this bit and must be held active long enough to allow the oscil-
activates power down operation. lator to restart and stahilize (normally less than 10
IDL PCON.O Idle mode bit. Setting this bit activates
msec). ' ,
idle mode operation.
If 1s are written to PD and IDL at the same time, PD takes
Precedence. The reset value of PCON is (OXXXOOOO).
EPROM VERSIONS
In the HM0S devices the PCON register only contains The EPROM versions of these devices are listed in Ta-
SMOD. The other four bits are implemented only in the
CHMOS devices. User software should never write 1s to
ble 4. The 8751H programs at VPP = 21V using one
unimplemented bits, since they may be used in future MCS- 50 msec PROG pulse per byte programmed. This re-
51 products. sults in at6tal programming time (4K bytes) of approx-
imately 4 minutes.
Figure 28. PCON: Power Control Register
6-25
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Table 4. EPROM Versions of the 8051 and 8052
Device EPROM EPROM Ckt Time Required to
VPP
Name Version Bytes Type Program Entire Array
B051 (B751) 4K HMOS .21.0V 4 minutes
B051AH B751H 4K HMOS 21.0V 4 minutes
BOC51BH B7C51 4K CHMOS 12.75V: 13 seconds
B052AH B752BH BK HMOS 12.75V 26 seconds
The 87S2BH and 87CS1 use the faster "Quick-Pulse" 87C51 AND 8752BH
programming™ algorithm. These devices program at
VPP = 12.7SV using a series of twenty-five 100 p.s The 87CS1 and 87S2BH contain two Program Memory
PROG pulses per byte programmed. This results in a locking schemes: Encrypted Verify and Lock Bits.
total programming time of approximately 26 seconds
for the 87S2BH (8K bytes) and 13 seconds for the Encrypted Verify: These devices implement a 32-byte
87CS1 (4K bytes). EPROM array that can be programmed by the custom-
er, and which can then be used to encrypt the program
Detailed procedures for programming and verifying code bytes during EPROM verification. The EPROM
each device are given in the data sheets. verification procedure is performed as usual, except
that each code byte comes out X-NORed ~th one of
the 32 key bytes. The key bytes are gone through in
EXPOSURE TO LIGHT sequence. Therefore, to read the ROM code, one has to
It is good practice to cover the EPROM window with know the 32 key bytes in their proper sequence.
an opaque label when the device is in operation. This is
not so much to protect the EPROM array·from inad- Unprogrammed bytes have the value FFH. Therefore,
vertent erasure, but to protect the RAM and other on- if the Encryption Array is lc;ft unprogrammed all the
chip logic. Allowing light to impinge on the silicon die key bytes have the value FFH. Since any code byte
while the device is operating can cause logical malfunc- X-NORed with FFH leaves the code byte. unchanged,
tion. leaving the Encryption Array unprogrammed in effect
bypasses the encryption feature.
LOck Bits: Also on the chip are two Lock Bits which
Program Memory Locks can be left unprogrammed (U) or programmed (P) to
In some micro controller applications it is desirable that obtain the following features:
the Program Memory be secure from software piracy. Bit 2 Bit 1 Additional Features
Intel has responded to this. need by implementing a
Program Memory locking scheme in some of the MCS- U U None
Sl devices. While it is impossible· for anyone to guaran- U P • Externally fetched code can not
tee absolute security against all levels of technological access internal Program Memory.
sophistication, the Program Memory locks in the MCS-
SI devices will present a formidable barrier against Hie- • Further programming disabled.
gal readout of protected software. P U (Reserved for Future definition.)
P P • Externally fetched code can not
8751H access internal Program Memory.
• Further programming disabled. .
The 87S1H contains· a lock bit which, once pro-
grammed, denies electrical access by any external • Program verification is disabled.
means to.the on-chip Program Memory. The effect .of
this lock bit is that while it is programmed the internal When Lock Bit 1 is programmed, the logic level at the
Program Memory can not be read out, the device can EA pin is sampled and latched during reset. If the d~
not be further programmed, and it can not execute ex- vice is powered up without a reset, the latch initializes
ternal Program Memory. Erasing the EPROM array to a random value, and holds that value until reset is
deactivates the lock bit and restores the device's full activated. It is necessary that the latched value of EA
functionality. It can then be r~programmed. be in agreement with the current logic level at that pin
in order for the device to function properly.
The procedure·for programming the lock bit is detailed
in the 87S1H data sheet.
6-26
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
ONCE Mode in the 87C51 Normal operation is restored after a normal reset is
applied.
The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51 with-
out the 87C51 having to be removed from the circuit. THE ON-CHIP OSCILLATORS
The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN HMOS Versions
is high; The on-chip oscillator circuitry for the HMOS
2. Hold ALE low as RST is deactivated. (HMOS-I and HMOS-II) members of the MCS-51 fam-
ily is a single stage linear inverter (Figure 29), intended
While the device is in ONCE mode, the Port 0 pins go for use as a crystal-controlled, positive reactance oscil-
into a float state, and the other port pins and ALE and lator (Figure 30). In this application the crystal is oper-
PSEN are weakly pulled high. The oscillator circuit ated in its fundamental response mode as an inductive
remains active. While the 87C51 is in this mode, an reactance in parallel resonance with capacitance exter-
emulator or test CPU can be used to drive the circuit. nal to the crystal.
Vee
TO INTERNAL
TIMINGCKTS
XTAL2
XTAL1
if
SUBST.
270252-23
Figure 29. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS®-51 Family
Q2
TO INTERNAL
TIMING CKTS
Vss
~-t---QUARTZ CRYSTAL
OR CERAMIC RESONATOR
270252-24
Figure 30. Using the HMOS On-Chip Oscillator
6-27
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
The crystal specifications and capacitance values (Cl To drive the HMOS parts with an external .clock
and C2 in Figure 30) are not critical. 30 pF can be used source, apply the external clock signal to XTAL2, and
in these positions at any frequency with good quality ground XTALl, as shown in Figure 31. A pullup resis-
crystals. A ceramic resonator can be used in place of tor may be used (to increase noise margin), but is op-
the crystal iii cost-sensitive applications. When a ce- tional if VOH of the driving gate exceeds the VlH MIN
ramic resonator is used, Cl and C2 are normally select- specification of XTAL2.
ed to be of somewhat higher values, typicaIly, 47 pF.
The manufacturer of the ceramic resonator should be
consulted for recommendations on the values of these CHMOS VERSIONS
capacitors.
The on-chip oscillator circuitry for the 80C5IBH,
A more in-depth discussion of crystal specifications, ce- shown in Figure 32, consists of a single stage linear
ramic resonators, and the selection of values for Cl and inverter intended for use as a crystal-controlled, posi-
C2 can be found in Application Note AP-155, "Oscilla- tive reactance oscillator in the same manner as the
tors for Microcontrollers," which is included in this HMOS parts. However, there are some important dif-
manual. ferences.
One difference is that the 80C5IBH is able to tum off
Vcc its oscillator under software control (by writing a 1 to
r the PO bit in PCON). Another difference is that in the
8051
80C51BH the internal clocking circuitry is driven by
EXTERNAL
the signal at XTALl, whereas in the HMOS versions it
OSCILLATOR
SIGNAL
t::>0-...- - 1 XTAL2
r-- XTAL1
is by the signal at XTAL2.
The feedback resistor Rr in Figure 32 consists of paral-
TTL leled n- and p- channel FETs controlled by the PO bit,
GATE ~ VSS such that Rr is opened when PO = 1. The diodes 01
WITH
TOTEM-POLE
and 02, which act as clamps to VCC and VSS, are
OUTPUT parasitic to the Rr FETs.
270252-25
Figure 31. Driving the HMOS MCS®-S1
Parts with an External Clock Source
TO INTERNAL
Vcc
TIMING CKTS
1 01
4000
XTAL1 XTAL2
D2
PD -----II+---.
270252-26
Figure 32. On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS®-S1 Family
6-28
inter HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
VCC
TO INTERNAL
TIMING CKTS
Rt
VSS
-------- XTAL1----- XTAL2------
80CS1
~--r--QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
270252-27
Figure 33_ Using the CHMOS On-Chip Oscillator
The oscillator can be used with the same external com- Rise and fall times are dependent on the external load-
ponents as the HMOS versions, as shown in Figure 33. ing that each pin must drive. They are often taken to be
Typically, CI = C2 = 30 pF when the feedback ele- something in the neighborhood of 10 nsec, measured
ment is a quartz crystal, and CI = C2 = 47 pF when a between 0.8V and 2.0V.
ceramic resonator is used.
Propagation delays are different for different pins. For
To drive the CHMOS parts with an external clock a given pin they vary with pin loading, temperature,
source, apply the external clock signal to XTALl, and VCC, and manufacturing lot. If the XTAL2 waveform
leave XTAL2 float, as shown in Figure 34. is taken as the timing reference, prop delays may vary
from 25 to 125 nsec.
The reason for this change from the way the HMOS
part is driven can be seen by comparing Figures 29 and The AC Timings section of the data sheets do not refer-
32. In the HMOS devices the internal timing circuits ence any timing to the XTAL2 waveform. Rather, they
are driven by the signal at XTAL2. In the CHMOS relate the critical edges of control and input signals to
devices the internal timing circuits are driven by the each other. The timings published in the data sheets
signal at XTALI. include the effects of propagation delays under the
specified test conditions.
80CS1
MCS®-S1 PIN DESCRIPTIONS
NC XTAL2
EXTERNAL VCC: Supply voltage.
OSCILLATOR
SIGNAL
t:>O------i XTAL1
VSS: Circuit ground potential.
VSS
CMOS GATE Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an open drain output port it can sink 8 LS
270252-28 TTL loads. Port 0 pins that have Is written to them
Figure 34. Driving the CHMOS MCS®-51 float, and in that state will function as high-impedance
Parts with an External Clock Source imputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external memory. In
this application it uses strong internal pullups when
emitting Is. Port 0 also emits code bytes during pro-
INTERNAL TIMING gram verification. In that application, external pullups
Figures 35 through 38 show when the various strobe are required.
and port signals are clocked internally. The figures do
not show rise and fall times of the signals, nor do they Port 1: Port 1 is an 8-bit bidirectional I/O port with
show propagation delays between the XTAL2 signal internal pullups. The Port 1 output buffers can sink/
and events at other pins. source 4 LS TTL loads. Port 1 pins that have Is written
6-29
HARDWARE DESCRIPTION OF THE.8051, 8052 AND 80C51
to them are pulled high by the internal pullups, and in The Port 3 output buffers can source/sink 4 LS TTL
that state can be used as inputs. As inputs, Port 1 pins loads.
that are externally being pulled low will source current
(ilL, on the data sheet) because ofthe internal pullups. RST: Reset input. A high on this pin for two machine
cycles while' the oscillator is' running resets the device.
In the 8052, pins P1.0 and Pl.l also serve the alternate
functions of T2 and T2EX. T2 is the Timer 2 external ALE/PROG: Address Latch Enable output pulse for
input. T2EX is the input through which a Timer 2 latching the low byte of the address during accesses to
"capture" is triggered. external memory. ALE is emitted at a constant rate of
'I. of the oscillator frequency, for external timing or
Port 2: Port 2 is an 8-bit bidirectional I/O port with clocking purposes, even when there are no accesses to
internal pullups. The Port 2 output buffers can sink/ external memory. (However, one ALE pulse is skipped
~ource 4 LS TTL loads. Port 2 emits the high-order during each access to external Data Me~ This pin
address byte during accesses to external meniory that is also the program pulse input (pROG during
use 16-bit addresses. In this application it uses the EPROM programming.
strong internal pullups when emitting Is. Port 2 also
receives the high-order address and control bits during PSEN: Program Store Enable is the read strobe to ex-
8751H programming and verification, and during pro- ternal Program Memory. When the device is executing
gram verification in the 8051AH. out of external Program Memory, PSEN is activated
twice each machine cycle (except that two PSEN acti-
Port 3: Port 3 is an 8-bit bidirectional I/O port with vations are~ed during accesses to external Data
internal pullups. It also serves the functions of various Memory). PSEN is not activated when the device is
special features of the MCS-51 Family, as listed below: executing out of internal Program Memory.
Port Pin Alternate Function EA/VPP: When EA is held high the CPU executes out
P3.0 RXD (serial input port) of internal Program Memory (unless the Program
P3.1 TXD (serial output port) Counter exceeds OFFFH in the 8051AH, or IFFFH in
P3.2 INTO (external interrupt 0) the 8052). Holding EA low forces the CPU to execute
P3.3 INT1 (external interrupt 1) out of externlll memory regardless of the Program
P3.4 TO (Timer 0 external input) Counter value. In the 8031AH and 8032, EA must be
P3.5 T1 (Timer 1 external input)
extremely wired low. In the EPROM devices, this pin
also receives the programming supply voltage (VPP)
P3.6 WR (external data memory
during EPROM programming. .
write strobe)
P3.7 RD (external data memory XTALl: Input to the inverting oscillator amplifier.
read strobe)
XTAL2: Output from the inverting oscillator amplifier..
ISTATE 11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1ISTATE 21
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
~~nnnnnnnnnnnnnnnnn
~UUUUUUUUUUUUUUUU~
ALE:
P2: PCHOUT PCHOUT
I PCHOUT
270252-29
Figure 35. External Program Memory Fetches
6-30
intJ HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I ~1P2 ~1P2
I
STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~1P2 ~1P2 ~In ~1P2 ~1P2 ~1P2
XTAL2:
ALE:
RD:
PO:
PCH OR PCH OR
P2: DPH OR P2 SFR OUT
P2SFR P2SFR
270252-30
Figure 36. External Data Memory Read Cycle
I I
STATE 41 STATE 5 STATE
~1P2 ~1P2 ~1P2
61 STATE 1 ISTATE 2.1 STATE 3.1 STATE 41 STATE 51
~1P2 ~1P2 ~1P2 ~1P2 ~1P2
XTAL2:
ALE:
jr--
ViR: PCLOUTIF
IS EXTERNAL
po: - - - - - I DPL OR RI
OUT
DATA OUT
~f ~
P2 PCH OR PCH OR
DPH OR P2 SFR OUT
P2SFR P2SFR
270252-31
Figure 37. External Data Memory Write Cycle.
6-31
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I ~I~ ~I~ ~I~ ~I~ ~I~
I
STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~I~ ~I~ ~I~
XTAL2:
- -YZ,P1 PO'P1~.
INPUTS S A M P L E D : . .
P2, P3, RST ~,P3, R S T = r l -
MOY PORT, SRC: OLD DATA NEW DATA
SERIAL PORT
SHIFT CLOCK
(MODE 0)'
---+I r-- RXD PIN SAMPLED RXD SAMPLED --.j ~
270252-32
Figure 38. Port Operation
6-32
Hardware Description of the 7
83C51FA
HARDWARE DESCRIPTION
OF THE 83C51FA (83C252)
INTRODUCTION Port
Name Function
Pin
The 83C51FA is an 8-bit control-oriented microcon-
troller based on the 8051 architecture. The 83C51FA is P1.2 ECI External Count Input to the PCA
an enhanced version of the 80C51BH and incorporates
many new features. These features include: P1.S CEXO External 110 for Compare/Capture
Module 0
• Programmable Counter Array with
- Compare/Capture P1.4 CEX1 External I/O for Comparel.Capture
- High Speed Output Module 1
- Pulse Width Modulator P1.5 CEX2 External I/O for Compare/Capture
- Watchdog Timer Module 2
• Programmable Serial Channel
- Automatic Address Recognition P1,6 CEXS External I/O for Compare/Capture
- Framing Error Detection ModuleS
• Enhanced Power Down Mode P1.7 CEX4 External I/O for Compare/Capture
Module 4
• 16-Bit Up/Down Timer/Counter
• 8K Factory Mask ROM
The time-base for the PCA is a programmable 16-bit
• 256 Bytes of On-Chip Data RAM timer/counter. This timer is the only one that can serve
• 7 Interrupt Sources the PCA. This timer is started or stopped by setting or
clearing bit CR in the Special Function Register
The 83C51FA uses the standard 8051 instruction set CCON, and can be programmed to count any of the
and is pin for pin compatible with the existing following signals (where Fosc is the 83C51FA oscilla-
MCS®-5l products, However, the numbering system tor frequency):
for the 83C51FA is slightly different. The 83C51FA is • Fosc/12
the factory masked ROM device; the 80C51FA is the The Counter increments once per machine cycle.
ROMless device; and the 87C51FA is the EPROM de-
vice. • Fosc/4
With a 16 MHz crystal, the counter increments once
It is assumed that the reader is familiar with the 8051 every 250 ns.
architecture. For more detailed information on the • Timer 0 overflow
8051, consult the "Hardware Description of the 8051 The counteds incremented whenever Timer 0 over-
and 8052" chapter. flows. This mode allows a programmable input fre-
quency to the PCA.
• External input on ECI pin
OVERVIEW OF THE PCA The counter is incremented when a I-to-O transition
is detected on the ECI pin. The counter is limited to
The Programmable Timer/Counter Array (PCA) con- input frequencies of Fosc/8 in this mode.
sists of a 16-bit counter and five 16-bit compare/cap-
ture modules. Each compare/capture module has its The 16-bit PCA timer/counter can also be pro-
own mode register, CCAPMn, which is used to config- grammed to either run or pause when the CPU is in
ure the module. The compare/capture modules and the Idle mode.
PCA counter share Port 1 pins for hardware interfacing
as shown below:
7-1
intJ HARDWARE DESCRIPTION OF THE 83C51FA
Each of the five 16-bit compare/capture modules can High speed output mode, an interrupt can be generated
be programmed to do one of the following: when the module executes its function.
• 16-bit capture; positive edge activated.
• 16-bit capture, negative edge activated. DESCRIPTION OF THE PCA
• 16-bit capture, both positive and negative edge acti- HARDWARE
vated.
• 16-bit software timer. The time base for the PCA is a 16-bit timer/counter
consisting of registers CH and CL (high and low bytes
• High-speed output. of the count value), controlled by Special Function
• 8-bit Pulse Width Modulator (PWM). Register CCON (Figure 1) and a mode register CMOD
(Figure 2).
In addition, Compare/Capture module 4 can be used as
a Watchdog Timer. CCON contains bits CF (Counter Flag) which gets set
by hardware when the counter rolls over and CR
When any o.f the compare/capture modules. are pro- (Counter Run) which is used to tum the counter on
grammed to the capture mode or the 16-bit .Timer/ and off. It also contains interrupt flags from each of the
five PCA modules.
CF CR CCF4 CCF3 CCF2 CCF1 CCFO·
Address = OD8H Reset Value = OOXOOOOOB
Symbol Position Function
CF CCON.7 PCA Counter Overflow flag. Set by hardware when the
counter rolls over. CF flags an interrupt if bit ECF in CMOD is
. set. CF may be set by either hardware or software. It can only
be cleared by software.
CR CCON.S Counter Run control bit. Set by software to turn the PCA
counter on. Clear by software to turn the PCA counter off.
- CCON.5 Not implemented, reserved for future use. •
CCF4 CCON.4 PCA Module 4 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
CCF3 CCON.3 PCA Module 3 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
CCF2 CCON.2 PCA Module 2 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
CCF1 CCON.1 PCA Module 1 interrupt flag. Set by hardware when a match or
capture occurs. Must be cieared by sonware.
CCFO CCON.O PCA Module 0 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
Figure 1. CCON: Counter Control Register
NOTE:
'User software should not write'1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.
7-2
inter HARDWARE DESCRIPTION OF THE 83C51FA
CMOD contains the following bits: CPS! and CPSO-select the counter input
CIDL- selects whether the PCA counter continues to ECF- enables CF to generate an interrupt.
run in Idle Mode
WDTE- enables the Watchdog Timer function
CIDL WDTE CPS1 CPSO ECF
Address = OD9H Reset Value = OOXXXOOOB
Symbol Position Function
CIDL CMOD.7 Counter Idle control: CIDL = 0 programs PCA Counter to continue
functioning during Idle mode. CIDL = 1 programs it to be gated off during
Idle.
WDTE CMOD.6 Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function.
WDTE = 1 enables it.
- CMOD.5 Not implem~nted, reserved for future use. •
- CMODA Not implemented, reserved for future use.'
- CMOD.3 Not implemented, reserved for future use.'
CPS1 CMOD.2 Count Pulse Select bit 1.
CPSO CMOD.1 Count Pulse Select bit o.
CPS1 CPSO PCA Count Pulse Selected
0 0 Internal clock, Fosc/12
0 1 Internal clock, Fosc/4
1 0 Timer 0 overflow
1 1 External clock at ECI pin (P1.2)
(maximum rate = Fosc/a)
ECF CMOD.O Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to
generate an interrupt. ECF = 0 disables that function of CF.
Figure 2. CMOD: Counter Mode Register
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.
Each of the five PCA modules has a Compare/Capture MATn-enables a comparator match to set the cor-
Mode register, CCAPMn, n = 0 through 4 (Figure 3). responding CCFn flag
The following bits in each CCAPMn register define TOGn- enables a comparator match to toggle the
that module's function. CEXnpin
ECOMn- enables that module's comparator function PWMn- enables the PWM output at the CEXn pin
CAPPn- enables the capture function on positive ECCFn- enables any Compare/Capture event to flag
transitions at theCEXn pin an interrupt
CAPNn- enables the capture function on negative
transitions at the CEXn pin
7-3
intJ HARDWARE DESCRIPTION OF THE 83C51FA
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Addresses = OOAH (n = 0) Reset Value = XOOOOOOOB
OOBH (n= 1)
OOCH(n=2)
OOOH (n=3)
OOEH (n=4)
Symbol Position Function
- CCAPMn.7 Not implemented, reserved for future use.·
ECOMn CCAPMn.6 ECOMn = 1 enables the comparator function. This bit is
automatically cleared by any write to the CCAPnL register,
and automatically set by any write to the CCAPnH register.
This prevents unintended matches from occurring during
writes to the 16:bit Compare/Capture register.
CAPPn CCAPMn.5 Positive edge capture enable. When CAPPn = 1, a positive
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module'S Compare/Capture register.
CAPNn CCAPMn.4 Negative edge capture enable. When CAPNn = 1, a negative
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module's Compare/Capture register.
MATn CCAPMn.3 When MATn = 1, a match of the PCA Counter with this
module'S Compare/Capture register causes the CCFn bit in
.. CCON to be set, flagging an interrupt.
TOGn CCAPMn.2 When TOGn = 1, a match of the PCA Counter with this
module's Compare/Capture register causes the CEXn pin to
toggle.
PWMn CCAPMn.1 When PWMn = 1, CEXn is driven high when the low byte of
the PCA Counter (CL) matches the low byte of this module's
Compare/Capture register (CCAPnL). When CL rolls over to
OOH, the CEXn pin is driven low and CCAPnL is updated with
the valLie in CCAPnH. This enables the CEXn pin to be used
as a pulse width modulated output. Software varies the pulse
. width by writing to CCAPnH, -
ECCFn CCAPMn.O Enables Compare/Capture Flag CCFn in the CCON register to
generate an interrupt.
Figure 3. CCAPMn: Compare/Capture Mode Register for PCA Module n
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
i6served bit is indateimlnate.
There are 6 modes of operation for each of the 5. PCA defined function. Invalid combinations will produce un-
modules: Shown below are the combinations of bits in defined results.
the CCAPMn register that are valid and have a
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function
0 0 0 0 0 0 0 No operation
X 1 0 0 0 0 X 16-bit capture by a positive-edge
trigger on CEXn
X 0 1 0 0 0 X 16-bit capture by a negativecedge
trigger on CEXn
X 1 1 0 0 0 X 16-bit capture by a transition
on CEXn
1 0 0 1 0 0 X 16-bit software timer
1 0 0 1 1 0 .x High Speed Output
1 0 0 0 0 1 0 a-bit PWM
x= Don't Care
7-4
inter HARDWARE DESCRIPTION OF THE 83C51FA
16-Bit TimerICounter 16-Bit Capture Mode
The 5 Compare/Capture modules share a 16-bit timer/ Setting CAPPn and/or CAPNn puts Compare/Cap-
counter as their "time base". The timer/counter, shown ture module n into Input Capture mode, as shown in
in Figure 4, can be programmed to increment in 4 dif- Figure 5. The external input pins CEXO through CEX4
ferent ways. The modes are shown below with the setup are sampled for a transition. When a valid transition is
values in the CMOD register: detected for the current mode of operation (rising edge,
falling edge, or either edge), CL is transferred into the
CCAPnL register, and CH is transferred into
CPS1 CPSO Method of Incrementing CCAPnH. The resulting value in the Capture Regis-
0 0 Internally clocked at Oscillator ters, CCAPnL and CCAPnH, reflect the values in CL
Frequency 112 and CH at the time a transition was detected on the
CEXn pin. The event flags an interrupt if bit ECCFn is
0 1 Internally clocked at Oscillator set.
Frequency 14
1 0 Incremented when Timer 0 overflows
1 1 Externally clocked on Pin P1.2/ECI.
(Limited to Oscillator Frequency 18)
TO PCA MODULES 0-4
COUNT
INTERRUPT
ENABLE
Fosc/12
Fosc/4
TIMER 0
OVERFLOW
'-t===:..:::::t-----[]ECI
270421-1
Figure 4. PCA Timer/Counter
7-5
HARDWARE DESCRIPTION OF THE 83C51FA
PCA TIMER / COUNTER VALUE
CEXn
CCAPMn REGISTER
270421-2
n = 0, 1, 2, 3 or 4
x = Don'l Care
Figure 5. 16-Blt Capture Mode
16 Bit Timer with the count value of the counter module. When they
are equal, a match signal is generated which can set the
Setting bit ECOMn in the Compare/Capture. Mode status bit CCFn in· the PCA COntrol register CCON
Register (CCAPMn) enables the Comparator function and/or toggle the corresponding CEXn pin.
as shown in Figure 6. The Comparator compares a
16-bit value stored in the compare/capture register
WOTE
(MODULE 4 ONLY)
_ . L____- II CAUSE
I
PCA TIMER
16 r-----------,
COUNTER VALUE
r----------~---------_1---------~
RESET
WRITE TO
. CCAPnL
RESET ------L..;
WRITE TO
CCAPnH
270421-3
n = 0, 1, 2, 3 or 4
x = Don'l Care
Figure 6. 16-Bit Comparator Mode
7-6
inter HARDWARE DESCRIPTION OF THE 83C51FA
Bit ECOMn is set by software and is initially cleared reverses the logic level of its" I/O pin, and/or can gener-
during reset. It also gets cleared when a write to ate an interrupt as shown in Figure 6. When the PCA
CCAPnL register happens and is set if CCAPnH is module is configured in this manner as a High Speed
written to. This feature prevents ·action until the com- Output, the user, by setting or clearing the pin in soft-
plete 16-bit value is loaded into the CCAPnH/L regis- ware, can select whether the module's output pin will
ter if the low value is written to the 16-bit register first. change from a logical 0 to a logical 1 or vice versa.
When the MATn (Match) bit is set in the Compare/
Capture Mode Register, the corresponding module in Pulse Width Modulator Mode
the PCA is configured as a 16-bit timer. When the val-
ue in the 16-bit Compare/Capture register is equal to Any or all of the 5 modules of the PCA can be pro-
the 16-bit value on the Count Bus, the hardware sets grammed to be a Pulse Width Modulator as shown in
the CCFn flag. This bit flags an interrupt if ECCFn is Figure 7. In this mode, the PWM output can be used to
also set. convert digital data to an analog signal by simple exter-
nal circuitry. The frequency of the PWM depends on
which of the four clock sources is selected for the PCA
High Speed Output Timer. With a 16 MHz crystal the maximum frequency
of the output waveform/of the PWM is 15.6 KHz. The
When programmed as a timer, the PCA module, dur- duty cycle of the waveform is controlled by the con-
ing every cycle, compares the contents of the 16-bit tents of an 8-bit register (CCAPnH) that can be pro-
timer with the preset value of its Compare registers. grammed to be any integer" from 0 to 255.
When a match" occurs, if bit TOGn is set, the module"
270421-4
n = 0, 1, 2, 3 or 4
x = Don't Care
Figure 7. 8-Bit PWM Mode
7-7
intJ HARDWARE DESCRIPTION OF THE 83C51FA
Watch Dog Timer Mode not activated unless the received byte is an address byte
(9th data bit = I), and the address corresponds to ei-
A Watchdog Timer js a circuit that automatically in- ther a Given Address or a Broadcast Address.
vokes a reset unless the system being watched sends
regular hold-off signals to the Watchdog. These circuits The feature works the same way in the 8-bit mode
are used in applications that are subject to electrical (mode I) as in the 9-bit modes, except that the stop bit
noise, power glitches, electrostatic discharges, etc., or takes the place of the 9th data bit. That is, if SM2 is set,
where high reliability is required with hands-off opera- RI is not activated unless the received byte agrees with
tion. either the Given or Broadcast address and is terminated
by a valid stop bit.
In this mode, every time the count in the PCA counter
module matches the value 'stored in compare/capture The Given Address is specified by the contents of two
module 4, an internal reset is generated. The' bit that new SFRs: SADDR and SADEN. The 83C51FA's in-
selects this mode is WDTE in the CMOD register. dividual address is defined in SADDR. SADEN is a
Compare/capture module 4 should be set up to be a mask byte that defines don't-cares in SADDR to form '
16-bit timer or a High Speed Output in the Watchdog the Given Address. For example,
Timer mode. ' SADDR = 01010110
SADEN = 11111100
To hold off the reset, the user's software can:
spec,ify the Given Address to be OIOIOIXX.
• Continually reset the PCA 16-bit timer value to a
lower value than the reset value in module 4. The Broadcast. Address is formed from the logical OR
• Clear the WDTE bit when a match is about to oc- of SADDR and SADEN. Zeros in the logical OR are
cur, and then set the WDTE bit just after the match don't-cares. For example, the values given above for
condition (temporarily disabling the feature). SADDR and SADEN defme the broadcast address to
or be 11 111 11X.
• Continually change the CCAP4H and CCAP4L val-
ue to one that is "far" from a match value. Automatic Address Recognition allows a host proces-
sor to establish communication -with an addressed
Finally, the Watchdog Timer can be used to program a slave, without all the other slave controllers having to
reset by allowing a match to occur. respond to the transmission. The addressed slave then
clears its SM2 bit to enable reception of data bytes (9th
data bit = 0) from the host.
EXTENDED SERIAL PORT FEATURES The Given and Broadcast addresses allow each micro-
The full duplex serial port of the 83C51FA is the same controller to have its own (Given) address and a com-
as the serial port of the 8052 but with two added fea- mon (Broadcast) address. A "host" on the serial chan-
tures: Automatic Address Recognition and Framing nel can selectively address single 83C51FA's using the
Error Detection. 'Given Address or all 83C51FA's using the Broadcast
Address.
Automatic Address Recognition On reset, the SADDR and SADEN registers are initial-
ized to OOH. This defines the Given and Broadcast ad-
Automatic Address Recognition is useful in multi-proc- dresses to be XXXXXXXX (all don't-cares) for back-
essor applications in which the CPUs communicate wards compatibility with the MCS®-51 family.
through the serial channel. Using this feature, the
83C51FA's Serial Port refrains from interrupting the
CPU unless it receives its own address. Automatic Ad- Framing Error Detection
dress Recognition is enabled by setting the SM2 bit in
SCON. - Another new feature of the Serial Port is Framing Er-
ror Detection. This allows the receiving controller to
Normally the Serial Port would be configured into ei- check the stop bit in modes I, 2, or 3. A missing stop
ther of the 9-bit modes (modes 2 and 3). In these bit causes a Framing Error bit, FE, to be set. The FE
modes, if SM2 is set, the Receive Interrupt flag RI is bit can then be checked in software immediately after
each reception to detect the lack of a valid stop bit. A
missing stop bit can be caused, for example, by noise on
the serial lines, or by two CPUs trying to transmit at
the same time.
7-8
inter HARDWARE DESCRIPTION OF THE 83C51FA
The FE bit, once set, must be cleared in software. A iced, the next instruction executed after RETI will be
valid stop bit does not cause the FE bit to be cleared. the one following the instruction that put the device in
Power Down.
The FE bit resides in SCON, and has the same bit ad-
dress as the SMO bit. A new control bit in the PCON
register determines if accesses to the SMO/FE bit ad- Power Off Flag
dress are to SMO or to FE. The new control bit in
PCON is called SMODO, and resides at PCON.6 (Fig- A Power Off Flag, POF, has been added to the PCON
ure 8). IfSMODO = 0, then accesses to SCON.7 are to register (Figure 8). This flag is set by hardware when
SMO. IfSMODO = I, then accesses to SCON.7 are to VCC comes up, and can be set or cleared by software.
FE. This allows one to distinguish between a "cold start"
reset and a "warm start" reset.
REDUCED POWER MODES A cold start reset is one that is coincident with VCC
being turned on to the device after it was turned off. A
warm start reset is one that. occurs after the device has
Idle Mode already been powered up and running. A warm start
reset could be generated, for example, by a Watchdog
Idle Mode is the same in the 83C51FA as in the Timer, or as an exit from Power Down Mode.
80C5IBH. Note that the PCA can be programmed to·
either pause or continue operations during Idle. To use the feature, one checks the POF bit in software
immediately after reset. POF = I would indicate a
cold start. The software then clears POF, and com-
Power Down Mode mences its tasks. POF = 0 immediately after reset
would indicate a warm start.
The Power Down Mode on the 83C51FA differs from
the SOC5IBH in one respect: the 83C51FA can exit VCC must remain above 3 volts for POF to retain a o.
Power Down with either a hardware Reset or an Exter-
nal Interrupt. (The 80C5IBH can only exit Power
Down with a hardware Reset.) An exit with an Exter- TIMER 2 AS AN UP/DOWN COUNTER
nal Interrupt allows not only the on-chip RAM to be
saved but also the Special Function Registers. Timer 2 is a general purpose 16-bit timer/counter
which is present in the 8052 and in the 83C51FA. Tim-
The External Interrupt, INTO or INTI, must be en- er 2 has the same functionality in both of these devices
abled and configured as level-sensitive to properly ter- except that in the 8052 Timer 2 can only count up, and
minate Power Down. Also the interrupt should not be in the 83C51FA Timer 2 can be programmed to count
executed before Vee is restored to its normal operating up or down. The option to count up or down becomes
level, and must be held down long enough for the oscil- available when the Timer is configured to its 16-bit
lator to restart and stabilize. Once the interrupt is serv- auto-reload mode.
SM001 SMOOO x POF GF1 GFO PO IOL
Address = 087H . Reset Value = OOXXOOOOB
POF Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This flag allows
detection.of a power failure caused reset. Vee must remain above 3V to retain this bit.
SMODO When set, Read/Writc:: accesses to SCON.7 are to the FE bit. When clear, Read/Write. accesses to
SCON.7 are to the SMO bit.
SMODI Same as the SMOD bit in the MSC-51 architecture. The additional bits are defined to be compatible with
the 8052 and 80C51BH.
Figure 8. PCON: Power Control Register
7-9
inter HARDWARE DESCRIPTION OF THE 83C51FA
x x x x x x x DCEN
Address = OC9H Reset Value = XXXX XXXOB
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
Figure 9. T2MOD: Timer 2 Mode Control Register
~
~ .~ !C/f2=o
T2 PIN ------~
TIMER 2
INTERRUPT
T2EX PIN ------+1
EXEN2
270421-5
Figure 10. Timer 2 Auto-Reload Mode when DCEN = 0
The Special Function Register T2MOD (present in the When DCEN is set (I), the Timer 2 Auto-Reload Mode
83C51FA but not in the 8052) contains a bit named takes the form shown in Figure 11. The T2EX pin now
DCEN (Down Counter Enable). T2MOD is shown in controls the direction of count. A logic 1 at T2EX
Figure 9. When this bit is clear (0), the Timer 2 Auto- makes Timer 2 count up. A logic 0 at T2EX makes
Reload Mode in the 83C51FA is exactly the same as iii Timer 2 count down. Also, the EXF2 bit toggles every
the 8052. Figure,IO shows Timer 2 in Auto-Reload time Timer 2 overflows or underflows. In this operating
Mode with DCEN = o. mode, the EXF2 bit does not flag an interrupt.
270421-6
Figure 11. Timer 2 Auto-Reload Mode when DC EN =:' 1
7-10
HARDWARE DESCRIPTION OF THE 83C51FA
UPPER 128 BYTES OF RAM FUNCTIONS OF PORT 1 PINS
The 83C51FA implements a full 256 bytes of on-chip P1.0/T2 may be used as an external count input to
data RAM. As in the 8052, the upper 128 bytes occupy Timer 2.
a parallel address space to the Special Function Regis-
ters. That means they have the same addresses, but they Pl.l/T2EX can be used to trigger a capture if Timer 2
are physically separate from SFR space. is in the Capture Mode, or to trigger a reload if Timer 2
is in the Auto-Reload Mode and DCEN is set to O.
When an instruction accesses an internal location above T2EX can also control the count direction if Timer 2 is
address 7FH, the CPU knows whether the access is to in the Auto-Reload Mode and DCEN set to 1. Finally,
the upper 128 bytes of data RAM or to SFR space by T2EX can be used as an external interrupt if Timer 2 is
the addressing mode used in the instruction. Instruc- being used as a baud-rate generator.
tions that use direct addressing access SFR space. For
example, P1.2/ECI takes the external signal to the PCA counter.
MOV OAOH, # data The frequency of the external signal is limited to one
eighth of the oscillator frequency or less. The PCA
accesses the SFR at location OAOH (which is P2). In- count is incremented every time the ECI pin makes a
structions that use indirect addressing access the upper 1-0 transition. .
128 bytes of data RAM. For example,
P1.3 through P1.7/CEXn functions depend on the con-
MOV @RO,#data figuration of their corresponding Compare/Capture
modules in the PCA. They can be configured to be a
~here RO contains OAOH, accesses the data byte at ad- rising edge, falling edge, or an "either edge" trigger
dress OAOH, rather than P2 (whose address is OAOH). input to a Compare/Capture module. They can also be
high speed outputs which toggle every time the PCA
Note that stack operations are examples of indirect ad- count matches the value in the corresponding Com-
dressing, so the upper 128 bytes of data RAM are avail- pare/Capture register. Finally, any of these pins can be
able as stack space. configured as an 8-bit Pulse Width Modulated (PWM)
output. In the PWM mode, the pin will be in the logical
"0" state for a programmable length of time, and will
PIN DESCRIPTION be in the logical "1" state for· the remainder of the
PWM duty cycle. The PWM duty cycle is variable be-
The 83C51FA is Pin-for-Pin compatible with the tween 1/256 and 256/256.
80C51BH. Port 1 on the 83C51FA has 8052 functional-
ity and additionally serves the PCA as shown below. Detailed descriptions of the functions of the PCA pins
can also be found in section 1.2, PCA feature descrip-
Port 1 pins and Alternate Functions. tion.
Port
Name Function
Pin
INTERRUPT STRUCTURE
P1.0 T2 External Count Input to Timer 2
P1.1 T2EX Timer 2 Capture/Reload Trigger The 83C51FA provides 7 interrupt sources. Five of
P1.2 ECI External Count Input to the PCA them (INTO/ and INTI/, Timer 0 and Timer I, and
P1.3 CEXO External 1/0 for Compare/Capture the Serial Port) are identical with those provided in the
Module 0 80C51BH. The 83C51FA also provides a Timer 2 inter-
P1.4 CEX1 External 1/0 for Compare/Capture rupt which is identical with the Timer 2 interrupt in the
Module 1 8052, and a PCA interrupt which is only found in the
P1.5 CEX2 External 1/0 for Compare/Capture 83C51FA. These interrupt sources are shown in Figure
Module 2 12.
P1.6 CEX3 External 110 for Compare/Capture
Module 3
P1.7 CEX4 External 110 for Compare/Capture
Module 4
7-11
HARDWARE DESCRIPTION OF THE 83C51FA
INTO---cY ITO
TFO-------------------------.~
INT1,...---<:r-
TF1------------------------.~
INTERRUPT
SOURCES
CF-3ECF
~\--------..,D)--------------+~
TF2 _ _ _ _ _ _ _ _
EXF2- -
...,D.·. ____________•
,- ~
270421-7
(Sea oxceptions ,,·,hen Timer 2 is used as baud rate gl3l"!Aratnr or an up/down counter.)
Figure 12. 83C51FA Interrupt Sources
The Timer 2 interrupt is generated by the logical OR of All of the bits that generate interrupts can be set or
TF2 and EXF2. Neither of these flags is cleared by cleared in software, with the same result as though it
hardware when the service routine is vectored to. In had been set or Cleared by hardware. That is, interrupts
fact, the service routine may have to determine whether can be generated or pending interrupts can be cancelled
it was TF2 or EXF2 that generated the interrupt, and in software. . .
the bit will have to be cleared in software.
Each of these interrupt sources can be individually en-
The PCA interrupt is generated by the logical OR of abled or disabled by setting or clearing a bit in Special
CF, CCFO, CCF1, CCF2, CCF3, and CCF4. None of Function Register IE (Figure 13). Note that IE also
these flags is Cleared by hardware when the service rou- contains a global disable bit, EA. If EA is set (I), the
tine is vectored to. In fact, normally the service routine interrupts· are individually enabled or disabled by their
will have to determine which bit flagged the interrupt corresponding bits in IE. If EA is clear (0), all inter-
and clear that bit in software. rupts are disabled.
7-12
1
\
HARDWARE DESCRIPTION OF THE 83C51FA
I
EA EC ET2 ES ET1 EX1 ETO EXO
Address = OASH Reset Value = OOOOOOOOB
Symbol Position Function
EA 1E.7 Disables all interrupts. If EA = 0, all interrupts are disabled. If
EA = 1, each interrupt can be individually enabled or disabled
by setting or clearing its enable bit.
EC IE.6 Enables or disables the PCA interrupt. EC = 1 enables it.
EC = 0 disables it.
ET2 IE.5 Enables or disables the Timer 2 interrupt. ET2 = 1 enables it.
ET2 = 0 disables it.
ES lEA Enables or disables the Serial Port interrupt. ES = 1 enables
it. ES = 0 disables it.
ET1 1E.3 Enables or disables the Timer 1 interrupt. ET1 = 1 enables it.
ET1 = 0 disables it.
EX1 IE.2 Enables or disables External Interrupt 1. EX1 = 1 enables it.
EX1 = 0 disables it.
ETO IE.1 Enables or disables the Timer 0 interrupt. ETO = 1 enables it.
ETO = 0 disables it.
EXO IE.O Enables or disables External Interrupt O. EXO = 1 enables it.
EXO = 0 disables it.
Figure 13. IE: Interrupt Enable Register
PRIORITY LEVEL STRUCTURE
priority interrupt can be interrupted by a high-priority
Each interrupt source can be individually programmed interrupt, but not by another low-priority interrupt. A
to one of two priority levels by setting or clearing a bit high-priority interrupt can't be interrupted by any oth-
in Special Function Register IP (Figure 14). A low- er interrupt source.
PPC PT2 PS PT1 PX1 PTO PXO
Address = OBSH Reset Value = XOOOOOOOB
Symbol Position Function
- IP.7 Not implemented, reserved for future use. •
PPC IP.6 Defines the PCA interrupt priority level. PPC = 1 programs it
to the high priority level.
PT2 IP.5 Defines the Timer 2 interrupt priority level. PT2 = 1 programs
it to the high priority level.
PS IPA Defines the Serial Port interrupt priority level. PS = 1
programs it to the high priority level.
PT1 IP.3 Defines the Timer 1 interrupt priority level. PT1 = 1 programs
it to the high priority level.
PX1 IP.2 Defines the External Interrupt 1 priority level. PX1 =1
programs it to the high priority level.
PTO IP.1 Defines the Timer 0 interrupt priority level. PTO = 1 programs
it to the high priority level.
PXO IP.O Defines the External Interrupt 0 priority level. PXO =1
programs it to the high priority level.
NOTE:
·User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.
Figure 14. IP: Interrupt Priority Register
7-13
intJ HARDWARE DESCRIPTION OF THE 83C51FA
If two interrupts of different priority levels are flagged location of the interrupt service routine as shoWn be-
simultaneously, the interrupt request of the higher pri- low.
ority level is serviced. If interrupts of the same priority SOURCE STARTING ADDRESS OF
level are flagged simultaneously, an internal polling se- SERVICE ROUTINE
quence determines which interrupt request is serviced. lEO 0003H
Thus within each priority level there is a second priori- .
TFO OOOBH
ty structure determined by the following polling se-
IE1 0013H
quence:
TF1 001BH
SOURCE PRIORITY WITHIN LEVEL 0023H
RI+TI
1. lEO (highest) TF2+EXF2 002BH
2. TFO PCA 0033H
3. lEI
Execution proc~eds from that location until the RETI
4. TFI instruction is encountered, which terminates the inter-
5.PCA rupt service routine. Note that the starting addresses of
6.RI+TI consecutive interrupt service routines are only 8 bytes
apart. That means if consecutive interrupts are being
7. TF2+ EXF2 (lowest) used (lEO and TFO, for example, or. TFO and lEI), and
if the first interrupt routine is more than 7 bytes long,
Note that the "priority within level" structure is only then that routine will have to execute a jump out to
used to resolve simultaneous requests of the same prior- some other memory location where the service routine
ity level. can be completed without overlapping the starting ad-
·dress of the next interrupt routine. .
LOCATION OF INTERRUPT SERVICE . Note that, although the polling position of the PCA-
ROUTINES generated interrilpt is higher than that of the Serial
Port, the starting address of the Serial Port interrupt
The Interrupt Control System acknowledges an inter- routine is unchanged from the 8051. This is for back-
rupt request by executing a hardware-generated wards software compatibility. Similarly, the Timer 2
LCALL to the appropriate service routine. The hard- interrupt 'starting addreSs is compatible with the 8052.
ware-generated LCALL pushes the contents of the Pro- This allows conversion of 8052 (HMOS) designs to the
gram Counter onto the stack (but it does not'save the 83C51FA (CHMOS) with no software modification.
PSW) and reloads the PC with the starting
7-14
inter HARDWARE DESCRIPTION OF THE 83C51FA
SPECIAL FUNCTION REGISTERS
A map of the Special Function Register (SFR) space is User software should not write Is to these unimple-
shown in Table 1. mented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
Note that not all of the addresses are occupied. Unoc- the reset or inactive values of the new bits will always
cupied addresses are not implemented on the chip. be 0, and their active values will be I.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.
Table 1. Special Function Register Memory Map and Values After Reset
F8 CH CCAPOH CCAP1H CCAP2H CCAP3H CCAP4H FF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
FO *S F7
00000000
E8 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EO 'ACC E7
00000000
08 CCON CMOO CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 OF
OOXOOOOO OOXXXOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO XOOOOOOO
DO • PSW 07
00000000
C8 T2CON T2MOO RCAP2L RCAP2H TL2 TH2 CF
00000000 XXXXXXXO 00000000 00000000 00000000 00000000
co C7
S8 • IP SAOEN SF
XOOOOOOO 00000000
So * P3 S7
11111111
A8 • IE SAOOR AF
00000000 00000000
AO • P2 A7
11111111
98 'SCON * SSUF 9F
00000000 XXXXXXXX
90 • P1 97
11111111
88 " TCON *TMOO • TLO • TL1 • THO, • TH1 8F
00000000 00000000 00000000 00000000 00000000 00000000
80 " PO • SP • OPL • OPH 'PCON •• 87
11111111 00000111 00000000 00000000 OOXXOOOO
• = Found In the 8051 core (See 8051 Hardware Description for explanations of these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.
X = Undefined.
7-15
Hardware Description of the 8'
83C152
HARDWARE DESCRIPTION
OF THE 83C152
1.0 INTRODUCTION use of external program memory. The second difference
is that RESET is active low in the 83CI52 and active
The 83CI52 Universal Communications Controller is high in the 80C51BH. This is very important to design-
an 8-bit microcontroller designed for the intelligent ers who may currently be using the 80C51BH and plan-
management of peripheral systems or components. The ning to use the 83C152, or are planning on using both
83CI52 is a derivative of the 80C51BH and retains the devices on the same board. The third difference is that
same functionality. The 83CI52 is fabricated on the GFO and GFI, general purpose flags in PCON, have
same CHMOS III process as the 80C51BH. What been renamed GFIEN and XRCLK. GFIEN enables
makes the 83CI52 different is that it has added func- idle flags to be generated in SDLC mode, and XRCLK
tions and peripherals to the basic 80C5IBH architec- enables the receiver to be externally clocked. All of the
ture that are supported by new Special Function Regis- previously unused bits are now being used and inter-
ters (SFRs). These enhancements include: a high speed rupt vectors have been added to support the new en-
multi-protocol serial communication interface, two hancements. Programmers using old code generated for
channels for DMA transfers, HOLD/HLDA bus con- the 80C51BH will have to examine their programs to
trol, a fifth I/O port, expanded data memory, and ex- ensure that new bits are properly loaded, and that the
panded program memory. new interrupt vectors will not interfere with their pro-
gram.
In addition to a standard UART, referred to here as
Local Serial Channel (LSC) , the 83Cl52 has an on- Throughout the rest of this manual the 80CI52 and the
board multi-protocol communication controller called 83CI52 will be referred to generically as the "CI52".
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definable protocols, The CI52 is based on the 80C51BH architecture and
and a subset of HDLC protocols. The GSC capabilities utilizes the same 80C5IBH instruction set. Figure 1.1 is
include: address recognition, collision resolution, CRC a block diagram of the C152. Readers are urged to
generation, flag generation, automatic retransmission, compare this block diagram with the 80C51BH block
and a hardware based acknowledge feature. This high diagram. There have been no new instructions added.
speed serial channel is capable of implementing the All the new features and peripherals are supported by
Data Link Layer and the Physical Link Layer as shown an extension of the Special Function Registers (SFRs).
in the OSI open systems communication model. This Very little of the information pertaining specifically to
model can be found in the document "Reference Model the 80C5IBH core will be discussed in this chapter.
for Open Systems Interconnection Architecture", The detailed information on such functions as: the in-
ISO/TC97/SCI6 N309. struction set, port operation, timer/counters, etc., can
be found in the MCS®-51 Architecture chapter in the
The DMA circuitry consists of two 8-bit DMA chan- Intel Embedded Controller Handbook. Knowledge of
nels with 16-bit addressability. The control signals; the 80C5IBH is required to fully understand this man-
Read (RD), Write (WR), hold and hold acknowledge ual and the operation of the C152. To gain a basic un-
(HOLD/HLDA) are used to access external memory. derstanding on the operation of the 80C51BH, the
The DMA channels are capable of addressing up to reader should familiarize himself with the entire MCS-
64K bytes (16 bits). The destination or source address 51 chapter of the Embedded Controller Handbook.
!;an be automatically incremented. The lower 8 bits of
the address are multiplexed on the data bus Port 0 and Another source of information that the reader may find
the upper eight bits of address will be on Port 2. Data is helpful is Intel's LAN Components User's Manual, or-
transmitted over an 8-bit address/data bus. Up to 64K . der number 230814. Inside are descriptions of various
bytes of data may be transmitted for each DMA activa- protocols, application examples, and application notes
tion. dealing with different serial communication environ-
ments.
The new I/O port (P4) functions the same as Ports 1-3,
found on the 80C51BH.
2.0 COMPARISON OF 80C152 AND
Internal memory has been doubled in the 83C152. Data 80C51BH FEATURES
memory has been expanded to 256 bytes, and internal
program memory has been expanded to 8K bytes.
2.1 Memory Space
There are also some specific differences between the A good understanding of the memory space and how it
83CI52 and the 80C51BH. The first is that the number- is used in the operation of MCS-51 products is essen-
ing system between the 83CI52 and the 80C5IBH is tial. All the enhancements on the CI52 are implement-
slightly different. The 83CI52 and the 80C5IBH are ed by accessing Special Function Registers (SFRs),
factory masked ROM devices. The 80CI52 and the added data memory, or added program memory.
80C3IBH are ROMless devices which require the
8-1
P4.0-P4.7 PO .0- PO.7
l
SARLI
SARHI
DARL1
DARHI
BCRL1 :t:
~
::u
c
:e~
"'1'1 ::u
c· m
......
c::
III
C
m
en
:.. n
(Xl ID
::u
N n0" =ti
-4
7<: (5
C Z
..
iii'
eD
III
o."
-4
3
~"
:t:
m
CI)
Co)
....n
U1
N
CRC
GENERATOR
ADRO-3
BAUD TCDCNT
Pl.O- Pl.7 P3.0- P3.7
270427-7
HARDWARE DESCRIPTION OF THE 83C152
2.1.1 SPECIAL FUNCTION REGISTERS (SFRs) (IDA), Source Address Space bit (SAS). Increment
~ource Address bit (ISA), DMA Channel Mode bit
The following list contains all the SFRs, their names (DM), Transfer Mode bit (TM), DMA Done bit
and function. All of the SFRs of the 80C51BH are reo (DONE), and the GO bit (GO). DCONO is used to
tained and for a detailed explanation of their operation, control DMA Channel O.
please refer to the chapter, "Hardware Description of
the 8051 and 8052" that is found in the Embedded DCONI - (93H) Same as DCONO except this is for
Controller Handbook. An overview of the new SFRs is DMA Channel 1.
found in Section 2.2.1.1, with a detailed explanation in
Section 3.7 and Section 4.5. GMOD - (84H) Contains the Protocol bit (PR). the
Preamble Length (PLI.O), CRC Type (CT). Address
Length (AL). Mode select (Ml.0), and External Trans-
2.1.1.1 New SFRs mit Clock (TXC). This register is used for GSC opera-
The following descriptions are quick overviews of the tion only.
new SFRs, and not intended to give a complete under- IENI - (OC8H) Interrupt enable register for DMA and
standing of their use. The reader should refer to the GSC interrupts. .
detailed explanation in Section 3 for the GSC SFRs,
and Section 4'for the DMA SFRs. IFS - (OA4H) Determines the number of bit times sepa-
rating transmitted frames.
ADR 0,1,2,3 - (95H, OA5H, OBSH, OCSH) Contains
the four bytes for address matching during GSC opera- IPNI - (OF8H) Interrupt priority register for DMA
tion. and GSC interrupts.
AMSKO - (OD5H) Selects "don't care" bits to be used MYSLOT - (OFSH) Contains the Jamming mode bit
with ADRO. (DCJ). the Deterministic Collision Resolution Algo-
rithm bit (DCR). and the DCR slot address for the
AMSKI - (OESH) Selects "don't care" bits to be used GSC.
with ADRI.
P4 - (OCOH) Contains the memory "image" of Port 4.
BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will PRBS - (OE4H) Contains a pseudo-random number to
equal (fosc)/«BAUD + I) X 8). be used in CSMA/CD backoff algorithms. May be read
or written to by user software.
BCRLO - (OE2H) Contains the low byte of a count-
down counter that determines when the DMA access RFIFO - (F4H) RFIFO is used to access a 3-byte FIFO
for Channel 0 is complete. that contains the receive data from the GSC.
BCRHO - (OE3H) Contains the high byte for count- RSTAT - (OE8H) Contains the Hardware Based Ac·
down counter for Channel O. knowledge Enable bit (HABEN), Global Receive En-
able bit (GREN). Receive FIFO Not Empty bit
BCRLl - (OF2H) Same as BCRLO except for DMA (RFNE). Receive Done bit (RDN). CRC Error bit
Channell. (CRCE). Alignment Error bit (AE), Receiver Colli-
BCRHI - (OF3H) Same as BCRHO except for DMA sion!Abort detect· bit (RCABT), and the Overrun bit
Channell. (OVR). used with both DMA and GSC.
BKOFF - (OC4H) An 8-bit count-down timer used SARLO - (OA2H) Contains the low byte of the source
with the CSMA/CD resolution algorithm. address for DMA transfers.
DARLO - (OC2H) Contains the low byte of the destina- SARHO - (OA3H) Contains the high byte of the source
tion address for DMA Channel O. address for DMA transfers.
DARHO - (OC3H) Contains the high byte of the desti- SARLI - (OB2H) Saine as SARLO but for DMA Chan-.
nation address for DMA Channel O. nell.
DARLI - (OD2H) Same as DARLO except for DMA SARHI - (OB3H) Same as SARHI but for DMA Chan-
Channell. nel I.
DARHI - (OD3H) Same as DARHO except for DMA SLOTTM - (OB4H) Determines the length of the slot
Channell. time in CSMA/CD.
DCONO - (92H) Contains the Destination Address TCDCNT - (OD4H) Contains the number of collisions
Space bit (DAS). Increment Destination Address bit in the current frame if using CSMA/CD GSC.
8-3
inter HARDWARE DESCRIPTION OF THE 83C152
Old(O)/New(N) Name Addr . Function
0 'A OEoH. ACCUMULATOR
N ADRO 095H GSC MATCH ADDRESS 0
N ADR1 OA5H GSC MATCH ADDRESS 1
N ADR2 OB5H GSC MATCH ADDRESS 2
N ADR3 OC5H GSC MATCH ADDRESS 3
N AMSKO OD5H GSC ADDRESS MASK 0
N AMSK1 OE5H GSC ADDRESS MASK 1
0 B OFOH B REGISTER
N BAUD 094H GSC BAUD RATE
N BCRLO OE2H DMA BYTE COUNT 0 (LOW)
N BCAHO OE3H DMA BYTE COUNT 0 (HIGH)
N BCRL1 OF2H DMA BYTE COUNT 1 (LOW)
N BCRH1 OF3H DMA BYTE COUNT 1 (HIGH)
N BKOFF OC4H GSC BACKOFF TIMER
N DARLO OC2H DMA DESTINATION ADDR 0 (LOW)
N DARHO OC3H DMA DESTINATION AD DR 0 (HIGH)
N DARL1 OD2H DMA DESTINATION ADDR 1 (LOW)
N DARH1 OD3H DMA DESTINATION ADDR 1 (HIGH)
N DCONO 092H . DMA CONTROL 0
N DCON1 093H DMA CONTROL 1
0 DPH 083H DATA POINTER (HIGH)
0 DPL 082H DATA POINTER (LOW)
N GMOD 084H GSCMODE
0 IE OA8H INTERRUPT ENABLE REGISTER 0
N IEN1 OC8H INTERRUPT ENABLE REGISTER 1
N IFS OA4H GSC INTER FRAME SPACING
0 IP OB8H INTERRUPT PRIORITY REGISTER 0
N IPN1 OF8H INTERRUPT PRIORITY REGISTER 1
N" MYSLOT OF5H GSC SLOT ADDRESS
0 PO b80H PORTO
0 P1 090H PORT 1
0 P2 OAOH PORT 2
0 P3 bBOH PORTa
N P4 OCOH PORT 4
0 PCON 087H POWER CONTROL
N PRBS ·OE4H GSC PSEUDO-RANDOM SEQUENCE
0 PSW ODOH PROGRAM STATUS WORD
N RFIFO OF4H GSC RECEIVE BUFFER
N RSTAT OE8H RECEIVE STATUS (DMA & GSC)
N SARLO OA2H DMA SOURCE ADDR 0 (LOW)
N SARHO OA3H DMA SOURCE ADDR 0 (HIGH)
N SARL1 OB2H DMA SOURCE AD DR i (LOW;
N SARH1 OB3H DMA SOURCE ADDR 1 (HIGH)
.0 SBUF 099H LOCAL SERIAL CHANNEL (LSC) BUFFER
0 SCON 098H LOCAL SERIAL CHANNEL (LSC) CONTROL
N SLOTTM OB4H GSC SLOT TIME
0 SP 08tH STACK POINTER
N TCDCNT OD4H GSC TRANSMIT COLLISION COUNTER
0 TCON 088H TIMER CONTROL
N TFIFO 085H GSC TRANSMIT BUFFER
0 THO 08CH TIMER 0 (HIGH)
ci TH1 08DH TIMER 1 (HIGH)
0 TLO 08AH TIMER 0 (LOW)
0 TL1 08BH TIMER 1 (LOW)
0 TMOD 089H TIMER MODE
N TSTAT OD8H TRANSMIT STATUS (DMA & GSC)
8-4
inter HARDWARE DESCRIPTION OF THE'S3C152
TFIFO - (85H) TFIFO is used to access a 3-byte FIFO The addresses of-the second 128 bytes of data memory
that contains the transmission data for the GSC. happen to overlap the SFR addresses. The SFRs and
their memory locations are shown in Figure 2.2. This
TSTAT - (OD8H) Contains the DMA Service bit means that. internal data memory spaces have the same
(DMA), Transmit Enable bit (TEN), Transmit FIFO address as the SFR address. However, each type of
Not Full bit (TFNF), Transmit Done bit (TDN), memory is addressed differently. To access data memo-
Transmit Collision Detect bit (TCDT), Underrun bit ry above 80H, indirect addressing or the DMA chan-
(UR), No Acknowledge bit (NOACK), and the Re- nels must be used. To access the SFRs, direct address-
ceive oata Line Idle bit (LNI). This register is used ing is used. When direct addressing is used, the address
with both DMA and GSC. is the source or destination, e.g. MOY A, IOH, moves
the contents of location IOH into the accumulator.
The general purpose flag bits (GFO and GFl) that exist When indirect addressing is used, the address of the
on the 80C51BH are no longer available on the C152. destination or source exists within another register, e.g.
GFO has been renamed GFIEN (GSC Flag Idle En- MOY A, @RO. This instruction moves the contents of
able) and IS used to enable idle fill flags. Also GFI has the memory location addressed by RO into the accumu-
been renamed XRCLK (External Receive Clock En- lator. Directly addressing the locations 80H to OFFH
able) and is used to enable the receiver to be clocked will access the SFRs. Another form of indirect address-
externally. ing is with the use of Stack Poillter Operations. If the
Stack Pointer contains an address and a PUSH or POP
instruction is executed, indirect addressing is actually
2.1.2 DATA MEMORY
used. Directly accessing an unused SFR address will
Internal data memory consists of 256 bytes as shown in give undefined results.
Figure 2.1. The first 128 bytes are addressed exactly
Physically, there are separate SFR memory and data
like an 80C51BH, using direct addressing.
memory spaces allocated on the chip. Since·there are
separate spaces, the SFRs do not diminish the available
data memory space.
rv
OffH OfFH
(0)
OVERLAPPING
MEMORY
ADDRESSES
A(0)
SPECIAL FUNCTION REGISTER
SPACE
oaOH
(0)
02fH
BIT ADDRESSABLE
MEMORY SPACE
020H
01FH .,
REGISTER BANK 3
017H
REGISTER BANK 2
010H
REGISTER BANK 1
007H
REGISTER BANK 0
USER DATA MEMORY SPACE
OOOH .. 270427-1
°NOTE:
User data memory above BOH must be addressed indirectly. Using direct addressing above BOH accesses 'the Special
Function Registers.
Figure 2.1. Data Memory Map
8-5
inter HARDWARE DESCRIPTION OF THE 83C152
External data memory is accessed like an SOC51BH, 2.1.2.1 Bit Addressable Memory
with "MOVX" instructions. Addresses up to 64K may
be accessed when using the Data Pointer (DPTR). The C152 has several memory spaces in which the bits
When accessing external data memory with the DPTR, are directly addressed by their location. The directly
the address appears on Port 0 and 2. When using the addressable bits and their symbolic names are shown in
DPTR, if less, than 64K of external data memory is Figure 2.3A, 2.3B, and 2.3C.
used, the address is emitted on all sixteen pins. This
means that when using the DPTR, the pins of Port 2 Bit addresses 0 to 7FH reside in on-board user data
not used for addresses cannot be used for general pur- RAM in byte addresses 20H to 2FH (see Figure 2.3A).
pose VO. An alternative to using 16-bit addresses with
the DPTR is to use RO or Rl to address the external Bit addresses SOH to.OFFH reside in the SFR memory
data memory. When using the registers to address ex- space, but not every SFR is bit addressable, see Figure
ternal data memory, the address range is limited to 256 2.3B. The addressable bits are scattered throughout the
bytes. However, software manipulation of VO Port 2 SFRs. The addressable bits occur every eighth SFR ad-
pins as normal I/O, allows this 256 bytes restriction to dress starting at SOH and occupy the entire byte. Most
be expanded via bank switching. When using RO or Rl of the bits that are addressable in the SFRs have been
as data pointers, Port 2 pins that'are not used for ad- given symbolic names. These names will often be re-
dressing, can be used as general purpose I/O. ferred to in this or other documentation on the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
names are shown in Figure 2.3C.
1 PGSlE POIIA 1 PGSlV PDllAO PGSRE PGSRV OFBH ADR2 OBSH
'I I I I. 'II I. 'I I I I, 'I I I II. 'I I I I, 'II I II, SLOmA OB4H
MYSLOT DCJ OCR SAS SM SA3 s.u SAl SAO OF5H SARHl OB3H
RFIFO OF4H SARLl OB2H
BCRH 1 OF3H 'I.
'BCRL 1 OF2H (0)P3 RD WR n TO INn INTO TXD RXD OBOH
'//1, 'II. 'III. '1111, 'III, 'II, 'II, 'I, 'I, 'II.
OFOH (0) IE EA ES En EXl ETO EXO OA8H
'I. 'I, 'I, 'II, 'III, 'I, 'I, '//1,
T OVR RCABT) AE CRCE RDN RFNE GREN HABEN OEBH ADRl OASH
'I. 'I. 'I. Irs OA4H
AMSK 1 OESH SARHO OA3H
'I. 'II, 'III, 'II. '1111. 'III. 'III. SARLO OA2H
PRBS OE4H '1111. 'III, '111.'111. '11/.'1111.
BCRHO OOH (0)P2 OAOH
BCRLO OE2H 'I. 'I.
'I. 'I. 'I. SBUF 099H
OEOH (')scaN SMO SMl SM2 REN TB8 RB8 n RI 098H
'I. 'I. ACRO 09SH
LNI NOACK UR TCDT TON TFNF TEN OMA OOSH BAUD 094H
'II. 'II, 'II, 'II, '//11. 'III. 'III, OCONl CAS IDA SAS !SA OM TM DONE GO 093H
AMSKO OOSH OCONO CAS IDA SAS !SA OM TM DONE GO 092H
TCDCNT OD4H 'II. 'III. 'II, 'I,
DARHl OD3H (O)Pl RD5A HLD !<xC Tit: DEiI GTXD GRXD 090H
DARL·I 002H 'II. 'III, 'II, 'i/i. 'ii.
'II, 'I, 'II/I. '11.'1111, 'III, 'I, THl 08DH
ev AC FO RSl RSO OV P ODOH THO 08CH
'II, 'I, 'I. 'II. 'III, 'III, 'I, TLl 08BH
EGSlE EDNAl EGSlV EDMAO EGSRE EGSRV OCBH TLO OSAH
'I. 'I. 'I. TMOD GATE C loll MO GATE ejl loll MO 089H
ADR3 OCSH (')TCON TFl lRl TFO lRO IEl 1T1 lEO ITO 088H
BKOFF DC4H PCON SMOD ARB REQ GAREN XRCLK GFiEN PO IDL 087H
DARHO OC3H 'II, 'II, 'I, '//1,
'I. 'I. 'II.
DARLO OC2H TFlFO 08SH
'I. GlAOD CTCLK loll MO AL CT PLl PLO PR 084H
OCOH DPH 083H
'I. 'I. 'I, 'II, DPL 082H
PS PTl PXl PTO PXO OB8H SP 081H
'IL 'IlL 'I, '1.'1111. 'III. '11/1.'11, (')PO 080H
270427-2
0= BIT ADDRESSABLE
270427-03
Figure 2.2. Special Function Registers
8-6
inter HARDWARE DESCRIPTION OF THE 83C152
Data Memory Map (bits):
Byte BIT ADDRESSES
Address (MSB) (LSB)
020H 07 06 05 04 03 02 01 00
021H OF DE 00 OC OB OA 09 08
022H 17 16 15 14 13 12 11 10
023H 1F 1E 10 1C 1B 1A 19 18
024H 27 26 25 24 23 22 21 20
025H 2F 2E 20 2C 2B 2A 29 28
026H 37 36 35 34' 33 32 31 30
027H 3F 3E 30 3C 3B 3A 39 38
028H 47 46 45 44 43 42 41 40
029H 4F 4E 40 4C 4B 4A 49 48
02AH 57 56 55 54 53 52 51 50
02BH 5F 5E 50 5C 5B 5A 59 58
02CH 67 66 65 64 63 62 61 60
020H 6F 6E 60 6C 6B 6A 69 68
02EH 77 76 75 74 73 72 71 70
02FH 7F 7E 70 7C 7B 7A 79 78
Figure 2.3A. Bit Addresses
Byte BIT ADDRESSES
Address (MSB) (LSB)
080H 87 86 85 84 83 82 81 80 (PO)
088H 8F 8E 80 8C 8B 8A 89 88 (TCON)
090H 97 96 95 94 93 92 91 90 (P1)
098H 9F 9E 90 9C 9B 9A 99 98 (SCON)
OAOH A7 A6 A5 A4 A3 A2 A1 AO (P2)
OA8H AF - - AC AB AA A9 A8 (IE)
OBOH B7 B6 B5 B4 B3 B2 B1 BO (P3)
OB8H - - - BC BB BA B9 B8 (IP)
OCOH C7 C6 C5 C4 C3 C2 C1 CO (P4)
OC8H - - CO CC CB CA C9 C8 (IEN1)
OOOH 07 06 05 04 03 02 01 00 (PSW)
008H OF OE 00 OC OB OA 09 08 (TSTAT)
OEOH E7 E6 E5 E4 E3 E2 E1 EO (A)
OE8H EF EE EO EC EB EA E9 E8 (RSTAT)
OFOH F7 F6 F5 F4 F3 F2 F1 FO (B)
OF8H - - FO FC FB FA F9 F8 (IPN1)
Figure 2.3B. Bit Addresses
8-7
HARDWARE DESCRIPTION OF THE 83C152
Byte SYMBOLIC NAME BIT MAP
Address (MSB) (LSB)
080H PO.7 PO.6 PO.S PO.4 PO.S PO.2 PO.1 PO.O (PO)
088H TF1 TR1 TFO TRO IE1 1T1 lEO ITO (TCON)
090H P1.7 P1.6 P1.S P1.4 P1.S P1.2 P1.1 P1.0 (P1)
098H SMO SM1 SM2 REN TB8 RB8 TI RI (SCON)
OAOH P2.7 P2.6 P2.S P2.4 P2.S P2.2 P2.1 P2.0 (P2)
OA8H EA - - ES ET1 EX1 ETO EXO (IE)
OBOH PS.7 PS.6 PS.S PS.4 PS.S PS.2 PS.1 PS.O (PS)
OB8H - - - PS PT1 PX1 PTO PXO (IP)
OCOH P4.7 P4.6 P4.S P4.4 P4.S P4.2 P4.1 P4.0 (P4)
OC8H - - EGSTE EOMA1 EGSTV EOMAO EGSRE EGSRV (IEN1)
OOOH CY AC FO RS1 RSO· ·OV - P (PSW)
008H LNI NOACK UR TCOT TON TFNF TEN OMA (TSTAT)
OEOH (A)
OE8H OVR RCABT AE CRCE RON RFNE GREN HABEN (RSTAT)
OFOH (B)
OF8H - - PGSTE POMA1 PGSTV POMAO PGSRE PGSRV (IPN1)
Figure 2.3C. Bit Addresses
2.1.3 PROGRAM MEMORY
The 83C152 contains 8K of ROM program memory, , . . . . - - - - - - . , FFFFH
and the 80C152 uses only external program memory.
Figure 2.4 shows the program memory locations and
where they reside. The user is allowed a maximum of EXTERNAL
64K of program memory. In the 83C152 program
memory fetches beyond 8K automatically access exter-
nal program memory. When program memory is exter-
nally addressed, all of the Port 2 pins emit the address.
Since all of Port 2 is affected by the address, unused
address pins cannot be used as normal I/O ports even if
less than 64K. of memory is being accessed.
1--------I1FFFH'
EXTERNAL IF U; =0
INTERNAL IF EA =1
' - - - - - - - - " ' OOOOH
270427·4
Figure 2.4. Program Memory
8-8
inter HARDWARE DESCRIPTION OF THE 83C152
2.2 Interrupt Structure added SFRs are IENI (CSH) for enabling the inter-
rupts and IPNI (FSH) for setting the priority. For an
The CI52 retains all five interrupts of the SOC5IBH. In explanation on how the priority of interrupts affects
addition, six new interrupts have been added for a total their operation please refer to the MCS-51 Architecture
of II available interrupts. Two SFRs have been added and Hardware Chapters in the Intel Embedded Con-
to the CI52 for control of the new interrupts. These troller Handbook.
IEN1 FUNCTIONS
Symbol Position Vector Function
- IEN1.7 RESERVED and do not exist on Chip.
- IEN1.6 RESERVED and do not exist on chip.
EGSTE IEN1.5 04BH GSC TRANSMIT ERROR-If TSTAT.O (DMA) is cleared, the
interrupt service routine at 4BH is invoked when TSTAT.6
(NOACK) or TSTAT.4 (TCDT) is set and EGSTE is enabled. If
TSTAT.O (DMA) is set, the interrupt service routine will be
invoked when the TSTAT.5 (UR) is set and EGSTE.is enabled.
EDMA1 IEN1A 053H DMA CHANNEL REQUEST 1-The interrupt service routine
at53H is invoked when DCON1.1 (DONE) is set and EDMA 1 is
enabled.
EGSTV IEN1.3 043H GSC TRANSMIT VALID-If TSTAT.O (DMA) is cleared, the
interrupt service routine at 43H is invoked when TSTAT.2
(TFNF) is set and EGSTV is enabled. If TSTAT.O (DMA) is set,
the interrupt service routine will be invoked when TSTAT.3
(TDN) is set and EGSTV is enabled.
EDMAO IEN1.2 03BH DMA CHANNEL REQUEST ~The interrupt service routine
at 3BH will be invoked when DCONO.1 (DONE) is set and
EDMAO is enabled.
EGSRE IEN1.1 033H GSC RECEIVE ERROR-The interrupt service routine at 33H
will be invoked when RSTATA (CRCE), RSTAT.7 (OVR),
RSTAT.6 (RCABT), or RSTAT.5 (AE), is set and EGSRE is
enabled. This functions the same whether or not TSTAT.O
(DMA) is set.
EGSRV IEN1.0 02BH GSC RECEIVE VALID-If TSTAT.O (DMA) is cleared, the
interrupt service routine at 2BH will be invoked when RSTAT.2
(RFNE) is set and EGSRV is enabled. If TSTAT.O (DMA) is
set, the interrupt service routine will be invoked when
RSTAT.3 (RDN) is set and EGSRV is enabled.
IPNI is used the same way the current SOC5IBH interrupt priority register (IP) is. By assigning a "I" to the
appropriate bit, that interrupt has a higher priority than an interrupt with a "0" assigned to it in the priority register.
The new interrupt priority register (IPNI) contents are:
Symbol Position Function
PGSTE IPN1.5 GSC TRANSMIT ERROR
PDMA1 IPN1.4 DMA CHANNEL REQUEST 1
PGSTV IPN1.3 GSC TRANSMIT VALID
PDMAO IPN1.2 DMA CHANNEL REQUEST 0
PGSRE IPN1.1 GSC RECEIVE ERROR
PGSRV IPN1.0 GSC RECEIVE VALID
8-9
intJ HARDWARE DESCRIPTION OF THE 83C152
The eleven interrupts are sampled in the following order when assigned the same priority level in the IP and IPNI
registers:
Priority Priority Interrupt Interrupt
Priority Symbolic Symbolic Symbolic Symbolic Vector
Sequence Address Name Address Name Address
1 IP.O PXO lE.O EXO 03hi (FIRST)
2 IPN1.0 PGSRV IEN1.0 EGSRV 2BH
3 IP.1 PTO 1E.1 ETO OBH
4 IPN1.1 PGSRE IEN1.1 EGSRE 33H
5 IPN1.2 PDMAO IEN1.2 EDMAO 3BH
6 IP.2 PX1 IE.2 EX1 13H
7 IPN1.3 PGSTV IEN1.3 EGSTV 43H
8 IPN1.4 PDMA1 IEN1.4 EDMA1 53H
9 IP.3 PT1 1E.3 ET1 1BH
10 IPN1.5 PGSTE IEN1.5 EGSTE 4BH
11 IP.4 PS IE.4 ES 23H (LAST)
2.3 Reset
RESET performs the same operations in both the 80C5lBH and the Cl52 and those conditions that exist at the end
of a valid RESET are:
Register Contents Register Contents
ACC OOH PO-P4 OFFH
ADRO-3 OOH PCON OXXXOOOOB
AMSKO OOH PRBS bOH
AMSK1 OOH PSW OOH
B OOH RFIFO INDETERMINATE
BAUD OOH RSTAT OOOOOOOOB
BCRHO INDETERMINATE SARHO INDETERMINATE
BCRH1 INDETERMINATE SARH1 INDETERMINATE
BCRLO INDETERMINATE SARLO INDETERMINATE
CRL1 INDETERMINATE SARL1 INDETERMINATE
BKOFF INDETERMINATE SBUF INDETERMINATE
DARHO INDETERMINATE SCON OOH
DARH1 INDETERMINATE SLOTTM OOH
DARLO INDETERMINATE SP 07H
DARL1 INDETERMINATE TCDCNT INDETERMINATE
DCONO OOH TCON / OOH
DCON1 OOH TFIFO INDETERMINATE
DPTR OOOOH THO OOH
GMOD XOOOOOOOB TH1 OOH
IE OXXOOOOOB TLO OOH
IEN1 XXOOOOOOB TL1 OOH
IFS OOH TMOb OOH
IP XXXOOOOOB TSTAT XXOO0100B
IPN1 XXOOOOOOB PC OOOOH
MYSLOT OOOOOOOOB
8-10
HARDWARE DESCRIPTION OF THE 83C152
The same conditions apply for both the 80C5lBH and 2.6 Package
C152 for a correct reset pulse or "power-on" reset ex-
cept that Reset is active low on the C152. Please refer
to the 8051/52 Hardware Description Chapter of the
a
The 83Cl52 is packaged in 48 pin DIP and a 68 lead
PLCC. This differs from the 40 pin DIP and 44 pin
Intel Embedded Controller Handbook for an explana- PLCC of the 80C51BH. The larger package is required
tion on how to provide a proper power-on reset. Since to accommodate the extra 8 bit I/O port (P4). Figure
Reset is active low on the C152, the resistor should be 2.5A and 2.5B show the packages and the pin names.
tied to VCC and the capacitor should be tied to VSS.
Because the clocking on part of the GSC circuitry is
independent of the processor clock, data may still be (GRXD) P1.0 vcc
transmitted and DEN active for some time after reset is
(GTXD) Pl.l P4.0
applied. The transmission may continue for a maxi-
mum of four machine cycles after reset is first pulled (DEN) Pl.2 P4.l
low. Although Reset has to be held low for only three (TXC) P1.3 P4.2
machine cycles to be recognized by the GSC hardware, (RXC) P1.4 P4.3
all of the GSC circuitry may not be reset until four (HLD) Pl.S P4.4
machine cycles have passed. If it is important in the
(HLDA) Pl.6 P4.S
user application· that all transmission and DEN be-
comes inactive at the end of a reset, then Reset will Pl.7 P4.6
have to be held low for a minimum of four machine RESET P4.7
cycles. (RXD) P3.0 EA
(TXD) P3.l ALE
(INTO) P3.2 PSEN
2.4 Port 4
(INn) P3.3 P2.7 (A1S)
I
Port 4 operation is identical to Ports 1-3 on the (TO) P3.4 P2.6 (A14)
80C51BH. The description of port operation can be (n) P3.S P2.S (A13)
found in the 8051/52 Hardware Description Chapter of (WR) P3.6 P2.4 (A12)
the Intel Embedded Controller Handbook.
(RO) P3.7 P2.3 (All)
(A/DO) PO.O P2.2 (Al0)
2.5 Timer/Counters (A/DO PO.l P2.l (A9)
(A/D2) PO.2 P2.0 (AB)
The 80C51BH and C152 have the same pair of 16-bit
(A/D3) PO.3 PO.7 (A/D7)
general purpose timer/counters. The user should refer
to the Intel Embedded Controller Handbook which de- XTAL2 PO.6 (A/D6)
scribes the timerlcounters and their use. The user XTALl PO.S (A/DS)
should bear in mind, when reading the Intel Embedded Vss PO.4 (A/D4)
Controller Handbook that the Cl52 does not have the
third event timer named Timer 2, which is in the 8052. 270427-5
Figure 2.SA. DIP Pin Out·
8-11
inter HARDWARE DESCRIPTION OFTHE'83C152
INDEX
CORNER'\..
"l "': "'! OJ "!
Ii: Ii: Ii: Ii: Ii: Ii: >'"
g~ c..i <i
'" > z Z z
<i
Z
. :;; . ... ....
0
0. 0.
N
0.
"'!
0. 0.
Pl.6 10 P4.S
Pl.7 11 P4.6
N.C. 12 P4.7
13 N.C.
P3.0 14 EA
P3.1 15 ALE
P3.2 16 PSEN
N.C. 17 N.C.
80C152
P3.3 18 83C152 N.C.
P3.4 19 N.C.
N.C. N.C.
N.C. N.C.
N.C. P2.7
P3.5 P2.6
P3.6 P2.5
P3.7 P2.4
N.C. P2.3
"! N
'" N ~
'""' ...0 . on
'" ...
c..i c..i c..i 0 N
Z ,z Z oi
..J ..J
0 ci ci ci > ci Q.
ci ci oi Q.
oi
Q. Q. Q. Q. ~ ~ Q. 0. Q. Q. Q.
X x
270427-6
Figure 2.58. PLCCPin Out.
2.7 Pin Desc.ription
The pin description for the 80C5lBH also applies to the C152 and is listed below. Changes have been made to the
. descriptions as they apply to the C152.
PIN DESCRIPTION
Pin
Description
Name
VSS Circuit ground potential.
VCC Supply voltage during normal, Idle, and Power down operation.' Nominally + 5V
...L 04nOI
.L lV-tO.
XTAL1 Input to the inverting oscillator amplifier. Also serves as the input for using an
external Clock signal.
XTAL2 Output from the oscillator amplifier.
PORTO ' Port 0 is an 8-bit open drain bi-directional 1/0 port. Port 0 pins that have 1s written to
them float and in that state can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external Program
and Data Memory: In this application it uses strong internal pullups when emitting
1s. Port 0 also outputs the code bytes during program verification in the 83C152.
External pullups are required during program verification.
PORT 1 Port 1 is an 8-bit bi-directionall/O port with internal pullups. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current because of the internal pull ups. Port 1 also has the following special
functions and for the special functions to operate a "1" has to be written to that pin
first.
8-12
inter HARDWARE DESCRIPTION OF THE 83C152
2.7 PIN DESCRIPTION (Continued)
Pin
Description
Name
Port Alternate Function
1.0 GSC receiver data input (GR x D)
1.1 GSC transmitter data output (GT x D)
1.2 Drive Enable to enable external drivers (DEN)
1.3 GSC external transmit clock input (T x C)
1.4 GSC external receive clock input (Rx C)
1.5 DMA hold request 1/0 (HOlD_)_
1.6 DMA hold acknowledge I/O (HlDA)
1.7 none
PORT 2 Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 2 pins that are externally being pulled low will source
current because of the internal pull ups. Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong
internal pullups when emitting 1s and cannot be used as inputs. During accesses to
external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 SFR. Port 2 receives the high-order address bits during program
verification of the ROM device.
PORT 3 Port 3 is an 8-bit bi-directionall/O port with internal pull ups. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the pull ups. Port 3 also has the following special functions and for the
special functions to operate that pin must be programmed to a "1" first.
Port Alternate Function
3.0 RXD (lSC serial data input port) I
3.1 TXD (lSC serial data output port)
3.2 INTO (external interrupt 0)
3.3 INT1 (external interrupt 1)
3.4 TO (Timer 0 external input)
3.5 I!JTimer 1 external input)
3.6 WR (external data memory write strobe)
3.7 RD (external data memory read strobe)
PORT 4 Port 4 is an 8-bit bi-directionall/O port with 40 internal pullups. Port 4 pins that have
1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 4 pins that are externally pulled-low will source
current because of the pullups. Port 4 also receives the low-order address bytes
during program verification in the 83C152.
RESET Reset input. A low level on this pin for two machine cycles while the oscillator is
running resets the device. An internal diffused resistor to VCC permits Power-On
reset using only an external capacitor to VSS. .
EA External Access enable. EA must be externally held low in order to enable the
device to fetch code from external Program Memory locations OOOOH to 1FFFH.
ALE Address latch Enable output pulse for latching the low byte of the address during
accesses to external memory. In normal operation ALE is emitted at a constant rate
of % the oscillator frequency, and may be used for external timing or clocking
purposes. Note, however, that one ALE pulse is skieP.ed during each access to
external Data Memory. (Including DMAs where no RD/WR generated for internal
source/destination.)
PSEN Program Store Enable is the read strobe to external Program Memory. When the
C152 is executing code from external Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each
access to external Data Memory.
8-13
intJ HARDWARE DESCRIPTION OF THE 83C152
2.8 Power Down and Idle 2.9 Local Serial Channel
Both of these operations function identically as in the The Local Serial Channel (LSC) is the name given to
80C51BH. Application Note 252, "Designing with the the UART that exists on all MCS-51 devices. The
80C5IBH" gives an excellent explanation on the use of LSC's function and operation is exactly the same as on
the reduced power consumption .modes. Some of the the 80C51BH. For a description on the use of the LSC,
items not covered in AP-252 are the considerations that refer to the 8051/52 Hardware Description Chapter in
are applicable when using the GSC or DMA· in con- the Intel Embedded Controller Handbook, under Serial
junction with the power saving modes. Interface.
The GSC continues to operate normally in Idl~ as long
as the interrupts are enabled. The interrupts need to be 3.0 GLOBAL SERIAL CHANNEL
enabled, so that the CPU can service the FIFO's and
terminate transmission or reception when appropriate.
After servicing the. GSC, user software. will need to 3.1 Introduction
again invoke the Idle command as the CPU does not
automatically re-enter the Idle mode after servicing the The Global Serial Channel (GSC) is a multi-protocol,
interrupts. high performance serial interface targeted for data rates
up to 2 MBPS with on-chip clock recovery, and 2.4
The GSC does not operate while in Power Down so the MBPS using the external clock options. In applications
steps required prior to entering Power Down become using the serial channel, the GSC implements the Data
more complicated. The sequence when entering Power Link Layer and Physical Link Layer as described in the
Down and the status of the I/O is of major importance ISO reference model for open systems interconnection.
in preventing damage to the C152 or other components
in the system. Since the only way to exit Power Down The GSC is designed to meet the requirements of a
is with a Reset, several problem areas become very sig- wide range of serial communications applications and is
nificant. Some of the problems that merit careful con- optimized to implement Carrier-Sense Multi-Access
sideration are cases where the Power Down occurs dur- with Collision Detection (CSMA/CD) and Synchro-
ing the middle of a transmission; and the possibility nous Data Link Control (SDLC) protocols. The GSC
that other stations are not or cannot enter this same architecture is also designed to provide flexibility in de-
mode. The state of the GSC I/O pins becomes critical fining non-standard protocols. This provides the ability
and the GSC status will need to be saved before power . to retrofit new products into older serial technologies,
down is entered. There will also need to be some meth- as well as the development of proprietary interconnect
od of identifying to the CPU that the following Reset is schemes for serial backplane environments.
probably not a cold start and that other stations on the
link may have already been initialized. The versatility of the GSC is demonstrated by the wide
range of choices available to the user. The various
The DMA circuitry stops operation in both Idle and modes of operation are summarized in Table 3.1. In
Power Down modes. Since operation is stopped' in both subsequent sections, each available choice of operation
modes, the process should be similar in each case. Spe- will be explained in detail.
cific steps that need to be taken include: notification to
other devices that DMA operation is about to cease for In using Table 3.1, the parameters listed vertically (on
a particular station or network, proper withdrawal the left hand side) represent an option that is selected
from DMA operation, and saving the status' of the (X). The parameters listed horizontally (along the top
DMA channels. Again, the status of the I/O pins dur- of the table) are all the parameters that could. theoreti-
ing Power Down needs careful consideration to avoid cally be selected (Y). The symbol at the junction of
damage to the C152 or other components. both X and Y determines the applicability of the option
Y.
Port 4 returns to its input state, which is high level
using weak pullup devices. Note, that not all combinations are backwards compati~
ble. For example, Manchester encoding requires half
duplex, but half duplex does not .require Manchester
encoding.
8-14
HARDWARE DESCRIPTION OF THE 83C152
Table 3.1
ADDRESS
DATA DU· ACKNOW- RECOG- PRE-
ENCODING FLAGS CRC PLEX LEDGE NITION BACKOFF AMBLE
M N N 0 1 N 1 3 H F N H U N 8' 1 N A D N 8
A R R 1 1 0 6 2 A U 0 A S 0 B 6 0 L E 0 B
N=NOT AVAILABLE N Z Z 1 / N B B L L N R E N I B R T T N I
M=MANDATORV C I 1 I E I I F L E D R E T I M E E E T
O=OPTIONAL H 1 D T T W D / T A R R
P = NORMALLV PREFERRED E 1 L C A A E A L N M
X=N/A S 1 E C U R F L A I
T 0 I T E I L T N
E T 0 N E I
R E S
D T
I
C
DATA ENCODING:
MANCHESTER(CSMA/CD) X N N 1 P 1 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
NRZI (SDLC) N X N P 1 1 0 0 0 0 0 N P 0 0 0 N N N 0 0
'. NRZ (EXT CLK) N N X 0 0 1 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0
FLAGS:Ollllll0 (SDLC) N P 0 X 1 1 0 0 0 0 0 N P 0 0 0 N N N 0 0
11/IDLE P N 0 1 X 1 0 0 0 N 0 0 0 0 0 0 0 0 0 1 0
CRC:NONE 1 1 1 1 1 X N N 1 N 1 1 1 1 1 1 N N N 1 1
l6-BITCCITI 0 0 0 0 0 N X N 0 0 0 0 0 0 0 0 0 0 0 0 0
32-BIT AUTODIN II 0 0 0 0 0 N N X 0 N 0 0 0 0 0 0 0 0 0 0 0
DUPLEX:HALF 0 0 0 0 0 1 0 0 X N 0 0 0 0 0 0 0 0 0 0 0
FULL N 0 0 M N N M N N X 0 N P 0 0 0 N N N 0 0
ACKNOWLEDGEMENT:NONE 0 0 0 0 0 1 0 0 0 0 X N N 0 0 0 0 0 0 0 0
HARDWARE 0 N N N 0 1 0 0 0 N N X N 0 0 0 N 0 0 N 0
USER DEFINED 0 P 0 0 0 1 0 0 0 P N N X 0 0 0 0 0 0 0 0
ADDRESS RECOGNITION:
NONE/ALL 0 0 0 0 0 1 0 0 0 0 0 0 0 X N N 0 0 0 0 0
8-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 N X N 0 0 0 0 0
l6-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 N N X 0 0 0 0 0
COLLISION RESOLUTION:
NORMAL \
0 N 0 N 0 N 0 0 M N 0 N 0 0 0 0 X N N N 0
ALTERNATE O' N 0 N 0 N 0 0 M N 0 0 0 0 0 0 N X N N 0
DETERMINISTIC 0 N 0 N 0 N 0 0 M N 0 0 0 0 0 0 N N X N 0
PREAMBLE:NONE N 0 0 0 1 1 0 0 0 0 0 N 0 0 0 0 N N N X N
8-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N X
32-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N N
64-BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 N N
JAM:D.C. M N N N 0 N 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
CRC M N N N 0 N 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
CLOCKING:EXTERNAL N M .N 0 0 N 0 0 0 0 0 N 0 0 0 0 N N N 0 0
INTERNAL 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CONTROL: CPU 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAW RECEIVE: 1 1 1 1 1 1 1 1 1 N 1 1 1 1 1 1 0 0 0 1 1
RAW TRANSMIT: 1 1 1 1 1 1 1 1 1 N 1 1 1 1 1 1 N N N 1 1
CSMAlCD: 0 N 2 1 P 1 0 0 M N 0 0 0 0 0 0 0 0 0 N 0
SDLC: N 0 0 P 1 1 0 0 0 0 0 N 0 0 0 0 N N N P 0
8-15
HARDWARE DESCRIPTION OF THE 83C152
Table 3.1 (Continued)
PRE·
AMBLE JAM CLOCK CONTROL
3 6 D C E I C D R R C 5
2 4 C R X N P M A A 5 D
N= NOT AVAILABLE B B C T T U A W W M L
M=MANDATORY I I I E E R T A C
0= OPTIONAL T T R R E R I
P= NORMALLY PREFERRED N N C A C
X=N/A A A E N D
L L I S
V M
E I
T
DATA ENCODING:
MANCHESTER 0 0 0 0 N M 0 0 0 0 M N
NRZI 0 0 N N N M 0 0 0 0 N M
NRZ 0 0 0 0 M N 0 0 0 0 0 0
FLAGS:01111110 0 0 N N 0 0 0 0 0 1 1 P
1111DLE 0 0 0 0 0 0 0 0 0 1 P 1
CRC:NONE 1 1 N N 1 1 1 1 1 1 1 1
16·BIT CCITT 0 0 -0 0 0 0 0 0 1 1 0 0
32·BIT AUTODIN " 0 O. 0 0 0 0 0 0 1 1 0 0
DUPLEX:HALF 0 0 0 0 0 0 0 0 0 0 0 0
FULL 0 0 N N 0 0 0 0 N N N P
ACKNOWLEDGEMENT:NONE 0 0 0 0 0 0 0 0 0 0 0 0
HARDWARE 0 0 0 0 N 0 0 0 N N 0 N
USER DEFINED 0 0 0 0 0 0 0 0 0 0 0 1
ADDRESS RECOGNITION:
NONE 0 0 0 _0 0 0 0 0 0 0 0 0
8·BIT 0 0 .0 0 0 0 0 0 1 1 0 0
16·BIT 0 0 0 0 0 0 0 0 1 1 0 0
COLLISION RESOLUTION:
NORMAL 0 0 0 0 N 0 0 0 0 N M N
ALTERNATE 0 0 0 0 N 0 0 ,0 0 N M N
DETERMINISTIC O. 0 0 0 N 0 0 0 0 N M N
PREAMBLE:NONE N N N N 0 0 0 0 0 0 N P
8·BiT N N 0 0 0 0 0 0 1 1 0 0
32·BIT X N 0 0 0 0 0 0 1 1 0 0
64·BIT N X 0 0 0 0 0 0 1 1 0 0
JAM:D.C. 0 0 X N 2 0 0 0 0 N M N
CRC 0 0 N X 2 0 0 0 0 N M N
CLOCKING:EXTERNAL 0 0 N N X N 0 0 0 0 2 0
INTERNAL 0 0 0 0 N X 0 0 0 0 0 0
CONTROL:CPU 0 0 0 0 0 0 X N 0 0 0 0
DMA 0 0 (j 0 0 0 N X 0 0 0 0
RAW RECEIVE: 1 1 0 0 1 ' 1 1 1 X N 1 1
RAW TRANSMIT: 1 1 N N 1 1 1 1 N X 1 1
CSMAlCD: 0 0 0 0 2 0 0 0 0 0 X N
SDLC: 0 0 N N 0 0 0 0 0 0 N X
8·16
HARDWARE DESCRIPTION OF THE 83C152
Note 1: Programmable in Raw transmit or receive of collision resolution made available to the user on the
mode. C152. Re-transmission is attempted when a resolution
algorithm indicates that a station's opportunity has ar-
Note 2: When CSMA/CD is enabled, an external clock rived.
can be used on the transmitter, but not the receiver.
Since the receiver monitors the link for Manchester vio- Normally, in CSMA/CD, re-transmission slot assign-
lations, external hardware would be required to refor- ments are intended to be random. This method gives all
mat the data from NRZ to Manchester on the transmit- stations an equal opportunity to utilize the serial com-
ter. These hardware requirements go beyond the expec- munication link but also leaves the possibility of anoth-
tations of this table for implementation. For that reason er collision due to two stations having the same slot
it was assumed that the external clock cannot be used assignment. There is an option on the C152 which al-
at all with CSMA/CD protocol, although it is actually lows all the stations to have their slot assignments pre-
possible to do so. viously determined by user software. This pre-assign-
ment of slots is called the deterministic resolution
Almost all the options available from Table 3.1 can be mode. This method allows resolution after the first col-
implemented with the proper software to perform the lision and ensures the access of the link to each station
functions that are necessary for the options selected. In during the resolution. Deterministic resolution can be
Table 3.1, a judgment has been made by the authors on advantageous when the link is being heavily used and
which options are practical and which are not. What collisions are frequently occurring and in real time ap-
this means is that in Table 3.1, an UN" should be inter- plications where determinism is required. Deterministic
preted as meaning that the option is either not practical resolution may also be desirable if it is known before-
when implemented with user software or that it cannot hand that a certain station's communication needs to be
be done. An "0" is used when that function is one of prioritized over those of other stations if it is involved
several that can be implemented with the GSC without in a collision.
additional user software.
The GSC is targeted to operate at bit rates up to 2.4 3.2.2 CSMAlCD FRAME FORMAT
MBps using the external clock options and up to 2 The frame format in CSMA/CD consists of a pream-
MBps using the internal baud rate generator, internal ble, Beginning of Frame flag (BOF), address field, in-
data formatting and on-chip clock recovery. The baud formation field, CRC, and End of Frame flag (EOF) as
rate generator allows most standard rates to be shown in Figure 3.1.
achieved. These standards include the proposed
IEEE802.3 LAN standard (1.0MBps) and the T1 stan-
dard (1.544MBps). The baud rate is derived from the IPREAMBLE IBOF IADDRESS IINFO ICRC IEOF I
crystal frequency. This makes crystal selection impor- Figure 3.1 Typical CSMA/CD Frame
tant when determining the frequency and accuracy of
the baud rate. PREAMBLE - The preamble is a series of alternating
Is and Os. The length of the preamble is programmable
to be 0, 8, 32, or 64 bits. The purpose of the preamble is
3.2 CSMA/CD Operation to allow all the receivers to synchronize to the same
clock edges and identifies to the other stations on-line
3.2.1 CSMA/CD OVERVIEW that there is activity indicating the link is being used.
For these reasons zero preamble length is not compati-
CSMA/CD operates by sensing the transmission line ble with standard CSMAlCD, protocols. When using
for a carrier, which indicates link activity. At the end of CSMAlCD, the BOF is considered part of the pream-
link activity, a station must wait a period of time, called ble compared to SDLC, where the BOF is not part of
the deference period, before transmission may begin. the preamble. This means that if zero preamble length
The deference period is also known as the interframe were to be used in CSMA/CD mode, no BOF would be
space. The interframe space is explained in Section generated. It is strongly recommended that zero pream-
3.2.3. ble length never be used in CSMA/CD mode. If the
preamble contains two consecutive Os, the preamble is
With this type of operation, there is always the possibil- considered invalid. If the C152 detects an invalid pre-
ity of a collision occurring after the deference period amble, the frame is ignored.
due to line delays. If a collision is detected after trans-
mission is started, a jamming mechanism is used to en- BOF - In CSMA/CD the Beginning-Of-Frame is a part
sure that all stations monitoring the line are awar,e of of the preamble and consists of two sequential Is. The
the collision. A resolution algorithm is then executed to purpose of the BOF is to identify the end of the pream-
resolve the contention. There are three different modes ble and indicate to the receiver(s) that the address will
immediately follow.
8-17
HARDWARE DESCRIPTION OF THE 83C152
ADDRESS - The address field is used to identify which algorithm can be used but IEEE 802.3 uses a 32-bit
messages are iIi.tended for which stations. The user CRC. The generation polynomial the CI52 uses with
must assign addresses to each destination and source. the 32-bit CRC is:
How the addresses are assigned, how they are main- G(X) = X32 + X26 + X23 + X22 +X16 + XI2 +
tained, and how each transmitter is made aware of , . XII + XIO + X8 + X7 + X5 + X4 + X2
which addresses are available is an issue that is left to .+ X + I
the user. Some suggestions are discussed in Section
3.5.5. Generally, each address is unique to each station The CRC generator, as shown in Figure 3.2, operates
but there are special cases where this is not true. In , by taking each bit as it is received and XOR'ing it with
these special cases, a message is intended for more than bit 31 of the current eRC. This result is then placed in
one station. These multi-targeted messages are called temporary storage. The result of XOR'ing bit 31 with
broadcast or multicast-group addresses. A broadcast the received bit is then XOR'd with bits 0, I, 3, 4, 6, 7,
address consisting of all Is will always be received by 9, 10, 11, 15,21,22,25 as the CRC is shifted right one
all stations. A multicast-group address usually is indi- position. When the CRC is shifted right, the temporary
cated by using a las the first address bit. The user can storage space holding the result of XOR'ing bit 31 and
choose to mask off all or selective bits of the address so the incoming bit is shifted into position O. The whole
that the GSC receives all messages or multicast-group process is then repeated with the next incoming or out-
messages. The address length is programmable to be 8 going bit. .
or 16 bits. An address consisting of all Is will always be
received by the GSC on the C152. The address bits are The usei' has no access to the CRC generator or the bits
always passed from the GSC to the CPU. With user which constitute the CRC while in CSMAlCD. On
software, the address can be extended beyond 16 bits, transmission, the CRC is automatically appended to
but the automatic address recognition will only work the data being sent, and on reception, the CRe bits are
on a maximum of 16 bits. User software will have to not normally loaded into the receive FIFO. Instead,
resolve any remaining address bits. they are automatically stripped. The only indication the
user has for the status of the eRC is a pass/fail flag.
INFO - This is the information field and contains the The pass/fail flag only operates during reception. A
data that one device on the link wishes to transmit to CRC is considered as passing when the the CRC gener-
another device. It can be of any length the user wishes ator has 1100011100000100 11011010 011110IlB as a
but needs to be in multiples of 8 bits. This is because remainder after all of the data, including the CRe
multiples of 8 bits are used to transfer data into or out checksum, from the transmitting station has been cy-
of the GSC FIFOs. The information field is delineated cled through the CRC generator. The preamble, BOF
from the rest of the components of the frame by the and EOF are not included as part of the CRC algo-
preceding address field and the following CRC.. The rithm. An interrupt is available that will interrupt the
receiver determines the position of the end of the infor- CPU if the CRC of the receiver is invalid. The user can
mation field by passing the bytes through a temporary enaole the CRC to be passed to the CPU by placing the
storage space. When the EOF is received the bytes in receiver in the raw receive mode.
temporary storage are the CRC, and the last bit re-
ceived previous to the CRC constitute the end of the This method of calculating the CRC is compatible with
information field. IEEE 802.3.
CRC - The Cyclic Redundancy Check (CRC) is an er- EOF - The End Of Frame indicates when the transmis-
ror checking algorithm commonly used in serial com- ,ion i, comnleted. The end flag in CSMA/CD consists
municationS. The CI52 offers two types of CRC algo- ~i an idle c~ndition. An idle c;ndition is assumed when
rithms, a 16-bit and a 32-bit. The 16-bit algorithm is there is no transitions and the link remains high for 2 or
normally ~sed in the SDLC mode and will be described more bit times.
in the SDLC section. In CSMAlCD applications either
8-18
HARDWARE DESCRIPTION OF THE 83C152
270427-8
Figure 3.2. CRC Generator
3.2.3 INTER FRAME SPACE around period is the amount of time that is needed by
user software to complete the handling of a received
The interframe space is the amount of time that trans- frame and be prepared to receive the next frame. An
mission is delayed after the link is sensed as being idle interframe space smaller than the required tum-around
and is used to separate transmitted frames. In alternate period could be used, but would allow some frames to
backoff mode, the interframe space may also be includ- be missed.
ed in the determination of when retransmissions may
actually begin. The C152 allows programmable inter- When a GSC transmitter has a new message to send, it
frame spaces of even numbers of bit times from 2 to will first sense the link. If activity is detected, transmis-
256. sion will be deferred to allow the frame in progress to
complete. When link activity ceases, the station contin-
The period of the interframe space is determined by the ues deferring for one interframe space period.
contents of IFS. IFS is an SFR that is programmable
from 0 to 254. The interframe space is measured in bit As mentioned earlier, the interframe space is used dur-
times. The value in IFS mUltiplied by the bit time ing the collision resolution period as well as during nor-
equals the interframe space unless IFS equals O. If IFS mal transmission. The backoff method selected affects
does equal 0, then the interframe space will equal 256 how the deference period is handled during normal
bit times. One of the considerations when loading the transmission. If normal backoff mode is selected, the
IFS is that only even numbers (LSB must be 0) can be interframe space timer is reset if activity occurs during
used because only the 7 most significant bits are loaded approximately the first half of the interframe space. If
into IFS. The LSB is controlled by the GSC and deter- alternate backoff or. deterministic backoff is selected,
mines which half of the IFS is currently being used. In the timer is not reset. in all cases whe~ the interframe
some modes, the interframe space timer is re-triggered space timer expires, transmission may begin, regardless
if activity is detected during the first half of the period. if there is activity 'on the link or not. Although the
The GSC determines which half of the interframe space C152 resets the interframe space timer if activity is de-
is currently being used by examining the LSB. A one tected during the first one-half of the interframe space,
indicates the first half and zero indicates the second this is not necessarily true of all CSMA/CD systems.
half of the IFS. (IEEE 802.3 recommends that the interframe space be
reset if activity is detected during the first two-thirds or
After reset IFS is 0, which delays the first transmission less of the interframe space.)
for both SDLC and CSMA/CD by 256 bit times (after
reset, a bit time equals 8 oscillator clock periods).
3.2.4 COLLISION RESOLUTION
In most applications, the period of the interframe space The method used to resolve a collision is called the
will be equal to or greater than the amount of time backoff algorithm.
needed to tum-around the' received frame. The turn-
8-19
HARDWARE DESCRIPTION OF THE 83C152
How the backoff algorithm executes is dependent on A collision is assumed if a pulse is less than three sam-
which part of the frame the collision was detected in. ple periods in length or if an. expected transition is
How collisions are detected is shown in Figure 3.3. If missed. Figures 3.3A and B show where transition must
the collision occurred before data has been loaded into occur and where transitions are invalid. The sample
the Receive FIFO, then reception' is simply stopped. . periods occur at a rate that is 8 times the baud rate as
determined by the SFR BAUD.
The time when the first byte is loaded into the Receive
FIFO is dependent on the CRC length. After detection During transmission, each device monitors its own
of the BOF flag, all subsequent data is passed through. transmission pin with its receive circuitry. A collision is
the CRC stripping/generation hardware. Also,there is assumed if the receiver detects Manchester encoding
an additional delay of 8 bit times, as the Receive FIFO violations as defined in Figures 3.3A and B.
operates with only eight bit quantities. This means that
after the BOF, there is a 24(40) bit time delay before Where the collision occurs determines what actions are
data is loaded into the Receive FIFO if the 16(32) bit taken. If the collision occurs after the preamble, the
CRC is selected. If the collision occurs after data has Timer Collision Detect (TCDT) bit is set. If the Enable
been loaded into the receive FIFO, then .the error flag Global Serial Transmit Error (EGSTE) interrupt
Receiver Abort (RCABT) is set and REN cleared. This (lEN 1. 5) is enabled, the CPU is interrupted. If this type
prevents another reception while the CPU tries to fig- of collision occurs, user software must determine what
ure out what to do next. If the Enable Global Serial actions to take for a proper recovery.
(channel) Receive Error (EGSRE) interrupt (IENl.l)
is enabled the CPU is interrupted. At this time user If the transmitting station detects the collision during
software must decide what actions to take to assure a the preamble or BOF, the actions taken are automatic.
proper recovery. The transmitter will attempt resolution up to eight
tries. After the eighth attempt, the error flag (TCDT) is
set. If EGSTE is enabled, the CPU is then interrupted.
LOGICAL o
VALUE
1. o o
MANCHESTER
ENCODING
.
".,. - - - "1" BIT, TIME - - - -.....
".:..'- - "0" BIT TIME - - - -..
"
(8 X BAUD) ,
R.ECEIVt
SAMPLING
RATE
INVALID
MANDATORY TRANSITION
270427-9
Figure 3.3A. CSMA/CD COllisions
8~20
HARDWARE DESCRIPTION OF THE 83C152
LOGICAL o
VALUE
o
MANCHESTER
ENCODING
,,>----
...
.
"1" BIT TIME - - - - - - - - - - "1" BIT TIME - - - -..
"
(8 X BAUD) ,
RECEIVE
SAMPLING'
RATE
INVALID
MANDATORY TRANSITION
OPTIONAL TRANSITION
270427-10
Figure 3.3B. CSMAlCD Collisions
When a transmitting GSC detects a collision, the first algorithm is used. These methods are .named: "Normal
action taken is to apply a jamming signal to the link. Backoff", "Alternate Backoff", and "Deterministic
The jam is sent following the end of the preamble, or Backoff".
immediately if the preamble has already .been complet-
ed. This action is taken to insure that other stations on Before going into detail on the various backoff schemes,
the link are aware that a collision has occurred. there is a parameter called the slot time that must be
understood by the user. The slot time is used during the
The jamming signal can be one of two types, D.C. or collision resolution and is the basic scheduling quantum
CRC. D.C. jam is selected by setting the DCI bit for retransmission once a collision is detected. The slot
(MYSLOT.7). The D.C. jam applies a continuous low time also represents the maximum length of a collision
level signal for a duration equal to the CRC length. To fragment and the upper bound on the acquisition time
select the CRC type of jam, the DCJ bit needs to be of the network. The value of the slot time is determined
cleared. CRC is selected after the C152 is reset. The by the contents of SLOTTM. SLOTTM is programma-
CRC,jam operates by taking the current CRC calculat- ble from b to 255. A slot time is equal to 256-SLOTTM
ed up to that point, inverting the data and applying that multiplied by the bit time,unless SLOTTM equals o. If
signal to the. link. o is used in SLOTTM, th~n the slot time period will
equal 256 bit times.· A bit time is equal to Ilbaud rate.
After applying the jam, the resolution phase is next. The timing requirements on the slot time is that it be
This phase will effect the throughput and efficiency of equal to, or greater than the longest round-trip propa-
the link once a collision is detected. There are three gation time of the signal plus the jam time. The jam
methods to choose from that determine which backoff time is equal to the CRC length.
8-21
intJ HARDWARE DESCRIPTION OF THE 83C152
Normal and Alternate CSMA/CD Modes In alternate mode the backoff time begins immediately
at the end of an interframe space after the jam. If alter-
In the Normal and Alternate Normal resolution modes, nate backoff is used then the slot time does not occur
the slot position assigned .to a station is determined by unin after the interframe space expires as shown in Fig-
the SFR, Pseudo Random Binary Sequence (PRBS). ure 3.4. This mode will usually be used when the inter-
The PRBS generates a random number by using a se- frame space is longer than the slot time. This prevents
ries of feedback shift registers that are clocked by the the situation where the slot time expires before the in-
CPU phase clocks. terframe space period. This preserves the bandwidth of
the collision resolution by insuring that each station is
There is a maximum physical limit of 256 slot positions allowed up to 8 re-attempts at transmission. Networks
available. The slot assigned is derived from PRBS dur- where the slot time is less than the interframe space
ing the resolution phase of a collision. But the value in generally exist where there is a short topology, or high
PRBS is ANDed' with the contents of TCDCNT. The data rates are used.
way TCDCNT operates is that as collisions occur,
TCDCNT shifts left one bit position and a 1 is shifted
into the LSB. As TCDCNT is filled with Is from colli- Deterministic Collision Resolution
sions, the maximum range of slot assignments also in- In Deterministic Collision Resolution, when a collision
creases by powers of 2. This variable upper limit is de- occurs, all stations enter a special mode, whether or not
termined by the number of collisions, but can never be they were involved in the collision. The resolution p~ri
greater than 255. The PRBS maximum value will be od is divided into a programmable number of slots With
(2**n)-I, where n is the number. of pre~?usly a~ each station having a unique slot assignment. The first
tempted transmissions that resulted In a colliSion. This slot starts after one interframe space. A station is al-
means that on the first re-transmission, the PRBS value lowed to start transmitting only during its own slot and
could be 0 or I, on the second re-transmission the will transmit as long as it needs to unless some error
PRBS could be any value from 0 to 3, and on the eighth occurs. After any transmission, one interframe expires
collision PRBS could be any value from 0 to 255. There before the next slot begins. If no collision occurs, the
is no way that the user software can get access to the protocol operates as in regular CSMA/CD mode.
slot position assigned to a station once the backoff pro-
cess has started. This method operates as follows. The user software as-
signs each station its own slot position and loads it in
The backoff can be programmed to start either at the the SFR, MYSLOT. That station has to wait a number
end of the jam, as in Ethernet, or at the end of the of slot times equal to (maximum number of slots) -
interframe space. (MYSLOT). Only the lower six bits of MYSLOT are
used for slot assignment. This means that when using
In normal mode the backoff time begins immediately at
deterministic resolution, a maximum of 63 stations in
the end of the jam. The slot time begins as soon as the . the network can participate in any collision resolution.
jam is completed but must wait until at le~t one int~r Another station may be added to the network, but not
frame space has completed before attemptIng transnus- allowed to participate in a resolution. That station
sion. Slot 0 is the first to occur, followed by Slot 1 and should have 0 as its assigned slot. This prevents the
so on. This means the lowest slot number assigned will station from attempting to retransmit during the colli-
win control of the link as long as the slot time ends sion resolution. When using deterministic resolution,
after the the interframe space expires. In networks the PRBS must be disabled. By writing OFFH into the
where the slot time is longer than the interframe space, PRBS, it is frozen into an all Is st.at.e. The maximum
normal backoff will usually be implemented. This is number of stations that may be involved in the resolu-
because the interframe space time will expire before tion is loaded into TCDCNT. The slot count does not
Slot 0 is complete. This is shown in Figure 3.4. In net- .
begin until the receiver senses that the line is idl~ and
works where the interframe space is longer than the slot
one interframe space expires. At the end of the Inter-
time, Slot 0 will expire before the interframe space and frame space the GSC starts counting the slots. Alter-
will not be able to transmit during that resolution at- nate backoff mode should be selected whenever deter-
tempt. Taken to an extreme where the interframe space ministic backoff mode is being used. Then, if activity is
is much larger than the slot time, it is possible that
detected on the link with deterministic backoff mode
there will be no resolution during the first couple of
selected, the GSC first waits uhtil the link is idle and
collisions because the possible number of slot times then waits until the end of the interframe space before
available will still be less than the interframe space.
the slot timer continues counting the slots. This allows
This would waste the bandwidth of the resolution by another station to transmit a pending message in its
not allowing all stations the opportunity of 8 attempts proper slot and 'each station gets an opportunity to
at retransmission.
transmit when the slot time equals the value in its
MYSLOT register.
8-22
HARDWARE DESCRIPTION OF THE 83C152
The bottom diagram of Figure 3.4 illustrates this mech- collision may attempt transmission during the resolu-
anism for a number of stations (MAX). It shows sta- tion period after an interframe space period. Determi-
tions with slot numbers (MAX-2), 2 and I transmitting nistic mode prevents this from happening because all
during the resolution period. Note the interframe space stations on the link are required to enter into the reso-
after the jam and after each transmission. After all the lution phase, whether or not they are involved in the
slot positions have been exercised, normal CSMA/CD collision. Then, a station is either allowed to transmit
operation resumes. Unless deterministic resolution is during its assigned slot or is prevented from transmit-
selected, it is possible that stations not involved in the ting during the resolution period.
Normal 8ackoff Alternate 8ackoff
~.
IFS
FIRST SLOT TIME FIRST IFS ST
~.
IFS
SLOT TIME IFS ST
SECOND SLOT TIME SLOT TIME SECOND IFS ST ST
SLOT TIME SLOT TIME SLOT TIME IFS ST Sf. ST
COLLISION- COLLISION
270427-11
Normal 8ackoff Mode
(CURRENT
BACKOFF
VALUE=) ~.- - - - - - ( 5 ) . (4) (3) (2) (.) (0)
(lN~IAL =><+!_+_--:)>.j..:~:,-:-----~:~-:-:-:-::-:-:-:-:
BACKOFF j I I I I
VALUE=5): : :.... : :
I I It-, I I I I I ,
: ... I ~ :~: :I!!: ~ : r:: :'~ : ~ : ~
(CURRENT
BACKOFF
VALUE=)~'------' (3) (2) (') (0)
-V: ):::: :
(INI~IAL -"...c:""_+-_J.""'''' "
9ACKOFF ., Ie,
VALUE=3): : :.... : :
1,1-, I I I I
;:: ~ :12: :I!!: ~: J:::: ~:
270427-12
T1 = Collision Detected T6 = Slot A(#4) or 8(#2) Occurring
T2 = Jam Applied T7 = Slot A( # 3) or 8( # 1) Occurring
T3 = Idle Detected T8 = Slot A( # 2) Occurring
T4 = Interframe Space Period T8 = Station 8 8egins Transmission
T5 = Slot A( # 5) or 8( # 3) Occurring T10 = Station A Loses Slot Assignment
Deterministic 8ackoff .Mode
,, ,,
, ,
, ,, , , ,, , 0 ...
;:: ~ , ~
1.... '&1')1
11-11-1 ~ ~
'00 10'1'
11-11-1 ;:: , ;:: ;:: '"
;:: ;::
270427-13
T1 = Collision Detected T8 = Assume Slot Time 4 Occurring
T2 = Jam Applied T9 = Slot Time 3 Occurring
T3 = 1 IFS, No Activity T1 0 = Slot Time 2 Occurs with Activity
T4 = Slot Time for Maximum Available Slot Occurring T11 = IFS for Slot Time 2
T5 = Slot Time for (MAX·1) Occurring T12 = Slot Time 1 Occurs with Activity
T6 = Slot Time for (MAX·2) Occurs with Activity T13 = IFS for Slot Time 1
T7 = IFS for Slot Time (MAX·2) T14 = Normal CSMAlCD Activity
. Figure 3.4. Slot Time Resolution
8-23
inter HARDWARE DESCRIPTION OF THE 83C152
3.2.5 CSMA/CD DATA ENCODING A transmitting station with HABEN enabled expects
an acknowledge. It must receive one prior to the end of
Manchester encoding/decoding is automatically select- the interframe space, or else an error is assumed and
ed when the user software selects CSMA/CO transmis- the NOACK bit is set. Setting of the TON bit is also
sion mode (See Figure 3.5). In Manchester encoding delayed until the end of the interframe space. Collisions
the value of the bit is determined by the transition in detected during the interframe space will also cause
the middle of the bit time, a positive transition is decod- NOACK to be set.
ed as a 1 and a negative transition is decoded as a O.
The user software may enable the interrupt so that the
If the external IX clock feature is chosen the transmis- CPU is notified when TON is set. If the OSC is serv-
sion mode is always NRZ (see Section 3.5.11). Using iced by OMA, the user must time out one interframe
CSMA/CO with the external clock option is not sup- space and then check the NOACK bit or the TON bit.
ported because the data needs reformatting from NRZ
to Manchester for the receiver to be able to detect code
violations and collisions. 3.3 SOLe Operation
3.2.6 HARDWARE BASED ACKNOWLEDGE 3.3.1 SDLC OVERVIEW
Hardware Based Acknowledge (HBA) is a data link SOLC is a communication protocol developed by IBM
packet acknowledging scheme that the user software and widely used in industry. It is based on a primary/
can enable with CSMA/CO protocol. It is not an op- secondary architecture and requires that each second-
tion with SOLC protocol however. ary station have a unique address. The secondary sta-
tions can only communicate to the primary station, and
In general HBA can give improved system response then, only when the primary station allows communi-
time and increased effective transmission rates over ac- cation to take place. This eliminates the possibility of
knowledge schemes implemented in higher layers of the contention on the serial line caused by the secondary
network architecture. Another benefit is the possibility station'S trying to transmit simultaneously.
of early release of the transmit buffer as soon as the
acknowledge is received. In the CIS2, SOLC can be configured to work in either
full or half duplex. When adhering to strict SOLC pro-
The acknowledge consists of a preamble followed by an tocol, full duplex is required. Full duplex is selected
idle condition. A receiving station with HABEN en- whenever a 16-bit CRC is selected. At the end of a valid
abled will send an acknowledge only if the in"oming reset thel6"bit CRC is selected. To select half duplex
address is unique to the receiving station and if the with a 16-bit CRC, the receiver must be turned off by
frame is determined to be correct with no errors. 'For user software before transmission. The receiver is
the acknowledge to be sent, ten must be set. For the turned off by clearing the OREN bit (RSTAT.l). The
transmitting· station to recognize the acknowledge receiver needs to be turned off because the address that
OREN must be set. A zero as the LSB of the address is transmitted is the address. of the secondary station'S
indicates that the address is unique and not a group or receiver. If not turned off, the receiver could mistake
broadcast address. Errors can be caused by collisions, the outgoing message as being intended for itself. When
incorrect CRC, misalignment, or FIFO overflow. The 32-bit CRCs are used, half duplex is the only method
receiver sends the acknowledge as soon as the line is available for transmission.
sensed to be idle. The l!~cr must progI1h~ the interframe
space and the preamble length such that the acknowl-
edge is completed before IFS expires. This is normally
done by programming IFS larger than the preamble.
o o o
I BIT I
- - TIME--+;
270427-14
Figure 3.5. Manchester Encoding
8-24
inter HARDWARE DESCRIPTION OF THE 83C152
3.3.2 SOLC Frame Format CONTROL - The control field is used for initialization
of the system, identifying the sequence of a frame, to
The format of an SOLC frame is shown in Figure 3.6. identify if the message is complete, to tell secondary
The frame consists of a Beginning of Frame flag, Ad- stations if a response is expected, and acknowledgement
dress field, Control Field, Information field (optional), of previously sent frames. The user software is responsi-
a CRC, and the End of Frame flag. ble for insertion of the control field as the .GSC hard-
ware has no provisions for the management· of this
IBOF IADDRESS ICONTROL IINFO ICRC IEOF I field. The interpretation and formation of the control
field must also be handled by user software. The infor-
Figure 3.6. Typical SOLC Frame mation following the control field is typically used for
information transfer, error reporting, and various other
BOF - The begin of frame flag for SOLC is 01111110. functions. These functions are accomplished by the for-
It is only one of two possible combinations that have six mat of the control field. There are three formats avail-
consecutive ones in SOLC. The other possibility is an able. The types of formats are Informational, Supervi-
abort character which consists of eight or more consec- sory, or Unnumbered. Figure 3.7 shows the various for-
utive ones. This is because SOLC utilizes a process mat types and how to identify them.
called bit stuffing. Bit stuffing is the insertion of a 0 as
the next bit every time a sequence of five consecutive Is Since the user software is responsible for the implemen-
is detected. The receiver automatically removes a 0 af- tation of the control field, what follows is a simple ex-
ter every consecutive group of five ones. This removal planation on the control field and its functions. For a
of the 0 bit is referred to as bit stripping. Bit stuffing is complete understanding and proper implementation of
discussed in Section 3.3.4. All the procedures required SOLC, the user should refer to the IBM document,
for bit stuffing and bit stripping are automatically han- GA27-3093-2, IBM Synchronous Oata Link Control
. died by the GSC. General Information. Within that document, is another
list of IBM documents which go into detail on the
In standard SOLC protocol the BOF signals the start of SOLC protocol and its use.
a frame and is limited to 8 bits in length. Since there is
no preamble in SOLC the BOF is considered an entire The control field is eight bits wide and the format is
separate field and marks the beginning of the frame. determined by bits 0 and 1. If bit 0 is a zero, then the
The BOF also serves as the clock synchronization frame is an informational frame. If bit 0 is a one and bit
mechanism and the reference point for determining the 1 a zero, then it is a supervisory frame, and if bit 0 is a
position of the address and control fields. one and bit I a one then the frame is an unnumbered
frame.
AOORESS - The address field is used to identify which
stations the message is intended for. Each secondary In an informational frame bits 3,2,1 contain the se-
station must have a unique address. The primary sta- quence count of the frame being sent.
tion must then be made aware of which addresses are
assigned to each station. The address length is specified Bit 4 is the P IF (Poll/Final) bit. If bit 4 equals 1 and
as 8-bits in standard SOLC protocols but it is expand- originates from the primary, then the secondary station
able to 16-bits in the C152. User software can further is expected to initiate a transmission. If bit 4 equals 1
expand the number of address bits, but the automatic and originates from a secondary station, then the frame
address recognition feature works on a maximum of 16- is t~e final frame in a transmission.
bits.
Bits 7,6,5 contain the sequence count a station expects·
In SOLC the addresses are normally unique for each on the next transmission to it. The sequence count can
station. However, there are several classes of messages vary from OOOB to 11 lB. The count then starts over
that are intended for more than one station. These mes- again at OOOB after the value IliB is incremented. The
sages are called broadcast and group addressed frames. acknowledgement is recognized by the receiving station
An address consisting of allIs will always be automati- when it decodes bits 7,6,5 of an incoming frame. The
cally received by the GSC, this is defined as the broad- station sending the transmission is acknowledging the
cast address in SOLC. A group address is an address frames received up to the count represented in bits 7,6,5
that is common to more than one station. The GSC (sequence count-I). With this method, up to seven se-
provides address masking bits to provide the capability quential frames may be transmitted prior to an ac-
of receiving group addresses. knowledgement being received. If eight frames were al-
lowed to pass before an acknowledgement, the sequence
If desired, the user software can mask off all the bits of count would roll over and this would negate the pur-
the address. This type of masking puts the GSC in a· pose of the sequence numbers.
promiscuous mode so that all addresses are received.
8-25
HARDWARE DESCRIPTION OF THE 83C152
BIT
POSITIONS-
7 65. 4 321 o
RE¢'EPTjlON SENDING
SEQUENCE SEQUENCE
270427-15
RECEPTION SEQUENCE - The sequence expected in (the SENDING SEQUENCE portion of the control byte
in the next received frame. This also confirms correct reception of up to seven frames prior to the sequence given.
POLL/FINAL - Identifies the frame as being a polling request from the master station or the last in a series of
frames from the master or secondary;
SENDING SEQUENCE- Identifies the sequence of the frame being transmitted.
o - If bit 0 = 0 the frame. is identified as a informational format type.
INFORMATION FORMAT
-----------------~----------------------------~---------
M
POSITIONS- 7 6 5 4 3 .2 o
~R-E~C-E-P-T~:IO-N-,-po-LL-/~~--~--~~
SEQ UEN CE FINAL
270427-16
RECEPTION SEQUENCE - Expected sequenceofframe for next reception.
POLL/FINAL - Identifies frame as being a polling request from the' master station or the last in a series of
frames from the master or secondary. .
MODE - Identifies whether receiver is ready (00), not ready (10) or a frame was rejected (Oi). The rejected frame
is identified by the reception sequence. .
0,1 - If bits I,D = 0,1 the frame is identified as a supervisory format type.
SUPERVISORY FORMAT
-------------~--------------------------------~-~-------
. M 7 6 5 432 1 0
POSITIONS-.--_ _·..,.--_ _,--_ _- - - . . - - - - , - -___- - - - . . . - -.....
,I.
.
COMMAND/ IpOLL/ICOMMAND/1
R~sPoNsE ViNAl·1 RESPONSE I
1 1
I I
II
270427-17
COMMAND/RESPONSE - Identifies the type of command. or response.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
1,1 - If bits I,D == 1,1 the 'frame is identified as an unnumbered format type.
NONSEQU'ENCED FO'RMAT , 270427-18
Figure 3.7. SDLC Control Field
8-26
inter HARDWARE DESCRIPTION OF THE 83C152
Following the informational control field comes the in- When the mode is 10, the sending station is indicating
formation to be transferred. that its receiver is not ready to accept frames.
In the supervisory format (bits 1,0 = 0,1) bits 3,2 de- Mode 11 is an illegal mode in SDLe protocol.
termine which mode is being used.
Bits 7,6,5 represent the value of the sequence the sta-
When the mode is 00 it indicates that the receive line of tion expects when the next transfer occurs for that sta-
the station that sent the supervisory frame is enabled tion. There is no information following the control field
and ready to accept frames. when the supervisory format is used.
When the mode is 01, it indicates that previously a In the unnumbered format (bits 1,0 = 1,1) bits 7, 6, 5,
received frame was rejected. The value in the receive 3, 2 (notice bit 4 is missing) indicate commands from
count identifies which frame(s) need to be retransmit- the primary to secondary stations or requests of second-
ted. ary stations to the pritnary.
The standard commands are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered Information (UI)
0 0 0 0 1 Set initialization mode (SIM)
0 1 0 0 0 Disconnect (DISC)
0 0 1 0 0 Response optional (UP)
1 1 0 0 1 Function descriptor in
information field (CFGR)
0 1 1 Identification in information field. (XID)
1 0 0 Test pattern in information field. (TEST)
The standard responses are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered information (UI)
0 0 0 0 1 Request for initialization (RIM)
0 0 0 1 1 Station in disconnected mode (OM)
1 0 0 0 1 Invalid frame received (FRMR)
0 1 1 0 0 Unnumbered acknowledgement (UA)
1 1 1 1 1 Signal loss of input (BCN)
1 1 0 0 1 Function descriptor in information field (CFGR)
0 1 0 0 0 Station wants to disconnect (RD)
1 0 1 1 1 Identification in information field (XID)
1 1 1 0 0 Test pattern in information field (TEST)
8-27
HARDWARE 'DESCRIPTION OF THE 83C152
In an unnumbered frame, information of variable rithms, a 16-bit and a 32-bit. The 32-bit algorithm is
length may follow the control field if UI is, used, or normally used in. CSMAlCD applications and is de-
information of fixed length may follow if FRMR is scribed in section 3.2.2. In most SDLC applications a
used. 16-bit CRC is used and the hardware configuration that
supports 16-bit CRC is shown in Figure 3.8; The gener-
As stated earlier, the user software is responsible for the ating polynomial that the CRC generator uses with the
proper management of the control field. This portion of 16-bit CRC is:
the frame is passed to or from the GSCFIFOs as basic
informational type data. G(X) = X"16 + X"12 + X"5 + 1
INFO - This is the information field and contains ,the The way the CRC operates is that as a bit is received it
data that,one device on the 'link' wishes to transmit to is XOR'd with bit 15 of the current CRC and placed in
another device. It can be of any length the user wishes, temporary storage. The result of XOR'ing bit 15 with
but must be a multiple of 8 bits. It is possible that some the received bit is then XOR'dwith bit 4 and bit 11 as
frames may contain no information field. The informa- the CRC is shifted one position to the right. The bit in
tion field is identified to the receiving stations by the temporary storage is shifted into position O.
preceding control field and the following CRC. The
GSC determines where the last of the information field The required CRC length for SDLC is' 16 bits. The
is by passing the bits through the CRC generator. CRC is automatically stripped from the frame and not
When the last bit or BOF is received the bits that re- passed on: to the CPU. The last 16 bits ,are then run
main constitute the CRC. though the CRC generator to insure that the correct
remainder is left. The remainder that is checked for is
CRC - The Cyclic Redundancy Check (CRC) is an er- 001110100001111B (lDOF Hex). If there is a mis-
ror checking sequence commonly used in serial com- match, an error is generated. The user software has the
munications. The C152 offers two types of CRC algo- optiqn of enabling this interrupt so the CPU is notified.
270427-19
Figure3_8_16-BitCRC
8-28
inter HARDWARE DESCRIPTION OF THE 83C152
EOF - The End Of Frame (EOF) indicates when the 3.3.5 SENDING ABORT CHARACTER
transmission is complete. The EOF is identified by the
end flag. An end flag consists of the bit pattern An abort character is one of the exceptions to the rule
01111110. The EOF can also serve as the BOF for the that disallows more than 5 consecutive Is. The abort
next frame. character consists of any occurrence of seven or more
consecutive ones. The simplest way for the CI52 to
send an abort character is to clear the TEN bit. This
3.3.3 DATA ENCODING causes the output to be disabled which, in turn, forces it
The transmission of data in SDLC mode is done via to a constant high state. The delay necessary to insure
NRZI encoding as shown in Figure 3.9. NRZI encod- that the link is high for seven bit times, is a task that
ing transmits data by changing the state of the output needs to be handled by user software. Other methods of
whenever a 0 is being transmitted. Whenever a I is sending an abort character are using the IFS register or
transmitted the state of the output remains the same as using the Raw Transmit mode. Using IFS still entails
the previous bit and remains valid for the entire bit clearing the TEN bit, but TEN can be immediately re-
time. When SDLC mode is selected it automatically enabled. The next message will not begin until the IFS
enables the NRZI encoding on the transmit line and expires. The IFS begins timing out as soon as DEN
NRZI decoding on the receive line. goes high which identifies the end of transmission. This
also requires that IFS contain a value equal to or great-
er than 8. This method may have the undesirable effect
3.3.4 BIT STUFFING/STRIPPING that DEN goes high and disables the external drivers.
The other alternative is to switch to Raw Transmit
In SDLC mode one of the primary rules of the protocol mode. Then, writing OFFH to TFIFO would generate a
is that in any normal data transmission, there will never high output for 8 bit times. This method would leave
be an occurrence of more than 5, consecutive Is. The DEN active during the transmission of the abort char-
GSC takes care of this housekeeping chore by automat- acter.
ically inserting a 0 after every occurrence of 5 consecu-
tive Is and the receiver automatically removes a zero When the receiver detects seven or more consecutive Is
after receiving 5 consecutive Is. All the necessary steps and data has been loaded into the receive FIFO, the
required for implementing bit stuffing and stripping are RCABT flag is set in RSTAT and that frame is ig-
incorporated into the GSC hardware. This makes the nored. If no data has been loaded into the receive
operation transparent to the user. About the only time FIFO, there are no abort flags set and that fraine is just
this operation becomes apparent to the user, is if the ignored. A retransmitted frame may immediately fol-
actual data on the transmission medium is being moni- Iowan abort character, provided the proper flags are
tored by a device that 'is not aware of the automatic used.
insertion of Os. The bit stuffing/stripping guarantees
that there will be at least one transition every 6 bit
times while the line is active.
o , , o o
BIT '
-TIME~
270427-20
Figure 3.9. NRZI Encoding
8-29
inter HARDWARE DESCRIPTION OF THE 83C152
3.3.6 LINE IDLE passing the message to the downstream· station. This
delay is necessary so that a station can decode its own
If 15 or more consecutive Is are detected by the receiv- address before the message is passed on. The various
er the Line Idle bit (LNI) in TSTAT is set. The seven networks are shown in Figure 3.10.
Is from the abort character may be included when sens-
ing for a line idle condition. The same methods used for
sending the Abort character can be used for creating 3.3.9 HDLC/SDLC COMPARISON
the Idle condition. However, the values would need to HDLC (High level Data Link Control) is a standard
be changed to reflect 15 bit times, instead of seven bit adopted by the International Standards Organization
times. (ISO). The HDLC standard is defined in theISO docu-
ment #ISO 6159 - HDLC unbalanced classes ofproce-
3.3.7 ACKNOWLEDGEMENT dures. IBM developed the SDLC protocol as a subset of
HDLC. SDLC conforms to HDLC protocol require-
Acknowledgment in SDLC is an implied acknowledge ments, but is more restrictive. SDLC contains a more
/ and is contained in the controi field. Part of the control precise definition on the modes of operation.
frame is the sequence number .of the next expected
frame. This sequence number is caUed the Receive Some of the major differences between SDLC and
Count. In transmitting the Receive Count, the receiver HDLCare:
is in fact acknowledging aU the previous frames prior to SDLC HDLC
the count that was transmitted. This allows for the Unbalanced (primary/ Balanced
transmission of up to seven frames before an acknowl- secondary) (peer to peer)
edge is required back to the transmitter. The limitation Modulo 8 (no extensions Modulo 128 (up to 127
of seven frames is necessary because the Receive Count
in the control field is limited to three binary diiits. This allowed, up to 7 out- outstanding frames
means that if an eighth transmission occurred this standing frames before before acknowledge
would cause the next Receive Count to repeat the first acknowledge is required) is required)
count that still is waiting for an acknowledge. This 8-bit addressing only Extended addressing
would defeat the purpose of the acknowledgement. The Byte aligned data Variable size of data
processing and general maintenance of the sequence
cOunt must be done by the user software. The Hard- The C152 does not support HDLC implementation re-
ware Based Acknowledge option that is provided in the quiring data alignment other than byte alignment. The
Cl52 is not compatible with standard SDLC protocol. user wiU find that many of the protocol parameters are
programmable in the Cl52 which allows easy imple-
mentation of proprietary or standard HDLC network.
3.3.8 PRIMARY/SECONDARY STATIONS User software needs to implement the control field
All SDLC networks are based upon a primary/second- functions.
ary station relationship. There can be only one primary
station in a network and aU the other stations are con-
sidered secondary. All communication is between the 3.4 User Defined Protocols
primary and secondary station. Secondary station to The explanation on the implementation of user defined
secondary station direct communication is prohibited. protocols would go beyond the scope of this manual,
If there is a need for secundary to secondary COfliiliuni-
but examining Table 3.1 should give the reader a con-
cation, the user software will have to make aUowances solidated list of niost of the possibilities. In this manual,
for the master to act as an intermediary. Secondary any deviation from the documents that cover the imple-
stations are aUowed use of the serial line only when the mentation of CSMA/CD or SDLC are considered user
master permits them. This is done by the master polling defmed protocols. Examples of this would be the use of
the secondary stations to see if they have a need to SDLC with the 32-bit CRC selected or CSMA/CD
access the serial line: This should prevent any collisions with hardware based acknowledge.
from occurring, provided each secondary station has its
own unique address. This arrangement also partiaUy
determines the types of networks supported. Normal
SDLC networks consist of point-to-point, multi·drop, 3.5 Using the GSC
or ring configurations and the Cl52 supports aU of
these. However, some SDLC processors support an au- 3.5.1 LINE DISCIPLINE
tomatic one bit delay at each node that is not supported
by the C152. In a "Loop Mode" configuration, is is Line discipline is how the management of the transfer
necessary that the transmission be delayed from the re- of data over the physical medium is controlled. Two
ception of the frames from the upstream station before types of line discipline will be discussed in this section:
full duplex and half duplex.
8-30
HARDWARE DESCRIPTION OF THE 83C152
Point-to-Point Network
270427-21
Multi-Drop Network
270427-22
Ring Network
270427-23
Figure 3.10. SOLe Networks
8-31
inter HARDWARE DESCRIPTION OF THE 83C152
Full duplex is the simultaneous transmission and recep- Some of the general areas that will impact the overall
tion of data. Full duplex uses anywhere from two to scheme on how to incorporate future changes to the
four wires. At least one wire is needed for transmission system are:
and one wire for reception. Usually there will also be a
ground reference on each signal if the distance from 1) Communication of the change to all the stations or
station to station is relatively long. Full-duplex opera- the primary station.
tion in the C152 requires that both the receive and the
transmit portion ,of the GSC are functioning at the 2) Maximum distance for communication. This will af-
same time. Since both the transmitter and receiver are fect the drivers used and the slot time.
operating, two CRC generators are also needed. The
C152 handles this problem by having one 32-bit CRC 3) More stations may be on the line at one time. This
generator and one 16-bit CRC generator. When sup- may impact the interframe space or the collision resolu-
porting full-duplex operation, the 32-bit CRC generator tion used.
is modified to work as a 16-bit CRC generator. When-
ever the 16-bit CRC is selected, the GSC automatically 4) If using CSMAlCD without deterministic resolu-
enters the full duplex mode. Half duplex with a 16-bit tion, any increase in network size will have a negative
CRC is discussed in the following paragraph. impact on the average throughput of the network and
lower the efficiency. The user will have to give careful
Half duplex is the alternate transmission and reception consideration when deciding how large a system can
of data over a single cornmon wire. Only one or two ultimately be and still maintain adequate performance.
wires are needed in half-duplex systems. One wire is
needed for the signal and if the distance to be covered is
long there will also. be a wire for the ground reference. 3.5.3 DMA SERVICING OF GSC CHANNELS
In half-duplex mode, only the receiver or- transmitter
There are two sources that can be used to control the
can operate at one time. When the receiver or transmit-
GSC. The first is CPU control and the second is DMA
ter operates is determined by user software, but typical-
control.
ly the receiver will always be enabled unless the GSC is
transmitting. Whenever half duplex is being used the
CPU control is used when user software takes care of
software must insure that only the receiver or transmit- . the tasks such as: loading the TFIFO, reading the RFI-
ter is enabled at any given time. This is particularly FO, checking the status flags, and general tracking of
important when using SDLC, so that the receiver will
the transmission process. As the number of tasks grow
not recognize its own address when the transmitter is and higher data transfer rates are used, the overhead
operating. Half-duplex operation in the C152 is sup- required by the CPU becomes the dominant consump-
ported with either 16-bit or 32-bit CRCs. Whenever a
tion of time. Eventually, a point is reached where the
32-bit CRC is selected, only half-duplex operation can
CPU is spending 100% of its time responding to the
be supported by the GSC. It is possible to simulate full-
needs of the GSC. An alternative is to have the DMA
duplex operation with a 32-bit CRC, but this would channels control the GSC.
require that the CRC be performed with software. CaI-
culating the CRC with the CPU would greatly reduce
A detailed explanation on the general use of the DMA
the data rates that could be used with the GSC. When-
channels is covered in Section 4. In this section only
ever a 16-bit CRC is selected, full-duplex operation is
those details required for the use of the DMA channels
automatically chosen and the GSC must be reconfig-
with the GSC will be covered.
ured if half-duplex operation is preferred.
The DMA channels can be configured by user software
3.5.2 PLANNING FOR NETWORK CHANGES so that the GSC data transfers are serviced by the
AND EXPANSIONS DMA controller. Since there are two DMA channels,
one channel can be used to service the receiver, and one
A complete explanation on how to plan for network channel can. be used to service the transmitter. In using
expansion will not be covered in this manual as there the DMA channels, the CPU is relieved of much of the
are far too many possibilities that would need to be time required to do the basic servicing ofthe GSC buff-
discussed. But there are several areas that will have ers. The types of servicing that the DMA channels can
major impact when allowing for changes in the system. provide are: loading of the transmit FIFO, removing.
In cases where there will never be any changes allowed, data from the receive FIFO, notification of the CPU
expansion plans become a mute issue. However, it is when the transmission or reception has ended, and re-
strongly suggested that there always be some allowance sponse to certain error conditions. When using the
for future modifications.
8-32
inter HARDWARE DESCRIPTION OF THE 83C152
DMA channels the source or destination of the data that will be received, up to 64K. If not using the Done
intended for serial transmission can be internal data flag, then GSC servicing would be driven by the receive
memory, external data memory, or any of the SFRs. Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected. When using the RDN flag, RFNE
The only tasks required after initialization of the DMA should also be checked to insure that all the data has
and GSC registers are enabling the proper interrupts been emptied out of the receive FIFO.
and informing the DMA controller when to start. After
the DMA channels are started all that is required of the The byte count register is used for all transmissions and
CPU is to respond to error conditions or wait until the this means that all packets going out will have to be of
end of transmission. the same length or the length of the packet to be sent
will have to be known prior to the start of transmission.
Initialization of the DMA channels requires setting up When using the DMA channels to service the GSC
the control, source, and destination address registers. transmitter, there is no practical way to disable the
On the DMA channel servicing the receiver, the con- Done flag. This is because the transmit done flag
trol register needs to be loaded as follows: DCONn.2 = (TDN) is set when the transmit FIFO is empty and the
0, this sets the transfer mode so that response is to GSC last message bit has been transmitted. But, when using
interrupts and put the DMA control in alternate cycle the DMA channel to service the transmitter, loads to
mode; DCONn.3 = 1, this enables the demand mode; the TFIFO continue to occur until the byte count
DCONnA = 0, this clears the automatic increment reaches O. This makes it impossible to use TDN as a
option for the source address; and DCONn.5 = I, this flag to stop the DMA transfers to TFIFO. It is possible
defines the source as SFR: The DMA channel servicing to examine some other registers or conditions, such as
the receiver also needs its source address register to the current byte count, to determine when to stop the
contain the address of RFIFO (SARHN = XXH, DMA transfers to TFIFO, but this is not recommended
SARLN = OF4H). On the DMA channel servicing the as a way to service the DMA and GSC when transmit-
transmitter, the control register needs to be loaded as ting because frequent reading of the DMA registers will
follows: DCONn.2 = 0; DCONn.3 = I; DCONn.6 = cause the effective DMA transfer rate to slow down.
0, this clears the automatic increment option for the
destination address; and DCONn.7 = I, this sets the When using the DMA channels, initialization of the
destination as SFR. The DMA channel serving the GSC would be exactly the same as normal except that
transmitter also requires that its destination address TSTAT.O = I (DMA), this informs the GSC that the
register contains the address of TFIFO (DARHN = DMA channels are going to he lIsed to service the GSC.
XXH, DARLN = 85H). Assuming that DCONO Although only TSTAT is written to, hoth the receiver
would be serving the receiver and DCONI the trans- and transmitter use this sallie DMA hit.
mitter, DCONO would be loaded with XXIOIOXOB
and DCONI would be loaded with IOXXIOXOB. The The interrupts EGSTE (IEN1.5), GSC transmit error;
contents of SARRO and DARHI do not have any im- EGSTV (lEN 1.3), GSC transmit valid; EGSRE
pact when using internal SFRs as the source or destina- (IENl.l), GSC receive error; and EGSRV (IENl.O),
tion. GSC receive valid; need to be enabled. The DMA inter-
rupts are normally not used when servicing the GSC
When using the DMA channels to service the GSC, the with the DMA channels. To ensure that the DMA in-
byte count registers will also need to be initialized. terrupts are not responded to is a function of the user
software and should be checked by the software to
The Done flag for the DMA channel servicing the re- make sure they are not enabled. Priority for these inter-
ceiver should be used if fixed packet lengths only are rupts can also be set at this time. Whether to use high
being transmitted or to insure that memory is not over- or low priority needs to be decided by the user. When
written by long received data packets. Overwriting of responding'to the GSC interrupts, if a buffer is being
data can occur when using a smaller buffer than the. used to store the GSC information, then the DMA reg-
packet size. In these cases the servicing of the DMA isters used for the buffer will probably need updating.
and/or GSC would be in response to the DMA Done
flag when the byte ~ount reaches zero. After this initialization, all that needs to be done when
the GSC is actually going to be used is: load the byte
In some cases the buffer size is not the limiting factor count, set-up the source addresses for the DMA chan-
and the packet lengths will be unknown. In these cases nei servicing the transmitter, set-up the destination ad-
it would be desirable to eliminate the function of the dresses for the DMA channel servicing the receiver,
Done flag. To effectively disable the Done flag for the and start the DMA transfer. The GSC enable bits
DMA channel servicing the receiver, the byte count should be set first and then the GO bits for the DMA.
should be set to some number larger than any packet This initiates the data transfers.
8-33
intJ HARDWARE DESCRIPTION OF THE 83C152
This simplifies the maintenance of the GSC and can Initialization of the system can be broken down into
make the implementation of an external buffer for several steps. First, are the assumptions of each net-
packetized information automatic. work station.
An external buffer can be used as the source of data for The first assumption is that the type of data encoding
transmission, or the destination of data from the receiv- to be used is predetermined for the system and that
er. In this arrangement, the message size is limited to each station will adhere to the same basic rules defining
the RAM size or 64K, whichever is smaller. By using that encoding. The second assumption is that the basic
an external buffer, the data can be accessed by other protocol and line discipline is predetermined and
devices which may want access to the serial data. The known. This means that all stations.are using CSMAI
amount of time required for the external data moves CD or SDLC or whatever, and that all stations are
will also decrease. Under CPU control, a "MOVX" either full or half duplex. The third assumption is that
command would take 24 oscillator periods to complete. the baud rate is preset for the whole system. Although
Under DMA control, external to internal, or internal to the baud rate could probably be determined by the mi-
external, data moves take only 12 oscillator periods. croprocessor just by monitoring the link, it will make it
much simpler if the baud rate is known in advance.
3.5.4 BAUD RATE One of the first things that will be required during sys-
tem initialization is the assignment of unique addresses
The GSC baud rate is determined by the contents of the
SFR, BAUD, or the external clock. The formula used for each station. In a two-station only environment this
to determine the baud rate when using the internal is not necessary and can be ignored. However, keep in
mind, that all systems should be constructed for easy
clock is:
future expansions. Therefore, even in only a two station
(fosc)/«BAUD+ 1)*8) system, addresses should be assigned. There are three
basic ways in which addresses can be assigned. The
For example if a 12 MHz oscillator is used the baud first, and most common is preassigned addresses that
rate can vary from: - are loaded into the station by the user. This could be
done with a DIP-switch, through a keyboard. The sec-
12,000,000/«0-1- 1)'8) = 1.5 MBPS ond method of assigning addresses is to randomly as-
sign an address and, then check for its uniqueness
to: throughout the system, and the third method is to
make an inquiry to the system for the assignment of a
12.000.000/«255+1)'8) ='5.859 KBPS unique address. Once the method of address assignment
is determined, the method should become part of the
There are certain requirements that the external clock specifications for the system to which all additions will
will need to meet. These requirements are specified in have to adhere. This, then, is the final assumption.
the data sheet. For a description of the use of the GSC
with external clock please read Section 3.5.11. The negotiation process may not be clear for some
readers. The following two procedures are given as a'
guideline for dynamic address assignment.
3.5.5 INITIALIZATION
In the first procedure, a station assumes a random ad-
Initialization can be broken down into two major' com-
dress and then checks for its uniqueness throughout the
ponents, i) iniiiaiizaiion of the component so that its
system. As a station is initialized into the system it
serial port is capable of proper communication; and 2)
sends out a message containing its assumed address.
initialization of the system or a station so that intelligi-
The format of the message should be such that any
ble communication can take place.
station decoding the address recognizes it as a request
for initialization. If that address is already used, the
Most of the initialization of the component has already
receiving station returns a message, with its own ad-
been discussed in the previous sections. Those items not
dress stating that the address in question is already tak-
covered are the parameters required for the component
en. The initializing station then picks another address.
to effectively communicate with other components.
When the initializing station sends its inquiry for the
These types of issues are common to both system and
address check, a timer is also started. If the timer ex-
component initialization and will be covered in the fol-
lowing text. pires before the iilquiry is responded to, then that sta-
tion assumes the address chosen is okay.
8-34
inter HARDWARE DESCRIPTION OF THE 83C152
In the second procedure, an initializing station asks for In Raw Receive, the transmitter should be externally
an address assignment from the system. This requires connected to the receiver. To do this a port pin should
that some station on the link take care of the task of be used to enable an external device to connect the two
maintaining a record of which addresses are used. This pins together. In Raw Receive mode the receiver acts as
station will be called station-I. When the initializing normal except that all bytes following the BOF are
station, called station-2, gets on the link, it sends out a loaded into the receive FIFO, including the CRC. Also
message with a broadcast address. The format of the address recognition is not active but needs to be per-
message should be such that all other stations on the formed in software. IfSDLC is selected as the protocol,
link recognize it as a request for address assignment. zero-bit deletion is still enabled. The transmitter still
Part of the message from station-2 is a random number operates as normal and in this mode most of the trans-
generated by the station requesting the address. Sta- mitter functions and an external transceiver can be test-
tion-2 then examines all received messages for this ran- ed. This is also the only way that the CRC can be read
dom number. The random number could be the address by the CPU, but the CRC error bit will not be set.
of the received message or could be within the informa-
tion section of a broadcast frame. All the stations, ex-
cept station-I, on the link should ignore the initializa- 3.5.7 EXTERNAL DRIVER INTERFACE
tion request. Station-I, upon receiving the initialization A signal is provided from the CI52 to enable transmit-
request, assigns an address and returns it to station-2. ter drivers for the serial link. This is provided for sys-
Station-l will be required to format the message in such tems that require more than what the GSC ports are
a manner so that all stations on the link recognize it as capable of delivering. The voltage and currents that the
a response to initialization. This means that all stations GSC is capable of providing are the saine levels as those
except station-2 ignore the return message. for normal port operation. The signal used to enable the
external drivers is DEN. No similar signal is needed for
3.5.6 TEST MODES the receiver.
There are two test modes associated with the GSC that
are made available to the user. The test modes are 3.5.8 JITTER (RECEIVE)
named Raw Receive and Raw Transmit. The test Datajitter is the difference between the actual transmit-
modes are selected by the proper setting of the two ted waveform and the exact calculated value(s). In
mode bits in GMOD (MO = GMOD.5, MI = NRZI, data jitter would be how much the actual wave-
GMOD.6). If Ml,MO = 0,1 then Raw Transmit is se- form exceeds or falls short of one calculated bit time. A
lected. If MI,MO = 1,0 then Raw Receive is enabled. bit time equals l/baud rate. If using Manchester encod-
ing, there can be two transitions during one bit time as
In Raw Transmit, the transmit output is internally con- shown in Figure 3.11. This causes a second parameter
nected to the Receiver input. This is intended to be to be considered when trying to figure out the complete
used as a local loop-back test mode, so that all data data jitter aniount. This other parameter is the half-bit
written to the transmitter will be returned by the re- jitter. The half-bit jitter is comprised of the difference in
ceiver. Raw Transmit can also be used to transmit user time that the half-bit transition actually occurs and the
data. If Raw Transmit is used in this way the data is calculated value. Jitter is important because if the tran-
emitted with no preamble, flag, address, CRC, and no sition occurs too soon it is considered noise, and if the
bit insertion. The data is still encoded with whatever transition occurs too late, then either the bit is missed
format is selected, Manchester with CSMA/CD, NRZI or a collision is assumed.
with SDLC or as NRZ if external clocks are used. The
receiver still operates as normal and in this mode most
of the receive functions can be tested.
8-35
inter HARDWARE DESCRIPTION OFTHE 83C152
LOGICAL o o o
VALUE
MANCHESTER
ENCODING
'I
'f "1" BIT TIME "1" BIT TIME a'
(8 X BAUDf
RECEIV
I
SAMPLING I
RATE
I I
....
I I
RECEIVED I
.. -
I I I I
DATA I I I I I I
'1 "1" BIT TIME 1'1 "0" BIT TIME .,
I
... I
, I
I
I
I
.-----
I I
RECEIVED I
.. -
I I I. I
DATA .1
I
I I
I
I
I
I I
---- ..
270427-24
Figure 3.11. Jitter
8-36
inter HARDWARE DESCRIPTION OF THE 83C152
I
I BIT I
:~ TIME ---..:
I
a a a
NRZ
L
270427-25
Figure 3.12. Transmit Waveforms
3.5.9 Transmit Waveforms has to be set to a 1. To select external clocking for'the
receiver, XRCLK (PCON.3) has to be set to a 1. Set-
The GSC is capable of three types of data encoding, ting both bits to I forces external clocking for the re-
Manchester, NRZI, and NRZ. Figure 3.12 shows ex- ceiver and transmitter.
amples of all three types of data encoding.
The external transmit clock is applied to pin 4 (TXC),
P1.3. The external receive clock is applied to pin 5
3.5.10 Receiver Clock Recovery (RXC), PI.4. To enable the external clock function on
The receiver is always monitored at eight times the the port pin, that pin has to be set to a 1 in the appro-
baud rate frequency, except when an external clock is priate SFR, PI.
used. When using an external clock the receiver is load-
ed during the clock cycle. Whenever the external clock option is used, the format
of the transmitted and received data is restricted to
In CSMA/CO mode the receiver synchronizes to the NRZ encoding and the protocol is restricted to SOLC;
transmitted data during the preamble. If a pulse is de- With external clock, the bit stuffing/stripping is still
tected as being too short it is assumed to be noise or a active with SOLC pr~.tocoI.
collision. If a pulse is too long it is assumed to be, a
collision or an idle condition.
3.6 GSC Operation
In SOLC the synchronization takes place during the
BOF flag. In addition, pulses less than four sample pe- 3.6.1 Determining Line Discipline
riods are ignored, and assumed to be noise. This sets a
lower limit on the pulse size of received zeros. In normal operation the GSC uses full or half duplex
operation. When using a 32-bit CRC (GMOO.3 = I),
In CSMA/CO the preamble consists of alternating Is operation can only be half duplex. If using a 16-bit
and Os. Consequently, the preamble looks like the CRC (GMOO.3 = 0), full duplex is selected by de-
waveform in Figure 3.13A and 3.13B. fault. When using a 16-bit CRC the receiver can be
turned off while transmitting (RSTAT.I = 0), and the
transmitter can be turned off during reception
3.5.11 External Clocking (TSTAT.I = 0). This simulates half-duplex operation
when using a 16-bit CRC.
To select external clocking, the user is given three
choices. External clocking.can be used with the trans- Normally, HOLC uses a 16-bit CRC, so half duplex is
mitter, with the receiver, or with both. To select exter- determined by turning off the receiver or transmitter.
nal clocking for the tran~mitter, XTCLK (GMOO.7) This is so that the receiver will not detect its own ad-
8-37
inter HARDWARE DESCRIPTION OF THE 83C152
CSMAICO Clock Recovery
o, 1 , 0 1 , 0 ,1 1 ,0 0 0 0',
IDEAL WAVEFORM
., ,
I I I I I I I I I I I I I I I I I
ax SAMPLING RATE 111111111111111111111111111111111111111111111111111111\1111111111111111.11111111,11111I11j11l1l11l11l11l1Ul1l111j111l1l1l11l11l1l1l11111111l1111
, ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-26
Figure 3.13A. Clock Recovery
SOLC Clock Recoyery
o 000 o 0: 0:
IDEAL WAVEFORM
, ,
I I I I I I I I I I I I I I I I I
ax SAMPLING RATE 1111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111
ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-27
Figure 3.138. Clock Recovery
8-38
infef HARDWARE DESCRIPTION OF THE 83C152
dress as transmission takes place. This also needs to be multi-cast address. The user software can enable the
done when using CSMA/CD with a 16-bit CRC for the interrupt for RDN to determine when a frame is com-
same reason. pleted.
In DMA mode the interrupts are generated by the in-
3.6.2 CPU/DMA CONTROL OF THE GSC ternal "transmit/receive done" (TDN,RDN) condi-
The data for transmission or reception can be 'handled tions. When the CPU responds to TDN or RDN,
by either the CPU (TSTAT.O = 0) or DMA controller checks are performed to see if the transmit underrun
(TSTAT.O = I). This allows the user two sets of flags error has occurred. The underrun condition is only
to control the FIFO. Associated with these flags are checked when using the DMA channels.
interrupts, which may be enabled by the user software.
Either one or both sets of flags may be used at the same Upon power up the CPU mode is initialized. General
time. DMA control is covered in Section 4.0. DMA control
of the GSC is covered in Section 3.5.4. IfDMA is to be
In CPU control mode the flags (RFNE,TFNF) are gen- used for serving the GSC, it must be configured into the
erated by the condition of the receive or transmit FI- serial channel demand mode and the DMA bit in
FO's. After loading a byte into the transmit FIFO, TSTAT has to be set.
there is a one machine cycle latency until the TFNF
flag is updated. Because of this latency, the status of 3.6.3 COLLISIONS AND BACK OFF
TFNF should not be checked immediately following
the instruction to load the transmit FIFO. If using the The actions that are taken by the GSC if a collision
interrupts to service the transmit FIFO,the one ma- occurs while transmitting depend on where the colli-
chine cycle of latency must be considered if the TFNF sion occurs. If a collision occurs in CSMA/CD mode
flag is checked prior to leaving the subroutine. following the preamble and BOF flag, the TCDT flag is
set and the transmit hardware completes a jam. Whcn
When using the CPU for control, transmission normal- this type of collision occurs, there will be no automatic
ly is initiated by setting the TEN bit (TSTAT.l) and retry at transmission. After the jam, control is returncd
then writing to TFIFO. TEN must be set before load- to the CPU and user software must then initiate what-
ing the transmit FIFO, as setting TEN "clears the trans- ever actions are necessary for a proper recovery. The
mit FIFO. TCDCNT should also be checked by user possibility that data might have been loaded into or
software and cleared if a collision occurred on a prior from the GSC deserves special consideration. If these
transmission. fragments of a message have been passed on to other
devices, user software may have to perform some exten-
To enable the receiver, GREN (RSTAT.l) is set. After sive error handling or notification. Before starting a
GREN is set, the GSC begins to look for a valid BOF. new message, the transmit and receive FIFOs will need
After detecting a valid BOF the GSC attempts to to be cleared. IfDMA servicing is being used the point-
match the received address byte(s) against the address ers must also be reinitialized. It should be noted that a
match registers. When a match occurs the frame is collision should never occur after the BOF flag in a well
loaded into the GSC. Due to the CRC strip hardware, designed system, since the system slot time will likely
there is a 40 or 24 bit time delay following the BOF be . less than the preamble length. The occurrence of
until the first data byte is loaded into RFIFO if the 32 such a situation is normally due to a station on the link
or 16 bit CRC is chosen. If the end of frame is detected that is not adhering to proper CSMA/CD protocol or
before data is loaded into the receive FIFO, the receiver is not using the same timings as the rest of the network.
ignores that frame.
A collision occurring during the preamble or BOF flag
If the receiver detects a collision during reception in is the nonnal type of collision that is expected. When
CSMA/CD mode and if any bytes have been loaded this type of collision occurs the GSC automatically
into the receive FIFO, the RCABT flag is set. The GSC handles the retransmission attempts for as many as
hardware then halts reception and resets GREN. The eight tries. If on the eighth attempt a collision occurs,
user software needs to filter any collision fragment data the transmitter is disabled, although the jam and back-
which may have been received. If the collision occurred off are performed. If enabled, the CPU is then inter-
, prior to the data being loaded into RFIFO the CPU is rupted. The user software should then determine what
not notified and the receiver is left enabled. At the end , action to take. The possibilities range from just report-
of a reception the RDN bit is set and GREN is cleared. ing the error and aborting' transmission to reinitializing
In HABEN mode this causes an acknowledgement to the serial channel registers and attempt retransmission.
be transmitted if the frame did not have a broadcast or
8-39
inter HARDWARE DESCRIPTION OF THE 83C152
If less than eight attempts are desired TCDCNT can be All the stations monitor the link as long as that station
loaded with some value which will reduce the number is active, even if not attempting to transmit. This is to
of collisions possible before TCDCNT overflows. The ensure that each station always defers the minimum
value loaded should consist of all 1s as the least signifi- amount oftime before attempting a transmission and so
cant bits, e.g. 7, OFH, 3FH. A solid block of Is is sug- that addresses are recognized. However, the collision
gested because TCDCNT is used as a mask when gen- detect circuitry operates slightly differently.
erating the random slot number assignment. The
TCDCNT register operates by shifting the contents one In normal back-off mode, a transmitting station always
bit position to the left as each collision is detected. As monitors the link while transmitting. If a collision is
each shift occurs a 1 is loaded into the LSB. When detected one or more of the transmitting stations apply
tCDCNT overflows, GSC operation stops and the the jam signal and all transmitting stations enter the
CPU is notified by the setting of the TCDT bit which back-off algorithm. The receiving stations also cop.-
can flag an interrupt. stantly monitor for a collision but do not take part in
the resolution phase. This allows a station to try to
The amount of time that the GSC has before it must be transmit in the middle of a resolution period. This in
ready to retransmit after a collision is determined by turn mayor may not cause another collision. If the new
the mode which is selected. The mode is determined station trying to transmit on the link does so during an
MO (GMOD.5) and Ml (GMOD.6). If MO and Ml unused slot time then there will probably not be a colli-
equal 0,0 (normal backoff) then the minimum period sion. If trying to transmit during a used slot time, then
before retransmission will be either the interframe there will probably be a collision. The actions the re-
space or the backoff period, whichever is longer. If MO ceiver does take when detecting a collision is to just
and Ml equal 1,1 (alternate backoff) then the minimum stop receiving data if data has 110t been loaded into
period before retransmission will be the interframe RFIFO or to stop reception, clear receiver enable
space plus the backoff period. Both of these are shown (REN) and set the receiver abort flag (RCABT -
in Figure 3.4. Alternate backoff must be enabled if us- RSTAT.6).
ing deterministic resolution. If the GSC is not ready to
retransmit by the time its assigned slot becomes avail- If deterministic resolution is used, the transmitting sta-
able, the slot time is lost and the station must wait until tions go through pretty much the same process as in
the collision resolution time period has' passed. normal back-off, except that the slots are predeter-
mined. All the receivers go through the back-off algo-
Instead of waiting for the collision resolution to pass, .rithm and may only transmit during their assigned slot.
the transmission could be aborted. The decision to
abort is usually dependent on the number of stations on
the link and how many collisions have already oc- 3.6.4 SUCCESSFUL ENDING OF
curred. The number of collisions can be obtained by TRANSMISSIONS AND RECEPTIONS
examining the register, TCDCNT. The abort is normal-
In both CSMA/CD and SDLC modes, the TDN bit is
ly implemented by clearing TEN. The new transmis-
set and TEN cleared at the end of a successful trans-
sion begins by setting TEN and loading TFIFO. The mission. The end of the transmission occurs when the
minimum amount of time available to initiate a retrans-
TFIFO is empty and the last byte has been transmitted.
mission would be one interframe space period after the In CSMAlCD the user should clear the TCDCNT reg-
line is sensed as being idle.
ister after successful transmission.
As the nUfiibef of stations approach 256 the probability At the end of a successfui reception, me RDN bit is set
of a successful transmission decreases rapidly. If there
. and GREN is cleared. The end of reception occurs
are more than 256 stations involved in the collision
when the EOF flag is detected by the GSC hardware.
there would be nb resolution since at least two of the
stations will always have the same backoff interval se-
lected.
8-40
inter HARDWARE DESCRIPTION OF THE 83C152
3.7 Register Descriptions The length includes the two bit Begin Of Frame (BOP) .
flag in CSMA/CD but does not include the SDLC flag.
ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address In SDLC mode, the BOF is an SDLC flag, otherwise it
Match Registers 0,1,2,3 - Contains the address match is two consecutive ones. Zero length is not compatible
values which determines which data will be accepted as in CSMA/CD mode. The user software is responsible
valid. In 8 bit addressing mode, a match with any of the for setting or clearing these bits.
four registers will trigger acceptance. In 16 bit address-
ing mode a match with ADR1:ADRO or ADR3:ADR2 GMOD.3 (CT) - CRC Type - If set, 32 bit AUTODIN-
will be accepted. Addressing mode is determined in lI-32 is used. If cleared, 16 bit CRC-CCITT is used.
GMOD (AL). The user software is responsible for setting or clearing
this flag.
AMSKO,1 (OD5H, OE5H) - Address Match Mask 0,1 -
Identifies which bits in ADRO,1 are "don't care" bits. GMOD.4 (AL) - Address Length - If set, 16 bit ad-
Writing a one to a bit in AMSKO,1 masks out that dressing is used. If cleared, 8 bit addressing is used. In 8
corresponding bit in ADDRO,l. bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADR1, ADR2, ADR3).
BAUD (94H) - GSC Baud Rate Generator - Contains "Don't Care" bits may be masked in ADRO and ADRI
the value of the programmable baud rate. The data rate with AMSKO and AMSKI. In 16 bit mode, addresses
will equal (frequency of the oscillator)/«BAUD + 1) are matched against "ADR1:ADRO" or "ADR3:
X (8)). Writing to BAUD actually stores the value in a ADR2". Again, "Don't Care" bits in ADR1:ADRO
reload register. The reload register contents are copied can be masked in AMSK1:AMSKO. A received address
into the BAUD register when the Baud register decre- of all ones will always be recognized in any mode. The
ments to OOH. Reading BAUD yields the current timer user software is responsible for setting or clearing this
value. A read during GSC operation will give a value flag.
that may not be current because the timer could decre-
ment between the time it is read by the CPU and by the GMOD.5,6 (MO,Ml) - Mode Select - Two test modes,
time the value is loaded into its destination. an optional "alternate backoff" mode, or normal back-
off can be enabled with these two bits. The user soft-
BKOFF (OC4H) - BackoffTimer - The backofftimer is ware is responsible for setting or clearing the mode bits.
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the Ml MO Mode
CSMA/CD collision resolution algorithm. The user 0 0 Normal
software may read the timer but the value may be inval- 0 1 Raw Transmit
id. as the timer is clocked asynchronously to the CPU. 1 0 Raw Receive
Writing to OC4H will have no effect. 1 1 Alternate Backoff
GMOD(84H) In raw receive mode, the receiver operates as normal
7 6 5 4 3 2 o except that all the bytes following the BOF are loaded
I XTCLK I I MO I AL I CT I PL1
M1 PLO I PR I into the receive FIFO, including the CRC. The trans-
mitter operates as normal.
Figure 3.14. GMOD
In raw transmit. mode the transmit output is internally
GMOD.O (PR) - Protocol- If set, SDLC protocols with connected to the receiver input. The internal connec-
NRZI encoding and SDLC flags are used. If cleared, tion is not at the actual port pin, but inside the port
CSMA/CD link access with Manchester encoding is latch. All data transmitted is done without a preamble,
used. The user software is responsible for setting or flag or zero bit insertion, and without appending a
clearing this flag. CRC. The receiver operates as normal. Zero bit dele-
tion is performed.
GMOD.I,2 (PLO,I) - Preamble length
In alternate backoff mode the standard backoff process
PLl PLO LENGTH (BITS) is modified so the the backoff is delayed until the end of
o 0 0 the IFS. This should help to prevent collisions con-
o 1 8 stantly happening because the IFS time is usually larger
1 0 32 than the slot time.
1 1 64
8-41
HARDWARE DESCRIPTION OF THE 83C152
GMOD.7 (XTCLK) - External Transmit Clock - If set PCON(087H)
an external IX clock is used for the transmitter. If 76543210
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to P1.3
(T x C). The user software is responsible for setting or
clearing 'this flag. External receive clock is enabled by PCON contains bits for power control, LSC control,
setting PCON.3. DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCONA.
IFS (OA4H) - Interframe Spacing - Determines the
number of bit times separating transmitted frames in PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
CSMA/CD. A bit time is equal to I/baud rate. Only GFIEN to a I caused idle flags to be generated between
even interframe space periods can be used. The number transmitted frames in SDLC mode. SDLC idle flags
written into this register is divided by two and loaded in consist of 01111110 flags creating the sequence
the most significant seven bits. Complete interframe 01111110011111110 ...... 01l'1111 10. A possible side
space is obtained by counting this seven bit number effect of enabling GFIEN is that the maximum possible
down to zero twice. A user software read of this register latency from writing to TFIFO until the first bit is
will give a value where the seven most significant bits transmitted increased from approximately 2 bit-times
gives the current count value and the least significant to around 8 bit-times. GFIEN has no effect with
bit shows a one for the first count-down and a zero for CSMA/CD.
the second count. The value read may not be valid 'as
the timer is clocked in' periods not necessarily associat- PCON.3 (XRCLK) - GSC External Receive Clock En-
ed with the CPU read of IFS. Loading this register with able - Writing a I to XRCLK ,enables an external clock
zero results in 256 bit times. to be applied to pin 5 (Port IA). The external clock is
used to determine when bits are loaded into the receiv-
er.
PCONA (GAREN) - GSC Auxiliary Receiver Enable
Bit - This bit needs to be set to a 1 to enable the recep-
tion of back-to~back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared be-
Figure 3.15. MYSLOT tween two sequential frames intended for the same sta-
tion on the link. If GAREN contains a 0 then the re-
MYSLOT.O, I, 2, 3, 4, 5 -Slot Address - The six ad- ceiver will be disabled upon reception of the EOF and
dress bits choose 1 of 64 slot addresses. Address 63 has by the time user software' re-enables the receiver the
the highest priority and address 1 has the lowest. A first bit(s) may have already passed, in the case of back-
value of zero will prevent a station froni transmitting to-back frames. Setting GAREN to a 1, prevents the
during the collision resolution period by waiting until receiver from being disabled by the EOF but GREN
all the possible slot times have elapsed. The user soft- will be cleared and can be checked by user software to
ware normally initializes this address in the operating determine that an EOF has been received. GAREN has
software. no effect if the GSC is in CSMA/CDmode.
MYSLOT.6 (DCR) - Deterministic Collision Resolu- PRBS (OE4H) - Pseudo-Random Binary Sequence -
tion A hJOrithm - When set. the alternate collision reso- This register contains apselldo-random number to be
iuti~~-;;}gorithm is selected. Retriggering of the IFS on used in the CSMA/CD backoff algorithm. The number
reappearance of the carrier is also disabled. When using is generated by using a' feedback shift register clocked
this feature Alternate Backoff Mode must be selected by the CPU phase clocks. Writing all ones to the PRBS
and several other registers must be initialized. User will freeze the value at all ones. Writing any other value
. software must initialize TCDCNT with the maximum to it will restart the PRBS generator. The PRBS is ini-
number of slots that are most appropriate for a particu- tialized to all zero's during RESET. A read of location
lar application. The PRBS register must be set to all OE4H will not necessarily give the seed, used. in ,the
ones. This disables the PRBS by freezing it's contents at backoff algorithm because the PRBS counters are
OFFH. The backoff timer is used to count down the clocked by internal CPU phase clocks. This means the
number of slots based on the slot timer value setting the contents of the PRBS may have been altered between
period of one slot. The user software is responsible for the time when the seed was generated and before a
setting or clearing this flag. READ has been internally executed.
MYSLOT.7 (DCJ) - D.C. Jam - When set selects D.C.
type jam, when clear, selects A.C. type jam. The user
software is responsible for setting or clearing this flag.
8-42
HARDWARE DESCRIPTION OF THE 83C152
RFIFO (OF4H) - Receive FIFO - RFIFO is a 3 byte had been loaded into the receive FIFO in CSMA/CD
buffer that is loaded each time the GSC receiver has a mode. In SDLC mode, RCABT indicates that 7 consec-
byte of data. Associated with RFIFO is a pointer that is utive ones were detected prior to the end flag but after
automatically updated with each read of the FIFO. A data has been loaded into the receive FIFO. The status
read of RFIFO fetches the oldest data in the FIFO. of this flag is controlled by the GSC.
RSTAT (OESH) - Receive Status Register RSTAT.7 (OVR) - Overrun - If set, indicates that the
76543210 receive FIFO was full and new shift register data was
written into it. The setting of this flag is controlled by
IORIRCABTIAElcRCEIRDNIRFNEIGRENIHABENI the GSC and it is cleared by user software.
Figure 3.16. RSTAT
SLOTTM (OBH) - Slot Time - Determines the length of
RSTAT.O (HABEN) - Hardware Based Acknowledge the slot time used in CSMAlCD. A slot time equals
Enable - If set, enables the hardware based acknowl- (256 - SLOTTM) X (I / baud rate). A read of
edge feature. The user software is responsible for setting SLOTTM will give the value of the slot time timer but
or clearing this flag. the value may be invalid as the timer is clocked asyn-
chronously to the CPU. Loading SLOTTM with 0 re-
RSTAT.I (GREN) - Receiver Enable - When set, the sults in 256 bit times.
receiver is enabled to accept incoming frames. This also
clears RDN, CRCE, AE, RCABT, and the receive TCDCNT (OD4H) - Transmit Collision Detect Count -
FIFO. It is cleared by the receiver at the end of a recep- Contains the number of collisions that have occurred if
tion or if any errors occurred. The user software is re- probabilistic CSMAlCD is used. The user software
sponsible for setting this flag and the GSC or user soft- must clear this register before transmitting a new frame
ware can clear it. The status of GREN has no effect on so that the GSC backoff hardware can accurately dis-
whether the receiver detects a collision in CSMAlCD tinguish a new frame from a retransmit attempt.
mode as the receiver input circuitry always monitors
the receive pin. In deterministic backoff mode, TCDCNT is used to
hold the maximum number of slots.
RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The re- TFIFO (S5H) - GSC Transmit FIFO - TFIFO is a 3
ceive FIFO is a three byte buffer into which the receive byte buffer with an associated pointer that is automati-
data is loaded. A CPU read of the FIFO retrieves the cally updated for each write by user software. Writing a
oldest data and automatically updates the FIFO point- byte to TFIFO loads the data into the next available
ers. Setting GREN to a one will clear the receive FIFO. location in the transmit FIFO. Setting TEN clears the
The status of this flag is controlled by the GSC. It is transmit FIFO so the transmit FIFO should not be
cleared if user empties receive FIFO. written to prior to setting TEN. If TEN is already set
transmission begins as soon as data is written to TFI-
RSTAT.3 (RDN) - Receive Done - If set, indicates the FO.
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun TSTAT (ODS) - Transmit Status Register
error occurred. The status of this flag is controlled by 76543210
the GSC.
LNI I NOACK I UR I TCDT I TDN I TFNF I TEN I DMA I
RSTAT.4 (CRCE) - CRC Error - If set, indicates that a Figure 3.17. TSTAT
properly aligned frame was received with a mismatched
CRC. The status of this flag is controlled by the GSC. TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
RSTAT.5 (AE) - Alignment Error - If set, indicates GSC interrupts occur on TDN and RDN, and also en-
that the line went idle when the receiver shift register ables UR to become set. If cleared, indicates that the
was not full and the resulting CRC was bad in the GSC is operating in its normal mode and interrupts
CSMAlCD mode. If a correct CRC was valid. then AE occur on TFNF and RFNE. For more information On
is not set. In SDLC mode, AE indicates that a non- DMA servicing please refer to the DMA section on
byte-aligned flag was received. The status of this flag is DMA serial demand mode (4.2.2.3). The user software
controlled by the GSC. is responsible for setting or clearing this flag.
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data
8-43
HARDWARE DESCRIPTION, OF THE 83C152
TSTAT.l (TEN) - Transmit Enable - When set causes 3.8 Serial Backplane VS. Network
TDN,UR, TCDT, and NOACK flag to be ,reset and Environment
the TFIFO cleared. The transmitter will clear TEN af-
ter a successful transmission, a collision during the The C152 GSC port is intended to fulfill the needs of
data, CRC, or end flag. The user software is responsible both serial backplane environment and the serial com-
for setting but the GSC or user software may clear this munication network environment. The serial backplane
flag. If cleared during a transmission the GSC transmit is where typically, only processor to processor commu-
pin goes to a steady state high level. .This is the method nications take place within a self contained box. The
used to send an abort character in SDLC., Also DEN is' communication usually only encompasses those items
forced to a high level. The end of transmission occurs which are necessary to accomplish the dedicated task
whenever the TFIFO is emptied. for the box. In these types of applications there may not
be a need for line drivers as the distance between the
TSTAT.2 (TFNF) - Transmit FIFO not full - When transmitter and receiver is relatively short. The net-
set, indicates that new data may be written into the work environment; however, usually requires transmis-
transmit FIFO. The transmit FIFO is a three byte buff- sion of data over large distances and requires drivers
er that loads the transmit shift register with data. The and/or repeaters to ensure the data is received on both
status of this flag is controlled by the GSC. ends.
TSTAT.3 (TDN) - Transmit Done - When set, indi-
cates the successfu1.completion ofa frame transmission: 4.0 DMA Operation
If HABEN is set, TDN will not be set until ,the end of
the IFS following the, transmitted message, so that the The C152 contains DMA (Direct Memory Accessing)
acknowledge can be checked. If an acknowledge is ex- logic to peiform high speed data tran'sfers between any
pected and not received, TDN'is not set. An acknowl- two of
edge is not expected following a broadcast or multi-cast
packet. The status of this flag is controlled by the GSC. Internal Data RAM
Internal SFRs
TSTAT.4 (TCDT) - Transmit Collision Detect - If set, External Data RAM
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or If external ,RAM is involved, the Port 2 and Port 0 ~
ifthere are more than eight collisions. The status of this are used as the address/data bus, and RD and WR
flag is ~ontrolled by the GSC. signals are generated as required. '
TSTAT.5 (UR) - Underrun - If set, indicates that in Hardware is also implemented to generate a Hold Re-
DMA mode the last bit was shifted out of the transmit quest signal and await a Hold Acknowledge response
register and that the DMA byte count did not equal before commencing a DMA that involves external
zero. When an underrun occurs, the transmitter, halts RAM.
without sending the CRC or the end flag. The status of
this flag is controlled by the GSC. Alternatively, the Hold/Hold Acknowledge hardware
can be programmed to 'accept a Hold Request signal
TSTAT.6 (NOACK) - No Acknowledge - If set, indi- from an external device and generate a Hold Acknowl-
cates that no acknowledge was received fodhe previous edge signal in response, to indicate to the requesting
frame. Will be set only if HABEN is set and no ac- device that the C152 will not commence a DMA to or
knowledge is received prior to the end of the IFS. from external RAM while the Hold Request is active. ,
NOACK is not set following a broadcast or a multi-
cast packet. The status of this flag is controlled by the
GSC. ' 4.1 DMA with the 80C152
TSTAT. 7 (LNI) - Line tdle - If set, indicates' the re- The C152 contains two identical general purPose 8-bit
ceive line is idle. In SDLC protocol it is set if 15 consec- DMA channels with 16-bit addressability: DMAO and
utive 'ones are' received. In CSMA/CD protocol, line DMAI. DMA transfers can be executed by either chan-
idle is set if no transitio~s occ~r on GR X D for approx- nel independent of the other, but only by one channel at
imately 1.6 bit times after a r~uired transition. LNI is a time. During the time that a DMA transfer is being
cleared after a transition on GRXD.The status of this executed, program execution is suspended. A DMA
flag is controlledby the GSC. transfer takes one machine cycle (12 oscillator
8-44
intJ HARDWARE DESCRIPTION OF THE 83C152
DMA CHANNEL 0 DMA CHANNEL 1
DARHO I I DARlO
DESTINATION ADDRESS
I, .I DARH1 II DARL1
DESTINATION ADDRESS
I.
.I SARHO II
SOURCE ADDRESS
SARLO I. .I SARH1 I I
SOURCE ADDRESS
SARL1 I,
BCRHO II BCRlO I, BCRH1 II BCRL1 I.
BYTE COUNT BYTE COUNT
I DCONO I I DCON1 I
DMAO CONTROL DMA 1 CONTROL
PCON
'-'
"-- Two new bits In PCON control
Hold/Hold Acknowledge logic
270427-28
Figure 4.1. DMA Registers
periods) per byte transferred, except when the destina- Two other bits in DCONn specify the physical source
tion and source are both in External Data RAM. In of the data to be transferred. These are SAS (Source
that case the transfer takes two 'machine cycles per Address Space) and ISA (Increment Source Address).
byte. The term DMA Cycle will be used to mean the If SAS = 0, the source is in data memory extern;i1 to
transfer of a single data byte, whether it takes 1 or 2 the CIS2. If SAS = 1, the source is internal. If SAS =
machine cycles. 1 and ISA = 0, the internal source is an SFR. If SAS
= 1 and ISA = 1, the internal source is in the 256-byte
Associated with each channel are seven SFRs, shown in data RAM.
Figure 4.1. SARLn and SARHn holds the low and high
bytes of the' source address. Taken together they form a In any case, if ISA = 1, the source address is automati-
16-bit Source Address Register. DARLn and DARHn cally incremented after each byte transfer. If ISA = 0,
hold the low and high bytes of the destination address, it is not.
and together form the Destination Address Register.
BCRLn and BCRHn hold the low and high bytes of the The functions of these four control bits are summarized
number of bytes to be transferred, and together form below:
the Byte Count Register. DCONn contains control and
flag bits. DAS IDA Destination Auto-Increment
External RAM no
Two bits in DCONn are used to specify the physical
destination of the data transfer. These bits are DAS
°° °1 External RAM yes
(Destination Address Space) and IDA (Increment Des- 1 0 SFR no
tination Address). If DAS = 0, the destination is in 1 1 Internal RAM yes
data memory external to the C152. If DAS = 1, the SAS ISA Source Auto-Increment
destination is internal to the CIS2. If DAS·= 1 and
0 External RAM no
IDA = 0, the internal destination is a Special Function
Register (SFR). If DAS = 1 and IDA = 1, the inter-
nal destination is in the 256-byte data RAM.
0 °1 External RAM yes
1 0 SFR no
1 1 Internal RAM yes
In any case, if IDA = 1, the destination address is
automatically incremented after each byte transfer. If
IDA = 0, it is not.
8-45
HARDWARE DESCRIPTION OF THE 83C152
There are four modes in which the DMA channel can dress. On-chip hardware then clears the flag (RI, TI,
operate. These are selected by the bits DM and TM RFNE, or TFNF) that initiated the DMA, and decre-
(Demand Mode and Transfer Mode) in DCONn: ments BCRn. Note that since the flag that initiated the
DMA is cleared, it will not generate an interrupt unless
OM TM Operating Mode DMA servicing is held off or the byte count equals O.
0 0 Alternate Cycles Mode DMA servicing may be held off when alternate cycle is
0 1 being used or by the status of the HOLD/HLDA logic.
Burst Mode
In these situations the interrupt for the LSC may occur
1 0 Serial Port Demand Mode
before the DMA can clear the RI or TI flag. This is
1 1 External Demand Mode because the LSC is serviced according to the status of
RI and TI, whether or not the DMA channels are being
The operating modes are described below. used for the transferring of data. The GSC does not use
RFNE or TFNF flags when using the DMA channels
so these do not need to be disabled. When using the
4.1.1 ALTERNATE CYCLE MODE DMA channels to service the LSC it is recommended
that the interrupts (RI and TI) be disabled. If the dec-
In Alternate Cycles Mode the DMA is initiated by set-
remented BCRn is OOOOH, on-chip hardware then
ting the GO bit in DCONn. Following the instrnction
clears the GO bit and sets the DONE bit. The DONE
that set the GO bit, one more instruction is executed,
bit flags an interrupt.
and then the first data byte is transferred from the
source address to the destination address. Then another
instruction is executed, and then another byte of data is 4.1.4 EXTERNAL DEMAND MODE
transferred, and so on in this manner.
In External Demand Mode the DMA is initiated by
Each time a data byte is transferred, ,BCRn (Byte one of the External Interrupt pins, provided the GO bit
Count Register for DMA Channel n) is decremented. is set. INTO initiates a Channel 0 DMA, and INTI
When it reaches OOOOH, on-chip hardware clears the initiates a Channel 1 DMA.
GO bit and sets the DONE bit, and the DMA ceases.
The DONE bit flags an interrupt. If the external interrupt is configured to be transition-
activated, then each I-to-O transition at the interrupt
pin sets the corresponding external interrupt flag, and
4.1.2 BURST MODE generates one DMA Cycle. Then, BCRn is decrement-
ed. No more DMA Cycles take place until another
Burst Mode differs from Alternate Cycles mode only in
I-to-O transition is seen at the external interrupt pin. If
that once the data transfer has begun, program execu-
the decremented BCRn = OOOOH, on-chip hardware
tion is entirely suspended until BCRn reaches OOOOH,
clears the GO bit and sets the DONE bit. If the exter-
indicating that all data bytes that were to be transferred
nal interrupt is enabled, it will be serviced.
have been transferred. The interrupt control hardware
remains active during the DMA, so interrupt flags may
If the external interrupt is configured to be level-acti-
get set, but since program execution is suspended, the
vated, then DMA Cycles commence when the interrupt
interrupts will not be serviced while the DMA is in
pin is pulled low, and continue for as long as the pin is
progress.
held low and BCRn is not OOOOH. If BCRn reaches 0
while the interrupt pin is still low, the GO bit is cleared,
4.i.3 SERiAL FORi DEiviAND MOCE the DONE bit is set, and the DMA ceases. If the exter-
nal interrupt is enabled, it will be serviced.
In this mode-the DMA can be used to service the Local
Serial Channel (LSC) or the Global Serial Channel If the interrupt pin is pulled up before BCRn reaches
(GSC). - OOOOH, then the DMA ceases, but the GO bit is still 1
and the DONE bit is still O. An external interrupt is not
In Serial Port Demand Mode the DMA is initiated by generated in this case, since in level-activated mode,
any of the following conditiollS, if the GO bit is set: pulling the pin to a logical 1 clears the interrupt flag. If
Source Address = SBUF .AND. AI = 1 the interrupt pin is then pulled low again, DMA trans-
Destination Address = SBUF .AND. TI = 1 fers will continue from where they were previously
stopped.
Source Address = AFIFO .AND. AFNE = 1
Destination Address = TFIFO .AND. TFNF = 1 The timing for the DMA Cycle in the transition-acti-
vated mode, or for the first DMA Cycle in the level-ac-
Each time one of the above conditions is met, one tivated mode is as follows: If the I-to-O transition is
DMA Cycle is executed; that is, one data byte is trans-
ferred from the source address to the destination ad-
8-46
HARDWARE DESCRIPTION OF THE 83C152
detected before the final machine cycle of the instruc- and RD and/or WR signals are generated as needed, in
tion in progress, then the DMA commences as soon as the same manner as in the execution of a MOVX
the instruction in progress is completed. Otherwise, one @DPTR instruction.
more instruction will be executed before the DMA
starts. No instruction is executed during any DMA Cy-
cle. 4.3 Hold/Hold Acknowledge
Two operating modes of Hold/Hold Acknowledge log-
4.2 Timing Diagrams ic are available, and either or neither may be invoked
by software. In one mode, the C152 generates a Hold
Timing diagrams for single-byte DMA transfers are Request signal and awaits a Hold Acknowledge re-
shown.in Figures 4.2 through 4.5 for four kinds of sponse before commencing' a DMA that involves exter-
DMA Cycles: internal memory to internal memory, in- nal RAM. This is called the Requester Mode.
ternal memory to external memory, external memory
to internal memory, and external memory to external In the other mode, the C152 accepts a Hold Request
memory. In each case we assume the Cl52 is executing signal from an external device and generates a Hold
out of external program memory. If the C152 is execut- Acknowledge signal in response, to indicate to the re-
ing out of internal program memory, then PSEN is in- questing device that the C 152 will not commence a
active, and the Port 0 and Port 2 pins emit PO and P2 DMA to or from external RAM while the Hold Re-
SFR data. If External Data Memory is involved, the quest is active. This is called the Arbiter mode,
Port 0 and Port 2 pins are used as the address/data bus,
1~- - - - - - 1 2 osc. PERIODS -----""11
ALE ~ _ _ _ _ _ _ _ _ _ --,f\.,__ __
""iN'ST1--- - - - - - - - -- - - - - -
PO ...,;;;;;;.,J __________________________________ ___ _
FLOAT - - - - - - -- - - -- -"\iPcl'FLOA~INST
~
P2~~__________~p~2~sr_R________~__ -JX PCH
_ _ _ _ _ _ _ DMA CYCLE------~I. _ RESUME PROGRAM
- EXECUTION
270427-29
Figure 4.2. DMA Transfer from Internal Memory to Internal Memory
- - - - - - 1 2 osc. PERIODS------li
1+1
ALE~_ _ _ _ _ _ _ _ _ -'f\.'_.___
'--
PO INST ::1.< DARLn X DMA DATA OUT
P2~~____________~DA~R~Hn~____________JX~ __~PC~H~ ___
WR \1..._ _ _ _- - J1 ,
- - - - - - - D M A C Y C L E - - - - - - - . ! - RESUME PROGRAM
EXECUTION
270427-30
Figure 4.3. DMA Transfer from Internal Memory to External Memory
8-47.
HARDWARE DESCRIPTION OF THE 83C152
~I'-----12 osc. PERIOOS ------+j'1
ALE ----f\'--________~r_\......_ __
I'WlJ '---
P2 ~...._ _ _ _ _ _ _S_AR_H_n_ _ _ _ _ _ _'X PCH
\'-----~/
- - I . - - - - - - O M A CYCLE _ _ _ _ _ _ _ 1 RESUME PROGRAM
,- , - EXECUTION
270427-31
Figure 4.4. DMA Transfer from External Memory to Internal Melflory
,------12 osc. PERIODS ----+f"'~---12 osc. PERIODS - - - - 1
ALE
'-
P2~~_ _ _ _~SA...R...
Hn~_ _ _ _Jx~ _____..... . ~ R...
Hn~_ ___JX~ __...Pc...H___
\ ....------1/
\ .....-----...1/
f-I,----------OMA CyCLE------------I- RES~~E~~~g~RAM
270427-32
Figure 4.5. DMA Transfer from External Memory to External Memory
4.3.1 REQUESTER MODE 4.3.2 ARBITER MODE
The Requester Mode is selected by setting the control For DMAs that are to be driven by some device other
bit REQ, which resides in PCON. In that mode, when than the C152, a different version of the Hold/Hold
the C152 wants to do a DMA to External Daia Memo- Acknow"lcdgc protocol is available. In this version the j
ry, it first generates a Hold Request signal, HLD, and device which is to drive the DMA sends a Hold Re-
waits for a Hold Acknowledge signal, HLDA, before quest signal, HLD, to the C152. If the C152 is current-
. commencing the DMA operation. Note that program ly performing a DMA to or from External Data Memo-
execution continues while HLDA is awaited. The ry, it will complete this DMA before responding to the
DMA is not begun until a logical 0 is detected at the Hold Request. When the C152 responds to the Hold
HLDA pin. Then, once the DMA has begun, it goes to Request, it 'does so by activating a Hold Acknowledge
completion regardless of the logic level at HLDA. signal, HLDA. This indicates that the C152 will not
commence a new DMA to or from External Data
The protocol is activated only for DMAs (not for pro- Memory while HLD remains active.
gram fetches or MOVX operations), and only for
DMAs to or from External Data Memory. If the data Note that in the Arbiter Mode the C152 does not sus-
destination and source are both internal to the C152, pend program execution at all, even if it is executing
the HLD/HLDA protocol is not used. from external program memory. It does not surrender
use of its own bus.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate function of The Hold Request input, HLD, is at P1.5. The Hold
port pin 1>1.6. Acknowledge output, HLDA, is at P1.6. This
,8-48
inter HARDWARE DESCRIPTION OF THE 83C152
version of the Hold/Hold Acknowledge feature is se-
lected by setting the.control bit ARB in PCON.
The functions of the ARB and REQ bits in PCON,
ALE (ARB)
then, are IF ilLiiii =1
ALE (REO)
ARB REQ Hold/Hold Acknowledge Logic IF IlIJlA =0
0 0 Disabled
ALE
0 1 C152 generates HLD, detects HLDA (REO) -----...--J
1 0 C152 detects HLD, generates HLDA 270427-34
1 1 Invalid
Figure 4.7. ALE Switch Select
The ALE Switch logic can be implemented by a single
4.3.3 USING THE HOLD/HOLD ACKNOWLEDGE 74HCOO, as shown in Figure 4.7.
The HOLD/HOLDA logic only affects DMA opera-
tion with external RAM and doesn't affect other opera- Figure 4.8 shows the additional gating that is required
tions with external RAM, such as MOVX instruction. when one of the CPUs is executing from external
ROM. In this case the CPU has constant access to its
Figure 4.6 shows a system in which two 83C152s are own local bus, and accesses the global RAM only after
sharing a global RAM. In this system, both CPUs are gaining access to a global address/data bus.
executing from internal ROM. Neither CPU uses the
bus except to access the shared RAM, and such access- If the CPU is programmed to be a Requester, as shown
es are done only through DMA operations, not by in Figure 4.8, then when it wants to access the global
MOVX instructions. RAM it first activates HLD, and continues program
execution on its own local bus while awaiting an active
One CPU is programmed to be the Arbiter and the level at HLDA.
other, to be the Requester. The ALE Switch selects
which CPU's ALE signal will be directed to the address An active level at HLDA enables the local bus to the
latch. The Arbiter's ALE is selected if HLDA is high, global bus, and signals the !!:9uester to proceed with
its DMA. The Requester's RD signal, rather than its
and the Requester's ALE is selected if HLDA is low .
.. Vee
A l8Xl0kll
PO
83C152
ARB P2
.--
..- Viii 7
r- RD
ALE I - -
U •
§I-
HLD HLDA
r-v 3
7
3
~
~
ALE
HLD HLDA SWITCH
ALE
83C152
REa
I'- Viii PO
~ RD P2 l-
DATA
.P
LOW HIGH
, '------'
OE SHARED ADDR
WE RAM
270427-33
Figure 4.6. Two 83C152s Sharing External RAM
8-49
intJ HARDWARE DESCRIPTION OF THE 83C152
LOCAL BUS
ROM
PO \ r - - - ; - - ,
BOC152
REQ
P2
ViR PSEN
rrn ALE
SHARED BUS"
HLD HLDA
, ).- ...
\
\
\
,
, LOW
,
,
: ADDR~
I ,
~-~--~
I HIGH
,
,
I
, I
I
I
I
I
,,,
I
,
t-......-OE ,
WE ,'
\
... ~
I
THLDA T,
SYSTEM ARBITER
270427-35
Figure 4.8. Separation of Local and Global Busses
8-50
inter HARDWARE DESCRIPTION OF THE 83C152
WR signal, is used to control the direction of the trans- Figure 4.9 shows the three tasks to which the internal
ceiver. This is to ensure that the transceiver will not try bus of the CI52 can be dedicated. In this figure, In-
to drive the local bus before the DMA has actually struction Cycle means the complete execution of a sin-
begun. gle instruction, whether it takes 1,2 or 4 machine cy-
cles. DMA Cycle means the transfer of a single data
RD from the Requester is ~cally ANDed with RD byte from source to destination, whether it takes 1 or 2
from the Arbiter to activate OE to the RAM. WR from machine cycles. (It takes 2 machine cycles.jf the desti-
the Requester can normally be hard-wired to WR from nation and source are both external to the CI52.) On-
the Arbiter to activate WE to the RAM. chip arbitration logic determines which type of cycle is
executed, according to the. following rules.
4.4 DMA Arbitration If the HLD/HLDA logic is disabled (ARB = 0, REQ
= 0):
The DMA Arbitration described in this section is not • A write to any DMA address or control register is
arbitration between two devices wanting to access a always followed by an Instruction Cycle. If the next
shared RAM, but rather on-chip arbitration between instruction is a read or write to a DMA address or
the two DMA channels on the C152. control register, the DMA cycle is held off one more
instruction cycle.
The CI52 provides two DMA channels, either of which
may be called into operation at any time in response to • A DMAO Cycle is called for if GOO = 1 and any of
real time conditions in the application circuit. Howev- the following conditions are satisfied:
er, only one DMA channel can be serviced during a 1. Channel 0 Burst Mode is selected;
single DMA cycle. 2. Channel 0 is in SP Demand Mode. and a SP De-
mand flag is up (but see • *);
In the event that both DMA channels request service at
the same time, DMA Channel 0 takes precedence.
270427-36
Figure 4.9. Internal Bus Tasks
8-51
HARDWARE DESCRIPTION OF THE 83C152
3. Channel 0 is in External .Demand Mode and an IDA (Increment Destination Address) If IDA = 1, the
External Demand flag is up; destination address' is automatically incremented after
4. Channel 0 is ·in Alternate Cycles Mode and Chan- each byte transfer. IfiDA =0, it is not..
nel 1 isn't, and the previous cycle was not a DMA
Cycle; SAS specifies the Source Address Space. If SAS = 0,
the source is in External Data Memory. If SAS = 1
5. Channel 0 and Channell are both in Alternate and ISA = 0, the source is an SFR. If SAS = 1 and
Cycles Mode, and the previous cycle was not a ISA = 1, the source is Internal Data RAM.
DMA Cycle, and the previous DMA Cycle was
not a DMAO cycle. ' ISA (Increment Source Address) If ISA = 1, the
• A DMAI Cycle is called for if GOI = 1 and no source address is automatically incremented after each
condition for a DMAO Cycle is satisfied, and any of byte transfer. If ISA.= 0, it is not.
the following conditions are satisfied:
1. Channel 1 Burst Mode is selected; DM (Demand Mode) If DM = 1, the DMA Channel
operates in Demand Mode. .In Demand Mode the
2~ Channel 1 is in SP Demand Mode and a SP De- DMA is initiated either by an external signal or by a
mand flag is up (but see "*); Serial Port flag, depending on the value of the TM bit.
3. Channel 1 is in External Dem~nd Mode and an If DM = 0, the DMA is requested by setting the GO
External Demand flag is up; bit in software.
4. Channel 1 is in Alternate Cycles Mode and Chan-
nel 0 isn't, and the previous cyCle was not a DMA TM (Transfer'Mode) If DM = 1 then TM selects
Cycle; whether a DMA is initiated by an external signal (TM
= I) or by a Serial Port flag (TM = 0). If DM = 0
5. Channel 1 and Channel 0 are both in Alternate then TM selects whether the data transfers are to be in
, Cycles Mode, and the previous cycle was not a bursts (TM = 1) or in alte~ate cycles (TM = 0).
DMA Cycle, and the previous DMA Cycle was
not a DMAI cycle. DONE indicates the completion of a DMA operation
"If a DMA Cycle is not called for, then an Instruc- and flags an interrupt. It is set to 1 by on-chip hardware
tion Cycle is executed. when BeRn = 0, and is cleared to 0 by on-chip hard-
*. A Special Case: Because of internal timing conflicts, ware when the interrupt is vectored to. It can also be
set or cleared by software.
a SP Demand Mode DMA Cycle in which the desti-
nation address is TFIFO will not be generated un-
less the previous cycle was an Instruction Cycle. GO is the enable bit for the DMA Channel itself. The
DMA Channel is inactive if GO = O.
Note that any time conditions are satisfied for a DMAO PCON I SMOD I ARB I REQ I GAREN I XRCLK I GFIEN I PDN IIDL I
Cycle, the DMAO Cycle will be executed, even if the
DMAI Channel is active. That is not to say a DMAI ARB enables the DMA logic to detect HLD and gener-
Cycle will be interrupted once it has begun. However, ate HLDA. After it has activated HLDA, the CI52 will
once a cycle has begun, be it,an'Instruction Cycle or a not begin a new DMA to or from External Data Mem-
DMA Cycle, it will be completed without interruption. ory as long as HLD is seen to be active. This logic is
disabled when ARB = 0, and enabled when ARB = 1.
If the HLD/HLDA logic is not disabled (either ARB
= i or REQ = i), then the HoidiHoid Acknowiedge
REQ enables the DMA logic to generate HLD and de-
protocol will also be observed, as previously described, tect HLDA before performing a DMA to or from Ex-
for DMAs to or from external RAM. ternal Data Memory. After it has activated HLD, the
C152 will not begin the DMA until HLDA is seen to be
active. This logic is disabled when REQ = 0, and en-
4.5 Summary of DMA Control Bits abled when REQ = 1.
DCONn I DAS I IDA I SAS liSA I OM I TM I DONE I GO I
DAS specifies the Destination Address Space. If DAS 5.0 GLOSSARY
= 0, the destination is in External Data Memory: If
DAS = 1 and IDA = 0, the destination is a Special ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Function Register (SFR). If DAS = 1 and IDA = 1, Match Registers 0,1,2,3 - The contents of these SFRs
the destination is in Internal Data RAM. are compared against the address bits from the serial
8-52
inter HARDWARE DESCRIPTION OF THE 83C152
data on the GSC. If the address matches the SFR, then DCI - D.C. Jam, see MYSLOT.
the ClS2 accepts that frame. If in 8 bit addressing
mode, a match with any of the four registers will trigger DCONO/I (092H,093H)
acceptance. In 16 bit addressing mode, a match with 76543210
ADRl:ADRO or ADR3:ADR2 will be accepted. Ad-
dress length is determined, by GMOD, (AL).
AE - Alignment Error, see RSTAT. The DCON registers control the operation of the DMA
channels by determining the source of data to be trans-
AL - Address Length, see GMOD. ferred, the destination of the data to be transfer, and the
various modes of operation.
AMSKO,l (ODSH, OESH) - Address Match Mask 0,1 -
Identifies which bits in ADRO,l are "don't care" bits. DCON.O (GO) - Enables DMA Transfer - When set it
Setting a bit to 1 in AMSKO,l identifies the corre- enables a DMA channel. If block mode is set then
sponding bit in ADDRO,1 as not to be examined when DMA transfer starts as soon as possible under CPU
comparing addresses. control. If demand mode is set then DMA transfer
starts when a demand is asserted and recognized.
BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will DCON.l (DONE) - DMA Transfer is Complete -
equal (fosc)/«BAUD+ 1) X 8). When set the DMA transfer is complete. It is set when
BCR equals 0 and is automatically reset when the
BCRLO,l (OE2H, OF2H) - Byte Count Register Low DMA vectors to its interrupt routine. If DMA inter-
0,1 - Contains the lower byte of the byte count. Used rupt is disabled and the user software executes a jump
during DMA transfers to identify to the DMA chan- on the DONE bit, then the user software must also
nels when the transfer is complete. . reset the done bit. If DONE is not set, then the DMA
transfer is not complete.
BCRHO,l (OE3H, OF3H) - Byte Count Register High
0,1 - Contains the upper byte of the byte. count. DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfers are used if the DMA channel is config-
BKOFF (OC4H) - Backoff Timer - The backoff timer is ured in block mode or external interrupts are used to
an eight bit count-down timer with a clock period equal initiate a transfer if in Demand Mode. When TM is
to one slot time. The backoff time is used in the cleared, Alternate Cycle Transfers are used if DMA is
CSMA/CD collision resolution algorithm. in the Block Mode, or Local Serial channel/GSC inter-
rupts are used to initiate a transfer if in Demand Mode.
BOF - Beginning of Frame flag -. A term commonly
used when dealing with packetized data. Signifies the DCON.3 (DM) - DMA Channel Mode - When set,
beginning of a frame. Demand Mode is used and when cleared, Block Mode
is used.
CRC - Cyclic Redundancy Check - An error checking
routine that mathematically manipulates a value depen- DCON.4 (ISA) - Increment Source Address - When
dent on the incoming data. The purpose is to identify set, the source address registers are automatically incre-
when a frame has been received in error. mented during each transfer. When cleared, the source
address registers are not incremented.
CRCE - CRC Error, see RSTAT.
DCON.S (SAS) - Source Address Space - When set, the
CSMA/CD - Stands for Carrier Sense, Multiple Ac- source of data for the DMA transfers is internal data
cess, with Collision Detection. memory if autoincrement is also set. If autoincrement is
not set but SAS is, then the source for data will be one
CT - CRC Type, see GMOD. of the Special Function Registers. When SAS is cleared,
the source for data is external data memory.
DARLO/l (OC2H, OD2H) - Destination Address Reg-
ister Low 0/1 - Contains the lower byte of the destina- DCON.6 (IDA) -' Increment Destination Address
tions' address when performing DMA transfers. Space - When set, destination address registers are in-
cremented once after each byte is transferred. When
DARHO/I (OC3H, OD3H) - Destination Address Reg- cleared, the destination address registers are not auto-
ister Low 0/1 - Contains the upper byte of the destina- matically incremented.
tions' address when performing DMA transfers.
DAS - Destination Address Space, see DCON.
8-53
inter HARDWARE DESCRIPTION OF THE 83C152
DCON.7 (DAS) - Destination Address Space - When GMOD(84H)
set, destination of data to be transferred is internal data 7 6 5 4 3 210
memory if autoincrement mode is also set. If autoincre-
ment is not set the destinationwill be one of the Special
Function Registers. When DAS is cleared then the des-
IXTCLK I M1 I MO I AL I CT I PL1 I PLO I PR I
tination is external data memory. The bits in this SFR, perform most of the configuration
on the type of data transfers to be used with the GSC.
DCR - Deterministic Resolution, see MYSLOT. Determines the mode, address length, preamble length,
protocol select, and enables the external clocking of the
DEN - An alternate function of one of the port I pins transmit data.
(p1.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always GMOD.O (PR) - Protocol- If set, SDLC protocols with
active when using the GSC and if P1.2 is programmed NRZI encoding, zero bit insertion, and SDLC flags are
to a 1. used. If cleared, CSMAlCD link access with Manches-
ter encoding is used.
DM - DMA Mode, see DCONO.
GMOD.l,2 (pLO, 1) - Preamble length
DMA - Direct Memory Access mode, see TSTAT.
PLI PLO LENGTH (BITS)
DONE - DMA done bit, see DCONO. 000
o 1 8
DPH -Data Pointer High, an SFR that contains the 1 0 32
high order byte of a general purpose pointer called the 1 1 64
data pointer (DPTR).
The length includes the two bit Begin Of frame (BOF)
DPL - Data Pointer Low, an SFR that contains the low flag in CSMAlCD but does not include the SDLC flag.
order bytc of the data pointer. In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
EDMAO ~ Enable DMA Channel 0 interriJpt, see in CSMAlCD mode.
IENl.
GMOD.3 (CT) - CRC Type - If set, 32-bit AUTODIN-
EDMAI - Enable DMA Channel 1 interrupt, see 11-32 is used. If cleared, 16-bit CRC-CCITT is used.
IENl.
GMOD.4 (AL) - Address Length - If set, 16-bit ad-
EGSRE - Enable GSC Receive Error interrupt, see dressing is used. If cleared, 8-bit addressing is used. In
IENl. 8-bit mode, a match with any of the 4 address registers
will allow that frame to be accepted (ADRO, ADRl,
EGSRV - Enable GSC Receive Valid interrupt, see ADR2, ADR3). "Don't Care" bits may be masked in
IENl. .
ADRO and ADRI with AMSKO and AMSKl. In 16-
bit mode, addresses are matched against
EGSTE - Enable GSC Transmit Error interrupt, see "ADRl:ADRO" or "ADR3:ADR2". Again, "Don't
IENl. Care" bits in ADRl:ADRO can be masked in
AMSKi:AMSKO. A received address of an ones win
EGSTV - Enable GSC Transmit Valid internipt, see always be recognizCd in any mode.
IENl.
GMOD.5, 6 (MO,Ml) -Mode Select- Two test modes,
EOF - A general term used in serial communications. an optional "alternate backofl" mode, or normal back-
EOF stands for End Of Frame and signifies when the off can be enabled with these two bits.
last bits of data are transmitted when using packetized
data. Ml MO Mode
o ·0 Normal
ES - Enable LSC Service interrupt, see IE. o 1 Raw Transmit
1 0 Raw Receive
ETO - Enable Timer 0 interrupt, see IE. 1 1 Alternate Backoff
ETl - Enable Timer 1 interrupt, see IE. GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
EXO - Enable External interrupt 0, see IE. cleared the internal baud rate generator provides the
EXI - Enable External interrupt 1, see IE.
8-54
inter HARDWARE DESCRIPTION OF THE 83C152
transmit clock. The input clock is applied to Pl.3 IE.2 (EXl) - Enables the external interrupt INTI on
(TxC). The user software is responsible for setting or P3.3.
clearing this flag. External receive clock is enabled by
setting PCON.3. IB.3 (ETI) - Enables the Timer 1 interrupt.
GO - DMA Go bit, see DCONO. IE.4 (ES) - Enables the Local Serial Channel interrupt.
GRxD - GSC Receive Data input, an alternate function IE.7 (EA) - The global interrupt enable bit. This bit
of one of the port I pins (P 1.0). This pin is used as the must be set to a 1 for any other interrupt to be enabled.
receive input for the GSC. PLO must be programmed
to a 1 for this function to operate. IENl - (OCSH)
76 5 4 3 2 1 0
GSC - Global Serial Channel - A high-level, multi-pro-
tocol, serial communication controller added to the IIIEGSTEIEDMA11EGSTVIEDMAOIEGSREIEGSRVI
SOC5lBH core to accomplish high-speed transfers of
packetized serial data. Interrupt enable register for DMA and GSC interrupts.
A 1 in any bit position enables that interrupt.
GTxD - GSC Transmit Data output, an alternate func-
tion of one of the port I pins (P 1.1). This pin is used as IENI.O (EGSRV) - Enables the GSC valid receive in-
the transmit output for the GSC. Pl.l must be pro- terrupt.
grammed to a I for this function to operate.
IEN1.1 (EGSRE) - Enables the GSC receive error in-
HBAEN - Hardware Based Acknowledge Enable, see terrupt.
RSTAT.
IENl.2 (EDMAO) - Enables the DMA done interrupt
HLDA - Hold Acknowledge, an alternate function of for Channel O.
one of the port 1 pins (Pl.6). This pin is used to per-
form the "HOLD ACKNOWLEDGE" function for IEN1.3 (EGSTV) - Enables the GSC valid transmit in-
DMA transfers. HLDA can be an input or an output, terrupt.
depending on the configuration of the DMA channels.
PI.6 must be programmed to a 1 for this function to IENl.4 (EDMAl) - Enables the DMA done interrupt
operate. for Channel 1.
HOLD - Hold, an alternate function of one of the port IEN1.5 (EGSTE) - Enables the GSC transmit error in-
1 pins (P1.5). This pin is used to perform the "HOLD" terrupt
function for DMA transfers. HOLD can be an input or
an output, depending on the configuration of the DMA IFS - (OA4H) Interframe Space, determines the number
channels. Pl.5 must be programmed to a 1 for this of bit tiflles separating transmitted frames.
function to operate.
IP (OBSH)
IDA - Increment Destination Address, see DCONO.
7 6 5 4 3 2 1 0
IE (OASH) I PS I PT1 I PX1 PTO PXO
765432 0
EA I ES I ET1 I EX1 I ETO EXO Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IE. A 1 assigns
the corresponding interrupt in IE a higher interrupt
Interrupt Enable SFR, used to individually enable the than an interrupt with a corresponding O.
Timer and Local Serial Channel interrupts. Also con~
tains the global enable bit which must be set to a 1 to IP.O (PXO) - Assigns the priority of external interrupt,
enable any interrupt to be automatically recoguized by INTO. .
the CPU.
IP.1 (PTO) - Assigns the priority of Timer 0 interrupt,
IE.O (EXO) - Enables the external interrupt INTO on TO.
P3.2.
IE.l (ETO) - Enables the Timer 0 interrupt.
inter HARDWARE DESCRIPTION OF THE 83C152
IP.2 (PXI)- Assigns the priority of external interrupt, Determines which type of Jam is used, which backoff
INTl. algorithm is used, and the DCR slot address for the
GSC. .
IP.3 (PTl) - Assigns the priority of Timer I interrupt,
Tl. MYSLOT.O,I,2,3,4,5 (SAO,I,2,3,4,5) - These bits deter-
mine which slot address is assigned to the CI52 when
IP.4 (PS) - Assigns the priority of the LSC interrupt, using deterministic backoff during CSMA/CD opera-
SBUF. tions on the GSC. Maximum slots available is 63. An
address of OOH prevents that station from participating
IPNI - (OFSH) in the backoff process.
76 5 4 3 2 1 0
I I I PGSTE I PDMA1 I PGSTV I PDMAO I PGSRE I PGSRV I MYSLOT.6 (DCR) - Determines which collision reso-
lution algorithm is used. If set to a I, then the determi-
Allows the user software two levels of prioritization to nistic backoff is used. If cleared, then a random slot
be assigned to each of the interrupts in IENl. A I as- assignment is used.
signs the corresponding interrupt in IENI a higher in-
terrupt than an interrupt with a corresponding O. MYSLOT.7 (DCJ) - Determines the type of Jam used
during CSMA/CD operation when a collision occurs.
IPNl.O (PGSRV) - Assigns the priority ofGSC receive If set to a I then a low D.C. level is used as the jam
valid interrupt. signal. If cleared, then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
IPNl.l (PGSRE) - Assigns the priority of GSC error CRC length.
receive iriterrupt.
NOACK - No Acknowledgment error bit, see TSTAT.
IPN1.2 (PDMAO) - Assigns the priority of DMA done
interrupt for Channel O. NRZI - Non-Return to Zero inverted, a type of data
encoding where a 0 is represented by a change in the
IPNl.3 (pGSTV) - Assigns the priority of GSC trans- level of the serial link. A I is represented by no change.
mit viilid interrupt.
OVR - Overrun error bit, see RSTAT.
IPNl.4 (PDMAI) - Assigns the priority ofDMA done
interrupt for Channel 1. PR - Protocol select bit, see GMOD. PCON (S7H)
76543210
IPNI.5 (pGSTE) - Assigns the priority of GSC trans-
mit error interrupt. ISMoolARSIREOIGARENIXRCLKIGFIENlpollOLI
ISA - Increment Source Address, see DCONO. PCON.O (IDL) -Idle bit, used to place the CI52 into
the idle power saving mode.
LNI - Line Idle, see TSTAT.
PCON.I (PD) - Power Down bit, used to place the
LSC - Local Serial Channel - The as¥nchronous serial CI52 into the power down power saving mode.
port found onL'__
__ .l __
0_ ~_:' _ _
MCS-51
all __ devices. Uses start/stop bits
1._ 1 L __ ... _ _ ... _ ...: __ _
i1UU t,;UU UUUMCJ UJUY 1 UyLC ilL i1 LlIUt:. FCON.2 (GFIEN) - GSC Fiag Idie Enabie bit, when
set, enables idle flags (01111110) to be generated be-
MO - One of two GSC mode bits, see TMOD. tween transmitted frames in SDLC mode.
MI - One of two GSC mode bits, see TMOD PCON.3 (XRCLK) - External.Receive Clock bit, used
to enable an external clock to be used for only the re-
MYSLOT - (OF5H) ceiver portion of the GSC.
76543210
PCON.4 (GAREN) - GSC Auxiliary Receive Enable
bit, used to enable the GSC to receive back-to-back
SDLC frames. This bit has no effect in CSMA/CD
mode.
8-56
HARDWARE DESCRIPTION OF THE 83C152
PCON.5 (REQ) - Requester mode bit, set to a I when RFIFO - (F4H) RFIFO is a 3-byte FIFO that contains
CI52 is to be operated as the requester station during the receive data from the GSC.
DMA transfers.
RSTAT (OE8H) - Receive Status Register
PCON.6 (ARB) - Arbiter mode bit, set to a I when 76543210
CI52 is to be operated as the arbiter during DMA
transfers.
PCON.7 (SMOD) - LSC mode bit, used to double the RSTAT.O (HBAEN) - Hardware Based Acknowledge
baud rate on the LSC. Enable - If set, enables the hardware based acknowl-
edge feature.
PDMAO - Priority bit for DMA Channel 0 interrupt,
see IPNl. ' RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. This also
PDMAI - Priority bit for DMA Channel I interrupt, clears RDN, CRCE, AE, RCABT and the receive
see IPNl. FIFO. It is cleared by the receiver at the end of a recep-
tion or if any errors occurred: The status of GREN has
PGSRE - Priority bit for GSC Receive Error interrupt, no effect on whether the receiver detects a collision in
see IPNl. CSMA/CD mode as the receiver input circuitry always
monitors the receive pin.
PGSRV - Priority bit for GSC Receive Valid interrupt,
see IPNl. RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The re-
PGSTE - Priority bit for GSC Transmit Error inter- ceive FIFO is a three byte buffer into which the receive
rupt, see IPNl. data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO point-
PGSTV - Priority bit for GSC Transmit Valid inter- ers. Setting GREN t9 a one will clear the receive FIFO.
rupt, see IPNl. The status of this flag is controlled by the GSC. This bit
is cleared if user S/W empties receive FIFO.
PLO - One of two bits that determines the Preamble
Length, see GMOD. RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
PLI - One of two bits that determines the Preamble be set if a CRC, alignment, abort, or FIFO overrun
Length, see GMOD. error occurred.
PRBS - (OE4H) Pseudo-Random Binary Sequence, gen- RSTATA (CRCE) - CRC Error - Ifset, indicates that a
erates the pseudo-random number to be used in properly aligned frame was received with a mismatched
CSMA/CD backoff algorithms. CRC.
PS - Priority bit for the LSC service interrupt, see IP. RSTAT.5 (AE) - Alignment Error - If set, indicates
that the line went idle when the receiver shift register
PTO - Priority bit for Timer 0 interrupt, see IP. was not full and the resulting CRC was bad in the
CSMA/CD mode. If a correct CRC was valid then AE
PTl - Priority bit for Timer I interrupt, see IP. is not set. In SDLC mode, AE indicates that a non-
byte-aligned flag was received.
PXO - Priority bit for External interrupt 0, see IP.
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
PXI - Priority bit for External interrupt I, see IP. - If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD
RCABT - GSC Receiver Abort error bit, see RSTAT. mode. In SDLC mode, RCABT indicates that 7 consec-
utive ones were detected prior to the end flag but after
RDN - GSC Receiver Done bit, see RSTAT. data has been loaded into the receive FIFO.
GREN - GSC Receiver Enable bit, see RSTAT. RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
RFNE - GSC Receive FIFO Not Empty bit, see written into it. It is cleared by user S/W.
RSTAT.
RI - LSC Receive Interrupt bit, see SCON.
8-57
inter HARDWARE DESCRIPTION OF THE 83C152
SARHO (OA3H) - Source Address Register High 0, SP (OSIH) - Stack Pointer, an eight bit pointer register
contains the high byte of the source address for DMA used during a PUSH, POP, CALL, RET, or RETI.
Channel O.
TCDCNT - (OD4H) Contains the number of collisions
SARHI (OB3H) - Source Address Register High I, in the current frame if using probabilistic CSMA/CD
contains the high byte of the source address for DMA and contains the maximum number of slots in the de-
Channell. terministic mode.
SARLO (OA2H) - Source Address Register Low 0, con- TCDT - Transmit Collision Detect, see TSTAT.
tains the low. byte of the source address for DMA
Channel O. TCON(OSSH)
76543210
SARLI (OB2H) - Source Address Register Low I, con-
tains the low byte of the source address for DMA I TF1 I TA1 I TFO I TAO IIE1 IIT1 I lEO liTO I
Channell.
TCON.O (ITO) - Interrupt 0 mode control bit.
SAS - Source Address Space bit, see DCONO.
TCON.I (lEO) - External interrupt 0 edge flag.
SBUF (099H) - Serial Buffer, both the receive and
transmit SFR location for the LSC. TCON.2 (IT!) - Interrupt I mode control bit.
SCON(09SH) TCON.3 (lEI) - External interrupt I edge flag.
76543210
TCON.4 (TRO) - Timer 0 run controi bit.
I SMO I SM1 15M2 I AENI TB8 I AB8 I TI I AI I
CON.5 (TFO) - Timer 0 overflow flag.
SCON.O (RI) - Receive Interrupt flag.
TCON.6 (TRI) - Timer I run control bit.
SCON.I (TI) - Transmit Interrupt flag.
TCON.7 (TFI) - Timer I overflow flag.
SCON.2 (RBS) - Receive Bit S, contains the ninth bit
that was received in Modes 2 and 3 or the stop bit in TDN.- Transmit Done flag, see TSTAT.
Mode I if SM20. Not used in Mode O.
TEN - Transmit Enable bit, see TSTAT.
SCON.3 (TBS) - Transmit Bit S, the ninth bit to be
transmitted in Modes 2 and 3. . TFNF - Transmit FIFO Not Full flag, see TSTAT.
SCON.4 (REN) - Receiver Enable, enables reception TFIFO - (S5H) TFIFO is a 3-byte FIFO that contains
for the LSC. the transmission data for the GSC.
SCON.5 (SM2) - Enables the multiprocessor communi- THO (OSCH) - Timer 0 High byte, contains the high
cation feature in Modes 2 and 3 for the LSC. byte for timer/counter O.
ScON.6 (SMI) - LSC mode specifier. THI (OSDH) - Timer I High byte, contains the high
byte for timer/counter 1. .
SCON.7 (SM2) - LSC mode specifier.
TI - Transmit Interrupt, see SCON.
SDLC - Stands for Synchronous Data Link Communi-
cation and is a protocol developed by IBM. TLO (OSAH) - Timer 0 Low byte, coptains the low byte
for timer/counter O.
SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD. TLI (OSBH) - Timer I Low byte, contains the low byte
for timerlCounter 1.
TM - Transfer Mode, see, DCONO.
8-58
inter HARDWARE DESCRIPTION OFTHE 83C152
TMOD(OS9H) TSTAT.2 (TFNF) - Transmit FIFO not full - When
76543210 set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte butT-
IGATE ICIT I M1 I MO I GATE I CIT I M1 I MO I er that loads the transmit shift register with data.
TMOD.O (MO) - Mode selector bit for Timer O. TSTAT.3 (TDN) - Transmit Done - When set, indi-
cates the successful completion of a frame ttansmission.
TMOD.l (Ml) - Mode selector bit for Timer O. If HBAEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
TMOD.2 (CIf) - Timer/Counter selector bit for acknowledge can be checked. If an acknowledge is ex-
TimerO. pected and not received, TDN is not set. An acknowl-
edge is not expected following a broadcast or multi-cast
TMOD.3 (GATE) - Gating Mode bit for Timer O. packet.
TMOD.4 (MO) - Mode selector bit for Timer 1. TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
TMOD.5 (Ml) - Mode selector bit for Timer 1. It is set if a collision occurs during the data or CRC or
if there are more than eight collisions.
TMOD.6 (C/T) - Timer/Counter selector bit for
Timer L TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
TMOD.7 (GATE) - Gating Mode bit for Timer 1. register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter halts
TSTAT (ODS) - Transmit Status Register without sending the CRC or the end flag.
7 6 5 4 32 1 0 TSTAT.6 (NOACK) - No Acknowledge - If set, indi-
ILNII NOACK I UR I TCOT ITON I TFNF I TEN IOMA I cates that no acknowledge was received for the previous
frame. Will be set only if HBAEN is set and no ac-
knowledge is received prior to the end of the IFS.
TSTAT.O (DMA) - DMA Select - If set, indicates that NOACK is not set following a broadcast or a multi-
'DMA channels are used to service the GSC FIFO's and cast packet.
GSC interrupts occur on TDN and RDN, and also en-
ables UR to become set. If cleared, indicates that the TSTAT.7 (LNI) - Line Idle - If set, indicates the re-
GSC is operating in it normal mode and interrupts oc- ceive line is idle. In SDLC protocol it is set if 15 consec-
cur on TFNE and RFNE.For more information on utive ones are received. In CSMA/CD protocol, line
DMA servicing please refer to the DMA section on idle is set if no transitions occur on GR X D for 1.6 bit
DMA serial demand mode (4.2.2.3). times after a required transition. LNI is cleared after a
transition on GRXD.
TSTAT.l (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flags to be reset and TxC - External Clock input for GSC transmitter.
the TFIFO cleared. The transmitter will clear TEN af-
ter a successful transmission, a collision during the UR - Underrun flag, see TSTAT.
data, CRC, or end flag. If cleared during a transmission
the GSC transmit pin goes to a steady state high level. XRCLK - External GSC Receive Clock Enable bit, see
This is the method used to send an abort character in· peON.
SDLC. Also DEN is forced to a high level. The end of
transmission is occurs whenever the TFIFO is emptied. XTCLK - External GSC Transmit Clock Enable bit,
seeGMOD.
8-59
MCS® . . 51 Programmer's Guide 9
and Instruction Set
MCS®-S1 PROGRAMMER'S GUIDE
AND INSTRUCTION SET
The information presented in this chapter is collected from the previous MCS®-51 chapters of this book. The
material has been selected and rearranged to form a quick and convenient reference for the programmers of the
MCS-51. This guide pertains specifically to the 8051, 8052 and 80C51.
The following list should make it easier to find a subject in this chapter.
Memory Organization
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-2
Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3
Direct and Indirect Address Area ........................................................ 9-5
Special Function Registers ............... ................................................. 9-7
Contents of SFRs after Power-On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-8
SFR Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-9
Program Status Word (PSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-10
Power Control Register (PCON) . . :. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 9-10
Interrupts. . .. .. . .. .. .. . ... .. . . .. .. . .. .. .. . . . . . . . .. . ... .. . . .. .. .. .. . .. .. . . . .. .. .. ... . . . ... 9-11
Interrupt Enable Register (IE) ............................................................. : 9-11
Assigning Priority Level .......................... "......................................... 9-12
Interrupt Priority Register . ..................................................... , .. ... . . . . .. 9-12
Timer/Counter Control Register (TCON) ................................................... 9-13
Timer/Counter Mode Control Register {TMOD} ............................................. 9-13
Timer Set-Up . ....................... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-14
Timer/Counter 0 .............................................. ...... ; ................... 9-14
Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
Timer/Counter 2 Control Register (T2CON). . . ... .. . . .. .. .. .. .. . . . . .. .. . .. .. . .. .. .. ... ...... 9-16
Timer/Counter 2 Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17
Serial Port Control Register. . . . . . .. .... . . . . . . .. .. .. . . .. .. .. .. .. . . .. . . . .... . .. .. . . ... ... ... 9-18
Serial Port Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
Generating Baud Rates ................................................................... 9-19
MCS-51 Instruction Set . ...... "................ ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-20
Instruction Definitions .................................................................... 9-24
9-1
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for Program Memory and Data Memory. The Program Memory can be up to
64K bytes long. The lower 4K (8K for the 8052) may reside on-chip.
Figure I shows a map of the 8051 program memory, and Figure 2 shows a map of the 8052 program memory.
FFFF r - - - - - - - - - - - . , "FFr-----------~
&OK
BYTES
EXTERNAL
14K
-OR BYTES
EXTERNAL
1~~---------~
AND
4KBYTES
INTERNAL
0000 ~---------~
270249-1
Figure 1. The 8051 Program Memory
9-2
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
FFFF , - - - - - - - - - - -.... FFFF,-----------~
56 K
BYTES
EXTERNAL
64K
--OR-.....,..... BYTES
EXTERNAL
~~--------------~
AND
1 F F F r - - - - - - - - - - -....
8KBYTES
INTERNAL
~L-----------------~
0000 L-_________ ..J
270249-2
Figure 2. The 8052 Program Memory
Data Memory:
The 8051 can address up to 64K bytes of Data Memory to the chip. The "MOVX" instruction is used to access the
external data memory. (Refer to the MeS-51 Instruction Set, in this chapter, for detailed description of instructions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) plus a number of Special Function Registers (SFRs).
The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing
(MOV @Ri). Figure 3 shows the 8051 and the 8052 Data Memory organization.
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
OFFFr------------------,
INTERNAL
FF..-------------,
84K
SFR. BYTES
DIRECT EXTERNAL
ADDRESSING
ONLY
~~--------~
7F - - AND -----l.,..
DIRECT.
INDIRECT
ADDRESSING
oo~--------~ ooooL-------------~
270249-3
Figure 3a. The 8051 Data Memory
FFFFr--------------------,
INTERNAL
f
INDIRECT
ADDRESSING ONLY
1,---1------, '"
FF
~HTOFFH
FF..---=-~------......,
84K
SFR. BYTES
DIRECT EXTERNAL
ADDRESSING
1-
ONLY
--AND . . . . . . .
~
7Fr--------------------i
DIRECT.
J
INDIRECT
ADDRESSING
oo~--------~
270249-4
Figure 3b. The 8052 Data Memory
9·4'
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Neverthe-
less, they are two separate areas and are accessed in two different ways.
For example the instruction
MOV 80H,#OAAH
writes OAAH to Port 0 which is one of the SFRs and the instruction
MOV RO,#80H
MOV @RO,#OBBH
writes OBBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will
contain OAAH and location 80 of the RAM will contain OBBH.
DIRECT AND INDIRECT ADDRESS AREA:
The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments
as listed below and shown in Figure 4.
1. Register Banks 0-3: Locations 0 through IFH (32 bytes). ASM-51 and the device after reset default to register
bank O. To use the other register banks the user must select them in the software (refer to the MeS-5l Micro
Assembler User's Guide); Each register bank contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the
first register (RO) of the second register bank. Thus, in order to use more'than one register bank, the SP should be
intialized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this
segment can be directly, addressed (0-7FH). '
The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is'to refer to their
addresses, ie. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on. '
Each of the 16 bytes in this segment can also be addressed as a byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if ~he stack pointer
has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction.
9-5
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Figure 4 shows the different segments of the on-chip RAM.
II-------8BylW
11....... - - - - - - - 1...1
78 7F
70 77
88 6F
60 67
SCRATCH
58 5F
PAD
50 57
AREA
48 4F
40 47
38 , 3F
30 37
28 ... 7F 2F BIT
ADDRESSABLE
20 O••• 27 SEGMENT
18 3 1F
10 2 17 REGISTER
08 1 OF BANKS
0 07
270249:"5
Figure 4. ·128 Bytes of RAM Direct and Indirect Addressable
9-6
infef MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SPECIAL FUNCTION REGISTERS:
Table 1 contains a list of all the SFRs and their addresses.
Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first
column of the diagram in Figure 5.
Table 1
Symbol Name Address
'ACC Accumulator OEOH
'B B Register OFOH
'PSW Program Status Word ODOH
SP Stack Pointer B1H
DPTR Data Pointer 2 Bytes
DPL Low Byte B2H
DPH High Byte B3H
*PO PortO BOH
*P1 Port 1 90H
*P2 Port 2 OAOH
'P3 Port 3 OBOH
*IP Interrupt Priority Control OBBH
'IE Interrupt Enable Control OA8H
TMOD Timer/Counter Mode Control 89H
*TCON Timer/Counter Control B8H
'+ T2CON Timer/Counter 2 Control OC8H
THO Timer/Counter 0 High Byte 8CH
TLO Timer/Counter 0 Low Byte 8AH
TH1 Timer/Counter 1 High Byte BDH
TL1 Timer/Counter 1. Low Byte BBH
+TH2 Timer/Counter 2 High Byte OCDH
+ TL2 Timer/Counter 2 Low Byte OCCH
+ RCAP2H T /C 2 Capture Reg. High Byte OCBH
+ RCAP2L T /C 2 Capture Reg. Low Byte OCAH
'SCON Serial Control 98H
SBUF Serial Data Buffer 99H
PCON Power Control B7H
• = Bit addressable
+ = 8052 only
9-7
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET?
Table -2 li$ts the contents of each SFR after power-on or a hardware reset.
Table 2. Contents of the SFRs after reset '
Register Value in Binary
°ACC 00000000
oS 00000000
°pSW 00000000
Sp 00000111
DPTR
DPH 00000000
DPL 00000000
'PO 11111111
'P1 11111111
'P2 11111111
'P3 11111111
"P 8051 XXXOOOOO,
8052 XXOOOOOO
'IE 80510XXOOOOO,
8052 OXOOOOOO
TMOD 00000000
'TCON 00000000
*+ T2CON 00000000
THO 00000000
TLO 00000000
TH1 00000000
TL1 00000000
+TH2 00000000
+TL2 00000000
+ RCAP2H 00000000
+ RCAP2L 00000000
'SCON 00000000
SBUF Indeterminate
PCON HMOS OXXXXXXX
CHMOS OXXXOOOO
x = Undefined
• = Bit Addressable
+ = 8052on!y
9-8
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SFR MEMORY MAP
8 Bytes
FB FF
FO B F7
EB EF
EO ACC E7
DB DF
DO PSW D7
CB T2CON RCAP2L RCAP2H TL2 TH2 CF
CO C7
BB IP BF
BO P3 B7
AB IE AF
AO P2 A7
98 SCON SBUF 9F
90 P1 97
B8 TCON TMOD TLO TL1 THO TH1 BF
BO PO SP DPL DPH PCON B7
t Figure 5
Bit
Addressable
9-9
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit
is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY AC FO RS1 RSO OV P
CY PSW.7 Carry Flag.
AC PSW.6 Auxiliary Carry Flag.
FO psw.s Flag 0 available to the user for general purpose.
RSI PSW.4 Register Bank selector bit I (SEE NOTE I).
RSO PSW.3 Register Bank selector bit 0 (SEE NOTE I).
OV PSW.2 Overflow Flag.
PSW.I Not implemented, reserved for future use.'
P psw.o Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of
'I' bits in the accumulator. .
NOTE:
1. The value presented by RSO and RS1 selects the corresponding register bank.
RS1 RSO Register Bank Address
0 0 0 OOH-07H
0 1 1 OBH-OFH
1 0 2 10H-17H
1 1 3 1BH-1FH
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOO I _. I GF1 GFO PO IOL
SMOD Double baud rate bit. If Timer I is used to generate baud rate and SMOD = I, the baud rate is doubled
when the Serial Port is used in modes I, 2, or 3.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
GFI General purpose flag bit.
GFO General purpose flag bit.
PD Power Down bit. Setting this bit activates Power Down operation in the 80CSIBH. (Available only in
CHMOS).
IDL Idle Mode bit. Setting this bit activates Idle Mode operation in the 80CSIBH. (Available only in CHMOS).
If Is are written to PD and IDL at the same time, PD takes precedence.
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
9-10
infef MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INTERRUPTS:
In order to use any of the interrupts in the MCS-SI, the following three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.
Interrupt Vector
Source Address
lEO 0003H
TFO OOOBH
IE1 0013H
TF1 001BH
RI&TI 0023H
TF2 & EXF2 002BH
In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to I, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx = 0 level activated
ITx = 1 transition activated
IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.
EA ET2 ES ET1 EX1 ETO EXO
EA IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
IE.6 Not implemented, reserved for future use.·
ET2 IE.S Enable or disable the Timer 2 overflow or capture interrupt (80S2 only).
ES IE.4 Enable or disable the serial port interrupt.
ETI IE.3 Enable or disable the Timer I overflow interrupt.
EXI IE.2 Enable or disable External Interrupt 1.
ETO IE. 1 Enable or disable the Timer 0 overflow interrupt.
EXO IE.O Enable or disable External Interrupt O.
·User software should not write Is to reserved bits. These bits may be used in future MCS-SI products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
9-11
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.
Remember"that while an interrupt service is in progress, it cannot be interrupted tJy a lower or same level interrupt.
PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level.
From high to low, interrupt sources are listed below:
lEO
TFO
lEI
TFI
RI or TI
TF2 or EXF2
IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a
higher priority.
I PT2 PS PT1 PX1 PTO PXO
IP. 7 Not implemented, reserved for future use.·
IP.6 Not implemented, reserved for future use.'
PT2 IP.S Defines the Timer 2 interrupt priority level (8052 only).
PS IP.4 Defines the" Serial Port interrupt priority level.
PTl "IP. 3 Defines the Timer 1 interrupt priority level.
PXl IP.2 Defines External Interrupt 1 priority level.
PTO IP. 1 Defines the" Timer 0 interrupt priority level.
PXO IP. 0 Defines th~ External Interrupt 0 priority level.
'User software should'not 'write Is to reserved bits. These bits may be used in future MeS-51 products to invoke
new features. In that case, 'the reset or inactive value of the new bit will be 0, and its active value will be 1.
• :.0\
9-12
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TeON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TF1 TR1 TFO TRO IE1 IT1 lEO ITO
TFI TCON. 7 Timer I overflow flag. Set by hardware when the Timer/Counter I overflows. Cleared by hard-
. ware as processor vectors to the interrupt service routine.
TRI TCON.6 Timer I run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
TFO TCON. 5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hard-
ware as processor vectors to the service routine.
TRO TCON. 4 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
lEI TCON. 3 External Interrupt I edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
IT! TCON. 2 Interrupt I type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
lEO TCON. 1 External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
ITO TCON. 0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.
I\: GATE CIT M1 MO I
)\:
GATE CIT M1 MO
)
I
TIMER 1 TIMER 0
GATE When TRx (in TCON) is set and GATE = I, TIMER/COUNTERx will run only while INTx pili is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = I (software
control).
ciT Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Coun-
ter operation (input from Tx input pin).
MI Mode selector bit. (NOTE 1)
MO Mode selector bit. (NOTE 1)
NOTE 1:
M1 MO Operating Mode
o o o 13-bit Timer (MCS-48 compatible)
o 1 1 16-bit Timer/Counter
o 2 8-bit Auto-Reload TimerlCounter
1 3 (Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
3 (Timer 1) Timer/Counter 1 stopped.
9-13
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER SET·UP
Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed .with the value shown for Timer 1 (Tables 5 and 6).
For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER,
then the value that must be loaded into TMoD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it'is assumed that the user, at this point,. is not ready to tum the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to 1.
TIMER/COUNTER 0
As a Timer:
Table 3
TMOD
TIMER 0 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer OOH 08H
1 16-bit Timer 01H 09H
2 8-bit Auto-Reload 02H OAH
3 two 8-bit Timers 03H OSH
As a Counter:
Table 4
TMOD
COUNTER 0 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 04H OCH
1 16-bit Timer 05H ODH
2 8-bit Auto-Reload OSH OEH
3 one 8-bit Counter 07H OFH
NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTO (P3.2) when TRO = 1
(hardware control).
9-14
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 1
As a Timer:
TableS
TMOD
TIMER 1 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer OOH BOH
1 16-bit Timer 10H 90H
2 B-bit Auto-Reload 20H AOH
3 does not run 30H BOH
As a Counter:
TableS
TMOD
COUNTER 1 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
0 13-bit Timer 40H COH
.1 16-bit Timer 50H DOH
2 B-bit Auto-Reload 60H EOH
3 not available - -
NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1
(hardware control).
9-15
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
1 TF2 1 EXF2 RCLK TCLK .1 EXEN2 TR2 C/T2.1 CP/RL2
TF2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
either RCLK = I or CLK = I .
EXF2 T2CON. 6 Timer 2 externa!. flag set when either a capture or reload is caused by a negative transition on
T2EX, and EXEN2= 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK nCON. 5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes I & 3. RCLK = 0 causes Timer I overflow to be used for the receive
clock.
TLCK T2CON. 4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes I & 3. TCLK = 0 causes Timer I overflows to be used for the
transmit clock.
EXEN2 T2CON. 3 Timer 2 external enable flag. When set,' allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 T2CON.2 Software START/STOP control for. Timer 2. A logic I starts the Timer.
C/T2 T2CON. 1 Timer or Counter select.
o = Internal Timer. I = External Event Counter (falling edge triggered).
CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when' EXEN2 = 1. When either RCLK = 1 or TCLK = I,
this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.
9-16
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to turn the Timer on.
As a Timer:
Table 7
T2CON
MODE INTERNAL EXTERNAL
CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Aulo-Reload OOH OSH
16-bit Capture 01H 09H
BAUD rate generator receive &
transmit same baud rate 34H 36H
receive only 24H 26H
transmit only 14H 16H
As a Counter:
TableS
TMOD
MODE INTERNAL EXTERNAL
CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bit Auto-Reload 02H OAH
16-bit Capture 03H OBH
NOTES:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX
(P1.1) pin except when Timer 2 is used in the baud rate generating mode.
9-17
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.
I SMO SM1 SM2 REN TB8 RB8 TI RI
SMO SCON.7 Serial Port mode specifier. (NOTE 1).
SMI SCON. 6 Serial Port mode specifier. (NOTE 1).
SM2 SCON.5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, ifSM2 is set
to 1 then RI will not be activated if the received 9th data bit (RB8) is O. In mode I, if SM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 9). .
REN SCON. 4 Set/Cleared by software to Enable/Disable reception.
TB8 SCON. 3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
RB8 SCON. 2. In modes 2 & 3, is the 9th data bit that was received. In mode 1, ifSM2 = 0, RB8 is the stop bit
that was received. In mode 0, RB8 is not used. . .
TI SCON. 1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
RI SCON. 0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.
NOTE 1:
SMO SM1 Mode Description Baud Rate
o 0 0 SHIFT REGISTER Fo.sc.l12
o 1 1 8-Bit UART Variable
1 0 2 9-Bit UART Fosc.l64 OR
Fosc.l32
3 9-Bit UART Variable
SERIAL PORT SET·UP:
Table 9
MODE SCON 5M2 VARIATION
0 10H
Single Processor
1 50H
Environment
2 90H
(SM2 = 0)
3 DOH
0 NA
• Multiprocessor
I 70H
EnVironment
2 BOH
(SM2 = 1)
3 FOH
GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Osc Freq
Baud Rate = - - -
12
Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (8052 only).
9-18
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
B d R te = K x Oscillator Freq.
au a 32 x 12 x [256 - (TH111
If SMOD = 0, then K = 1.
If SMOD = I, then K = 2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs to know the reload value for THI.
Therefore, the equation to calculate THI can be written as:
TH1 = 256 _ K x Ose Freq.
384 x baud rate
THI must be an integer value. Rounding off THI to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.
USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (PI.O) the baud rate is:
B d Timer 2 Overflow Rate
au Rate = 16
And if it is being clocked internally the baud rate is:
Osc Freq
Baud Rate = 32 x [65536 - (RCAP2H, RCAP2L))
To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as:
. RCAP2H, RCAP2L = 65536 - 3 O~c F~e~
2x au ate
SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is Va. or '1.4 of the oscillator frequency depending on the value of the SMOD
bit in the PCON register.
In this mode none of the Timers are used and the clock co~es from the internal phase 2 clock.
SMOD = I, Baud Rate = Va. Osc Freq.
SMOD = 0, Baud Rate = '1.4 Osc Freq.
To set the SMOD bit: ORL PCON, # 80H. The address of PCON is 87H.
SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.
9-19
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MCS®-S1 INSTRUCTION SET
Table 10.8051 Instruction Set Summary
Interrupt Response Time: Refer to Hardware De- Oscillator
Mnemonic' Description Byte
scription Chapter. Period
ARITHMETIC OPERATIONS
Instructions that Affect Flag Settings(1)
ADD A,Rn Add register to 12
Instruction Flag Instruction Flag Accumulator
C OV AC / C OV AC ADD A,direct Add direct byte to 2 12
ADD X X X ClRC 0 Accumulator
ADDC X X X CPlC X ADD A,@Ri Add indirect RAM 12
SUBB X X X ANlC,bit X to Accumulator
MUl 0 X ANlC,/bit X ADD A,#data Add immediate 2 12
DIV 0 X ORlC,bit X data to
DA X ORlC,bit X Accumulator
RRC X MOVC,bit X AD DC A,Rn Add register to 12
RlC X CJNE X Accumulator
SETBC with Carry
(I)Note that operations on SFR byte address 208 or ADDC A,direct Add direct byte to 2 12
bit addresses 209-215 (i.e., the PSW or bits in the Accumulator'
PSW) will also affect flag settings. with Carry
ADDC A,@Ri Add indirect 12
Note on instruction set and ad,dressing modes: RAM to
Rn - Register R7-RO of the currently se- Accumulator
lected Register Bank.. with Carry
direct - 8-bit- internal data location's address. ADDC A,#data Add immediate '2 12
This could be an Internal Data RAM data toAcc
location (0-127) or a SFR [i.e., I/O with Carry
port, control register, status register, SUBB A,Rn Subtract Register 12
etc. (128-255)J. from Acc with
@Ri - 8-bit internal data RAM location (0- borrow
255) addressed indirectly through reg- SUBB A,direct Subtract direct 2 12
ister Rl orRO. byte from Acc
#data - 8-bit constant included in instruction. with borrow
#data 16 - 16-bit constant included in instruction. SUBB A,@Ri Subtract indirect 12
addr 16 - 16-bit destination address. Used by RAMfromACC
LCALL & LJMP. A branch ,can be with borrow
anywhere within the 64K-byte Pro- SUBB .A,#data Subtract 2 12
gram Memory address space. immediate data
addr 11 - II-bit destination address. Used by from Acc with
ACALL & AJMP. The branch will be borrow
within the same 2K-byte page of pro- iNC A increment 12
gram memory as the first byte of the Accumulator
following instruction. INC Rn Increment register 12
rei - Signed (two's complement) 8-bit offset INC direct Increment direct 2 12
byte. Used by SJMP and all condition- byte
al jumps. Range is -128 to + 127 INC @Ri Increment direct 12
bytes relative to first byte of the fol- RAM
lowing instruction. DEC A Decrement 12
bit - Direct Addressed bit in Internal Data Accumulator
RAM or Special Function Register. DEC Rn Decrement 12
-New operation not provided by Register
8048AH/8049AH. DEC direct Decrement direct 2 12
byte
DEC . @Ri Decrement 12
indirect RAM
All mnemonics copyrighted @Intel Corporation 1980
9-20
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10. 8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
ARITHMETIC OPERATIONS (Continued) LOGICAL OPERATIONS (Continued)
INC DPTR Increment Data 24 RL A Rotate 12
Pointer Accumulator Left
MUL AB Multiply A & B 48 RLC A Rotate 12
DIV AB Divide A by B 48 Accumulator Left
DA A Decimal Adjust 12 through the Carry
Accumulator RR A Rotate 12
LOGICAL OPERATIONS Accumulator
ANL A,Rn AND Register to 12 Right
Accumulator RRC A Rotate 12
ANL A,direct AND direct byte 2 12 Accumulator
to Accumulator Right through
ANL A,@Ri AND indirect 12 the Carry
RAM to SWAP A Swap nibbles 12
Accumulator within the
ANL A,#data AND immediate 2 12 Accumulator
data to DATA TRANSFER
Accumulator MOV A,Rn Move 12
ANL direct,A AND Accumulator 2 12 register to
to direct byte Accumulator
ANL direct, # data AND immediate 3 24 MOV A,direct Move direct 2 12
data to direct byte byte to
ORL A,Rn OR register to 12 Accumulator
Accumulator MOV A,@Ri Move indirect 12
ORL A,direct OR direct byte to 2 12 RAM to
Accumulator Accumulator
ORL A,@Ri OR indirect RAM 12 MOV A,#data Move 2 12
to Accumulator immediate
ORL A,#data OR immediate 2 12 data to
data to Accumulator
Accumulator MOV Rn,A Move 12
ORL direct,A OR Accumulator 2 12 Accumulator
to direct by1e to register
ORL direct, # data OR immediate 3 24 MOV Rn,direct Move direct 2 24
data to direct byte byte to
XRL A,Rn Exclusive·OR 12 register
register to MOV Rn,#data Move 2 12
Accumulator immediate data
XRL A,direct Exciusive·OR 2 12 to register
direct byte to MOV direct,A Move 2 12
Accumulator Accumulator
XRL A,@Ri Exciusive·OR 12 to direct by1e
indirect RAM to MOV direct,Rn Move register 2 24
Accumulator to direct by1e
XRL A,#data Exciusive·OR 2 12 MOV direct, direct Move direct 3 24
immediate data to byte to direct
Accumulator MOV direct,@Ri Move indirect 2 24
XRL direct,A Exclusive·OR 2 12 RAM to
Accumulator to direct byte
direct byte MOV direct, # data Move 3 24
XRL direct, # data Exclusive·OR 3 24 immediate data
immediate data to direct byte
to direct byte MOV @Ri,A Move 12
CLR A Clear 12 Accumulator to
Accumulator indirect RAM
CPL A Complement 12 All mnemonics copyrighted ® Intel Corporation 1980
Accumulator
9-21
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
DATA TRANSFER (Continued) BOOLEAN VARIABLE MANIPULATION
MOV @Ri,direct Move direct 2 24 CLR C Clear Carry 1 12
byte'to ' CLR bit Clear direct bit 2 12
indirect RAM SETB C Set Carry 1 12
MOV @Ri,#data Move 2 12 SETB bit Set direct bit 2 12
immediate CPL C Complement 12
data to Carry
indirect RAM CPL bit Complement 2 12
MOV DPTR,#dataI6 Load Data 3 24 direct bit
Pointer with a ANL C,bit AND direct bit 2 24
16-bit constant to CARRY
MOVC A,@A+DPTR Move Code 24 ANL C,/bit AND complement 2 24
byte relative to of direct bit
DPTRtoAcc to Carry
MOVC A,@A+PC Move Code 24 ORL C,bit OR direct bit 2 24
byte relative to to Carry
PC to Acc ORL C,/bit OR complement 2 24
MOVX A,@Ri Move 24 of direct bit
External to Carry
RAM (8-bit MOV C,bit Move direct bit 2 12
addr) toAcc to Carry
MOVX A,@DPTR Move 24 MOV bit,C Move Carry to 2 24
External direct bit
, RAM (16-bit JC rei Jump if Carry 2 24
addr) toAcc is set
MOVX @Ri,A Move Acc to 24 JNC rei Jump if Carry 2 24
External RAM not set
(8-bit addr) JB bit,rel Jump if direct 3 24
MOVX @DPTR,A Move Accto 24 Bit is set
External RAM JNB bit,rel Jump if direct 3 24
(16-bit addr) Bit is Not set
PUSH direct Push direct 2 24 JBC , bit,rel Jump if direct 3 24
byte onto Bit is set &
stac~ clear bit
POP direct Pop direct 2 24 PROGRAM BRANCHING
byte from ACALL addrll Absolute 2 24
stack Subroutine
XCH A,Rn Exchange 12 Call
register with LCALL addr16 Long 3 24
Accumulator Subroutine
XCH A,direct Exchange 2 12 Call
direct byte RET Return from 24
with Subroutine
Accumulator RETI Return from 24
XCH A,@Ri Exchange , 12 interrupt
indirect RAM AJMP addrll Absolute 2 24
with Jump
Accumulator LJMP addr16 Long Jump 3 24
XCHD A,@Ri Exchange low- 12 SJMP rei Short Jump 2 24
order Digit (relative addr)
indirect RAM All mnemonics copyrighted ©Intel Corporation 1980
withAcc
9-22
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set Summary (Continued)
Oscillator Oscillator
Mnemonic Description Byte Mnemonic Description Byte
Period Period
PROGRAM BRANCHING (Continued) PROGRAM BRANCHING (Continued)
JMP @A+DPTR Jump indirect 24 CJNE Rn, # data,rel Compare 3 24
relative to the immediate to
DPTR register and
JZ rei Jump if 2 24 ·JumpifNot
Accumulator Equal
is Zero CJNE @Ri,#data,rel Compare 3 24
JNZ rei Jump if 2 24 immediate to
Accumulator indirect and
is Not Zero Jump if Not
CJNE A,direct,rel Compare 3 24 Equal
direct byte to DJNZ Rn,rel Decrement 2 24
Acc and Jump register and
if Not Equal Jump if Not
CJNE A,#data,rel Compare 3 24 Zero
immediate to DJNZ direct,rel Decrement 3 24
Acc and Jump direct byte
if Not Equal and Jump if
Not Zero
NOP No Operation 12
All mnemonics copyrighted @lIntel Corporation 1980
9-23
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INSTRUCTION DEFINITIONS
ACALL addr11
Function: Absolute Call
Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
I6-bit result onto the,stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the, five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.
Example: Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL SUBRTN '
at location OI23H, SP will contain 09H, internal RAM locations OSH and 09H will contain
25H and OIH, respectively, and the PC will contain 0345H.
Bytes: 2
Cycles: 2
Encoding: I a10 a9 a8 1 0 0 0 11 a7 a6 a5 a4 a3' a2 a1 aO
Operation: ACALL
(PC) - (PC) + 2
(SP) - (SP) + 1
«SP» - (PC7-O)
(SP) - (SP) + 1
«SP» - (PCIS-S)
(PCw_o) - page address
9-24
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADD A, < src-byte >
Function: Add
Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumula-
tor. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occured..
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number pro-
duced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or imme-
diate.
Example: The Accumulator holds OC3H (llOOOO1IB) and register 0 holds OAAH (10 10 10 lOB). The
instruction,
ADD A,RO
will leave 6DH (01 101 101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to I.
ADD A,Rn
Bytes:
Cycles:
Encoding: I0 o 1 0 1 r r r
Operation: ADD
(A) ~ (A) + (Rn)
ADD A,direct
Bytes: 2
Cycles:
Encoding: I0 010 o1 0 1 direct address
Operation: ADD
(A) ~ (A) + (direct)
9-25
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADD A,@RI
Bytes:
Cycles:
Encoding: 100 1 0 011
Operation: ADD
(A) - (A) + «R0)
ADD A,#data
Bytes: 2
Cycles:
Encoding:
1 00 1 0 o1 0 0 immediate data
Operation: ADD
(A)-(A) + # data
ADDC A, <src-byte >
Function: Add with Carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out ofbit.7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or imme-
diate.
Example: The Accumulatpr holds OC3H (1 100001 IB) and register 0 holds OAAH (lOlOlOlOB) with the
carry flag set. The instruction,
ADDC A,RO
will leave 6EH (01101 1lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1. .
9-26
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADDC A,Rn
Bytes:
Cycles:
Encoding: 1,--0_O_l_-,--_l_r_r_r--l1
Operation: ADDC
(A) ~ (A) + (C) + (Rn)
AD DC A,direct
Bytes: 2
Cycles:
Encoding: L..1_o_o_1_~0_1_0_1-, direct address
Operation: ADDC
(A) ~ (A) + (C) + (direct)
ADDC A,@Ri
Bytes:
Cycles:
Encoding: 10 0 1 1 0 1 1 i
Operation: ADDC
(A) ~ (A) + (C) + «Ri»
AD DC A,#data
Bytes: 2
Cycles:
Encoding: 1-1_0_0_1_-,--0_1_0_0-, immediate data I
Operation: ADDC
(A) ~ (A) + (C) + #data
9-27
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
AJMP addr11
Function: Absolute Jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
Example:· The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.
Bytes: 2
Cycles: 2
Encoding: I a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 aO
Operation: AJMP
(PC) +- (PC) + 2
(PCIO-O) +- page address
ANL < dest-byte > , < src-byte >
Function: Logical-AND for byte variables
Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the Accumulator holds OC3H (110000 11 B) and register 0 holds 55H (OlOlOlOlB) then the
instruction,
"A...NL LA..,RO
will leave 41H (OlOOOOOlB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
the Accumulator at run-time. The instruction, '
ANL Pl,#OlllOOllB
will clear bitS 7, 3, and 2 of output port 1.
9-28
intJ MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ANL A,Rn
Bytes:
Cycles:
Encoding:
1 01
o1 1 r r r
Operation: ANL
(A) ~ (A) A (Rn)
ANL A,direct
Bytes: 2
Cycles:
Encoding: I0 1 o1 o1 0 1 direct address
Operation: ANL
(A) ~ (A) A (direct)
ANL A,@Ri
Bytes:
Cycles:
Encoding:
1 01
o1 o1 1
. Operation: ANL
(A) ~ (A) A «Ri»
ANL A, # data
Bytes: 2
Cycles:
Encoding:
1 01
o1 o10 0 immediate data
Operation: ANL
(A) ~ (A) A #data
ANL direct,A
Bytes: 2
Cycles:
Encoding: 1 01
o1 001 0 direct address
Operation: ANL
(direct) ~ (direct) A (A)
9-29
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ANL direct, # data
Bytes: 3
Cycles: 2
Encoding: I 0 .1 0 1 0 0 1 1 direct address I immediate data
Operation: ANL
(direct) +- (direct) " #data
ANL C,<src-bit>
Function: Logical-AND for bit variables
Description: If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash ("/") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.
Only direct addressing is allowed for the source operand.
.Example: Set the carry flag if, and only if, PI.O = 1, ACC. 7 = 1, and OV = 0:
MOV C,Pl.O ;LOAD CARRY WITH INPUT PIN STATE
ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG
ANL C,bit
Bytes: 2
Cycles: 2
Encoding: 11 000 001 0 bit address
Operation: ANL
(C) +- (C) " (bit)
ANL C,/bit
Bytes: 2
Cycles: 2
Encoding: I1o1 0000 bit address
Operation: ANL
(C) +- (C) " I (bit)
9-30
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CJNE < dest-byte > , < src-byte > , rei
Function: Compare and Jump if Not Equal.
Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned
integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.
Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the se-
quence,
CJNE R7,#60H, NOT_EQ
R7 = 60H.
JC IFR7 < 60H.
R7> 60H.
sets the carry flag anc;l branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R 7 is greater or less than 60H.
If the data being presented to Port I is also 34H, then the instruction,
WAIT: CJNE A,PI,WAIT
clears the carry flag and continues with the next instruction in sequence, since the Accumula-
tor does equal the data read from Pl. (If some other value was being input on PI, the program
will loop at this point until the PI data changes to 34H.)
CJNE A,direct,rel
Bytes: 3
Cycles: 2
Encoding: I1 0 1 1 0 1 0 1 direct address reI. address
Operation: (PC) - (PC) + 3
IF (A) <> (direct)
THEN
(PC) - (PC) + relative offset
IF (A) < (direct)
THEN
(C)-l
ELSE
(C)-O
9-31
infef MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CJNE A,#data,rel
Bytes: 3
Cycles: 2
Encoding: . 11 011 o1 0 0 immediate data reI. address
Operation: (PC) - (PC) + 3
IF (A) < > data
THEN
(PC) - (PC) + relative offset
IF (A) < data
THEN
(C)-l
ELSE
(C)-O
CJNE Rn,#data,rel
Bytes: 3
Cycles: 2
Encoding: 110 1 1 1 r r r immediate data rei. address
Operation: (PC) - (PC) + 3
IF (Rn) < > data
THEN
(PC) - (PC) + relative offset
IF (Rn) < data
THEN"
(C)-l
ELSE
(C)-O
CJNE @Ri,#data,rel
Bytes: 3
Cycles: 2
Encoding: 11 0 1 1 0 1 1 immediate data rei. address
Operation: (PC) - (PC) + 3
IF «Ri» < > data
THEN
(PC) - (PC) + relative offset
IF «Ri» < data
THEN
(C)-l
ELSE
(C)-O
9-32
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CLR A
Function: Clear Accumulator
Description: The Accumulator is cleared (all bits set on zero). No flags are affected.
Example: The Accumulator contains SCH (0101 I 100B). The instruction,
CLR A
will leave the Accumulator set to OOH (OOOOOOOOB).
Bytes:
Cycles:
Encoding: 11 1 1 0 1 0 0
Operation: CLR
(A)~O
CLR bit
Function: Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Example: Port I has previously. been written with SDH (OlOllIOIB). The instruction,
CLR P1.2
will leave the port set to S9H (OIOIIOOIB).
CLR C
Bytes:
Cycles:
Encoding: 11 0 0 0 0 1 1
Operation: CLR
(C)~O
CLR bit
Bytes: 2
Cycles:
Encoding: 1 1 1 0 0.1 0 0 1 0 bit address
Operation: CLR
(bit) ~O
9-33
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL A
Function: Complement Accumulator
Description: . Each bit of the Accumulator is logically complemented (one's complement). Bits which previ-
ously contained a one are changed to a zero and vice-versa. No flags are affected.
Example: The Accumulator contains 5CH (01011100B). The instruction,
CPL A
will leave the Accumulator set to OA3H (10100011B).
Bytes:
Cycles:
Encoding: I1 1 1 0 1 0 0
Operation: CPL
(A) ..... -, (A)
CPL bit
Function: Complement bit
Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly address-
able bit.
Note: When this instruction is used to modify an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example: Port 1 has previously been written with 5BH (Ol011101B). The instruction sequence,
CPL Pl.l
CPL P1.2
will leave the port set to 5BH (01011011B).
CFL C
Bytes:
Cycles:
Encoding: I1 0 1 1 0 0 1 1
Operation: CPL
(C) ..... -, (C)
9-34
intJ MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL bit
Bytes: 2
Cycles:
Encoding: 1-1_1_0_1_1----'-_0_0_1_0--' bit address
Operation: CPL
(bit) - -, (bit)
DA A
Function: Decimal-adjust Accumulator for Addition
Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx 10 IO-xxxxi II 1), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagat-
ed through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1OIOxxxx-l1 lxxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentiilily, this instruction performs the
decimal conversion by adding OOH, 06H, 60H, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD nota-
tion, nor does DA A apply to decimal subtraction.
9-35
inter MCS®·S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Example: The Accumulator holds the "value 56H (01010110B) representing the packed "BCD digits of the
decimal number 56. Register 3 contains the value 67H (OllOOllIB) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC A,R3
DA A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OOI00I00B), indicating "the packed BCD digits of the decimal number 24, the low-order two
digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust'instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and "1 is
124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD A,#99H
DA A
will leave the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order
byte of the sum can be interpreted to mean 30 - 1 = 29.
Bytes:
Cycles:
Encoding: I1 1 0 1 0 1 0 0
Operation: DA
-contents of Accumulator are BCD
IF [[(A3-O) > 9] V [(AC) = III
THEN(A3_0) +- (A3-0) + 6
AND
IF [[(A7-4) > 9] V [(C) = III
THEN (A7-4) +- (A7-4) + 6
9-36
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DEC byte
Function: Decrement
Description: The variable indicated is decremented by 1. An original value of DOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect. .
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: °
Register contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain DOH
and 4OH, respectively. The instruction sequence,
DEC @RO
DEC RO
DEC @RO
will leave register
3FH.
°
set to 7EH and internal RAM locations 7EH and 1FH set to OFFH and
DEC A
Bytes:
Cycles:
Encoding: _O_O_O_..L.0_ 1_ O
L...I _ 0--l
Operation: DEC
(A) +- (A) - 1
DEC Rn
Bytes:
Cycles:
Encoding: I °°°1 1 rr r
Operation: DEC
(Rn) +- (Rn) - 1
9-37
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DEC direct
Bytes: 2
Cycles:
Encoding: 1 000 1 o1 0.1 direct address
Operation: DEC
(direct) - (direct) - 1
DEC @RI
Bytes:
Cycles:
Encoding: 1 000 1 o 11
Operation: DEC
«Ri» - «Ri» - 1
DIV AB
Function: Divide
Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.
Exception: if B had originally contained OOH, the values returned in the Accumulator and B-
register will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example: The Accumulator contains 251 (OFBH or 1111101lB) and B contains 18 (l2H or 0OOI00lOB).
The instruction,
DIV AB
will leave 13 in the Accumulator (ODH or 0000llOlB) and the value 17 (11H or 00010001B) .
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes:
Cycles: 4
Encoding: 11 0 0 0 0 1 0 0 I·
Operation: DIV
(Ah5-8 _ (A)/(B)
(Bh.o
9-38
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DJNZ < byte> , < rel-addr >
Function: Decrement and Jump if Not Zero
Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to
OFFH. No flags are affected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC to
the first byte of the following instruction.
The location decremented may be a register' or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Internal RAM locations 40H, SOH, and 60H contain the values 01H, 70H, and ISH, respec-
tively. The instruction sequence,
DJNZ 40H,LABEL_l
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values OOH, 6FH, and ISH in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
MOV R2,#8
TOGGLE: CPL P1.7
DJNZ R2,TOGGLE
will toggle Pl.7 eight times, causing four output pulses to appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes: 2
Cycles: 2
Encoding: L.1_1_1_0_1-,-_1_r_r_r..J 'I reI. address
Operation: DJNZ
(PC) +- (PC) + 2
(Rn) +- (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) +- (PC) + rei
9-39
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DJNZ direct,rel
Bytes: 3
Cycles: 2
Encoding: I1 1 0 1 0 1 0 1 direct address reI. address
Operation: DJNZ
(PC) - (PC) + 2
(direct) - (direct) - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) - (PC) + rei
INC <byte>
Function: Increment
Description: INC increments the indicated variable by 1. An original value ofOFFH will overflow to OOH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Register 0 contains 7EH (011 11 11 lOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respective-
ly) OOH and 4lH.
INC A
Bytes:
Cycles:
I I
Encoding: I0 0 0 0 I 0 1 0 0
Operation: INC
(A) - (A) + 1
9-40
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INC Rn
Bytes:
Cycles:
Encoding: I 00 0 0 I 1 r r r
Operation: INC
(Rn) ~ (Rn) + 1
INC direct
Bytes: 2
Cycles:
Encoding: I 0 000 I o 1 0 1 direct address
Operation: INC
(direct) ~ (direct) +
INC @Ri
Bytes:
Cycles:
Encoding: I 000 0 I 011
Operation: INC
«Ri» ~ «Ri» +
INC DPTR
Function: Increment Data Pointer
Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Example: Registers DPH and DPL contain 12H 'and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and OlH.
'Bytes:
Cycles: 2
Encoding: I1 0 1 0 0 0 1 1
Operation: INC
(DPTR) ~ (DPTR) + 1
9-41
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JB blt,rel
Function: Jump if Bit set
Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byteofthe next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port 1 is 110010 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB P1.2,LABELl
JB ACC.2,LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: I0 0 1 0 0 0 0 0 bit address reI. address
Operation: JB
(PC) - (PC) + 3
/
IF (bit) = 1
THEN
(PC) - (PC) + rei
JBC bit,rel
Function: Jump if Bit is set and Clear bit
Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is comput-
ed by adding the signed rehitive-displacement in the third instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example: The Accumulator holds 56H (0 10 10 1l0B). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (0 10 1OOlOB).
9-42
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Bytes: 3
Cycles: 2
Encoding: LI_o_o_o_-,---o_o_o_o--, bit address reI. address
Operation: mc
(PC) <E- (PC) + 3
IF (bit) = I
THEN
(bit) <E- °
(PC) <E- (PC) + rei
JC rei
Function: Jump if Carry is set
Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. No flags are affected .
. Example: The carry flag is cleared. The instruction sequence,
JC LABELl
CPL C
JC LABEL 2
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes: 2
Cycles: 2
Encoding: I ° 1 °° ° ° ° ° reI. address
Operation: JC
(PC) <E- (PC) + 2
IF (C) = I
THEN
(PC) <E- (PC) + rei
9-43
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JMP @A+DPTR
Function: Jump indirect
Description: Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and
load the resulting sum to the program counter. This will be the address for subsequent instruc-
tion fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order
eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data
Pointer is altered. No flags are affected.
Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions wiil
branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
MOV DPTR,#JMP_TaL
JMP @A+DPTR
AJMP LABELO
AJMP LABELl
AJMP LABEL2
AJMP LABE;L3
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte -instruction, so the jump instructions start at
every other address.
Bytes:
Cycles: 2
Encoding: I0 1 1 0 0 1 1
Operation: JMP
(PC) +-- (A) + (DPTR)
9-44
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JNB bit,rel
Function: Jump if Bit Not set
Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative;displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port I is 1100101OB. The Accumulator holds 56H (010101 lOB). The
instruction sequence,
JNB P1.3,LABELI
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: LI_o_o_1_1--,-_0_0_0_0-, bit address reI. address
Operation: JNB
(PC) +- (PC) + 3
IF (bit) = °
THEN (PC) +- (PC) + reI.
JNC reI
Function: Jump if Carry not set
Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified.
Example: The carry flag is set. The instruction sequence,
JNC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
the label LABEL2.
Bytes: 2
Cycles: 2
EncodIng: 1-1_0_ _
0_1--,-_0_0_0_0-, reI. address
Operation: JNC
(PC) +- (PC) + 2
IF (C) = °
THEN (PC) +- (PC) + rei
9-45
inter MCS®~51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JNZ rei
Function: Jump if Accumulator Not Zero
Description: If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with
the next instruction.. The 'branch destination is computed by adding the signed relative-dis-
placement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified.·No flags are affected.
Example: The Accumulator originally holds OOH. The instruction sequence,
JNZ LABELl
INC A
JNZ LABEL2
will set the Accumulator to OlH and continue at label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 1,--o__1_1--1._0_0_0_0-, reI. address
Operation: JNZ '
(PC) ~ (PC) + 2
IF (A) *°
THEN (PC) ~ (PC) + reI
JZ rei
Function: Jump if Accumulator Zero
Description: If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with
the next instruction; The branch destination is computed by adding the signed relative-dis-
placement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example: The Accumulator originally contains OlH. The instruction sequence,
JZ LABELl
DEC A
JZ LABEL2
will change the Accumulator to OOH and cause program execution to continue at the instruc-
tiori identified by the label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 1 ° ° °°°°
1 1 reI. address
Operation: JZ
(PC) ~ (PC) + 2
IF (A) = 0
THEN (PC) ~ (PC) + rei
9-46
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
LCALL addr16
Function: Long call
Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of
the LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the full 64K-byte program memory address space.
No flags are affected. .
Example: Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction, .
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations OSH and 09H
will contain 26H and OIH, and the PC will contain 1234H.
Bytes: 3
Cycles: 2
Encoding: ..._O_O_O_->-_O_O_1_0...J
1 addr15-addrB addr7-addrO
Operation: LCALL
(PC) ~ (PC) + 3
(SP) ~ (SP) + I
«SP» ~ (PC7-0)
(SP) ~ (SP) + I
«SP» ~ (PCI5-S)
(PC) ~ addrl5_0
LJMP addr16
Function: Long Jump
Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected. .
Example: The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
UMP JMPADR
at location 0123H will load the program counter with 1234H.
Bytes: 3
Cycles: 2
Encoding: 1 ° °0·1 °° °
0 1 addr15-addrB addr7 -addrO
Operation: LJMP
(PC) ~ addft5_0
9-47
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV < dest-byte> , < src-byte >
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.
Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is IOH. The data
present at input port I is 1100 10 lOB (OCAH).
MOY RO,#30H ;RO <= 30H
MOY A,@RO ;A <= 40H
MOY Rl,A ;Rl <= 40H
MOY B,@Rl ;B <= lOH
MOY @Rl,PI ;RAM (40H) < = OCAH
MOY P2,PJ ;P2 #OCAH
leaves the value 30H in register 0, 40H in both the Accumulator and register 1, lOR in register
B, and OCAR (llOOIOIOB) both in RAM location 40R and output on port 2.
MOV A,Rn
Bytes:
Cycles:
Encoding: 11 1 1 0 1 r r r
Operation: MOY
(A) -(Rn)
·MOV A,dlrect
Bytes: 2
Cycles:
Encoding: 11 1 1 0 o1 0 1 direct address
Operation: MOY
(A) - (direct)
MOV A,ACC Is not a valid Instruction.
9-48
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV A,@Ri
Bytes:
Cycles:
Encoding: I1 1 1 0 o1
Operation: MOV
(A) -- «Ri»
MOV A, # data
Bytes: 2
Cycles:
Encoding: I0 1 1 1 o1 0 0 immediate data
Operation: MOV
(A) -- #data
MOV Rn,A
Bytes:
Cycles:
Encoding: I 1 111 1 r r r
Operation: MOV
(Rn) -- (A)
MOV Rn,direct
Bytes: 2
Cycles: 2
Encoding: I 1 010 1 r r r direct addr.
Operation: MOV
(Rn) -- (direct)
MOV Rn, # data
Bytes: 2
Cycles:
Encoding:
1 01
11 1 r r r immediate data
Operation: MOV
(Rn) -- #data
9-49
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV dlrect,A
Bytes: 2
Cycles:
Encoding: 11 1 1 o1 0 1 I direct address
Operation: MOV
(direct) +- (A)
MOV direct,Rn
Bytes: 2
Cycles: 2
Encoding: 11 000 1 r r r direct address
Operation: MOV
(direct) +- (Rn)
MOV dlrect,direct
Bytes: 3
Cycles: 2
Encoding: 1 1 000 o1 0 1 dir. addr. (src) dir. addr. (dest)
Operation: MOV
(direct) +- (direct)
MOV direct,@Ri
Bytes: 2
Cycles: 2
Encoding: 1 1 000 011 direct addr.
Operaiiuii: 1I.'1"'\.T.7
IVIVY
(direct) +- «Ri»
MOV direct,#data
Bytes: 3
Cycles: 2
Encoding: I· 0 .1 o1 0 1 direct address immediate data
Operation: MOV
(direct) +- #data
9-50
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV @Ri,A
Bytes:
Cycles:
Encoding: I111 011
Operation: MOV
«Ri» ~ (A)
MOV @RI,dlrect
Bytes: 2
Cycles: 2
Encoding: I1 o1 0 011 direct addr.
Operation: MOV
«Ri» ~ (direct)
MOV @Ri,#data
Bytes: 2
Cycles:
Encoding: 101 o1 immediate data
Operation: MOV
«RI» ~ #data
MOV < dest·bit > , <src·bit>
Function: Move bit data
Description: The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.
Example: The carry flag is originally set. The data present at input Port 3 is llOOOlOlB. The data
previously written to output Port 1 is 35H (OOllOlOlB).
I
MOV pl.3,e
MOV e,P3.3
MOV p1.2,e
will leave the carry cleared and change Port 1 to 39H (OOlllOOlB).
9-51
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV C,bit
Bytes: 2
Cycles: . 1
Encoding: 11 010 001 0 bit address
Operation: MOV
(C) +- (bit)
MOV bit,C
Bytes: 2
Cycles: 2
Encoding: 1 1 001 001 0 bit address
Operation: MOV
. (bit) +- (C)
MOV DPTR,#data16
Function: Load Data Poin~er with a 16-bit constant
Description: The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.
Example: The instruction,
MOV DPTR, # 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
Bytes: 3
Cycles: 2
Encoding: 11 0 0 1 0 0 0 0 immed. data 15-8 immed. data7-0
Operation: MOV
(DPTR) +- #data15.0
DPH 0 DPL +- #data15_8 0 #data7.Q
9-52
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVC A,@A+ <base-reg>
Function: Move Code byte
Description: The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumu-
lator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not al-
tered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
REL_PC: INC A
MOVC A,@A+PC
RET
DB 66H
DB 77H
DB 88H
DB 99H
If the subroutine is called with the Accumulator equal to OlH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVe from the table, the
corresponding number would be added to the Accumulator instead ..
MOVC A,@A+DPTR
Bytes:
Cycles: 2
Encoding: I1 0 0 1 0 0 1 1
Operation: MOVC
(A) +- «A) + (DPTR»
MOVC A,@A + PC
Bytes:
Cycles: 2
Encoding: I1 0 0 0 0 0 1 1
Operation: MOVC
(PC) +- (PC) + 1
(A) +- «A) + (PC»
9-53
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVX <dest-byte > , < src-byte >
Function: Move External
Description: The MOVX instructions transfer data between the Accumulator and a byte of external data
,memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of Rq or Rl in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
, .output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the low-
order eight bits (DPL) with data., The P2 Special Function Register retains its previous con-
tents while the P2,output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional ,
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
, output high-order address bits to P2 followed by a MOVX instruction using RO or Rl.
Example: An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port O. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and' 1 contain 12H and 34H.
Location 34H,of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@Rl
MOVX @RO,A
copies the value 56H into both the Accumulator and external RAM location 12H.
9-54
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVX A,@Ri
Bytes:
Cycles: 2
Encoding: I 1 110 001
Operation: MOVX
(A) - «Ri»
MOVX A,@DPTR
Bytes:
Cycles: 2
Encoding: I 1 110 0000
Operation: MOVX
(A) - «DPTR»
MOVX @Ri,A
Bytes:
Cycles: 2
Encoding: I1 1 1 1 001
Operation: MOVX
«Ri» - (A)
MOVX @DPTR,A
Bytes:
Cycles: 2
Encoding: I 1 1 1 1 o0 0 0
Operation: MOVX
(DPTR)-(A)
9-55
inter MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
NOP
Function: No Operation
Description: Execution continues at the following instruction. Other than the PC, no registers or flags are
affected. .
Example: It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,
CLR P2.7
NOP
NOP
NOP
NOP
SETB P2.7
Bytes:
Cycles:
Encoding: 1 0 0 0 0 1- 0 0 0 0 1
Operation: NOP
(pC)-(PC) +
MUL AB
Function: Multiply
Description: MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left inthe Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otehrwise it is cleared.
The carry flag is always cleared.
Example: Originally the Accumulator holds the value 80 (50H). Register. B holds the value 160 (OAOH).
The instruction,
MUL AB
will give the product 12,800 (32ooH), so B is changed to 32H (ooIIOOlOB) and the Accumula-
tor is cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles: 4
Encoding: 1 1 0 1 0 0 1 0 0
Operation: MUL
(Ah-o - (A) X (B)
(BhS-8
9-56
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL <dest-byte> <src-byte>
Function: Logical-OR for byte variables
Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the Accumulator holds OC3H (l 100001 IB) and RO holds 55H (OlOlOIOIB) then the in-
struction,
ORL A,RO
will leave the Accumulator holding the value OD7H (1IOIOl1IB).
When the destination is a directly addressed byte, the instruction can set combinations of bits
. in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable computed
in the Accumulator at run-time. The instruction,
ORL, PI,#OOIIOOIOB
will set bits 5, 4, and I of output Port 1.
ORL A,Rn
Bytes:
Cycles:
Encoding: I0 1 0 0 1 r r r
Operation: ORL
(A) ~ (A) V (Rn)
9-57
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL A,dlrect
Bytes: 2
Cycles:
Encoding: I 0 1 00 o1 0 1 direct address
Operation: ORL
(A) - (A) V (direct)
ORL A,@Ri
Bytes:
Cycles:
Encoding: 1 01
00 o1 1 i
Operation: ORL
(A) - (A) V «Ri»
ORL A, # data
. Bytes: 2
Cycles:
".
Encoding: I0 1 o0 I o 1 0 0 immediate data
I
Operation: ORL
(A) - (A) V #data
ORL dlrect,A
Bytes: 2
Cycles:
Encoding: I 0 1 00 001 0 direct address
Operation: ORL
(direct) - (direct) V (A)
ORL direct, # data
Bytes: 3
Cycles: 2
Encoding: 1 01
o0 001 1 direct addr. immediate data
Operation: ORL
(direct) - (direct) V #data
9-58
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL C,<src-blt>
Function: Logical-OR for bit variables
Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state·
otherwise. A slash ("I") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0:
MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN PIO
ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7
ORL C,/OV ;OR CARRY WITH THE INVERSE OF OV.
ORL C,bit
Bytes: 2
Cycles: 2
Encoding: 1 1 001 0 bit address
1 01
Operation: ORL
(C) -- (C) V (bit)
ORL C,Ibit
_ Bytes: 2
Cycles: 2
Encoding: I 1 010 0000 bit address
Operation: ORL
(C) -- (C) V (bit)
9-59
intJ MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
POP direct
Function: Pop from stack.
Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly ad-
dressed byte indicated. No flags are affected.
Example: The Stack Pointer originally contains the value' 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OlH, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes: 2
Cycles: 2
Encoding: LI _1_1_0_1-L_O_'_0_0_0---, direct address
Operation: POP
(direct) -+-- «SP»
(SP) -+-- (SP) - 1
PUSH direct
Function: Push onto stack
Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affect-
ed.
Example: On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instrnction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBH and store 23H and OlH in internal RAM locations
OAH and OBH, respectively.
Bytes: 2
Cycles: 2
Encoding: 11100 0000 direct address
Operation: PUSH
(SP) -+-- (SP) + 1
«SP» -+-- (direct)
9-60
inter MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RET
Function: Return from subroutine
Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.
Example: The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH
contain the values 23H and OlH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.
Bytes:
Cycles: 2
Encoding: I0 0 1 0 0 0 1 0
Operation: RET
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1
RETI
FunctIon: Return from interrupt
Description: RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.
Example: The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAH and OBH contain the
values 23H and OlH, respectively. The instruction,
RET!
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
Bytes:
Cycles: 2
Encoding: _ _~_O_O_1_0--,
,-1_O_O
Operation: RET!
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1
9-61
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RL A
Function: Rotate Ac.cumulator Left
Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
Example: The Accumulator holds the value OC5H (1IOOOlOlB). The instruction.
RLA
leaves the Accumulator holding the value 8BH (IOOOlOllB) with -the carry unaffected.
Bytes:
Cycles:
Encoding: I °0 1 0 0 0 1 1
Operation: RL
(An + I) - (An) n = 0 - 6
(AO) - (A7)
RLC A
Function: Rotate Accumulator Left through the Carry flag
Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No
other flags are affected. .
Example: The Accumulator holds the value OC5H (1IOOOlOlB). and the carry is zero. The instruction.
RLC A
leaves the Accumulator holding the value 8BH (IOOOIOlOB) with the carry set.
Bytes:
Cycles:
Encoding: LI_o_O_1_--,-_O_O_1_1....J
Operation: RLC
(An + 1) - (An) n = 0 -:- 6
(AO) - (C)
(C) -(A7)
9-62
intJ MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTIO!ll SET
RR A
Function: Rotate Accumulator Right
Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
Example: The Accumulator holds the value OC5H (I 1000 10 lB). The instruction,
RR A
leaves the Accumulator holding the value OE2H (11 1000 lOB) with the carry unaffected.
Bytes:
Cycles:
Encoding: I0 0 0 0 I0 0 1 1
Operation: RR
(An) +- (An + I) n = 0 - 6
(A7)+- (AO)
RRC A
Function: Rotate Accumulator Right through Carry flag
Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.
Example: The Accumulatorholds the value OC5H (llOOOlOlB), the carry is zero. The instruction,
RRC A
.leaves the Accumulator holding the value 62 (01 1000 lOB) with the c!lrry set.
Bytes:
Cycles:
Encoding: I0 0 0 1 O. 0 1 1
Operation: RRC
(An) +- (An t I) n = 0 - 6
(A7) +- (C)
(C) +- (AO)
9-63
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SETB <bit>
Function: Set Bit
Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.
Example: The carry flag is cleared. Output Port I has been written with the value 34H (OOllOlOOB). The
instructions,
SETB C
SETB Pl.O
wi11leave the carry flag set to 1 and change the data output on Port 1 to 3SH (OOllOlOlB).
SETB C
Bytes:
Cycles:
Encoding: I110 1 001 1
Operation: SETB
(C)~ 1
SETB bit
Bytes: 2,
Cycles:
Encoding: I1101 001 0 bit address
Operation: SETB
(bit) +- 1
9-64
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SJMP rei
Function: Short Jump
Description: Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes
preceding this instruction to 127 bytes following it.
Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP RELADR
will assemble into location OlOOH. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore,
the displacement byte of the instruction will be the relative offset (OI23H-OI02H) = 21H. Put
another way, an SJMP with a displacement ofOFEH would be a one-instruction infinite loop.)
Bytes: 2
Cycles: 2
Encoding: I1 0 0 0 0 0 0 0 reI. address
Operation: SJMP
(PC) +- (PC) + 2
. (PC) +- (PC) + rei
,9-65
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SUBB A,<src-byte>
Function: Subtract with. borrow
Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or imme-
diate.
Exarriple: The Accumulator holds OC9H (llOOlOOlB), register 2 holds S4H (0 10 10 1OOB), and the carry
flag is set. The instruction,
SUBB A,R2
will leave the value 74H (01 110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus S4H is 7SH. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction. .
SUBB A,Rn
Bytes:
Cycles:
Encoding: LI_1_0_0_1...J.._1_r_r_r..j
Operation: SUBB
(A) ~ (A) - (C) - (Rn)
9-66
intJ MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SUBB A,direct
Bytes: 2
Cycles:
Encoding: 1 1 001 o1 0 1 direct address
Operation: SUBB
(A) - (A) - (C) - (direct)
SUBB A,@Ri
Bytes:
Cycles:
Encoding: 11 001 011
Operation: SUBB
(A) - (A) - (C) - «Ri»
SUBB A, # data
Bytes: 2
Cycles:
Encoding: 11 001 o1 0 0 immediate data
1
Operation: SUBB
(A) - (A) - (C) - #data
SWAP A
Function: Swap nibbles within the Accumulator
Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
Example: The Accumulator holds the value OC5H (lJOOO101B). The instruction,
SWAP A
leaves the Accumulator holding the value 5CH (0101 1100B).
Bytes:
Cycles:
Encoding: I1 1 0 0 0 1 0 0
Operation: SWAP
(A3-O) ~ (A7-4)
9-67
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XCH A,<byte>
Function: Exchange Accumulator with byte variable
Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct; or register-indirect addressing.
Example: RO contains the address 20H. The Accumulator holds the value 3FH (OOlllllIB). Internal
RAM location 20H holds the'value 75H (Ol1lOlOlB). The instruction,
XCH A,@RO
will leave RAM location 20H holding the values 3FH (0011 11 11 B) and 75H (Ol1lOlOlB) in
the accumulator.
XCH A,Rn
Bytes:
Cycles:
Encoding: 1 1 100 1, r r r
Operation: , XCH
(A) -;. (Rn)
XCH A,direct
Bytes: 2
Cycles:
Encoding: 11 100 o1 0 1 direct address
Operation: XCH
(A) -;. (direct)
XCH A,@Ri
Bytes:
Cycles:
Encoding: 1 1 100 011
Operation: XCH
(A) -;. «Ri»
9-68
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XCHD A,@RI
Function: Exchange Digit
Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.
Example: RO contains the address 20H. The Accumulator holds the value 36H (001101 lOB). Internal
RAM location 20H holds the value 75H (OllIOlOIB). The instruction,
XCHD A,@RO
will leave RAM location 20H holding the value 76H (Oil 101 lOB) and 35H (OOllOlOlB) in the
Accumulator.
Bytes:
Cycles:
Encoding: _1_1_0_1--,-_0_1_1--,
LI
Operation: XCHD
(A3.Q) ~ «Ri3.Q»
XRL <dest-byte>,<src-byte>
Function: Logical Exclusive-OR for byte variables
Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
(Note: When this illstruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example: If the Accumulator holds OC3H (IlOOOOllB) and register 0 holds OAAH (10 1010 lOB) then
the instruction, .
XRL A,RO
will leave the Accumulator holding the value 69H (OllOlOOlB).
When the destination is a directly addressed byte, this instruction can complement combina-
tions of bits in any RAM location or hardware register. The pattern of bits to be complement-
ed is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL Pl,#OOllOOOlB
will complement bits 5, 4, and 0 of output Port 1.
9-69
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL A,Rn
Bytes:
Cycles:
Encoding: '1 01 1 0 1 'r r r
Operation: XRL
(A) +- (A) ¥ (Rn)
XRL A,direct
Bytes: 2
Cycles:
Encoding: I0 1 1 0 o1 0 1 direct address
Operation: XRL
(A) +- (A) ¥ (direct)
XRL A,@RI
Bytes:
Cycles:
Encoding: I0 1 1 0 o1 1 i
Operation: XRL
(A) +- (A) ¥«Ri»
XRL A,#data
Bytes: 2
Cycles:
Encoding:
1 01 1 0 o1 0 0 immediate data
I
Operation: XRL
(A) +- (A) ¥ #data
XRL dlrect,A'
Bytes: 2
Cycles:
Encoding: I0 1 1 0 001 0 direct address
Operation: XRL
(direct) +- (direct) ¥ (A)
9-70
inter MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL direct,#data
Bytes: 3
Cycles: 2
Encoding: I0 1 1 0 0 0 1 1 direct address immediate data
Operation: XRL
(direct) <E- (direct) V #data
9-71
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MCS® . . 51 Data Sheets,
Application Notes,
10
Development Support
Tools and Index
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intJ MCS®-51
8-BIT CONTROL-ORIENTED MICROCOMPUTERS
8031/8051
8031 AH/8051 AH
8032AH/8052AH
8751H/8751H-8
• High Performance HMOS Process
• Boolean Processor
• 2-Level
Internal Timers/Event Counters
• Programmable
Bit-Addressable RAM
• 32 I/O Lines
Interrupt Priority Structure
• Full Duplex Serial
• 64K Program(Four 8-Bit Ports)
•
Channel
111 Instructions (64 Single-Cycle)
• Security Feature Protects EPROM Parts
Memory Space
• 64K Data Memory Space
• Against Software Piracy
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, inch,Jding multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
Internal Memory Timersl
Device Interrupts
Program Event Counters
Data
8052AH 8Kx8ROM 256x8 RAM 3 x 16-Bit 6
8051AH 4Kx8ROM 128x8RAM 2 x 16-Bit 5
8051 4Kx8 ROM 128x8RAM 2 x 16-Bit 5
8032AH none 256x8 RAM 3 x 16-Bit 6
8031AH none 128x8RAM 2 x 16-Bit 5
8031 none 128x8RAM 2 x 16-Bit 5
8751H 4Kx8 EPROM 128x8 RAM 2 x 16-Bit 5
8751H-8 4Kx8 EPROM 128x8 RAM 2 x 16-Bit 5
The 8751H is an EPROM version of the 8051AH; that is, the on-chip Program Memory can be electrically
programmed, and can be erased by exposure to ultraviolet light. It is fully compatible with its predecessor, the
8751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the
EPROM against unauthorized read-out, and a programmable baud rate modification bit (SMOD). The 8751H-8
is identical to the 8751 H but only operates up to 8 MHz.
October 1987
10-1 Order Number: 270048-003
inter MCS®"51
POD PO 1 P2~P21
r----~-----·~~~ .~~~------------~,
Vcc
y==-l .
~
= I
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I r---.,---.
PHii
ALE
Ei
RST~
I L.....---r....L..--I
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XTAll
o P1.0-Pl." P3.0-P3.7
~
270048-1
Figure 1. MC.5®-S1 Block Diagram
PIN DESCR!PT!ONS Port 0 pins that have 1S written to them float, and in
that state can be used as high-impedance inputs.
vee Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Supply voltage. Data Memory. In this application it uses strong inter-
na! pull ups when emitting 1S and can source and
sink a LS TTL inputs.
vss
Port 0 also receives the code bytes during program-
Circuit ground. ming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pullups are required during
PortO program verification. .
Port 0 is an a-bit open drain bidirectional 110 port. As
an output port each pin can sink a Ls TTL inputs..
10-2
intJ MCS®-51
80s2·80l2 ONLY INDEX
..
L{=~
CORNER
f~~
"! C"! '": U"
" ;;: ii: ii: ..,.; uz ~~
;;:
. .. .' N
" -• o· .. ;
•
...
Pl.0 .VCC
P1.S ,. PO.4
:31"
Pl.l PO.O ADO
Pl.2 PO.l ADI Pl.6 pO.S
P1.l PO.2 AD2 P1.7 : ;31 PO,6
Pl.4 PO.l ADl RST ,,' .n PO.7
P1.S PO.4 AD4 Pl.O ,,' :U EA
Pl.6 PO.S ADS NC n. Ne
"
Pl.7
RST
RXD Pl.O
PO.6 ADS
PO.7 AD7
EAlVpp
Pl.l n.
Pl.2
Pl.l n.
. "
."
ALE
PSEN .
:31 P2.7
TXD Pl. 1 ALEIPROG P3.4 :3C1 P2.6
INTO Pl.2 PSEN P3.S
"
17: 'n P2.S
P2.7 Als
INTI Pl.l
TO Pl.4 P2.6A14 •••••••• • :~
Tl Pl.s P2.S All ~ ~ ~ ~ ~~~~~~~
WR Pl.6 P2.4 A12
:! i! > Do a. D. Go a.
Do D..
><><
AD Pl.7 P2.l All 270048-3
XTAL2 P2.2 Al0
XTAll P2.1 A9 Pad
vss P2.0 A8
270048-2
Pin
Figure 2. MCS®-51 Connections
Port 1 ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
Port 1 is an 8-bit bidirectional I/O port with internal the P2 Special Function Register.
pullups. The Port 1 'output buffers can sink/source 4
LS TTL inputs. Port 1 pins that have 1s written to Port 2 also receives the high-order address bits dur-
them are pulled high by the internal pullups, and in ing programming of the EPROM parts and during
that state can be used as inputs. As inputs, Port 1 program verification of the ROM and EPROM parts.
pins that are externally being pulled low wiii source
current (ilL on the data sheet) because of the inter-
nal pullups. Port 3
Port 1 also receives the low-order address bytes Port 3 is an 8·bit bidirectional I/O port with internal
during programming of the EPROM parts and during pullups. The Port 3 output buffers can sink/source 4
program verification of the ROM and EPROM parts. lS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups" and in
In the 8032AH and B052AH, Port 1 pins P1.0 and that state can be used as inputs. As inputs, Port 3
P1.1 also serve the T2 and T2EX functions, respec- pins that are externally being pulled low wiii source
tively. current (ill on the data sheet) because of the pull-
ups.
Port 2 Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port 2 is an 8~bit bidirectional 1/0 port with internal
pullups. The Port 2 output buffers can sink/source 4 Port
Alternative Function
lS TTL inputs. Port 2 pins that have 1s written to Pin
them are pulled high by the internal pull ups, and in P3.0 RXD (serial input port)
that state can be used as inputs. As inputs, Port 2 P3.1 TXD (serial output port)
pins that are externally being pulled low wiii source P3.2 INTO (external interrupt 0)
current (ill on the data sheet) because of the inter- P3.3 INT1 (external interrupt 1)
nal pullups. P3.4 TO (Timer 0 external input)
P3.5 I!JTimer 1 external input)
Port 2 emits the high-order address byte during P3.6 WR (external data memory write strobe)
fetches from external Program Memory and during P3.7 RD (external data memory read strobe)
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Dur-
10-3
intJ
RST Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
Reset input. A high on this pin for two machine cy- code from any location in external Program Memory.
cles while the oscillator is running resets the device.
This pin also receives the 21 V programming supply
voltage (VPP) during programming of the EPROM
ALE/PROG parts.
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external XTAL1
memory. This pin is also the program pulse input
(PROG) during programming of the EPROM parts. Input to the inverting oscillator amplifier.
In normal operation ALE is emitted' at a constant
,rate of % the oscillator frequency, and may be used XTAL2
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac- Output from the inverting oscillator amplifier.
cess to external Data Memory.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAl2 are the input and output, respec-
Program Store Enable is the read strobe to external tively, of an inverting amplifier which can be config-
Program Memory. ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator .
When the device is executing code from external may be used. More detailed information concerning
Program Memory, PSEN is activated twice each ma- the use of the on-chip oscillator is available in Appli-
chine cycle, except that two PSEN activations are cation Note AP-155,"Oscillators for Microcontrol-
skipped during each access to external Data Memo: lers."
ry.
To drive the device from an external clock source,
XTAl1 should be grounded, while XTAl2 is driven,
EA/VPP as shown in Figure 4. There are no requirements on
the duty cycle of the external clock Signal, since the
External Access enable EA must be strapped to input to the internal clocking circuitry is through a
VSS in order to enable any MeS-51 device to fetch divide-by-two flip-flop, but minimum and maximum
code froiT) external Program memory locations 0 to high and low times specified on the Data Sheet must
OFFFH (0 to 1FFFH, in the 8032AH and 8052AH). be observed. .
r--11
C2
, I XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
---i XTAL2
-L
D
____--I XTAL 1
XTAL1
Cl
vss "'---1 vss
_L.
270048-4 270048-5
Cl , C2 ~ 30 pF ± 10 pF for Crystals
~ 40 pF ± 10 pF for Ceramic Resonators Figure 4. External Drive Configuration
Figure 3. Oscillator Connections
10-4
inter MCS®·51
ABSOLUTE MAXIMUM RATINGS· "Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias ...... O·C to 70·C age to the device. This is a stress rating only and
Storage Temperature .......... - 65·C to + 150·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAIVpp Pin to Vss ... -0.5V to + 21.5V tional sections of this specification is not implied Ex-
Voltage on Any Other Pin to Vss .... - 0.5V to + 7V posure to absolute maximum rating conditions for
Power Dissipation ..............•........... 1.5W extended periods may affect device reliability.
D.C. CHARACTERISTICS TA = ,
0·Ct070·C·Vee = 5V ±10%;Vss = ov
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage (Except EA Pin of -0.5 0.8 V
8751 H & 8751 H-8)
VIL1 Input Low Voltage to EA Pin of 0 0.7 V
8751 H & 8751H-8
VIH Input High Voltage (Except XTAL2, 2.0 Vee + 0.5 V
RST)
VIH1 Input High Voltage to XTAL2, RST 2.5 Vee + 0.5 V XTAL1 = VSS
VOL Output Low Voltage (Ports 1, 2, 3)" 0.45 V IOL = 1.6 mA
VOL1 Output Low Voltage (Port 0, ALE, PSEN)*
8751 H, 8751 H-8 0.60 V IOL = 3.2mA
0.45 V IOL = 2.4 mA
All Others 0.45 V IOL = 3.2mA
VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 V IOH = -80/LA
VOH1 Output High Voltage (Port 0 in 2.4 V IOH = -400/LA
External Bus Mode)
IlL Logical 0 Input Current (Ports 1, 2, 3,
RST) 8032AH, B052AH -800 /LA VIN = 0.45V
All Others -500 /LA VIN = 0.45V
11L1 Logical 0 Input Current to EA Pin of -15 mA
B751 H & 8751 H-8 Only
1112 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45V
III Input Leakage Current (Port 0)
B751 H & 8751 H-8 ±100 /LA 0.45 s VIN s Vee
All Others ±10 /LA 0-45 s VIN s Vee
IIH Logical 1 Input Current to EA Pin Qf 500 /LA
8751 H & 8751 H-B
IIH1 Input Current to RST to Activate Reset 500 /LA VIN < (Vee - 1.5V)
Icc Power Supply Current:
8031/8051 160 mA
8031AH/8051AH 125 mA All Outputs
8032AH/B052AH 175 mA Disconnected;
8751 H/8751 H-8 250 mA EA = Vee
Cia Pin CapaCitance 10 pF Test freq = 1 MHz
• NOTE:
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make .1-to-O
transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
10-5
inter MCS®·51
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
load Capacitance for Port 0, ALE, and PSEN = 100 pF;
load Capacitance for All Other Outputs = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TClCl Oscillator Frequency 3.5 12.0 MHz
TlHll ALE Pulse Width 127 2TClCl-40 ns
TAVll Address Valid to ALE low 43 TClCl-40 ns
TllAX Address Hold after ALE low 48 TClCl-35 ns
TlLlV ALE low to Valid Instr In
8751H 183 4TClCl-150 ns
All Others 233 4TClCl":'100 ns
TLLPl ALE low to PSEN low 58 TClCL-25 ns
TPLPH PSEN Pulse Width
8751H 190 3TClCl-60 ns
All Others 215 3TClCl-35 ns
TPLIV PSEN Low to Valid Instr In
8751H 100 3TClCL-150 ns
All Others 125 3TCLCl-'125 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 63 TClCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCl-8 ns
TAVIV Address to Valid Instr In
8751H 267 5TCLCL-150 ns
All Others 302 5TClCl-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 400 6TClCL-100 ns
TWlWH WR Pulse Width 400 6TClCL-100 ns
TRLDV RD low to Vafid Data In 252 5TCLCL-165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 97 2TCLCL-70 ns
TllDV ALE low to Valid Data In 517 8TCLCl-150 ns
TAVDV Address to Valid Data In 585 9TCLCl-165 ns
TllWl ALE Low to RD or WR Low 200 300 3TCLCl-50 3TClCL+50 ns
TAVWL Address to RD or WR low 203 ' 4TClCL -130 ns
TQVWX Data Valid to WR Transition
8751H 13 TClCL-70 ns
All Others 23 TClCL-60 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHQX Data Hold after WR 33 TClCl-50 ns
TRlAZ AD low to Address Float 20 20 ns
TWHlH RD or WR High to ALE High
8751H 33 133 TClCL-50 TClCl+50 ns
All Others 43 123 TClCL-40 TCLCL+40 ns
NOTE:
'This table does not include the B751-BAC. characteristics (see next page).
10-6
intJ MCS®·51
This Table is only for the 8751H·8
A.C. CHARACTERISTICSTA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
8 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 8.0 MHz
TLHLL ALE Pulse Width 210 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 85 TCLCL-40 ns
TLLAX Address Hold after ALE Low 90 TCLCL-35 ns·
TLLlV ALE Low to Valid Instr In 350 4TCLCL-150 ns
TLLPL ALE Low to PSEN Low 100 TCLCL-25 ns
TPLPH PSEN Pulse Width 315 3TCLCL-60 ns
TPLIV PSEN Low to Valid Instr In 225 3TCLCL-150 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 105 TCLCL-20 ns
TPXAV PSEN to Address Valid 117 TCLCL-8 ns
TAVIV Address to Valid Instr In 475 5TCLCL-150 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 650 6TCLCL-100 ns
TWLWH WR Pulse Width 650 6TCLCL-100 ns
TRLDV AD Low to Valid Data In 460 5TCLCL-165 ns
TAHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 180 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 850 8TCLCL-150 ns
TAVDV Address to Valid Data In 960 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 325 425 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 370 4TCLCL-130 ns
TQVWX Data Valid to WA Transition 55 TCLCL-70 ns
TQVWH Data Valid to WR High 125 7TCLCL-150 ns
TWHQX Data Hold after WR 75 TCLCL-50 ns
TRLAZ RD Low to Address Float 20 20 ns
TWHLH AD or WR High to ALE High 75 175 TCLCL-50 TCLCL+50 ns
10-7
inter MCS®-S1
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270048-6
10-8
inter MCS®·51
EXTERNAL DATA MEMORY READ CYCLE
ALE
1 - - - - - T L L O y ------<~
PORTO
PORT 2 P2.0-P2.7 OR A8-A1S FROM DPH A8-A 15 FROM PCH
270048-7
EXTERNAL DATA MEMORY WRITE CYCLE
I+--~ T,LHLL TWHLH
ALE
TLLWL-<~·"o----TWLWH---"""'~
Tavwx
I+-_I-':':;;'~ 1--+---TaVWH----~
PORTO DATA OUT
PORT 2 P2.0-P2.7 OR A8-Ais FROM DPH A8-A1S FROM PCH
270048-8
10-9
inter
SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to 70·C; VCC = 5V ±10%; VSS = OV;
Test Conditions: TA Load Capacitance = 80 pF .
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL ,...s
TQVXH Output Data Setup to Clock Rising 700 1OTCLCL -133 ns
Edge
TXHQX Output Data Hold after Clock 50 2TCLCL-117 ns
Rising Edge
TXHDX Input Data Hold after Clock Rising 0 0 ns
Edge
TXHDV Clock Rising Edge to Input Data 700 1OTCLCL -133 ns
Valid ..
SHIFT REGISTER TIMING WAVEFORMS
1-4-'OVI!H+1 ~UHQII I·
-------r\----~X X~~~X~___JX~__~X~~-JX~·---JX~--~7
I j .. t
~
SETlI
WAITE TO SBUf ""D' --l I-""D'
t
~
SET AI
ClUA __ r
270048-9
10-10
inter MCS®-51
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency (except 8751 H-8) 3.5 12 MHz
8751H-8 3.5 8 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
I.------TCLCL -------<~
270048-10
A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4=X >
045
20
0.8
TEST POINTS < 2.0
08
)C
270048-11
A.C. Tesling: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
10-11
MCS®-51
EPROM CHARACTERISTICS
Table 3 EPROM Programming Modes
Mode RST . PSEN ALE . EA P2.7 P2.6 P2.S P2.4
Program 1 0 O· VPP 1 0 X X
Inhibit 1 0 1 X 1 0 X X
Verify 1 0 1 1 0 0 X X
Security Set 1 0 O· VPP 1 1 X X
NOTE.
"1" = logic high for that pin "VPP" = + 21V ± 0.5V
"0" = logic low for that pin ·ALE is pulsed low for 50 ms.
"X" = "don't care"
Programming the EPROM Note that the EAIVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for .
To be programmed, the part must be running with a any amount of time. Even a narrow glitch above that
4 to 6 MHz oscillator. (The reason the oscillator voltage level can cause permanent damage to the
needs to be running is that the internal bus is being device. The VPP source should be well regulated
used to transfer address and program data to appro- and free of glitches.
priate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0-P2.3 of Port 2, while the code byte to be Program Verification
programmed into that location is applied to Port o.
If the Security Bit has not been programmed, the on-
The other Port 2 pins, and RST, PSEN, and EA
chip Program Memory can be read out for verifica-
should be held at the "Program" levels indicated in
tion purposes, if desired, either during or after the
Table 3. ALE is pulsed low for 50 ms to program the
programming operation. The address of the Program
code byte into the addressed EPROM location. The
Memory location to be read is applied to Port 1 and
setup is shown in Figure 5.
pins P2.0-P2.3. The other pins should be held atthe
"Verify" levels indicated in Table 3. The contents of
Normally EA is held at a logic high until just before
the addressed location will come out on Port O. Ex-
ALE is to be pulsed. Then EA is raised to + 21 V,
ternal pullups are required on Port 0 for this opera-
ALE is pulsed, and then EA is returned to a logic
tion.
high. Waveforms and detailed timing specifications
are shown in later sectio,ns of this data sheet. The setup, which is shown in Figure 6, is the· same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
+SV
low read strobe.
+5V
8751H
PH
P2.S
P2.6
P2.7
.--_---1 XTAL2
L--'+-H XTAL1
VSS
VSS
270048-12
Figure 5. Programming Configuration
270048-13
Figure 6. Program Verification
10-12
inter MCS®-51
EPROM Security +SV
X = "DON'T CARE"
The security feature consists of a "locking" bit which
when programmed denies electrical access by any VCC
external means to the on-chip Program Memory. PI
The bit is programmed as shown in Figure 7. The
PO X
setup and procedure are the same as for normal P2.0-
EPROM programming, except that P2.6 is held at a P2.3
8751H
logic high. Port 0, Port 1, and pins P2.0-P2.3 may be
in any state. The other pins should be held at the P2.4 ALE ALEIPROG
"Security" levels indicated in Table 3. P2.5
P2.6
Once the Security Bit h~s been programmed, it can P2.7 Eli EA.'VPP
be cleared only by full erasure of the Program Mem- XTAL2
ory. While it is programmed, the internal Program
RST VIHI
Memory can not be read out, the device can not be
XTAL1
further programmed, and it can not execute out of
external program memory. Erasing the EPROM, VSS PSEN
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.
270048-14
Figure 7. Programming the Security Bit
Erasure Characteristics
The recommended erasure procedure is exposure
Erasure of the EPROM begins to occur when the
to ultraviolet light (at 2537 Angstroms) to an integrat-
chip is exposed to light with wavelengths shorter
ed dose of at least 15 W-sec/cm 2 . Exposing the
than approximately 4,000 Angstroms. Since sunlight
EPROM to an ultraviolet lamp of 12,000 /kW/cm 2
and fluorescent lighting have wavelengths in this
rating for 20 to 30 minutes, at a distance of about 1
range, exposure to these light sources over an ex- inch, should be sufficient.
tended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadver-
Erasure leaves the array in an all 1s state.
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
TA= 21°C to 27°C; VCC = 5V ±10%; VSS = OV
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 20.5 21.5 V
IPP Programming Supply Current 30 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to VPP 48TCLCL
TSHGL VPP Setup to PROG Low 10 /ks
TGHSL VPP Hold after PROG 10 /ks
TGLGH PROGWidth 45 55 ms
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Oata Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
10-13
inter MCS@·51
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
Pl.0-fll.7 "\.
ADDRESS ADDRESS
P2.0-fl2.3 /
PORTO DATA IN
- _TAVQV
DATA OUT
TDVGL I- _ .• _TGHDX
TAVGL ~ I- TGHAX
'LE/PROG
,~
TSHGL TGHSL
TGLGH
21V:t .SV
\
Ei./vpp ~ TTL HIGH TTL HIGH TTL HIGH
, --
TEHSH
I- TELQV_ _TEHQZ
P2.7
(ENABLE)
J J
270048-15
For programming conditions see Figure 5. For verification conditions see Figure 6.
10-14
8051AHP
MCS®-51 FAMILY
8-BIT CONTROL-ORIENTED MICROCONTROLLER
WITH PROTECTED ROM
• High Performance HMOS Process • .Boolean Processor
• Internal Timers/Event Counters • Bit-Addressable RAM
• 2-Level Interrupt Priority Structure • Programmable Full Duplex Serial
• 32 I/O Lines (Four 8-Bit Ports) Channel
• 4K Program Memory Space • 111 Instructions (64 Single-Cycle)
• .Protection Feature Protects ROM Parts • 4K Data Memory Space*
Against Software Piracy *Expandable to 64K
• Available in 40 Pin Plastic and CERDIP
Packages
(See Packaging Outlines and Dimensions Order #231369)
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
MCS-51 HMOS Internal Memory Timers!
Interrupts
Family Device Program Event Counters
Data
8051AH 4Kx 8 ROM 128 x 8 RAM 2 x 16-Bit 5
8051AHP 4Kx8 ROM 128 x 8 RAM 2 x 16-Bit 5
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
September 1987
10-15 Order Number: 270279-002
8051AHP
PQ O-PO 1 P2o-P21
Yee
r --- - -- - ---~tttt;- rl±!t~- - - ----------,
I
~ I
.tiI I
I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I
I
I
I
I
I
I
I
I r-----,,----,
"E.
ALE
PI.D-P1.1 P3.0-P37
270279-1
Figure 1. MCS®·51 Block Diagram
PIN DESCRIPTIONS Port 0 is also the multiplexed low·order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
Vee nal pullups v-when emitting 1s and can SOUiC6 and
sink a LS TTL inputs.
Supply Voltage.
Port 0 also receives the code bytes during program-
ming of the EPROM parts, and outputs the code
Vss bytes during program verification of the ROM and
EPROM parts. External pullups are required during
Circuit ground. program verification.
Port 0 Port 1
Port 0 is an a-bit open drain bidirectional 1/0 port. As Port 1 is an a-bit bidirectional I/O port with internal
an output port each pin can sink a LS TTL inputs. pullups. The Port 1 output buffers can sink source 4
LS TTL inputs. Port 1 pins that have 1s written to
Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.
10-16
intJ 8051AHP
P1.0 vee
Pl.l PO.O ADO
P1.2 PO.l ADI
P1.3 PO.2 AD2
Pl.4 PO.3 AD3
P1.S PO.4 AD4
Pl.6 PO.S ADS
P1.7 PO.6 AD6
RST PO.7 AD7
RXD P3.0 10 EAlVpp
TXD P3.1 11 ALE'PROG
INTO P3.2 12 PSEN
INTI P3.3 13 P2.7 AIS
TO P3.4 P2.6A14
TI P3.S P2.S A13
WR P3.6 P2.4 A12
Rii P3.7 P2.3 Al1
XTAL2 P2.2 Al0
XTALI P2.1 A9
VSS P2.0 AS
270279-2
Pin
Figure 2. MCS®-51 Connections
them are pulled high by the internal pullups, and in Port 3
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source Port 3 is an S-bit bidirectional I/O port with internal
current (IlL, on the data sheet) because of the inter- pullups. The Port 3 output buffers can sink/source 4
nal pullups. LS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
Port 2 pins that are externally being pulled low will source
current (IlL on the data sheet) because of the pull-
Port 2 is an S-bit bidirectional I/O port with internal ups.
pullups. The Port 2 output buffers can sink/source 4
LS TTL inputs. Port 2 pins that have 1s written to Port 3 also serves the functions of various special
them are pulled high by the internal pullups, and in features of the MCS-51 Family, as listed below:
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the inter- Port
Alternative Function
nal pullups. Pin
P3.0 RXD (serial input port)
Port 2 emits the high-order address byte during
P3.1 TXD (serial output port)
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit P3.2 INTO (external interrupt 0)
'addresses (MOVX @DPTR). In this application it P3.3 INT1 (external interrupt 1)
uses strong internal pullups when emitting 1s. Bits P3.4 TO (Timer 0 external input)
P2.4 through P2.7 are forced to 0, effectively limiting P3.5 T1 (Timer 1 external'input)
external Data and Code space to 4K each in the P3.6 WR (external data memory write strobe)
S051AHP during external accesses'. During access- P3.7 RD (external data memory read strobe)
es to external Data Memory that use S-bit addresses
(MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order address bits dur-
ing programming of the EPROM parts and during
program verification of the ROM and EPROM parts .
• Protection feature
10-17
B051AHP
RST XTAL1
Reset input. A high on this pin for two machine cy- Input to the inverting oscillator amplifier.
cles while the oscillator is running resets the device.
XTAL2
ALE/PROG
Output from the inyerting oscillator amplifier.
Address Latch Enable output pulse for latching the
low byte of the' address during accesses to external
memory. OSCILLATOR CHARACTERISTICS
In normal operation ALE is emitted at a constant XTAL 1 and XTAL2 are the input and output, respec-
rate of % the oscillator frequency, and may be used tively, of an inverting amplifier which can be config-
for external timing or clocking purposes. Note, how- ured for use as an on-chip oscillatbr, as shown in
ever, that one ALE pulse is skipped during each ac- Figure 3. Either a quartz crystal or ceramic resonator
cess to external Data Memory. may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, "Oscillators for Microcontrol-
lers."
Program Store Enable is the read strobe to external To drive the device from an external clock source,
Program Memory. XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
When the device is executing code from external the duty cycle 'of the external clock Signal, since the
Program Memory, PSEN is activated twice each ma- input to the internal clocking circuitry is through a
chine cycle, except that two PSEN activations are divide-by-two flip-flop, but minimum ,and maximum
skipped during each access to external Data Memo- high and low times specified on the Data Sheet must
ry. be observed.
EA/Vpp EXTERNAL
OSCILLATOR ---...,.....f ,XTAL2
External Access enable EA should be strapped to SIGNAL
Vee for internal program executions. EA must be
strapped to Vss in order to enable any MeS-51 de-
vice to fetch code from external Program memory
locations 0 to OFFFH.
~ XTAL1
C2
rl T
..L
IXTAL2 ....-...,.....f vss
0 270279-5
Figure 4. External Drive Configuration
XTAL1
C1
DESIGN CONSIDERATION
vss
The 8051AHP cannot access external program or
Data memory above 4K. This means that the follow-
270279-4 ing instructions that use the Data Pointer only read/
C1. C2 = 30 pF ± 10 pF for Crystals write data at address locations below 4K:
= 40 pF ± 10 pF for Ceramic Resonators
MOVX A, @DPTR
Figure 3. Oscillator Connections MOVX @DPTR, A
When the Data Pointer contains an address above
the 4K limit, those locations will not be accessed.
10-18
inter 8051AHP
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O'C to + 70'C age to the device. This is a stress rating only and
Storage Temperature .......... - 65'C to + 150'C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAlVpp Pin to Vss ... -0.5V to + 21.5V
tional sections of this specification is not implied. Ex-
Voltage on Any Other Pin to Vss .... -0.5V to + 7V posure to absolute maximum rating conditions for
Power Dissipation .......................... 1.5W extended periods may affect device reliability.
D.C. CHARACTERISTICS TA = O'Cto +70'C;Vee = 5V ±10%;Vss = OV
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage (Except XTAL2, RST) 2.0 Vee + 0.5 V
VIH1 Input High Voltage to XTAL2, RST 2.5 Vee + 0.5 V XTAL1 = Vss
VOL Output Low Voltage (Ports 1, 2, 3)' 0.45 V IOL = 1.6 mA
Vou Output Low Voltage (Port 0, ALE, PSEN)* 0.45 V IOL = 3.2 mA
VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 V IOH = -80 p.A
VOH1 Output High Voltage (Port 0 in External Bus Mode) 2.4 V IOH = - 400 p.A
IlL Logical 0 Input Current -500 p.A VIN = 0.45V
IIL2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45V
III Input Leakage Current (Port 0) ±10 p.A 0.45 S; VIN S; Vee
IIH Input Current to RST to Activate Reset 500 p.A VIN < (Vee - 1.5V)
Icc Power Supply Current 125 mA All Outputs
Disconnected;
EA = VCC
CIO Pin Capacitance 10 pF Test freq = 1 MHz
'NOTE:
Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1·to-0
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
10-19
8051AHP
A.C. CHARACTERISTICS TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min. Max "
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold after ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 233 4TCLCL-100 ns·
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSENPulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instr In 125 3TCLCL-125 ns
TPXIX Input Instr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL.,...8 ns
TAVIV Address to Valid Instr In 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TALAH AD Pulse Width 400 6TCLCL-100 ns
TWLWH WA Pulse Width 400 6TCLCL-100 ns
TALDV AD Low to Valid Data In 252 5TCLCL-165 ns
TAHDX Data Hold after AD 0 0 ns
TAHDZ Data Float after AD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to AD or WA Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to AD or WA Low 203 4TCLCL-130 ns
TOVWX Data Valid to WA Transition 23 TCLCL-60 ns
TOVWH Data Valid to WA High 433 7TCLCL-150 ns
TWHOX Data Hold after WA 33 TCLCL-50 ns
.TALAZ AD Low to Address Float 20 20 ns
TWHLH AD or WA High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
10-20
inter 8051AHP
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270279-6
EXTERNAL DATA MEMORY READ CYCLE
""-_~TLHLL
ALE
f4-----TLLDY - - - - . - j
--I.---TRLRH +----1
PORTO
I-~----TAYDY ------t
PORT 2 P2.0-P2.7 OR A8-A 15 FROM DPH A8-A 15 FROM PCH
270279-7
8051AHP
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
TLLW·L--I~".""---TWLWH -----<~
TQVWX
~-'~--~~-+-----TQVWH------~
PORTO DATA OUT
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270279-8
10-22
inter 8051AHP
SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to + 70·C; Vee = 5V ± 10%; Vss = OV;
Test Conditions: TA Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL ,...s
TOVXH Output Data Setup to Clock Rising 700 1OTCLCL -133 ns
Edge
TXHOX Output Data Hold after Clock 50 2TCLCL-117 ns
. Rising Edge
TXHDX Input Data Hold after Clock Rising 0 0 ns
Edge
TXHDV Clock Rising Edge to Input Data 700 1OTCLCL -133 ns
Valid
SHIFT REGISTER TIMING WAVEFORMS
'~fXLIL~
-------,
t"4-,QVIH ... 1 ~TlHQ. I
\ X X X~ __~X~__~X~__~X~__~x~__~1
~
. I
""D' ~
j I-""D'
t
SET II
,
WAITE TO SBUF
I""UT OA'..
_____ J~_J'~~
t
SET RI
CLEAR RI
270279-9
10-23
inter 8051AHP
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCl Oscillator Frequency 3.5 12 MHz
TCHCX High Time 20 ns
TClCX low Time 20. ns
TClCH Rise Time 20 os
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
....- - - - T C l C l - - - - - . . - j
270279-10
. . .> < x=
A.C. TESTING INPUT, OUTPUT WAVEFORM
u=x
Program Verification
2.0 2.0
The program verification test mode has been elimi-
nated on the 8051 AHP. It is not possible to verify the
TEST POINTS
ROM contents using this mode, the way EPROM
0.8 0.8
0.45 programmers typically do. Also, the ROM contents
270279-11 cannot be verified by a program executing out of
external program memory due to the restricted ad--
A.C. Testing: Inputs are driven at 2.4V for a Logic "'1" and 0.45V
. for a Logic "0". Timing measurements are made at 2.0V for a
dressing on the 8051AHP.
Logic "1" and 0.8V for a Logic "0".
10-24
8031 AH/8051 AH
8032AH/8052AH
8751 H/8751 H-8
EXPRESS
• Extended Temperature Range • Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125·C with Vee = 5.5V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.
D_C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%; Vss = ov
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.75 V
VIH Input High Voltage (Except 2.1 Vee + 0.5· V
XTAL2, RST)
lee Power Supply Current:
8051AH,8031AH 135 mA All Outputs
8052AH, 8032AH 175 mA Disconnected;
8751H,8751H-8 265 mA EA = Vee
IIL2 Logic 0 Input Current (XTAL2) -4.0 mA Vin = 0.45V
October 1987
10-25 Order Number: 270007-002
intJ MCS®·51 EXPRESS
Table 1. Prefix Identification
Prefix Package Type Temperature Rlmge Burn·ln
P plastic commercial no
D cerdip commercial no
C ceramic commercial no
N PLCC commercial no
R LCC commercial no
TP plastic extended no
TO cerdip extended no
TC ceramic extended no
QP plastic .commercial . yes
QD cerdip commercial yes
QC ceramic commercial yes
LP plastic extended yes
LD cerdip extended yes
LC ceramic extended yes
Please note:
• Commercial temperature range is O·C to 70·C. Extended temperature range is .,..40·C to +85·C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125·C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
• The following devices are not available in ceramic packages:
8051AH,8031AH
8052AH, 8032AH
• The following devices are not available in extended temperature range:
8751 H, 8751 H-8
Examples: P8031AH indicates 8031AH in a plastic package and specified for commercial temperature range,
without burn-in. LD8051 AH indicates 8051 AH in a cerdip package and specified for extended temperature
range with burn-in.
10-26
intJ 8751BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
• Program Memory Lock • Two 16·Bit Timer/Counters
• 128 Bytes Data Ram • 5 Interrupt Sources
• Quick Pulse Programming™ Algorithm • Programmable Serial Channel
• 12.75 Volt Programming Voltage • 64K External Program Memory Space
• Boolean Processor • 64K External Data Memory Space
• 32 Programmable I/O Lines
PO.O- PO.7 P2.0-P2.7
~~
r---------- ~
Vss
.... ~
-----------,
-:F
PSEN
ALE/1'IW1l
D/Vpp
RST
Pl.0-P1.7 P3.0-P3.7
270248-1
Figure 1. 8751BH Block Diagram
August 1987
10-27 Order Number: 270248-002
inter 8751BH
PIN DESCRIPTIONS inputs, Port 1 pins that are externally being pulled
low will source current (I,L, on the data sheet) be-
cause of the internal pullups.
PLO Vee Port 1 also receiveS! the low-order address bytes
PLI PO.O (ADO) during EPROM programming and program verifica-
PL2 PO.l (AD1) tion.
PL3 PO.2 (AD2)
PL4 PO.3 (AD3) Port 2: Port 2 is an 8-bit bidirectional liD port with
PLS PO.4 (AD4) internal pull ups. The Port 2 output buffers can sinkl
PL6 PO.S (ADS)
source 4 LS TIL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pull-
PL7 PO.6 (AD6)
ups, and in that state can be used as inputs. As
RESET PO.7 (AD7)
inputs, Port 2 pins that are externally being pulled
(RXD) P3.0 EA!VPP low will' source current (I,L, on the data sheet) be-
(TXD) P3.1 ALE/PROG cause of the internal pullups.
(INTO) P3.2 PSEN
(iNTl) P3.3 P2.7 (A1S) Port 2 emits the high-order address byte during
(TO) P3.4 P2.6 (AI4) fetches from external Program Memory and during
(Tl ) P3.S P2.S (AI3) accesses to external Data Memory'that use 16-bit
(Wil) P3.6 P2.4 (AI2) addresses (MOVX @DPTR). In this application it
(iID) P3.7
uses strong internal pullupswhen emitting 1s. Dur-
P2.3 (All)
ing accesses to external Data Memory that use 8-bit
XTAL2 P2.2 (Al0)
addresses (MOVX @Ri), Port 2 emits the contents of
XTALI P2.1 (A9) the P2 Special Function Register.
VSS P2.0 (AB)
270248-2 Port 2 also receives the high-order address bits dur-
ing EPROM programming and program verification.
Figure 2. Pin Connections
Port 3: Port 3 is an 8-bit bidirectional liD port with
Vee: Supply voltage. internal pullups. The Port 3 output buffers can sinkl
source 4 LS TIL inputs. Port 3 pins that have 1s
Vss: Circuit ground. written to them are pulled high by the internal pull-
ups, and in that state can be used as inputs. As
Port 0: Port 0 is an 8-bit open drain bidirectional I/O inputs, Port. 3 pins that are externally being pulled
port. As an output port each pin can sink 8 LS TIL low will source current (I,L, on the data sheet) be-
inputs. Port 0 pins that have 1s written to them float, cause of the pullups.
and in that state can be used as high-impedance
inputs. Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:
Port 0 is also the multiplexed low-order address and
data bus during' accesses to external Program and
Data Memorv. In this application it uses stronQ inter-
nal pullups when emitting 1s, and can source and
I::: IRXD (Sefi~li:~;~ia;:~unction
Pin
sink 8 LS TIL inputs. P3.1 TXD (seriai output port)
P3.2 INTO (external interrupt 0)
Port 0 also receives the code bytes during EPROM P3.3 INT1 (external interrupt 1)
programming, and outputs the code bytes during P3.4 TO (Timer 0 external input)
program verification. External pullups are required P3.5. T1 (Timer 1 external input)
during program verification. P3.6 WR (external data memory write strobe)
P3.7 AD (external data memory read strobe)
Port 1: Port 1 is an 8-bit bidirectional liD port with
internal pull ups. The Port 1 output buffers can sinkl
source 4 'LS TIL inputs. Port 1 pins that have 1s RST: Reset input. A high on this pin for two machine
written to them are pulled high by the internal pull- cycles while the oscillator is running resets the de-
ups, and in that state can be used as inputs. As vice.
10-28
inter 8751BH
ALE/PROG: Address Latch Enable output pulse for To drive the device from an external clock source,
latching the low byte of the address during accesses XTAL 1 should be grounded, while XTAL2 is driven,
to external memory. Thi~ pin is also the program as shown in Figure 4. There are no requirements on
pulse input (PROG) during EPROM programming. the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
In normal operation ALE is emitted at a constant divide-by-two flip-flop, but minimum and maximum
rate of 1/6 the oscillator frequency, and may be high and low times specified on the Data Sheet must
used for external timing or clocking purposes. Note, be observed.
however, that one ALE pulse is skipped during each
access to external Data Memory.
C2
PSEN: Program Store Enable is the Read strobe to I - - p - - - j XTAL2
External Program Memory.
When the 8751 BH is executing code from external
o
Program Memory, PSEN is activated twice each ma- I-_~--j XTAL 1
chine cycle, except that two PSEN activations are
skipped during each access to External Data Memo- t - - - - - - - - - I vss
ry.
270248-3
EA/Vpp: External Access enable. EA must be Cl, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations Figure 3_ Oscillator Connections
OOOOH to OFFFH. Note, however, that if either of the
Lock Bits are programmed, EA will be internally
latched on reset.
EXTERNAL
OSCILLATOR----j XTAL2
EA should be strapped to Vee for internal program SIGNAL
executions.
This pin also receives the 12.75V programming sup- - XTALl
ply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from, the inverting oscillator amplifi- 270248-4
er.
Figure 4. External Clock Drive Configuration
OSCILLATOR CHARACTERISTICS DESIGN CONSIDERATIONS
XTAL 1 and XTAL2 are the input and output, respec- Exposure to light when the device is in operation
tively, of an inverting amplifier which can be config-
may cause logic errors. For this reason, it is suggest-
ured for use as an on-Chip oscillator, as shown in
ed that an opaque label be placed over the window
Figure 3. Either a quartz crystal or ceramic resonator when the die is exposed to ambient light.
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cations Note AP-155, "Oscillators for Microcontrol-
lers."
10-29
intJ 8751BH
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .......... - 65·C to + 150·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAlVpp Pin to Vss .•. - 0.5V to + 13.0V
tional sections of this specification is not implied Ex-
Voltage on Any Other Pin to Vss .. ;. -0.5V to + 7V posure to absolute maximum rating conditions for
Power Dissipation ..•....................... 1.5W extended periods may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption) NOTICE Specifications contained within the
following tables are subject to change.
ADVANCE INFORMATION-8EE INTEL FOR DESIGN-IN INFORMATION
D.C. CHARACTERISTICS (TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV)
Symbol Parameter Min Max Unit Test Conditions
V,L Input Low Voltage (Except EA) -0.5 O.S V
V,L1 Input Low Voltage EA Vss 0.7 V.
V,H Input High Voltage 2.0 Vcc+ 0.5 V
(Except XTAL2, RST, EA)
V,H1 Input High Voltage XTAL2, RST 2.5 Vcc+ 0.5 V XTAL1 = VSS
V,H2 Input High Voltage to EA 4.5 5.5 V
VOL Output Low Voltage 0.45 V IOL = 1.6 rnA (Note 1)
(Ports 1, 2 and 3)
VOL1 Output Low Voltage 0.45 V IOL = 3.2 rnA (Notes 1, 2)
(Port 0, ALE/PROG, PSEN)
VOH Output High Voltage 2.4 V IOH = -SOtJoA
(Ports 1, 2, 3, ALE/PROG and PSEN)
VOH1 Output High Voltage 2.4 V IOH = - 4OO tJoA
(Port 0 in External Bus Mode)
I,L Logical 0 Input Current -1 rnA Y,N = 0.45V
(Ports 1, 2, 3 and RST)
I'L1 Logical 0 Input Current (EA) -10 rnA Y,N = VSS
I'L2 Logical 0 Input Current (XTAL2) -3.2 rnA V'N= 0.45 VXTAL1 = Vss
III Input Leakage Current (Port 0) ±10 tJo A 0.45 < Y,N < Vcc
I'H Logical 1 Input Current (EA) 1 rnA 4.5V < Y,N < 5.5V
I'H1 Input Current to RST 500 tJo A Y,N < (Vcc - 1.5V)
to Activate Reset
Icc Power Supply Current 175 rnA All Outputs Disconnected
C,O Pin Capacitance 10 pF Test Freq = 1MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1·to-O transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALEI
PROG pin may exceed O.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch
with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin.
10-30
inter 8751BH
A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vee = 5V ± 10%; VSS = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instruction In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-:-25 ns
TPLPH PSEN Pulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instruction In 125 3TCLCL-125 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instruction In 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 23 TCLCL-60 ns
TQVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHQX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
10-31
inter 8751BH
ALE _ _J
PORT 0
---
PORT 2 _ _ _J
270248-5
External Program Memory Read Cycle
ALE
PSEN
i-----TLLDV 'I
- - - < - t - - - TRLRH -----+I
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-A15 FROM DPH AB-A 15 FROM PCH
270248-6
External Data Memory Read Cycle
ALE-{ \
-TLHLL- ....i-TWHLH
PSEN 1
~TLLWL TWLWH
,.
- TAVLL I--TLLAX- ~
TQVWH -
J
I-TWHQX
PORTO
:::r FRol~i~~ DPL
TAVWL
DATA OUT K AO-A7 FROM PCL INSTR. IN
PORT2
=> P2.0-P2.7 OR AB-A15 FROM DPH AB-A 15 FROM PCH
270248-7
External Data Memory Write Cycle
10-32
infef 8751BH
SERIAL PORT TIMING - SHIFT REGISTER MODE
TEST CONDITIONS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF)
12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL f-Ls
TOVXH Output Data Setup to 700 1OTCLCL - 133 ns
Clock Rising Edge
TXHOX Output Data Hold After 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 1OTCLCL -133 ns
Input Data Valid
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
~j-TXHQX
OUTPUT DATA \ 0 IX 1 IX 2 X 3 X 4 X 5 X ·6 X 7 I
I
WRITE TO SBUF
j.TXHDV I:-IrTXHDX t
SET TI
INPUT DATA - - - -......r.:'AL~,.....W:ALI~D.-""'Y::::ALI:-::D,.,..-I:';A':':'U:v-.r.:'~,....."\I:';~.-""'Y~,.,..-r.:':~
ALID ALID ALID ALID
I t
CLEAR RI SET RI
270248-8
Shift Register Mode Timing Waveforms
_--TCLCL--~
270248-9
ExternalClock Drive Waveforms
10·33
8751BH
EXTERNAL CLOCK DRIVE AC TESTING INPUT/OUTPUT WAVEFORMS
Symbol
TCHCX
Parameter
1/TClCl Oscillator Frequency 3.5
High Time
Min Max Units
20
12 MHz
ns
2.4=X
0.45 V
.
-
2.0
O.B TEST POINTS
2.0'
O.B
-
)C
270248-10
TClCX low Time 20 ns AC inputs during testing are driven at 2.4V for a logic "1" and
0.45V for a logic "0". Timing measurements are made at 2.0V for
TClCH Rise Time 20 ns a logic "1" and 0.8V for a logic "0".
TCHCl Fall Time 20 ns
EPROM CHARACTERISTICS a
amount of time. Even narrow glitch above that volt-
age level can cause permanent damage to the de-
vice. The Vpp source should be well regulated and
Programming the EPROM free of glitches.
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro-
AOOR.
priate internal registers.) The address of an EPROM OOOOH/orrrH
location to be programmed is applied to Port 1 and
pins P2.0 - P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 and 3 pins, and RST, PSEN, and
EAIVpp should be held at the "Program" levels indi- 87518H
cated in Table 3. AlE/PROG is pulsed low to pro-
--+ P3.6
gram the code byte into the addressed EPROM lo- --+ P3.7
cation. The setup is shown in Figure 5. ,..-......- - 1 XTAL 2
Normally EA~is held at a logic high-'!ntil just
before AlE/PROG is to be pulsed. Then EAIVpp is '--+--+-1 XTAL 1
raised to Vpp, AlE/PROG is pulsed low,and then Vss
EAIVpp is returned to a valid high voltage. The volt-
age on the EAIVpp pin must be at the valid EAIVpp 270248-11
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later Figure 5. Programming the EPROM
sections of this data sheet.
Note that the EAIVpp pin must not be allowed to go
above the maximum specified Vpp level for any
10-34
8751BH
Table 3. EPROM Programming Modes
ALEI EAI
MODE RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O' Vpp 1 1 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12. 75V ± 0.25V
• ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)
QUICK-PULSE PROGRAMMINGTM tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
ALGORITHM operation. (If the Encryption Array in the EPROM
The 8751 BH can be programmed using the Quick- has been programmed, the data present at Port 0
Pulse Programming Algorithm for microcontrollers. will be Code Data XNOR Encryption Data. The user
The features of the new programming method are a . must know the Encryption Array contents to manual-
lower Vpp (12.75 volts as compared to 21 volts) and ly "unencrypt" the data during verify.)
a shorter programming pulse. It is possible to pro-
gram the entire 4K Bytes of EPROM memory in less The setup, which is shown in Figure 6, is the same
than 13 seconds with this algorithm as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
To program the part using the new algorithm, Vpp low read strobe.
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 ftseconds, 25 times. Then, the byte just
programmed may be verified. After programming,
the entire array should be verified. The Program
Lock features are programmed using the same ADDR.
PGM DATA
OOOOH/OFFF
method, but with the setup as shown in Table 3. The (USE 10K
PULLUPS)
only difference in programming Lock features is that
the Lock features cannot be directly verified. In-
stead, verification of programming is by observing SEE
that their features are enabled. TABLE 3 8751BH
VIH
_P3.7
PROGRAM VERIFICATION
...--..---1 XTAL 2
If the Lock Bits have not been programmed, the on- '--"'-+--IXTAL 1 VIHI
chip Program Memory can be read out for verifica- Vss
tion .purposes, if desired, either during or after the
programming operation. The address of the Program 270248-12
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.3. The other pins should be held at Figure 6. Verifying the EPROM
the "Verify" ,levels indicated in Table 3. The con-
10-35
inter 8751BH
PROGRAM MEMORY LOCK Erasing the EPROM also erases the Encryption Ar-
ray and the Lock Bits, returning the part to full un-
The two-level Program Lock system consists of 2 locked functionality.
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against soft- To ensure proper functionality of the chip, the inter-
ware piracy. nally latched value of the EA pin must agree with its
external state.
ENCRYPTION ARRAY
ERASURE CHARACTERISTICS
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every Erasure of the EPROM begins to occur when the
time that a byte is addressed during a verify, 5 ad- chip is exposed to light with wavelengths shorter
dress lines are used to select a byte of the Encryp- than approximately 4,000 Angstroms. Since sunlight
tion Array. This byte is then exclusive-NORed and fluorescent lighting have wavelengths in this
(XNOR) with the code byte, creating an Encrypted range, exposure to these light sources over an ex-
Verify byte. The algorithm, with the array in the un- tended time (about 1 week in sunlight, or 3 years in
programmed state (all 1s), will return the code in its room-level fluorescent lighting) could cause inadver-
original, unmodified form. tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
It is recommended that whenever the Encryption Ar- label be placed over the window.
ray is used, at least one of the Lock Bits be pro-
grammed as well. The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to anintegrat-
ed dose of at lease 15. W-sec/cm. Exposing the
LOCK BITS· EPROM to an ultraviolet lamp of 12,000 !J-W/cm rat-
ing for 20 to 30 minutes, at a distance of about 1
Also included in the,EPROM Program Lock scheme inch, should be sufficient.
are two Lock Bits which function as shown in Table
4. Erasure leaves the array in an all 1s state.
Table 4. Lock Bits and their Features
Lock Bits
Logic Enabled
LB1 LB2
U U Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)
P U MOVC instructions executed from
external program memory are
disabled from fetching code b~'!es
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
P P Same as above, but Verify is also
disabled
U P Reserved for Future Definition
P = Programmed
U = Unprogrammed
10-36
inter 8751BH
ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
IPP Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TOVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 J..Lsec
TGHSL Vpp Hold After PROG 10 J..Lsec
TGLGH PROGWidth 90 110 J..Lsec
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 J..Lsec
PROGRAMMING VERIFICATION
PI.O-PI.7
P2.0-P2.3
-----{=:::!AO~D~R~ES~S~ ADDRESS
-TAVQV
PORT 0 .-----1{=~~~ DATA OUT
TDVGL
ALE/PROG ------,,1
TELQVll'-_ _ _ )""I__ T_EH_Q_Z_ __
P2.7
--- 270248-13
EPROM Programming and Verification Waveforms
10-37
8052BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
8032BH .
SINGLE-CHIP 8-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
8032BH-ROMless
8052BH-8K Bytes of Factory Mask-Programmed ROM
• 256 Bytes Data Ram • Programmable Serial Channel
• Boolean Processor • Separate Transmit/Receive Baud Rate
Capability
• 32 Programmable I/O Lines
• Three 16-Blt Timer/Counters • 64K External Program Memory Space
• 6 Interrupt Sources • 64K External Data Memory Space .
PO.O-PO.7 P2.0-P2.7
v~
r----------
. ~~~
-----------,
~
PORT 0 PORT 2
DRIVERS DRIVERS
I'ml
'L~~
RST
PI.0-P1.7 P3.0- P3.7
Figure 1. Block Diagram 270192-1
October 1987
10-38 Order Number: 270192-1103
inter 8052BH/8032BH
PIN DESCRIPTIONS In addition, P1.0 and P1.1 serve the functions of the
following speCial features of the MCS®-51 Family:
(T2) PI.O
Port Pin Alternate Function
Vee
(T2EX) PI.I PO.O (ADO) P1.0 T2 (Timer/Counter 2 External Input)
PI.2 PO.I (ADI) P1.1 T2EX (Timer/Counter 2
PI.3 PO.2 (AD2)
Capture/Reload Trigger)
PI.4 PO.3 (AD3)
PI.S PO.4 (AD4)
PI.6 PO.S (ADS) Port 2: Port 2 is an a-bit bidirectional I/O port with
PI.7 PO.6 (AD6) internal pullups. The Port 2 output buffers can sink/
RESET 9 PO.7 (AD7) source 4 LS TTL inputs. Port 2 pins that have 1s
(RXD) P3.0 written to them are pulled high by the internal pull-
(TXD) P3.1 ALE ups, and in that state can be used as inputs. As
(INTO) P3.2 PSEN inputs, Port 2 pins that are externally being pulled
(INTI) P3.3 P2.7 (AIS) low will source current (IlL, on the data sheet) be-
(TO) P3.4 P2.6 (AI4) cause of the internal pullups.
(TI) P3.S P2.S (AI3)
(ViR) P3.6 P2.4 (AI2) Port 2 emits the high-order address byte during
(iW) P3.7 P2.3 (All) fetches from external Program Memory and during
XTAL2 P2.2 (AIO) accesses to external Data Memory that use 16-bit
XTAL1 P2.1 (A9) addresses (MOVX @DPTR). In this application it
VSS P2.0 (AS) uses strong internal pullups when emitting 1s. Dur-
270192-2 ing accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
Figure 2. Pin Connections the P2 Special Function Register.
Vee: Supply voltage. Port 3: Port 3 is an a-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
Vss: Circuit ground. source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pull-
Port 0: Port 0 is an a-bit open drain bidirectional I/O ups, and in that state can be used as inputs. As
port. As an output port each pin can sink a LS TTL inputs, Port 3 pins that are externally being pulled
inputs. Port 0 pins that have 1s written to them float, low will source current (IlL, on the data sheet) be-
and in that state can be used as high-impedance cause of the pullups.
inputs.
Port 3 also serves the functions of various special
Port 0 is also the multiplexed low-order address and' features of the MCS®-51 Family, as listed below:
data bus during accesses to external Program and
Data Memory; In this application it uses strong inter- Port Pin Alternate Function
nal pullups when emitting 1s, and can source and
sink a LS TTL.inputs. P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
Port 1: Port 1 is an a-bit bidirectional I/O port with P3.2 INTO (external interrupt 0)
internal pullups. The Port 1 output buffers can sink/ P3.3 INT1 (external interrupt 1)
source 4 LS TTL inputs. Port 1 pins that have 1s P3.4 TO (Timer 0 external input)
written to them are pulled high by the internal pull- P3.5 T1 (Timer 1 external input)
ups, and in that state can be used as inputs. As P3.6 WR (external data memory write strobe)
inputs, Port 1 pins that are externally being pulled
P3.7 RD (external data memory read strobe)
low will source current (IlL, on the data sheet) be-
cause of the internal pullups.
10-39
inter 8052BH/8032BH
RST: Reset input. A high on this pin for two machine Figure 3. Either a quartz crystal or ceramic resonator
cycles while the oscillator is running resets the de- may be used. More detailed information concerning
vice. the use of the on-chip oscillator is available in Appli-
cations Note AP-155, "O~cillators for Microcontrol-
ALE: Address Latch Enable output pulse for latching lers."
the low byte of the address during accesses to ex-
ternal memory; . To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
In normal operation ALE is emitted at a constant as shown in Figure 4. There are no requirements on
rate of 1/6 the oscillator frequency, and may be the duty cycle of the external clock signal, since the
used for external timing or clocking purposes. Note, input to the internal clocking circuitry is through a
however, that one ALE pulse is skipped during each divide-by-two flip-flop, but minimum and maximum
access to external Data Memory. high and low times specified on the Data Sheet must
be observed. .
PSEN: Program Store Enable is the Read strobe to
External Program Memory.
C2
When the device is executing code from external 1 - -.....--1 XTAL2
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access to External Data Memo-
o
ry. 1 - -.....--1 XTAL 1
EA: External Access enable. EA must be strapped to . t - - - - - - - - 1 vss
Vss in order to enable the device to fetch code from
External Program Memory locations OOOOH to 270192-3
1FFFH. Note, however, that if either of the Lock Bits Cl, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
are programmed, EA will be internally latched on re-
set. . Figure 3. Oscillator Connections
EA should be strapped to Vee for internal program
executions.
EXTERNAL
OSCILLATOR----I XTAL2
XTAL 1: Input to the inverting oscillator amplifier. SIGNAL
XTAL2: Output from the inverting oscillator amplifi-
er. ,..-- XTAL 1
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respec- 270192-4
tively, of an inverting amplifier which can be config-
uredfor use as an on-chip oscillator, as shown in
CiftllPA A Cvt"""'I!II1
I ."WI'"" ..... _ ...."" ••• u. 1"1ft,,...,
_1_"",", n.i
_ • •..
• .a.
__ =-_._ .. _..
t"ftftfi"'II.a.t;"""
........
10-40
intJ 8052BH/8032BH
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent dam-
AmbientTemperature Under Bias .... O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature, .......... - 6S·C to + 1S0·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EA Pin
tional sections of this specification is not implied. Ex-
to Vss ...................... -O.SV to + 13.0V
posure to absolute maximum rating conditions for
Voltage on Any Other Pin to Vss .... -O.SV to + 7V extended periods may affect device reliability.
Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not NOTICE' Specifications contained within the
device, power consumption) following tables are subject to change.
ADVANCE INFORMATION. Contact Intel for Design-In Information.
D.C. CHARACTERISTICS (TA = O·Cto +70·C;Vcc = sv ±10%;Vss = OV)
Symbol Parameter . Min Max Unit Test Conditions .
VIL Input Low Voltage (Except EA) -0.5 O.B V
VIL1 Input Low Voltage EA Vss 0.7 V
VIH Input High Voltage 2.0 Vee+ 0.5 V
(Except XTAL2, RST, EA)
VIH1 Input High Voltage XTAL2, RST 2.5 Vee+ 0.5 V XTAL1 = Vss
VIH2 Input High Voltage to EA 4.5 5.5 V
VOL Output Low Voltage 0.45 V IOL = 1.6 mA (Note 1)
(Ports 1, 2 and 3)
VOL1 Output Low Voltage 0.45 V IOL = 3.2 mA (Note 1) .
(Port 0, ALE, PSEN)
VOH Output High Voltage 2.4 V IOH = -BO",A
(Ports 1, 2, 3, ALE and PSEN)
VOH1 Output High Voltage 2.4 V IOH = -400 ",A
(Port 0 in External Bus Mode)
IlL Logical 0 Input Current -500 ",A VIN = 0.45 V
(Ports 1, 2, 3 and RSn
IIL1 ' Logica(O Input Current (EA) -10 mA VIN = VSS
500 ",A
IIL2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0.45V XTAL1 = Vss
III Input Leakage Current (Port 0) ±10 ",A 0.45 < VIN <Vee
IIH Logical 1 Input Current (EA) 1 mA 4.5V < VIN < 5.5V
IIH1 Input Current to RST 500 ",A VIN < (Vee- 1.5V)
. to activate Reset
Icc Power Supply Current 175 mA All Outputs Disconnected
CIO Pin Capacitance 10 pF Testfreq = 1MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O·transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE 'pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use·an address latch with a Schmitt
Trigger STROBE input.
10-41
inter 8052BH/8032BH
EXPLANATION OF THE AC 'SYMBOLS L:Logic level LOW, or ALE.
P:PSEN.
Each timing symbol has 5 characters. The first char- O:Output data.
acter is always a, "T" (stands for time). The other R:RD signal.
characters, depending on their positions, stand for T:Time.
the name of a signal or the logical status of that V:Valid.
signal. The following isa I.ist of all the characters and W:WR signal.
what they stand f o r . ' .' X:No longer a valid logic level. .
Z:Float.
A:Address ..
C:Clock. For example;
D:lnput data. TAVLL = Time from Address Valid to ALE 'Low.
H:Logic level HIGH. TLLPL = Time from ALE Low to PSEN Low.
1:lnstruction (program memory contents).
A_C. CHARACTERISTICS (TA = O·C to 70·C; Vee = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION. Contact Intel for Design-In Information.
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol Parameter 12MHz9sc Variable· OSCillator • Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 I
TCLCL-40 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instruction In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSENPulse,Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instruction In 125 3TCLCL -1.25 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 63 TCLCL-20 ns
TPXAV PSEN to Address Valid ' 75 TCLCL-8 ns
..
TAVIV Address to Valid Instruction In 302' 5TCLCL-115 ns .
TPLAZ PSEN Low to Address FI~at 20 20 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
IWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low toValid Data In 517 8TCLCL-150 ns
TAVDV Address to Valic! Data In 585 9TCLCL-165 ns
TLLWL' ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low . 203 4TCLCL-130 ns'
TOVWX Data Valid to WR Transition 23 '. TCLCL-60 , ns
TOVWH' , Data Valid to WR High ,433 7TCLCL-150 ns
TWHOX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
10-42
intJ 8052BH/8032BH
~LE _ _...J
PSEN _ _..I
TPXAV
TPXIZ
PORT 0 _ _ _..1 AO-.A7
PORT 2
---- External Program Memory Read Cycle
AB-AI5
270192-5
ALE
PSEN
i-----TLLDV ' I
-----0-1---- TRLRH -----+l
RD ----+-----~ ~------------------
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-AI5 FROM DPH AB-A 15 FROM PCH
270192-6
External Data Memory Read Cycle
ALE
, I J
-TLHLL- =L-TWHLH
~
~TLLWL
, TWLWH
-. TAVLL !-TLLAX- ~
TQVWH - '-TWHQX
PORTO
~ FRoll~i~h DPL
-
DATA OUT XAO-A7 FROM PCL INSTR. IN
TAVWL
PORT2
:::::> P2.0-P2.7 OR AB-A 15 FROM DPH AB-AI5 FROM PCH
270192-7
External Data Memory Write Cycle
10-43
8052BH/8032BH
SERIAL PORT TIMING - SHIFT REGISTER MODE
.TEST CONDITIONS TA = 0·Ct070·C;"Vcc =5V ± 10%;Vss = OV; Load Capacitance = 80pF
.. 12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL /Ls
TOVXH Output Data Setup ~o 700 10TCLCL"'-133 ns
Clock Rising Edge c
TXHOX Output Data Hold After 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 1OTCLCL -133 ns
Input Data Valid
INSTRUCTION I 0 2 3 4 5 6 7 8
ALE
CLOCK
I TOVXH I r-TXHOX I"
---"'I:\~--:O~""-:-\IX IXr--:2~""\Xr-~~X
OUTPUT DATA 1 3 4 X 5 -X 6
X 7 I
t
WRITE TO SBUF"
.J TXHDV I:
~r~~ I
SET TI
INPUT DATA ~L ~u ~Il ~LIIl ~Ull ~ ~
t I
CL~R RI SET RI
270192-8
Shift Register Mode Timing Waveforms
14-TCHCX-+I TCLCH-I 14- -+I J+- TCHCL
-~-TCLCL---+I
270192-9
External Cloc~ Drive Waveforms
10-44
8052BH/8032BH
EXTERNAL CLOCK DRIVE AC TESTING INPUT/OUTPUT WAVEFORMS
Symbol
TCHCX
Parameter
1/TCLCL Oscillator Frequency 3.5
High Time
Min Max Units
20
12 MHz
ns
2.4=X
0.4SV
2.0
o~
TEST POINTS
2.0
o~
)C
. .
270192-10
TCLCX Low Time 20 ns AC inputs during testing are driven at 2.4V for a logic 'T' and
0.45V for a logic "0". Timing measurements are made at 2.0V for
TCLCH Rise Time 20 ns a logic '"1" and O.BV for a logic "0".
TCHCL Fall Time 20 ns
Table 1_ Lock Bits and their Features
Lock Bits
PROGRAM MEMORY LOCK Logic Enabled'
LB1 LB2
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are U U Minimum Program Lock features
used to protect the program memory against soft- enabled. (Code Verify will still be
ware piracy. The following description applies to the encrypted by the Encryption
8752BH. The same options are also available on the Array)
8052BH, mask-programmed at the factory. P U MOVC instructions executed from
external program memory are
disabled from fetching code bytes
ENCRYPTION ARRAY from internal memory, EA is
sampled and latched on reset,
Within the EPROM array are 32 bytes of Encryption and further programming of the
Array that are initially unprogrammed (all 1s). Every EPROM is disabled
time that a byte is addressed during a verify, 5 ad-
dress lines are used to select a byte of the Encryp- P P Same as above, but Verify is also
tion Array. This byte is then exclusive-NORed disabled
(XNOR) with ·the code byte, creating an Encrypted
U P Reserved for Future Definition
Verify byte. The algorithm, with the array in the un-
programmed state (all 1s), will return the code in its P = Programmed
original, unmodified. form. . U = Unprogrammed
It is recommended that whenever the Encryption Ar- To ensure proper functionality of the chip, the inter-
ray is used, at least one of the Lock Bits be pro- nally latched value of the EA pin must agree with its .
grammed as well. extern~l.state.
LOCK BITS
Also included in the Program Lock scheme are two
Lock Bits which function as shown in Table 1.
10-45
8752B'H
SINGLE-CHIP8-BIT MICROCOMPUTER,
WITH 8K BYTES OF EPROM PROGRAM,MEMORY
..'
• Program Memory Lock • 6 Interrupt Sources
• 256 Bytes Data Ram' • Programmable Serial Cliannel
• Quick Pulse Programming™ Algorithm • Separate Transmit/Receive Baud Rate
Capability
• .12:75 Volt Programming Voltage
.64K External Program Memory Space
• Boolean Processor
• 32 Programmable I/O Lines • 64K External Data Memory Space
• Three 16·Bit Timer/Counters
PO.O-PO.7 P2.0-P2.7
~~
Vss
r - - - - - -,- - - -
. p..~t..I.lI~ :--:---------,
-F
i'S£iI
AU:/1'RllC
£A'Yitr ::I~ CO'NTRO>L\
P1.0-Pl.7 P3.0-P3.7
270429-1
Figure 1. Block Diagram
October 1987
10-46 Order Number: 270429-001
inter 8752BH
PIN DESCRIPTIONS Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
(T2) PLO Vee In addition, P1.0 and P1.1 serve the functions of the
(T2EX) Pl.l, PO.O (ADO) following special features of the MCS®-S1 Family:
Pl.2 PO.l (AD1)
Pl.3 PO.2 (AD2) Port Pin Alternate Function
Pl.4 PO.3 (AD3) P1.0 T2 (Timer/Counter 2 External Input)
Pl.S PO.4 (AD4) P1.1 T2EX (Timer/Counter 2
Pl.S PO.S (ADS) Capture/Reload Trigger)
Pl.7 PO.S (ADS)
RESET PO.7 (AD7) Port 2: Port 2 is an a-bit bidirectional I/O port with
(RXD) P3.0 EA/Vpp internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
(TXD) P3.1 ALE/PROG
written to them are pulled high by the. internal pull-
(INTO) P3.2 PSEN ups, and in that state can be used as inputs. As
{lNT1) P3.3 P2.7 (A lS) inputs, Port 2 pins that are externally being pulled
(TO) P3.4 P2.S (A14) low will source current (IlL, on the data sheet) be-
(T1 ) P3.S P2.S (A13) cause of the internal pullups.
(WR) P3.S P2.4 (A12)
Port 2 emits the high-order address byte during
(RO) P3.7 P2.3 (All) fetches from external Program Memory and during
XTAL2 P2.2 (Al0) accesses to external Data Memory that use 16-bit
XTALl P2.1 (A9) addresses (MOVX @DPTR). In this application it
Vss P2.0 (A8) uses strong internal pullups when emitting 1s. Dur-
ing accesses to external Data Memory that use a-bit
270429-2 addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Figure 2. Pin Connections
Port 2 also receives the high-order address bits dur-
Vee: Supply voltage. ing EPROM programming and program verification.
Vss: Circuit ground. Port 3: Port 3 is an a-bit bidirectional I/O port with
intermil pullups. The Port 3 output buffers can sink/
Port 0: Port 0 is an a-bit open drain bidirectional 110 source 4 LS TTL inputs. Port 3 pins that have 1s
port. As an output port each pin can sink a LS TTL written to them are pulled high by the internal pull-
inputs. Port 0 pins that have 1s written to them float, ups, and in that state can be used as inputs. As
and in that state can be used as high-impedance inputs, Port 3 pins that are externally being pulled
inputs. . low will source current (IlL, on the data sheet) be-
cause of the pull ups.
Port 0 is also the multipl~xed low-order address and
data bus during accesses to external Program and Port 3 also serves the functions of various special
Data Memory. In this application it uses strong inter- features of the MCS®-S1 Family, as listed below:
nal pullups when emittill9 1s, and can source and
sink a LS TTL input~ .. Port Pin Alternate Function
Port 0 also receives the code bytes during EPROM P3.0 RXD (serial input port)
programming, and outputs the code bytes during P3.1 TXD (serial output port)
program verification. External pullups are required P3.2 INTO (external interrupt 0)
during program verification. P3.3 INT1 (external interrupt 1)
P3.4 TO (Timer 0 external input)
Port 1: Port 1 is an a-bit bidirectional I/O port with
P3.S T1 (Timer 1 external input)
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s P3.6 WR (external data memory write strobe)
written to them are pulled high by the internal pull- P3.7 RD (external data memory read strobe)
ups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled RST: Reset input. A high on this pin for two machine
low will source current .(IIL' on the data sheet) be- cycles while the oscillator is running resets the de-
cause of the internal pullups. vice.
10-47
8752BH
ALE/PROG: Address Latch Enable output pulse for cations Note AP-155, "Oscillators for Microcontrol-
latching the low byte of the address during accesses lers."
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming on To drive the device from an external clock source,
the 8752BH. XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
In normal operation ALE is emitted at a constant the duty cycle of the external clock signal, since the
rate of 1/6 the oscillator frequency, and may be input to the internal clocking circuitry is through a
used for external timing or clocking purposes. Note, divide-by-two flip-flop, but minimum and maximum
however, that one ALE pulse is skipped during each high and low times specified on the Data Sheet must
access to external Data Memory. be observed.
PSEN: Program Store Enable is the Read strobe to
External Program Memory: C2
r---1I--.---f XTAL2
When the device is executing code from external
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access ~o External Data Memo- t--.....--I XTAL 1
ry.
.....~-----I Vss
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to 270429-3
fetch code from External Program Memory locations_ C1. C2 = 30 pF ± 10 pF for prystals
= 40 pF ± 10 pF for Caramic Resonators
OOOOH to 1FFFH. Note, however, that if either of the
Lock B.its are programmed, EA will be internally Figure 3. Oscillator Connections
latched on reset.
EA sh.ould be strapped to Vee for internal program
executions. . . EXTERNAL
OSCILLATOR~---I XTAL2
SIGNAL
This pin also receives the 12.75V programming sup-
ply voltage (Vpp) during EPROM programming.
- XTAL1
XTAL 1: Input to the inverting oscillator amplifier. _ Vss
XTAL2: Output from the inverting oscillator amplifi-
er.
270429-4
Figure 4. External Clock Drive Configuration
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config- DESIGN .CONSIDERATIONS
ured .for use as an on-chip oscillator, as shown in
Exposure to light when tlie 8752BH is in operation
Figure 3. Either a quartz crystal or ceramic resonator may cause logic errors. For this reason, it is suggest-
may be used. More detailed information concerning
ed that an opaque label be placed over. the window
the use of the on-chip oscillator is available in Appli- of the 8752BH when the die is exposed to ambient
light.
10-48
inter 8752BH
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias ...... ODC to 70DC age to the device. This is a stress rating only and
Storage Temperature .......... -6SDC to + 1S0DC functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAlVpp Pin to Vss ... -O.SV to + 13.0V
tional sections of this specification is not implied. Ex-
Voltage on Any Other Pin to Vss .... -O.SV to + 7V posure to absolute maximum rating conditions for
Power Dissipation .......................... 1.SW extended periods may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption) NOTICE Specifications contained within the
fol/owing tables are subject to change.
D.C. CHARACTERISTICS (TA = ODCto +70DC;Vcc = sv ±10%;Vss = OV)
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage (Except EA) -0.5 0.8 V
VILl Input Low Voltage EA Vss 0.7 V
VIH Input High Voltage 2.0 Vee+ 0.5 V
(Except XTAL2, RST, EA)
VIH1 Input High Voltage XTAL2, RST 2.5 Vec+ 0.5 V XTAL1 = Vss
VIH2 Input High Voltage to EA 4.5 5.5 V
VOL Output Low Voltage 0.45 V IOL = 1.6 mA (Note 1)
(Ports 1, 2 and 3)
Vall Output Low Voltage 0.45 V 10L = 3.2 mA (Note 1, 2)
(Port 0, ALE/PROG, PSEN)
VOH Output High Voltage 2.4 V IOH = -80/LA
(Ports 1, 2, 3, ALE/PROG and PSEN)
VOH1 Output High Voltage 2.4 V IOH = - 400 /LA
(Port 0 in External Bus Mode)
IlL Logical 0 Input Current -500 /LA VIN = 0.45V
(Ports 1, 2, 3 and RST)
IIL1 Logical 0 Input Current (EA) -10 mA VIN = Vss
500 /LA
IIL2 Logical 0 Input Current (XTAL2) -3.2 mA VIN = 0,45V XTAL1 = Vss
III Input Leakage Current (Port 0) ±10 /LA 0.45 < VIN < Vee
IIH Logical 1 Input Current (EA) 1 mA 4.5V < VIN < 5.5V
IIH1 Input Current to RST 500 /LA VIN < (Vee - 1.5V)
to activate Reset
lee Power Supply Current 175 mA All Outputs Disconnected
Cia Pin Capacitance 10 pF Test freq = 1 MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-\0-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the device. ALE refers to a timing signal that is output on the ALE/PROG pin.
10-49
8752BH
EXPLANATION OF THE AC SYMBOLS L:Logic level LOW, or ALE
P:PSEN ..
Each timing symbol has 5 characters. The first char- Q:Output data
acter is always a 'T' (stands for time). The other .' R:RD signal
characters, depending on their positions, stand for T:Time
the name. of a signal or the logical status of that V:Valid
signal. The following is a,list of all the ch!lracters and W:WR signal
what they stand for. X:No longer a valid logic level
Z:Float
A:Address
C:Clock' For example,
D:lnput Data
H:Logic level HIGH TAVLL = Time from Address Valid to ALE Low.
1:lnstruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low.
A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vcc. = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other OutpLits = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min' Max
l/TCLCL OsCiliator Frequency 3.5 12.0 MHz'
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 43 TCLCL-40 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instruction In 233 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 58 TCLCL-25 ns
TPLPH PSEN Pulse Width 215 3TCLCL-35 ns
TPLIV PSEN Low to Valid Instruction In 125 3TCLCL-125 ns
TPXIX .input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 63 . TCLCL-20 ns
TPXAV PSEN to Address Valid 75 TCLCL-8 ns
TAVIV Address to Valid Instruction In 302 5TCLCL-115 ns
TPLAZ PSEN Low to Address Float 20 20 ns,
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 .0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low. 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TOVWX Data Valid to WR Transition 23 TCLCL-60 ns
TOVWH Data Valid to WR High 433 7TCLCL-150 ns
TWHOX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
10-50
8752BH
ALE _ _J
PSEN _ _J
]I--!----Ji"_____. TPXAV
TPXIZ
PORT a _ _J AO-A7
PORT 2 _ _.....J AB-AI5
270429-5
External Program Memory Read Cycle
ALE
PSEN
i------TLLDV 'I
--+--- TRLRH ---~
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-AI5 FROM DPH AB-AI5 FROMPCH
270429-'6
External Data Memory Read Cycle
-1:.-TLHLL~
ALE I ~
4TWHLH
~TLLWL TWLWH
,
-
J
.- TAVLL -TLLAX- ~ --TWHQX
TQVWH
PORTO
:::r FRoIAA~i~~
TAVWL
DPL DATA OUT 1\ AO-A7 FROM PCL INSTR. IN
PORT2
:::::> P2.0-P2.7 OR AB-A 15 FROM DPH X AB-A 15 FROM PCH
270429-7
External Data Memory Write Cycle
10-51
8752BH
SERIAL PORT TIMING-SHIFT REGISTER MODE
TEST CONDITIONS TA = o·c to + 70·C; vee = 5V ± 10%; vss = OV; Load Capacitance = 80 pF
12MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time .1.0 12TCLCL . /Ls
TOVXH Output Data Setup to 700 10rCLCL --.: 133. ns
Clock Rising Edge
TXHOX Output Data Hold After . 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 10TCLCL-133 ns
Input Data Valid
INSTRUCTION I 0 ·1 2· 3 4 6 7 8
ALE
CLOCK
~!-TXHQX
OUTPUT DATA· \ 0 IX 1 2 X 3 X 4 X 5 X 6X 7/
t
WRITE TO SBUF
I
-l TXHDV r.: . ....
-lrTXHDX I
SET TI
INPUT DATA -.,.....----\r.:AJ~,....-w:AlI~·~-\r.:A-:-::U)J'"-,.r.:':AL'::!ID.;--V~AIJ~,...."'\r.~AIJ'="-\r.:AIJ":':D)J'"-,.r.:':":!J
t I
CLEAR RI SET RI.
270429-8
Shift Register Mode Timing Waveforms
270429-9
External Clock Drive Waveforms
10-52
inter 8752BH
EXTERNAL CLOCK DRIVE A.C. TESTING INPUT/OUTPUT WAVEFORMS
Symbol Parameter
'1/TClCl Oscillator Frequency 3.5
Min Max Units
12 MHz 2 . 4 = X 2.0
O.B TEST POINTS
2.0
0.8
)C
TCHCX High Time 20 ns 0.45V - -
270429-10
TClCX low Time 20 ns AC inputs during testing are driven ,at 2.4V.for a logic "1" and
O.4SV for a logic "0". Timing measurements are made at 2.0V for
TClCH Rise Time 20 ns a logic "1" and O.BV for a logic "0".
TCHCl Fall Time 20 ns
EPROM CHARACTERISTICS gram" levels indicated in Table 1. AlE/PROG is
pulsed low to program the code byte into the ad-
Table 1 shows the logic levels for programming the dressed EPROM location. The setup is shown in Fig-
Program Memory, the Encryption Table, and the ure 5.
lock Bits and for reading the Signature bytes.
Normally EAlVpp is held at a logic high..J!.ntil just
before AlE/PROG is to be pulsed. Then EAlVpp is
Programming the EPROM raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The volt-
To be programmed, the 8752BH must be running age on the EAlVpp pin must be at the valid EAlVpp
with a 4 to 6 MHz oscillator. (The reason the oscilla- high level before a verify is attempted. Waveforms
tor needs to be running is that the internal bus is and detailed· timing specifications are shown in later
being used to transfer address and program data to sections of this data sheet.
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to Note that the EAlVpp pin must not be allowed to go
Port 1 and pins P2.0 - P2.4 of Port 2, while the code above the maximum specified Vpp level for any
byte to be programmed into that location is applied amount of time. Even a narrow glitch above that volt-
to Port O. The other Port 2 and 3 pins, and RST, age level can cause permanent damage to the de-
PSEN, and EAlVpp should be held at the "Pro- vice. The Vpp source should be well regulated and
free of glitches.
+5V
25 100!-'. PULSES TO GND
8752BH
.--_--IXTAL2
L -......-+-IXTAL 1
Vss
270429-11
Figure 5. Programming the EPROM
10-53
inter 8752BH
Table 1 EPROM Programming Modes
ALEI EAI
MODE RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp'
Program Code Data 1 0 O' Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O· Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12.75V ±0.25V
*ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)
QUICK-PULSE PROGRAMMINGTM PROGRAM VERIFICATION
ALGORITHM
If the Lock Bits have not been programmed, the on-
The 8752BH can be programmed using the Quick- chip Program Memory can be read out for verifica-
Pulse Programming™ Algorithm for microcontrol- tion purposes, if desired, either during or after the
lers. The features of the new programming method programming operation. The address of the Program
are a lower Vpp (12.75 volts as compared to 21 Memory location to be read is applied to Port .1 and
volts) and a shorter programming pulse. It is possi- pins P2.0 - P2.4. The other pins should be held at
ble to program the entire 8K Bytes of EPROM mem- the "Verify" levels indicated in Table 1. The con-
ory in less than 25 seconds with this algorithm! tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
To program the part using the new algorithm, Vpp operation. (If the Encryption Array in the EPROM
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed has been programmed, the data present at Port 0
low for 100 fLseconds, 25 times as shown in Figure will be Code Data XNOR Encryption Data. The user
6. Then, the byte just programmed may be verified. must know the Encryption Array contents to manual-
After programming, the entire array should be veri- ly "unencrypt" the data during verify.)
fied. The Program Lock features are programmed
using the same method, but with the setup as shown The setup, which is shown in Figure 7, is the same
in Table 1. The only difference in programming Lock as for programming the EPROM except that pin P2.7
features is that the Lock features cannot be directly is held at a logic low, or may be used as an active
verified. Instead, verification of programming is by low read strobe.
observing that their features are enabled.
11~, - - - - - - 2 5 PULSES
'I
ALE/PROG:~-----~
'----.---J .
'-.~ 10)'. MIN1 I' 100,u'
:1:10)'. 'I
ALE/PROG :---...:...,\
o L._ _ _ _ _ _ _..J n'-_ _ _ _ _ _..... '-._ __
n 270429-12
Figure 6. PROG Waveforms
10-54
8752BH
270429-13
Figure 7. Verifying the EPROM
PROGRAM MEMORY LOCK Table 2. Lock Bits and their Features
Lock Bits
The two-level Program Lock system consists of 2 Logic Enabled
Lock bits and a 32-byte Encryption Array which are LB1 LB2
used to protect the program memory against soft-
ware piracy. U U Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
ENCRYPTION ARRAY Array)
P U MOVC instructions executed from
Within the EPROM array are 32 bytes of Encryption external program memory are
Array that are initially unprogrammed (all 1s). Every disabled from fetching code bytes
time that a byte is addressed during a verify, 5 ad- from internal memory, EA is
dress lines are used to select a byte of the Encryp- sampled and latched on reset,
tion Array. This byte is then exclusive-NORed and further programming of the
(XNOR) with the code !:Iyte, creating an Encrypted EPROM is disabled
Verify byte. The algorithm, with the array in the un-
programmed state (all 1s), will return the code in its P P Same as above, but Verify is also
original, unmodified form. disabled
U P Reserved for Future Definition
It is recommended that whenever the Encryption Ar-
ray is used, at least one of the Lock Bits be pro- P = Programmed
grammed as well. U = Unprogrammed
LOCK BITS READING THE SIGNATURE BYTES·
Also included in the EPROM Program Lock scheme The signature bytes are read by the same procedure
are two Lock Bits which function as shown in Table as a normal verification of locations 030H and 031 H,
2. except that P3.6 and P3.7 need to be pulled to a
logic low. Thevalues returned are:
Erasing the EPROM also erases the Encryption Ar- (030H) = 86H indicates manufactured by Intel
ray and the Lock Bits, returning the part to full un- (031 H) = 52H indicates 8752BH
locked functionality.
To ensure proper functionality of the chip, the inter-
nally latched value of the EA pin must agree with its
external state.
10-55
8752BH
ERASURE CHARACTERISTICS this type of exposure, it is suggested that an opaque
label be placed over the window.
Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter The recommended erasure procedure is exposure
than approximately 4,000 Angstroms. Since sunlight to ultraviolet light (at 2537 Angstroms) to an integrat-
and fluorescent lighting have wavelengths in this ed dose of at lease 15 W-sec/cm. Exposing the
range, exposure to these light sources over an ex- EPROM to an ultraviolet lamp of 12,000 jJ-W/cm rat-
tended time (about 1 week in sunlight, or 3 years in ing for 30 minutes, at a distance of about 1 inch;
room-level fluorescent lighting) could cause inadver- should be sufficient.
tent erasure. If an application subjects the device to
Erasure leaves the array in an all 1s state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, Vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 rnA
1/TCLCL Oscillator Frequency 4 -6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 jJ-s
TGHSL Vpp Hold After PROG 10 jJ-s
TGLGH PROGWidth 90 110 jJ-s
TAVaV Address to Data Valid 48TCLC;L
TELaV ENABLE Low to Data Valid 48TCLCL
TEHaZ Data Float After ENABLE 0 48TCLCL.
TGHGL PROG High to PROG Low 10 jJ-s
PROGRAMMING VERIFICAnON
PI.a-pI.7
p2.a-p2.4 ---:----{=:A~D~DR~ES~S~~=~--~-__;=:::!A~DD~RE~SS~J----
-TAVQV
PORT a ----H:=~~~:=H_-----:--_{~DA~TA~O~U~T::Jf-----:--
TDVGL
ALE/PROG -----""\1
TSHGLj--
_ _ _ TGLGH
fA/vpp ~lI---"'vp-p---'i!-----.ll'---:;::t,.:;::::::-_ _.f-____I - - - - -
P2.7 --J ="!T_EHSH
~.~----~-------
~-~
TEHQZ
270429-14
EPROM Programming and Verification Waveforms
10-56
SOC51 BH/SOC51 BH-1 /SOC51 BH-2
CHMOS SINGLE-CHIP S-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
SOC31 BH/SOC31 BH-1/S0C31 BH-2
CHMOS SINGLE-CHIP S-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
SOC51BH/SOC31BH-3.5 to 12 MHz, Vee = 5V ± 20%
SOC51BH-1/S0C31BH-1-3.5 to 16 MHz, Vee = 5V ±20%
SOC51BH-2/S0C31BH-2-0.5 to 12 MHz, Vee = 5V ± 20%
• Power Control Modes • High Performance CHMOS Process
• 128 x 8-Bit RAM • Boolean Processor
• 32 Programmable I/O Lines _ 5 Interrupt Sources
• Two 16-Bit Timer/Counters • Programmable Serial Port
• 64K Program Memory Space • 64K Data Memory Space
The MCS®-51 CHMOS products are fabricated on Intel's CHMOS III process and are functionally compatible
with the standard MCS-51 HMOS and EPROM products. CHMOS III is a technology which combines the high
speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination ex-
pands the effectiveness of the powerful MCS-51 architecture and instruction set.
Like the MCS-51 HMOS versions, the MCS-51 CHMOS products have the following features: 4K byte of ROM
(80C51 BH/80C51 BH-1/80C51BH-2 only); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a five-
source two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In
addition, the MCS-51 CHMOS products have two software selectable modes of reduced activity for further
power reduction-Idle and Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters serial port and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
-IVSS~
- I
- I
I
270064-1
Figure 1. Block Diagram
September 1987
10-57 Order Number: 270064·005
inter 80C51BH, -1, -2/80C31BH, -1,-2
IDLE MODE Vss
In the Idle mode; the CPU puts itself to sleep while Circuit ground.
all the on chip peripherals stay active. The instruc-
tion that invokes the Idle mode is the last instruction
executed in the normal operating mode before Idle PortO
mode is activated. The content of CPU, the on chip
RAM, and all the Special Function Registers remain Port Ois an 8-bit open drain bi-directional 1/0 port.
intact during this mode. The Idle mode can be termi- Port 0 pins that have 1's written to them float, and in
nated either by any enabled interrupt, at which time that state can be used .as high-impedance inputs.
the process is picked up at the interrupt service rou-
tine and continued, or by a hardware reset which Port 0 is also the multiplexed low-order address and
starts the processor the same as a power on reset. data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1s; Port 0 al~9 outputs the
POWER DOWN MODE code bytes during program verification in the
80C51 SH. External pullups are required during pro-
In the Power Down mode the oscillator is stopped, gram verification.
and the instruction that invokes Power Down is the
last instruction executed. The· on-chip. RAM and
Special Function Registers retain their values until Port 1
the Power Down mode is terminated.
Port 1 is an 8-bit bidirectional I/O port with internal
The only exit from Power bown is a hardware reset. pullups. Port 1 pins that have 1s written to them are
Reset redefines the SFRs but does not change the pulled high by the internal pull ups, and in that state
on-chip RAM. The reset should not be activated be- can be used as inputs. As inputs, Port 1 pins that are
fore Vee is restored to its normal operating level and externally being pulled low will source current (ilL,
must be held active long enough to allow the oscilla- on the data sheet) because of the internal pullups.
tor to restart and stabilize.
The control bits for the reduced power modes are in Port 2
the Special Function Register PCON.
Port 2 is an 8-bit bidirectional 1/0 port with'internal
NOTE: pullups. Port 2 pins that have 1s written to them are
For more detailed information on these reduced pulled high by the internal pullups, and in that state
power modes refer to Application Note AP-252, can be used as inputs. As inputs, Port 2 pins that are
"Designing with the 80C51 SH". externally being pulled low will source current (ilL,
on the data sheet) because of the internal pull ups.
PIN DESCRIPTIONS Port 2 emits the high-order address byte during
fetches from external Program Memory and during
Vee
Supply voltage during normal, Idle, and Power Down
operations.
Table 1. Status of the external pins during Idle and Power Down modes
Program
Mode ALE PSEN PORTO PORT 1 PORT 2 PORT 3
Memory
Idle Internal 1 1 Data Data Data Data
, Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
10-58
intJ 80C51BH, -1, -2/80C31BH, -1,-2
INDEX
Pl.0 VCC CORNER
Pl.l PO.O
Pl.2 PO.l
Pl.3 PO.2
Pl.4 PO.3 P1.5 ~(~ ~~ PO.4
Pl.5 PO.4 Pl.6 )=~ :~ PO.S
Pl.6 PO.5 ' Pl.7 :.: ~ ~~! PO.6
Pl.7 PO.I RST !~1 ~H PO.7
RST PO.7
P3.0/RXD EA P3.0 H] ~~ EA
P3.1/TXD ALE NC 1~ ~ r~ NC
P3.2/iN'fii iiSEN P3.1 ~~~ ~~ ALE
P3.3INTl P2.7 P3.2 !! ~ ~}~ PSEN
P3.4/TO 'P2.6 r~! P2.7
P3.3 ~~!
P3.S/Tl P2.5
P3.6/WR P2.4
P3.4 !!; rM P2.6
P3.7/iii) P2.3 P3.S j!] r~ P2.S
XTAL2 P2.2 :~: ;~: :2: :;;: ;R: :A~ ::: r~; ;i: ;s;; :~:
XTALl P2.1
VSS P2.0
270064-2 270064-3
Pin Pad
Diagrams are for pin reference only.
Package sizes ,are not to scale.
Figure 2. Connection Diagrams
accesses to external Data Memory' that use 16-bit RST
addresses (MOVX @DPTR). In this, application it
uses strong internal pullups when emitting 1s. Dur- Reset input. A high on this pin for two machine cy-
ing accesses to external Data Memory that use S-bit cles whiie the oscillator is running resets the device.
addresses (MOVX @Ri), Port 2 emits the conten(s of An internal diffused resistor to Vss permits Power-
the P2 Special Function Register. On reset using only an external capacitor to Vee.
Port 3 ALE
Port 3 is an S-bit bidirectional 110 port with internal Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
pullups. Port 3 pins that have 1s written to them are
pulled high by the internal pullups, and in that state. memory.
can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (ilL, In normal operation ALE is emitted at a constant
on the data sheet) because of the pullups. rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
Port 3 also serves the functions of various special however,that one ALE pulse is skipped during each'
features of the MCS-51 Family, as listed below: access to external Data Memory.
Port Pin Alternate Function
P3.0 RXD (serial input port)
P3.1 TXD (serial output port) Program Store Enable is the read strobe to external
Program Memory.
P3.2 INTO (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
P3.6 WR (external data memory write
strobe)
P3.7 RD (external data memory read
strobe)
10-59
inter 80C51BH, ~1, -2/80C31BH, -1,-2
When the 80C51 BH is executing code from external ured for use as an on-chip oscillator, as shown in
Program Memory, PSEN is activated twice each ma- Figure 3. More detailed information concerning the
chine cycle, except that two PSEN activations are use of the on-chip oscillator is available in Applica-
skipped during each access to external Data Memo- tion Note AP-155,. "Oscillator for Microcontr'ollers".
ry. PSEN is not activated during fetches from inter-
nal program memory. To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require-
EA ments on the duty cycle of the external clock signal,
External Access enable. EA must be strapped to since the input to the internal clocking circuitry is
Vss in order to enable the device to fetch code from through a divide~by-two flip"flop, but minimum and
external Program Memory locations· OOOOH to maximum high and low times specified on the Data
Sheet must be observed. .
OFFFH. If EA is strapped to Vee the device executes
from internal Program Memory unless the program
counter contains an address greater than. OFFFH.
Design Considerations
• At power on, the voltage on Vee and RST must
XTAL1 a
come up at the same time for proper start-up.
Input to the inverting oscillator amplifier and input to. • Before entering· the Power Down mode the con-
the internal clock generator circuits. tents oUhe Carry Bit and B.7 must be equal.
• When the Idle mode is terminated by a hardware
reset, the device normally resumes program exe-
XTAL2 cution, from where it .left off, up to two machine
Output from the inverting oscillator amplifier. cycles before the internal reset algorithm takes
control: On-chip hardware inhjbits access to inter-
nal RAM in this event, but access to the port pins
is, not inhibited. To elimin.ate the possibility of an
unexpected write when Idle is terminated by re-
30pF" set, the instruction following the .one that invokes
Idle should not be on~ that writes to a port pin or
to external memory. ..
t - - - - - - - - I vss
NC
270064-4 XTAL2
Figure 3. Crystal OSCillator EXTERNAL
OSCILLATOR --~----------1 XTAL 1
SIGN~L
':,: .
Oscillator, Characteristics VSS
XTAL 1 and XTAL2 are the inpl,lt and output, respec-
tively, of an inverting ,amplifier which can be config-
270064-5.
Figure 4. External Drive Configuration
10-60
inter 80C51BH, -1, -2/80C31BH, -1,-2
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may caU.se permanent dam-
Ambient Temperature Under Bias .... o'e to + 70'e age to the device. This is a stress rating only and
Storage Temperature .......... - 65'e to + 150~e functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on any
tional sections of this specification is not implied Ex-
Pin to Vss ................ -0.5V to Vcc + 0.5V posure to absolute maximum rating conditions for
Voltage on Vcc to Vss ............. -0.5V to 6.5V extended periods may affect device reliability..
Power Dissipation ......................... 1.0W·
"This value is based on the maximum allowable die temperature and NOTICE Specifications contained within the
the thermal resistance of the package. following tables are subject to change.
D.C. CHARACTERISTICS (TA = o'e to 70'e; Vcc = 5V ± 20%; Vss = OV)
Symbol Parameter Min Typ(3) Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 Vee -0.1 V
(ExceptEA)
VIL1 Input Low Voltage (EA) -0.5 0.2 Vee - 0.3 V
VIH ,Input High Voltage 0.2 Vee + 0.9 Vee + 0.5 V
(Except XT AL 1, RST)
VIH1 Input High Voltage 0.7 Vee Vee + 0.5 V
(XTAL1, RSn
VOL Output Low Voltage 0.45 V IOL = 1.6mA(1)
(Ports 1. 2. 3)
VOL1 Output Low Voltage 0.45 'V IOL = 3.2 mA (1)
, (Port 0, ALE, PSEN)
VOH Output High Voltage 2.4 V IOH = -60 /LA Vee = 5V ±10%
(Ports 1, 2, 3, ALE, PSEN)
0.75 Vee V IOH = -25/LA
0.9 Vee V IOH= -10/LA
VOH1 Output High Voltage 2.4 V IOH = -800 /LA Vee = 5V ± 10%
(Port 0 in External Bus
0.75 Vee V IOH = -300/LA
Mode)
0.9 Vee V IOH = -80 /LA (2)
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1, 2, 3)
ITL Logical 1 to 0 Transition -650 /LA VIN = 2V
Current (Ports 1, 2, 3)
III Input Leakage Current ±10 /LA 0.45 < VIN < Vee
(PortO, EA)
RRST Reset Pulidown Resistor 50 150 . KO
CIO Pin Capacitance 10 pF Test Freq = 1 MHz, T A = 25'C
Icc Power Supply Current:
Active Mode, 12 MHz (4) 11 20 mA
Idle Mode, 12 MHz (4) 1.7 5 mA (5)
I Power Down Mode 5 50 /LA
10-61
80C51BH, -1, -2/80C31BH, -1, ~2
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vou; of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pil')s make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input. , '
2. Capacitive loading on PO,rts 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vcc
specification when the address bits are stabilizing.
a
3. "Typicals" are based on limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature,'5V. '
4. ICCMAX at other frequencies is given by
Active Mode: ICCMAX = 1.47'X FREQ + 2.35
Idle Mode: ICCMAX = 0.33 x FREQ + 1.05 ,
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mAo See Figure 5.
5. See Figures 6 through 9 for Icc test conditions.
2S ,--""r--,--...,-"T1 ~~~VE MODE
1 151---+-----ifr-+-----..I ACTIVE MODE
TYP(3)
XTAL2
XTAL1
10r---+-~___i-~+--~
vss
MAX
IDLE MODE 270064-15
Figure 7. Icc Test Condition, Idle Mode.
TYP(3) All other pins are disconnected.
L:~d:::::::t:=:t=~ IDLE MODE
4MHz BMHz 12MHz 16MHz
FREQ AT XTAL 1
270064-13
Figure 5. Icc vs. Frequency.
Valid only within frequency specifications of
the device under test.
XTAL2
XTALI
vss
270064-14
Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
" I
10-62
inter 80C51BH, -1, -2/80C31BH, -1,-2
Vce- O.S • - - - - - -~~----
. . 0.7 Vee
0.4SV 0.2 Vce -O.l
TCHCL
270064-16
Figure 8. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
Vce
lee~
",---v-
ee... vce
PO
RST Eli
XTAL2
XTALl
vss
270064-17
Figure 9. Icc Test Condition, Power Down Mode. All other pins are disconnected. Vcc = 2V to 6V.
EXPLANATION OF THE AC SYMBOLS P: PSEN.
Q: Output data.
Each timing symbol has 5 characters. The first char- A: AD signal.
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status of that . W: WA signal.
signal. The following is a list of all the characters and X: No longer a valid logic level.
what they stand for. . Z: Float.
A: Address.
C: Clock. EXAMPLE:
D: Input data.
H: Logic level HIGH. TAVLL = Time for Address Valid to ALE Low.
I: Instruction (program memory contents). TLLPL = Time for ALE Low to PSEN Low.
L: Logic level LOW, or ALE.
10-63
80C51BH, -1, -2/80C31BH, -1,-2
A.C. CHARACTERISTICS
(TA = O·C to 70·C, Vee =. 5V ± 20%, Vss = OV, Load Capacitance for Port 0, ALE, and PSEN = 100 pF,
Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12MHzOsc Variable OSCillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency MHz
80C51 BH/80C31 BH 3.5 12
80C51 BH-1 /80C31BH-1 3,5 16
80C51 BH-2/80C31 BH-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL - 40 ns
TAVLL Address Valid to ALE Low 28 TCLCL - 55 ns
TLLAX Address Hold After ALE Low 48 TCLCL - 35 ns
TLLlV ALE Low to Valid Instr In 234 4TCLCL - 100 ns
TLLPL ALE Low to PSEN Low 43 TCLCL - 40 ns
TPLPH PSEN Pulse Width 205 3TCLCL - 45 ns
TPLIV PSEN Low to Valid Instr In 145 .3TCLCL - 105 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 59 TCLCL - 25 ns
TAVIV Address to Valid Instr In 312 5TCLCL - 105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL - 100 ns
TWLWH WR Pulse Width 400 6TCLCL - 100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL - 165 .ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL - 70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL- 150 ns
TAVDV Address to Valid Data In 585 9TCLCL - 165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL - 50 3TCLCL + 50 ns
TAVWL Address Valid to RD or WR Low 203 4TCLCL - 130 ns
TOVWX Data Valid to WR Transition 23 TCLCL - 60 ns
TWHOX Data Hold After WR 33 TCLCL - 50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL - 40 TCLCL + 40 ns
10-64
intJ 80C51BH, -1, -2/80C31BH, -1,-2
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
ALE
---- ---TLLDy----
--TLLWl.-!----TRLAH-t----
------~------, Ir-----------------
TAHDZ
- -TRLAZ TRHD. -
I
--::
PORTO DATA IN
------TAyDy-------
PORT 2 P2.0·P2.7 OR A8·A15 FAOM DPH AI·A1S FROM PCH
270064-6
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
-TAYLL- - - - - - T P l P H - - -
TLLPL
TLUV
TPXIZI--
TPIII- -
INSTR
POATD IN
PORT 2 AI-AtS
270064-7
10-65
intJ 80C51BH, "1, -2/80C31BH, -1,-2
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
-TLLWL--j----TWLWH-----
TWHQX
..L
PORTO DATA OUT INSTR
IN
PORT 2 P2.0 - P2.7 OR AI - A15 FROM DPH AI - A15 FROM PCH
270064-8
10-66
inter 80C51BH, -1, -2/80C31BH, -1,-2
. -
i
L
Wz
§ 0
...t.
cO
]-i!i ]-i
I
I!l
! :!
I
Shift Register Mode Timing Waveforms
10·67
intJ 80C51BH, -1, -2/80C31BH, -1, ~2
EXTERNAL CLOCK DRIVE
" Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency MHz
80C51 BH/80C31 BH 3.5 12
80C51 BH-1/80C31 BH-1 3.5 16
80C51 BH-2/80C31 BH-2 . 0.5 12
TCHCX High Time 20 ns
..
TCLCX LciwTime 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: TA = O·C to 70·C; Vee = 5V ±20%; Vss == OV; Load Capacitance = 80 pF
Parameter··· 12 MHzOsc Variable Oscillator
Symbol Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL p.s
TQVXH Output Data Setup to Clock Rising Edge 700 10TCLCL - 133 ns
TXHQX Output Data Hold After Clock Rising Edge 50 2TCLCL - 117 ns
TXHDX Input Data Hold After Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 700 10TCLCL - 133 ns
EXTERNAL CLOCK DRIVE WAVEFORM.
270064-10
AC TESTING INPUT, OUTPUT WAVEFORMS
vee- o.s
0.45 V
=>( 0.2 VCC·+O.9
0.2 VCC-O.l
-.-=:.::..------
. x=.
270064-11
FLOAT WAVEFORMS
TIMING REFERENCE
POINTS
VOH-O.l V
'--_ _ _---,_....J~ VOL +0.1 V
270064-12
For liming purposes a port pin is no longer floating when a
AC Inpuls during testing are driven at Vee -.0.5 for a logic "1" 100 mV change .from load voltage occurs, and begins to float
and 0.45 V for a logic "0". Timing measurements are made at VIH when a 100 mV change from the loaded VOHIVOl level occurs.
min. for a logic "1" and Vil max. for a logic "0". . IOl/lOH ;;, ± 20 rnA. .
10-68
80C31 BH/80C51 BH
EXPRESS
• Extended Temperature Range • 3.5 to 12 MHz Vee = 5V± 20%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS, products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125°C with Vee = '6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheelspecifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed' here.
September 1987
10-69 Order Number: 270218-002
inter 80C31BH/80C51BH EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature.
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40'C to + 85'C; Vcc = 5V ± 20%; Vss = OV
LImits Test
Symbol Parameter Unit
Min Max C~mdltlons
VIL Input Low Voltage (Except EA) -0.5 0.2Vcc - 0.15 V
VIL1 EA. -0.5V 0.2Vcc - 0.35 V
VIH Input High Voltage (Except XTAL1, RST) 0.2Vcc + 1 VCC + 0.5 V
,.
VIH1 Input High Voltage to XTAL 1, RST 0.7Vcc + 0.1 Vcc + 0.5 V
IlL Logical 0 Input Current (Port 1, 2, 3) -75 jJ-A Vin = 0.45V
ITL Logical 1 to 0 transition -750 jJ-A. Yin = 2.0V
Current (Ports 1, 2, 3)
Table 1 Prefix Identification
Prefix Package Type Temperature Range Burn-In
P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No-
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
OP Plastic Commercial Yes
OD Cerdip Commercial Yes
ON PLCC Commercial Yes
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
• Commercial temperature range Is O'C to 70'C. Extended temperature range is -40'C to +85'C.
• Burn·in is dynamic for a minimum time of 160 hours at 125'C. Vee = 6.9V ±0.25V. following guidelines in MIL·STO·883 .
Method 1015 (Test Condition OJ.
Examples:
P80C31 BH indicates 80C31 BH in a plastic package and specified for commercial temperature range, without
burn·in.
LD80C51 BH indicates 80C51 BH in a cerdip package and specified for extended temperature range with burn·
in.
. 10·70
87C51/87C51-1/87C51-2
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
87CS1-3.S to 12 MHz, Vee = sv ± 10%
87CS1-1-3.S to 16 MHz, Vee = SV ± 10%
87CS1-2-0.S to 12 MHz, Vee = SV ± 10%
• High Performance CHMOS EPROM • Programmable Serial Channel
• Quick-Pulse Programming™ Algorithm • TTL- and CMOS-Compatible Logic
• 2-Level Program Memory Lock Levels
• Boolean Processor • 64K External Program Memory Space
• 128-Byte Data RAM • 64K External Data Memory Space
• 32 Programmable I/O Lines • IDLE and POWER DOWN Modes
• Two 16-Bit Timer/Counters • ONCETM Mode Facilitates System
Testing
• 5 Interrupt Sources
• LCC, PLCC, and DIP Packaging
Available
The 87C51 is the EPROM version of the 80C51 BH. It is fabricated on Intel's CHMOS II-E process. It contains
4K bytes of on-chip Program memory that can be electrically programmed, and can be erased by exposure to
ultraviolet light.
The 87C51 EPROM array uses a modified Quick-Pulse programming algorithm, by which the entire 4K-byte
array can be programmed in about 12 seconds.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue. functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
r----------
~
270147-1
Figure 1. MCS®-S1 Architectural Block Diagram
October 1987
10-71 Order Number: 270147-004
87C51/87C51-1/87C51-2
P"O vee
P", PO.O (AOO)
P"2 PO.l (ADI)
P,,3
P"4
PO.2 (AD2)
PO.3 (AD3)
INDEX
CORNER
"": "! "! "l u
ii: ii: ii: ii: ii: z > ~
g"l
g .. ..'"
N
d d
P"S PD.4 (AD4)
P"6 PO.S (ADS) PO.4
P"7 PO.6 (AD6) PO.S
RESET PO.7 (AD7) PO.6
(RXD) P3.0 EA/VPP RST PO.7
(TXD) P3.1 ALE/PROG P3.0 EA/Vpp
(INTO) P3.2 PSEN NC Ne
(INTI) P3.3 P2.7 (A1S)
P3.1 ALE/PROG
(TO) P3.4 P2.6 (AI4)
P3.2 PSEN
(T1) P3.S P2.S (AI3)
P3.3 P2.7'
(Wil) P3.6 P2.4 (AI2)
P3~4 P2.6
(Rli) P3.7 P2.3 (All)
P3.S P2.S
XTAL2 P2.2 (AID)
XTALI P2.1 (A9)
VSS P2.D (AS)
270147-2
.'" ..'"
..; ~ N
...J
~ ~
x x
>
::;
'"'" u
z
o "-:
'"
~ ~ N N ..
N
DIP 270147-21
LCC/PLCC
Figure 2. Pin Connections .
PIN DESCRIPTION· Port 2: Port 2 is an a-bit b.idirectional 110 port with
internal pullups. Port 2 pins that have 1s written to
Vee: Supply voltage during normal, Idle, and Power them are pulled high by the internal pullups, and in
Down operations. - that state can be used as inputs.. As inputs, Port 2
pins that are externally being pulled IQw will source
Vss: Circuit ground. current (IlL, on the data sheet) because of the inter-
nal pullups.
Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL Port 2 emits the high-order address byte during
inputs. Port 0 pins that have 1s written to them float, fetches from external Program memory and during
and in that state can be used as high-impedance accesses to external Data Memory that use 16-bit
inputs. address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1s.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this During accesses to external Data Memory that use
application it uses strong internal pullups when emit- a-bit addresses (MOVX @Ri), Port 2 emits the con-
ting 1s. ter)ts of the P2 Special Function Register.
Port 0 also receives the code bytes'during EPROM Port 2 also receives some control signals and the
programming, and outputs the code bytes during high-order address bits during EPROM programming
program verification. External pullups are required and program verification.
during program verification.
Port 3: Port 3 is an a-bit bidirectional 110 port with
Port 1: Port 1 is an a-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to
internal pullups. Port 1 pins that have .1 s written to them are pulled high by the internal pullups, and in
them are pulled high by the internal pullups,and in
that state can be used as inputs. As inputs, Port 3
that state can be used as inputs. As inputs, Port 1"
pins that are externally being pulled low will source
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pull-
current (IlL, on the data sheet) because of the inter- ups..
nal pullups.
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
10-72
inter 87C51/87C51-1/87C51-2
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Pin Name Alternate Function XTAL2
P3.0 RXD Serial input line
XTAL 1
P3.1 TXD Serial output line
P3.2
P3.3
INTO
INT1
External Interrupt 0
External Interrupt 1
...------t vss
P3.4 TO Timer 0 external input
270147-3
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe Figure 3. Using the On-Chip Oscillator
P3.7 RD External Data Memory Read strobe
Port 3 also receives some control signals for
EPROM programming and program verification.
NC - XTAL2
RST: Reset input. A logic high on this pin for two EXTERNAL
machine cycles while the oscillator is running resets OSCILLATOR ----I XTAL 1
SIGNAL
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an exter-
nal capacitor to Vee.
ALE/PROG: Address Latch Enable output signal for 270147-4
latching the low byte of the address during accesses
to external memory. This pin is also the program Figure 4. External Clock Drive
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant OSCILLATOR CHARACTERISTICS
rate of 1/6 the oscillator frequency, and may be
XTAL 1 and XTAL2 are the input and output, respec-
used for external timing or clocking purposes. Note,
tively, of an inverting amplifier which can be config-
however, that one ALE pulse is skipped during each
ured for use as an on-chip oscillator, as shown in
access to external Data Memory.
Figure 3.
PSEN: Program Store Enable is the Read strobe to To drive the device from an external clock source,
External Program Memory. When the 87C51 is exe- XTAL 1 should be driven, while XTAL2 is left uncon-
cuting from Internal Program Memory, PSEN is inac- nected, as shown in Figure 4. There are no require-
tive (high). When the device is executing code from ments on the duty cycle of the external clock signal,
External Program Memory, PSEN is activated twice since the input to the internal clocking circuitry is
each machine cycle, except that two PSEN activa- through a divide-by-two flip-flop, but minimum and
tions are skipped during each access to External maximum high and low times specified on the Data
Data Memory. Sheet must be observed.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the 87C51 to IDLE MODE
fetch code from External Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the In Idle Mode, the CPU puts itself to sleep while all
Lock Bits is programmed, the logic level at EA is the on-chip peripherals remain active. The mode is
internally latched during reset. invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
EA must be strapped to Vee for internal program unchanged during this mode. The Idle Mode can be
execution. terminated by any enabled interrupt or by a hard-
ware reset.
This pin also receives the 12.75V programming sup-
ply voltage (Vpp) during EPROM programming. It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes pro-
XTAL 1: Input to the inverting oscillator amplifier and gram execution, from where it left off, up to two ma-
input to the internal clock generating circuits. chine cycles before the internal reset algorithm
takes control. On-Chip hardware inhibits access to
XTAL2: Output from the inverting oscillator amplifi- internal RAM in this event, but access to the port
er.
10-73
infef 87C51/87C51-1/87C51-2
Table 1 Status of the external pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51BH."
pins is not inhibited. To eliminate the possibility of an Lock Bits: Also on th'e chip are two Lock Bits which
unexpected write to a port pin when Idle is terminat- can be left unprogrammed (U) or can be pro-
ed by reset, the instruction following the one that grammed (P) to obtain the following additional fea-
invokes Idle should not be one that writes to a port tures:
pin or to external memory.
Bit 1 Bit2 Additional Features
POWER DOWN MODE U U none
In the Power Down mode the oscillator is stopped, P U • Externally fetched code can not
and the instruction that invokes Power Down is the access internal Program Memory.
last instruction executed. The on-chip RAM and • Further programming disabled.
Special Function Registers retain their values until U P (Reserved for Future definition.)
the Power Down mode is terminated.
P P • Externally fetched code can not
a
The only exit from Power Down is hardware reset. access internal Program Memory.
Reset redefines the SFRs but does not change the • Further programming disabled.
on-chip RAM. The reset should not be activated be- • Program verification is disabled.
fore VCC is restored to its normal operating level and
must be held active long enough to allow the oscilla-
tor to restart and stabilize. When Lock Bit 1 is programmed, the logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch
DESIGN CONSIDERATIONS initializes to a random value, and holds that value
until reset is activated. It is necessary that the
Exposure to light when the device is in operation
latched value of EA be in agreement with the current
may cause logic errors. For this reason, it is suggest-
logic level at that pin in order for the device to func-
ed that an opaque label be placed over the window
tion properly.
when the die is exposed to ambient light.
If using the 87C51 to prototype for the 80C51 BH,
consult the Design Considerations section of the ONCETM MODE
80C51 BH data sheet.
The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51
PROGRAM MEMORY LOCK without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits. 1. Pull ALE low while the device is in reset and
PSEN is high;
Encrypted Verify: The 87C51 implements a 32- 2. Hold ALE low as RST is deactivated.
byte EPROM array that can be programmed by the
customer, and which can then be used to encrypt While the device is in ONCE mode, the PortO pins
the program code bytes during EPROM verification. go into a float state, and the other port pins and ALE
The EPROM verification procedure is performed as and PSEN are weakly pulled high. The oscillator cir-
usual, except that each code byte comes out logical- cuit remains active. While the 87C51 is in this mode,
ly X-NORed with one of the 32 key bytes. The key an emulator or test CPU can be used to drive the
bytes are gone through in sequence. Therefore, to circuit. Normal operation is restored when a normal
read the ROM code, one has to know the 32 key reset is applied.
bytes in their proper sequence.
10-74
inter 87C51/87C51-1/87C51-2
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O°C to + 70°C age to the device. This is a stress rating only and
Storage Temperature , ......... - 65°C to + 150°C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
tional sections of this specification is not implied. Ex-
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V posure to absolute maximum rating conditions for
Power Dissipation .......................... 1.5W extended periods may affect device reliability.
(Based on package heat transfer limitations, not de-
vice power consumption). NOTICE Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS: (TA = O°Cto +70°C;Vcc = 5V ±10%;Vss = OV)
Symbol Parameter Min Typ(1) Max Unit Test Conditions
VIL Input Low Voltage (Except EA) -0.5 .2Vcc-· 1 V
VILl Input Low Voltage to EA 0 .2Vcc-·3 V
VIH Input High Voltage (Except XTAL 1, RST) .2Vcc+·9 Vcc+·5 V
VIHl Input High Voltage (XTAL1, RST) 0.7Vcc Vcc+·5 V
VOL Output Low Voltage (Ports 1,2, 3) 0.45 V IOL = 1.6 rnA (2)
VOLl Output Low Voltage (Port 0, ALE, PSEN) 0.45 V IOL = 3.2 rnA (2)
VOH Output High Voltage (Ports 1. 2. 3, ALE. PSEN) 2.4 V IOH = -60p.A
.75Vcc V IOH = -25p.A
.9Vcc V IOH = -10 p.A
VOHl Output High Voltage (Port 0 in 2.4 V IOH = -BOO p.A
.75Vcc V IOH = - 300 p.A
External Bus Mode) V IOH = -BO p.A (3)
.9Vcc
IlL Logical 0 Input Current (Ports 1. 2. 3) -50 p.A VIN = 0.45 V
IlL Logicall-to-O transition current -650 p.A (4)
(Ports 1, 2. 3)
ILl Input Leakage Current (Port 0) ±10 p.A VIN = VIL or VIH
Icc Power Supply Current:
Active Mode @ 12 MHz (5) 11.5 25 rnA
Idle Mode @ 12 MHz (5) 1.3 4 rnA (6)
Power Down Mode 3 50 p.A
RRST Internal Reset Pulldown Resistor 50 300 kfl
CIO Pin Capacitance _10 pF
NOTES:
1. "Typicals" are based on a limited 'number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp. 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading> 100pF). the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger. or use an address latch with a Schmitt
Trigger STROBE input. ' ,
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specifi-
cation when the address bits are stabilizing.
4. Pins of Ports 1. 2. and 3 source a transition current when they are being externally driven from 1 to O. The transition
current reaches its maximum value when VIN is approximately 2V.
5. IccMAX at other frequencies is given by:
Active Mode: IccMAX = 0.94 x FREQ + 13.71
Idle Mode: IccMAX = 0.14 x FREQ + 2.31
where FREQ is the external oscillator frequency in MHz. IccMAX is given in mAo See Figure 5.
6. See Figures 6 through 9 for Icc test conditions.
10-75
87C51/87C51·1/87C51·2
30
IIAX
ACTIVE IIODE
25
RST
20
XTAL2
I XTALI
VSS
'"E
u
!.! 270147-18
10
Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.
5~--~~+---+---~
TYP(1)
~=±::::::::±:=:t:=J IDLE MODE
4_ SMHz 1211Hz 16MHz
FREQ AT XTAL1 .
270147-16
RST
Figure 5. Icc vs. FREQ. Valid only
within frequency specifications of the XTAL2
device under test. XTALI
VSS
270147-20
Figure 9. Icc Test Condition, Power Down
Mode. All other pins are disconnected.
Vce = 2V to 5.5V.
RST
XTAL2
XTALI
Vss
270147-17
Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
270147-19
Figure 8. Clock Signal Waveform for
Icc tests In Active and Idle Modes.
TCLCH = TCHCL = 5 ns.
10-76
inter 87C51/87C51-1/87C51-2
EXPLANATION OF THE AC SYMBOLS L:Logic level LOW, or ALE.
P:PSEN.
Each timing symbol has 5 characters. The first char- O:Output data.
acter is always a 'r (stands for time). The other R:RD signal.
characters, depending on their positions, stand for T:Time.
the name of a signal or the logical status of that V:Valid.
signal. The following is a list of all the characters and W:WR signal.
what they ~tand for. X:No longer a valid logic level.
Z:Float.
A:Address.
C:Clock. For example,
D:lnput data.
, H:Logic level HIGH. TAVLL = Time from Address Valid to ALE Low.
1:lnstriJction (program memory contents). TLLPL = Time from ALE Low to PSEN Low.
A.C. CHARACTERISTICS: (TA = O°C to + 70°C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency
87C51 3.5 12 MHz
87C51-1 3.5 16
87C51-2 0.5 12
TLHLL ALE Pulse Width 127 2TCLCL:"-40 ns
TAVLL Address Valid to ALE Low 28 TCLCL-55 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 43 TCLCL-40 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instr In 145 3TCLCL-105 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ Input Instr Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instr In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transition 23 TCLCL-60 ns
TWHOX Data Hold After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123· TCLCL-40 TCLCL+40 ns
10-77
inter 87C51/87CS1-1/87C51-2
ALE _ _J
PSEiii
---
PORT 0
......._ - - '
PORT 2 _ _ _J AB-A15
270147-5
External Program Memory Read Cycle
ALE
PSEN I------TLLDV----I'I
----I~--- TRLRH -----I
PORTO INSTR. IN
TAVDV
PORT2 P2.0-P2.7 OR AB-A15 FROM DPH AB-A15 FROM PCH
270147-6
External Data Memory Read Cycle
ALE
PSEN
TLLWL ----1"'1---- TWLWH --'----I
PORTO -
FROM RI OR DPL DATA OUT INSTR. IN
~---TAVWL---~
PORT 2 P2.0-P2.7 ORAB-A15 FROM DPH A8-A 15 FROM PCH
270147-7
External Data Memory Write Cycle
10-78
intJ 87C51/87C51-1/87C51-2
EXTERNAL CLOCK DRIVE EXTERNAL CLOCK DRIVE WAVEFORM
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
87CS1 3.S 12 MHz
87CS1-1 3.S 16
87CS1-2 O.S 12
TCHCX High Time 20 ns 270147-8
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
SERIAL PORT TIMING-SHIFT REGISTER MODE
12 MHz
Variable Oscillator
Symbol Parameter Oscillator Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL /ls
TOVXH Output Data Setup to Clock Rising Edge 700 1OTCLCL -133 ns
TXHOX Output Data Hold After Clock Rising Edge SO 2TCLCL-117 ns
TXHDX Input Data Hold After Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 700 1OTCLCL - 133 ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 4 5 7.
ALE
CLOCK
OUTPUT DATA "-----.,."'-----rJ "----_...JX....._-...JX....._-...JX....._-...JX....._-...JX"----_...J!
WRITE10 'SBUF
I
SET TI
INPUT DATA -----"'""'\.,-'"""\,,-"""1... C":":':'r-'r,.,..",'r---,.r:-:-=\,,...-...r:-~~--...r-c:""',,.-. . ,,.,,.,.:=...,-.. . .,.,,.,.,=",
I. I
CLEAR RI SET RI
270147-9
A.C. TESTING:
INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM
VCC-0.5~ 0.2Vcc+0.9
_ 0.2 Vce-0.1
>C
•
0.45V , ~.....;;.;.....-----....
270147-10 270147-11
For timing purposes a port pin is no longer floating when a 100
AC inputs during testing are driven at Vee - 0.5 for a Logic "1" mV change from load voltage occurs, and begins to float when a
and 0.45V for a Logic "0." Timing measurements are made at VIH 100 mV change from the loaded VOHIVOL level occurs. IOLlioH
min for a Logic "I" and VIL max for a Logic "0". ;, ±20 rnA.
10-79
inter 87C51/87C51-1/87C51-2
EPROM CHARACTERISTICS to identify the device. The Signature bytes identify
the device as an 87C51 manufactured by Intel.
The 87C51 is programmed by a modified Quick-
Pulse Programming™ algorithm. It differs from Older Table 2 shows the logic levels for reading the signa-
methods in the value used for Vpp (Programming ture byte, and for programming the Program Memo-
Supply Voltage) and in the width and number of the ry, the Encryption Table, and the Lock Bits. The cir-
ALE/PROG pulses. cuit configuration and waveforms for Quick-Pulse
Programming™ are shown in Figures 10 and 11.
The 87C51 contains two signature bytes that can be Figure 12 shows the circuit configuration for· normal
read and used by an EPROM programming system Program Memory verification.
Table 2. EPROM Programming Modes
ALEI EAI
MODE RST PSEN P2.7 P2.6 P3.7 P3.6
PROG Vpp
Read Signature 1 0 1 1 0 0 0 0
Program Code Data 1 0 O· Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Pgm Encryption Table 1 0 O· Vpp 1 0 1 0
Pgm Lock Bit 1 1 0 o· Vpp ( 1 1 1 1
Pgm Lock Bit 2 1 0 O· Vpp 1 1 0 0
NOTES: ,
"1" = Valid high for that pin
"0" = Valid low for that pin
Vpp = 12.7SV ± 0.2SV
Vcc = SV ± 10% during programming and verification
*ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100 ILS{± 10
ILS) and high for a minimum of 10 ILS,
+5V
vee
AO-A7 Pl PO PGM DATA
RST EA/Vpp +12.75V
ALE/PROG 25 100)'$ PULSES TO GND
P3.6
PSEN 0
87C51
P3.7
P2.7
XTAL2 P2.6 0
P2.0 A8-All
XTAL 1
-P2.3
Vss
270147-12
Figure 10. Programming Configuration
10-80
inter 87C51/87C51-1/87C51-2
,'------25 PULSES
1 .. "
ALE/PROG:~-----~
'-----'
100!:!s
1'-..
10}'s I.41N1 " :t 10}'s "
ALE/PROG:
aI n n 270147-13
Figure 11. PROG Waveforms
Quick-Pulse Programming™ through 1FH, using the "Pgm Encryption Table" lev-
els. Don't forget that after the Encryption Table is
The setup for Microcontroller Quick-Pulse Program- programmed, verify cycles will produce only encrypt-
mingTM is shown in Figure 10. Note that the 87C51 ed data.
is running with a 4 to 6 MHz oscillator. The reason
the oscillator needs to be running is that the device To program the Lock Bits, repeat the 25-pulse pro-
is executing internal address and program data gramming sequence using the "Pgm Lock Bit" lev-
transfers. els. After one Lock Bit is programmed, further pro-
gramming of the Code Memory and Encryption Ta-
The address of the EPROM location to be pro- ble is disabled. However, the other Lock Bit can still
grammed is applied to Ports 1 and 2, as shown in be programmed.
Figure 10. The code byte to be programmed into
that location is applied to Port O. RST, PSEN, and Note that the EA/vpp pin must not be allowed to go
pins of Ports 2 and 3 specified in Table 2 are held at above the maximum specified Vpp level for any
the "Program Code Data" levels indicated in Table amount of time. Even a narrow glitch above that volt-
2. Then ALE/PROG is pulsed low 25 times as age level can cause permanent damage to the de-
shown in Figure 11. vice. The Vpp source should be well regulated and
free of glitches and overshoot.
To program the Encryption Table, repeat the 25-
pulse programming sequence for addresses 0
10-81
intJ 87C51/87C51-1/87C51-2
+sv
1---1-1' PGt.!
AO-A7 PI 1 - - - . / DATA
RST EA/Vpp
ALE/PROG
P3.6
PSEN 1+---0
B7CSI
P3.7
P2.7 ....- - 0 (ENABLE)
XTAL2 P2.6 ....- - 0
""''''-r-l XTAL 1
vSS
270147-14
Figure 12. Program Verification
Program Verification Program/Verify. Algorithms
If Lock Bit 2 has not been programmed, the on-chip Any algorithm in agreement with the conditions list-
Program Memory can be read out for program verifi- ed in Table 2, and wliich satisfies the timing specifi-
cation. The address of the Program Memory location cations, is suitable. .
to be read is applied to Ports 1 ·and 2 as shown in
Figure 12. The other· pins are held at the "Verify
Code Data" levels indicated in Table 2. The con- Erasure Character.istics
tents of the addressed location will be emitted on
Port O. External pullups ·are required on Port 0 for Erasure of the EPROM begins to occur when the
this operation. Detailed timing specifications are chip is exposed to light with wavelengths shorter
shown in later sections of this data sheet. than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
If the Encryption Table has been programmed, the range, exposure to these light sources over an ex-
data presented at Port 0 will be the Exclusive NOR tended time (about 1 week in sunlight, or 3 years in
of the program byte with one of the encryption bytes. room level fluorescent lighting) could cause inadver-
The user will have to know the Encryption Table tent erasure. If an application subjects the device to
contents in order to correctly decode the verification this type of exposure, it is suggested that an opaque
data. The Encryption Table itself can not be read label be placed over the window.
out.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
Reading the Signature Bytes ed dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
The Signature bytes are read by the same procedure rating for 30 minutes, at a distance of about 1 inch,
as a normal verification of locations 030H and 031 H, should be sufficient.
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are: Erasure leaves the array in an all 1s state..
(030H) = 89H indicates manufactured by Intel
(031 H) = 57H indicates 87C51
10·82
inter 87C51/87C51-1/87C51-2
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA = 21°C to 27°C, vee = 5V ±10%, VSS = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 fJ-s
TGHSL Vpp Hold After PROG 10 fJ-s
TGLGH PROGWidth 90 110 fJ-s
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 fJ-s
EPROM Programming and Verification Waveforms
PROGRAMMING- VERIFICATION-
Pl.0-Plo7
ADDRESS ADDRESS
P2.D-P2.3
-TAVQY
PORT 0 DATA IN DATA OUT
TDVGL -I t- ~ TGHDX
TAVGL - ~ TGHAX
TSHGL-~:"
ALE/Pi!OO
_TGHGL
- - TGLGH 1 _ TGHSL
J LOGIC I LOGIC 1
________ ~G~Q ____
----- ---- ------
P2.7
(ENABLE)
·1. -TEHSH
----,--If
TELQV-
- I-TEHQZ
270147-15
'FOR PROGRAMMING CONDITIONS SEE FIGURE 10.
FOR VERIFICATION CONDITIONS SEE FIGURE 12.
10-83
inter 87C51
EXPRESS
• Extended Temperature Range • 3.S MHz to 12 MHz Vee = SV ± 10%
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temper-
ature range of O'C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range' of - 40'C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125'C with Vee = 6.0V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
October 1987
10-84 Order Number: 270430-001
87C51 EXPRESS
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = OV
Limits Test
Symbol Parameter Unit
Min Max Conditions
VIL Input Low Voltage (Except EA) -0.5 0.2Vee - 0.15 V
VIL1 EA 0 0.2Vee - 0.35 V
VIH Input High Voltage (Except XTAL 1, RST) 0.2Vee +1 Vee + 0.5 V
VIH1 Input High Voltage to XTAL 1, RST 0.7Vee + 0.1 Vee + 0.5 V
IlL Logical 0 Input Current (Port 1, 2, 3) -75 /LA VIN = 0.45V
ITL Logical 1 to 0 transition -750 /LA VIN = 2.0V
Current (Ports 1, 2, 3)
Icc Power Supply Current (Note 1)
Active Mode 35 mA
Idle Mode 6 mA
Power Down Mode 50 /LA
NOTE:
1. Vee = 4.5V-5.5V, Frequency Range = 3.5 MHz-12 MHz.
10-85
87C51 EXPRESS
Table 1 Prefix Identification
Prefix Package Type Temperature Range(2) Burn-ln(3)
P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No
R LCC Commercial No
TP Plastic Extended No
TO Cerdip Extended No
TN PLCC Extended No
TR LCC Extended No
OP Plastic Commercial Yes
OD Cerdip Commercial Yes
ON PLCC Commercial Yes
OR LCC Commercial Yes
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes·
LR LCC Extended Yes
NOTES:
2. Commercial temperature range is O'C to + 70'C. Extended temperature range is - 40'C to + 85'C.
3. Burn-in is dynamic for a minimum time of 160 hours at .+ 125'C, Vee = 6.0V ±0.25V, following guidelines in MIL-STD-
883 Method 1015 (Test Condition D).
Examples:
P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burn-in.
/
10-86
inter 87C51FA (87C252)
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH
PROGRAMMABLE COUNTER ARRAY, UP/DOWN
COUNTER, 8K BYTES USER PROGRAMMABLE EPROM
• High Performance CHMOS EPROM.
• 32 Programmable I/O Lines
• Power Control Modes
• Programmable Serial Channel with:
7 Interrupt Sources
• Three 16-Bit Timer/Counters
• - Framing Error Detection
• Programmable Counter Array with:
- High Speed Output, - Automatic Address Recognition
- Compare/Capture,
- Pulse Width Modulator,
• TTL Compatible Logic Levels
- Watchdog Timer capabilities • 64K External Program Memory Space
• Up/Down Timer/Counter • 64K External Data Memory Space
• Two Level Program Lock System • MCS®-51 Fully Compatible Instruction
Set
• 8K On-Chip EPROM
• Power Saving Idle and Power Down
• 256 Bytes of On-Chip Data RAM Modes
• Quick Pulse Programming™ Algorithm
• ONCETM (On-Circuit Emulation) Mode
• Boolean Processor
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory. .
The Intel 87C51 FA is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
CHMOS II-E technology .. Being a member of the MCS®-51 family, the 87C51 FA uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The
87C51 FA is an enhanced version of the 87C51. It's added features make it an even more powerful microcon-
troller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabili-
ties such as motor control. It also has a more versatile serial channel that facilitates multi-processor communi-
cations.
October 1987
10-87 . Order Number: 270258-002
87C51FA
PO.0-PO.7
,.----------~~~..:..~ -------- ..
~~
VSS
..r
z
Pmi TIMING ~
~IC==~~=~====~:;:=~==::::===::;::~==J
p::
ALE/I'l!l!ll
£A/VPP AND ::>
RST CONTROL ~ ~
;:;
P1.0- P1.7 P3.0-P3.7
270258-1
Figure 1. 87C51FA Block Diagram
10·88
inter 87C51FA
PIN DESCRIPTIONS In addition, Port 1 serves the functions of the follow-
ing special features of the a7C51 FA:
(T2) PLO Vee Port Pin Alternate Function
(T2EX) Plol PO.O (ADO) P1.0 T2 (External Count Input to Timerl
(ECI) Plo2 PO.l (AD1) Counter 2)
(CEXO) Pl.3 PO.2 (AD2)
P1.1 T2EX (Timer/Counter 2 Capturel
(CEX1) Plo4 PO.3 (AD3) Reload Trigger and Direction Control)
(CEX2) Pl.S PO.4 (AD4)
P1.2 ECI (External Count Input to the PCA)
(CEX3) Pl.S PO.S (ADS)
P1.3 CEXO (External 1/0 for Comparel
(CEX4) Pl.7 PO.S (ADS)
Capture Module 0)
RESET PO.7 (AD7)
P1.4 CEX1 (External 1/0 for Compare/
(RXD) P3.0 EA/Vpp
Capture Module 1)
(TXD) P3.l ALE/PROG
P1.5 CEX2 (External 1/0 for Comparel
(iNTO) P3.2 PSEN
Capture Module 2)
(iNT1) P3.3 P2.7 (A1S)
(TO) P3.4
P1.6 CEX3 (External I/O for Comparel
P2.S (A14)
Capture Module 3)
(n) P3.S P2.S (A13)
(ViR) P3.S P2.4 (A12)
P1.7 CEX4 (External 1/0 for Comparel
Capture Module 4)
(Rii) P3.7 P2.3 (All)
XTAL2 P2.2 (Al0)
XTALl P2.l (A9)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Vss P2.0 (AB)
270258-2 Port 2: Port 2 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
Figure 2. Pin Connections LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
Vee: Supply voltage. that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
Vss: Circuit ground. current (IlL, on the data sheet) because of the inter-
nal pullups.
Port 0: Port 0 is an a-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS Port 2 emits the high-order address byte during
TIL inputs. Port 0 pins that have 1's written to them fetches from external Program Memory and during
float, and in that state can be used as high-imped- accesses to external Data Memory that use 16-bit
ance inputs. addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. Dur-
Port 0 is also the multiplexed low-order address and ing accesses to external Data Memory that use a-bit
data bus during accesses to external Program and addresses (MOVX @Ri), Port 2 emits the contents of
Data Memory. In this application it uses strong inter- the P2 Special Function Register.
nal pullups when emitting1's, and can source and
sink several LS TIL inputs. Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
Port 0 also receives the code bytes during EPROM tion.
programming, and outputs the code bytes during
program verification. External pullup resistor~ are re- Port 3: Port 3 is an a-bit bidirectional 1/0 port with
quired during program verification. internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to
Port 1: Port 1 is an a-bit bidirectional 1/0 port with them are pulled high by the internal pullups, and in
internal pullups. The Port 1 output buffers can drive that state can be used as inputs. As inputs, Port 3
LS TIL inputs. Port 1. pins that have 1's written to pins that are externally being pulled low will source
them are pulled high by the internal pull ups, and in current (IlL, on the data sheet) because of the pull-
that state can be used as inputs. As inputs, Port 1 ups.
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the inter-
nal pullups.
10-a9
intJ 87C51FA
Port 3 also serves the functions of various special QSCILLATOR CHARACTERISTICS
features of the MCS-51 Family, as listed below:
XTAL 1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
Port Pin Alternate Function ured for use as an on-chip oscillator, as shown in
P3.0 RXD (serial input port) Figure 3. Either a quartz crystal or ceramic resonator
P3.1 TXD (serial output port) may be used. More detailed information. concerning
P3.2 INTO (external interrupt 0) the use of the on-chip oscillator is available in Appli-
cation Note AP-155, "Oscillators for Microcontrolc
P3.3 INT1 (external interrupt 1)
lers."
P3.4 TO (Timer 0 external input)
P3.5 T1 (Timer 1 external input) To drive the device from an external clock source,
P3.6 WR (external data memory write strobe) XTAL1 should be driven, whileXTAL2 floats, as
P3.7 RD (external data memory read strobe) shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in-
RST: Reset input. A high on this pin for two machine put to the internal clocking circuitry is through a di-
cycles while the oscillator is running resets the de- vide-by-two flip-flop, but minimum and maximum
vice. An internal pulldown resistor permits a power- high and low times specified on the data sheet must
on reset with only a capacitor connected to Vee. be observed.
ALE: Address Latch Enable output pulse for latching
C2
the low byte of the address during accesses to ex-
I - - t - - - I XTAL2.
ternal memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FA.
1 - -.....--1 XTAL 1
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used t - - - - - - - I Vss
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac- 270258-3
cess to external Data Memory. C1, C2 = 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG Figure 3. Oscillator Connections
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to N/C XTAL2
external Program Memory.
EXTERNAL
When the 87C51FA is executing code from external OSCILLATOR XTAL 1
Program Memory, PSEN is activated twice.each ma- SIGNAL
chine cycle, except that two PSEN activations are Vss
skipped during each access to external Data Memo-
ry.
270258-4
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to Figure 4. External Clock .Drive Configuration
fetch code from external Program Memory locations
OOOOH to 1FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be inter- IDLE MODE
nally latched on reset. .
The user's software can invoke the Idle Mode. When
EA should be strapped to Vee for internal program the microcontroller is in this mode, power consump-
executions. . tion is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
This pin also receives the programming supply volt- the processor stops execiJting instructions. Idle
age (Vpp) during EPROM programming. Mode will be exited if the chip is reset or if an en-
abled interrupt occurs. The PCA timer/counter can
XTAL 1: Input to the inverting oscillator amplifier. optionally be left running or paused during Idle
Mode.
XTAL2: Output from the inverting oscillator amplifier.
10-90
intJ 87C51FA
POWER DOWN MODE • When the idle mode is terminated by a hardware
reset, the device normally resumes program exe-
To save even more power, a Power Down mode can cution, from where it left off, up to two machine
be invoked by software. In this mode, the oscillator cycles before the internal reset algorithm takes
is stopped and the instruction that invoked Power control. On-chip hardware inhibits access to inter-
Down is the last instruction executed. The on-chip nal RAM in this event, but access to the port pins
RAM and Special Function Registers retain their val- is not inhibited. To eliminate the possibility of an
ues until the Power Down mode is terminated. unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes
On the 87C51 FA either a hardware reset or an ex- Idle should not be one that writes to a port pin or
ternal interrupt can cause an exit from Power Down. to external memory.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values. ONCETM MODE
The interrupt must be enabled and configured as
level sensitive. To properly terminate Power Down The ONCE ("On-Circuit Emulation") Mode facilitates
the reset or external interrupt should not be execut- testing and debugging of systems using the
ed before Vee is restored to its normal operating 87C51 FA without the 87C51 FA having to be re-
level, and must be held active long enough for the moved from the circuit. The ONCE Mode is invoked
oscillator to restart and stabilize. by:
1) Pull ALE low while the device is in reset and
PSEN is high;
DESIGN CONSIDERATION 2) Hold ALE low as RST is deactivated.
• Ambient light is known to affect the internal RAM
While the device is in ONCE Mode, the Port 0 pins
contents during operation. If the 87C51 FA appli-
cation requires the part to be run under ambient go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator cir-
lighting, an opaque label should,be placed over
the window to exclude light. cuit remains active. While the 87C51 FA is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a nor-
mal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Mode ALE PSEN PORTO PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Applica-
tion Note AP-252, "Designing with the 80C51BH."
10-91
inter 87C51FA
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O°C to + 70°C age t'o the device. This is a stress rating only and
Storage Temperature .......... - 65°C to + 150°C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
tional sections of this specification is not implied Ex-
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V posure to absolute maximum rating conditions for
Power Dissipation .......................... 1.5W extended periods may affect device reliability.
(based on PACKAGE heat transfer limitations, not
device power consumption) NOTICE Specifications contained within the
. following tables are subject to change.
ADVANCED INFORMATION-CONTACT
. INTEL FOR DESIGN-IN INFORMATION
. .
D.C. CHARACTERISTICS: (TA = ,
O°Cto +70°C'Vcc = ,
5V +10%'VsS
- = OV)
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2Vcc-0.1 V
VIL1 Input Low Voltage EA 0 0.2 Vcc-0.3 V
VIH Input High Voltage 0.2Vcc+0.9 Vcc+0.5 V
(Except XTAL2, RST, EA)
VIH1 Input High Voltage 0.7Vcc Vcc+ 0.5 V
(XTAL, RST)
VOL Output Low Voltage 0.45 V IOL = 1.6 mA(1)
(Ports 1 , 2 and 3)
VOL1 Output Low Voltage _ _ 0.45 V IOL = 3.2 mA(1)
(Port 0, ALE/PROG, PSEN)
VOH Output High Voltage 2.4 V IOH = -60,..,A
(Ports 1 , 2 and 3
ALE/PROG and PSEN) V IOH = -10,..,A(2)
0.9Vcc
VOH1 Output High Voltage 2.4 V IOH = -800,..,A
(Port 0 in Exfernal Bus Mode) 0.9VCC V IOH = -80,..,A(2)
IlL Logical 0 Input Current -50 ,..,A VIN = 0.45V
(Ports 1 , 2, and 3)
III Input leaka~Current ±10 ,..,A VIN = VIL or VIH
(Port 0 and EA)
ITL Logical 1 to 0 Transition Current -650 ,..,A VIN = 2V
(Ports 1, 2, and 3)
RRST RST Pulldown Resistor 40 225 KO
CIO Pin Capacitance 10 pF @1MHz, 25°C
Icc Power Supply Current: (Note 3)
Running at 12 MHz (Figure 5) 30 rnA
Idle Mode at 12 MHz (Figure 5) 7.5 mA
Power Down Mode 100 ,..,A
NOTES:
1. Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1 to
a transitions during bus operations. In applications where capacitance loading exceeds 1aa pFs, the noise pulse on the ALE
signal may exceed a.BV. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger. or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports a and 2 cause the VOH on ALE and PSEN to drop below the a.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions.
10-92
intJ 87C51FA
40mA
30mA
"'AX.
20mA
ACTIVE V RST
V_ V -
....
TYPICAL
B7C51FA
IOmA
OmA
-- r-'DLE MAX.
TYPICAL
XTAL2
XTALl
vss
OMHz 4t.1Hz StAHz 12MHz 16MHz
270258-5 270258-6
ICC Max at other frequencies is given by:
All other pins disconnected
Active Mode
TCLCH = TCHCL = 5 ns
Icc MAX = 2.2 X FREQ + 3.1
Idle Mode
Icc MAX = 0.49 x FREQ + 1.6 Figure 6. Icc Test Condition, Active Mode
Where FREQ is in MHz, IccMAX is given in rnA.
Figure 5. Icc vs Frequency
RST
B7C252
XTAL2
XTALf
Vss
270258-7 270258-8
All other pins disconnected All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 9. Icc Test Condition, Power Down Mode.
Figure 7. ICC Test Condition Idle Mode Vcc = 2.0V to 5.5V.
Vee· a.s • - - - - - -~~----..,.
a.7 vee
a.4SV ---1(a;2 vce-a.t
TCHCL
270258-19
Figure S. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TClCH = TCHCl = 5 ns.
10-93
inter 87C51FA
EXPLANATION OF THE AC SYMBOLS L: Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters. The first char- Q: Output Data
acter is always a 'T' (stands for time). The other R: RD signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
0: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low
A.C. CHARACTERISTICS (TA = o·C to + 70·C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol 12 MHz Oscillator Variable Oscillator
Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12 MHz
TLHLL ALE Pulse Width 127 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 28 TCLCL-55 ns
~LLAX Address Hold After ALE Low 48 TCLCL-35 ns
~LLlV ALE Low to Valid Instruction In 234 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 43 TCLCL-40 ns
~PLPH PSEN Pulse Width 205 3TCLCL""""45 ns
TPLIV PSEN Low!o Valid Instruction In 145 3TCLCL-105 ns
~PXIX Input Instruction Hold After PSEN 0 0 ns
~PXIZ Input Instruction Float After PSEN 59 TCLCL-25 ns
TAVIV Address to Valid Instruction In 312 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 ns
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH WR Pulse Width 400 6TCLCL-100 ns
TRLDV RD Low to Valid Data In 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to WR Low 203 4TCLCL-130 ns
TQVWX Address Valid before WR 23 TCLCL-60 ns
~WHQX Data Hold after WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 43 123 TCLCL-40 TCLCL+40 ns
10-94
inter 87C51FA
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
PORT a
----'
PORT 2 _ _ _J AB-A15
270258-9
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
1 - - - - - - TLLDV 'I
---0-1---- TRLRH _ - - - I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR AB-A15 FROM DPH AB-A15 FROM PCH
270258-10
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL--~---TWLWH---I
I---+---TQVWH - - - - - i
],--~~-""""Ii.
PORTO DATA OUT INSTR. IN
PORT2 P2.0-P2.7 OR AB-A15 FROM DPH AB-A 1 5 FROM PCH
270258-11
10-95
inter 87C51FA
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O·C to + 70·C; vee = 5V +
- 10%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1 12TCLCL IJ.s
TQVXH Output Data Setup to Clock 700 1OTCLCL -133 ns
RiSing Edge
TXHQX Output Data Hold after 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After Clock 0 0 ns
Rising Edge
TXHDV Clock Rising Edge to Input 700 1OTCLCL -133 ns
Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 3.5 12 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270258-13
10-96
inter 87C51FA
A.C. TESTING INPUT
Input, Output Waveforms Float Waveforms
>C
VCC-0.5-=::X: 0.2 VCC+0.9 VOH-D.l V
TIMING REFERENCE
POINTS
0.45 V 0.2 VCC-O.l VOL +0.1 V
270258-15
270258-14
For timing purposes a port pin is no longer floating when a
AC Inputs during testing are driven at Vee-0.5V for a Logic "1" 100 mV change from load voltage occurs, and begins to float
and 0.45V for a Logic "0". Timing measurements are made at V,H when a 100 mV change from the loaded VOHIVOl level occurs.
min for a Logic "1" and VOL max for a Logic "0". IOl/lOH ;, ± 20 mA.
EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program' Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
ALEI EAI
Mode RST PSEN P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 O· Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Table 1 0 O' Vpp 1 0 0 1
Use Addresses 0-1 FH
Program Lock x=1 1 0 O' Vpp 1 1 1 1
Bits (LBx) x=2 1 0 O' Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0
NOTES:
"1" = Valid high for that pin
'0" = Valid low for that pin
"VPP" = +12.75V ±0.25V
• ALE/PROG is pulsed low for 100 /Jos for programming. (Quick·PulseProgramming™)
PROGRAMMING THE EPROM Normally EAIVpp is held at logic high un_!!!...iust be-
fore ALE/PROG is to be pulsed. Then EAIVpp is
To be programmed, the part must be running with a raised to Vpp, ALE/PROG is pulsed low, and then
4 to 6 MHz oscillator. (The reason the oscillator EAIVpp is returned to a valid high Voltage. The volt·
needs to be running is that the internal bus is being age on the EAIVpp pin must be at the valid EAIVpp
used to transfer address and program data to appro· high level before a verify is attempted. Waveforms
priate internal EPROM locations.) The address of an and detailed timing specifications are shown in later
EPROM location to be programmed is applied to sections of this data sheet.
Port 1 and pins P2.0 • P2.4 of Port 2, while the code
byte to be programmed into that location is applied Note that the EAIVpp pin must not be allowed to go
to Port O. The other Port 2 and 3 pins, RST PSEN, above the maximum specified Vpp level for any
and EAIVpp should be held at the "Program" levels amount of time. Even a narroW glitch above that volt-
indicated in Table 2. ALE/PROG is pulsed low to age level can cause permanent damage to the de·
program the code byte into the addressed EPROM vice. The Vpp source should be well regulated and
location. The setup is shown in Figure 10. free of glitches.
10·97
intJ 87C51FA
+5V
Vee
AO-A7 P1 PO PGM DATA
RST EA/Vpp ....--+12.75V
ALE/PROG ....- - 2 5 100}-" PULSES TO GND
P3.6
PSEN 1+---0
87C51FA
P3.7
P2.7
XTAL2 P2:6 ....- - 0
\
. XTAL 1. P2.0
-P2.4
Vss
270258-20
Figure 10. Programming the EPROM
Quick-Pulse Programming™ Algorithm Program Verification
The 87C51 FA can be programmed using the Quick- If the Program Lock. Bits have not been pro-
. Pulse Programming™ Algorithm for microcontrol- grammed, the on-chip Program Memory can be read
lers. The fe.?tures of the new programming method out for verification purposes, if desired, either during
area lower Vpp (12.75V as compared to 21V) and a or after the programming operation. The address of
shorter programming pulse. It is possible to program the Program Memory location to be read is applied
the entire 8K Bytes of EPROM memory in less than to Port 1 and pins P2.0 - P2.4. The other pins should
25 seconds with this algorithm! be held at the "Verify" levels indicated in Table 3.
The contents of the addressed locations will come
To program the part using the new algorithm, Vpp out on Port O. External pullups are required on Port 0
must be 12.75V ±0.25V. ALE/PROG is pulsed low for this operation. .
for 100 ,..,S, 25 times as shown in Figure 11. Then,
the byte just programmed may be verified. After pro- If the Encryption Array in the EPROM has been pro-
gramming, the entire array should be ver.ified. The grammed, the data present at Port 0 will be Code
Program Lock features are programmed using the Data. XNOR Encryption Data. The user must know
same method, but with the setup aS,shown in Table the Encryption Array contents to manually "unen-
2. The only difference in programming Program Lock crypt" the data during verify.
features is that the Program Lock features cannot be
directly verified. Instead, verification of programming The.setup, which is shown in Figure 12, is the same
is by observing that their features are enabled. as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
low read strobe.
10-98
intJ 87C51FA
1 ~I'------2S PULSES - - - - - . - J ' I
ALE/PROG:---:utJLllJt - - - - -
'--'
ULWu-
1 "-. 10}'! MIN1 I' !~~'t: 'I
ALE/PROG:---":o~I _ _ _ _ _ _... nL_____--In. .___
270258-21
Figure 11. PROG Waveforms
Vee
I-_LJ\. PGM
AD-A7 PI PO
t - - - - . / DATA
RST EA/Vpp
ALE/PROG
P3.6
PSEN ....- - 0
87CSIFA
P3.7
P2.7 1 + - - 0 (ENABLE)
XTAL2 P2.6 1+---0
'--'-"'-:1---1 XTAL 1 P2.0 1/L--A8-_A 12
-P2.4 \.~-:.;;;....
Vss
270258-22
Figure 12. Verifying the EPROM
10-99
87C51FA
EPROM Program Lock Reading the Signature Bytes
The two-level Program Lock system consists of two The signature bytes are read by the same procedure
Program Lock bits and a 32 byte Encryption Array as a normal verification of locations 030H and 031 H,
which are used to protect the .program memory except that P3.6 and P3.7 need to be pulled to a
against software piracy. . logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031H) = 50H indicates 87C51FA
Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every Erasure Characteristics
time that a byte is addressed during a verify, 5 ad- Erasure of the EPROM begins to occur when the
dress lines are used to select a byte of the Encryp- chip is exposed to light with wavelength shorter than
tion Array. This byte is then exclusive-NOR'ed approximately 4,000 Angstroms. Since sunlight and
(XNOR) with the code byte, creating an Encrypted fluorescent lighting have wavelengths in this range,
Verify byte. The algorithm, with the array in the un- exposure to these light sources over an extended
programmed state (all 1's), will return the code in it's time (about 1 week in sunlight, or 3 years in room-
original, unmodified form. level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it i~ suggested that an opaque la-
Program Lock Bits bel be placed over the window.
Also included in the EPROM Program Lock scheme
The recommended erasure procedure is exposure
are two Program Lock Bits which are programmed
to ultraviolet light (at 2537 Angstroms) to an integrat"
as shown in Table 2.
ed dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 p..W/cm rat-
Table 3 outlines the features of programming the
Lock Bits.
ing for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasing the EPROM also erases the Encryption Ar-
Erasure leaves the all EPROM Cells in a 1's state.
ray and the Program Lock Bits, returning the part to
full functionality.
Table 3 Program Lock Bits and their Features
Program Lock Bits
Logic Enabled
LB1 LB2
U U No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)
P U MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled.
P P Same as above, but Verify is also disabled
U P Reserved for Future Definition
10-100
inter 87C51FA
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 2rc; Vee = 5V±0.25V; vss = OV)
(TA
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 V
Ipp Programming Supply Current 50 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 /Ls
TGHSL Vpp Hold after PROG 10 /Ls
TGLGH PROG Width 90 110 /Ls
TAVOV Address to Data Valid 48TCLCL
TELOV ENABLE Low to Data Valid 48TCLCL
TEHOZ Data Float after ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 /Ls
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
Pl.0-Pl.?
ADDRESS ADDRESS
P2.0-P2.4
-TAVQV
PORT 0 DATA OUT
TGHDX
TAVGL
ALE/PROG
TSHGLr---
EIi/vpp
1
TGLGH
~.-:.-,,","
Vpp EA/HIGH
TEHQZ
P2.?
TELQVl
}
270258-18
10-101.
83C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY
MASK PROGRAMMABLE ROM
80C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
• Superset of 80C51BH Architecture
• 64KB Data Memory Addressing
• 1/0 Port (1.5 Mbps/2.4 Mbps Max)
Multi-Protocol Serial Communication
• Dual On-Chip DMA Channels
256 Bytes On-Chip RAM
-SDLC • Hold/Hold Acknowledge
-HDLC • Two General Purpose Timer/Counters
-CSMA/CD
- User Definable Protocols • 56 Special Function Registers
• Full Duplex/Half Duplex • 11 Interrupt Sources
• MCS®-51 Compatible UART • Available in 48 Pin Dual-in-Line Package
• 12 MHz Maximum Clock Frequency • and 68 Pin Surface Mount PLCC
• Multiple Power Conservation Modes Package
• 64KB Program Memory Addressing
(See Packaging Spec. Order # 231369)
The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applica-
tions. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multiwire cables found in board level parallel-to-se-
rial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial-to-
parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modulari-
ty of hardware and software designs. All of these-cost, network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
(GRXO) no I
(GTDX) Pl.! 2
(DEN) P1.2 :3
(i'Xc) PI.3 04
(m) PI.4 5 P4.6
(RIB) P1.5 PO
(HLDA) PloG RESET 13 N.C.
P3.D 14
(TXD) P3.1 80C152A
(imo) P3.2 P3.3 18 83C152A
(iNTi) P3.3 13 Pl.4 19
N.C.
P2.7
P3.S P2.6
P3.6 P2.S
P3.7
270188-3
270188-2
Figure 1. Connection Diagrams
September 1987
10-102 Order Number: 270188-003
r
P4.0-P4.7 P2.0-P2.7
-----" (
I SARL1
I SARHl
DARLl
I
DARHl
BCRL1
I
~
c...CD I CD
0
....
0
o m
~·o
~
oc.J :III"
n
I TLO IPNl
en
N
l>
.....
SBUf(RX) CD
Co)
THO IENl
C
iii· TL1 IP
~~~f~Tit~ ....0en
...
(Q
DI
THl IE
SCON
N
l>
3
~
'lEJ
aID
Iiiiil
ADRO-3
IF'
BAUD ~
_-.J ~
P1.0- P1.7 P3.0- P3.7 270188-1
~
aID
~
inter 80C152A/83C152A
Pin # Pin Description
DIP PLCC(1)
48 2 Vcc-Supply voltage.
24 3,33(2) Vss-Circuit ground.
18-21, 27-30, Port O-Port 0 is an 8-bit open drain bidirectional 110 port. As an output port each pin
25-28 34-37 can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external memory. In this application it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pull ups are
required during program verification. .
1-8 4-11 Port 1-Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Pin Name Alternate Function
P1.0 GRXD GSC data input pin
P1.1 GTXD GSC data output pin
P1.2 DEN GSC enable signal for an external driver
P1.3 TXC GSC input pin for external transmit clock
P1.4 RXC GSC input pin for external receive clock
P1.5 HLD DMA hold input/output
P1.6 HLDA DMA hold acknowledge input/output
29-36 41-48 Port 2-Port 2 is an 8~bit bidirectional 1/0 port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally being pulled IQw will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory and during accesses to external Data Memory that use 16-bit addresses
(MOVX @ DPTR and DMAoperations). In this application it uses strong internal pullups
when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
10-17 14-16, Port 3-Port 3 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 3 pins that
18,19, have 1s written to them are pulled high by the internal pullups, and in that state can be
23-25 used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin Name Alternate Function
P3.0. RXD Serial input line
P3;1 TXD Serial output line
P3.2 INTO External Interrupt 0
P3.3 INT1 External Interrupt 1
P3.4 TO Timer 0 external input
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe
P3.7 RD External Data Memory Read strobe
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-104
intJ 80C152A/83C152A
Pin Description (Continued)
Pin # Pin Description
47-40 65-58 Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.
9 13 RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.
38 55 ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory. .
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.
37 54 PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
39 56 EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.
23 32 XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.
22 31 XTAL2-0utput from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL2
XTAL 1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config- XTAL 1
ured for use as an on-chip oscillator, as shown in
Figure 3. t - - - - - - I Vss
To drive the device from an external clock source, ,270188-4 .
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require- Figure 3. Using the On-Chip Oscillator
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data NC XTAL2
Sheet must be observed. . EXTERNAL
OSCILLATOR XTAL 1
SIGNAL
Vss
270188-5
Figure 4. External Clock Drive
10-105
infef 80C152A/83C152A
IDLE MODE POWER DOWN MODE
In Idle Mode, the CPU puts itself to sleep while most In Power Down Mode, the oscillator is stopped and
of the on-chip peripherals remain active. The major . all on-chip functions cease except that the on-chip
peripherals that do not remain active during Idle, are RAM contents are maintained. The mode Power
the DMA channels. The Idle Mode is invoked by Down is invoked by software.. The Power Down
software. The content of the on-chip RAM and all Mode can be terminated only by a hardware reset.
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.
Table 1. Status of the external pins during Idle and Power Down modes
,
Program
Mode . ALE PSEN PortO Port 1 Port 2 Port 3 Port 4
Memory
Idle Internal 1 1 Data Data Data Data Data
Idle External 1 1 Float Data Address Data Data
Power Down Internal 0 0 Data Data Data Data Data
Power Down External 0 0 Float' Data Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "DeSigning with the 80C51BH."
10-106
intJ 80C152A183C152A
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .......... - 6S·C to + 1S0·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on Any pin to Vss .. - O.SV to (Vee + O.SV)
tional sections of this specification is not implied. Ex-
Voltage on Vee to VSS ........... -O.SVto +6.SV posure to absolute maximum rating conditions for
Power Dissipation ....................... 1.0 W(7) extended periods may affect device reliability.
NOTICE: Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = SV ± 10%; Vss = OV)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 1)
V,L Input Low Voltage -O.S 0. 2Vee- 0.1 V
(All Except EA)
V,L1 Input Low Voltage - -O.S 0.2Vee- 0.3 V
(EA)
V,H Input High Voltage 0.2Vee+ 0.9 Vee+ O.S V
(Except XTAL 1, RST)
V,H1 Input High Voltage 0.7Vee Vee+ O.S V
(XTAL 1, RST)
VOL Output Low Voltage 0.45 V IOL = 1.6 mA
(Ports 1, 2, 3, 4) (Note 2)
VOL1 Output Low Voltage 0.45 V IOL =3.2mA
(Port 0, ALE, PSEN) (Note 2)
VOH Output High Voltage 2.4 V IOH = -60p..A
(Ports 1, 2, 3, 4, Vee = SV ±10%
ALE, PSEN)
0.9Vee • V IOH = -10 p..A
VOH1 Output High Voltage 2.4 V IOH = -400 p..A
(Port 0 in External Vee = SV ±10%
Bus Mode)
0.9Vee V IOH = -40 p..A (Note 3)
I,L Logical 0 Input -so p.A V,N = O.4SV
Current (Ports 1, 2, 3, 4)
ITL Logical 1 to 0 -6S0 p.A V,N = 2V
Transition Current
(Ports 1, 2, 3, 4)
III Input Leakage ±10 p.A O.4S<V,N <Vee
(PortO, EA)
RRST Reset Pullup Resistor 40 k!l
10-107
80C152A/83C152A
NOTES:
1. "Typicals" are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were
made with Vcc = 5V at room temperature.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and S. The noise is due to external bus capacitance discharging into the. Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading >.100 pF), the noise pulse on the ALE pin may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
S. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specifi-
cation when the address bits are stabilizing.
4. Icc is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, ~ = VSS + 0.5V, VIH =
~ - 0.5V; XTAL2 N.C.; Port 0 pins connected tei Vc~'Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vcc and GSC inactive.
5. The specifications relating to external data memory characteristics are also applicable to DMA operations.
6. TOVWX should not be confused with TOVWX as specified for aOC51BH. On aOC152, TOVWX is measured from data
valid to rising edge of WR. On aOC51BH, TOVWX is measured from data valid to falling edge of WR. See timing diagrams.
7. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
. .
MAX Icc (ACTIVE) =(2.24 X FREQ) + 4.16 (Note 4)
MAX Icc (IDLE) = (0.8 X FREQ) + 2.2 (Note 4)
where FREQ is the external oscillator Frequency in Megahertz and Icc is in Milliamps
45
40
35 MAX Icc
30 (ACTIVE) (NOTE 4)
'< 25 /"
.§. TYPICAL Icc
~
20 ./ '" (ACTIVE) (NOTE 1)
/ " ...... ~
--
15 MAX Icc
10 ./' (IDLE) (NOTE 4)
5 ~- TYPICAL Icc
IDLE (NOTE 1)
0
4 8 12
FREQUENCY (MHz)
270188-17
Figure 5. icc vs Frequency
EXPLANATION OF THE AC SYMBOLS
I: Instruction (program memory contents).
Each timing symbol has 5 characters. The first char- L: Logic level LOW, or ALE.
acter is always a 'T' (stands for time). The other P: PSEN.
characters, depending on their positions, stand for Q: Output data.
, the name of a signal or the logical status of that R: READ signal.
signal. The following is a list of all the characters and T: Time.
what they stand for. V: Valid.
W: WRITE signal.
A: Address; X: No longer a valid logic level.
C: Clock Z: Float.
0: Input data.
H: Logic level HIGH. For example,
TAVLL = Time for Address Valid to ALE Low..
TLLPL = Time for ALE Low to PSEN Low.
10-108
intJ 80C152A183C152A
A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Note 5)
12MHz Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12 MHz
TLHLL ALE Pulse Width 126 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 28 TCLCL-55 ns
TLLAX Address Hold After ALE Low 48 TCLCL-35 ns
TLLlV ALE Low to Valid 233 4TCLCL-100 ns
Instruction In
TLLPL ALE Low to PSEN Low 43 TCLCL-40 ns
TPLPH PSEN Pulse Width 205 3TCLCL-45 ns
TPLIV PSEN Low to Valid 145 3TCLCL-105 ns
Instruction In
TPXIX Input Instruction 0 0 ns
Hold After PSEN
TPXIZ Input Instruction 58 TCLCL-25 ns
Float After PSEN
TAVIV Address to Valid 311 5TCLCL-105 ns
Instruction In
TPLAZ PSEN Low to Address 10 10 ns
Float
TALAH AD Pulse Width 400 6TCLCL-100 ns
TWLWH WA Pulse Width 400 6TCLCL-100 ns
TALDV AD Low to Valid 251 5TCLCL-165 ns
Data In
TAHDX Data Hold After AD 0 0 ns
TAHDZ Data Float After AD 96 2TCLCL-70 ns
TLLDV ALE Low to Valid 516 8TCLCL-150 ns
'Data In
TAVDV Address to Valid 585 9TCLCL-165 ns
Data In
TLLWL ALE Low to AD or 200 300 3TCLCL-50 3TCLCL+50 ns
WALow
TAVWL Address to RD or 203 4TCLCL-130 ns
WALow
TOVWX Data Valid to WA 333 6TCLCL-167 ns
(Note 6) Transition
TWHOX Data Hold After WA 33 TCLCL-50 ns
TALAZ AD Low to Address 0 0 ns
Float
TWHLH RD or WR High to 43 123 TCLCL-40 TCLCL+40 ns
ALE High
10-109
inter 80C152A/83C152A
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
rssEN _ _J
PORT 0 _ _..I
PORT 2 ___ ,~ ______ ~~~ _______ n~ ______
AB-A'15 _____
~
270188-6
EXTERNAL DATA MEMORY READ CYCLE
ALE ,
PSEN I-----TLLDV------l.,
- - i - - - TRLRH - - - I
PORTO' INSTR. IN
PORT2 P2.0-P2.7 OR AB-A15 FROt.! DPH A8-A 15 FROt.! PCH
270188-7
10-110
80C152A/83C152A
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
, I \.
P TWHlH
PSEN \. ~
I+-- TlLWL TWlWH
WR ~
TOVWX
,I
-- TAVll ~TLLAX~ - r- TWHOX
PORTO
::::r AO-A7 FROM R. OR DPL )
TAVWl
DATA OUT X XAO-A7 FROM PCl INSTR. IN
'PORT 2
-
~ P2.0-P2.7 OR A8-A15 FROM DPH X A8-A15 FROM PCH
270188-8
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max· Units
1/TClCl Oscillator Frequency 3.5 12 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270188-9
10-111
inter 80C152A183C152A
LOCAL SERIAL CHANNEL TIMING":"SHIFT REGISTER MODE
12MHz Variable Oscillator
Symbol Parameter Units
Min. Max Min Max
TXLXL Serial Port Clock Cycle 1000 12TCLCL ns
Time
TQVXH Output Data Setup to 700 10TCLCL-133 ns
Clock Rising Edge
TXHQX Output Data Hold After 50 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 700 10TCLCL-133 ns
Input Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
ALE
CLOCK
OUTPUT DATA '--_~ '----r' '--_--'X'-__.JX 4 X 5 x...._--IX.... --.;..-J 1
t t
WRITE TO SBur SET TI
INPUT DATA _____ --'~J~--'
t t
CLEAR RI SET RI
270188-10
A.C. TESTING:
INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM
VCC-o.S =X0.2VCC+O.9 )C,
0.2Vcc-O.l
0.4SV ~.....;;;;:..------
270188-11 270188-12
For Timing Purposes a Port Pin is no Longer Floating when a 100
AC Inputs During Testing are Driven at Vee-O.S for a Logic "1"
mV change from Load Voltage Occurs, and Begins to Float when·
and O.4SV for a Logic "0". Timing Measurements are made at VIH
Min for a Logic "1" and Vil Max'for a Logic '~O". a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH ~ ± 20 rnA
10-112
inter 80C152A/83C152A
GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate Generator
,
12 MHz (BAUD = 0) Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
HBTJR Allowable jitter on 0.058 (0.125 x fJ.s
the Receiver for % (BAUD+1)X
bit time (Manchester 8TCLCL)
encoding only) -25 ns
FBTJR Allowable jitter on 0.142 (0.25 x fJ.s
the Receiver for one (BAUD+1)X
full bit time (NRZI 8TCLCL)
and Manchester) -25 ns
HBTJT Jitter of data from ±35 ±35 ns
Transmitterfor %
bit time (Manchester
encoding only)
FBTJT Jitter of c;lata from ±70 ±70 ns
Transmitter for one
full bit time (NRZI
and Manchester)
DRTR Data rise time for 20 20 ns
Receiver (Note 8)
DFTR Data fall time for 20 20 ns
Receiver (Note 9)
NOTES:
8. Same as TCLCH, use External Clock Drive Waveform.
9. Same as TCHCL, use External Clock Drive Waveform.
GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
II BT 'I I
MANCHESTER :::::x: I
I
~i~
:-~
I I I
I
~~-+
I
X ~ I I
I
C::::
I
GRXD
I HBTJR FBTJR I
NRZ1:::::X:
~, I
~
t,1
,~
I
GRxD
FBTJR
270188-13
10-113
intJ 80C152A/83C152A
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
MANCHESTER.
t+'----
I'
*
BT ----~·I
::::l---.. .$~,. . ~'lo...----i--"""jolo"--.J.I~1
I
$ 1......1.....
$ *$
I
I _ _ _ _~HB~T~JT~~~__....I~-~-~FB~T~JT----....I
x::::
I
I
GTxD
NRZI=::J!(_ _ _ _ _ _ _ 4$::,==.~~:==.$r'______. . . x:::: GTxD
FBTJT
270188-14
GLOBAL SERIAL PORT TIMINGS-External Clock
12MHz Variable OSCillator
Symbol Parameter' Unit
Min Max Min Max
1/ECBT GSC Frequency with an 0.009 2.4 0.009 1/5TClCl MHz
External Clock
ECH External Clock High 197 2TClCl ns
+ 30ns
ECl External Clock low 197 2TClCL ns
+ 30ns
ECRT External Clock Rise 20 20 ns
Time (Note 8)
ECFT External Clock Fall 20 20 ns
Time (Note 9)
ECDVT External Clock to Data ns
Valid Out - Transmit 150 150
(to External Clock ,
Negative Edge)
ECDHT External Clock Data ns
Hold - Transmit 0 0
, (to External Clock
Negative Edge)
ECDSR External Clock Data 45 45 ns
Set-up - Receiver
(to External Clock
Positive Edge)
ECDHR External Clock to Data 50 50 ns
Hold - Receiver
(to External Clock
Positive Edge)
10-114
inter SOC152A1S3C152A
GSC TIMINGS (EXTERNAL CLOCK)
t+·----ECBT----~·1
-----x
1 1
EXTERNAL CLOCK f. 'X I
t---ECL-----::--- ECH ----.: 1
_ _...;...1 ~ : - ECDVT
TRANSMIT DATA : X :x:r--.;;..;..;.------.;....,;.-.-
ECDHT ~ :+
141· - - - - E C B T 'I
1 1 1
EXTERNAL CLOCK -----X""I_ _ _ _ Ji:,-----X I~---"""''----
1 --' ECDSR '-ECDHR--' '--_ _ _..J
_ _"""1"'_ _ ' ,
RECEIVE DATA
_ _....._....J,X Xr...,..---------.....;i---
, _ " -_ _ _ _ _ _ _ _ _......_ _
270188-15
10-115
80C152A/83C152A
NOTES ON THE OPERATION OF THE 2. SDLe Flags While Idling
80C152A In SDLC Mode, the GSC can be programmed to
transmit SDLC flags between transmission
1. Current in Power Down Mode frames. This is done by setting the GFIEN bit in
Typically, Icc in Power Down Mode is about PCON. When the GSC is so programmed, the
·10 ""A. However, you may note under certain con- DEN signal is asserted only during the actual
ditions an abnormally high Icc, about 600 ""A, in transmission frame, not during the idle fill flags. In
Power Down. This is caused by an interaction be- this case the DEN signal will normally not be used
tween internal signals local to the interrupt control to enable the line driver, but is available for use as
system. The problem disappears once an inter- a positive indication that a transmission frame is
rupt, any interrupt, is requested and serviced. in progress.
Therefore, if Icc in Power Down is critical to the 3. Immediate Deactivation of DEN in CSMAlCD
application, it is suggested that an interrupt be Mode
generated and exercised before Power Down is CSMAlCD protocols typically require two bit-
invoked. times .of inactivity in the line to indicate an idle
condition. Note, however, that the 80C152A deac-
. tivates DEN immediately at the end of the trans-
mission frame.
10-116
83C 152JA/83C 152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY MASKED
PROGRAMMABLE ROM
80C152JA/80C152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
80C152JB/80C152JB-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH EXTENDED 1/0
• Superset of 80C51 Architecture • 64KB Data Memory Addressing
• Multi-Protocol Serial Communication • 256 Bytes On-Chip RAM
I/O Port (2.048 Mbps/2.4 Mbps Max)
• Dual On-Chip DMA Channels
-SDLC
-HDLC • Hold/Hold Acknowledge
-CSMAlCD • Two General Purpose Timer/Counters
- User Definable Protocols
• 56 Special Function Registers
• Full Duplex/Half Duplex
• 11 Interrupt Sources
• MCS®-51 Compatible UART
• Available in 48 Pin Dual-in-Line Package
• 16.5 MHz Maximum Clock Frequency and 68 Pin Surface Mount PLCC
• Multiple Power Conservation Modes Package
(See Packaging Spec. Order #231369)
• 64KB Program Memory Addressing
The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single·chip 8·bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applica-
tions. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-
serial and serial-to-parallel ~onverters. The 83C152 contains, in silicon, all the features needed for the serial-
to-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modulari-
ty of hardware and software designs. All of these-cost, network parameter and real estate improvements-
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
September 1987
10-117 Order Number: 270431-001
inter 80C152JAl83C152JA/80C152JB ~[Q)W~OO©[§ OOOIP@OOINl~"iiO@OO
(GRXO)
(GTOX)
vee
P4.0
INDEX
CORNER'\,.
. . . 2 ~ i ;~~ 4
Ill;; "l q <i
z z z ~ : i. :. i
N .,
(DEN) P4.1
Pl.6 P"',5
(TXC) P4.2
Pl.7 P4.6
(RxC) P1.4 P4.3
N.C. P4.7
(HLO) P1.S P4.4
N.C.
(HLOA) P1.6 P4.5
P3.0 EA
Pl.7 P4.6
P3.1 ALE
RESET P4.7 (TOP VIEW)
P3.2 PSEN
(RXO) P3.0 EA N.C. N.C.
(TXO) P3.1 ALE P3.3 8DC1S2JA N.C.
83C152JA
(INTO) P3.2 PSEN P3.4 N.C.
(iNTi) P3.3 P2.7 (A1S) N.C. N.C.
(TO) P3.4 P2.6 (AI4) N.C. N.C.
(Tl) P3.S P2.S (AI3) N.C. P2.7
(i¥R) P3.S P2.4 (AI2) P3.5 P2.6
(Rii) P3.7 P2.3 (All) PM P2.5
(A/DO) PO.O P2.2 (Al0) P3.7 P2.4
(A/Ol) PO.l
(A/02) PO.2
P2.1 (A9)
P2.0 (A8)
N.C.
...
N ~ gJ iil ;; N . . Pi m
., .,., ., .," ., ~ ~ :; ~ ~
P2.3
(A/03) PO.3
XTAL2
PO.7 (A/07)
PO.S (A/OS) g~ --;" ~
f
'1 ~ ::;
~ ~~
. ~~~
"!
~ ~
<iz
~ ~
OJ
~
XTALl PO.S (A/OS)
~ S
V,s PO.4 (A/04) 270431-2
270431-1
P4.5
P4.S
P4.1
P6.3
EA
P3.1 ALE
P3.2 PSEN
PS.O (TOP VIEW) EPSEN
P3.3 P6.2
P3.4 8~152JB PS.7
P5.1 P6.4
P5.2 P5.7·
PS.3 P2.7
P3.5 P2.6
P3,6 P2.5
P3.7 P2.4
.,.
N.C. P2.3
::. re ~ iil ;;; ~ ~ ;:\ ~ i;; :ll III ~ :;; ~ ~
~ ~
OJ
~ ~
~
~ ~
::; ~"<oI;
> ~ ....
"~ ~ d ~ ~ "! C!
~ .~ ~
OJ
~
270431-3
Figure 1. Connection Diagrams
10·118
·P6.0-P6.7 P4.0-P4.7 PO.O-PO.7 P2.0-P2.7
-----11 t
SARL1
SARHI
OARL1
OARHI
CI)
BCRL1
o
....CJI
(")
~
l>
......
CI)
." Co)
iD: ....CJI
(")
...CD
c
'?
!'l
UJ
1.£1 N
Co.
l>
......
em
..... 0'
~ I"~
CI)
n
;I;' THO o
CO
C ....(")CJI
~
TLI
iii"
...
ce
DI
·EBEN
,
THI
~
3 a:J
~
~
l§!
~
;:;g
©
IiiiiI
~
'liil
ADRD-3
©
2&
~
BAUD
_-.J ~
~
Pl.0- P1.7 P3.0-P3.7 270431-4 <=
'On 80C152JB Only ©
~
intJ 80C152JAl83C152JA/80C152JB ~@w~oo©~ DOOIP©OOIMl~'jj'D©OO
80C152JB General Description EPSEN is used in conjunction with Port 5 and Port 6
program memory operations. EPSEN functions like
The 80C152JB is a ROM less extension of the PSEN during program memory operation, but sup-
aOC152 Universal Communication controller. The ports Port 5 and Port 6. EPSEN is the read strobe to
80C152JB has the same five 8-bit I/O ports of the externai program memory for Port 5 and Port 6.
80C152, plus an additional two 8-bit 1/0 ports, Port 5 EPSEN is activated twice during each machine cycle
, and Port 6. The 80C152JB also has two additional unless an external data memory operation occurs on
control pins, EBEN (EPROM Bus ENable), and Port(s) 0 and Port 2. When external data memory is
EPSEN (EPROM bus Program Store ENable). accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
EBEN selects the functionality of Port 5 and Port 6. Note that data memory fetches cannot be' made
When EBEN is low, these ports are strictly I/O, simi- through Ports 5 and 6.
lar to Port 4. The SFR location for Port 5 is 91 Hand
Port 6 is OA 1H. This means Port 5 and Port 6 are not When EBEN is high and EA is low, all program mem-
bit addressable. With EBEN low, all program memo- ory operations take place via Ports 5 and 6. The high
rY fetches take place via Port 0 and Port 2. (The byte of the address goes out on Port 6, and the low
80C152 is a ROMless only product). When EBEN is byte is output on Port 5. ALE is still used to latch the
high, Port 5 and Port 6 form an address/data bus address on Port 5. Next, the op code is read on Port
called the E-Bus (EPROM-Bus) for program memory 5. The timing is the same as when using Ports 0 and
operations. ' 2 for external program memory operations.
Table 1. Program Memory Fetches
Program
EBEN EA PSEN EPSEN Comments
Fetch via
0 0 PO,P2 Active Inactive Addresses O-OFFFFH
0 1 N/A N/A N/A Invalid Combination
1 0 P5,P6 Inactive Active Addresses O-OFFFFH
1 1 P5,P6 Inactive Active Addresses 0-1 FFFH
PO,P2 Active Inactive Addresses :?: 2000H
10-120
inter SOC 152JAlS3C 152JAlSOC152JB ~@W~OO©[§ OOO[F@OOIM]~'iiO@OO
Pin # Pin Description
DIP PLCC(1)
48 2 Vee-Supply voltage.
24 3,33(2) Vss-Circuit ground.
18-21, 27-30, Port O-:-Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin
25-28 34-37 can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed
data bus. In these applications it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification~
1-8 4-11 Port 1-Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pull ups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Pin Name Alternate Function
P1.0 GRXD GSC data input pin
P1.1 GTXD GSC data output pin
P1.2 DEN GSC enable signal for an external driver
P1.3 TXC GSC input pin for external transmit clock
P1,4 RXC GSC input pin for external receive clock
P1.5 HLD DMA hold input/ output
P1.6 HLDA DMA hold acknowledge input/output
29-36 41-48 Port 2-Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that
have 1 s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 2. pins that are externally being pulled low will source.
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low. During accesses to external Data Memory that use 16-
bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
10-17 14-16, Port 3-Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that
18,19, have 1s written to them are pulled high by the internal pull ups, and in that state can be
23-25 used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin Name Alternate Function
P3.0 RXD Serial input line
.. P3.1
P3.2
TXD
INTO
Serial output line
External Interrupt 0 .
P3.3 INT1 External Interrupt 1
P3,4 TO Timer 0 external input
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe
P3.7 RD External Data Memory Read strobe
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-121
inter 80C152JAl83C152JA/80C 152JB ~1ID\Yl~OO©[§ OOO!F©OO!MI~ii"O©OO
Pin Description (Continued)
Pin # Pin Description
47-40 65-58 Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (Ill, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.
9 13 RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.
38 55 ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.
37 54 PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
39 56 EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.
23 32 XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.
22 31 XTAL2-0utput from the inverting oscillator amplifier.
N/A 17,20 Port 5-Port 5 is an 8-bit bidirectional 1/0 port with internal pullups. Port 5 pins that
21,22 have 1s written to them are pulled high by the internal pullups, and in that state can
38,39 be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
40,49 source current (Ill, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pull ups when emitting 1s.
N/A 67,66 Port 6-Port 6 is an 8-bit bidirectional 1/0 port with internal pullups. Port 6 pins that
52,57 have 1s written to them are pulled high by the internal pullups, and in that state can
50,68 be used as inputs. As inputs, Port 6 pins that are externally pulled low will source
1,51 current (Ill, on the data sheet) because of the internal pullups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pull ups when
emitting 1s.
N/A 12 EBEN-E-Bus Enable input that designates whether program memory fetches take
, place via Ports O.and 2 or Ports 5 and 6. Table 1 shows how the ports are used-in
conjunction with EBEN.
53 EPSEN-E-bus Pr9gram Store Enable is the Read strobe to external program__
memory when EBEN is high. Table 2,shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA.
10-122
80C152JA/83C152JA/80C152JB ~(Q)W~OO©~ OOOIF@OOIMl~liO@OO
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respec-
NC - XTAL2
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in EXTERNAL
Figure 3. OSCILLATOR - - - - I XTAL 1
SIGNAL
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left uncon- ~L.v_s_s__
nected, as shown in Figure 4. There are no require-
ments on the duty cycle of the external clock signal, 270431-6
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and Figure 4. External Clock Drive
maximum high and low times specified on the Data
Sheet must be observed.
IDLE MODE
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
XTAL2 peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
XTAL 1 software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
+-------1 vss by any enabled interrupt or by a hardware reset.
270431-5
POWER DOWN MODE
Figure 3. Using the On-Chip Oscillator
In Power Down Mode, the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software. The Power Down
Mode can be terminated only by a hardware reset.
Table 2. Status of the External Pins During Idle and Power Down Modes
80C152JAl83C152JA
Program
Mode ALE PSEN Porta Port 1 Port 2 Port 3 Port 4
Memory
Idle Internal 1 1 Data Data Data Data Data
Idle External 1 1 Float Data Address Data Data
Power Down Internal 0 0 Data Data Data Data Data
Power Down External 0 0 Float Data Data Data Data
80C152JB
Instruction
Mode ALE PSEN EPSEN Porta Port 1 Port 2 Port 3 Port 4 Port 5 Port 6
Bus
Idle PO,P2 1 1 1 Float Data Address Data Data OFFH OFFH
Idle P5,P6 1 1 1 Data Data Data Data Data OFFH Address
Power Down PO,P2 0 0 1 Float Data Data Data Data OFFH OFFH
Power Down P5,P6 0 1 0 Data Data Data Data Data OFFH OFFH
NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "Designing with the 80C51BH."
10-123
intJ 80C152JA/83C152JA/80C152JB ~@W~OO©[§ OOO!P@!ru!Ml~iiO@OO
ABSOLUTE MAXIMUM RATINGS* *Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias .... O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .......... - 65·C to + 150·C functional operation of the device at these or any
.other conditions above those indicated in the opera-
Voltage on Any pin to Vss .. -0.5\.1 to (Vee + 0.5V)
tional sections of this specification is not implied. Ex-
Voltage on Vee to VSS ........... -0.5V to + 6.5V posure io absolute maximum rating conditions for
Power Dissipation ....................... 1.0W(9) extended periods may affect device reliability.
NOTICE' Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS (TA = O·Cto +70·C;Vee = 5V ±10%;Vss = OV)
Typ
Symbol Parameter Min Max Unit Test Conditions
(Note 3)
Vil Input Low Voltage -0.5 0.2Vec- 0.1 V
(All E~cept EA, EBEN)
VIl1 Input LowVoltage -0.5 0.2Vee- 0.3 V
(EA, EBEN)
VII-i Input High Voltage· 0.2Vee+ 0.9 Vee+ 0.5 V
(Except XTAL 1, RST)
VIH1 Input High Voltage 0.7Vee Vee+ 0.5. V
(XTAL1, RST) ,
VOL Output Low Voltage 0.45 V IOl = 1.6 mA
(Ports 1, 2, 3, 4, 5, 6) (Note 4)
Vou Output Low Voltage 0.45 V IOl = 3.2mA
(Port 0, ALE, PSEN, EPSEN) (Note 4)
VOH Output High Voltage 2.4 V IOH = -60p..A
(Ports 1, 2, 3, 4, 5, 6 COMM9 Vee = 5V ±to%
ALE, PSEN, EPSEN)
0.9Vee V IOH = -10'p..A
VOH1 Output High Voltage 2.4 V IOH = -400;UA
(Port 0 in External Vee = 5V ±10% .
Bus Mode)
0.9Vee, V IOH = - 40 p..A (Note 5)
III Logical 0 Input ·-50 p..A VIN = O.4SV
Current (Ports 1, 2, 3, 4, 5, 6)
ITl Logiqal 1 to 0 -650 p..A VIN = 2V
Transition Current
(Poits 1, 2, 3, 4, 5, 6)
..
III Input Leakage ±10 p..A 0.45 <VIN <Vee
(portO, EA)
RRST Reset Pullup Resistor 40 kfl.
IIH Logical 1 Input Current (EBEN) +60 p..A
Icc Power Supply Current:
Active (i 6.5 MHz) 31 .41.1 rnA (Note 6)
Idle (16.5 MHz) 8 15.4 mA (Note 6)
Power Down Mode 10 p..A Vee = 2.0V to 5.5V
10-124
80C152JAl83C152JAl80C152JB &,[gJW&,OO©[§ OOOlf@ffiJ[MJ&''ii'O@OO
NOTES:
3. "Typicals" are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were
made with Vee = 5V at room temperature.
4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vee specifi-
cation when the address bits are stabilizing.
6. lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, V,L = Vss + 0.5V, V,H =
Vee - 0.5V; XTAL2 N.C.; Port 0 pins connected to Vee. "Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vee and GSC inactive.
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.
B. TQVWX should not be confused with TQVWX as specified for BOC51BH. On BOC152, TQVWX is measured from data
valid to rising edge of WR. On BOC51 BH, TQVWX is measured from data valid to falling edge of WR. See timing diagrams.
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10. All specifications relating to external program memory characteristics are applicable to:
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the BOC152JB.
MAX Icc (ACTIVE) = (2_24 X FREQ) + 4_16 (Note 6)
MAX Icc (IDLE) = (0_8 X FREQ) + 2.2 (Note 6)
45
MAX Icc (ACTIVE)
40
35 /'
'/
30 TYPICAL Icc
~ /'" /"" (ACTIVE) (NOTE 1)
--
25
5u 20
.... v /'"
2
15 /'" V MAX Icc (IDLE)
10
_/ /" ....-
- :::---
...-::: TYPICAL Icc
5 IDLE (NOTE 1)
0
4 8 12 16
FREQUENCY (MHz)
270431-7
Figure 5. Icc vs Frequency
I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
EXPLANATION OF THE AC SYMBOLS P: PSEN.
Q: Output data.
Each timing symbol has 5 characters. The first char- R: READ signal.
acter is always a 'T' (stands for time). The other T: Time.
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status of that W: WRITE signal.
signal. The following is a list of all the characters and X: No longer a valid logic level.
what they stand for. Z: Float.
A: Address. For example,
C: Clock
D: Input data. TAVLL = Time for Address Valid to ALE Low.
H: Logic level HIGH. TLLPL = Time for ALE Low to PSEN Low.
10-125
SOC152JA/S3C 152JAlSOC152JB ~[Q)W~OO©[§ OOO~@OOIMl~iiO@OO
A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Lqad Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION: SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Note 7,10)
Symbol 16.5 MHz . Variable Oscillator
Parameter Unit
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12 MHz
80C152JA
83C152JA
80C152JB
80C152JA-1 3.5 16.5 MHz
83C152JA·1
80C152JB-1
TLHLL ALE Pulse Width 81 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 5 TCLCL-55 ns
TLLAX Address Hold After ALE Low 25 TCLCL-35 ns
TLLlV ALE Low to Valid 142 4TCLCL-100 ns
Instruction In
TLLPL ALE Low to PSEN Low 20' TCLCL-40 ns
TPLPH PSEN Pulse Width 137 3TCLCL-45 ns
TPLIV PSEN Low to Valid 77 3TCLCL-105 ns
Instruction In
TPXIX Input Instruction 0 0 ns
Hold After PSEN
TPXIZ Input Instruction 35 TCLCL-25 ns
Float After PSEN ,
TAVIV Address to Valid 198 5TCLCL-105 ns
Instruction In
TPLAZ PSEN Low to Address 10 10 ns
Float
TRLRH RD Pulse Width 263 6TCLCL-100 ns
TWLWH WR Pulse Width 263 6TCLCL-100 - ns
TRLDV RD Low to Valid 138 5TCLCL-165 ns
Data In
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 51 2TCLCL-70 ns
TLLDV ALE Low to Valid 335 8TCLCL-150 ns
Data In
TAVDV Address to Valid 380 9TCLCL-165 ns
Data In
TLLWL ALE Low to RD or 132 232 3TCLCL-50 3TCLCL+50 ns
WRLow
TAVWL Address to RD or 112 4TCLCL-130 ns
WRLow
TQVWX(8) Data Valid to WR 196 6TCLCL-167 ns
Transition
TWHQX Data Hold After WR 10 TCLCL-50 ns
TRLAZ RD Low to Address o ' 0 ns
Float
TWHLH RD or WR High to 20 100 TCLCL-40 TCLCL+40 ns
ALE High
10-126
inter 80C152JAl83C152JAl80C152JB ~[Q)WbW~'J©[g O~IP@rnl[i'li]~iJO@~
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _oJ
PORT O/PORT 5
----'
PORT 2/PORT 6 AB-A15
----'
270431-8
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN I-----TLLDV-----I'I
TRLRH ---I
RD
PORTO INSTR. IN
PORT2 P2.0-P2.7 OR A8-A 15 FROM DPH A8-A 15 FROM PCH
270431-9
10-127
infef 80C152JA/83C152JA/80C1 ~2JB ~[Q)\Yl~OO©~. oOO!r@OO[MJ~'U'O@OO
EXTERNAL DATA MEMORY WRITE CYCLE
ALE I \.
i=4- TWHLH
PSEN \.
,
-TLLWL TWLWH
-'
WR 1
TQVWX J
-. TAVLL I-- TLLAX---j -. r- TWHQX
PORTO
::::r AO-A7 FROM R, OR DPL )
TAVWL
DATA OUT X X AO- A7 FROM PCL INSTR. IN
PORT2
=> P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
270431-10
'EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TClCL Oscillator Frequency 3.5 16.5 MHz
TCHCX High Time 20 ns
TClCX low Time 20 ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270431-11
10-128
inter SOC 152JA/S3C152JA/SOC152JB ~[Q)W~OO©~ OOOIF@OOIMl~'ifO@OO
LOCAL SERIAL CHANNEL TIMING-SHIFT REGISTER MODE
16.5 MHz Variable OSCillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle 727 12TCLCL ns
Time
TOVXH Output Data Setup to 473 10TCLCL-133 ns
Clock Rising Edge
TXHOX Output Data Hold After 4 2TCLCL-117 ns
Clock Rising Edge
TXHDX Input Data Hold After 0 0 ns
Clock Rising Edge
TXHDV Clock Rising Edge to 473 10TCLCL-133 ns
Input Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I 7
ALE
CLOCK
r- TQVXH~ r- TXHQX
OUTPUT OATA
'''---'''''---r' '-----rJ "---""'--..JX'-_---JX 4 X'-_---JX"---_-'x"---""'--..JI
t t
WRITE TO SSUF SET TI
INPUT OATA _ _ _ _ _...J'\;;;;;J',_,,'I;.;.;.:;;;"-.....J'=~'--..J'.;;.;:;;,\,_I'I;..=''_.....J'I;...;;J'I_J,;.;.;;;;;;(,,_,'I;...;;;;J''
t t
CLEAR RI SET RI
270431-12
A.C. TESTING:
INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM
vce-O.s===>(
0,45 V
0.2Vcc+0.9
_;..0_.2_V.,;;CC;,.-_0_.1_ _ __
L
270431-13 270431-14
For Timing Purposes a Port Pin is no Longer Floating when a
AC Inputs During Testing are Driven at Vcc-O,5 for a Logic "1"
100 mV change from Load Voltage Occurs, and Begins to Float
and 0.45V for a Logic "0", Timing Measurements are made at VIH
when a 100 mV change from the Loaded VOHIVOL Level occurs
Min for a LogiC "1" and VIL Max for a Logic "0",
IOLIiOH ;, ± 20 rnA.
10-129
intJ 80C152JA/83C152JA/80C152JB ~[Q)W~OO©~ OOOIF@OOIMl~ii"O@OO
GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate ,Generator
16.5 MHz (BAUD = 0) Variable Oscillator
Unit
Symbol Parameter
Min Max IIIlIn Max
HBTJR Allowable jitter on 0.0375 ,(0.125 x ,.,.s
the Receiver for % (BAUD+1)X
bit time (Manchester 8TCLCL)
encoding only) --:25,ns
FBTJR Allowable jitter on 0.10 (0.25 x ,.,.s
the Receiver for one (BAUD+1)X
full bit time (NRZI 8TCLCL)
and Manchester) -25 ns
HBTJT Jitter of data from ±35 ±35 ns
Transmitter for %
bit time (Manchester
encoding only)
FBTJT Jitter of data from ±70 ±.70 ns
Transmitter for one
full bit time (NRZI
and Manchester)
DRTR Data rise time for 20 20 ns
Receiver(11 )
DFTR Data fall time for 20 20 ns
Receiver!1'2)
~OTES:
'11. Same as TCLCH, use External Clock Drive Waveform.
12. Same as TCHCL, use External Clock Drive Waveform.
GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
II BT 'I
c::::
1 1
MANCHESTER =::J(
1
~X~ ~I
I......
~I~;'-------'I
X.' ~ 1
GRxD
1 HBTJR' 1 FBTJR 'I
NRzr=:::X
~ I ~
)K
'I' I
~ : GRxD
FBTJR
270431-15
10-130
intJ SOC152JAlS3C152JAlSOC152JB ~[Q)\\7~OO©~ OOOI?@OOIMl~ii'O@OO
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
~I'--------BT--------~'I I
MANCHESTER =::x I
I
? X, ? ? X,..-~?r--x:::: GTxD
'----"""Tl~..,,_"':'+~"'------''--''''~~,'---'I :~~ I
I
I_----H-B-TJ-T-~-~I~-~--F-BT-JT---~I
NRZ1=::X ~. ~ .~ ~ GTxD
ai'
FBTJT
270431-16
GLOBAL SERIAL PORT TIMINGS-External Clock
16.5 MHz . Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
1/ECBT GSC Frequency with an 0.009 2.4 0.009 Fosc x 0.145 MHz
External Clock
ECH External Clock High 15.5 2TClCl ns
+ 30ns
ECl External Clock low 155 2TClCl ns
+ 30 ns
ECRT External Clock Rise 20 20 ns
Time(11)
ECFT External Clock Fall 20 20 ns
Time(12)
ECDVT External Clock to Data ns
Valid Out - Transmit 150 150
(to External Clock
Negative Edge)
ECDHT External Clock Data ns
Hold - Transmit 0 0
(to External Clock
Negative Edge)
ECDSR External Clock Data 45 45 ns
Set-up - Receiver
(to External Clock
Positive Edge)
ECDHR External Clock to Data 50 50 ns
Hold - Receiver
(to External Clock
Positive Edge)
10-131
intJ 80C152JA/83C152JA/80C152JB ~IQ)\YI~OO©[§ OOOIr@OO[M)~'iiO@OO
GSC TIMINGS (EXTERNAL CLOCK)
f4"I'----ECBT ------+1'1
----x
1 1
EXTERNAL CLOCK
~ECL----:
1. 'X
: - - - ECH - . : "'I_ _ _--J
/
_ _....;...1 :-- ECDVT
:X,.-.;;...;.------...;....--
-+j
TRANSMIT DATA : X
ECDHT -+t ;....~--------....- -
f4"I'----ECBT------+t·1
EXTERNAL CLOCK ----x'--___J/:,-----..,.
1
1
1
I~______ J
1
/,-----.. .X
~
1 - : ECDSR '--ECDHR-: 1
RECEIVE DATA -~'''':--X Xr -;---......------..:.:.--
, ,~~--------~~--
270431-17
10-132 .
inter 27C64/S7C64
64K (SK x S) CHMOS PRODUCTION AND
UV ERASABLE PROMS
• CHMOS Microcontroller and • High Performance Speeds
Microprocessor Compatible - 150 ns Maximum Access Time
- 87C64-lntegrated Address Latch
• New Quick-Pulse Programming™
- Universal 28 Pin Memory Site, 2-line Algorithm (1 second programming)
Control
• Available in 28-Pin Cerdip and Plastic
• Low Power Consumption DIP Package and 32-Lead PLCC
-100}J-A Maximum Standby Current Package.
• Noise Immunity Features (See Packaging Spec, Order #231369)
- ± 10% Vee Tolerance
- Maximum Latch-up Immunity
Through EPI Processing
Intel's 27C64 and 87C64 CHMOS EPROMs are 64K bit 5V only memories organized as 8192 words of 8 bits.
They employ advanced CHMOS*II-E circuitry for systems requiring low power, high performance speeds, and
immunity to noise. The 87C64 has been optimized for multiplexed bus microcontroller and microprocessor
compatibility while the 27C64 has a non-multiplexed addressing interface and is plug compatible with the
standard Intel 2764A (HMOS II-E).
The 27C64 and 87C64 are offered in both a ceramic DIP, Plastic DIP, and Plastic Leaded Chip Carrier (PLCC)
Packages. Cerdip packages provide flexibility in prototyping and R&D environments; whereas Plastic DIP and
PLCC EPROMs provide optimum cost effectiveness in production environments. A new Quick-Pulse Program-
mingTM Algorithm is employed which can speed up programming by as much as one hundred times.
The 87C64 incorporates an address latch on the address pins to minimize chip count in multiplexed bus
systems. Designers can eliminate an external address latch by tieing address and data pins of the 87C64
directy to the processor's multiplexed address/data pins. On the falling edge of the ALE input (ALE/CE),
address information at the address inputs (Ao-A12) of the 87C64 is latched internally. The address inputs are
then ignored as data information is passed on th~ same bus.
The highest degree of protection against latch·up is achieved through Intel's unique EPI processing. Preven-
tion of latch-up is provided for stresses up to 100 mAon address and data pins from -1V to Vcc + 1V.
'liMOS and CHMOS are patented processes of Intel Corporation.
DATA OUTPUTS
0 0-07
OUTPUT ENABLE
PROG LOGIC
OUTPUT BUffERS.
Y-GATING
65,536 BIT
CELL MATRIX
290000-1
Shaded 'Areas' i> .:::';,:;:::represent the 87C64 version
Figure 1. Block Diagram
October 1987
10-133 Order Number: 290000-007
27C64/87C64
27C64/87C64
P27C64/P87C64
27256 27128 2732A 2716 2716 2732A 27128 27256
Vpp Vpp Vee Vee Vee
A'2 A'2 PCM J5GlVl A'4
A7 A7 A7 A7 N.C. Vee Vee A,s A,s
A6
As
A6
As
A6
As
A6
As ..'. As
As
As
As
As
As
As
As
A4 A4
c.._
A4 A4 A" Vpp All All All
AS As AS Aa at' DE DENpp DE DE
A2 A2 A2 A2 A,. A,o A,o A,o A,o
A, A, A, A, ~ ~ ~ ~,
An An AD AD ~ 07 07 ~
00 00 00 00 06 Os Os 06
0, 0, 0, 0, Os Os Os Os
02 02 02 ~ 04 04 04 04
Gnd Gnd Gnd Gnd Os Os . Os Oa
290000-2
NOTE:
Intel "Universal Site" Compatible EPROM Pin Confi~urations are shown in the adjacent blocks to 27C64 Pins,
Shaded Areas 1u!!L~represenllhe 87C64 version
Figure 2. Pin Configuration
A6 0 AS
A' AI
U All
A~ 32 PIN PLCC Ne
A2
0.450" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)
A,
TOP VIEW
AD
Ne
00
290000-11
Figure 3. PLCC(N) Lead Configuration
10-134
27C64/87C64
Extended Temperature (Express) EXPRESS EPROM Product Family
EPROMs
PRODUCT DEFINITIONS
The Intel EXPRESS EPROM family is a series of Type Operating Burn-in 125°C (hr)
electrically programmable read only memories which Temperature eC)
have received additional processing to enhance a Oto +70 168 ±8
product characteristics. EXPRESS processing is T -40 to +85 NONE
available for several densities of EPROM, allowing L -40 to +85 168 ±8
the choice of appropriate memory size to match sys-
A -40 to + 125 NONE
tem applications.
B -40 to + 125 168 ±8
EXPRESS EPROM products are available with 168
± 8 hour, 125°C dynamic burn-in using Intel's stan-
dard bias configuration. This process exceeds or EXPRESS Options
meets most industry specifications of burn-in. The 27C64/87C64 Versions
standard EXPRESS EPROM operating temperature Packaging Options
range is O°C to 70°C. Extended operating tempera-
Speed Cerdip PLCC Plastic
ture range (- 40°C to + 85°C) EXPRESS products Versions DIP
are available along with automotive temperature -1 T,L,a T T
range (- 40°C to + 125°C) products. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected -15 T, L,a T T
to 0.1 % electrical AaL. This may allow the user to -2 T,L,a,A,B T,A T,A
reduce or eliminate incoming inspection testing. -20 T,L,a,A· T T
-STD T, L,a,A, B T,A T,A
-25 T,L,a,A T T
-3 T,L,a,A,B T,A T,A
-30 T,L,a,A T T
READ OPERATION
D.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for:
27C64
Symbol Parameter 87C64 Test Conditions
Min Max
ISB Vee Standby Current (mA) CMOS 0.1 CE = Vee,OE = VIL
TTL 1.0 CE = VIH, OE = VIL
lee1(1) Vee Active Current (mA) TIL 20,30 OE = CE = VIL
Vee Active Current at TIL 20,30 OE = CE = VIL
High Temperature Vpp = Vee, Tambient = 85°C
NOTE:
1. See notes 4 and 6 of Read Operation D.C. Characteristics.
30~s
H
AOruLJ
:'rLS
Vee A'2
290000-14
°00, Binary Sequence from Ao to A12
°2
290000-13
DE = +sv = 1 Kfl
R vee = +sv
vpp = +sv GND = OV CE = 33.3 KHz
PGM = +sv
Burn·ln Bias and Timing Diagrams
10-135
intJ 27C64/87C64
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under ':Abso-
Operating Temperature _ lute Maximum Ratings" may cause permanent dam-
During Read ............. ~ .... O°C to + 70°C(2) age to the device. This is a stress rating only and
functional operation of the device at these or any
Temperature Under Bias ......... -lO°C to + 80·C
other conditions above those indicated in the opera-
Storage Temperature .......... - 65°C to + 150·C tional sections of this specification is not implied Ex-
Voltage on Any Pin with posure to absolute maximum rating conditions for
Respect to Ground .............. - 2~OV to 7V(1) extended periods may affect device reliability. -
Voltage on Pin Ag with
Respect to Ground ......... -2.0V to + 13.5V(1)
Vpp Supply Voltage with Respect to Ground
During Programming ......... - 2.0V to + 14V(1)
Vcc Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.OV(1)
READ OPERATION D.C. CHARACTERISTICS O°C s TA S + 70°C
Symbol Parameter Notes Min Typ(3) Max Unit Test Condition
III Input Leakage Current 0.01 1.0 ,."A VIN = OV to 5.5V
ILO Output Leakage Current ±10 ,."A VOUT = OV to 5.5V
IpP1 Vpp Current Read 6 100 ,."A Vpp = Vcc
ISB Vcc Current Standby ICMOS 5 100 ,."A CE = Vcc
with Inputs- ITTL 4 1.0 mA CE = VIH
ICC1 Vcc Current Active 4,6 20,30 mA CE = VIL
f = 5 MHz, lOUT = 0 mA
VIL Input Low Voltage (± 10% Supply) -0.5 0.8
(TTL)
V Vpp = Vcc
Input Low Voltage -0.2 0.2
(CMOS)
VIH Input High Voltage(± 10% Supply) 2.0 Vcc+ 0.5
(TTL)
V Vpp = Vcc
Input High Voltage Vcc- 0.2 Vcc+ 0.2
(CMOS)
VOL Output LOw Voltage 0.45 V 10L =2.1 mA
VOH Output High Voltage 3.5 V 10H= -2.5mA
los Output Short Circuit Current 7 100 mA
Vpp Vpp Read Voltage 8 Vcc- 0.7 _ Vce V
,
NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions. 5. ALE ICE or CE is Vee ± 0.2V. All other inputs can have
the inputs may undershoot to - 2.0V for periods less than any value within spec.
20 ns. Maximum D.C. Voltage on output pins is 6. Maximum Active power usage is the sum Ipp + Icc. The
Vce + 0.5V which may overshoot to Vee + 2V for periods maximum current value is with Outputs 00 to 07 unloaded.
less than 20 ns. 7. Output shorted _for no more than one second. No- more
2. Operating temperature is for commercial product defined- than one output shorted at a time. los is sampled but not
by this specification. Extended temperature options are 100% tested.
available in EXPRESS and Military version. 8. Vpp may be one diode voltage drop below Vee. It may
S. Typical limits are at Vee = 5V; TA = + 25°C. be connected directly to Vee.
4. 20 mA forSTD and -3 versions; 30 mA for -2 and
150 ns version-!!.
VIL. VIH levels at TTL inputs.
10-136
intJ 27C64/87C64
READ OPERATION
A.C. CHARACTERISTICS 27C64(1) O·G ~ TA ~ + 70·G
27C64-1 27C64-2
27C64 27C64-3
Vee ±5% N27C64-1 N27C64-2
N27C64 N27C64-3
P27C64-1 P27C64-2
Versions (3)
27C64-15 27C64-20 Unit
Vee ±10% 27C64-25 27C64-30
N27C64-15 N27C64-20
N27C64-25 N27C64·30
P27C64-15 P27C64-20
Symbol Characteristic Min Max Min Max Min Max Min Max
tACC Address to Output Delay 150 200 250 300 ns
tCE CE to Output Delay 150 200 250 300 ns
tOE OE to Output Delay 75 75 100 120 ns
tDF(2) OE High to Output High Z 35 55 60 105 ns
tOH(2) Output Hold from Addresses, CE 0 0 0 0 ns
or OE Change·Whichever is First
NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.SV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.
A.C. WAVEFORMS 27C64
V,H-----"\
ADDRess
ADDRESSES VALID.
VIL _ _ _ _ _J
V,H -------+-,.
_--ICEI31~
V,H -------+----""
~-----t.cc-------<·I
OUTPUT _ _ _ _ _~H;,;;IG;,;;H;,;;Z_ _ _ _ _+H++< HIGHZ
290000-5
NOTES:
1. Typical values are for T A = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.
10-137
27C64/87C64
A.C. CHARACTERISTICS 1II«llo·c:5: T A :5: + 70·C
87C64-1 87C64-2
87C64 87C64-3
Vee ±5% N87C64-1 N87C64-2
Versions (3) N87C64 N87C64-3
P87C64-1 P87C64-2
87C64-15 87C64-20 Unit
87C64-25 87C64-30
Vee ±10% N87C64-15 N87C64-20
N87C64-25 N87C64-30
P87C64-15 P87C64-20
Symbol Parameter Min Max Min Max . Min Max Min Max
tLL Chip Deselect Width 50 50 60 75 ns
tAL Address.to CE-Latch Set-up 7 20 25 30 ns
tLA Address Hold from CE-LATCH 30 .45 50 60 ns
tACL CE-Latch Access Time 150 200 250 300 ns
tOE Output Enable to Output Valid 75 75 100 120 ns
tCOE ALE ICE to Output Enable 30. 45 50 60 ns
tCHZ(2) Chip Deselect to Output in High Z 45 50 60 75 ns
tOHZ(2) Output Disable to Output 35 50 60 75 ns
in HighZ
NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.BV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.
A.C. WAVEFORMS .....•!
ALE/CE
tACL
OUTPUTS
-tCOE--t+----IOE
OE----~ ......_ _ _ __J
290000-6
CAPACITANCE(1) TA = 25·C. f = 1.0 MHz
Symbol Parameter Max Unit Conditions
CIN Address/Control Capacitance 6 pF VIN = OV
COUT Output Capacitance 12 pF VOUT = OV
NOTE:
1. Sampled. Not 100% tested.
A_C_ TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
2.4
2.0>
0.8
____
TEST POINTS _ _
2.0
OUTPUT
~0.8;.... __
fil-'N9"
3.3Kn
0.45
DEVICE
UNDER ~DUT
290000-10 TEST
CL= 100 pF
A.C. Testing: Inputs are driven at 2.4V for a Logic "1 "and 0.45V
'for a Logic "a". Timing measurements are made at 2.0V for a .l
logic "I" and O.BV for a Logic "0".
290000-3
CL ;= 100 pF
CL Includes Jig Capacitance
10-138
27C64/87C64
DEVICE OPERATION
The modes of operation of the 27C64/87C64 are
listed in Table 1. A single SV power supply is re-
quired in the read mode. All inputs are TIL levels
except for VPP and 12V on A9 for inteligent Identifier
mode.
Table 1. Mode Selection for 27C64 and 87C64
Pins A,LE/CE PGM . Vpp
OE Ag Ao Vee Outputs
Mode CE (7) (7)
Read VIL VIL VIH X(l) X Vee S.OV DOUT
Output Disable VIL VIH VIH X X Vee S.OV HighZ
Standby VIH X X X X Vee S.OV HighZ
Programming VIL VIH VIL X X (4) (4) DIN
Program Verify VIL VIL VIH X X (4) (4) DOUT
Program Inhibit VIH X X X X (4) (4) HIGHZ
inteligent Identifier(3) VIL VIL VIH VH(2) VIL Vee Vee 89 H (6)
-Manufacturer 88 H (6)
inteligent Identifier(3) VIL VIL VIH VH(2) VIH Vee Vee 07 H
-27C64
inteligent Identifier(3, 5) VIL VIL VIH VH(2) VIH Vee Vee 37 H
-87C64
NOTES:
1. X can be VIL or VIH.
2. VH = 12.0V ± O.5V.
3. A1-Aa, A10-12 = VIL.
4. See Table 2 for Vcc and Vpp voltages.
5. ALE ICE has to be toggled in order to latch in the addresses and read the signature codes.
6. The Manufacturer's identifier reads 89H for Cerdip devices; 88H for Plastic DIP and PLCC devices. _
7. In Read Mode tie PGM and Vpp to Vee.
Read Mode: 27C64 Read Mode: 87C64
The 27C64 has two control functions, both of which The 87C64 was designed to reduce the hardware
must be logically active in order to obtain data at the interface requirements when incorporated in proces-
outputs. Chip Enable (CE) is the power control and sor systems with multiplexed address-data busses.
should be used for device selection. Output enable Chip count (and therefore power and board space)
(OE) is the output control and should be used to can be minimized when the 87C64 is designed as
gate data from the output pins. Assuming that ad- shown in Figure 4. The processor's multiplexed bus
dresses are stable, the address access time (tAee) (ADo-7) is tied to both address and data pins of the
is equal to the delay from CE to output (teE). Data is 87C64. All address inputs of the 87C64 are latched
available at the outputs after a del~f tOE from the when ALE/CE is brought low, thus eliminating the
falling edge of OE, assuming that CE has been low need for a separate address latch.
and addresses have been stable for at least
tAee-tOE·
10-139
inter 27C64/87C6:4
The 87C64 internal address latch is directly enabled SYSTEM CONSIDERATIONS
through the use of the ALE/CE line. As the transition
occurs on the ALE/CE from the TTL high to the low The power switching characteristics of EPROMs re-
state, the last address presented at the address pins quire careful decoupling of the devices. The supply
is retained. Data is then enabled onto the bus from current, Icc, has three segments that are of interest
the EPROM by the OE pin. to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
Vss Vee RST Vee Vss . edges of Chip Enable. The magnitude of these tran-
sient and inductive current peaks is dependent on
the output capacitive and inductive loading of the
device. The associated transient voltage peaks can
be. suppressed by complying with Intel's Two-Line
Control; and by properly selected decoupling capaci-
tors. It is recommended that a 0.1 p..F ceramic ca-
pacitor be used on every device between Vee and
290000-4 GND. This should be a high frequency capaCitor for
low inherent inductance and should be placed as
Figure 4. 80C31 with 87C64 clo.se to the device as possible. In addition, a 4.7 p..F
System Configuration bulk electrolytic capacitor should be used between
Vee and GND for every eight devices. The bulk ca-
pacitor should be located near where tlie power sup-
Standby !\/lode ply is connected to the array. The purpose of the
,bulk capacitor is to overcome the voltage droop
The 27C64 and 87C64 have Standby modes which caused by the inductive effect of PC board-traces.
reduce the maximum Vee current to 100 p..A. Both
are placed in the Standby m'ode when CE or
ALE/CE are in the CMOS-high state. When in the PROGRAMMING MODES
Standby mode, the outputs are in a high impedance
state, independent of the OE input. Caution: Exceeding 14Von Vpp will permanently
damage the device.
Two Line Output Control Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
Because EPROMs are usually used in larger memo- selectively programming "Os" into the desired bit lo-
ry arrays, Intel has provided 2 control lines which cations. Although. only "Os" will be programmed;
accommodate this multiple memory connection. The both "1 s" and "Os" can be present in the data word.
two control lines allow for: The only way to change a "0" to a "1" is by ultravio-
a) the lowest possible memory power dissipation, let light erasure.
and
The device is in the programming mode when Vpp is
b) complete assurance that output. bus .contention raised to its programming voltage (See Table 2) and
will not occur. CE (or ALE/CE) and PGM are both at TTL low and
OE = VIH. The data to be programmed is applied 8
To use these two control lines most efficiently, CE , bits in parallel' to the data output pins. The levels
(or 'ALE/CE) should be decoded and used' as the required for the address and data inputs are TTL:
primary device selecting function, while OE should
be made a common connection to all devices in the
array and connected to the READ line from the sys- Program Inhibit
tem control bus. This assures that all deselected
memory devices are in their low power standby Programming of multiple EPROMSin parallel with
mode and that the output pins are active only when different data is easily accomplished by using ·the
data is desired from a particular memory device. Program Inhibit mode. A high-level CE (or ALE/CE)
or PGM input inhibits the other devices from being
programmed.
10-140
inter 27C64/87C64
Except for CE (or ALE/CE), all like inputs (including ERASURE CHARACTERISTICS (FOR
OE) of the parallel EPROMs may be common. A TTL
CERDIP EPROMS)
low-level pulse applied to the £9lM input with Vpp at
its programming voltage and CE (or ALE/CE) = VIL The erasure characteristics are such that erasure
will program the selected device. begins to occur upon exposure to light with wave-
lengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
Program Verify types of fluprescent lamps have wavelengths in the
3000-4000A range. Data shows that constant expo-
A verify (read) should be performed on the pro- sure to room level fluorescent lighting could erase
grammed bits to determine that they have been cor- the EPROM in approximately 3 years, while it would
rectly programme!LThe verify is performed with OE take approximately 1 week to cause erasure when
and CE (or ALE/CE) at VIL, PGM at VIH, and Vee exposed to direct sunlight. If the device is to be ex-
and Vpp at their programming voltages. Data should posed to these types of lighting conditions for ex-
be verified a minimum of tOE after the falling edge of tended periods of time, opaque labels should be
OE. placed over the window to prevent unintentional era-
sure.
inteligent Identifier™ Mode The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
The inteligent Identifier Mode allows the. r~adin~ ~ut of 2537 Angstroms (A). The integrated dose (Le., UV
of a binary code from an EPROM that will Identify Its
intensity x exposure time) for erasure should be a
manufacturer and type. This mode is intended for minimum of 15 Wsec/cm 2. The erasure time with
use by programming equipment for the purpose of .this dosage is approximately 15 to 20 minutes using
automatically matching the device to be pro-
an ultraviolet lamp with a 12000 )J-W/cm2 power rat-
grammed with its corresponding programming algo-
ing. The EPROM should be placed withi~ 1 in~h of
rithm. This mode is functional in the 25°C ± 5°C am-
the lamp tubes during erasure. The maximum inte-
bient temperature range that is required when pro-
grated dose an EPROM can be exposed to without
gramming the device. damage is 7258 Wsec/cm 2 (1 week @ 12000 )J-W/
cm 2). Exposure of the device to high intensity UV
To activate this mode, the programming equipment light for longer periods may cause permanent dam-
must force 11.5V to 12.5V on address line A9 of the
age.
EPROM. Two identifier bytes may then be se-
quenced from the device outputs by toggling ad-
dress line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
CHMOS NOISE CHARACTERISTICS
Mode. Special EPI processing techniques have enabled In-
tel to build CHMOS with features adding to system
Byte 0 (AO = VIL) represents the manufacturer code reliability. These include input/output protection to
and byte 1 (AO = VIH) the device identifier code. latch-up. Each of the data and address pins will not
These two identifier bytes are given in Table 1. latch-up with currents up to 100 mA and voltages
ALE/CE of the 87C64 has to be toggled in order to from -1V to Vee + 1V.
latch in the addresses and read the Signature
Codes. Additionally, the Vpp (programming) pin is designed
to resist latch-up to the 14V maximum device limit.
10-141
27C64/87C64
290000-12
Figure 5. Quick-Pulse Programming™ Algorithm
Quick-Pulse Programming™ Algorithm fication to determine when the address byte has
been successfully programmed. Up to 25 100 /Jos
Intel's 27C64 and 87C64 EPROMs can now be pro- pulses per byte are provided before a failure is rec-
grammed using the Quick-Pulse Programming Algo- ognized. A flowchart of the Quick-Pulse Program-
rithm, developed by Intel to substantially reduce the ming Algorithm is shown in Figure 5.
throughput time in the production environment. This
algorithm allows these devices to be programmed in For the Quick Pulse Programming Algorithm, the en-
under one second, almost a hundred fold improve- tire sequence of programming pulses and byte verifi-
ment over previous algorithms. Actual programming cations is performed at Vee = 6.25V and Vpp at
time is a function of the PROM programmer being 12.75V. When programming of the EPROM has
used. been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.
The Quick-Pulse Programming Algorithm uses initial
pulses of 100 microseconds followed by a byte veri-
10-142
inter 27C64/87C64
D.C. PROGRAMMING CHARACTERISTICS (27C64/87C64) T A = 25°C ± 5°C
Table 2
Limits Test Conditions
Symbol Parameter
(Note 1)
Min Max Unit
III Input Current (All Inputs) 1.0 p.A VIN = VIL or VIH
VIL Input Low Level (All Inputs) -0.1 0.8 V
VIH Input High Level 2.0 Vee + 0.5 V
VOL Output Low Voltage During Verify 0.45 V IOL = 2.1 mA
VOH Output High Voltage During Verify 3.5 V IOH = -2.5 mA
lee2(3) Vee Supply Current 30 mA
IpP2(3) VPP Supply Current (Program) 30 mA CE = VIL
VIO Ag inteligent Identifier Voltage 11.5 12.5 V
Vpp Programming Voltage 12.5 13.0 V
Vee Supply Voltage During Programming 6.0 6.5 V
A.C. PROGRAMMING CHARACTERISTICS 27C64
T A = 25°C ± 5°C, See Table 2 for Vee and Vpp Voltages
Limits Conditions
Symbol Parameter
(Note 1)
Min Typ Max Unit
tAS Address Setup Time 2 p.s
toES OE Setup Time 2 p.s
tos Data Setup Time 2 p.s
tAH Address Hold Time 0 p.s
tOH Data Hold Time 2 p.s
tOFP OE High to Output Float Delay 0 130 ris (Note'2)
tvps Vpp Setup Time 2 p.s
tves Vee Setup Time 2 p.s
teEs CE Setup Time 2 p.s
tpw PGM Program Pulse Width 95 100 105 p.s Quick-Pulse
toE Data Valid from OE 150 ns
N'OTES: .
A_C_ CONDITIONS OF TEST
1. Vee must be applied simultaneously or before Vpp and
Input Rise and Fall Times (10% to 90%) ...... 20 ns removed Simultaneously or after Vpp.
Input Pulse Levels ...•.............. 0.45V to 2.4V 2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no long-
Input Timing Reference Level ....... 0.8V and 2.0V er driven-see timing diagram.
Output Timing Reference Level ...... 0.8V and 3.5V ' 3. The maximum current value is with outputs 00 to 07 Un-
loaded.
10-143
intJ 27C64/87C64
PROGRAMMING WAVEFORMS 27C64
.PRDGRAM VERIFY
'~ -
ADDRESSES
_IA' __
ADDRESS STABLE
L
~
_'AH
DATA DATA IN STABLE
~ HIGHZ
DATA OUT vlLlD
12.75V
~ID' __ f+'DH.,
It'
- ~
'OF,!»
.-.-/ _'VP'__
Vpp
5.0V
8.25V
,
Vee ,
5.0V -.-/ _'ve,_
V,H
-
CE
V"
\
_'e,,_
V'H
PGM
-
V"
I,.
l- i-- 'OES1
-
'OE(2)
- I-- -
V'H
DE
V"
topw
, \
290000-9
NOTES: "
1. The Input Timing Reference Level is 0.8V for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27C64, a 0.1 ,.F capacitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.
10-144
intJ 27C64/87C64
A.C. PROGRAMMING CHARACTERISTICS 87C64:
TA = 25°C ±5°C, See Table 2 for Vee and Vpp Voltages: . . ..
Lilnits
Symbol ..Parameter Unit Conditions
Min Typ Max
tvps Vpp Setup Time 2 p.s
tves Vee Setup Time 2 p's
tLL Chip Deselect Width 2 p.s
tAL Address to Chip Select Setup 1 p.s
tLA Address Hold from Chip Select 1 p.s
tpw PGM Pulse Width 95 100 105 p.s Quick-Pulse
tos Data Setup Time 2 p.s
tOFP OE High to Data Float 0 130 ns
tOES Output Enable Setup Time 2 p.s
tOE Data Valid from Output Enable 150 ns
tOH Data Hold Time 2 tJ. s
teEs CE Setup Time 2 p.s
NOTE:
1. Programming tolerances and test conditions are the same as 27C64.
PROGRAMMING WAVEFORMS :etc6~1
ADDRESS )I( ADDRESSES (
, !-=tAL+ -tLA-
DATA - X-
ALE/CE I-
I-tDS " HD~~tOES-r--J:OE I-tDf:J-
tLL-
(1)
Vpp
~ t vps
- - tves tCES-
(1)
Vee ~
~
tpw"
-;~;w
\-..J
290000-8
NOTE:
1. 12.75V Vpp & 6.25V Vee for Quick-Pulse Programming Algorithm.
10-145
inter ·87C257
256K (32Kx 8) CHMOS UV ERASABLE PROM
• CHMOS/NMOS Microcontroiler and • Noise Immunity Features
Mlcroproce$sor Compatible - ± 10% Vee Tolerance
- 87C257-1ntegrated Address Latch - Maximum Latch·up Immunity
- Universal 28 Pin Memory Site, 2·line Through EPI Processing
Control .
• New Quick·Pulse Programming™
'., Low Power Consumption Algorithm
• High Performance Speeds - 4 Second Programming
- 170 ns Maximum Access Time • Available in 28·Pln Cerdip Package
(See Packaging Spec .• Order '" 231369)
Intel's 87C257 CHMOS EPROM is a 256K-bit 5V only memory organized as 32,768 8-bit words. It employs
advanced CHMOS*II-E circuitry for systems requiring low power, high speed performance, and noise immuni-
ty. The 87C257 is optimized for compatibility with multiplexed address/data bus microcontrollers such as
Intel's 16 MHz 80.51- and 80.96- families.
The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's multiplexed address/data pins. Address information (inputs Ao-A14) is latched
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.
The 87C257 is offered in a ceramic DIP package, providing flexibility in prototyping and R&D environments.
The 87C257 employs the Quick-Pulse Programming™ Algorithm for fast and reliable programming.
Intel's EPI processing achieves the highest degree of latch-up protection. Address and data pin latch-up
prevention is provided for stressesup to 10.0. mA from -1V to Vcc + 1V.
'HMOS and, CHMOS are patented processes of Intel Corporation.
DATA OUTPUTS
0 0-07
5E OUTPUT ENABLE
PROG LOGIC
OUTPUT BUffERS
CE
CHIP ENABLE
ALE ADDRESS LATCH ENABLE
Y DECODE Y-GATING
:>:
~
In X DECODE 262,144 BIT
Ao-A I4 In CELL MATRIX
ADDRESS '"'"
Q
INPUTS Q
..:
290135-1
Figure 1. Block Diagram
October 1987
10.-146 Order Number: 290135-002
87C257
Pin Names
Ao-A14 ADDRESSES
00-0 7 OUTPUTS
OE OUTPUT ENABLE
CE CHIP ENABLE
ALE/vpp Address Latch
Enable/Vpp
N.C. NO CONNECT
87C64 87C257 87C64
ALE/Vpp vee
Vpp Vee
A12 A12 A14 PGM
A7 A7 A13 N.C
As As As As
As As A9 Ag
A4 A4 All An
As A, OE OE
A2 A2 AID A10
A1 AI CE ALE/CE
Ao AD ~ 07
00 00 06 Os
01 01 Os Os
02 02 04 04
Gnd GND 03 Os
290135-2
Figure 2. DIP Pin Configuration
NOTE:
Intel "Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent.
10~147
inter 87C257
. EXTENDED TEMPERATURE
(EXPRESS) EPROMs -
The Intel EXPRESS EPROM family receives addi-
tional processing to enhance product characteris-
tics. EXPRESS processing is available for several
EPROM densities allowing the appr-opriate memory
size to match system applications. EXPRESS
EPROMs are available with 168 ±8 hour, 125·C dy-
namic burn-in using Intel's standard bias configura-
tion. This process meets or exceeds most industry
burn-in specifications. The standard EXPRESS
EPROM operating temperature range is O·C to
+ 70·C. Extended operating temperature range Vee
07
(-40·C to +85·C) EXPRESS and automotive tem-
06
perature range (- 40·C to + 125·C) products are
also available. Like all Intel EPROMs, the EXPRESS 05
EPROM family is inspected to 0.1 % electrical AQL. °4
This allows reduction or elimination of incoming test-
ing.
°3
29013S-4
OE = SVR = 1 KflVcc= +SV
ALElVpp = + SV Vss = GND CE = GND
AUTOMOTIVE AND EXPRESS
OPTIONS
Versions
Speed Packaging Options
Versions Cerdlp
-200V05 A
-250V10 A
•
-250V05 A
29013S-S
Binary Sequence from AD 10 A14
AUTOMOTIVE AND EXPRESS EPROM Burn-In Bias and Timing Diagrams
PRODUCT FAMILY
PRODUCT DEFINITIONS
Operating Burn-in 125·C
Type
Temperature ("C) (hr)
Q O·Cto +70·C 168 ±8
T - 40·C to + 85·C NONE
L - 40·C to + 85·C 168 ±8
A - 40·C to + 125·C NONE
B - 40·C to + 125·C 168 ±8
10-148
infef 87C257
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Operating Temperature, During age to the device. This is a stress rating only and
Read .....••••••.••.•••....•. O'C to + 70'C(2)
functional operation of the device at these or any
Temperature Under Bias ..••... -1 O'C to + 80'C(2)
other conditions above those indicated in the opera-
Storage Temperature .......... - 65'C to + 150'C tional sections of this specification is not implied Ex-
Voltage on any Pin with posure to absolute maximum rating conditions for
Respectto Ground ........••••• - 2V to + 7V(1) ex/ended periods may affect device reliability.
Voltage on Ag with
Respect to Ground ....•..••. - 2V to + 13.5V(1) NOTICE Specifications contained within the
Vpp Supply Voltage with Respect to Ground following tables are subject to change.
During Programming •.•.•.•.. - 2V to + 14.0V(1)
Vcc Supply Voltage with .
Respectto Ground ....•......• -2V to +7.0V(1)
READ OPERATION
D.C. CHARACTERISTICS TTL and NMOS Inputs
Symbol Parameter Notes Min Typ(3) Max Units Test Condition
III Input Load Current 0.Q1 1.0 ".A VIN = OV to 5.5V
ILO Output Leakage Current ±10 ".A VOUT = OV to 5.5V
158 Vee Current Standby I' Switching 10 mA CE = ALE = VIH
with Inputs- I Stable 1.0 mA CE = VIH. ALE = VIL
leel Vee Current Active 5 30 mA CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA
VIL Input Low Voltage ( ± 10% Supply) 1 -0.5 O.B V
VIH Input High Voltage (± 10% Supply) 2.0 Vee + 0.5 V
VOL Output Low Voltage 0.45 V 10L = 2.1 mA
VOH Output High Voltage 2.4 V 10H = -400".A
los Output Short Circuit Current 6 100 mA
D.C. CHARACTERISTICS CMOS Inputs
Symbol Parameter Notes Min Typ(3) Max Units Test Condition
III Input Load Current 0.01 1.0 ".A VIN = OV to 5.5V
ILO Output Leakage Current ±10 ".A VOUT = OV to 5.5V
158 Vee Current Standby 1 Switching 4 6 mA CE = ALE = Vee
with Inputs- 1 Stable 100 CE = Vec. ALE = GND
".A
leel Vee Current Active 5 15 mA CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA
VIL Input Low Voltage (± 10% Supply) -0.2 0.8 V
VIH Input High Voltage (± 10% Supply) 0.7 Vee Vee + 0.2 V
VOL Output Low Voltage 0.4 V 10L = 2.1 mA
VOH Output High Voltage Vee - O.B 'V 10H = -2.5 mA
los Output Short Circuit Current 6 100 mA
NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions. the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum D.C. voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V. TA = + 25'C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
10-149
87C257
READ OPERATION
A.C. CHARACTERISTICS(1) O·C s: TA s: + 70·C
Verslons(3)
I Vee ±5% 87C257·170V05 87C257-200V05 87C257-250V05
I Vee ±10% 87C257-200V10 87C257-250V10 Units
Symbol Characteristic Min Max Min Max Min Max
tACC Address to Output Delay 170 200 250 ns
tCE CE to Output Delay 170 200 250 ns
tOE OE to Output Delay 70 75 100 ns
tOF(2) OE High to Output High Z 35 40 55 ns
toH(2) Output Hold from Addresses, CE or 0 0 0 ns
OE Change·Whichever is First
tLL Latch Deselect Width 35 55 60 ns
tAL(2) Address to Latch Set·Up 7 15 25 ns
tLA Address Hold from LATCH 20 30 40 ns
tLOE ALE to Output Enable 20 30 .40 ns
NOTES: A.C. CONDITIONS OF TEST
1. See A.C. Testing Input/Output Waveforms for timing
measurements. . ,
Input Rise and Fall Times (10% to 90%) ....•. 10 ns
2. Guaranteed and sampled.
3. Model Number Prefixes: No Prefix = CERDIP.
Input Pulse Levels., ................... VOL to VOH
Input Timing Reference Level ..•.........•... 1.5V
Output Timing Reference Level ........ VIL and VIH
A.C. WAVEFORMS
V1H
ALE
V1L
VIH _ _ _ _~~--+_
CE
V1L
(2)
V ____
IH
+ _________ _
t LOE --~-tOE
Of
V1L
~~~---~cc------~
OUTPUT VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..!i!:~L._t:§~~~~§:~~
HIGH Z
V1L
290135-6
NOTES:
1. This parameter is only sampled and is not 100% tested.
2. DE may be delayed up to IcE:"tOE after the falling edge of CE without impact on tCE'
10-150
inter 87C257
CAPACITANCE(1} TA = 25°C. f = 1.0 MHz
Symbol Parameter Max Units Conditions
CIN Address/Control Capacitance 6 pF VIN = OV
COUT Output Capacitance 12 pF VOUT = OV
NOTE:
1. Sampled. Not 100% tested.
A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
1.:~
~~IN914
1.5 -lEST POINlS :::::: IH OUTPUT
V1L -
3.3k.D.
DEVICE
UNDER OUT
290135-7
TEST
:e-- CL
A.C. testing inputs are driven at VOH for a Logic "I" 290135-S
and VOL for a Logic "a". Timing measurements are CL = 100 pF
made-at VIH for a Logic "1" and VIL for a Logic "a". CL Includes Jig Capacitance
DEVICE OPERATION
Table 1 lists 87C257 operating modes. Read mode requires a single 5V power supply. All input. levels are TTL
or CMOS except A9 in inteligent Identifier mode and Vpp.
Table 1. Mode Selection
Pins ALE/
CE OE As Ao Vee Outputs
Vpp
Mode
Read VIL VIL X(1) X X 5.0V DOUT
Output Disable - VIL VIH X X X 5.0V HighZ
Standby VIH X X X X 5.0V HighZ
Programming VIL VIH X X (Note 4) (Note 4) DIN
Program Verify VIH VIL X X (Note 4) (Note 4) DOUT
Optional Program VIL VIL X X Vee (Note 4) DCUT
Verify (Note 4)
Program Inhibit VIH VIH X X (Note 4) (Note 4) HighZ
inteligent Identifier(3) VIL VIL VH(2) VIL X Vec 89H
-Manufacturer
inteligent Identifier(3) VIL VIL VH(2) VIH X VCC 24H
-87C257
NOTES:
1. X can be VIL or VIH.
2. VH = 12.0V ±0.5V.
3. AI-As. AlO-12 = VIL. A13-14 = X.
4. See Table 2 for Vee and Vpp programming voltages.
10-151
inter 87C257
Read Mode Two Line Output Control
The 87C257 has two control functions; both must be EPROMs are often used in larger memory arrays.
logica"y active to obtain data at the outputs. Chip Intel provides two contol inputs to acCommodate
Enable (CE) is the power control and the device-se- multiple memory connections. Two-line control pro-
lect. Output enable (OE) gates data to. the output vides for:
pins by controlling the output buffer. When the ad- a) the lowest possible memory power dissipation,
dress is stable (ALE = VIH) or latched (ALE = VII), Md .
the address access time (tACe) equals the delay
from CE to output (teE). Ou~ts display valid data b) complete assurance that output bus contention
tOE after the falling edge of OE, assuming tACC and will not occur.
teE times are met.
To efficiently ·use these two control inputs, an ad-
The 87C257 reduces the hardware interface in multi- dress decoder should enable CE, while OE should
plexed address-data bus systems. Figure 4 shows a be connected to a" memory-array devices and the
low power, sma" board space, minimal chip system's READ control line. This assures that only
87C257/microcontro"er design. The processor's selected memory devices have active outputs while
multiplexed bus (ADo.7) is tied to the 87C257's ad- deselected memory devices are in low-poWer stand-
dress and data pins. No separate. address latch is by mode.
needed because the 87c257 latches a" address in-
pilts when ALE is low.
SYSTEM CONSIDERATIONS
The ALE input controls the 87C257's internal ad-
EPROM power switching characteristics require
dress latch. As ALE transitions from VIH to VIL, the
careful device decoupling. System designers are in-
last address present at the address pins is retained.
terested in three supply current (ICC) issue!r-stand-
The OE control can then enable EPROM data onto
the bus. by current levels, active current levels, and transient
current peaks produced by falling and rising edges
. of Chip Enable. Transient current magnitudes de-
vss vee RST pend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling ca'
pacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 IlF ceramic
'capacitor connected between its Vcc and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additiona"y, for every eight devices, a 4.7 IlF elec-
trolytic capacitor should be placed between Vcc.and
GND at the array's power supply connection. The
bulk capacitor will overcome voltage slumps caused
by PC board trace inductances.
290135-9
PROGRAMMING MODES'
Figure 4. 80C31 with 87C257
Caution: Exceeding 14Von Vpp will permanently
System Configuration
damage the devIce.
Initia"y, and after each erasure, a" EPROM bits are
Standby Mode in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Al-
The standbLmode substantially reduces Vcc cur-
rent. When CE = VIH, the standby mode places the though only "Os" are programmed, the data word
outputs in a high impedance state, independent of
the OE input.
10-152
intJ 87C257
can contain both "1s" and "Os". Ultraviolet light era- inteligent Identifier™ Mode
sure is the only way to change "Os" to "1s".
The inteligent Identifier Mode will determine an
The programming mode is entered when Vpp is EPROM's manufacturer and device type. Program-
raised to its programming voltage (see Table 2). ming equipment can automatically match a device
Data is programmed by applyil]Lan 8-bit word to the with its proper programming algorithm.
output pins (00-7). Pulsing CE to TTL-low while
OE = VIH will program data. TTL levels are required This mode is activated when programming equip-
for address and data inputs. ment forces 12V ±0.5V on the EPROM's Ag ad-
dress line. With A1-Aa, A1O-A12 = VIL (A13-14 are
don't care), address line Ao = VIL will present the
Program Inhibit manufacturer's code and Ao = VIH'the device code
(see Table 1). When Ag = VH, ALE need not be
The Program Inhibit mode allows parallel program- toggled to latch each identifier address. This mode
ming of multiple EPROMs with different data. With functions in the 25°C ± 5°C ambient temperature
Vpp at its programming voltage, a CE-Iow pulse pro- range required during programming.
grams the desired EPROM. CE-high inputs inhibit
programming of non-targeted devices. Except for CE
and OE, parallel EPROMs may have common in- ERASURE CHARACTERISTICS (FOR
puts.
CERDIP EPROMS)
Exposure to light of wavelength shorter than 4000
Program Verify Angstroms (A) begins EPROM erasure. Sunlight and
some fluorescent lamps have wavelengths in the
With Vpp and Vee at their programming voltages, a 3000.,...4000A range. Constant exposure to room-Iev-'
verify (read) determines that bits are correctly pro- el fluorescent light can erase an EPROM in about 3
grammed. The verify is performed with CE = ~ years (about 1 week for direct sunlight). Opaque la-
and OE = VIL. Valid data is available tOE after OE bels over the window will prevent unintentional era-
falls low. sure under these lighting conditions.
The recommended erasure procedure is exposure,
Optional Program Verify to 2537A ultraviolet light. The minimum integrated
dose (intensity x exposure time) is 15 Wsec/cm 2.
The optional verify allows parallel programming and
Erasure time using a'12000 p.W/cm2 ultraviolet
verification when several devices share a common
lamp is approximately 15 to 20 minutes. The
bus. It is performed with CE = OE = VIL and Vpp =
EPROM should be placed about 1 inch from the
Vee = 6.25V. The normal read mode is then used
lamp. The maximum integrated dose is 7258
for .E!:9gram~erify. Outputs will tri-state depending Wsec/cm 2 (1 week @ 12000 p.W/cm 2 ). High intensi-
on OE and CEo
ty UV light exposure for longer periods can cause
permanent damage.
10-153
inter 87C257
290135'-10
Figure 5. Qulck·Pulse Programmlng™ Algorithm
CHMOS NOISE CHARACTERISTICS tion to determine when the addressed byte is cor-
rectly programmed. The algorithm terminates if 25
System reliability is enhanced by Intel's CHMOS 100/kS pulses fail to program a byte. Figure 5 shows
EPI-process techniques. Protection on each data the Quick-Pulse Programming algorithm flowchart.
and address pin prevents latch-up; even with 100
mA currents and voltages from -1V to Vee + 1V. The entire program-pulse/byte-verify sequence is
Additionally, the Vpp pin is designed to resist latch- performed with Vee = 6.25V and Vpp = 12.75V.
up to the 14V maximum device limit. . When programming is complete, all bytes should be
compared to the original data with Vee = 5.0V.
Quick-Pulse Programmlng™ Algorithm
Alternate Programming
The Quick-Pulse Programming algorithm programs
Intel's 87C257 EPROM. Developed to substantially Intel's 27C256 and 27256 Quick-Pulse Programming
reduce production programming throughput time, algorithms will also program the 87C257. By overrid-
this algorithm can program a 87C257 in under four . ing a check for the inteligent Identifier, older or non-
seconds. Actual programming time depends on the upgraded PROM programmers can program the
PROM programmer used. . 87C257. See Intel's 27C256 and 27256 data sheets
for programming waveforms of these alternate algo-
The Quick-Pulse Programming algorithm uses a 100 rithms.
microsecond initial-pulse followed by a byte verifica-
10-154
intJ 87C257
D.C. PROGRAMMING CHARACTERISTICS TA = 25°C ±SoC
Table 2
limits
Symbol Parameter Test Conditions
Min Max Unit
III Input Current (All Inputs) 1.0 ).tA VIN = VIL or VIH
VIL Input Low Level (All Inputs) -0.2 0.8 V
VIH Input High Level 2.0 Vee + 0.5 V
VOL Output Low Voltage During Verify 0.4 V IOL = 2.1 rnA
VOH Output High Voltage During Verify Vee - 0.8 V IOH = -400).tA
lee2(3) Vee Supply Current 30 rnA
IpP2(3) Vpp Supply Current (Program) 50 rnA CE = VIL
VIO Ag inteligent Identifier Voltage 11.5 12.5 V
Vpp(1) Programming Voltage 12.5 13.0 V
Ved 1) Supply Voltage During Programming 6.0 6.5 V
A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C; see Table 2 for Vee and Vpp voltages.
Limits
Symbol Parameter Conditions
Min Typ Max Unit
tAS Address Setup Time 2 ).ts
tOES OE Setup Time 2 ).ts
tos Data Setup Time 2 ).ts
tAH Address Hold Time 0 ).ts
tOH Data Hold Time 2 ).ts
tOFP(2) OE High to
0 130 ns
Output Float Delay
tVPS(1) Vpp Setup Time 2 ).ts
tves(1) Vee Setup Time 2 ).ts
tpw CE Program Pulse Width 95 100 105 ).ts
toE Data Valid from OE 150 ns
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 unloaded.
10-155
'V
12.0 V . - - - - -
I
1 1"ta lig ent Identifier. • 1"ta ng ent identifier
Manufacturer
Ag
I
=12.0V
Dey;ce
I " Blank Check
Illegal Bit Check I
I' Pro rom
g
I
I • Program
Verify
I
I • Re~d
Verify
I I
JJ
oC)
JJ
l>
s:
l
Address~::==>f AO=VIL '""'Z:AI-8'Al0-12=VIL~ ADDRESSVALID )~ ADDRESS STABLE I .n; "uun~JJ ,"",u ~ s:
Z
VIH Q
~
Data
VIL '
<
m
ALE;::el~ : ~ ~ - - - - - - - - - -1-- ~ ~ --~ -----t i
."
oJJ
s:
en
65~~~ . --; - ---- --- T -----~ -----
Vee
~ ..,.
01)
~ VIH o
N
(J1
en cr ..,.CI1
VIL
VIH ~
OE
VIL
290135-11
NOTES:
1. The input timing reference level is VIL = 0.8V and VIH = 2V.
2. toE and tOFP are device characteristics but must be accommodated by the programmer.
3. To prevent device damage durir]g programming, a 0.1 ,..F capacitor is required between Vpp and ground to suppress spurious voltage transients. , ~
4. During programming, the address latch function is bypassed whenever Vpp = 12.75V or A9 = VH. When Vpp and A9 are at TTL levels, the address'latch function is aID
enabled, and the device functions in read mode. ' ' ' Iffiil
5. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH. F
~
~
~
~
C:g
UPI-4S2
CHMOS PROGRAMMABLE 1/0 PROCESSOR
83C452 - 8K x 8 Mask Programmable Internal ROM
87C452P - 8K x 8 Piggyback EPROM
80C452 - External ROM/EPROM
• 83C452/87C452P/80C452:3.5 to 16 MHz
• Two 16-Bit Timer/Counters
•
Clock Rate
Software Compatible with the MCS-51 • Boolean Processor
Family • 8BitInterrupt
Addressable RAM
• 128-Byte Bi-Directional FIFO Slave • Programmable Sources
Interface • Channel Full Duplex Serial
• Two DMA Channels
• 64K Program Memory Space
• 256 X 8-Bit Internal RAM
• 64K Data Memory Space
• 34 Additional Special Function
Registers • 68-Pin PGA
•
(See Packaging Spec" Order: #231369)
40 Programmable I/O Lines
,The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave 1/0 Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip, The UPI-452
is the newest member of Intel's UPI family of products, It is a general-purpose slave 1/0 Processor that allows
the deSigner to grow a customized interface solution.
The UPI-452 contains 'a complete 80C51 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent of the UPI-4S2 core CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.
The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-452 internal CPU and external host CPU, bypassing the FIFO.
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a, single DMA operation. Three distinct memory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).
September 1987
10-157 Order Number: 231428-003
C
o
o'"
,Q00
c'"
_z
~":::"
l
!II
o "'z
01 ~I'"
I
o~I ~
:::a 00 it
~ ~I ..... 0
!1; AO~Z
- - - - - - - - - -l} - -
NfAf'TIC
r-
illi - - - - - -I ~I~ ,
"II
iiii
...
r:::
ID
I o
...
Z
o»o::::!;;Itn
~z!:"''i:
~c~~~
'"
~
~ -fl- ---------ft --- i:~
" FIFO FIFO " FIFO HOST-
~
IMMEDIATE I HOST DMA
:-" INPUT MODULE OUTPUT FIFO COMMAND AND
...n
:I>
41>-
CHANNEL SLAVE- CHANNEL INTERFACE INTERRUPT
REQUEST
.....
~
U1
:::T
;::;:
ID
2-
r:::
~m
INTERFACE
srn~
HCON
HSTAT
., '."
Iroo; I II ~
CX> et ...:',
: ;
,,~
PI)
m : i
0'
:J.r.::. __ .JL_-,
#" .... • I
n
~
~
• I I •
C
iii"
~
TI
ea
ii1 l§!
3
~
DMA TIMING
~
AND CONTROL
~
DCON1
SAR1
~
'iiiI
DAR 0
BCRO
DAR 1
BCR 1
©
22J
",L
~
~
@
- ~@ - --
oJ ~
~
~ ~
co 1,/
.!.. @
~
inter UPI·452
~-----------------~------,
i>sEN
ALE
EA
RST
231428-2
Figure 1. Architectural Block Diagram (Continued)
10-159
UPI-4S2
TABLE OF CONTENTS
Introduction
Table of Contents
List of Tables and Figures
Pin Description
Architectural Overview
Introduction
FIFO Buffer Interface
FIFO Programmable Features
Immediate Commands
DMA
FIFO/Slave Interface Functional Description
Overview
Input FIFO Channel
Output FIFO Channel
Immediate Commands
Host & Slave Interface Special Function Registers
Slave Interface Special Function Registers
External Host Interface Special FunctionRegisters
FIFO Module-External Host Interface .
Overview
Slave Interface Address Decodin£ .
Interrupts to the Host
DMA Requests to the Host
FIFO Module-Internal CPU Interface
Overview
Internal CPU Access to FIFO via Software Instructions
General Purpose DMA Channels
Overview
Architecture
DMA Special Function Registers
DMA Transfer Modes
External Memory DMA
Latency
DMA Interrupt Vectors
Interrupts When DMA is Active
DMA Arbitration
Interrupts
Overview
FIFO Module Interrupts to Internal CPU
Interrupt Enabling and Priority
FIFO-External Host Interface FIFO DMA Freeze Mode
Overview.
Initialization
Invoking FIFO DMA Freeze Mode During Normal Operation
. FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode
Internal CPU Read & Write of the FIFO During FIFO DMA Freeze Mode
Memory Organization
Accessing External Memory
Miscellaneous Special Function Register Descriptions
10-160 .
intJ UPI-452
LIST OF TABLES AND FIGURES
Figures:
1. Architectural Block Diagram
2. UPI-452 68-Pin PGA Pinout Diagram
3. UPI-452 Conceptual Block Diagram
4. UPI-452 Functional Block Diagram
5. Input FIFO Channel Functional Block Diagram
6. Output FIFO Channel Functional Block Diagram
7a. Handshake Mechanisms for Handling Immediate Command IN Flowchart
7b. Handshake Mechanisms for Handling Immediate Command OUT Flowchart
8. DMA Transfer from: External to External Memory
9. DMA Transfer from: External to Internal Memory
10. DMA Transfer from: Internal to External Memory
11. DMA Transfer Waveform: Internal to Internal Memory
12. Disabling FIFO to Host Slave Interface Timing Diagram
Tables:
1. Input FIFO Channel Registers
2. Output FIFO Channel Registers
3. UPI-452 Address Decoding
4. DMA Accessible Special Function Registers
5. DMA Mode Control - PCON SFR
6. Interrupt Priority
7. Interrupt Vector Addresses
8. Slave Bus Interface Status During FIFO DMA Freeze Mode
9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
10. Threshold SFRs Range of Values and Number of Bytes to be Transferred
11 a. 80C51 Special Function Registers
11 b. UPI-452 Additional Special Function Registers
12. Program Status Word (PSW)
13. PCON Special Function R~gister
10-161
inter UPI-452
~
t '"
... ~'"....
.
..: .. ~ °...
0..
N
0.. ~
"!
OJ
0..
"!
OJ
0..
III
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.... ....'"
0..
...
0..
C!
OJ
0..
::l
0..
"1
OJ
0..
.,
N
0..
...N
~
0..
'0
Q)
@@ @ @ @ @ @ @@
~ P4.S P4.6 @) @@ @ @ @ @ @ @@ @ Pmi EA
1:
Q)
c P4.7 XTAL1
® @ @ @ PO.7 PO.6
°c,E
8 . XTAL2 AO @ @ @ @ PO.S PO.4·
Q)
=-E Al A2 @ @ @ @ PO.3 PO.2
,g Vss ell @ @ @ ® PO.l Vss
'C
~ READ @ @ ® 0 po.o PLO
·1 DRQOUT/
@ @
1~ WRITE
DRQIN/
INTRQOUT ® ® P1.1 Pl.2
>'E INTRQIN
INTRQ @) @ 0 0 Pl.3 Pl.4
'E~
... .0
DB7 DBS €D @@ @ @ @ @ @ @ ® <D Pl.S Pl.6
.!!ti
.n. @<§ @ @ @ @ @ @ @
.'" ...
IJm
(~= .,m
CI
'"mCI ;;;
CI
": ..; ~
0.. .. .
~ ~ '''1
0:
.. m
CI
...m
CI
....m
CI
0
m
CI ~ ::l .. ..'" "1 ..;
0..
":
0:'
PIN NO.1
MARK
..
m
CI
...
m
CI
....
m
CI
0
m
CI
u
,;'
"1
'" '"
0.. ..
"1 ..;
0..
":
0:
.,m
'"
m ;;;
....
..;
....
..; "!
..'" ..'"
"'! C! "1
PIN NO.1
MARK
CI CI CI 0..
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0.. 0:
'0 @(8l @ @ @ @ @ @ @ '\(
Q)
~
Q)
'C
c
DB7 DBS €D @@ @ @ @ @ @ @ ® <D Pl.S Pl.6
"
Q)
DRQIN/
INTRQIN
INTRQ @) @ 00 0 Pl.3 Pl.4
. =-
E . DRQOUTj
e'E
_01
WiiiTE
INTRQOUT
@ @ ® ® Pl.l Pl.2
-g.8 ~ READ @ @ ® 0 PO.O PLO
It Q)
.S'! -5
> C Vss cs @ @ @ ® PO.l Vss
III 0
1~
0>"
Al A2 @ @ @ @ PO.3 PO.2
>~ XTAL2 AO @ @ @ @ po.s PO.4
'Cc
f! P4.7 XTAL1 @ @ @ @ PO.7 PO.6
-~
c-
O> c
c
o c
c,o
Q) P4.S P4.6 @) @@ @@ @ @ @ @@ @ Pmi EA
ec'
o E @@ @ @ @ @ @ @@
1J8
..
.... ..."10..
:.;: C! ....
0..
"1
OJ
0..
N
0.. .'"
N N
0..
":
OJ
0.. I~
...
. ...
0
.. ~u
... .. ...
..
'" ~'"'"
... ~
0.. 0..
N N
0..
N
0..
III
>
u ....
<
231428-18
Figure 2. UPI-4S2 68-Pin PGA Pinout Diagram
10-162
inter UPI-452
UPI MICROCONTROLLER FAMILY Packaging
The UPI-452 joins the current members of the UPI The 80C452 comes in a 68-pin PGA (Pin Grid Array)
microcontroller family. UPl's are derivatives of the package, while the 87C452P will be offered in a pig-
MCSTM family of microcontrollers. Because of their gyback package. This piggyback package will con-
on-chip system bus interface, UPl's are designed to sist of the standard 68-pin PGA package with a
be system bus "slaves", while their microcontroller 2764A EPROM soldered on top. These two pack-
counterparts are intended as system bus "masters". ages allow designers to use either on-chip EPROM
or external memory for their initial designs. The
These UPI Microcontrollers are fully supported by 83C452 (ROM version) will come in the standard 68-
Intel's EPROM programmers (iUP-201) and develop- pin PGA package. A complete description of
ment tools (ICE, ASM and PLM). 87C452P programming can be found at the end of
this data sheet.
UPI Family MCSFamily
RAM ROM EPROM
(Slave (Master Speed
(Bytes) (Bytes) (Bytes)
Configuration) Configuration)
80C452 80C51 12MHz 256 - -
83C452 80C51 12 MHz 256 8K -
87C452P 80C51 12 MHz 256 - 8K
80C452-1 80C51 16MHz 256 - -
83C452-1 80C51 16 MHz 256 8K -
87C452P-1 80C51 16 MHz 256 - 8K
UPI-4S2 PIN DESCRIPTIONS
Symbol Pin # Type Name and Function
Vss 9/43 I Circuit Ground.
Vee 60 I + 5V power supply during normal, idle, programming and
verification operation. It is also the standby power pin for power
down mode. ..
XTAL1 38 I Input to the oscillator's high gain amplifier. A crystal or external
source can be used.
XTAL2 39 0 Output from the high gain amplifier.
PortO I/O Port 0 is an 8-bit open drain bi-directional I/O port. It is used for data
(ADO-AD7) input and output during programming and verification. External
PO.O 8 pull ups are required during program verification. Port 0 can sink
.1 10 eight LS TIL inputs. It is also the multiplexed low-order address and
.2 11 data local expansion bus during accesses to external memory.
.3 12
.4 13
.5 14
.6 15
PO.7 16
10-163
inter UPI-452
UPI-452 PIN DESCRIPTIONS (Continued)
Symbol Pin # Type Name and Function
Port 1 1/0 Port 1 is an 8-bit quasi-bi-directionaII/O-port.lt is used for low-order
(AO-A~ address byte during programming and verification. Port 1 can sink
(HLD, HLDA) four LS TIL inputs. The alternate functions can only be activated if
P1.0 7 the corresponding bit latch in the port SFR contains a 1. Otherwise,
the port pin is stuck at O. Pins P1.5 and P1.6 are multiplexed with
.- HLD and HLDA respectively whose functions are defined as below:
.1 6 Port Pin Alternate Function
.2 _ 5 P1.5 HLD -Local bus hold
,.3 4 input/output signal
.4 3 P1.6 HLDA -Local bus hold
.5 2 acknowledge input
.6 1
P1.7 68
Port 2 1/0 Port 2 is an 8-bit quasi-bi-directionaII/O port. It also emits the high-
(AS-A15) - order 8 bits of address when accessing local expansion bus
P2.0 29 external memory (or during 87C452P programming and verification) .
.1 28 Port 2 can sink four LS TIL inputs .
.2 27
.3 25
.4 24
.5 23
.6 22
.7 21
Port 3 1/0 Port 3 is an 8-bit quasi-bi-directionaII/O port. It is also multiplexed
P3.0 67 with the interrupt, timer, local serial channel, RDI and WRI
.1 66 functions that are used by various options. The alternate functions
.2 65 can only be activated if the corresponding bit latch in the port SFR
.3 64- contains a 1. Otherwise, the port pin is stuck at O. Port 3 can sink
.4 63 four LS TIL inputs. The alternate functions assigned to the pins of
.5 62 Port 3 areas follows:
.6 61 Port Pin Alternate Function
P3.7 59 P3.0 RxD - Serial input port
P3.1 TxD - Serial output port
P3.2· INTO - Interrupt 0 Input
P3.3 INT1 - Interrupt 1 Input
P3.4 TO - Input to counter 0
P3.5 T1 - Input to counter 1
P3.6 WRI - The write control signal latches the
data from Port 0 outputs into the
External Data Memory on the
local bus.
P3.7 RDI - The read control signal latches the
data from Port 0 outputs on the
local bus.
10-164
intJ UPI·452
UPI·452 PIN DESCRIPTIONS (Continued)
Symbol Pin # Type Name and Function
Port 4 I/O Port 4 is an 8-bit quasi-bi-directionall/O port. Port 4 can sink/source
P4.0 30 four TIL inputs. It is also used as the control signals during EPROM
.1 31 programming and verification drive pins as follows:
.2 32 Port Pin Alternate Function
.3 33 P4.5 '1' during program and verify
.4 34 P4.6 '0' during program and verify
.5 35 P4.7 '0' during verify - used as output enable
.6 36 '1' during programming w/ ALE = 0
.7 37 Note: see Programming and Verification Characteristics in AC/DC
Specification section.
RST 20 I A high level on this pin for two machine cycles while the oscillator is
running resets the device. An internal pulldown resistor permits Power-
on reset using only a capacitor connected to Vee.
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members. This function has been transferred to
the Vee pin.
ALE/PGM 18 110 Provides Address Latch Enable output used for latching the address
into external memory during normal operation. Receives the program
pulse input during EPROM programming. ALE can sink/source eight LS
TIL inputs.
PSEN 19 0 The Program Store Enable output is a control signal that enables the
external Program Memory to the bus during normal fetch operation.
PSEN can sink/source eight LS TIL inputs.
EA 17 I When held at TIL high level, the UPI-452 executes instructions from the
internal ROM/EPROM when the PC is less than 8192 (8K, 2000H).
When held at a TTL low level, the UPI-452 fetches all instructions from
external Program Memory.
DBO 58 110 Host Bus Interface is an 8-bit bi-directional bus. It is used to transfer
DB1 57 data and commands between the UPI-452 and the host processor. This
DB2 56 bus can sink/source eight LS TIL inputs.
DB3 55
DB4 54
DB5 53
DB6 52
DB7 51
CS 44 I This pin is the Chip Select of the UPI-452.
AO 40 I These three address lines are used to interface with the host system.
A1 41 They define the UPI-452 operations. The interface is compatible with
A2 42 the Intel microprocessors and the MULTIBUS. .
READ 46 I This pin is the read strobe from the host CPU. Activating this pin causes
the UPI-452 to place the contents of the Output FIFO (either a
command or data) or the Host Status/Control Special Function Register
on the Slave Data Bus.
WRITE 47 I .This pin is the write strobe from the host. Activating this pin will cause
the value on the Slave Data Bus to be written into the register specified
by AO-A2.
DRaiN/ 49 0 This pin requests an input transfer from the host system whenever the
INTRalN Input Channel requires data.
DRaOUT/ 48 0 This output pin requests an output transfer whenever the Output
INTRaOUT Channel requires service. If the external host to UPI-452 DMA is
enabled, and a Data Stream Command is at the Output FIFO, DRaOUT
is deactivated and INTRa is activated (see 'GENERAL PURPOSE DMA
CHANNELS' section).
10-165
intJ UPI·452
UPI·452 PIN DESCRIPTIONS (Continued)
Symbol Pin # Type Name and Function
INTRQ 50 0 This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.
DACK 45 I This pin is the DMA acknowledge for the host bus interface Input
and Output Channels. When activated, a write command will cause
the data on th~ Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO). A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (+ 5V) in systems which do not
have a DMA controller (see Address Decoding).
VeelVpp 26 I + 5V power supply during operation. The Vee pin receives the
+ 12V EPROM programming and verification supply voltage.
ARCHITECTURAL OVERVIEW scription of the UPI-4S2's core CPU functional
blocks including;
- Timers/Counters
Introduction -I/O Ports
The UPI-452 slave microcontroller incorporates an - Interrupt timing and control (other than FIFO and
80C51 with double the program and data memory, a DMA interrupts)
slave interface which allows it to be connected di- - Serial Channel
rectly to the host system bus as a peripheral, a FIFO
buffer module, a two channel OMA processor, and a = Local Expansion Bus
fifth I/O port (Figure 3). The UPI-452 retains all of - Program/Data Memory structure
the 80C51 architecture, and is fully compatible with - Power-Saving Modes of Operation •
the MCS-51 instruction set.
- CHMOS Features
The Special Function Register (SFR) interface con- - Instruction Set
cept introduced in the MCS-51 family of .microcon-
trollers has been expanded in the UPI-452. To the • except 87C452P piggyback package
20 Special Function Registers of the MCS-51, the
UPI-452 adds 34 more. These additional Special Figure 3 contains a'conceptual block diagram of the
Function Registers, like those of the MCS-5.1, pro- UPI-452. Figure 4 provides a functional block dia-
vide access to the UPI-452 functional elements in- gram.
cluding the FIFO, DMA and added interrupt capabili-
ties. Several of the 80C51 core Special Function
Registers have also been expanded to support add- FIFO Buffer Interface
ed features of the UPI-4S2.
A unique feature of the UPI-452 is the incorporation
This data sheet describes the unique features of the of a 128 byte FIFO array at the host-slave interface.
UPI-452. Refer to the 80C51 data sheet for a de- The FIFO allows asynchronous bi-directional trans-
fers between the host CPU and the internal CPU.
231428-7
Figure 3. UPI-452 Conceptual Block Diagram
10-166
UPI·452
F-.?"=:::":"; ADDITIONAL FEATURES: I
-SERIAL CHANNEL I
-EXTERNAL INTERRUPTS I
~~~~ . :~~g{~~~~~~SION
BUS
-RD
-WR
-EXTERNAL
COUNTER INPUT
-EPROM PROGRAM
AND VERIFY
~ _ ..c~~~O_L __ • ___ _
231428-8
Figure 4. UPI-452 Functional Block Diagram
The division of the 128 bytes between Input and nel Boundary Pointer (CBP) SFR. This register con-
Output channels is user programmable allowing tains the number of address locations assigned to
maximum flexibility. If the entire 128 byte FIFO is the Input channel. The remaining address locations
allocated to the Input channel, a high performance are automatically assigned to the Output FIFO. The
Host can transfer up to 128 bytes at one time, then CBP SFR can only be programmed by the internal
dedicate its resources to other functions while the CPU during FIFO DMA Freeze Mode (See FIFO-Ex-
internal CPU processes the data in the FIFO. Vari- ternal. Host Interface FIFO DMA Freeze Mode de-
ous handshake signals allow the external Host to scription). The CBP is initialized to 40H (64 bytes)
operate independently and without frequent monitor- upon reset.
ing of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the The number in the Channel Boundary Pointer SFR is
same order that it was sent by the host without the actually the first address location of the Output
need to keep track of addresses. Three slave bus FIFO. Writing to the CBP SFR reassigns the Input
interface handshake methods are supported by the and Output FIFO address space. Whenever the CBP
UPI-452: DMA, Interrupt and Polled. is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
The FIFO is nine bits wide. The ninth bit acts as a the CBP SFR.
command/data flag. Commands written to the FIFO
All of the FIFO space may be assigned to one chan-
by either the host or internal CPU are called Data
nel. In such a situation the other channel's data path
Stream Commands or DSCs. DSCs are written to
consists of a single SFR (FIFO IN/COMMAND IN or
t~e input FIFO by the Host via a unique external
FIFO OUT/COMMAND OUT SFR) location. .
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Func- CBP InputF.IFO Output FIFO
tion Register (SFR). When encountered by the host Register Size Size
or internal CPU a Data Stream Command can be 0 1 128
used as an address vector to user defined service 1 1 128
routines, DSCs provide synchronization of data and 2 2 126
commands between the Host and internal CPU. 3 3 125
4 4 124
FIFO PROGRAMMABLE FEATURES •
7B 123
• •
5
7C 124 4
Size of Input/Output Channels 7D 125 3
7E 128 1
The 128 bytes of FIFO space can be allocated be- 7F 128 1
tween the Input and Output channels via the Chan-
10-167
UPI-452
FIFO Read/Write Pointers of the three·writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memo-
These normally operate in auto-increment (and auto- ry and the Special Function Register array. The Spe-
rollover) mode, but can be reassigned by the internal cial Function Register array appears as a set of
CPU during FIFO DMA Freeze Mode (See FIFO-Ex- unique dedicated memory addresses which may be
ternal Host Interface FIFO DMA Freeze Mode de- used as either the source or destination address of a
scription). . DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Reg-
isters for mode, source and destination addresses,
Threshold Register and byte count to be transferred. Each DMA channel
has four programmable modes: .
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input - Alternate Cycle Mode
FIFO to generate a Host interrupt. The Output FIFO --, Burst Mode
Threshold SFR' contains the number of bytes, data - FIFO or Serial Channel Demand Mode
and/or DSC(s), that must be in the FIFO before an
interrupt is generated. The Threshold feature pre- - External Demand Mode
vents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data. The A complete description of each mode and DMA op-
thresholds, therefore, allow the FIFO's operation to eration m~y be found in the section titled "General
be adjusted to the speed of the Host, optimizing the Purpose DMA Channels".
overall interface performance.
FIFO/SLAVE INTERFACE
Immediate Commands FUNCTIONAL DESCRIPTION
The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the Overview
external Host and internal CPU called Immediate
C-ommends. As the name implies, an !mmediate. The FIFO is a 128 Bvte RAM arrav with recirculatina
Command is available to the receiving'CPU immedi- pointers to manage- the read and write accesseS.
ately, via an interrupt, without being entered into the The FIFO consists of an Input and an Output chan-
FIFO as are Data Stream Commands. Like Data nel. Access cycles to the FIFO by the internal CPU
Stream Commands, Immediate Commands are writ- and external Host are interleaved and appear to be
ten either via a unique external address by the host occurring concurrently to both the internal CPU and
CPU, or via dedicated SFR by the internal CPU. external Host. Interleaving access cycles ensures
efficient use of this shared resource. The internal
The DSC and/or Immediate Command interface CPU accesses the FIFO in the same way it would
may be defined as either Interrupt or Polled under access any of the Special Function Registers e.g.,
user program control via the Interrupt Enable (IE), direct and register indirect addressing as well as ar-
Slave Control Register (SLCON), and, Interrupt En- ithmetric and logical instructions.
able Priority (IEP) Special Function Registers, for the
internal CPU and via the Host Control SFR for the.
external Host CPU. Input FIFO Channel
The. Input FIFO Channel provides for data transfer
DMA from the external Host to the internal CPU (Figure 5).
The registers associated with the Input Channel dur-
The UPI-452 contains a two channel internal DMA ing normal operation are listed in Table 1*.
controller which allows transfer of data between any
Table 1. Input FIFO Channel Registers'
Register Name Description
1) Input Buffer Latch Host CPU Write only
2) FIFO IN SFR Internal CPU Read only
3) COMMAND IN SFR Internal CPU Read only
4) Input FIFO Read Pointer SFR Internal CPU Read only
.5) Input FIFO Write Pointer SFR Internal CPU Read only
6) Input FIFO Threshold SFR Internal CPU Read only
.. ..
'See "'FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode SFR charactenstlcs deSCription .
10-168
inter UPI-4S2
EXTERNAL HOST
CPU
EXTERNAL
ADDRESS HOST DATA
BUS
INPUT WRITE
POINTER (IWPR)
!::
ID
THRESHOLD SFR INPUT FIFO
(ITHR) i!:
'"
z
INPUT READ
POINTER (IRPR)
231428-9
Figure 5. Input FIFO Channel Functional Block Diagram
The host CPU writes data and Data Stream Com· The Inl'lut FIFO Channel addressing is controlled by
mands into the Input Buffer Latch on the rising edge the Input FIFO Read and Write Pointer SFRs. These
of the external WR signal. External addressing de· SFRs are read only registers during normal opera·
termines whether the byte is a data byte or Data tion. However, during FIFO DMA Freeze Mode (See
Stream Command and the FIFO logic sets the ninth FIFO·External Host Interface FIFO DMA Freeze
bit of the FIFO accordingly as the byte is moved Mode description),. the internal CPU has write ac-
from the Input Buffer Latch into the FIFO. A "1" in cess to them. Any write to these registers in normal
the ninth bit indicates that the incoming byte is a mode will have no effect. The Input Write Pointer
Data Stream Command. The internal CPU reads SFR contains the address location to which datal
data bytes via the FIFO IN SFR, and Data Stream commands are written from the Input Buffer Latch.
Commands via the COMMAND IN SFR. The write pointer is automatically incremented after
each write and is reset to zero if equal to the CBP,
A Data Stream Command will generate an interrupt as the- Input FIFO operates as a circular buffer.
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can If a write is performed on an empty FIFO, the first
then be read via the COMMAND IN SFR. Data can byte is also written into the FIFO IN or COMMAND
only be read via the FIFO IN SFR and Data Stream IN SFR. If the Host continues writing while the Input
Commands via the COMMAND IN SFR. Attempting FIFO is full, an external interrupt, if enabled, is sent
to read Data Stream Commands as data by address· to the host to Signal the overrun condition. The
ing the FIFO IN SFR will result in '~OFFH" being writes are ignored by the FIFO control logic. Similar·
read, and -the Input FIFO Read Pointer will remain Iy, an internal CPU read of an empty FIFO will cause
intact. (This prevents accidental misreadin,9 of Data an underrun error interrupt to be generated to the
Stream Commands.) Attempting to read data as internal CPU and a value of "OFFH" will be read by
Data Stream Commands will have the same conse· the internal CPU.
quence.
10·169
UPI-452
The Read Pointer SFR holds the address of the next number of bytes assigned to the Input FIFO (CBP)
byte to be read from the Input FIFO. An Input FIFO minus the number of bytes programmed in the Input
read operation post-increments the Input Read FIFO Threshold SFR. With this feature the Host is
Pointer SFR and loads a new data byte into the assured that it can write at least a threshold number
FIFO IN SFR or a Data Stream Command into the of bytes to the Input FIFO channel without worrying
COMMAND IN SFR at the end of the read cycle. about an overrun condition. Once the Request for
Service is generated it remains active until the Input
An Input FIFO Request for Service (via DMA, Inter- FIFO becomes full.
rupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a "threshold" value Output FIFO Channel
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Thresh- The Output FIFO Channel provides data transfer
old SFR can be from 0 to (CBP-2). The Request for from the UPI-452 internal CPU to the external Host
Service Interrupt is generated only after the Input (Figure 6).
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total' The registers associated with the Output Channel
during normal operation are listed in Table 2*.
231428-10
Figure 6. Output FIFO Channel Functional Block Diagram
Table 2. Output FIFO Channel Registers
Register Name Description
1) Output Buffer Latch Host CPU Read only
2) FIFO OUT SFR Internal CPU Read and Write
3) COMMAND OUT SFR Internal CPU Read and Write
4) Output FIFO Read Pointer SFR Internal CPU Read only
5) Output FIFO Write Pointer SFR Internal CPU Read only
6) Output FIFO Threshold SFR Internal CPU Read only
'See "'FIFO·EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE"' section for FIFO DMA Freeze Mode register characteristics description.
10-170
inter UPI-4S2
The UPI-452 internal CPU transfers data to the Out- 2.) The second type of Request for Service is called
put FIFO via the FIFO OUT SFR and commands via "Flush Mode" and occurs when the internal CPU
the COMMAND OUT SFR. If the byte is written to writes a Data Stream Command into the Output
the COMMAND OUT SFR, the ninth bit is automati- FIFO. Its purpose is to ensure that a data block
cally set (= 1) to indicate a Data Stream Command. entered into the Output FIFO, which is less than
If the byte is written to the FIFO OUT SFR the ninth the programmed threshold, will generate a Re-
bit is cleared (=0). Thus the FIFO OUT and COM- quest for Service interrupt, if enabled, and be
MAND OUT SFRs are the same but the address de- read, or "Flushed" from the Output FIFO, by the
termines whether the byte entered in the FIFO is a external host CPU regardless of the status of the
DSC or data byte. OTHR SFR.
The Output FIFO preloads a byte into the Output
Buffer Latch. When the Host issues a RD/ signal, Immediate Commands
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the Immediate Commands provide direct communica-
Output Buffer Latch, a flag is set and an interrupt, if tion between the external Host and UPI-452. Unlike
enabled, is generated if the byte is a DSC (ninth bit Data Strearri Commands which are entered into the
is set). The operation is carefully timed such that an FIFO, the Immediate Command is available to the
interrupt can be generated in time for it to be recog- receiving CPU directly, bypassing the FIFO. The Im-
nized by the Host before its next read instruction. mediate Command can serve as a program vector
Internal CPU write and external Host read opera- pOinting into a jump table in the recipients software.
tions are interleaved at the FIFO so that they appear Immediate Command Interrupts are generated, if en-
to be occurring concurrently. abled, and a bit in the appropriate Status Register is
set when an Immediate Command is input or output.
The Output FIFO read and write pointer operation is A similar bit is provided to acknowledge when an
the same as for the Input Channel. Writing to the Immediate Command has been read and whether
FIFO OUT or COMMAND OUT SFRs will increment the register is available to receive another com-
the Output Write Pointer SFR but reading from it will mand. The bits are reset when the Immediate Com-
leave the write pointer unchanged. A rollover of the mands are read. Two Special Function Registers are
Output FIFO Write Pointer causes the pointer to be dedicated to the Immediate Command interface. Ex-
reset to the value in the Channel Boundary Pointer ternal addressing determines whether the Host is
(CBP) SFR. . accessing the Input FIFO or the Immediate Com-
mand IN (IMIN) SFR. The internal CPU writes Imme-
If the external host attempts to read a Data Stream diate Commands to the Immediate Command OUT
Command as a data byte it will result ,in invalid data (IMOUT) SFR.
(OFFH) being read. The DSC is not lost because the
invalid read does not increment the pointer. Similarly Both processors have the ability to enable or disable
attempting to read a data byte as a Data Stream Immediate Command Interrupts. By disabling the in-
Command has the same result. terrupt, the recipient of the Immediate Command
can poll the status SFR and read the Immediate
A Request for Service is generated to the external Command at its convenience. Immediate Com-
Host under the following two conditions: mands should only be written when the appropriate
1.) Whenever the internal CPU has written a thresh- Immediate Command SFR is empty (as indicated in
the appropriate status SFR:HSTAT/SSTAT). Simi-
old number of bytes or more intothe Output FIFO
(threshold = (OTHR) + 1). The threshold num- larly, the Immediate Command SFR should only be
ber should be chosen such that the bus latency read when there is data in the Register.
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU The flowcharts in Figure 7a and 7b illustrate the
side. The threshold limit should be large enough proper handshake mechanisms between the exter-
to make a bus request by the UPI-452 to the ex- nal Host and internal CPU when handling Immediate
ternal host CPU worthwhile. Once a request for Commands.
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 1 to the Output FIFO Size. The
threshold number can be programmed via the
OTHR SFR.
10-171
infef UPI-4S2
r----------------
SET SET
a
\:V
,
.oil
GENERATES INTERRUPT
....
GENERATES
TO INTE.RNAL CPU INTERRUrT TO HOST
, ,
,,
) )
• 4
SET SET
a
\:V
, ,
.oil .oil
GENERATES GENERATES INTERRUPT
INTERRUPT TO HOST TO INTE.RNAL CPU
,, ,,
-----------------~
... _-----
231428-12
231428-11
Figure 7a. Handshake Mechanisms for Handling Figure 7b. Handshake Mechanisms for Handling
Immediate Command IN Flowchart Immediate Command OUT Flowchart
10-172
inter UPI-4S2
HOST & SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers:
1) Mode Special Function Register (MODE)
2) Slave Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAT)
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit. Only the
Slave Control Register (SLCON) is bit addressable.
1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface. It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU.
The MODE SFR can be directly modified by the internal CPU through direct address instructions. It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command, either Immediate or DSC, to vector to that routine.
Symbolic Physical
Address Address
MODE MD6 MD5 MD4 OF9H
(MSB) (LSB)
Status On Reset:
1" o o o 1* 1"
MD7 (reserved)"'
MD6 Request for Service to external CPU via;
1 = DMA (DRQIN/DRQOUT) request to external host when the Input or Output FIFO channel re-
quests service
o = Interrupt (INTRQIN/INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I/O Buffer Latch
MD5 Configure DRQIN/INTRQIN and DRQOUT/INTRQOUT to be either;
1 = Enable (Actively driven)
o= Disable (Tri-state)
MD4 Configure INTRQ to be either;
1 = Enable (Actively driven)
o= Disable (Tri-state)
MD3 (reserved)' *
MD2 (reserved)"
MD1 (reserved)"
MDO (reserved)"
2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface. All interrupts are to the internal
CPU.
10-173
inter UPI-452
Symbolic Physical
Address Address
SLCON IFI OFI ICII I' ICOI FRZ IFRS ·OFRS OE8H
(MSB) (LSB)
Status On Reset:
o o o o o 1" o o
IFI Enable Input FIFO Interrupt (due to Underrun Error Condition, Data Stream Command or Request
Service)
1 = Enable
0= Disable
OFI Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service)
1 = Enable
0= Disable
Note: If the DMA ill configured to service a FIFO demand, then the Request for Service Interrupt is
not generated.
ICII Generate Interrupt when a command is written to the Immediate Command in Register
1 = Enable
0= Disable
ICOI Generate Interrupt when Immediate Command Out Register is Available
1 = Enable
0= Disable
FRZ Enable FIFO DMA Freeze Mode
1 = Normal operation
o = FIFO DMA Freeze Mode
SC2 (reserved) ••
IFRS Input FIFO Channel Request for Service
1, = Request when Input FIFO not empty
o = Request when Input FIFO full
OFRS Output FIFO Channel Request for Service
1 = Request when Output FIFO not full
o = Channel Request when Output FIFO empty
NOTES:
°A '1' will be read from all SFR reserved locations except HCON SFR,HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.
3) Slave Status SFR (SSTAT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface. It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action.
Symbolic Physical
Address Address
, SSTAT OE9H
o o o
(MSB) (LSB)
10-174
inter UPI-452
SST7 Output FIFO Overrun Error Condition
1 = No Error
o= Error (latched until Slave Status SFR is read)
SSTS Immediate Command Out Register Status
1 = Full (Le. Host CPU has not read previous Immediate Command Out sent by internal CPU)
0= Available
SST5 FIFO DMA Freeze Mode Status
1 = Normal Operation
o= FIFO DMA Freeze Mode in Progress
SST4 Output FIFO Request for Service Flag
1 = Output FIFO does not request service
o= Output FIFO requests service
SST3 Input FIFO Underrun Error Condition Flag
1 = No Underrun Error
o= Underrun Error (latched until Slave Status SFR is read)
SST2 Immediate Command In SFR Status
1 = Empty
o= Immediate Command received from host CPU
SST1 Data Stream Command/Data at Input FIFO Flag
1 = Data (not DSC)
o= DSC (at COMMAND IN SFR)
SSTO Input FIFO Request For Service Flag
1 = Input FIFO Does Not Request Service
o= Input FIFO Request for Service
EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs:
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands. The protocol for implementing this is entirely determined by the user.
1) Host Control SFR (HCON)
By writing to the Host Control SFR, the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452.
Symbolic Physical
Address Address
HCON HC7 HCS HC5 HC4 HC3 HC1 OE7H
(MSB) (LSB)
Status On Reset:
0 0 0 0 0 O' 0 O'
10-175
intJ UPI-452
HC7 Enabie Output FIFO Interrupt due to Underrun Error Condition, Data Stream Command or Service
Request
1 = Enable
0= Disable
HC6 Enable Input FIFO Interrupt due to Overrun Error Condition, or Service Request
1 = Enable
0= Disable
HCS Enable the generation of the Interrupt due to Immediate Command Out being present
1 = Enable
0= Disable
HC4 Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate
Command byte
1 = Enable
o = Disable
HC3 Reset UPI-4S2
1 = Software RESET
o = Normal Operation
HC2 (reserved)"
HC1 Select between INTRQ and INTRQINIINTRQOUT as Request for.5ervice interrupt signal when DMA is
disabled .
1 = INTRQ
o= INTRQIN or INTRQOUT
HCO (reserved)"
. NOTES:
'A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.
2) Host Status SFR (HSTAT)
The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the
source of an external interrupt during polling. Like the Slave Status SFR, the Host Status SFR reflects the
current status of the FIFO-external host interface. ..
Symbolic Physical
Address Address
HSTAT OE6H
- Output FIFO Status -+
Status On Reset:
1/0'
(MSB) (LSB)
10-176
infef UPI-4S2
HST7 Output FIFO Underrun Error Condition FIFO MODULE - EXTERNAL HOST
1 = No Underrun Error
INTERFACE
o = Underrun Error (latched until Host
Status Register is read)
Overview
HST6 Immediate Command Out SFR Status
1 = Empty The FIFO-external Host interface supports high
o = Immediate Command Present speed asynchronous bi-directional 8-bit data trans-
fers. The host interface is fully compatible with Intel
HST5 Data Stream Command/Data at Output microprocessor local busses and with MULTIBUS.
FIFO Status The FIFO has two specialized DMA request pins for
1 = Data (not DSC) Input and Output FIFO channel DMA requests.
o = DSC (present at Output FIFO COM- These are multiplexed to provide a dedicated Re-
MAND OUT SFR) quest for Service interrupt (DRQINIINTRQIN,
(Note: Only if HST4 = 0, if HST4 = 1 then un- DRQOUT /INTRQOUT).
determined)
The external Host can program, under user defined
HST4 Output FIFO Request for Service Status
1 = No Request for Service protocol, thresholds into the FIFO Input and Output
o = Output FIFO Request for Service due to: Threshold SFRs which determine when the FIFO
Request for Service interrupt is generated to the
a. Output FIFO containing the threshold Host CPU. The FIFO module external Host interface
number of bytes or more is configured by the internal CPU via the MODE
b. Internal CPU sending a block of data ter- SFR. "The external Host can enable and disable
minated by a DSC (DSC Flush Mode) Host interface interrupts via the Host Control SFR."
HST3 Input FIFO Overrun Error Condition Data Stream Commands in the Input FIFO channel
1 = No Overrun Error allow the Host to influence the processing of data
o = Overrun Error (latched until Host Status blocks and are sent with the data flow to maintain
Register is read) synchronization. Data Stream Commands in the
Output FIFO Channel allow the internal CPU to per-
HST2 Immediate Command In SFR Status form the same function, and also to set the Output
1 = Full (i.e. Internal CPU has not read pre- FIFO Request Service status logic to the host CPU
vious Immediate Command sent by Host) regardless of the programmed value in the Thresh-
o = Empty old SFR.
* Reset value;
'1' - if read by the external Host Slave Interface Address Decoding
'0' - if read by internal CPU (reads shadow The UPI-452 determines the desired Host function
latch - see FIFO DMA Freeze Mode descrip- through address decoding. The lower three bits of
tion) the address as well as the READ, WRITE, Chip Se-
lect (CS) and DMA Acknowledge (DACK) are used
HST1 FIFO DMA Freeze Mode Status
1 = Freeze Mode in progress. for decoding. Table 3 shows the pin states and the
(In Freeze Mode, the bits of the Host Status Read or Write operations associated with each con-
SFR are forced to a '1' initially to prevent the figuration.
external Host from attempting to access the
FIFO. The definition of the Host Status SFR Interrupts to the Host
bits during FIFO DMA Freeze Mode can be The UPI-452 interrupts the external Host via the
found in FIFO DMA Freeze Mode descrip- INTRQ pin. In addition, the DRQIN and DRQOUT
tion) pins can be multiplexed as interrupt request lines,
o = Normal Operation INTRQIN and INTRQOUT respectively, when DMA
HSTO Input FIFO Request Service Status is disabled. This provides two special FIFO "Re-
1 = Input FIFO does not request service quest for Service" interrupts.
o = Input FIFO request service due to the
Input FIFO containing enough space for the There are eight FIFO-related interrupt sources; two
host to write the threshold number of bytes from The Input FIFO; three from The Output FIFO;
or more one from the Immediate Command Out SFR; one
from the Immediate Command IN SFR; and one due
to FIFO DMA Freeze Mode.
INPUT FIFO: The Input FIFO interrupt is generated
whenever:
a. The Input FIFO contains space for a threshold
number of bytes.
10-177
intJ UPI·452
Table 3. UPI·452 Address Decoding
DACK CS A2 A1 AD Read Write
1 1 X X X No Operation No Operation
1 0 0 0 0 Data or DMA from Output FIFO Channel Data or DMA to Input FIFO Channel
1 0 0 0 1 Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel
1 0 0 1 0 Host Status SFR Read Reserved
1 0 0 1 1 Host Control SFR Read Host Control SFR Write
1 0 1 0 0 Immediate Command SFR Read Immediate Command to SFR Write
1 0 1 1 X Reserved Reserved
0 X X X X DMA Data from Output FIFO Channel DMA Data to Input FIFO Channel
1 0 1 0 1 Reserved Reserved
NOTES:
1. Attempting to read a DSC as a data byte will result in invalid data being read. The read pointers are not incremented so
that the DSC is not lost. Attempting to read a data byte as a DSC has the same result.
2. If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MD6) in the MODE SFR. Care should be taken when using DACK. For proper operation, DACK must be driven
high (+5V) when not using DMA.
b. When an Input FIFO overrun error condition ex- b. An Immediate Command IN interrupt is generat-
ists. The appropriate bits in the Host Status SFR ed, if enabled, to the Host when the internal CPU
are set and the interrupt is generated only if en- has read a byte from the Immediate Command IN
abled. (IMIN) SFR. The read operation clears the Host
Status SFR Immediate Command IN Status bit
OUTPUT FIFO: The Output FIFO Request for S'erv- (HSTAT HST2) indicating that the' Immediate
jt"'o Intorr'l""t ,,"t"\,...,+,...,.. in ... ,..i ...... il,.. ........ _""" ......... _ ... +UIG
........ I_
..... ..., I I . "...... U ....... ...,t'vl~U.Q~ III CI .:Jlllllial IllClr II 10' Qo:t 111-
Comrnand iN SFR is empty. The corresponding
put FIFO interrupt: Slave Status (SSTAT) SFR bit is also set to indi-
a. When the FIFO contains the threshold number of cate an empty status. Setting the Slave Status
bytes or more. SFR bit generates a FIFO-Slave Interface inter-
rupt, if enabled, to the internal CPU. (See Figure
b. Output FIFO error condition interrupts are gener-
7a, Immediate Command IN Flowchart.)
ated when the Output FIFO is underrun.
c. Data Stream Command present in the Output NOTE:
Buffer Latch. ' Immediate Command IN and OUT interrupts are ac-
tually specific Request For Service interrupts to the
A Data Stream Command interrupt is used to halt
Host.
normal processing, using the command as a vector
to a service routine. When DMA is disabled, the user
FIFO DMA FREEZE MODE: When the internal CPU
may program (through HC1) INTRa to include FIFO
invokes FIFO DMA Freeze Mode, for example at re-
Request for Service Interrupts or use INTRalN and
set or to reconfigure the FIFO interface, INTRa is
INTRaOUT as Request for Service Interrupts.' ,
activated. The INTRa can only be deactivated by
IMMEDIATE COMMAND INTERRUPTS: the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
a. An Immediate Command Out Interrupt is generat- is disabled by the internal CPU).
ed, if enabled, to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared, Once an interrupt is generated, INTRa will remain
when the internal CPU writes to the Immediate high until no interrupt generating condition exists.
Command OUT (IMOUT) SFR. When the Host For a FIFO underrun/overrun error interrupt, the in-
reads the Immediate Command OUT (IMOUT) terrupt condition is deactivated by the external Host
SFR the corresponding" bit in the Host Status reading the Host Status SFR. An interrupt is serv-
(HSTAT) SFR is set. This causes the Slav,e Status iced by reading the Host Status SFR to determine
Immediate Command OUT Status bit (SSTAT the source of the interrupt and vectoring the appro-
SST6) to be cleared indicating that the Immediate priate service routine.
Command OUT (IMOUT) SFR is empty. If en-
abled, a FIFO-Slave Interface will also begener-
ated to the internal CPU. (See Figure 7b, Immedi-
ate Command OUT Flowchart.)
10-178
UPI-4S2
DMA Requests to the Host nation via the DMAO/DMA 1 Source Address or Des-
tination Address Special Function Registers. The
The UPI-452 generates two DMA requests, DRQIN FIFO module manages the transfer of data between
and DRQOUT, to facilitate data transfer between the the external host and FIFO SFRs.
Host and the Input and Output FIFO channels. A
DMA acknowledge, DACK, is used as a chip select
and initiates a data transfer. The external READ and Internal CPU Access to FIFO Via
WRITE signals select the Input and Output FIFO re- Software Instructions
spectively. The CS and address lines can also be
used as a DMA acknowledge for processors with The internal CPU has access to the Input and Out-
onboard DMA controllers which do not generate a put FIFOs via the FIFO IN/COMMAND IN and FIFO
DACK signal. OUT/COMMAND OUT SFRs which reside in the
Special Function Register Array. At the end of every
The internal CPU can configure the UPI-452 to re- instruction that involves a read of the FIFO IN/COM-
quest service from the external host via DMA or in- MAND IN SFR, the SFR is written over by a new
terrupts by programming Mode SFR MD6 bit. In ad- byte from the Input FIFO channel when available. At
dition the external Host enables DMA requests the end of every instruction that involves a write to
through bits 6 and 7 of the Host Control SFR. When the FIFO OUT/COMMAND OUT SFR, the new byte
a DMA request is invoked the number of bytes trans- is written into the Output FIFO channel and the write
ferred to the Input FIFO is the total number of bytes pointer is incremented after the write operation (post
in the Input FIFO (as determined by the CBP SFR) incremented).
minus the value programmed in the Input FIFO
Threshold SFR. The DMA request line is activated The internal CPU reads the Input FIFO by using the
only when the Input FIFO has a threshold number of FIFO IN/COMMAND IN SFR as the source register
bytes that can be transferred. in an instruction. Those instructions which read the
Input FIFO are listed below:
The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a ADD A,FIFO IN/COMMAND IN
less than threshold size block of data (Flush Mode) AD DC A,FIFO IN/COMMAND IN
or when the Output FIFO threshold is reached. The PUSH FIFO IN/COMMAND IN
request remains active until the Input FIFO becomes
ANL A,FIFO IN/COMMAND IN
full or the Output FIFO becomes empty. If a DSC is
encountered during an Output FIFO DMA transfer, ORL A,FIFO IN/COMMAND IN
the DMA request is dropped until the DSC is read. XRL A,FIFO IN/COMMAND IN
The DMA request will be reactivated after the DSC is CJNE A,FIFO IN/COMMAND IN, rei
read and remains active until the Output FIFO be-
SUBB A,FIFO IN/COMMAND IN
comes empty or another DSC is encountered.
MOV direct,FIFO IN/COMMAND IN
MOV @Ri,FIFO IN/COMMAND IN
FIFO MODULE - INTERNAL CPU MOV Rn,FIFO IN/COMMAND IN
INTERFACE MOV A,FIFO IN/COMMAND IN
After each access to these registers, they are over-
Overview written by a new byte from the FIFO.
The Input and Output FIFOs are accessed by the
NOTE:
internal CPU through direct addressing of the FIFO
Instructions which use the FIFO IN or COMMAND
IN/COMMAND IN and FIFO OUT/COMMAND OUT
IN SFR as both a source and destination register
Special Function Registers. All of the 80C51 instruc-
will have the data destroyed as the next data byte
tions involving direct addressing may be used to ac-
is rewritten into the FIFO IN register at the end of
cess the FIFO's SFRs. The FIFO IN, COMMAND IN
the instruction. These instructions are not support-
and Immediate Command In SFRs are actually read
ed by the UPI-452 FIFO. Data can only be read
only registers, and their Output counterparts are
through the FIFO IN SFR and DSCs through the
write only. Internal DMA transfers data between In-
COMMAND IN SFR. Data read through the COM-
ternal memory, External Memory and the Special
MAND IN SFR will be read as OFFH, and DSCs
Function Registers. The Special Function Registers
read through the FIFO IN SFR will be read as
appear as another group of dedicated memory ad-
OFFH. The Immediate Command in SFR is read
dresses and are programmed as the source or desti-
with the same instructions as the FIFO IN and
COMMAND IN SFRs.
10-179
inter UPI-4S2
The FIFO IN, COMMAND IN and Immediate Com- dress Register (DAR). (Note: Since the FIFO IN SFR
mand In SFRs are read only registers. Any write op- is a read only register, the DMA transfer will be ig-
eration performed on these registers will be ignored nored if it is used asa DMA DAR. This is also true if
and the FIFO pOinters will remain intact. the FIFO OUT SFR is used as a DMA SAR.)
The internal CPU uses the FIFO OUT SFR to write Each DMA channel is software programmable to op-
to the Output FIFO and any instruction which uses erate in either Block Mode or Demand Mode. In the
the FIFO OUT or COMMAND OUT SFR as a desti- Block Mode, DMA transfers can be further .pro-
nation will invoke a FIFO write. DSCs are differenti- grammed to take place in Burst Mode or Alternate
ated from data by writing to the COMMAND OUT Cycle mode. In Burst Mode, the processor halts its
SFR. In the FIFO, Data Stream Commands have the execution and dedicates its resources to the DMA
ninth bit assoCiated with the command byte set to transfer. In Alternate Cycle Mode, DMA cycles and
"1". The instructions used to write to the Output instruction cycles occur alternately.
FIFO are listed below:
In Demand Mode, a DMA transfer occurs only when
MOV FIFO OUT /COMMOUt, A it is demanded. Demands can be accepted from an
MOV FIFO OUT/COMMOUT, direct external device (through External Interrupt pins,
. MOV FIFO OUT /COMMOUT, Rn EXTO/EXT1) or from either the Serial Channel or
POP FIFO OUT /COMMOUT FIFO flags. In this way, a DMA transfer can be syn-
chronized to an external device, the FIFO or the Se-
MOV FIFO OUT/COMMOUT, #data rial Port. If the External Interrupt is configured in
MOV FIFO OUT/COMMOUNT, @Ri Edge Mode, a single byte transfer occurs per tran-
sition. The external interrupt itself will occur if en-
NOTE: abled. If the External Interrupt is configured in Level
Instructions which use the FIFO OUT/COMMAND Mode, DMA transfers continue until the External In-
OUT SFRs as both a source and destination regis- terrupt request goes inactive or the byte count be-
ter cause invalid data to be written into the Output comes zero. The following flags activate Demand
'FIFO. These instructions are not supported by the Mode transfers of one byte to/from the FIFO or Seri-
UPI-4S2 FIFO. al Channel:
RI - Serial Channel Receiver Buffer Full
GENERAL PURPOSE DMA CHANNELS TI - Serial Channel Transm!tter Buffer Empty
Overview Architecture
There are two identical General Purpose DMA Chan- There are three 16 bit and one 8 bit Special Function
nels on the UPI-4S2 which allow high speed data Registers associated with each DMA channel.
transfer from one writeable memory space to anoth- • The 16 bit Source Address SFR (SAR) points to
er. As many as 64K bytes can be transferred in a the source byte.
single DMA operation. The following memory
spaces can be used with DMA channels: • The 16 bit Destination Address SFR (DAR) points
to the destination.
• Internal Data Memory
• The 16 bit Byte Count SFR (BCR) contains the
• External Data Memory number of bytes to be transferred and is decre-
• Special Function Registers mented when a byte transfer is accomplished.
• The DMA Control SFR (DCON) is eight bits wide
The Special Function Register array appears as a and specifies the source memory space, destina-
limited group of dedicated memory addresses. The tion memory space and the mode of operation.
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the In Auto Increment mode, the Source Address and/
sourCe or destination address. The Special Function or Destination Address is incremented when a byte
Registers which may be used in DMA transfers are is transferred. When a DMA transfer is complete
listed in Table 4. Table 4 also shows whether the (BCR = 0), the DONE bit is set and a maskable
SFR may be used as Source or Destination only, or interrupt is generated. The GO· bit must be set to
both. . . start any DMA transfer (also, the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freeze
The FIFO can be accessed during DMA by using the Mode). The two DMA channels are deSignated as
FIFO IN SFR as the DMA Source Address Register DMAO and DMA 1, and their corresponding registers
(SAR) or the FIFO OUT SFR as the Destination Ad- are suffixed by 0 or 1; e.g. SARO, DAR 1, etc.
10-1BO
UPI-4S2
Table 4 DMA Accessible Special Function Registers
Source Destination
SFR Symbol Address Either
Only Only
Accumulator AlACC OEOH Y
B Register B OFOH Y
FIFO IN FIN OEEH Y
COMMAND IN CIN OEFH Y
FIFO OUT FOUT OFEH Y
COMMAND OUT COUT OFFH Y
Serial Data Buffer SBUF 099H Y
PortO PO 080H Y
Port 1 P1 090H Y
Port 2 P2 OAOH Y
Port 3 P3 OBOH Y
Port 4 P4 OCOH Y
DMA Special Function Registers
DMA Control SFR: DCONO, DCON1
Symbolic Physical
Address Address
DCONO 092H
DCON1 093H
Reset Status: DCONO and DCON1 = OOH
Bit Definition:
DAS IDA Destination Address Space
0 0 External Data Memory without Auto-Increment
0 1 External Data Memory with Auto-Increment
1 0 Special Function Register
1 1 Internal Data Memory
SAS ISA Source Address Space
0 0 External Data Memory without Auto-Increment
0 1 External Data Memory with Auto-Increment
1 0 Special Function Register
1 1 Internal Data Memory
DM TM DMA Transfer Mode
0 0 Alten1ate-Cycle Transfer Mode
0 1 Burst Transfer Mode
1 0 FIFO or Serial Channel Demand Mode
1 1 External Demand Mode
10-181
intJ UPI-452
DONE DMA transfer Flag: service request is generated. DMA transfer cycles
are alternated with instruction execution cycles.
o .DMA transfer .is not completed. DMA transfers are terminated as in FIFO Demand
DMA transfer is complete. Mode.
NOTE:
This flag is set when contents of the Byte Count Output Channel
SFA decrements to zero. It is reset automatically The DMA is configured as in FIFO Demand Mode
when the DMA vectors to its interrupt routine. and transfers are initiated whenever an Output FIFO
GO Enable DMA Transfer: requests service. DMA transfer cycles are alternated
with instruction execution cycles. DMA transfers are
o Disable DMA transfer (in all modes). terminated as in FIFO Demand Mode.
Enable DMA transfer. If the DMA is in
the Block mode, start DMA transfer if The FIFO logic resets the interrupt flag after trans-
possible. If it is in the Demand mode, ferring the byte, so the interrupt is never generated.
enable the channel and wait for a de-
mand. . Once the DMA is programmed to service the FIFO,
the request for service interrupt for the FIFO is inhib-
NOTE: ited until the DMA is done (BCA = 0). .
The GO bit is reset when the BCA decrements to
zero.
2. BURST MODE
In BUAST mode the DMA is initiated by setting the
DMA Transfer Modes GO bit in the DCON SFR. The DMA operation con-
The following four modes of DMA operation are pos- tinues until BCA decrements to zero (zero byte
sible in the UPI-4S2. count), then an interrupt is generated (if enabled).
No interrupts are recognized during a DMA opera-
tion once started.
1. ALTERNATE=CYCLE P.10CE
General Input Channel
Alternate cycle mode is useful when CPU process- The FIFO Input Channel can be used in burst mode
ing must occur during the DMA transfers. In this by specifying the FIFO IN SFA as the DMA Source·
mode, a DMA cycle and an instruction cycle occur Address. DMA transfers begin when the GO bit in
alternately. The interrupt request is generated (if en- the DMA Control SFA is set. The number of bytes to
abled) at the end of the process; i.e. when BCA dec- be transferred must be specified in the Byte Count
rements to zero. The transfer is initiated by setting SFR (BCA) and auto-incrementing of the SAA must
the GO bit in the DCON SFR. be disabled. Once the GO bit is set nothing can in-
terrupt the transfer of data until the BCR is zero. In
Alternate-Cycle FIFO Demand Mode this mode, a Data Stream Command encountered in
the FIFO will be held in the COMMAND IN SFA with
Alternate cycle demand mode is useful for FIFO the pointers frozen, and invalid data (FFH) will be
transfers of a less urgent nature. As mentioned be- read through the FIFO IN SFA. If the input FIFO
fore, CPU instruction cycles are interleaved with becomes empty during the block transfer,an OFFH
DMA transfer cycles, allowing true parallel process- will be read until BCA decrements to zero.
ing.
This mode differs from FIFO Demand Mode in that Output Channel
.CPU instruction cycles must be interleaved with
DMA transfers, even if the FIFO is demanding DMA. The Output FIFO Channel can be used in burst
In FIFO Demand Mode, CPU cycles would never oc- mode by specifying the FIFO OUT or COMMAND
cur if the FIFO demand was present. OUT SFR as the DMA Destination Address. DMA
transfers begin when the GO bit is set. This mode
can be used to send a block of data or a block of
Input Channel Data Stream Commands. If the FIFO becomes full
The DMA is configured as in FIFO Demand Mode during the block transfer, the remaining data will be
and transfers are initiated whenever an Input FIFO lost.
10-182
UPI-452
NOTE: is not full or empty. DMA transfers begin when the
All interrupts including FIFO interrupts are not rec- Request For Service Flag is activated by the FIFO
ognized in Burst Mode. Burst Mode transfers logic and continue as long as the flag is active. The
should be used to service the FIFO only when the Flag remains active until one of the following occurs:
user is certain that no Data Stream Commands are 1) The FIFO becomes full
in the block to be transferred (Input FIFO) and that
the FIFO contains enough space to store the block 2) SCR = 0 (this generates a DMA interrupt and
to be transferred. In all other cases Alternate Cycle sets the DONE bit).
or Demand Mode should be used.
As in Alternate Cycle FIFO 'Demand Mode, the FIFO
logic resets the interrupt flag after transferring the
3. FIFO AND SERIAL CHANNEL DEMAND byte, so the interrupt is never generated.
MODES
After the GO bit is set, the DMA is activated if one of
NOTES:
the following conditions takes place:
1. If the output FIFO is configured as a one byte SAR(0/1) = FIFO IN and HIFRS flag is set
buffer and the user program consists of two-cycle DAR(0/1) = FIFO OUT and HOFRS flag is set
instructions only, then Alternate-Cycle Mode should
be used. The HIFRS and HOFRS Signals are internal flags
2. In non-auto increment mode for internal to exter-
which are not accessible by software. These flags
nal, or external to internal transfers, the lower 8 bits are similar to the SSTO and SST4 flags in the Slave
of the external address should not correspond to
Status Register except that they are of the opposite
the FIFO or Serial Port address.
polarity and once set they are not cleared until the
Input FIFO becomes empty (HIFRS) or the Output
FIFO Demand Mode FIFO becomes full (HOFRS).
Although any DMA mode is possible using the FIFO
buffer, only FIFO Demand and Alternate Cycle FIFO Serial Channel Demand Mode
Demand Modes are recommended. FIFO Demand
Mode DMA transfers using the input FIFO Channel Serial Channel Demand Mode is the logical choice
are set-up by setting the GO bit and specifying the when using the Serial Port. The OM As can be acti-
FIFO IN register as the DMA Source Address Regis- vated by one of the Serial Channel Flags. Receiver
ter. The BCR should be set to the maximum number interrupt (RI) or Transmitter Interrupt (TI).
of expected transfers. The user must also program
bit 1 of the Slave Control Register (SC1) to deter- SAR(0/1) = SBUF and RI flag is set
mine whether the Slave Status (SSTAT) SFR FIFO DAFl(0/1) = SBUF and TI flag is set
Request For Service Flag will be activated when the
FIFO becomes not empty or full. Once the Request NOTE:
For Service Flag is activated by the FIFO, the DMA TI flag must be set by software to initiate the first
transfer begins, and continues u'ntil the request flag transfer. '
is deactivated. While the request is active, nothing
can interrupt the DMA (Le. it behaves like burst When the DMA transfer begins, only one byte is
mode). The DMA Request is held active until one of transferred at a time. The serial port hardware auto-
the following occurs: matically resets the flag after completion of the
transfer, so an interrupt will not be generated unless
1) The FIFO becomes empty.
DMA servicing is held off due to the DMA being
2) A Data Stream Command is encountered (this done (BCR = 0) or when the Hold/Hold Acknowl-
generates a FIFO interrupt and DMA operation edge logic is used and the DMA does not own the
resumes after the Data Stream Command is bus. In this case a Serial Port interrupt may be gen-
read). erated if enabled because of the status of the RI or
3) BCR = 0 (this generates a DMA interrupt and TI flags.
sets the DONE bit).
In FIFO demand mode, Alternate cycle FIFO de-
DMA transfers to the Output FIFO Channel are simi- mand mode or Serial Port demand mode only one of
lar. The FIFO OUT or COMMAND OUT SFR is the the following registers (SBUF, FIN or FOUT) should
DMA Destination Address SFR and a transfer is be used- as either the SAR or DAR registers to pre-
started by setting the GO bit. The user programs bit vent undesired transfers. For example if SARO =
o of the Slave Control SFR (SCO) to determine FIN and DARO = SBUF in demand mode, the DMA
whether a demand occurs when the Output FIFO transfer will start if either the HI FRS or TI flags are
set.
10-183
UPI-452
4. EXTERNAL DEMAND MODE ARBITER MODE: In this mode, the UPI-452 is the
bus master. It configures port pin P1.5 as HLD input
The DMA can be initiated by an external device via and pin P1.6 as HLDA output. When a device as-
External interrupt 0 and 1 (INTO/INT1) pins. The serts the HLD signal to use the .local bus, the UPI-
INTO pin demands DMAO (Channel 0) and INT1 de- 452 asserts the HLDA Signal after current instruction
mands DMA 1 (Channel 1). If the interrupts are con- execution is complete. If the UPI-452 needs an ex-
figured in edge mode, a single byte transfer is ac- ternal access via a DMA channel, it waits until the
complished for every request. Interrupts also result requester releases the bus, HLD goes inactive.
(INTO and INT1) after every byte transfer (if en-
abled). If the interrupts are configured in level mode, DISABLE MODE: When external program memory is
the DMA transfer continues until the request goes accessed by an instruction or by program counter
inactive or BCR = o. In either case, a DMA interrupt overflow beyond the internal ROM address or exter-
is generated (if enabled) when BCR = o. The GO bit nal data memory is accessed by MOVX instructions,
must be set for the transfer to begin. it is a local memory access and the HLD/HLDA logic
is not initiated. When a DMA channel attempts data
transfer to/from the external data memory, the
EXTERNAL MEMORY DMA HLD/HLDA logic is' initiated as described below.
DMA transfers from the internal memory space to
When transferring data to or from external memory the internal memory space does not initiate the
via DMA, the HOLD (HLD) and HOLD-ACKNOWL- HLD/HLDA logiC.
EDGE (HLDA) signals are used for handshaking;
The HOLD and HOLD-ACKNOWLEDGE are active The balance of the PCON SFR bits are described in
low signals which arbitrate control of the local bus. the "80C51 Register Description: Power Control
The UPI-452 can .be used in a system where mUlti- ·SFR" section below.
masters are connected to a single parallel Address/
Data bus. The HLD/HLDA signals are used to share
resources (memory, peripherals, etc.) among all the Latency
processors on the local bus. The UPI-452 can be
When the GO bit is set, the -UPI-452 finishes the
configured in any of three different External Memory
~J.odss controlled by bits 5 and G (REO &.ARSj in
current instruction before starting the DMA opera-
the PCON SFR '(Table 5). Each mode is described tion. Thus the maximum latency is 3.0 microseconds
(at 16 MHz). .'
below:
REQUESTER MODE: In this mode, the UPI-452 is
not the bus master, but must request the bus from
DMA Interrupt Vectors
another device. The UPI-452 configures port pin Each DMA channel has a unique vectored interrupt
P1.5 as a HLD output and pin P1.6 as a HLDA input. associated with it. There are two vectored interrupts
The UPI-452 issues a HLD signal when it needs ex- associated with the two DMA channels. The DMA
ternal access for a DMA channel. It uses the local interrupts are enabled and priorities set via the Inter-
bus after receiving the HLDA signal from the bus rupt Enable and Priority SFR (see "Interrupts" sec-
master, and will not release the bus until its DMA tion). The interrupt priority scheme is similar to the
operation is complete. scheme in 80C51.
Table 5. DMA MODE CONTROL - PCON SFR
Symbolic Physical
Address Address
PCON -* ARB REQ -* -* -* -* -*. 87H
(MSB) (LSB)
. 'Defined as per MLS-51 Data Sheet
Reset Statu!': OOH
Definition:
ARB REQ
0 0 HLD/HLDA logic is disabled.
0 1 The UPI-452 is in the Requester Mode.
1 0 The UPI-452 is in the Arbiter Mode.
1 1 Invalid
10-184
infef UPI-452
When a DMA operation is complete (BCR decre- If the UPI-452 (as a Requester) asserts a HLD signal
ments to zero), the DONE flag in the respective to request a DMA transfer (see "External Memory
DCON (DCONO or DCON1) SFR is set. If the DMA DMA")and its other DMA Channel requests a trans-
interrupt is enabled, the DONE flag is reset automat- fer before the HLDA signal is received, the channel
ically upon vectoring to the interrupt routine. having higher priority is activated first. A Burst Mode
transfer on channel 0 can not be interrupted since
DMAOhas the highest priority. A Demand Mode
Interrupts When DMA is Active transfer on channel 0 is the only type of activity that
can interrupt a block transfer on DMA 1.
If a Burst Mode DMA transfer is in progress, the in-
terrupts are not serviced until the DMA transfer is If, while executing a DMA transfer, the Arbiter re-
complete. This is also true for level activated Exter- ceives a HLD signal, and then before it can acknowl-
nal Demand DMA transfers. During Alternate Cycle edge, its other DMA Channel requests a transfer, it
DMA transfers, however, the interrupts are serviced then completes the second DMA transfer before
at the end of the DMA cycle. After that, DMA cycles sending the HLDA signal to release the bus to the
and instruction execution cycles occur alternately. In HLD request.
the case of edge activated External Demand Mode
DMA transfers, the interrupt is serviced at the end of DMA transfers may be held off under the following
DMA transfer of that single byte. conditions:
1. A write to any of the DMA registers inhibits the
DMA for one instruction cycle.
DMA Arbitration
Only one of the two DMA channels is active at a NOTE:
An instruction cycle may be executed in 1, 2 or 4
time, except when both are configured in the Alter-
nate Cycle mode. In this case, the DMA cycles and machine cycles dependent on the instruction being
executed. DMA transfers are only executed after
Instruction Execution cycles occur in the following
order: the completion of an instruction cycle never be-
tween machine cycles of a single instruction cycle.
1. DMA Cycle o. Similarly instruction cycles are only executed upon
2. Instruction execution. completion of a DMA transfer whether it be a one
3. DMA Cycle 1. machine cycle transfer or two machine cycles (for
ext. to ext. memory transfers).
4. Instruction execution.
2. A single machine cycle DMA register read opera-
DMAO has priority over DMA 1 during simultaneous tion (Le. MOV A, DCONO) will inhibit the DMA for
activation of the two DMA channels. If one DMA one instruction cycle. However a two cycle DMA
channel is active, the other DMA channel, if activat- register read operation will not inhibit the DMA
(Le. MOV P1, DCONO).
ed, waits until the first one is complete.
If the HOLD/HOLD Acknowledge logic is enabled in
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Alternate Cycle Mode, it will requestor mode the hold request will go active once
take two instruction cycles before DMA 1 is activated the go bit has been set (for burst mode) and once
(due to the priority of DMAO). Once DMA 1 becomes the demand flag is set (for demand mode) regard-
active, the execution will follow the normal se- less of whether the DMA is held off by one of the
quence. above conditions.
The DMA Transfer waveforms- are in Figures 8-11.
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Burst Mode, the DMA 1 Burst
transfer will follow the DMAO Alternate Cycle trans-
fer (after the completion- of the next instruction).
10-185
intJ UPI-452
51 52 53 5. 55 56 51 52 53 5. 55 56
05C
Jl.fl.I1.. nsLru-Lfl..I1..ru-Lfl.I1.. n..rLru-L nsLru-L nsLr"'"
ALE
r 1\ r ~
PORT2 -- S URCE ADOR S AIS-A OES NATION ADD E55 "15 A8
PORTO "7-AO DATA IN >-- A7- Q X ~ATA OUT
r
OM" CYCLE
231428-13
Figure 8. DMA Transfer from External Memory to External Memory
OM... CYCLE
51 52 53 5' 55 56 51' 52 53
CLOCK
ALE
PSEN
PORT2 IN51 "DOR SOURCE ADDRESS "15-A8
PORTO INST A7-AO DATA IN
iiii
231428-14
Figure 9. DMA Transfer from External Memory to Internal Memory
51 52 53 5' 55 56 51 ,I' 52 53
CLOCK
ALE
PORT2 -:--'-...... ..JI'_ _-t-_""OES;;;;T~'NA.;.;T;.;.;10.;.;N.;.;AO"'0"iRE;;;.55;....;.A;.;.15;..-'fA8......_ - t -_ _"'i'"_ _+_
PORTO DATA OUT
I--------O"A CyCLE-------1
231428-15
Figure 10. DMA Transfer from Internal Memory to External Memory
10-186
inter UPI-452
51 52 53 54 55 56 51 52 53
CLOCK
ALE
P5EN
PORT2
PORTO
IN5TRUCTION
DMA CYCLE EXECUTION
231428-16
Figure 11. DMA Transfer from Internal Memory to Internal Memory
INTERNAL INTERRUPTS Table 6. Interrupt Priority
Interrupt Source Priority Level
(highest)
Overview External Interrupt 0 o
The UPI-452 provides a total of eight interrupt sourc- Internal Timer/Counter 0 1
es (Table 6). Their operation is the same as in the DMA Channel 0 Request 2
BOC51 , with the addition of three new interrupt External Interrupt 1 3
sources for the UPI-452 FIFO and DMA features. DMA Channel 1 Request 4
These added interrupts have their enable and priori- Internal Timer/Counter 1 5
ty bits in the Interrupt Enable and Priority (IEP) SFR. FIFO - Slave Bus Interface 6
The IEP SFR is in addition to the BOC51 Interrupt Serial Channel 7
Enable (IE) and Interrupt Priority (IP) SFRs. The add- (lowest)
ed interrupt sources are also globally enabled or dis-
abled by th~ EA bit in the Interrupt Enable SFR. Ta- Table 7. Interrupt Vector Addresses
ble 6 lists the eight interrupt sources in order of pri- Interrupt Source Starting Address
ority. Table 7 lists the eight interrupt sources and External Interrupt 0 3 (003H)
their respective address vector location in program Internal Timer/Counter 0 11 (OOBH)
memory. (DMA interrupts are discussed in the "Gen- External Interrupt 1 19 (013H)
eral Purpose DMA Channels" section. Additional in- Internal Timer/Counter 1 27 (01 BH)
terrupt information for Timer/Counter, Serial Chan-
Serial Channel 35 (023H)
nel, External Interrupt may be found in the Microcon-
troller Handbook for the BOC51.) FIFO - Slave Bus Interface 43 (02BH)
DMA Channel 0 Request 51 (033H)
DMA Channel 1 Request 59 (03BH)
FIFO Module Interrupts to Internal CPU
The FIFO module generates interrupts to the inter- FIFO requests service when it becomes empty or
nal CPU whenever the FIFO requests service or not full as determined by bit 0 of the Slave Control
when a Data Stream Command is in the COMMAND SFR (OFRS). Request for Service interrupts are
IN SFR. The Input FIFO will request service whenev- generated only if enabled by the internal CPU via the
er it becomes full or not empty depending on bit 1 of Interrupt Enable SFR, and the Slave Control Regis-
the Slave Control SFR (IFRS). Similarly, the Output ter.
. 10-1B7
UPI-452
A Data Stream Command Interrupt is generated Immediate Command OUT bit (SSTAT SST6) to
whenever there is a Data Stream Command in the be set and the corresponding Host Status bit
COMMAND IN SFR. The interrupt is generated to (HSTAT HST6) to be cleared indicating the SFR is
ensure that the internal interrupt is recognized be- empty. When the internal CPU writes to the Imme~
fore another instruction is executed. diate Command OUT SFR, the Host Status bit is
set and Slave Status bit is cleared to indicate the
, ~FR isfull. (See Figure 7b, Immediate Command
Immediate Command Interrupts OUT Flowchart.) ,
a. An Immediate Command IN interrupt is generat-
ed, if enabled, to the internal CPU when the Host NOTE:
has written to the Immediate Command IN (IMIN) Immediate Command IN and OUT interrupts are ac-
SFR. The, write operation clears the Slave Status tually specific FIFO-Slave Interface interrupts to the
SFR bit (SSTAT SS:r2) and sets the Host Status internal CPU.
SFR bit (HSTAT HST2) to indicate that a byte is
present in the Immediate Command IN' SFR. One instruction from the main program is executed
When the internal CPU reads the Immediate Com- between two Consecutive interrupt service routines
mand IN (IMIN) SFR the Slave Status SFR status as in the 80C51. However, if the second interrupt
bit is set, and the Host Status SFR status bit is service routine is due to a Data Stream Command
cleared indicating the IMIN SFR is empty. Clear- Interrupt, the main program instruction is not execut~
ing the Host Status SFR bit will cause a Request ed (to prevent misreading of invalid data).
For Service (INTRQ) interrupt, if enabled, to signal
the Host that the IMIN SFR is empty. (See Figure
7a, Immediate Command IN Flowchart.) Interrupt Enabling and Priority
b. An Immediate Command OUT interrupt is gener- Each of the three interrupt special function registers
ated; if enabled, to the internal CPU when the (IE, IP and IEP) is listed below with its corresponding
Host has read the Immediate Command QUT bit definitions.
SFR. The Host read causes the Slave Status
Interrupt Enable SFR (IE)
Symbolic ' Physical
Address Address
IE EAI I ES ET1 ,EX1 ETO ,',EXO OA8H
(MSB) (LSB)
Symbol, P,?sition Function
EA IE.7 - Enables all interrupts. If EA = 0, no interrupt will be
acknowledged. If EA = 1, each'interrupt source is
individually enabled or disabfed by setting or clearing its'
-- enable bit. ,,'
1E.6 (reserved)
- 1E.5 (reserved)
ES lEA Serial Channel interrupt enable
ET1 1E.3 Internal Timer/Counter 1 Overflow Interrupt
EX1 IE.2 Externallnterrilpt-Request 1-
ETO 1E.1 In,ternal Timer/Counter 0 Overflow Interrupt
EXO lE.O , External Interrupt Request o.
10-188
UPI·452
Interrupt Priority SFR (IP)
A priority level of 0 or 1 may be assigned to each interrupt source, with 1 being higher priority level, through the
IP and the IEP (Interrupt Enable and Priority) SFR. A priority level of 1 interrupt can interrupt a priority level 0
service routine to allow nesting of interrupts.
Symbolic Physical
Address Address
IP PS PT1 PX1 PTO PXO OB8H
(MSB) (LSB)
Priority Within
Symbol Position Function
A Level
(lowest)
- IP.7 (reserved) -
- IP.6 (reserved) -
- IP.5 (reserved) -
PS IP.4 Local Serial Channel 0.7
PT1 IP.3 Internal Timer/Counter 1 0.5
PX1 IP.2 External Interrupt Request 1 0.3
PTO IP.1 Internal Timer/Counter 0 0.1
PXO IP.O External Interrupt Request 0 0.0
(highest)
Interrupt Enable and Priority SFR (IEP)
The Interrupt Enable and Priority Register establishes the enabling and priority of those resources not covered
in the Interrupt Enable and Interrupt Priority SFRs.
Symbolic Physical
Address Address
IEP I.PFIFO I EDMAO I EDMA1 I PDMAO I PDMA1 I EFIFO I OF8H
(MSB) (LSB)
Priority
Symbol Position Function Within a
Level
- IEP.7 (reserved)
- IEP.6 (reserved)
PFIFO IEP.5 FIFO Slave Bus Interface Interrupt Priority 0.6
EDMAO IEP.4 DMA Channel 0 Interrupt Enable
EDMA1 IEP.3 DMA Channel 1 Interrupt Enable
PDMAO IEP.2 DMA Channel 0 Priority 0.2
PDMA1 IEP.1 DMA Channel 1 Priority 0.4
EFIFO IEP.O FIFO Slave Bus Interface Interrupt Enable
10-189
inter UPI-452
FIFO:.EXTERNAL HOST INTERFACE DMA Freeze Mode bit defaults to FIFO DMA Freeze
Mode (SLCON FRZ = O). Below is a list of the FIFO
FIFO DMA FREEZE MODE Special Function Registers and their default power
on reset values;
Overview SFRName Label Value
During FIFO DMA Freeze Mode the internal CPU Channel Boundary Pointer· CBP 40H 164D
can reconfigure the FIFO interface. FIFO DMA Output Channel Read Pointers ORPR 40H 164D
Freeze Mode is provided to prevent the Host from Output Channel Write Pointers OWPR 40H 164D
accessing the FIFO during a reconfiguration se-
Input Channel Read Pointers IRPR OOH 100D
quence. The internal CPU invokes FIFO DMA
Freeze MOde by clearing bit 3 of 'the Slave Control Input Channel Write Pointers IWPR OOH 100D
SFR (SC3). INTRQ becomes active whenever FIFO Input Threshold ITHR BOH I 12BD
DMA Freeze Mode is invoked to indicate the freeze Output Threshold OTHR 01H 110
status. The interrupt can only be deactivated by the
Host reading the Host Status SFR. The Input and Output FIFO channels may be recon-
figured by programming any of these SFRs while the
During FIFO DMA Freeze Mode only two operations FIFO Host interface is in FIFO DMA Freeze Mode.
are possible by the Host to the UPI-452 slave, the The UPI-452 also notifies the Host that FIFO DMA
balance are disabled, as shown in Table B. The in- Freeze Mode is in progress by setting the Host
ternal DMA is disabled during FIFO DMA Freeze Status SFR FIFO DMA Freeze Mode Status bit,
Mode, and the internal CPU has write access to all FIFO DMA Freeze Mode In Progress. The Host in-
of the FIFO control SFRs (Table 9). terrogates the Host Status SFR to determine the
status of the FIFO Host interface following reset be- .
fore attempting to read ,from or write to the UPI-452
Initialization FIFO buffer.
At power on reset the FIFO Host interface is auto-
matica!!y frozen. The Slave Control Enab!e F!FO
Table 8. Slave Bus Interface Status During FIFO DMA Freeze Mode
Interface Pins; Operation In Status In
CS A2 A1 AD READ WRITE
DACK Normal Mode FIFO DMA Freeze Mode
1 0 0 1 0 0 1 Read Host Status SFR Operational
1 0 0 1 1 0 1 Read HostControl SFR Operational
1 0 0 1 1 1 0 Write Host Control SFR Disabled
1 0 0 0 0 0 1 Data or DMA Data from Disabled
Output Channel
1 0 0 0 0 1 0 Data or DMA Data to Disabled
Input Channel
1 0 0 0 1 0 1 Data Stream Command from Disabled
Output Channel
1 0 0 0 1 1 0 Data Stream Command to Disabled
Input Channel
1 0 1 0 0 0 1 Read Immediate Command Disabled
Qut from Output Channel
1 0 1 0 0 1 0 Write Immediate Command Disabled
In to Input Channel
0 X X X X 0 1 DMA Data from Outp,ut Disabled
Channel
0 X X X X 1 0 DMA Data to Input Channel Disabled
10-190
inter UPI·452
The UPI-452 can also be programmed to interrupt FIFO DMA Freeze Mode without first stopping the
the Host following power on reset in order to indi- external Host from accessing the UPI-452 will not
cate to the Host that FIFO DMA Freeze Mode is in guarantee a clean break with the external Host.
progress. This is done by enabling the INTRO inter-
rupt output pin via the MODE SFR (MD4) before the The proper way to invoke FIFO DMA Freeze Mode is
Slave Control SFR Enable FIFO DMA Freeze Mode by issuing an Immediate Command to the external
bit is set to Normal Mode. At power on reset the host indicating that FIFO DMA Freeze Mode will be
Mode SFR is forced to zero. This disables all inter- invoked. Upon receiving the Immediate Command,
rupt and DMA output pins (INTRO, DROIN/ the external Host should complete servicing all
INTROIN and DROOUTIINTROOUT). Because the pending interrupts and DMA requests, then send an
Host Status SFR FIFO DMA Freeze Mode In Prog- Immediate Command back to the UPI-452 acknowl-
ress bit is set, a Request For Service, INTRO, inter- edging the FIFO DMA Freeze Mode request. After
rupt is pending until the Host Status SFR is read. issuing the first Immediate Command, the internal
This is because the FIFO DMA Freeze Mode inter- CPU should not perform any action on the FIFO until
rupt is always enabled. If the Slave Control FIFO FIFO DMA Freeze Mode is invoked .
. DMA Freeze Mode bit (SLCON FRZ) is set to Nor-
mal Mode before the MODE SFR INTRO bit is en- If FIFO DMA Freeze Mode is invoked without stop-
abled, the INTRO output will not go active when the ping the Host during Host transfers, only the last two
MODE SFR INTRO bit is enabled if the Host Status bytes of data written into or read from the FIFO will
SFR has been read. be valid. The timing diagram for disabling the FIFO
module to the external Host interface is illustrated in
The default values for the FIFO and Slave Interface Figure 12. Due to this synchronization sequence, the
represents minimum UPI-452 internal initialization. UPI-452 might not go into FIFO DMA Freeze Mode
No specific Special Function Register initialization is immediately after SC3 is cleared. A special bit in the
required to begin operation of the FIFO Slave Inter- Slave Status Register (SST5) is provided to indicate
face. The last initialization instruction must always the status of the FIFO DMA Freeze Mode. The FIFO
set the UPI-452 to Normal Mode. This causes the DMA Freeze Mode operations described in this sec-
UPI-452 to exit FIFO DMA Freeze Mode and en- tion are only valid after SST5 is cleared.
ables Host read/write access of the FIFO.
As FIFO DMA Freeze Mode is invoked, the DROIN
Following reset, either hardware (via the RST pin) or or DROOUT will be deactivated (stopping the trans-
software (via HCON SFR bit HC3) the UPI-452 re- ferring of data), bit 1 of the Host Status SFR will be
quires 2 internal machine cycles (24 TCLCL) to up- set (HST1 = 1), and SST5 will be cleared (SST5 = 0)
date all internal registers. to indicate to the external Host and internal CPU
that the slave interface has been frozen. After the
freeze becomes effective, any attempt by the exter-
Invoking FIFO DMA Freeze Mode .nal Host to access the FIFO will cause the overrun
During Normal Operation and underrun bits to be activated (bits HST7 (for
reads) or HST3 (for writes». These two bits, HST3
When the UPI-452 is in normal operation, FIFO DMA and HST7, will be set (deactivated) after the Host
Freeze Mode should not be arbitrarily invoked by Status SFR has been read. If INTRO is used to re-
clearing SC3 (SC3 = 0) because the external Host quest service, the FIFO interface is frozen upon
runs asynchronously to the internal CPU. Invoking completion of any Host read or write operation in
progress.
DRQIN/
DRQOUT
..J
~ -----55 ~----,
I' ~.! A FIFO RD/WR AFTER INTERFACE
, FREEZE IS INVOKED WILL CAUSE
, HST 3 OR HST7 TO BE SET
5r-------------~~~----~~----~--~~----~
INTRQ -1_ --------------------- :FIFO INTERNALLY STOPPED FROM
ACCEPTING OR OUTPUTIING DATA
SC3
HST1 ___________________________ ~
231428-17
Figure 12. Disabling FIFO to Host Slave Interface Timing Diagram
10-191
inter UPI-4S2
External Host writing to the Immediate Command In HCON, the Input Channel error condition flag
SFR and the Host Control SFR is also inhibited (HST3) will be cleared.
when the .slave bus interface is frozen. Writing to
these two registers after FIFO DMA Freeze Mode is
invoked will also cause HST3 (overrun) to be activat- Input FIFO Pointer Registers
ed (HST3 = 0). Similarly, reading the Immediate (IRPR & IWPR)
Command Out Register by the external Host is dis-
abled during FIFO DMA Freeze Mode, and.any at- Once the FIFO module is in FIFO DMA Freeze
tempt to do so will cause the clearing '(deactivating, Mode, error flags due to overrun and underrun of the
"0") of HST7 bit (underrun). Input FIFO pointers will be dis.abled. Any attempt to
create an overrun or unqerrun condition by changing
After the slave bus interface is frozen, the internal the Input FIFO pointers would result in an inconsist-
CPU can perform the following operations on the ency in performance between the status flag and the
FIFO Special Function Registers (these operations threshold counter.
are allowed only during FIFO DMA Freeze Mode).
To enhance the speed of the UPI-452, read opera"
For FIFO 1. Changing the Channel tions on the Input FIFO will look ahead by two bytes.
Reconfiguration Boundary Pointer SFR. Hence, every time the IRPR is changed during FIFO
2. Changing the Input and DMA Freeze Mode, two NOPs need to be executed
Output Threshold SFR. so that the two byte pipeline can be updated with the
new data bytes pointed to by the new IRPR. The
To Enhance the 3. Writing to ,the read and write Threshold Counter SFR also needs to change by the
Testability pointers of the Input and same number of bytes as the IRPR (increase
Threshold Counter if IRPR goes forward or decrease
Output FIFO's.
if IRPR goes backward). This will ensure that future
4. Writing to and reading the interrupts will still be generated only after a thresh-
Host Control SFRs. old number of bytes are available. (See "Input and
5. Controlling some bits of Host Output FIFO Threshold SFR" section below.)
and Slave Status SFRS.
6. Reading the Immediate In FIFO DMA Freeze Mode, the internal CPU can
Command Out SFR and also change the content of IWPR, and each change
Writing to the Immediate of IWPR also requires an update. of the Threshold
Comand In SFR. Counter SPR.
Normally, the internal CPU cannot write into the In-
put FIFO. It can, however, during FIFO DMA Freeze
Description of each of these special Mode by first reconfiguring the FIFO as an Output
functions are as
.. follows: FIFO (Refer to "Input and Output FIFO Threshold
SFR" section below). Changing the IRPR to be
equal to IWPR generates an empty condition while
FIFO Module SFRs During changing IWPRto be equal to IRPR generates a full
FIFO DMA Freeze Mode condition. The order in which the pointers are written
Table 9 summarizes the characteristics of all the determines whether a full or empty condition is gen-
FIFO Special Function Registers during normal and erated.
FIFO DMA Freeze Modes. Theregisters that require
special treatment in FIFO DMA Freeze Mode are:
HCON, IWPR, IRPR, OWPR, ORPR, HSTAT, Output.FIFO Pointer SFR
SSTAT, MIN & MOUT SFRs. They can be described (ORPR and OWPR)
in detail as follows:
In FIFO DMA Freeze Mode the contents of OWPR
can be changed by the internal CPU, but each.
change of OWPR or ORPR requires the Threshold
Host Control SFR (HCON) Counter SFR to be updated as described in the next
During normal operation, this register is written to or section. A NOP must be executed whenever a new
read by the external Host. However, in FIFO DMA value is written into ORPR, as just described for
Freeze Mode (Le. SST5 = 0) the UPI-452 internal changes to IRPR. As before; changing ORPR to be
CPU has write access to the Host Control SFR and equal to OWPR will generate an empty condition,
write operations to this SFR by the external Host will Output FIFO overrun or underrun condition cannot
not be accepted. If the Host attempts to write to be generated though. The FIFO pointers should not
be set to a value outside of its range.
10-192
inter UPI·452
Table 9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Normal FIFO DMA Freeze Mode
Label Name Operation Operation
(SST5 = 1) (SST5 = 0)
HCON Host Control Not Accessible Read & Write
HSTAT Host Status Read Only Read & Write 4
SLCON Slave Control Read & Write Read & Write
SSTAT Slave Status Read Only Read & Write 4
IEP Interrupt Enable & Priority Read & Write Read & Write
MODE Mode Register Read & Write Read & Write
IWPR Input FIFO Write Pointer ReadOniy Read & Write 5
IRPR Input FIFO Read Pointer Read Qnly Read & Write 1, 5
OWPR Output FIFO Write Pointer Read Only Read & Write 6
ORPR Output FIFO Read Pointer Read Only Read & Write 2, 6
CBP Channel Boundary Pointer Read Only Read & Write 3
IMIN Immediate Command In Read Only Read & Write
IMOUT Immediate Command Out Read & Write Read & Write
FIN FIFO IN Read Only Read Only
CIN COMMAND IN Read Only Read Only
FOUT FIFO OUT Read & Write Read & Write
COUT COMMAND OUT Read & Write Read & Write
ITHR Input FIFO Threshold Read Only Read & Write
OTHR Output FIFO Threshold Read Only Read & Write
NOTES:
1. Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location.
2. Writing to ORPR will automatically cause the IOBl SFR to load the contents of the Output FIFO at that ORPR address.
3. Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels.
4. The internal CPU cannot directly change the status of these registers. However, by changing the status of the FIFO
channels, the internal CPU can indirectly change the contents of the status registers.
5. Changing the Input FIFO Read/Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter
SFR.
6. Changing the Output FIFO Read/Write Pointers also requires that a consistent update of the Output FIFO Threshold
Counter SFR.
10-193
intJ UPI·452
Input and Output FIFO Threshold SFR Host Status SFR (HSTAT)
(ITHR & OTHR)
When in, FIFO DMA Freeze Mode, some bits in the
The Input and Output FIFO Threshold SFRs are also Host Status SFR are forced high and will not reflect
programmable by the internal CPU during FIFO DMA the new status until the system returns to normal
Freeze Mode. For proper operation of the Threshold operation. The definition of the register in FIFO DMA
feature, the Threshold SFR should be changed only Freeze Mode is as follows:
when the Input and Output FIFO channels are emp-
ty, since they reflect the current number of bytes NOTE:
available to read/write before an'internipt is gener- The internal CPU reads this shadow latch value
ated. . when reading the Host Status SFR. The shadow
latch will keep the information for these bits so nor-
Table 10 illustrates the Threshold SFRs range of mal operation can be resumed with the right status.
values and the number of bytes to be transferred The following bits are set (= 1) when FIFO DMA
when the Request For Service Flag is activated: Freeze Mode is invoked;
HST7 Output FIFO Error Condition Flag,
Table 10. Threshold SFRs Range of Values and
1 = No error.
Number of Bytes to be Transferred
ITHR No. of Bytes No. of Bytes
o = An invalid read has been done on the
OTHR output FIFO or the Immediate Command
(lower Available to (lower Available to Olit Register by the host CPU.
~even bits) be Written seven bits be Read
0 CBP 1 2 NOTE:
1 CBP-1 2 3 The normal underrun error condition status is dis-
2 CBP-2 3 4 abled. If an Immediate Command Out (IMOUT)
• • • • SFR read is attempted during FIFO DMA Freeze
• • • • Mode, the contents of the IMOUT SFR is output on
• • • • the Data Buffer and the, error status is cleared
(= ~.' ,
CBP·3 ,3 (80H-CBP)·3 (80H-CBP)-2
GBP-2· 2 (80H-CBP)-2 (80H-CBP)-1 HST6 Immediate Command Out SFR Status
(80H-CBP)·1 (80H-CBP)
During normal operation, this bit is cleared
(= 0) when the IMOUT SFR is written by the
The eighth bit of the Input and Output FIFO Thresh- UPI-452 internal CPU and set (= 1) when the
old SFR indicates the status of the service requests IMOUT SFR is read by the external Host.
regardless of the freeze condition. If the eighth bit is Once the host-slave interface is frozen (Le.
a "1", the FIFO is requesting service from the exter- SST5 = 0), this bit will be read as a 1 by the
nal Host. In other words, when the Threshold SFR host CPU. A shadow latch will keep the infor-
value goes below zero (2's complement), a service mation for this bit so normal operation can be
request is generated". Normally the ITHR SFR is resumed with the correct status.
decremented after each external Host write to the
Shadow latch:
Input FIFO and incremented after each internal CPU
read of the Input FIFO. The OTHR SFR is decre- 1 = Internal CPU reads the IMOUT SFR
mented by internal CPU writes and incremented by o = Internal CPU writes to the IMOUT SFR
external Host reads. Thus if the pointers are moved
HST5 Data Stream Command at Output FIFO
when the FIFO's are not empty, these relationships
can be used to calculate the offset for the Threshold This bit is forced to a "1" during FIFO DMA
SFRs. It is best to change the Threshold SFRs only Freeze Mode to prevent ,the external host
when the FIFO's are empty to avoid this complica~ CPU from trying to read the DSC. Once nor-
tion. The threshold registers should also be updated mal. operation is resumed, HST5 will reflect
after the pointers have been manipulated. the Data/Command status of the currentbyte
in the Output FIFO.
NOTE: Shadow Latch (read by the internal CPU):
When programming the ITHR SFR, the eighth bit
1 = No Data Stream Command (DSC)
should be set to 1 (OR'd with 80H). This causes
HSTAT SFR HSTO = 0, Input FIFO Request For o = Data Stream Command at Output FIFO
Service. If ITHR bit 7 = 0 then HSTAT HSTO = 1,
Input FIFO Does Not Request Service, and no in-
terrupt will be generated.
'The 8th bit of the ITHR SFR must be set during initialization if the
Host interrupt request is desired immediately upon leaving Freeze
Mode,
10-194
intJ UPI·452
HST4 Output FIFO Service Request Status SST? Output FIFO Overrun Error Flag
When FIFO DMA Freeze Mode is invoked, Inoperative in FIFO DMA Freeze Mode.
this bit no longer reflects the Output FIFO Re- SST6 Immediate Command Out SFR Status
quest Service Status. This bit wll be forced to
a 111". In FIFO DMA Freeze Mode, this bit will be
cleared when the internal CPU reads the Im-
HST3 Input FIFO Error Condition Flag mediate Command Out SFR and set when
1 = No error. the internal CPU writes to the Immediate
a = One of the following operations has Command Out Register.
been attempted by the external host and SST5 FIFO-External Interface FIFO DMA Freeze
is invalid: Mode Status
1) Write into the Input FIFO This bit indicates to the internal CPU that
2) Write into the Host Control SFR FIFO DMA Freeze Mode is in progress and
that it has write access to the FIFO Control,
3) Write into the Immediate Command In Host control and Immediate Command SFRs.
SFR
SST4 Output FIFO Request Service Status
NOTE: During normal operation, this bit indicates to
The normal Input FIFO overrun condition is dis- the internal CPU that the Output FIFO is
abled. ready for more data. The status of this bit re-
HST2 Immediate Command In SFR Status flects the position of the Output FIFO read
and write pointers. Hence, in FIFO DMA
This bit is normally cleared when the internal Freeze Mode, this flag can be changed by the
CPU reads the IMIN SFR and set when the internal CPU indirectly as the read and write
external host CPU writes into the IMIN SFR. pointers change.
When the host-slave interface is frozen, read-
ing and writing of the IMIN by the internal SST3 Input FIFO Underrun Flag
CPU will change the shadow latch of this bit. Inoperative during FIFO DMA Freeze Mode.
This bit will be read as a "1" by the external During normal operation, a read operation
Host. clears (= 0) this bit when there are no data
Shadow latch. bytes in the Input FIFO and deactivated (= 1)
1 = Internal CPU writes into IMIN SFR when the Slave Status SFR is read. In FIFO
DMA Freeze Mode, this bit will not be cleared
a = Internal CPU reads the IMIN SFR by an Input FIFO read underrun error condi-
HST1 FIFO DMA Freeze Mode Status tion, nor will it be reset by the reading of the
1 = FIFO DMA Freeze Mode. Slave Status SFR.
a= Normal Operation (non-FIFO DMA SST2 Immediate Command In SFR Status
Freeze Mode). This bit is normally activated (= 0) when the
external host CPU writes into the Immediate
NOTE: Command In SFR and deactivated (= 1)
This bit is used to indicate to the external Host that when it is read by the internal CPU. In FIFO
the host-slave interface has been frozen and hence DMA Freeze Mode, this bit will not be activat-
the external Host functions are now reduced as ed (= 0) by the external Host's writing of the
shown in Table 8. Immediate Command IN SFR since this func-
HSTO Input FIFO Request Service Satus . tion is disabled. However, this bit will be
cleared (= 0) if the internal CPU writes to the
When slave interface is frozen this bit no Immediate Command In SFR and it will be set
longer reflects the Input FIFO Request Serv- = 1) if it reads from the register.
ice Status. This bit will be forced to a "1".
SST1 Data Stream Command at Input FIFO Flag
In FIFO DMA Freeze Mode, this bit operates
Slave Status SFR (SSTAT) normally. It indicates whether the next byte of
data from the Input FIFO is a DSC or data
The Slave Status SFR is a read-only SFR. However, byte. If it is a DSC byte, reading from the
once the slave interface is frozen, most of the bits of FIFO IN SFR will result in reading invalid data
this SFR can be changed by the internal CPU by (FFH) and vice versa. In FIFO DMA Freeze
reconfiguring the FIFO and accessing the FIFO Spe- Mode, this bit still reflects the type of data
cial Function Registers. byte available from the Input FIFO.
10-195
UPI-4S2
SSTO Input FIFO Service Request Flag changed. (See "Input and Output FIFO Threshold
During normal operation, this bit is activated SFR" section below.)
(= 0) when the Input FIFO contains bytes that
can be read by the internal CPU and deacti-
vated (= 1) when the Input FIFO does not MEMORY ORGANIZATION
need any service from the internal CPU. In
FIFO DMA Freeze Mode, the status of this bit The UPI-452 has separate address spaces for Pro-
should not change unless the pointers of the gram Memory and Data Memory like the 80C51. The
Input FIFO are changed. In this mode, the in- Program Memory can be. up to 64K bytes. The lower
ternal CPU can indirectly change this bit by 8K of Program Memory may reside on-chip. The
changing the read .and write pointers of the Data Memory consists of 256 bytes of on-chip RAM,
Input FIFO but cannot change it directly. up to 64K bytes of off-chip RAM and a number of
"SFRs" (Special Function Registers) which appear
as yet another set of unique memory addresses.
Immediate Command In/Out SFR Table 11a_lnternal Memory Addressing
(IMIN/IMOUT) Memory Space Addressing Method
If FIFO DMA Freeze Mode is in progress, writing to Lower 128 Bytes of Direct or Indirect
the Immediate Command In SFR by the external Internal RAM
host will be disabled, and any such attempt will
cause HST3 to be cleared (=0). Similarly, the Imme- Upper 128 Bytes Indirect Only
diate Command Out SFR read operation (by the of Internal RAM
host) will be disabled internally and read attempts
UPI-452 SFR's Direct Only
will cause HST7 to be cleared (= 0).
The 80C51 Special Function Registers are listed in
Internal CPU Read and Write of the Table 11 a, and the additional UPI-452 SFRs are list-
FIFO During FIFO DMA Freeze Mode ed in Table 11 b. A brief description of the 80C51
core SFRs is also provided below.
In normal operation, the Input FIFO can only be read
by the internal CPU and similarly, the Output FIFO
can only be written by the internal CPU. During FIFO Accessing External Memory
DMA Freeze Mode, the internal CPU can read the
entire contents of the Input FIFO by programming As in the 80C51, accesses to external memory are
the CBP SFR to 7FH, setting the IRPR SFR to zero, of two types: Accesses to external Program Memory
and then the IWPR SFR to zero. Programming the and accesses to external Data Memory.
pointer registers in this order generates a FIFO full
signal to the FIFO logic and enables internal CPU External Program Memory is accessed under two
read operations. If the IWPR and IRPR are already conditions:
zero, the write pointer should be changed to a non- 1) Whenever signal EA = 0; or
zero value to clear the empty status then the point- 2) Whenever the program counter (PC) contains a
ers can be set to zero. Writing to the IRDR SFR number that is larger than 1FFFH.
automatically updates the look ahead registers.
This requires that the ROM less versions have EA
In a similar manner, the internal CPU can write to all wired low to enable the lower 8K program bytes to
128 bytes of the FIFO by setting the CBP SFR to
be fetched from external memory.
zero, setting OWPR SFR to zero, and then setting
ORPR SFR to zero. This generates a FIFO empty External Data Memory is accessed using either the
signal and allows internal CPU write operations to all MOVX @DPTR (16 bit address) or the MOVX @Ri (8
128 .bytes of the FIFO. The Threshold registers also bit address) instructions, or during external data
need to be adjusted when the pointers are memory transfers.
10-196
infef UPI-4S2
Table 11 b. 80C51 Special Function Registers Table 11c. UPI·452 Additional Special
Function Registers (Continued)
Symbol Name Address Contents
Symbol Name Address Contents
'ACC Accumulator OEOH OOH
'B B Register OFOH OOH DARLO Low Byte/ OC2H I
'PSW Program Status ODOH OOH DARHO Hi Byte/ OC3H I
Word Channel 0
SP Stack Pointer 81H 07H DARL1 Low Byte/ OD2H I
DPTR Data Pointer 82H OOOOH DARH1 Hi Byte/ OD3H I
(consisting of DPH Channel 1
and DPL) OOH
DCONO DMAO Control 92H
'PO PortO 80H OFFH
DCON1 DMA 1 Control 93H OOH
'P1 Port 1 90H OFFH
"P2 Port 2 OAOH OFFH FIN FIFO IN OEEH I
"P3 Port 3 OBOH OFFH FOUT FIFO OUT OFEH I
*IP Interrupt Priority OB8H OEOH HCON Host Control OE7H OOH
Control Host Status OE6H OFBH
HSTAT
"IE Interrupt Enable OA8H 60H
*IEP Interrupt Enable OF8H OCOH
Control
and Priority
TMOD Timer/Counter 89H OOH
Mode Control IMIN Immediate Command OFCH I
In
"TCON Timer/Counter 88H OOH
Control IMOUT Immediate Command OFDH I
THO Timer/Counter 8CH OOH Out
o (high byte) . IRPR Input Read OEBH OOH
TLO Timer/Counter 8AH OOH Pointer
o (low byte) ITHR Input FIFO OF6H 80H
TH1 Timer/Counter 8DH OOH Threshold
1 (high byte) IWPR Input Write OEAH OOH
TL1 Timer/Counter 8BH OOH Pointer
.1 (low byte) MODE Mode Register OF9H 8FH
"SCON . Serial Control 98H OOH ORPR Output Read OFAH 40H
SBUF Serial Data Buff 99H I Pointer
PCON Power Control 87H 10H
OTHR Output FIFO OF7H 01H
I = Indeterminate Threshold
Table 11c. UPI-452 Additional OWPR Output Write. OFBH 40H
Special Function Registers Threshold
Symbol Name Address Contents *P4 Port 4 OCOH OFFH
DMA Source Address
BCRLO DMA Byte OE2H I
Count Low Byte/ SARLO Low Byte/ OA2H I
BCRHO High Byte/ OE3H I SARHO Hi Byte/ OA3H I
Channel 0 Channel 0
BCRL1 Low Byte/ OF2H I SARL1 Low Byte/ OB2H I
BCRH1 Hi Byte/ OF3H I SARH1 Hi Byte/ OB3H I
Channel 1 Channel 1
CBP Channel Boundary OECH 40H "SLCON Slave Control OE8H 04H
Pointer SSTAT Slave Status OE9H 08FH
CIN COMMAND IN OEFH I I = Indeterminate
The SFRs marked with an asterisk (*) are both bit- and
COUT COMMAND OUT OFFH I
byte- addressable. The functions of the SFRs are as fol-
DMA Destination lows:
Address
10-197
inter UPI·452
Miscellaneous Special Function DATA POINTER
Register Description
The Data Pointer (DPTR) consists of a high byte
SOC51 SFRs (DPH) and a low byte (DPL). Its intended function is
to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent S-bit registers.
ACCUMULATOR
ACC is the Accumuator SFR. The mnemonics for PORTS 0 TO 4
accumulator-specific instructions, however, refer to
the accumulator simply as A. PO, P1, P2, P3 and P4 are the SFR latches of Ports
0, 1, 2, 3 and 4, respectively.
B REGISTER SERIAL DATA BUFFER
The B SFR is used during multiply and divide opera-
The Serial Data Buffer is actually two separate regis-
tions. For other instructions it can be treated as an-
ters, a transmit buffer and a receive buffer register.
other scratch pad regster.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Mov-
ing a byte to SBUF is what initiates the
PROGRAM STATUS WORD transmission.) When data is moved from SBUF, it
The PSW SFR contains program status information comes from the receive buffer.
as detailed in Table 12.
TIMER/COUNTER SFR
STACK POINTER Register pairs (THO, TLO), and (,rH1, TL1) are the
16-bit counting registers for Timer/Counters 0 and 2.
The Stack Pointer register is S bits wide. It is incre-
mented before data is stored during PUSH and
CALL executions. While the stack may reside any- POWER CONTROL SFR (PCON)
where in on-chip RAM, the Stack Pointer is.initialized
to 07H after a reset. This causes the stack to begin The PCON Register (Table 13) controls the power
at location OSH. down and idle modes in the UPI-452, as well as pro-
viding the ability to double the Serial Channel baud
rate. There are also two general purpose flag bits
available to the user. Bits 5 and 6 are used to set the
HOLD/HOLD Acknowledge mode (see '~General
Purpose DMA Channels" section), and bit 4 is not
used.
10-19S
inter UPI·452
Table 12. Program Status Word
Symbolic Physical
Address Address
PSW CY AC FO RS1 RSO OV P ODOH
(MSB) (LSB)
Symbol Position Name
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry (For BCD operations)
FO PSW.5 Flag 0 (user assignable)
RS1 PSW.4 Register Bank Select bit 1"
RSO PSW.3 Register Bank Select bit 0"
OV PSW.2 Overflow Flag
- PSW.1 (reserved)
P PSW.O Parity Flag
'(RS1, RSO) enable Internal RAM register banks as follows:
RS1 RSO Internal RAM Register Bank
0 0 BankO
0 1 Bank 1
1 0 8ank2
1 1 Bank3
Table 13. peON Special Function Register
Symbolic Physical
Address Address
PCON SMOD ARB REO GF1 GFO PD IDL 087H
(MSB) (LSB)
'Symbol Position Function
SMOD PCON7 Double Baud rate bit. When set to a
1, the baud rate is doubled when the
serial port is being used in either
Mode 1, 2 or 3 ..
ARB PCON6 HLD/HLDA Arbiter control bit"
REO PCON5 HLD/HLDA Requestor control bit"
- PCON4 (reserved)
GF1 PCON3 General-purpose flag bit
GFO PCON2 General-purpose flag bit
PD PCON1 Power Down bit. Setting this bit
activates power down operation.
IDL PCONO Idle Mode bit. Setting this bit
activates idle mode operation .
..
'See Ext. Memory OM"''' deSCriptIon.
NOTE:
If 1's are written to PO and IOL at the same time, PO takes precedence. The reset value of peON is (OOOXOOOO).
10-199
inter UPI-452
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent dam-
Ambient Temperature Under Bias ..... o·c to 70'Ct age to the device. This is a stress rating only and
Storage Temperature .......... - 65'C to + 150'C functional operation of the device at these or any
other conditions above those indicated in the opera-
Voltage on Any
tional sections of this specification is not implied. Ex-
Pin to Vss ............... -0.5V to Vee + 0.5V posure to absolute maximum rating conditions for
Voltage on Vee to Vss ............ -0.5V to + 6.5V extended periods may affect device reliability.
Power Dissipation ........................ 1.0W··
Vec/Vpp Supply Voltage with NOTICE: Specifications contained within the
Respect to Ground following tables are subject to change.
During Programming ......... - 0.6V to + 14.0V
D.C. CHARACTERISTICS TA = 0'Ct070'C;Vee = 5V ±10%;Vss = ov
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee + 0.5 V
(except XTAL 1, RST)
VIH1 Input High Voltage 3.9 Vee + 0.5 V
(XTAL1, RST)
VOL Output Low Voltage 0.45 V IOL = 1.6 mA (Note 1)
(Ports 1, 2, 3, 4) -
Vou Output Low Voltage 0.45 V IOL = 3.2 mA (Note 1)
(.,y,.,.,nt Pnrt
'-.~--I""'.' _.....- 1., -,
? ~
-, <1\
"
VOH Output High Voltage 2.4 V IOH = -60 /LA, Vee = 5V ±10%
(Ports 1, 2, 3, 4)
0.75 Vee V IOH= -25/LA
0.9 Vee V IOH = -10,LA
VOH1 Output High Voltage 2.4 V IOH = -400 /LA, Vee = 5V ±10%
(except Ports 1, 2, 3, 4 and
0.75 Vee V IOH = -150/LA
Host Interface (Slave) Port)
0.9 Vee V IOH = -40 /LA (Note 2)
VOH2 Output High Voltage 2.4 V IOH = -400 /LA, Vee = 5V ± 10%
(Host Interface (Slave) Port)
3.0 V IOH = 1 mA
Vee - 0.4 V IOH = -10/LA
IlL Logical 0 Input Current -50 /LA VIN = 0.45V
(Ports 1, 2, 3, 4)
ITL Logical 1 to 0 Transition ~650 /LA VIN = 2V
Current (Ports 1, 2, 3., 4)
t Ambient Temperature under Bias for 87e452P IS o'e to 50'e.
10-200
UPI-4S2
D.C. CHARACTERISTICS TA = O°C to 70°C; VCC = 5V ± 10%; VSS = OV (Continued)
Symbol Parameter Min Max Units Test Conditions
III Input Leakage Current ±10 p.A 0.45V < VIN < Vcc
(except Ports 1, 2, 3, 4)
loz Output Leakage Current ±10 p.A 0.45V < VOUT < Vcc
(except Ports 1,2, 3, 4)
ICCl Operating Current (Note 6) 15 mA Vcc = 5.5V, 16 MHz
Icc Operating Current (Note 7) 50 mA Vcc = 5.5V, 16 MHz (Note 4)
Icci Idle Mode Current 25 mA Vcc = 5.5V, 16 MHz (Note 5)
Ipo Power Down Current 100 p.A Vcc = 2V (Note 3)
RRST Reset Pull down Resistor 50 150 KO
CIO Pin Capacitance 20 pF 1 MHz, TA = 25°C
(sampled, not tested on all parts)
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall before the 0.9 Vee
specification when the address bits are stabilizing.
3. Power DOWN lee is measured with all output pins disconnected; EA = Port 0 = Vee; XTAL2 N.C.; RST = Vss; DB =
Vee; WR = RD = DACK = CS = AO = Al = A2 = Vee. Power Down Mode is not supported on the 87C452P.
4. lee is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH ""
Vee - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = Vee; WR = RD = DACK = CS = AO = A1 = A2 = Vee. lee would be
slightly higher if a crystal oscillator is used.
5. Idle lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V,
VIH = Vee - 0.5V; XTAL2 N.C.; Port 0 = Vee: EA = RST = Vss; WR = RD = DACK = CS = AO = A1 = A2 = Vee.
6. 87C452P Piggyback EPROM only.
7. 80C452 and 83C452 only.
EXPLANATION OF THE AC SYMBOLS Q: Output data.
R: READ signal.
Each timing symbol has 5 characters. The first char-
T: Time.
acter is always a 'T' (stands for time). The other
characters, depending on their positions, stand for V: Valid.
the name of a signal or the logical status of that W: WRITE signal.
signal. The following is a list of all the characters and
what they stand for:
X: No longer a valid logic level.
A: Address. Z: Float.
C: Clock.
D: Input data. EXAMPLE
H: Logic level HIGH. TAVLL = Time for Address Valid to ALE Low.
I: Instruction (program memory contents). TLLPL = Time for ALE Low to PSEN Low.
L: Logic level LOW, or ALE.
P: PSEN.
10-201
UPI-452
A.C. CHARACTERISTICS TA = O·C to 70·C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE, and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
16 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 16 MHz
TLHLL ALE Pulse Width 85 2TCLCL-40 ns
TAVLL Address Valid to ALE Low 25 TCLCL-55 ns
TLLAX Address Hold after ALE Low 28 TCLCL-35 ns
TLLlV ALE Low to Valid Instr In 185 4TCLCL-100 ns
TLLPL ALE Low to PSEN Low 22 TCLCL-40 ns
TPLPH PSEN Pulse Width 142 3TCLCL-45 ns
TPLIV PSEN Low to Valid Instr In 110 3TCLCL-105 ns
TPXIX Inputlnstr Hold after PSEN 0 0 ns
TPXIZ Input Instr Float after PSEN 57 TCLCL-25 ns
TAVIV Address to Valid Instr In 225 5TCLCL-105 ns
TPLAZ PSEN Low to Address Float 10 10 .ns
TRLRH RD Pulse Width 275 6TCLCL-100 , ns
T'vVLVVH WR Puise Width 275 6TCLCL-iOO ns
TRLDV RD Low to Valid Data In 148 5TCLCL-165 ns
TRHDX Data Hold after RD 0 0 ns
TRHDZ Data Float after RD 2TCLCL-70 ns_
TLLDV ALE Low to Valid Data In 350 8TCLCL-150 ns
TAVDV Address to Valid Data In 398 9TCLCL-165 ns
TLLWL ALE Low to RD or WR Low 137 237 3TCLCL-50 3TCLCL+50 ns
TAVWL Address Valid to Read or Write Low 120 4TCLCL-130 ns
TOVWX Data Valid to WR Transition 2 TCLCL-60 ns
TWHOX Data Hold after WR 12 TCLCL-50 ns
TRLAZ RD Low to Address Float 0 0 ns
TWHLH RD or WR High to ALE High 23 103 TCLCL-40 TCLCL+40 ns
TOVWH Data Valid to WR (Setup Time) 288 7TCLCL-150 ns
10-202
inter UPI-452
EXTERNAL DATA MEMORY READ CYCLE
ALE~
-- r----------------~I~
TWHLHCJ-----\
~ ____ _J
I
\\.. _ _- . J1
14
. 1 - - - - TLLDV - - - - - - I
PORTO
PORT2 _ _...J P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
231428-19
EXTERNAL PROGRAM MEMORY READ CYCLE.
TLHLL ......
ALE
·~~t----TPLPH ----+I
PORTO
PORT2 _ _-'~_ _ _ _~~~_ _ _ _ _J~_ _ _ _~A~8_-~A~1~5________
231428-20
10-203
inter UPI-452
EXTERNAL DATA MEMORY WRITE CYCLE
ALE.
PSENJ
.-.rr___________________ ~_H_L_H-_L~~
1 \...
______ _J
'''''_ _-'1
I+---+-~-TOVWH ---f4-I~HOX
r---r~_-"\l
PORTO DATA OUT
PORT2 _ _ _J P2.0 - P2.7 OR A8 - A15 FROM DPH A8-A15 FROM PCH
231428-21
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION I a 2 3 4 5 6 7 B
.,<" . n n n n n n n n n n n n n n n n n n I
-~~~~~~~~~~~~~~~~~~~
_ _ _ _--iI-lXLXL -I
CLOCK
~rlXHOX
OUTPUT DATA \'--__~ ""__~ '-__-JX 3 X 4 X 5 X 6 X 7 I
t
WRITE TO SBUF
t
SETTI
INPUT DATA _ _ _ _ _J
t
t
CLEAR Rl
SET Rl
231428-22
10-204
inter UPI-452
EXTERNAL CLOCK DRIVE
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency 3.5 16 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
TCLCH Rise Time 20 ns
TCHCL Fall Time 20 ns
NOTE:
External clock timings are sampled, not tested on ali parts.
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: T A = O·C to 70·C; Vee = 5V ± 10 %; V55 = OV; Load Capacitance = 80 pF
16MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 750 12TCLCL ns
TOVXH Output Data Setup to Clock Rising Edge 492 1OTCLCL -133 ns
TXHOX Output Data Hold after Clock Rising Edge 8 2TCLCL-117 ns
TXHDX Input Data Hold after Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 492 1OTCLCL -133 ns
EXTERNAL CLOCK DRIVE WAVEFORM
Vee-0.5 - - - - ~~:-:--"'"
0.45V
231428-23
AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS
Vee-0.5 --V 0.2 Vee+0.9
0.45VJ\_0_.2_V.,,:e::;e_-0_._
1------'.
>C TIMING REFERENCE
POINTS
231428-24 . 231428-25
AC inputs during testing are driven at Vee -0.5V for a logic "1" For timing purposes a port pin is no longer floating when a
and OA5V for a logic "0". Timing measurements are made at VIH 100 mV change from load voltage occurs, and begins to float
min. for a logic "1" and VIL max. for a logic "0". when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/IOH <: ± 20 rnA.
10-205
intJ UPI-4S2
HLD/HLDA WAVEFORMS
Arbiter Mode
HLD -----.~. THMIN ----+I. V,.....---------
I - THLAL 114-.----TAMIN I - THHAH =tr-------
231428-26
Requestor Mode
HLD _ _ _ .....If( j
HLDA _ _~{,~_
I- TAHHL-----+l-
,,,..,-----
231428-31
HLD/HLDA TIMINGS
Test Conditions: TA = O·C to +70·C; Vee = 5V ±10%, Vss = OV; Load Capacitance = 80 pF
16MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TUlAIPt.1 ~I"\'"
I I ItVIII .. HLD Pulss \Nidth 350 AT"'" ,",I I
.... lvL.vL.-r: IUU liS
TAMIN HLDA Pulse Width 350 4TCLCL+100 ns
THHAH HLD to HLDA Delay if 350 4TCLCL-100 4TCLCL+100 ns
HLDA is Granted
THLAL HLD to HLDA Delay 350 4TCLCL-100 4TCLCL+100 ns
TAHHL HLDA Inactive to 150 4TCLCL-100 ns
HLDActive
HOST PORT WAVEFORMS
Tee
)
TRV
Tee
f
~
TDR
~TDH
DATA )
DRQIN
DRQOUT
231428-27
10·206
inter UPI-4S2
HOST PORT TIMINGS
Test Conditions: TA = O°C to 70·C; Vee = 5V ±10%; Vss = OV; Load Capacitance = 80 pF
16 MHzOsc Variable Oscillator
Symbol Parameter Units
Min Max Min Max
TCC Cycle Time 375 6TCLCL ns
TPW Command Pulse Width 100 100 ns
TRV Recovery Time 60 60 ns
TAS Address Setup Time 5 5 ns
TAH Address Hold Time 30 30 ns
TOS Write Data Setup Time 30 30 ns
TOHw Write Data Hold Time 5 5 ns
TOHR Read Data Hold Time 5 40 5 40 ns
TOV READ Active to Read 85 92 nson ns
Data Valid Delay 12 MHz Part
TDR WRITE Inactive to Read 300 4.8TCLCL ns
Data Valid Delay
(Applies only to Host
Control SFR)
TRa READ or WRITE Active 150 150 ns
to DRaiN or DRaOUT Delay
PROGRAMMING MODES ERASURE CHARACTERISTICS
Caution: Exceeding 14V on Vpp will permanently The erasure characteristics are such that erasure
damage the device. begins to occur upon exposure to light with wave-
lengths shorter than approximately 4000 Angstroms
Initially, all bits of the EPROM are in the "1" state. (A). It should be noted that sunlight and certain
Data is introduced by selectively programming "Os" types of fluorescent lamps have wavelengths in the
into the desired bit locations. Although only "Os". will 3000A-4000A range. Data shows that constant ex-
be programmed, both "1 s" and "Os" can be present posure to room level fluorescent lighting could erase
in the data word. The only way to change a "0" to a the EPROM in approximately three years, while it
"1" is by ultraviolet light exposure (Cerdip would take approximately one week to cause era-
EPROMs). sure when exposed to direct sunlight. If the EPROM
is to .be exposed to these types of lighting conditions
This device is in the programming mode when Vpp is
for extended periods of time, opaque labels should
raised to its programming voltage and ALE/PGM are
be placed over the window to prevent unintentional
both at TIL-low. The data to be programmed is ap-
erasure.
plied 8 bits in parallel to the Port 0 pins. The levels
required for the address and data inputs are TIL. The recommended erasure procedure is exposure
The address is applied to Port 1 and 2. to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
Program Verify intensity x exposure time) for erasure should be a
A verify should be performed on the programmed minimum of fifteen (15) Wsec/cm 2. The erasUre
bits to determine that they have been correctly pro- time with this dosage is approximately 15 to 20 min-
grammed. The verify is performed with OE at VIL, utes using an ultraviolet lamp with a 12,000 /LW/cm 2
PGM at VIH and Vpp and Vee at their programming power rating. The EPROM should be placed within
voltages. one inch of the lamp tubes during erasure. The maxi-
mum integrated dose an EPROM can be exposed to
inteligent IdentifierTM Mode without damage is 7258 Wsec/cm 2 (1 week @
12000 /LW/cm2), Exposure of the EPROM to high
inteligent IdentifierTM Mode is not supported on the intensity UV light for longer periods may cause per-
87C452P piggyback EPROM device. ' manent damage.
10-207
UPI-4S2
DEVICE
FAILED
DEVICE
FAILED
231428-29
Figure 4. inteligent Programming™ Flowchart
inteligent Programming™ Algorithm duration of the initial PGM pulse(s) is one millisec-
ond, which will then be followed by a longer overpro-
The inteligent Programming Algorithm, a standard in gram pulse of length 3X ms. X is an iteration counter
the industry for the past few years, is required for all and is equal to the number of the initial one millisec-
of Intel's 12.5V DERDEP EPROMs. Plastic amd ond pulses applied to a particular location, before a
PLCC EPROMs may also be programmed using this correct verify occurs. Up to 25 one-millisecond puls-
method. A flowchart of the inteligent Programming es per byte are provided for before the overprogram
Algorithm is shown in Figure 4. pulse is applied.
The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
10-208
UPI-452
The entire sequence of program pulses and byte verifications is performed at Vcc· = 6.0V and Vpp =
12.5V. When the inteligent Programming cycle has been completed, all bytes should be compared to the
. original data with Vee = Vpp = 5.0V.
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
PORT I.PORT2 ~C~AgDD~REgSStO~-j'~2=}-----t::!A~DD~R~ES~S~O~-~'2~:>----
TAVQV -
PORTO---t-C:JD~~!A~IN=:>-t--------(JD~AT~A~O~UT~1-----
J TGHDX-
~TDVGl_
_ TAVGl :-
I-
TGHAX I- TElQV
I - "1
Ll
TEHQZ
----~-I~~~~ I~,--------~--~~TD-H-AX-~----
AlE/PGM I
-j ~,TPHGl
+:~~~l -ITEHSH
1- TDXOl- 1
·1
231428-30
A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C (see EPROM PROGRAMMING D.C. CHARACTERISTICS for Vee and Vpp Voltages)
12MHzOSC
Symbol Parameter Test Conditlons*(1)
Min Max Unit
TAVGL Address Setup to PGM 2.9 J.l.s
TDXOL OE Setup from Data Float 2.0 J.l.s
TDVGL Data Setup to PGM 3.8 J.l.s
TOHAX Address Hold after OE 0 J.l.s
TGHDX· Data Hold after PGM 2.0 ns
TEHOZ Data Float after OE 0 1.6 J.l.s (Note 3)
TOHAX Address Hold after PGM 0 J.l.s
TPHGL Vpp Setup to PGM 2.0 J.l.s
TCHGL Vee Setup to PGM 2.0 J.l.s
TEHSH OE Setup to Vpp and Vee 2.0 J.l.s
TGLGH PGM Pulse Width 0.95 1.05 ms inteligent Programming
TAVQV Address to Data Valid 3.0 J.l.s
TOPW PGM Overprogram Pulse Width 2.85 78.75 ms (Note 2)
TELOV Data Valid from OE 2.0 J.l.s
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from 2.85 ms to 78.75 ms as a function of the iteration counter value X
(inteligent Programming Algorithm only).
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
4. The maximum current value is· with Port 0 unloaded.
10-209
intJ UPI-452
D.C. PROGRAMMING CHARACTERISTICS TA = 25°C ±5%
Limits
Symbol Parameter Test Conditions*(1)
Min Max Unit
lee2(4) Vee Supply Current (Program and Verify) 150 mA
IpP2(4) Vpp Supply Current (Program) 50 mA CE = VIL
VID Ag Inteligent Identifier Voltage 11.5 12.5 V
Vpp inteligent Programming Algorithm 12.0 13.0 V CE = PGM = VIL
Vee inteligent Programming Algorithm 5.75 6.25 V
10-210
inter APPLICATION
NOTE
AP-70
November 1987
Using the Intel MCS®-51 Boolean
Processing Capabilities
JOHN WHARTON
MICROCONTROLLER APPLICATIONS
Order Number: 203830·001
10·211
AP-70
1.0 INTRODUCTION Table 1 summarizes the quantitative differences be-
tween the members of the MCS®-48 and 8051 families.
The Intel microcontroller family now has three new The 8751 contains 4K bytes of EPROM program mem-
members: the Intel® 8031, 8051, and 8751 single-chip ory fabricated on-chip, while the 8051 replaces the
microcomputers. These devices, shown in Figure I, will EPROM with 4K bytes of lower-cost mask-
allow whole new classes of products to benefit from programmed ROM. The 8031 has no program memory
recent advances in Integrated Electronics. Thanks to on-chip; instead, it accesses up to 64K bytes of program
Intel's new HMOS technology, they provide larger pro- memory from external memory. Otherwise, the three
gram and data memory spaces, more flexible I/O and new family membeJ,"S are identical. Throughout this
peripheral capabilities, greater speed, and lower system Note, the term "8051" will represent all members of the
cost than any previous-generation single-chip micro- 8051 Family, unless specifically stated otherwise.
computer.
The CPU in each microcomputer is one of the indus-
try's fastest and most efficient for numerical calcula-
tions on byte operands. But controllers often deal with
P1.0- - vee bits, not bytes: in the real world, switch contacts can
only be open or closed, indicators should be either lit or
P1.1- - po.o dark, motors are either turned on or off; and so forth.
P1.2 - - PO .. 1 For such control situations the most significant aspect
P1.3 - - PO.2
of the MCS®-51 architecture is its complete hardware
support for one-bit, or /loolean variables (named in
P1.4 - - PO.3 honor of MathematiCian George Boole) as a separate
P1.5 - - PO.4 data type.
P1.6- - PO.5
The 8051 incorporates a number of special features
PH - - PO.6 which support the direct manipulation and testing of
RST - - PO.7
individual bits and allow the use of single-bit variables
in performing logical operations. Taken together, these
P3.0/RXD - - VPP/EA features are referred to as the MCS-Sl Boolean Proces-
P3.1/TXD - -~/ALE sor. While the bit-processing capabilities alone would be
adequate to solve many' control applications, their true
p3.2iiNTci - - PSEN
power comes when they are used in conjunction with
P3.3/iNii - - P2.7 the microcomputer's byte-processing and numerical ca-
P3.4/TO - - P2.6
pabilities.
P3.51T1 - - P2.5 Many concepts embodied by the Boolean Processor will
P3.6/WR - - P2.4 certainly be new even to experienced microcomputer
system designers. The purpose of this Application Note
P3.7/iiii - - P2.3
is to explain these concepts and show how they are
XTAL2 - - P2.2 used.
XTAL1 - - P2.1
For detailed information on these parts refer to the
VSS - - P2.0 Intel Microcontroller Handbook, order number
210918. The instruction set, assembly language, and use
203830-1 of the 8051 assembler (ASM51) are further described iIi
the MCS®·51 Macro Assembler User's Guide for DOS
Figure 1. 8051 Family Pinout Diagram Systems, order number 122753.
Table 1. Features of Intel's Single-Chip Microcomputers
EPROM ROM External Program Data Instr. Input!
Interrupt Reg.
Program Program Program Memory Memory Cycle Output
Sources Banks
Memory Memory Memory (Int/Max) (Bytes) Time Pins
8748 8048 8035 1K4K 64 2.5 JLs 27 2 2
- 8049 8039 2K4K 128 1.36 JLs 27 2 2
8751 8051 8031 4K64K 128 1.0 JLs 32 5 4
10-212
inter AP-70
2.0 BOOLEAN PROCESSOR plex (albeit slower) ones, which in tum link together
eventually solving the problem at hand. A four-bit CPU
OPERATION executing multiple precision subroutines can, for exam-
The Boolean Processing capabilities of the 8051 are ple, perform 64-bit addition and subtraction. The sub-
based on concepts which have been around for some routines could in tum be building blocks for floating-
time. Digital computer systems of widely varying de- point multiplication and division routines. Eventually,
signs all have four functional elements in common (Fig- the four-bit CPU can simulate a far more complex "'vir-
ure 2): tual" machine.
• a central processor (CPU) with the control, timing, In fact, any digital computer with the above four func-
and logic circuits needed to execute stored instruc- tional elements can (given time) complete any algo-
tions: rithm (though the proverbial room full of chimpanzees
• a memory to store the sequence of instructions mak- at word processors might first re-create Shakespeare's
ing up a program or algorithm: classics and this Application Note)! This fact offers lit-
• data memory to store variables used by the pro- tle consolation to product designers who want pro-
gram: grams to run as quickly as possible. By definition, a
and real-time contrql algorithm must proceed quickly
enough to meet the preordained speed constraints of
• some means of communicating with the outside other equipment.
world.
One of the factors determining how long it will take a
The CPU usually includes one or more accumulators or microcomputer to complete a given chore is the num-
special registers for computing or storing values during ber of instructions it must execute. What makes a given
program execution. The instruction set of ~uch a computer architecture particularly well- or poorly-suit-
processor generally includes, at a minimum, operation ed for a class of problems is how well its instruction set
classes to perform arithmetic or logical functions on matches the tasks to be performed. The better the
program variables, move variables from one place to "primitive" operations correspond to the steps taken by
another, cause program execution to jump or condi- the control algorithm, the lower the number of instruc-
tionally branch based on register or variable states, and tions needed, and the quicker the program will run. All
instructions to call and return from subroutines. The else being equal, a CPU supporting 64-bit arithmetic
program and data memory functions sometimes share a directly could clearly perform floating-point math fast-
single memory space, but this is no~ always the case. er than a machine bogged-down by multiple-precision
When the address spaces are separated, program and subroutines. In the same way, direct support for bit
data memory need not even have the same basic word manipulation naturally leads to more efficient pro~
width. grams handling the binary input and output conditions
inherent in digital control problems.
A digital computer's flexibility comes in part from
combining simple fast operations to produce more com-
TIMING &
CONTROL
PROGRAM
MEMORY
ACCUMULATOR
& REGISTERS
INPUTI REAL
OUTPUT WORLD
PORTS
CENTRAL
DATA
PROCESSING
MEMORY
UNIT
203830-2
Figure 2. Block Diagram for Abstract Digital Computer
10-213
AP·70
Processing Elements tions of Table 2, several sophisticated program control
features like multiple addressing modes, subroutine
The introduction stated that the 8051 's bit-handling ca- nesting, and a two-level interrupt structure are useful in
pabilities alone would be sufficient to solve some con- s~ructuring Boolean Processor-based programs.
trol applications. Let's see how the four basic elements
of a digital computer-a CPU with associated registers, Boolean instructions are one, two, or three bytes long,
program memory, addressable data RAM, and I/O ca- depending on what function they perform. Those in-
pability-relate to Boolean variables. volving only the carry flag have either a single-byte
opcode or an opcode followed by a conditional-branch
CPU. The 8051 CPU incorporates special logic devoted destination byte (Figure 3a). The more general instruc-
to executing several bit-wide operations. All told, there tions add a "direct address" byte after the opcode to
are 17 such instructions, all listed in Table 2. Not specify the bit affected, yielding two or three byte en-
shown are 94 other (mostly byte-oriented) 8051 instruc- codings (Figure 3b). Though this format allows poten-
tions. tially 256 directly addressable bit locations, not all of
them are implemented in the 8051 family.
Program Memory. Bit-processing instructions are
fetched from the same program memory as other arith-
metic and logical operations. In addition to the instruc-
opcode
Table 2. MCS·S1TM Boolean
Processing Instruction Subset SETBC
Mnemonic Description Byte eyc CLRC
SETB C Set Carry flag 1 1 CPLC
SETB bit Set direct Bit 2 1
CLR
CLR
C
bit
Clear Carry flag
Clear direct bit
1
2
1
1
opcode I displacement I
CPL C Complement Carry flag 1 1
CPL bit Complement direct bit 2 1 JC rei
MOV C.bit Move direct bit to Carry flag 2 1
jNC rei
MOV bit.C Move Carry flag to direct bit 2 2
a.) Carry Control and Test Instructions
ANL C.bit AND direct bit to Carry flag 2 2
ANL C.bit AND complement of direct 2 2
ORL C.bit
bit to Carry flag
OR direct bit to Carry flag 2 2
opcode I I bit address
ORL C.bit OR complement of direct 2 2
bit to Carry flag SETB bit
CLR bit
JC rei Jump if Carry is flag is set 2 2
CPL bit
JNC rei Jump if No Carry flag 2 2
ANLC, bit
JB bit.rel Jump if direct Bit set 3 2
JNB bit.rel Jump if direct Bit Not set 3 2 ANL C,/ bit
JBC bit.rel Jump if direct Bit is set & 3 2 ORLC, bit
Clear bit ORL C,/ bit
Address mode abbreviations MOVC, bit
MOV bit,C
C-Carry flag.
bit-128 software flags, any 1/0 pin, control or status
bit.
rei-Ali conditional jumps include an 8-bit offset byte.
opcode I I bit address I displacement I
JB bit, rei
Range is + 127 -128 bytes relative to first byte of the
JNB bit, rei
following instruction.
JBC bit, rei
All mnemonics copyrighted@ Intel Corporation 1980.
b.) Bit Manipulation and Test Instructions
Figure 3. Bit Addressing Instruction Formats
10-214
AP-70
Dtrect Bit Addr••••• Hardware
RAM B~te Regl.ter
Byte (MSB) (LSB) Addr••• (MSB) (LSB) Symbol
7FH~
1-";:;'" I~
OFFH
OFOH F7 FO B
2FH 7F 7E 7D 7C 7B 7A 79 78
2EH n 76 75 74 73 72 71 70 OEOH E7 EO ACC
2DH 6F 6E 6D 6C 6B 6A 69 68
2CH 67 66 65 64 63 62 61 60 ODOH D7 DO PSW
2BH SF 5E 5D 5C 5B SA 59 58
2AH 57 56 55 54 53 52 51 50 OB8H B8 tP
29H 4F 4E 4D 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40 OBOH B7 BO P3
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 3D OA8H AF A8 tE
25H 2F 2E 2D 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20 OAOH A7 AO P2
23H IF IE lD lC lB lA 19 18
22H 17 16 15 14 13 12 11 10 98H 9F 98 SCON
21H OF DE OD OC DB OA 09 08
20H 07 06 05 04 03 02 01 DO 90H 97 90 PI
lFH
Bank 3
18H
17H
88H 8F 88 TCON
10H Bank 2
OFH
D8H Bank 1
07H
80H 87 80 PO
BankO
DO
203830-3
a.):RAM Bit Addresses· b.) Special Function Register Bit Addresses
Figure 4. Bit Address Maps
Data Memory. The instructions in Figure 3b can oper- Input/Output. All 32 I/O pins can be addressed as indi-
ate directly upon 144 general purpose bits forming the vidual inputs, outputs, or both, in any combination.
Boolean processor "RAM." These bits can be used as Any pin can be a control strobe output, status (Test)
software flags or to store program variable~. Two oper- input, or serial I/O link implemented via software. An
and instructions use the CPU's carry flag ("C") as a additional 33 individually addressable bits reconfigure,
special one-bit register: in a sense, the carry is a "Boole- control, and monitor the status of the CPU and all on-
an accumulator" for logical operations and data trans- chip peripheral functions (timer counters, serial port
fers. modes, interrupt logic, and so forth).
10-215
inter AP-70
(MSB) (LSB) OV PSW.2 Overflow flag.
Settcleared by hardware dur-
I CY lAC I FO RS1 RSO OV
ing arithmetic instructions to
Symbol Position Name and Significance indicate overflow conditions.
CY PSW.7 Carry flag. PSW.1 (reserved)
Settcleared by hardware· or P PSW.O Parity flag.
software .during certain arith- Set/cleared by hardware each
metic and logical instructions. instruction cycle to indicate an
AC PSW.6 Auxiliary Carry flag. odd/even number of "one"
Settcleared by hardware dur- bits in the accumulator, i.e.,
ing addition or subtraction in- even parity:
structions to indicate carry or Note- the contents of (RS1, RSO)
borrow out of bit S. enable the working register
FO PSW.5 Flag O. banks as follows:
Settcleared/tested . by soft- (0,0) - Bank 0 (OOH-07H)
ware as a user-defined status (0,1) - Bank 1 (OBH-OFH)
flag. (1,0)-Bank2 (19H-17H)
(1,1) - Bank S (1BH-1FH)
RS1 PSW.4 Register bank Select control
bits.
RSO PSW.S 1 & O. Settcleared by software
to determine working register
bank (see Note).
Figure 5. PSW-Program Status Word Organization
(MSB) (LSB)
INT1 PS.S Interrupt 1 input pin.
I RD I WR I T1 I TO IINT1 I INTO I TXD I RXD I Low-level or falling-edge trig-
gered.
Symbol Position Name and Significance Interrupt 0 input pin.
INTO PS.2
RD PS.7 Read data control output. Low-level or falling-edge trig-
Active low pulse generated by gered.
hardware when external data
TXD PS.1 Transmit Data pin for serial
memory is read. port in UART mode. Clock out-
WR PS.6 Write data control output. put in shift register mode.
Active low pulse generated by
RXD PS.O Receive Data pin for serial
hardware when external data
port in UART mode. Data I/O
memory is written.
pin in shift register mode.
T1 PS.5 Timer/counter 1 external input
or test pin.
TO PS.4 Timer/counter 0 external input
or test pin.
Figure 6. P3-Alternate I/O Functions of Port 3
Direct Bit Addressing Bit addresses between 128 and 255 (80H and OFFH)
correspond to bits in a number of special registers,
The most significant bit of the direct address byte se- mostly used for I/O or peripheral control. These posi-
lects one of two groups of bits: Values between 0 and tions are numbered with a different scheme than RAM:
127 (DOH and 7FH) defme bits in a block of 32 bytes of the five high-order address bits match those of the reg-
on-chip RAM, between RAM addresses 20H and 2FH ister's own address, while the three low-order bits iden-
(Figure 4a). They are numbered consecutively from the tify the bit position within that register (Figure4b).
lowest-order byte'S lowest-order bit through the high-
est-order byte'S highest-order bit.
10-216
infef AP-70
Notice the column labeled "Symbol" in Figure 5. Bits the five bits not implemented in IE and IP should not
with special meanings in the PSW and other registers be accessed: they can not be used as sof~ware flags.
have corresponding symbolic names. General-purpose
(as opposed to carry-specific) instructions may access Addressable Register Set. There are 20 special function
the carry like any other bit by using the mnemonic CY registers in the 8051, but the advantages of bit address-
in place of C, PO, PI, P2, and P3 are the 8051's four ing only relate to the II described below. Five poten-
I/O ports: secondary functions assigned to each of the tially bit-addressable register addresses (OCOH, OC8H,
eight pins of P3 are shown in Figure 6. OD8H, OE8H, & OF8H) are being reserved for possible
future expansion in microcomputers based on the
Figure 7 shows the last four bit addressable registers. MCS-51 architecture. Reading or writing non-existent
TCON (Timer Control) and SCON (Serial port Con- registers in the 8051 series is pointless, and may cause
trol) control and monitor the corresponding peripher- unpredictable results. Byte-wide logical operations can
als, while IE (Interrupt Enable) and IP (Interrupt Pri- be used to manipulate bits in all non-bit addressable
ority) enable and prioritize the five hardware interrupt registers and RAM.
sources. Like the reserved hardware register addresses,
10-217
intJ AP-70
(MSB) (LSB)
IE1 TCON.3 Interrupt 1 Edge flag.
ITF1 I TR1 I TFO I TRO IIE1 IIT1 I lEO liTO I Set by hardware when exter-
nal interrupt edge detected.
Symbol Position Name and Significance Cleared when interrupt pro-
TF1 TCON.7 Timer 1 overflow Flag. cessed.
Set by hardware on timer/ In TCON.2 Interrupt 1 Type control bit.
counter overflow. Cleared Set/cleared by software to
when interrupt processed. specify falling edge/low level
TR1 TCON.a Timer 1 Run control bit. triggered external interrupts.
Set/cleared by software to turn lEO rCON.1 Interrupt 0 Edge flag:
timer/counter on/off. Set by hardware when exter-
TFO TCON.5 Timer 0 overflow Flag. nal interrupt edge detected.
Set by hardware on timer/ 'Cleared when interrupt pro-
counter overflow. Cleared cessed.
when interrupt processed. ITO TCON.O Interrupt 0 Type control bit.
TRO TCONA Timer 0 Run control bit. Set/cleared by software to
Set/cleared by software to turn specify falling edge/low level
timer/counter on/off. triggered external interrupts.
a.) TCON-Timer/Counter Control/Status Register
(MSB) (LSB) RBB SCON.2 Receive Bit B.
ISMO I SM1 I SM21 REN I TBS I RBSI TI I RI I Set/cleared by hardware to in-
dicate state of ninth data bit
Symbol Position Name and Significance received.
SMO SCON.7 Serial port Mode control bit o. TI SCON.1 Transmit Interrupt flag.
Set/cleared by software (see Set by hardware when byte
note). transmitted. Cleared by soft-
SM1 SCON.a Serial port Mode control bit 1. ware after servicing.
Set/cleared by software (see RI SCON.O Receive Interrupt flag.
note). Set by hardware when bytere-
SM2 SCON.5 Serial port Mode control bit 2. ceived. Cleared by software
Set by software to disable re- after servicing.
ception of frames for which bit Note- the state of (SMO, SM1)
B is zero. selec~s:
REN SCON.4 Receiver Enable control bit. (O,O)-Shift register I/O
Set/cleared by software to en- expansion.
able/disable serial data recep- (0,1 )-8-bit UART, variable
tion. data rate.
TBB SCON.3 Transmit Bit B. (1,O)-9-bit UART, fixed data
Set/cleared by hardware to de- rate.
terminestate of ninth data bit (1,1 )":"'9-bit UART, variable
transmitted in 9-bit UART data rate.
mode.
b.) SCON--Serial Port Control/Status Register
Figure 7. Peripheral Configuration Registers
10-21B
AP-70
(MSB) (lSB)
ES ET1 EX1 ET1 1 EXO 1
Symbol Position Name and Significance, EX1 1E.2 Enable External interrupt 1
EA IE.? Enable All control bit. control bit. Set! cleared by
Cleared by software to disable software to enable/disable in-
all interrupts, independent of terrupts from INT1.
the state of IE.4-IE.O. ETO IE.1 Enable Tilller 0 control bit.
1E.6 (reserved) Set! cleared by software to en-
1E.5 able/disable interrupts from
timer / counter O.
ES IE.4 Enable Serial port control bit.
Set/cleared by software to en- EXO IE.O Enable External interrupt 0
able/disable interrupts from TI control bit. Set/cleared by
or RI flags. software to enable/disable in-
terrupts from INTO.
ET1 IE.3 Enable Timer 1 control bit.
Set!cleared by software to en-
able/disable interrupts from
timer/counter 1.
c.) IE-Interrupt Enable Register
(MSB) (lSB)
1-1-1 PS PT1 PX1 PTO PXO
Symbol Position Name and Significance PX1 IP.2
External interrupt 1 Priority
IP.? (reserved) control bit. Set/cleared by
IP.6 (reserved) software to specify high/low
IP.5 (reserved) priority interrupts for INT1.
PS IP.4 Serial port Priority control bit. PTO IP.1 Timer 0 Priority control bit.
Set! cleared by software to Set/ cleared by software to
specify high/low priority inter- specify high/low priority inter-
rupts for Serial port. rupts for timer/counter O.
PT1 IP.3 Timer 1 Priority control bit. PXO IP.O External interrupt 0 Priority
Set/cleared by software to control bit. Set/cleared by
specify high/low priority inter- software to specify high/low
rupts for timer/counter 1. priority interrupts for INTO.
d.) IP-Interrupt Priority Control Register
Figure ? Peripheral Configuration Registers (Continued)
The accumulator and B registers (A and B) are normal- instructions that manipulate these bits. It may be help-
ly involved in byte-wide arithmetic, but their individual ful to refer back to Table 2 while reading this section.
bits can also be used as 16 general software flags. Add-
ed with the 128 flags in RAM, this gives 144 general State Control. Addressable bits or flags may be set,
purpose variables for bit-intensive programs. The pro- cleared, or logically complemented in one instruction
gram status word (PSW) in Figure 5 is a collection of cycle with the two-byte instructions SETB, CLR, and
flags and machine status bits including the carry flag CPL. (The "B" affixed to SETB distinguishes it from
itself. Byte operations acting on the PSW can therefore the assembler "SET" directive used for symbol defini-
affect the carry. tion.) SETB and CLR are analogous to loading a bit
with a constant: 1 or O. Single byte versions perform the
same three operations on the carry.
Instruction Set The MCS-51 assembly language specifies a bit address
Having looked at the bit variables available to the Boo- in any of three ways:
lean Processor, we will now look at the four classes of • by a number or expression corresponding to the di-
rect bit address (0-255):
10-219
intJ AP-70
• by the name or address of the register containing the Logical Operations. Four instructions perform the logi-
bit, the dot operator symbol (a period: "."), and the cal-AND and logical-OR operations between the carry
bit's position in the register (7 -0): and another bit, and leave the results in the carry. The
• in the case of control and 'status registers, by the instruction mnemonics are ANL and ORL;' the absence
predefined assembler symbols listed in the first col- or presence of a slash mark ("/") before the source
umns'ofFigures 5-7. operand indicates whether to use the positive-logic val-
ue or the logical complement of the addressed bit. (The
Bits may also be given user-defined names with the as- source operand itself is never affected.)
sembler "BIT" directive and any of the above tech-
niques. For example, bit 5 of the PSW may be cleared Bit-test Instructions. The conditional jump instructions
by any of the four instructions. "JC rei" (Jump on Carry) and "JNC rei" (Jump on
Not Carry) test the state of the carry flag, branching if
USR_FLG BIT PSW.5 User Symbol Definition it is a one or zero, respectively. (The letters "rei" de-
note relative code addressing.) The three-byte instruc-
CLR OD5H Absolute AddreSSing tions "JB bit.rel" and "JNB bit. rei" (Jump on Bit and
CLR PSW.5 Use of Dot Operator Jump on Not Bit) test the state of any addressable bit in
CLR FO Pre-Defined Assembler a similar manner. A fifth instruction combines the
Symbol Jump ~m Bit and Clear operations. "JBC bit. rei" condi-
CLR USR_FLG User-Defined Symbol tionally branches to the indicated address, then clears
the bit in the same two cycle instruction. This operation
Data Transfers. The two-byte MOV instructions can is the same as the MCS-48 "JTF" instructions.
transport any addressable bit to the carry in one cycle,
or copy the carry to the bit in two cycles. A bit can be All 8051 conditional jump instructions use program
moved between two arbitrary locations via the carry by counter-relative addressing, and all execute in two cy-
combining the two instructions. (If necessary, push and cles. The last instruction byte encodes a signed dis-
pop the PSW to preserve the previous contents of the placement ranging from -128 to + 127. During execu-
carry.) These instructions can replace the multi-instruc- tion, the CPU adds this value to the incremented pro-
tion sequence of Figure 8, a program structure appear- gram counter to produce the jump destination. Put an-
ing in controller applications, whenever flags or outputs other way, a conditional jump to the immediately fol-
are conditionally switched on or off. - iowing instruction wouid encode OOH in the offset byte.
A section of program or subroutine written using only
relative jumps to nearby addresses will have the same
machine code independent of the code's location. An
assembled routine maybe repositioned anywhere in
memory, even crossing memory page boundaries, with-
out having to modify the program or recompute desti-
ISOLATE nation addresses. To facilitate this flexibility, there is iui
SOURCE unconditional "Short Jump" (SJMP) which uses rela-
BIT
tive addressing as well. Since a programmer would have
quite a chore trying to compute relative offset values
from one instruction to another, ASM51 automatically
computes the displacement needed given only the desti-
NO nation address or label. An error message will alert the
programmer if the destination is "out of range."
The so-called "Bit Test" instructions implemented on
many other microprocessors simply perform the logi-
SET CLEAR cal-AND operation between a byte variable and a con-
DESTINATION DESTINATION
BIT BIT stant mask, and set or clear a zero flag depending on
the result. This is essentially equivalent to the 8051
"MOV C.bit" instruction. A second instruction'is then
needed to conditionally branch based on the state of the
zero flag. This does not constitute abstract bit-address-
ing in the MCS-51 sense. A flag exists only as a field
203830-4
Figure 8. Bit Transfer Instruction Operation
10-220
AP-70
within a register: to reference a bit the programmer Table 3. Other Instructions Affecting
must know and specify both the encompassing register the Carry Flag
and the bit's position therein. This constraint severely
Mnemonic Description Byte eyc
limits the flexibility of symbolic bit addressing and re-
duces the machine's code-efficiency and speed. ADD A,Rn Add register to 1
Accumulator
Interaction with Other Instructions. The carry flag is ADD A,direct Add direct byte to 2
also affected by the instructions listed in Table 3. It can Accumulator
be rotated through the accumulator, and altered as a ADD A,@Ri Add indirect RAM to
side effect of arithmetic instructions. Refer to the Us- Accumulator
er's Manual for details on how these instructions oper- ADD A,#data Add immediate data 2
ate. to Accumulator
AD DC A,Rn Add register to
Accumulator with
Simple Instruction Combinations Carry flag
ADDC A,direct Add direct byte to 2
By combining general purpose bit operations with cer- Accumulator with
tain addressable bits, one can "custom build" several Carry flag
hundred useful instructions. All eight bits of the PSW ADDC A,@Ri Add indirect RAM to
can be tested directly with conditional jump instruc- Accumulator with
tions to monitor (among other things) parity and over- Carry flag
flow status. Programmers can take advantage of 128 ADDC A,#data Add immediate data 2
software flags to keep track of operating modes, re- to Acc with Carry flag
source usage, and so forth. SUBB A,Rn Subtract register from
Accumulator with
The Boolean instructions are also the most efficient borrow
way to control or reconfigure peripheral and I/O regis- SUBB A,direct Subtract direct byte 2
ters. All 32 I/O lines become "test pins," for example, from Acc with borrow
tested by conditional jump instructions. Any output pin SUBB A,@Ri Subtract indirect RAM
can be toggled (complemented) in a single instruction from Acc with borrow
cycle. Setting or clearing the Timer Run flags (TRO and SUBB A,#data Subtract immediate 2
TRI) tum the timer/counters on or off; polling the data from Acc with
same flags elsewhere lets the program determine if a borrow
timer is running. The respective overflow flags (TFO MUL AB Multiply A & B 4
and TFI) can be tested to determine when the desired DIV AB Divide A by B 4
period or count has elapsed, then cleared in preparation DA A Decimal Adjust
for the next repetition. (For the record, these bits are all Accumulator
part of the TCON register, Figure 7a. Thanks to sym-
RLC A Rotate Accumulator
bolic bit addressing, the programmer only needs to re-
Left through the Carry
member the mnemonic associated with each function.
flag
In other words, don't bother memorizing control word
RRC A Rotate Accumulator
layouts.)
Right through Carry
flag
In the MCS-48 family, instructions corresponding to
some of the above. functions require specific opcodes. CJNE A,direct.rel Compare direct byte 3 2
Ten different opcodes serve to clear complement the to Acc &Jump if. Not
software flags FO and Fl, enable/disable each inter- Equal
rupt, and start/stop the timer. In the 8051 instruction CJNE A,#data.rel Compare immediate 3 2
set, just three opcodes (SETB, CLR, CPL) with a direct to Acc &Jump if Not
bit address appended perform the same functions. Two Equal
test instructions (JB and JNB) can be combined with CJNE Rn,#data.rel Compare immed to 3 2
bit addresses to test the software flags, the 8048 I/O register &Jump if Not
pins TO, TI, and INT, and the eight accumulator bits, Equal
replacing 15' more different instructions. CJNE @Ri,#data.rel Compare immed to 3 2
indirect & Jump if Not
Table 4a shows how 8051 programs implement soft- Equal
ware flag and machine control functions associated
with special opcodes in the 8048. In every case the All mnemonics copyrighted © Intel Corporation 1980.
MCS-51 solution requires the same number of machine
cycles, and executes 2.5 times faster.
10-221
intJ AP-70
Table 4a. Contrasting 8048 and 8051 Blt;Control and Testing Instructions
8048 8x51
Bytes Cycles ""Sec Bytes Cycles Be ""Sec
Instruction Instruction
Flag Control
CLR C 1 1 2.5 CLR C 1 1
CPL FO 1 1 2.5 CPL FO 2 1
Flag Testing
JNC offset 2 2 5.0 JNC rei 2 2
JFO offset 2 2 5.0 JB FO.rel 3 2
JB7 offset 2 2 5.0 JB ACC.7.rel 3 2
Peripheral POlling
JTO offset 2 2 5.0 JB TO.rel 3 2
JN1 offset 2 2 5.0 JNB INTO.tel 3 2
JTF offset 2 2 5.0 JBC TFO.rel 3 2
Machine and Peripheral Control
STRT T 1 1 2.5 SETB TRO 2 1
EN 1 1 1 2.5 . SETB EXO 2 1
DIS TCNT1 1 1 2.5 CLR ETO 2 1
Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions
8048 8051
Bytes Cycles ""Sec Bytes Cycles Be ""Sec
Instruction Instruction
Flag Control
Set carry
CLR C
CPL C = 2 2 5.0 SETB C 1 1
Set Software Flag
CLR FO
CPL FO = 2 2 5.0 SETB FO 2 1
Turn Off Output Pin
ANL P1.#OFBH = 2 2 5.0 CLR P1.2 2 1
Complement Output Pin
IN AP1
XRL A#04H
OUTL P1.A = 4 6 15.0 CPL P1.2 2 1
Clear Flag in RAM
MOV RO.#FLGADR
MOV A@RO
ANL A#FLGMASK
MOV @RO.A = 6 6 15.0 CLR ·USER_FLG 2 1
10-222
AP-70
Table 4b Replacing 8048 Instruction Sequences with Single 8x51 Instructions (Continued)
8048 8x51
Bytes Cycles ,.,.Sec Bytes Cycles & ,.,.Sec
Instruction Instruction
Flag Testing:
Jump if Software Flag is 0
JFO $+4
JMP offset = 4 4 10.0 JNB FO.rel 3 2
Jump if Accumulator bit is 0
CPL A
JB7 offset
CPL A = 4 4 10.0 JNB ACC.7.rel 3 2
Peripheral Polling
Test if Input Pin is Grounded
IN A.P1
CPL A
JB3 offset = 4 5 12.5 JNB P1.3.rel 3 2
Test if Interrupt Pin is High
JN1 $+4
JMP offset = 4 4 10.0 JB INTO.rel 3 2
3.0 BOOLEAN PROCESSOR Combining Boolean and byte-wide instructions can
APPLICATIONS produce great synergy. An MCS-5l based application
will prove to be:
So what? Then what does all this buy you? • simpler to write since the architecture correlates
more closely with the problems being solved:
Qualitatively, nothing. All the same capabilities could
• easier to debug because more individual instructions
be (and often have been) implemented on other ma- have no unexpected or undesirable side-effects:
chines using awkward sequences of other basic opera-
tions. As mentioned earlier, any CPU can solve any • more byte efficient due to direct bit addressing and
problem given enough time. program counter relative branching:
• faster running because fewer bytes of instruction
Quantitatively, the differences· between a solution al- need to be fetched and fewer conditional jumps are
lowed by the 8051 and those required by previous ar- processed:
chitectures are numerous. What the S051 Family buys • lower cost because of the high level of system-inte-
you is a faster, cleaner, lower-cost solution to micro- gration within one component.
controller applications.
These rather unabashed claims of excellence shall not
The opcode space freed by condensing many specific
go unsubstantiated. The rest of this chapter examines
S04S instructions into a few general operations has been less trivial tasks simplified by the Boolean processor.
used to add new functionality to the MCS-51 architec- The first three compare the S051 with other micro-
ture-both for byte and bit operations. 144 software
processors; the last two go into S051-based system de-
flags replace the S04S's two. These flags (and the carry) signs in much greater depth.
may be directly set, not just cleared and complemented,
and all can be tested for either state, not just one. Oper-
ating mode bits previously inaccessible may be read,
tested, or saved. Situations where the· 8051 instruction Design Example # 1-Bit Permutation
set provides new capabilities are contrasted with S04S First off, we'll use the bit-transfer instructions to per-
instruction sequences in Table 4b. Here the S051 speed mute a lengthy pattern of bits.
advantage ranges from 5x to l5x!
10-223
intJ AP-70
A steadily increasing number of data communication Different microprocessor architectures would best im-
products use encoding methods to protect the security pement this type of permutation in different ways.
of sensitive information. By law, interstate financial Most approaches would share the steps of Figure lOa:
transactions involving the Federal banking system must • Initialize the Permutation Buffer to default state
be transmitted using the Federal Information Pro- (ones or zeroes):
cessing Data Encryption Standard (DES).
• Isolate the state of a bit of a byte from the Key
Basically, the DES combines eight bytes of "plaintext" Buffer. Depending on the CPU, this might be ac-
data (in binary, ASCII, or any other format) with a 56- complished by rotating a word of the Key Buffer
bit "key", producing a 64-bit encrypted value for trans- through a carry flag or testing a bit in memory or an
mission. At the receiving end the same algorithm is accumulator against a mask byte:
applied to the incoming data using the same key, repro- • Perform a conditional jump based on the carry or
ducing the original eight byte message. The algorithm zero flag if the Permutation Buffer default state is
used for these permutations is fixed; different user-de- correct:
fined keys ensure data privacy. • Otherwise reverse the corresponding bit in the per-
mutation buffer with logical operations and mask
It is not the purpose of this note to describe the DES in bytes.
any detail. Suffice it to say that encryption/decryption
is a long, iterative process consisting of rotations, exclu- Each step above may require several instructions. The
sive -OR operations, function table look-ups, and an last three steps must be repeated for all 48 bits. Most
extensive (and quite bizarre) sequence of bit permuta- microprocessors would spend 300 to 3,000 microsec-
tion, packing, and unpacking steps. (For further details onds on each of the 16 iterations.
refer to the June 21, 1979 issue of Electronics maga-
zine.) The bit manipulation steps are included, it is ru- Notice, though, that this flow chart looks a lot like
mored, to impede a general purpose digital supercom- Figure 8. The Boolean Processor can permute bits by
puter trying to "break" the code. Any algorithm imple- simply moving them from the source to the carry to the
menting the DES with previous generation micro- destination-a total of two instructions taking four
processors would spend virtually all of its time diddling bytes and three microseconds per bit. Assume the Shift-
bits. ed Key Buffer and Permutation Buffer beth reside.in
bit-addressable RAM, with the bits of the former as-
The bit manipulation performed is typified by the Key signed symbolic name~ SKB_l, SKB_2, ... SKB_
Schedule Calculation represented in Figure 9. This step 56, and that the bytes of the latter are named PB_I,
is repeated 16 times for each key used in the course of a ... PB_8. Then working from Figure 9, the software
transmission. In essence, a seven-byte, 56-bit "Shifted for the permutation algorithm would be that of Exam-
Key Buffer" is transformed into an eight-byte, "Permu- pIela. The total routine length would be 192 bytes,
tation Buffer" without altering the shifted Key. The requiring 144 microseconds.
arrows in Figure 9 indicate a few of the translation
steps. Only six bits of each byte of the Permutation
Buffer are used; the two high-order bits of each byte are
cleared. This means only 48 of the 56 Shifted Key Buff-
er bits are used in anyone iteration.
Permuted and Shifted 56-Bit Key Buffer
~ ~
---------------------"--------------------- --------------------"---------------------
14151111 21 2425
"" " 3334
PERMUTATION BYTE 1 PERM BYTE 2 PERM BYTE 3 PERM BYTE 4 BYTE 5 BYTE 6 PERM BYTE 7 PERM BYTE 8
203830-5
48-Bit Key KI
Figure 9. DES Key Schedule Transformation
10-224
inter AP-70
REPEAT
FOR EACH
BIT OF
SHIFTED
KEY
BUFFER
(48 TIMES)
SET PERMUTATION (LEAVE PERMUTATION
BUFFER BIT BUFFER BIT
PC2(1) CLEARED)
203830-6
Figure 10a. Flowchart for Key Permutation Attempted with a Byte Processor
10-225
Ap·70
~
I CLEAR ACCUMULATOR
I
LOAD BIT MAPPED ONTO BIT 5 OF
PERMUTATION BYTE INTO CARRY
I ROTATE LEFT INTO ACC.
I
LOAD BIT. MAPPED ONTO BIT 4
OF PERMUTATION BYTE INTO CARRY
REPEAT'
I ROTATE LEFT INTO ACC.
I FOR EACH
BYTE OF
PERMUTATION
BUFFER
(8 TIMES)
t
,
LOAD BIT MAPPED ONTO BIT 0
OF PERMUTATION BYTE INTO CARRY
I ,
. ROTATE LEFT INTO ACC.
STORE ACC. INTO PERMUTATION
I
BUFFER
,
I
I
Figure 10b. DES Key Permutation With Boolean Processor
203830-7
10-226
inter AP-70
The algorithm of Figure lOb is just slightly more effi- Example 1. DES Key Permutation Software.
cient in this time-critical application and illustrates the a.) "Brute Force" technique
synergy of an integrated byte and bit processor. The
bits needed for each byte of the Permutation Buffer are MOV C,SKB_l
assimilated by loading each bit into the carry (1 Jots.) MOV PB_l.l, C
and shifting it into the accumulator (1 Jots.). Each byte MOV C,SKB_2
is stored in RAM when completed. Forty-eight bits MOV PB_4.0,C
thus need a total of 112 instructions, some of which are MOV C,SKB_3
listed in Example lb. MOV PB_2.5,C
MOV C,SKB_4
Worst-case execution time would be 112 microseconds, MOV PB_l. 0, C
since each instruction takes a single cycle. Routine
length would also decrease, to 168 bytes. (Actually, in
the context of the complete encryption algorithm, each MOV C,SKB_55
permuted byte would be processed as soon as it is as- MOV PB_5.0,C
similated-saving memory and cutting execution time MOV C,SKB_56
by another 8 Jots.) MOV PB_7.2,C
To date, most banking terminals and other systems us- b.) Using Accumulator to Collect Bits
ing the DES have needed special boards or peripheral
controller chips just for the encryption/decryption pro- CLR A
cess, and still more hardware to form a serial bit stream MOV C,SKB_14
for transmission '(Figure l1a). An 8051 solution could RLC A
pack most of the entire system onto the one chip (Fig- MOV C,SKB_17
ure 11b). The whole DES algorithm would require less RLC A
than one-fourth of the on-chip program memory, with MOV C, SKB_ll
the remaining bytes free for operating the banking ter- RLC A
minal (or whatever) itself. MOV C,SKB_24
RLC A
Moreover, since transmission and reception of data is MOV C,SKB_l
performed through the on-board UART, the unen- RLC A
crypted data (plaintext) never even exists outside the MOV C,SKB_5
microcomputer! Naturally, this would afford a high de- RLC A
gree of security from data interception. MOV PB_l,A
MOV C,SKB_29
RLC A
MOV C,SKB_32
RLC A
MOV PB_8,A
10-227
inter AP-70
CONTROL AND ADDRESS BUSSES
l
I
DISPLAY
DATA
I
ENCRY· TO
PTION MODEM
CPU RAM ROM UART
UNIT
KEYBOARD
I
I
SYSTEM DATA BUS
J
203830-8
a.) Using Multi-Chip Processor Technology
~DISPL_AY----JK'--------ll~ I -
TAO
TO
KEYBOARD
•
-y
PO
8051
R.D .. MODEM
P1
I'll
203830-9
b.) Using One Single-Chip Microcomputer
Figure 11. Secure Banking Terminal Block Diagram
Design Example # 2-5oftware Figures 12a and 12b show algorithms for receiving or
transmitting a byte of data. (Another section of pro-
Serial 1/0 gram would invoke this algorithm eight times, synchro-
An exercise often imposed on beginning microcomput- nizing it with a start bit, clock signal, software delay, or
er students is to write a program simulating a UART. timer interrupt.) Data is received by testing an input
Though doing this with the 8051 Family may appear to pin, setting the carry to. the same state, shifting the
be a moot point (given that the hardware for a full carry into a data buffer, and saving the partial frame in
UART is on-chip), it is still instructive to see how it internal RAM. Data is transmitted by shifting an out-
would be done, and maintains a product line tradition. put. buffer through the carry, and generating each bit
on an output pin.
As it turns out, the 8051 microcomputers can receive or
transmit serial data via software very efficiently using A side-by-side comparison of the software for this com-
the Boolean instruction set. Since any I/O pin may be a mon "bit-banging" application with three different mi-
serial input or output, several serial links could be croprocessor architectures is shown in Table Sa and 5b.
maintained at once. The 8051 solution is more efficient than the others on
every count!
10-228
AP-70
PIN = 1
SET CARRY CLEAR CARRY
203830-10
a.) Reception
203830-11
b.) Transmission
Figure 12. Serial 110 Algorithms
10-229
intJ AP-70
Table 5. Serial 1/0 Programs for Various Microprocessors
a.) Input Routine.
8085 8048 8051
1:-1 SERI'ORT MOV C.SERPI"
A>,; I MASK CI.R C
.r!. 1.0 .I>,;TO 1.0
CMC CI'I. C
1.0: LXI HI..SERBlJF MOV RO.RSFR8l'~
MOV A.M MOV A.@RO MOV A.SERBl:~
RR RRC A RRC A
MOV M.A MOV @RIl.A MOV SERBl'r.A
RESUlTS:
K I"STRl:CTIO-';S 71>,;STRlTTIO:-lS 41>,;STRl'CTIO>,;S
14 BYTES 9 BYTES 7 BYTES
5b STATES 9 CYCI.F.S 4 CYCLES
19 uSEC 22.5 uSF.e. 4 uSEC
h.) Output Routine.
8085 8048 8051
LXI HI..SERBlI~ Mov RO .• SERBllF
MOV A.M MOV A.@RO MOV A.SE R Bl' F
RR RRC A RRC A
MOV M.A MOV @RO.A MOV SERBl'F.A
1-'; SERPORT
.Ie HI .Ie HI
1.0: A>,; I :-lOT MASK A>,; I. SERPRT.R"OT MASK MOV SfRPI".C
.IMP C:-IT .IMP C~T
HI: ORI MASK HI: ORI. SERPRT.RMASK
CII;T:OlIT SfRl'ORT CST:
RESlILTS:
10lNSTRlJCTI0II;S K Ii'iSTRlJCTIONS 4 INSTRlJCTlONS
20 BYTES 13 BYTES 7 BYTES
72 STATES II CYCLES 5 CYCI.ES
24 uSEC 27.5 uSEC 5 uSEC
203830-30
Design Example # 3-Combinatorial Figure 13 shows TTL and' relay logic diagrams for a
Logic Equations function of the six variables U through Z. Each is a
solution of the equation.
Next we'll look at some simple uses for bit-test instruc-
tions and logical operations. (This example is also pre- Q = (Ue(V + W» + (XeV) + Z
sented in Application Note AP-69.)
Equations of this sort might be reduced using Kar-
Virtually all hardware IJesigners have solved complex naugh Maps or algebraic techniques, but that is not the
functions using combinatorial logic. While the hard- purpose of this example. As the logic complexity in-
ware involved may vary from relay logic, vacuum creases, so does the difficulty of the reduction process.
tubes, or TTL or to more esoteric technologies like flu- Even a minor change to the function equations as the
idics, in each case the goal is the same: to solve a prob- design evolves wOjlld require tedious re-reduction from
lem represented by a logical function of several Boolean scratch.
variables.
10-230
infef AP-70
v
W ----L__'''
x
}----o
y
z
203830-12
Q = (U • (V + W)) + (x. Y) + Z
a.) Using TTL
v
x y
CRI
CR2
203830-13
. b.) Using Relay Logic
Figure 13. Hardware Implementations of Boolean Functions
For the sake of comparison we will implement this to an output pin on some third port. The first two im-
function three ways, restricting the software to three plementations follow the flow-chart shown in Figure
proper subsets of the MeS·51 instruction set. We will 14. Program flow would embark on a route down a
also assume that U and V are input pins from different test-and-branch tree and leaves either the "True" or
input ports, Wand X are status bits for two peripheral "Not True" exit ASAP-as soon as the proper result
controllers, and Y and Z are software flags set up earli· has been determined. These exits then rewrite the out-
er in the program. The end result must be written put port with the result bit respectively one or zero.
10-231
AP-70
The code which results is cumbersome and error prone.
It would be difficult to prove whether the software
worked for all input combinations in programs of this
sort. Furthermore, execution time will vary widely with
input data.
Thanks to the direct bit-test operations, a single in-
struction can replace each move mask conditional jump
sequence in Example 2a, but the algorithm would be
equally convoluted (see Example 2b). To lessen the
confusion "a bit" each input variable is assigned a sym-
. bolic name.
A more elegant and efficient implementation (Example
2c) strings together the Boolean ANL and ORL func-
tions to generate the output function with straight-line
code. When finished, the carry flag contains the result,
which is simply copied out to the destination pin. No
flow chart is needed-code can be written directly from
the logic diagrams in Figure 14. The result is simplicity
itself: fast, flexible, reliable, easy to design, and easy to
debug.
An 8051 program can simulate an N-input AND or
OR gate with at most N + 1 lines of source program-
one for each input and one line to store the results. To
simulate NAND and NOR gates, complement the car-
ry after computing the function. When some inputs to
the gate have "inversion bubbles", perform the ANL or
ORL operation on inverted operands. When the first
input is inverted, either load the operand into the carry .
and then complement it, or use DeMorgan's Theorem
FUNCTION FUNCTION to convert the gate to a different form.
IS FALSE IS TRUE
Example 2. Software Solutions to Logic Function of
CLEAR 0 Figure 13.
a.) Using only byte-wide logical instructions
'BFUNCI SOLVE, RANDOM LOGIC
FUNCTION OF 6 VARIABLES
BY LOADING AND MASKING
203830-14 THE APPROPRIATE BITS IN
THE ACCUMULATOR. THEN
Figure 14. Flow Chart for EXECUTING CONDITIONAL
Tree-Branching Algorithm JUMPS BASED ON ZERO
CONDITION. (APPROACH USED
Other digital computers must solve equations of this· BY BYTE-ORIENTED
type with standard word-wide logical iristructions and ARCHITECTURES.) BYTE AND
conditional jumps. So for the first implementation, we MASK VALUES CORRESPOND TO
won't use any generalized bit-addressing instructions. RESPECTIVE "BYTE ADDRESS
As we shall soon see, being constrained to such an in- AND BIT POSI;rIONS •.
struction subset produces somewhat sloppy software
solutions. MCS-51 mnemonics are used in Example 2a: OUTBUF DATA 22H
other machines might further cloud the situation by .;OUTPUT PIN STATE MAP
requiring operation-specific mnemonics like INPUT,
OUTPUT, LOAD, STORE, etc., instead of the MOV
mnemonic used for all variable transfers in the 8051
instruction set.
10-232
inter Ap·70
TESTV: MOV A,P2 U BIT PI.I
ANL A,#OOOOOIOOB V BIT P2.2
JNZ TESTU W BIT TFO
MOV A,TCON X BIT lEI
ANL A,#OOIOOOOOB Y BIT 20H.0
JZ TESTX Z BIT 2IH.I
TESTU: MOV A,PI Q. BIT P3.3
ANL A,#OOOOOOIOB
JNZ SETQ. TEST_V: JB V,TEST_U
TESTX: MOV A,TCON JNB W,TEST_X
ANL A,#OOOOIOOOB TEST_U: JB U,SET_Q.
JZ TESTZ TEST_X: JNB X,TEST_Z
MOV A,20H JNB Y,SET_Q.
ANL A,#OOOOOOOIB TEST_Z: JNB Z,SET_Q.
JZ SETQ. CLR_Q.: CLR Q.
TESTZ: MOV A,2lH JMP NXTTST
ANL A,#OOOOOOIOB SET_Q.: SETB Q.
JZ SETQ. NXTTST:(CONTINUATION OF
CLRQ.: MOV A,OUTBUF :PROGRAM)
ANL A,#IIIIOIIIB
JMP OUTQ. c.) Using logical operations on Boolean variables
SETQ.: MOV A,OUTBUF :FUNC3 SOLVE A RANDOM LOGIC
ORL A,#OOOOIOOOB FUNCTION OF 6 VARIABLES
OUTQ.: MOV OUTBUF,A USING STRAIGHT __ LINE
MOV P3,A LOGICAL INSTRUCTIONS ON
MCS-51 BOOLEAN VARIABLES.
b.) Using only bit-test instructions
:BFUNC2 SOLVE A RANDOM LOGIC MOV C,V
FUNCTION OF 6 VARIABLES ORL C,W ;OUTPUT OF OR GATE
BY DIRECTLY POLLING EACH ANL C,U ;OUTPUT OF TOP AND GATE
BIT. (APPROACH USING MOV FO,C ;SAVE INTERMEDIATE STATE
MCS-51 UNIQ.UE BIT-TEST MOV C,X
INSTRUCTION CAPABILITY.) ANL C,Y ;OUTPUT OF BOTTOM AND GATE
SYMBOLS USED IN LOGIC ORL C,FO :INCLUDE VALUE SAVED ABOVE
DIAGRAM ASSIGNED TO ORL C,Z :INCLUDE LAST INPUT
CORRESPONDING 'Sx51 BIT :VARIABLE
ADDRESSES. MOV Q.,C :OUTPUT COMPUTED RESULT
10-233
intJ AP-70
An upper-limit can be placed on the complexity of soft- Imagine the three position tum lever on the steering
ware to simulate a large number of gates by summing column as a single-pole, triple-throw toggle switch. In
the total number of inputs and outputs. The actual total its central position all contacts are open. In the up or
should be somewhat shorter, since calculations can be down positions contacts close Causing corresponding
"chained," as shown. The output of one gate is often lights in the rear of the car to blink. So far very simple.
the first input to another; bypassing the intermediate
variable to eliminate two lines of source. Two more tum signals blink in the front ofthe car, and
two others in the dashboard. All six bulbs flash when
an emergency switch is closed; A thermo-mechanical
Design Example # ~Automotlve relay (accessible under the dashboard in case it wears
Dashboard Functions out) causes the blinking.
Now let's apply these techniques to designing the soft. Applying the brake pedal turns the tail light filaments
ware for a complete controller system. This application on constantly ... unless a tum is in progress, in which
is patterned after a familiar real-world application case the blinking tail light is not affected. (Of course,
which isn't nearly as trivial as it might first appear: the front tum signals and dashboard indicators are not
automobile tum signals. affected by the brake pedal.) Table 6 summarizes these
operating modes.
Table 6. Truth Table for Turn-Signal Operation
Input Signals Output Signals
Left Right. Left . Right
Brake Emerg. Left Right
Turn Turn Front Front
Switch Sw,ltch Rear Rear
Switch Switch & Dash & Dash
0 0 0 0 Off Off Off Off
0 0 0 1 Off Blink Off Blink
0 0 1 0 Blink Off Blink Off·
0 1 0 0 Blink Blink Blink Blink
0 1 0 1 Blink Blink Blink Blink
0 1 1 0 Blink Blink Blink Blink
1 0 0 0 Off Off On On
1 0 0 1 Off Blink On Blink
1 0 1 0 Blink Off Blink On
1 1 0 0 Blink Blink On On
1 1 0 1 Blink Blink On Blink
1 1 1 0 Blink Blink Blink On
10-234
inter AP-70
But we're not done yet. Each of the exterior turn signal each termination for each filament lead to extra cost
(but not the dashboard) bulbs has a second, somewhat and labor during construction, lower reliability and
dimmer filament for the parking lights. Figure 15 safety, and more costly repairs. And considering the
shows TTL circuitry which could control all six bulbs. system's present complexity, increasing its reliability or
The signals labeled "High Freq." and "Low Freq." rep- detecting failures would be quite difficult.
resent two square-wave inputs. Basically, when one of
the turn switches is closed or the emergency switch is There are two reasons for going into such painful detail
activated the low frequency signal (about 1 Hz) is gated describing this example. First, to show that the messiest
through to the appropriate dashboard indicator(s) and part of many system designs is determining what the
turn signal(s). The rear signals are also activated when controller should do. Writing the software to solve
the brake pedal is depressed provided a turn is not be- these functions will be comparatively easy. Secondly, to
ing made in the same direction. When the parking light show the many potential failure points. in the system.
switch is closed the higher frequency oscillator is gated Later we'll see how the peripheral functions and intelli-
to each front and rear turn signal, sustaining a low-in- gence built into a microcomputer (with a little creativi-
tensity background level. (This is to eliminate the need ty) can greatly reduce external interconnections and
for additional parking light filaments.) mechanical part count.
In most cars, the switching logic to generate these func-
tions requires a number of multiple-throw contacts. As The Single-Chip Solution
many as 18 conductors thread the steering column of
some automobiles solely for turn-signal and emergency The circuit shown in Figure 16 indicates five input pins
blinker functions. (The author discovered this recently to the five input variables-left-turn select, right-turn
to his astonishment and dismay when replacing the select, brake pedal down, emergency switch on, and
whole assembly because of one burned contact.) parking lights on. Six output pins turn on the front,
rear, and dashboard indicators for each side. The mi-
A multiple-conductor wiring harness runs to each cor- crocomputer implements all logical functions through
ner of the car, behind the dash, up the steering column, software, which periodically updates the output signals
and'down to the blinker relay below. Connectors at as time elapses and input conditions change.
L. TURN
EMERG r---....- - - - - - L. DASH
L. FRNT
BRAKE L. REAR
R. TURN
r---....+----- R. DASH
R. FRNT
R.REAR
PARK
LO. HI.
FREO. FREO.
OSCILLATOR OSCILLATOR
203830-15
Figure 15. TTL Logic Implementation of Automotive Turn Signals
10-235
intJ AP-70
+12V
+12V
8051
LEn
FRONT
:"
Pl.S
Pl.0
RIGHT
FRONT
EMERGENCY Pl.l P1.I
SWITCH
PARKING LEn
Pl.2 DASHBOARD
LIGHTS Pl.7
Pl.3 RIGHT
TURN DASHBO.ARD
SWITCH P2.0
P1.4
LEn
REAR
P2,1
RIGHT
REAR
PU
MODE SIGNAL CONTROLLER OUTPUT SIGNAL
SENSORS CONDITIONING BUFFERS BULBS
203830-16
Figure 16. Microcomputer Turn-Signal Connections.
Design Example # 3 demonstrated that symbolic ad-
dressing with user-defined bit names makes code and R_DASH BIT P2.0 ;DASHBOARD RIGHT-
documentation easier to write and maintain. Accord- ;TURN INDICATOR
ingly, we'll assign these I/O pins names for use I_REAR BIT P2.1 ;REAR LEFT-TURN
throughout the program. (The format of this example ;INDICATOR
will differ somewhat from the others. Segments of the R_REAR BIT P2.2 ;REAR RIGHT-TURN
overall program will be presented in sequence as each is ;INDICATOR
described.)
Another key advantage of symbolic addressing will ap-
INPUT PIN DECLARATIONS: pear further on in the design cycle. The locations of
;(ALL INPUTS ARE POSITIVE-TRUE LOGIC) cable connectors, signal conditioning. circuitry, voltage
regulators, heat sinks, and the like all affect P.C. board
BRAKE BIT .Pl.O .;BRAKE PEDAL layout. It's quite likely that the somewhat arbitrary pin
;DEPRESSED assignment defined early in- the software design cycle
EMERG BIT Pl.l ;EMERGENCY BLINKER will prove to be less than optimum; rearranging the I/O
;ACTIVATED pin assignment could well allow a more compact mod-
PARK BIT Pl.2 ;PARKING LIGHTS ON ule, or eliminate Costly jumpers on a single-sided board.
I_TURN BIT Pl.3 ;TURN LEVER DOWN (These considerations apply especially to automotive
R_TURN BIT Pl.4 ;TURN LEVER UP and other cost-sensitive applications needing single-
chip controllers.) Since other architectures mask bytes
OUTPUT PIN DECLARATIONS: or use "clever" algorithms to isolate bits by rotating
them into the carry, re-routing an input signal (from bit
I_FRNT BIT Pl.5 ;FRONT LEFT-TURN I of port 1, for example, to bit 4 of port 3) could require
;INDICATOR extensive modifications throughout the software.
R_FRNT BIT Pl.6 ;FRONT RIGHT-TURN
;INDICATOR The Boolean Processor's direct bit addressing makes
I_DASH .BIT Pl.7 ;DASHBOARD LEFT-TURN such changes absolutely trivial. The number of the port
;INDICATOR containing the pin is irrelevent, and masks and complex
10-236
AP-70
program structures are not needed. Only the initial "tuned" to approximately I Hz for the tum- and emer-
Boolean variable declarations need to be changed; gency-indicator blinking rate.
ASM5l automatically adjusts all addresses and symbol-
ic references to the reassigned variables. The user is Loading THO with -16 will cause an interrupt after
assured that no additional debugging or software verifi- 4.096 ms. The interrupt service routine reloads the
cation will be required. high-order byte of timer 0 for the next interval, saves
the CPU registers likely to be affected on the stack, and
then decrements SUB_DIY. Loading SUB_DIY.
with 244 initially and each time it decrements to zero
;INTERRUPT RATE SUBDIVIDER will produce a 0.999 second period for the highest-or-
SUB_DIV DATA 20H der bit.
;HIGH-FREQUENCY OSCILLATOR BIT
HI_FREQ BIT SUB_DIV,O
:LOW-FREQUENCY OSCILLATOR BIT ORG OOOBH ;TIMER 0 SERVICE VECTOR
LO_FREQ BIT SUB_DIV,7 MOV THO,#-16
PUSH PSW
ORG OOOOH PUSH ACC
JMP INIT PUSH B
DJNZ SUB_DIV,TOSERV
ORG IOOH MOV SUB_DIV,#244
;PUT TIMER 0 IN MODE I
INIT; MOV TMOD,#OOOOOOOIB The code to sample inputs, perform calculations, and
:INITIALIZE TIMER REGISTERS update outputs-the real "meat" of the signal control-
MOV TLO,#O ler algorithm-may be performed either as part of the
MOV THO,#-16 interrupt service routine or as part of a background
;SUBDIVIDE INTERRUPT RATE BY 244 program loop. The only concern is that it must b'e exe-
MOV SUB_DIV,#244 cuted at least serveral dozen times per second to pre-
:ENABLE TIMER INTERRUPTS vent parking light flickering. We will assume the for~
SETB ETO mer case, and insert the code into the timer 0 service
:GLOBALLY ENABLE ALL INTERRUPTS routine.
SETB EA
;START TIMER First, notice from the logic diagram (Figure 15) that
SETB TRO the subterm (PARK. H_FREQ), asserted when the
parking lights are to be on dimly, figures into four of
;(CONTINUE WITH BACKGROUND PROGRAM) the six output functions. Accordingly, we will first
compute that term and save it in a temporary location
;PUT TIMER 0 IN MODE I named· "DIM". The PSW contains two general purpose
;INITIALIZE TIMER REGISTERS flags: FO, which corresponds to the 8048 flag of the
same name, and PSW.1. Since the PSW has been saved
;SUBDIVIDE INTERRUPT RATE BY 244 and will be restored to its previous state after servicing
;ENABLE TIMER INTERRUPTS the interrupt, we can use either bit for temporary stor-
;GLOBALLY ENABLE ALL INTERRUPTS age.
;START TIMER
DIM BIT PSW.I ;DECLARE TEMP
Timer 0 (one of the two on-chip timer counters) re- :STORAGE FLAG
places the thermo-mechaniCal blinker relay in the dash-
board controller. During system initialization it is con- MOV C,PARK :GATE PARKING
figured as a timer in mode I by setting the least signifi- ;LIGHT SWITCH
cant bit of the timer mode register (TMOD). In this ANL HLFREQ ;WITH HIGH
configuration the low-order byte (fLO) is incremented ;FREQUENCY
every machine cycle, overflowing and incrementing the ;SIGNAL
high-order byte (THO) every 256 /Ls. Timer interrupt 0 MOV DIM,C ;AND SAVE IN
is enabled so that a hardware interrupt will occur each :TEMP. VARIABLE
time THO overflows.
An eight-bit variable in the bit-addressable RAM array This simple three-line section of code illustrates are"
will be needed to further subdivide the interrupts via markable point. The software indicates in very abstract
software. The lowest-order bit of this counter toggles terms exactly what function is being performed, inde-
very fast to modulate the parking lights: bit 7 will be
10-237
Ap·70
pendent of the hardware· configuration. The fact that
these three bits include an input pin, a bit within a ORL C,DIM ;AND PARKING
program variable, and a software flag in the PSW is ;LIGHT FUNC.TION
totally invisible to the programmer. MOV L_REAR, C ;AND OUTPUT TO
;TURN SIGNAL
Now generate and output the dashboard left turn sig-
nal.
Now we have to go through a similar sequence for the
right-hand equivalents to all the left-turn lights. This
also gives us a chance to see how the code segments
MOV C,L_TURN ;SET CARRY IF above look when combined.
;TURN
ORL C,EMERG ;OR EMERGENCY
; SELECTED MOV C.R_TURN ;SET CARRY H-
. ANL C, LO_FREQ ;GATE IN 1 HZ ; TURN
;SIGNAL ORL C.EMERG ;OR EMERGENCY
MOV LDASH,C ;AND OUTPUT TO ;SELECTED
;DASHBOARD ANL C,LO_FREQ ;IF SO. GATE IN 1
;HZ SIGNAL
MOV R_DASH.C ;AND OUTPUT TO
To generate the left front turn signal we only need to ;DASHBOARD
add the parking light function in FO. But notice that the MOV.FO.C ;SAVE FUNCTION
function· in the carry will also be needed for the rear ;SO FAR
signal. We can save effort later by saving its current ORL C.DIM ;ADD IN PARKING
state in FO. .;LIGHT FUNCTION
MOV R_FRNT.C ;AND OUTPUT TO
;TURN SIGNAL
MOV C.BRAKE ;GATE BRAKE
MOV FO.C ;SAVE FUNCTION ;PEDAL SWITCH
;SO FAR ANL C. R_ TURN ;WITH TURN
ORL C,DIM ;ADD IN PARKING ;LEVER
;LIGHT FUNCTION ORL C.FO ;INCLUDE TEMP.
MOV L_FRNT.C ;AND OUTPUT TO ;VARIABLE FROM
;TURN SIGNAL ;DASH
ORL C.DIM ;AND PARKING
Finally, the rear left turn signal should also be on when ;LIGHT FUNCTION
.the brake pedal is depressed, provided a left turn is not MOV R_REAR.C ;AND OUTPUT TO
in progress. ;TURN SIGNAL
(The perceptive reader may notice that simply rear-
MOV C,BRAKE ;GATE BRAKE ranging the steps could eliminate one instruction from
;PEDAL SWITCH each sequence.)
ANL C,L_TURN ;WITH TURN
;LEVER Now that all six bulbs are in the proper states, we can
ORL C,FO ;INCLUDE TEMP. return from the interrupt routine, and the program is
;VARIABLE FROM.DASH finished. This code essentially· needs to reverse the
status saving steps at the beginning of the interrupt.
Table 7 Non-Trivial Duty Cycles
Sub_Dlv Bits Duty Cycles
7 6 5 4 3 2 1 0 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5%
X X X X X 0 0 0 Off Off Off Off Off Off Off
X X X X X 0 0 1 Off Off Off Off Off Off On
X X X X X 0 1 0 Off Off Off Off Off On On
X X X X X 0 1 1 Off Off Off Off On On On
X X X X X 1 0 0 Off Off Off On On On On
X X X X X 1 0 1 Off Off On On On On On
X X X X X 1 1 0 Off On On On On On On
X X X X X 1 1 1 On On On On On On On
10-238
AP-70
driver circuits combining shift-register inputs with high
POP B ;RESTORE CPU drive level outputs have been introduced recently.
;REGI STERS.
POP ACC Cascading multiple shift registers end-to-end will ex-
POP PSW pand the number of outputs even further. The data rate
RETI in the I/O expansion mode is one megabaud, or 8 /.I.s.
per byte. This is the mode which the serial port defaults
to following a reset, so no initialization is required.
Program Refinements. The luminescence of an incan-
descent light bulb filament is generally non-linear: the The software for this technique uses the B register as a
50% duty cycle of HI_FREQ may not produce the "map" corresponding to the different output functions.
desired intensity. If the application requires, duty cy- The program manipulates these bits instead of the out-
cles of 25%, 75%, etc. are easily achieved by ANDing put pins. After all functions have been calculated the B
and ORing in additional low-order bits of SUB_DIY. register is shifted by the serial port to the shift-register
For example, 30 H/ signals of seven different duty cy- driver. (While some outputs may glitch as data is shift-
cles could be produced by considering bits 2-0 as ed through them, at 1 Megabaud most people wouldn't
shown in Table 7. The only software change required notice. Some shift registers provide an "enable" bit to
would be to the code which sets-up variable DIM; hold the output states while new data is being shifted
in.)
MOV C,SUB_DIV.l;START WITH 50 This is where the earlier decision to address bits sym-
;PERCENT bolically throughout the program is going to payoff.
ANL C,SUB_DIV.O;MASK DOWN TO 25 This major I/O restructuring is nearly as simple to im-
;PERCENT plement as rearranging the input pins. Again, only the
ORL C,SUB_DIV.2;AND BUILD BACK TO bit declarations need to be changed.
;62 PERCENT
MOV DIM,C ;DUTY CYCLE FOR
;PARKING LIGHTS. LFRNT BIT B.O ;FRONT LEFT-TURN
;INDICATOR
R_FRNT BIT B.l ;FRONT RIGHT-TURN
Interconnections increase cost and decrease reliability. ;INDICATOR
The simple buffered pin-per-function circuit in Figure LDASH BIT B.2 ;DASHBOARD LEFT-TURN
16 is insufficient when many outputs require higher- ;INDICATOR
than-TTL drive levels. A lower-cost solution uses the R_DASH BIT B.3 ;DASHBOARD RIGHT-TURN
8051 serial port in the shift-register mode to augment ;INDICATOR
I/O. In mode 0, writing a byte to the serial port data LREAR BIT B.4 ;REAR LEFT-TURN
buffer (SBUF) causes the data to be output sequentially ;INDICATOR
through the "RXD" pin while a burst of eight clock R_REAR BIT B.5 ;REAR RIGHT-TURN
pulses is generated on the "TXD" pin. A shift register ;INDICATOR
connected to these pins (Figure 17) will load the data
byte as it is shifted out. A number of special peripheral
+ 12V
8051
P3.0 r--------"'i ~ATA 07 05
P3.1 1 - - - -......, eLK 8·BIT SHIFT REGISTER
203830-17
Figure 17. Output Expansion Using Serial Port
10-239
AP-70
The original program to compute the functions need standard double filament bulb, but with the filaments
not change. After computing the output variables, the driven in parallel to tolerate single-element failures.
control map is transmitted to the buffered shift register
through the serial port. Even with redundancy, the lights will eventually fail.
To handle this inescapable fact current or voltage sens-
MOV SBUF,B ;LOAD BUFFER AND TRANSMIT ing circuits on each main drive wire can verify that
each bulb and its high-current driver is functioning
The Boolean Processor solution holds a number of ad- properly. Figure 18 shows one such circuit.
vantages over older methods. Fewer switches are re-
quired. Each is simpler, requiring fewer poles and lower Assume all of the lights are turned on except one: i.e.,
current contacts. The flasher relay is eliminated entire- all but one of the collectors are grounded. For the bulb
ly. Only six filaments are driven, rather than 10. The which is turned off, if there is continuity from + l2V
wiring harness is therefore simpler and less expensive-- through the bulb base and filament, the control wire, all
one conductor for each of the six lamps and each of the connectors, and the P.C. board traces, and if the tran-
five sensor switches. The fewer conductors use far few- sistor is indeed not shorted to ground, then the collec-
er connectors. The whole system is more reliable. tor will be pulled to + l2V. This turns on the base of
Q8 through the corresponding resistor, and grounds the
And since the system is much simpler it would be feasi- input pin, verifying that the bulb circuit is operational.
ble to implement redundancy and or fault detection on The continuity of each circuit can be checked by soft-
the four main turn indicators. Each could still be a ware in this ~ay.
WIRING +12V
HARNESS
1
I
®
.. ·1 (Q 1 A 17\\
Pl.6
Pl.7
P2.0
-
P2.l
P2.2
=
+5V
TO
203830-18
Figure 18
10-240
AP-70
Now turn all the bulbs on, grounding all the collectors. The complete assembled program listing is printed in
Q7 should be turned off, and the Test pin should be Appendix A. The resulting code consists of 67 program
high. However, a control wire shorted to + 12V or an statements, not counting declarations and comments,
open-circuited drive transistor would leave one of the which assemble into 150 bytes of object code. Each pass
collectors at the higher voltage even now. This too through the service routine requires (coincidently)
would turn on Q7, indicating a different type offailure. 67 /Ls plus 32 /Ls once per second for the electrical test.
Software could perform these checks once per second If executed every 4 ms as suggested this software would
by executing the routine every time the software count- typically reduce the throughput of the background pro-
er SUB_DIY is reloaded by the interrupt routine. gram by less than 2%.
Once a microcomputer has been designed into a system,
DJNZ SUB_DIV,TOSERV new features suddenly become virtually free. Software
MOV SUB_DIV,#244 ;RELOAD COUNTER could make the emergency blinkers flash alternately or
ORL Pl,#lllOOOOOB ;SET CONTROL at a rate faster than the turn signals. Turn signals could
;OUTPUTS HIGH override the emergency blinkers. Adding more bulbs
ORL P2,#00000111B would allow multiple taillight sequencing and syncopa-
CLR LFRNT ;FLOAT DRIVE tion-true flash factor, so to speak.
;COLLECTOR
JB TO ,FAULT ;TO SHOULD BE
;PULLED LOW Design Example # 5-Complex Control
;PULL COLLECTOR Functions
;BACK DOWN
CLR L_DASH Finally, we'll mix byte and bit operations to extend the
JB TO ,FAULT use of 8051 into extremely complex applications.
SETB L_DASH
CLR L_REAR Programmers can arbitrarily assign I/O pins to input
JB TO ,FAULT and output functions only if the· total does not exceed
SETB L_REAR 32, which is insufficient for applications with a very
CLR R_FRNT large number of input variables. One way to expand the
JB. TO ,FAULT number of inputs is with a technique similar to multi-
SETB R_FRNT . plexed-keyboard scanning.
CLR R_DASH
JB TO ,FAULT Figure 19 shows a block diagram for a moderately com-
SETB R_DASH plex programmable industrial controller with the fol~
CLR R_REAR lowing characteristics:
JB TO ,FAULT •. 64 input variable sensors:
SETB R_REAR
• 12 output signals:
;WITH ALL COLLECTORS GROUNDED. TO • Combinational and sequential logic computations:
SHOULD BE HIGH • Remote operation with communications to a host
;IF SO. CONTINUE WITH INTERRUPT processor via a high-speed full-duplex serial link:
ROUTINE.
JB TO , TOSERV • Two prioritized external interrupts:
FAULT: ;ELECTRICAL • Internal real-time and time-of-day clocks.
;FAILURE
;PROCESSING While many microprocessors could be programmed to
;ROUTINE . provide these capabilities with assorted peripheral sup-
;(LEFT TO port chips, an 8051 microcomputer needs no other inte-
;READER'S grated circuits!
;IMAGINATION)
TOSERV: ;CONTINUE WITH The 64 input sensors are logically arranged as an 8x8
; INTERRUPT matrix. The pins of Port 1 sequentially enable each col-
. ;PROCESSING umn of the sensor matrix: as each is enabled Port 0
reads in the state of each sensor in that column. An
eight-byte block in bit-addressable RAM remembers
the data as it is read in so that after each complete scan
cycle there is an internal map of the current state of all
sensors. Logic functions can then directly address the
elements of the bit map.
10-241
AP-70
+ 5V
r-
XTAL1
It VCC RST
1.0uF
12M~Z
~
~ XTAL2
-
SERIAL \
LINK , RXD
TXD
INTO
-
INT1
ASYNCHRONANS
INTERRUPTS
RETURN 8051
LINES
\ P3.4
0 8 16 24 32 40 48 56 PO.O
P3.5
1 57 PO.1
P3.6
2 58 PO.2
'3- - I-rsg PH
--
4
8.8
SENSOR
MATRIX
60
PO.3
PO.4
"5- 61 PO.5
P2.0
P2.1 MACHINE
6 62 PO.6
P2.2 ACTUATORS
7 15 23 31 39 47. 55 63 PO,]
P2.3
I t P2.4
~
P1.0 P2.5
P1.1 P2.6
P1.2 P2.7
P1.3
P1.4
_ _ N.C.
P1.5 ALE
P1.6 PSEN _ N . C .
P1.7
)..J VSS EA
SCAN
LINES
r 203830-19
Figure 19. Block Diagram of 54-Input Machine Controller
The computer's serial port is configured as a nine-bit There are several ways to implement the sensor matrix
UART, transferring data at 17,000 bytes-per-second. circuitry, all logically similar. Figure 20a shows one
The ninth bit may distinguish between address and data possibility. Each of the 64 sensors consists of a pair of
bytes. simple switch contacts in series with a diode to permit
multiple contact closures throughout the matrix.
The 8051 serial port can be configured to detect bytes
with the address bit set, automatically ignoring all oth- The scan lines from Port 1 provide eight un-encoded
ers. Pins INTO and INTI are interrupts configured.re- active-high scan signals for enabling columns of the
spectively as high-priority, falling-edge triggered and matrix. The return lines on rows where a contact is
low-priority, low-level triggered. The remaining 12 I/O closed are pulled high and read as logic ones. Open
pins output TTL-level control signals to 12 actuators. return lines are pulled to ground by one of the 40 kn
resistors and are read as zeroes. (The resistor values
must be chosen to ensure all return lines are pulled
above the 2.0V logic threshold, even in the worst-case,
10-242
intJ AP-70
where all contacts in an enabled column are closed.)
Since PO is provided open-collector outputs and high- Example 3.
impedance MOS inputs its input loading may be con- INPUT_SCAN: ;SUBROUTINE TO READ
sidered negligible. ;CURRENT STATE
;OF 64 SENSORS AND
The circuits in Figures 20b-20d are variations on this ;SAVE IN RAM 20H-27H
theme. When input signals must be electrically isolated MOV RO,#20H ;INITIALIZE
from the computer circuitry as in noisy industrial envi- ;POINTERS
ronments, phototransistors can replace the switch diode MOV RI,#28H ;FOR BIT MAP
pairs and provide optical isolation as in Figure 20b. ;BASES
Additional opto-isolators could also be used on the con- MOV A,#80H ;SET FIRST BIT
trol output and special signal lines. ;IN ACC
SCAN; MOV PI,A ;OUTPUT TO SCAN
The other circuits assume that input signals are already ;LINES
at TTL levels. Figure 20c uses octal three-state butTers RR A ;SHIFT TO ENABLE
enabled by active-low scan signals to gate eight signals ;NEXT COLUMN
onto Port o. Port 0 is available for memory expansion ;NEXT
or peripheral chip interfacing between sensor matrix MOV R2,A ;REMEMBER CUR-
scans. Eight-to-one multiplexers in Figure 20d select ;RENT SCAN
one of eight inputs for each return line as determined ;POSITION
by encoded address bits output on three pins of Port 1. MOV A,PO ;READ RETURN
(Five more output pins are thus freed for more control ;LINES
functions.) Each output can drive at least one standard XCH A,@RO ;SWITCH WITH
TTL or up to 10 low-power TTL loads without addi- ;PREVIOUS MAP
tional butTering. ;BITS
MOV @RI,A ;SAVE PREVIOUS
Going back to the original matrix circuit, Figure 21 ;STATE AS WELL
shows the method used to scan the sensor matrix. Two INC RO ;BUMP POINTERS
complete bit maps are maintained in the bit-addressable INC RI
region of the RAM: one for the current state and one MOV A,R2 ;RELOAD SCAN
for the previous state read for each sensor. If the need ;LINE MASK
arises, the program could then sense input transitions JNB ACC,7;SCAN;LOOP UNTIL ALL
and or debounce contact closures by comparing each ;EIGHT COLUMNS
bit with its earlier value. ;READ
RET
The code in Example 3 implements the scanning algo-
rithm for the circuits in Figure 20a. Each column is
enabled by setting a single bit in a field of zeroes. The
bit maps are positive logic: ones represent contacts that
are closed or isolators turned on.
10-243
inter AP-70
...
+5V
.
~
~
~~ ! +8x4K
8051
"0" "8" "56" RETURN
~~~ ~~~
......
....J- LINES
f0- r- t---+---+---++-----_~ PO.O
"1"
~....L-
I- -+---.....--++----....4-.-1 PO.l
--+----:r. I~ - I-~f----:---t-+----.-t-t-I~ PO.2
: I t-'-t: : :~::
---+----"- -+.-1-+ I I ::::
~_L~_ II III ~~~
~-~. - -S!z I-
PO.7
~----''----+-+---------4 Pl.0
'----:-------++--------1 Pl.l
'---------,--++----------4 Pl.2
'-----------++-----'----l Pl.3
'------------++--------l Pl.4
' - - - - - - - - - - - - - + + - - - - - - - 1 Pl.5
'--------------------4I-+---------l Pl.6
' - - - - - - - - - - - - - - - - - - - - - - + - l > . . - - - - - - - - 1 Pl.7
SCAN II
LINES
203830-20
a.) Using Switch Contact/Diode Matrix
Figure 20. Sensor Matrix Implementation Methods
10·244
AP-70
+SV
+8x4K
h
-
(~,*) "0"
~
()I¥~"
l
..-
"
~
O¥Y)"S6"
RETURN
,LINES
ll- L-
f- - I ~
po.o
......., .-
~
(~,¥)
P"-
"1"
Ct;z)l +-
~
C~'¥)"S7"
1 ~
PO.l
1 -- PO.2
I
-- I I
PO.3
I I I~I I
PO.4
po.s
1+1+' PO.6
~
Q:::l)_"7"
b.-.rl
(~'~"lS"
I .........
( ~K~"63"
l - T" r - -r ~ PO.7
8x40K t;
-
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.6
Pl.7
.:' '
seA: ....
LINES
203830-21
b.) Using Optically-Coupled Isolators
Figure 20. Sensor Matrix Implementation Methods (Continued)
10·245
AP-70
nlnn!
8051
11111111 Iitttttr .. -NM""-NM""
C N M ... C N M ...
~ :!:!c:!~~~~ C C
........ C
_ N C C C
r-" lG. 2G 74lS244 ,- lG. 2G 74lS244
N N N
...>-
;:~~:;: >-
N M ... > N
>-
M
>-
_ ....... N ~ ~ ~ N N N N
I I 1 1
'--i-+_+_+-+_+_+_+_......-+-+-+-+-+-t-i--+_--<t----+_+-+_+_+_-+--+--___ po.o
'--+_+_+-+_+_+_+_-~-+-+-+-+-t-i--+_--__+-+_~+--+--+--___IPOl
'--i-+_+-+-+_+---.....-+-+-+-+-+--+----~t-t-+-+-+----i PO.2
'--t-t-t-+-t----......-t--+-+-t--+-----..-t-+-~+----i P03
~+-+-+_+-----......-+-+-+--+_------<--+_+-+_--l PO.4
' - - t - + - t - - - - - -.....-+--+--+-------~t-+---i po.s
' - - + - i - - - - - - -......- + - - i - - - - - - - - ' -....+---i PO.6
' - - t - - - - - , . . - - - -.....- - - i - - - - - - - - - . . - - - i PO.7
I I I I I
~ ' - - - - - - - - - - - - - - - \ Pl.0
' - - - - - - - - - - - - - - - i Pl.1
'-----------------1 Pl.2
G
:~::
' - - - - - - - - - - - - - - - - - - - - - ; Pl.S
~-----~--------~----~
'-----------------------'-----------'""""i PH
203830-22
c.) Using TTL Three-State Buffers
Figure 20. Sensor Matrix Implementation Methods (Continued)
10-246
AP-70
r---
, , , , , ,
rrrnrrr ntrnn
DO 01 02 03 04 05 06 07
74151
DO 01 02 03 04 05 06 07
74151
nrrnn
DO 01 02 03 04 05 0& D7
74151
C B A Y S C' B A Y S C B A Y s
1+ ~ ~
PO.O
PO.1
L ..1-.1 PO.2
I PO.3
PO.4
PO.5
PO.&
PO.7
11 11 11 11 11
~
P1.0
1 1 1 1 P1.1
~ P1.2
'--
203830-23
d.) Using TTL Data Selectors
Figure 20. Sensor Matrix Implementation Methods (Continued)
10-247
inter Ap..70
venting some artificial design problem, software corre-
sponding to commonplace logic elements will be dis-
cussed.
Combinatorial Output Variables. An output variable
which is a simple (or not so simple) combinational
function of several input variables is computed in the
spirit of Design Example 3. All 64 inputs are represent-
INITIALIZE MAP ed in the bit maps: in fact, the sensor numbers in Figure
BliFFER POINTERS 20 correspond to the absolute bit addresses in RAMI
AND SCAN MASK
The code in Example,4 activates an actuator ,connected
to P2.2 when sensors 12, 23, and 34 are closed and
sensors 45 and 56 are open.
OUTPUT SCAN
MASK TO SCAN Example 4.
LINES; ,
STORE SHIFTED Simple Combinatorial Output Variables.
MASK
;SET P2.2=(12) (23) (34) ( 45) ( 56)
MOV C,12
ANL C,23
ANL C,34
READ RETURN
LINES AND UPDATE
ANL C, 45
BIT MAPS ANL C, 56
MOV P2.2,C
Intermediate Variables. The examination of a typical
relay-logic ladder diagram will show that many of the
rungs control not outputs but rather relays whose con-
tacts figure into the computation of other functions. In
effect, these relays indicate the state of intermediate
variables of a computation.
The MCS-51 solution can use any directly addressable
bit for the storage of such intermediate variables. Even
when all 128 bits of the RA:Marray are dedicated (to
input bit maps in this example), the ,accumulator, PSW,
and B register provide 18 additional flags for intermedi-
ate variables.
For example, suppose switches 0 through 3 control a
safety interlock system. Closing any of them should de-
203830-24
activate certain outputs. Figure 22 is a ladder diagram
for this situation. The interlock function could be re-
Figure 21. Flowchart for computed for every output affected, or it may be com-
Reading In Sensor Matrix puted once and save (as implied by the diagram). As
the program proceeds this bit can qualify each output.
What happens after the sensors have been scanned de-
pends on the individual application. Rather than in-
10-248
inter AP-70
Example 5. Incorporating Override signal into actu- Latching Relays. A latching relay can be forced into
ator outputs. either the ON or OFF state by two corresponding input
signals, where it will remain until forced onto the oppo-
CALL INPUT_SCAN site state-analogous to a TTL Set/Reset flip-flop. The
MOV C,O relay is used as an intermediate variable for other calcu-
ORL C,l lations. In the previous example, the emergency condi-
ORL C,2 tion could be remembered and remain active until an
ORL C,3 "emergency cleared" button is pressed.
MOV FO,C
Any flag or addressable bit may represent a latching
COMPUTE FUNCTION 0 relay with a few lines of code (see Example 6).
ANL C, FO
MOV PLO,C Example 6. Simulating a latching relay.
COMPUTE FUNCTION 1 ;I_SET SET FLAG 0 IF C=l
LSET: ORL C,FO
ANL C, FO MOV FO,C
MOV Pl,l,C
COMPUTE FUNCTION 2 ;I_RSET RESET FLAG 0 IF C=l
LRSET: CPS C
ANL C, FO ANL C,FO
MOV Pl,2,C MOV FO,C
Time Delay Relays. A time delay relay does not re-
"0" spond to an input signal until it has been present (or
I absent) for some predefined time. For example, a bal-
last or load resistor may be switched in series with a
"1"
D.C. motor when it is first turned on, and shunted from
the circuit after one second. This sort of time delay may
"2"
be simulated by an interrupt routine driven by one of
the two 8051 timer counters. The procedure followed
by the routine depends heavily on the details of the
"3" exact function needed: time-outs or time delays with
resettable or non-resettable inputs are possible. If the
interrupt routine is executed every 10 milliseconds the
code in Example 7 will clear an intermediate variable
set by the background program after it has been active
for two seconds.
Example 7. Code to clear USRFLG after a fixed
time delay.
JNB USR_FLG,NXTTST
DJNZ DLAY_COUNT,NXTTST
CLR USR_FLG
MOV DLAY_COUNT,#200
NXTTST; , ..
203830-25
Figure 22. Ladder Diagram for
Output Override Circuitry
10-249
inter AP-70
Serial Interface to Remote Processor. When it detects A programmed controller which simulates each Boole-
emergency conditions represented by certain input an function with a subroutine would be less efficient by
combinations (such as the earlier Emergency Override), at least an order of magnitude. Extra software is needed
the controller could shut down the machine immediate- for the simulation routines, and each step takes longer
ly andlor alert the host processor via the serial port. to execute for three reasons: several byte-wide logical
Code bytes indicating the nature of the problem could instructions are executed per user program step (rather
be transmitted to a central computer. In fact, at 17,000 than one Boolean operation): most of those instructions
bytes-per-second, the entire contents of both bit maps take longer to execute with microprocessors""performing
could be sent to the host processor for further analysis multiple off-chip accesses: and calling and returning
in less than a millisecond! If the host decides that con- from the various subroutines requires overhead for
ditions warrant, it could alert other remote processors stack operations.
in the system that a problem exists and specify which
shut-down sequence each should initiate. For more in- In fact, the speed of the Boolean Processor solution is
formation on using the serial port, consult the MCS-Sl " likely to be much faster than the system requires. The
User's Manual. CPU might use the time left over to compute feedback
parameters, collect and analyze execution statistics,
Response Timing perform system diagnostics; and so forth.
One difference between relay and programmed indus-
trial controllers (when each is considered as a "black Additional Functions and Uses
box") is their respective reaction times to input chang-
es. As reflected by a ladder diagram, relay systems con- With the building-block basics mentioned above many
tain a large number of "rungs" operating in parallel. A more operations may be synthesized by short instruc-
change in input conditions will begin "propagating tion sequences.
through the system immediately, possibly affecting the
output state within milliseconds. Exclusive-OR. There are no common mechanical devic-
es or relays analogous to the Exclusive-OR operation,
Software, on the other hand, operates sequentially. A so this instruction was omitted from the Booiean
change in input states will not be detected until the next Processor. However, the Exclusive-OR or· Exclusive-
iime an input scan is periormed, and wiii not affect the NOR operation may be performed in two instructions
outputs until that section of the program is reached. by conditionally complementing the carry or a Boolean
For that reason the raw speed of computing the logical variable based on the state of any other testable bit.
functions is of extreme importance.
Here the Boolean processor pays off. Every instruction ;EXCLUSIVE-;OR FUNCTION IMPOSED ON CARR~
mentioned in this Note completes in one or two micro- ;USING FO IS INPUT VARIABLE."
seconds-the minimum instruction execution time for ;XOR_FO: JNB FO,XORCNT ;(nJB" FOR X-NOR)
many other microcontrollers! A ladder diagram con- .CPL C
taining a hundred rungs, with an average of four con- ;XORCNT: ••••• "•••
tacts per rung can be replaced by approximately five
hundred lines of software. A complete pass through the
entire matrix scanning routine and all computations xeH. The contents of the carry and some other bit may
would require about a millisecond: less than the time it be exchanged (switched) by using the accumulator as
takes for most relays to change state. " temporary storage. Bits can be moved into and out of
the accumulator simultaneously using the Rotate-
10-250
inter AP-70
through-carry instructions, though this would alter the Design Example 2 can be extended quite readily to 16
accumulator data. or more bits by using multi-byte input and output buff-
ers.
;EXCHANGE CARRY WITH USRFLG Many mass data storage peripherals and serial commu-
XCHBIT: RLC A nications protocols include Cyclic Redundancy (CRC)
MOV C,USR_FLG codes to verify data integrity. The function is generally
RRC A computed serially by hardware using shift registers and
MOV USR_FLG,C Exclusive-OR gates, but it can be done with software.
RLC A As each bit is received into the carry, appropriate bits
in the multi-byte data buffer are conditionally comple-
mented based on the incoming data bit. When finished,
Extended Bit Addressing. The 8051 can directly address the CRC register contents may be checked for zero by
144 general-purpose bits for all instructions in Figure ORing the two bytes in the accumulator.
3b. Similar operations may be extended to any bit any-
where on the chip with some loss of efficiency.
4.0 SUMMARY
The logical operations AND, OR, and Exclusive-OR
are performed on byte variables using six different ad- A truly unique facet of the Intel MCS-51 microcomput-
dressing modes, one of which lets the source be an im- er family design is the collection of features optimized
mediate mask, and the destination any directly address- for the one-bit operations so often desired in real-world,
able byte. Any bit may thus be set, cleared, or comple- real-time control applications. Included are 17 special
mented with a three-byte, two-cycle instruction if the .instructions, a Boolean accumulator, implicit and direct
mask has all bits but one set or cleared. addressing modes, program and mass data storage, and
many I/O options. These are the world's first single-
Byte variables, registers, and indirectly addressed RAM chip microcomputers able to efficiently manipulate, op-
may be moved to a bit addressable register (usually the erate on, and transfer either bytes or individual bits as
accumulator) in one instruction. Once transferred, the data.
bits may be tested with a conditional jump, allowing
any bit to be polled in 3 microseconds-still much fast- This Application Note has detailed the information
er than most architectures-or used for logical calcula- needed by a microcomputer system designer to make
tions. (This technique can also simulate additional bit full use of these capabilities. Five design examples were
addressing modes with byte operations.) used to contrast the solutions allowed by the 8051 and
those required by previous architectures. Depending on
Parity of bytes or bits. The parity of the current accu" the individual application, the 8051 solution will be eas-
mulator contents is always available in the PSW, from ier to design, more reliable to' implement, debug, and
whence it may be moved to the carry and further verify, use less program memory, and run up to an or-
processed. Error-correcting Hamming codes and simi- der of magnitUde faster than the same function imple-
lar applications require computing parity on groups of mented on previous digital computer architectures.
isolated bits. This can be done by conditionally comple-
menting the carry flag based on those bits or by gather- Combining byte- and bit-handling capabilities in a sin-
ing the bits into the accumulator (as shown in the DES gle microcomputer has a strong synergistic effect: the
example) and then testing the. parallel parity flag. . power of the result exceeds the power of byte- and bit-
processors laboring individually. Virtually all user ap-
Multiple byte shift and eRe codes plications will benefit in some way from this duality.
Data intensive applications will use bit addressing for
Though the 8051 serial port can accommodate eight- or test pin monitoring or program control flags: control
nine-bit data transmissions, some protocols involve applications will use byte manipulation for parallel I/O
much longer bit streams. The algorithms presented in expansion or arithmetic calculations.
It is hoped that these design examples give the reader
an appreciation of these unique features and suggest
ways to exploit them in his or her own application.
10-251
1515-11 MCS-51 MACRO ASSEMBLER Vl.0
OB.JECT MODULE PLACED I.N : FO: AP70. HEX
ASSEMBLER INVOKED BY: .: Fl.aom51 ap70 ore date(328)·
(
LOC OB.J LINE SOURCE.
SXREF TITLE(AP'-70 APPENDIX)
2
3
; ******************************-:.*****.*~*****************
4 THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET
5 OF THE INTEL E051 MICROCOMPUTER TO PERFORM A NUMBER OF
6 AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS. RELATING TO
7 TURN SIGNAL CONTROL. EMERGENCY BLINKERS. BRAKE LIGHT
8
9
10
CONTROL. AND PARKING LIGHT OPERATION.
THE ALGOR·ITHMS AND' HARDWARE ARE DESCR IBED IN DESJGN
ExAMPLE .. 1I4 OF INTEL' APPLICATION NOTE AP-70.
0»
Oc
'11 "USING. THE.... IN·TEL MCS-51 <TM) ::::J,...
12
'13
BOOLEAN PROCESSING CAPABILITIES" ,...0
14" .;************************'-***************~**************** "'3
15
16 INPUT PIN DECLARATIONS: go»
17
18
(ALL INPUTS ARE POSITIVE-TRUE LOGIC.
INPUTS· ARE HIGH WHEN 'RESPECTIVE SWITCH CONTACT IS CLOSED. f ~~"tJ
19 -"tJ
.... 0090 20 BRAKE BIT PI. 0 BRAKE PEDAL· DEPRESSED "tJCD m ~
o
rU
0091 21 EMERG BIT PI. 1 EMERGENCY BLINKER ACTIVATED
"'-IZ 'U
(11
I\)
0092
0093
22
23
PARK
L_TURN
BIT
BIT
PI. 2
PI. 3
PARKING LIGHTS ON
TURN LIEVER DOWN OCe
CC ... _ 21
0094 24 R_TURN BIT PI. 4 TURN LEVER UP
. 25 "'::::J><
D) •
26 OUTPUT PIN DECLARATIONS:
27
28
(ALL OUTPUTS ARE POSITIVI: TRUE LOGIC
BULB IS TURNED ON WHEN OUTPUT PIN IS HIGH.
35'»
29 r- Co
_.
-·n
0095
0096
0097
OOAO
30
31
32
33
L1RNT
R_FRNT
L_DASH
R,-DASH
BIT
BIT
BIT
BIT
PI. 5
PI. 6
PI 7
P2.0
FRONT I_EFT-TURN INDICATOR
FRONT IHGHT-TURN INDICATOR
DASHBO.~RD LEFT'-TURN INDICATOR
DASHBO.~RD RIGHT-TURN INDICATOR
_.
tn
,...D)
::::JO
.
,...
OOAI 34 L_REAR BIT P2. I REAR, LI::FT-TURII! INDICATOR.' CC ...
00A2 35 R_REAR BIT P2. 2 REAR'RIGHT-TURN INDICATOR
36
00A3 37 S_FAIL BIT P2 . .J ELECTR.ICAL SYSTEM FAULT 'INDICATOR
38
39 INTERNAL VARIABLE DEFINI"rIONS:
40
0020 41 SUB DIV DATA 20H INTERRUPT RATE SUBDIVIDER
0000 42 HIJ"REG lilT SUB_DIV. 0 HIGH-FREGUENCY OSCILLATOR BIT.
0007 43 LO_FREG BIT SUB_DIV. 7 LOW-FREGUENCY OSCILLATOR BIT
44 ;
00D1 45 DIM BIT PSW. I PARKING LIGHTS ON FLAG
46
47 ; =======:::========.==;=============::========:=============:===
'48 +1 $E.JECT
203830-26
LOC OD.J
0000 020040
LINE
49
:10
SOURCE
ORG
L.J.MP
OOOOH
INIT
RESET VECTOR
(
51
OOOB 52 ORG OOOBH TIMER 0 SERVICE VECTOR
OOOD 7:18CFO 53 MOV THO •• -16 HIGH TIMER BYTE AD.JUSTED TO CONTROL INT RATE
OOOE CODO 54 PUSH PSW EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW
0010 0.154 55 A.JMP UPDATE (CONTINUE WITH REST .OF ROUTINE)
56
0040 57 ORG 0040H
0040 758AOO 58 INIT: MOV TLO •• O ZERO LOADED INTO LOW-ORDER BYTE AND
0043 7:18CFO 59 MOV THO •• -16 -16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD
0046 758961 60 MOV TMOD •• OI10000IB 8-BIT AUTO RELOAD COUNTER MODE FOR TIMER 1.
61 16-BIT TIMER MODE FOR T'IMER 0 SELECTED
0049 7520F4 62 MOV SUD_DIV •• 244 SUBDIVIDE INTERRUPT RATE BY 244 FOR I HZ
004C D2A9 63 SETB ETO USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM
004E D2AF 64 SETB EA CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS
0050 D2BC 65 SETB TRO KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW
0052 BOFE ·66 S.JMP S START BACKGROUND PROGRAM EXECUTION
67
68
0054 D52038 ·69 UPDATE: D.JNZ SUD_DIV.TOSERV EXECUTE SYSTEM TEST ONLY ONCE PER SECOND
0057 7520F4 70 MOV. SUB_DIV •• 244 GET VALUE FOR NEXT ONE SECOND DELAY AND
71 GO THROUGH ELECTRICAL SYSTEM TEST CODE:
..... 005A 4390EO 72 ORL Pl •• 11100000B SET CONTROL OUTPUTS HIGH »
o
ro
(J1
005D
0060
43A007
C295
73
74
ORL
CLR
P2 •• 000pOll1B
LJRNT FLOAT DRIVE COLLECTOR
l'
......
t.)
0062 20D428 ·75 .JD TO. FAULT TO SHOULD BE PULLED LOW o
0065 D295 76 SETB L_FRNT PULL COLLECTOR BACK DOWN
0067 C297 -77 CLR L_DASH REPEAT SEGUENCE FOR L __ DASH.
0069 20D421 78 .JB TO. FAULT
006C D297 79 SETB L_DASH
006E C2Al 80 CLR L_REAR L REAR.
0070 20B41A 81 .JB TO. FAULT
0073 D2Al 82 SETB L_REAR
0075 C296 83 CLR R_FRNT R_FRNT.
0077 20B413 84 .JB TO. FAULT
007A D296 85 SETB RjRNT
007C' C2AO 86 CLR R_DASH R_DASH.
007E 20B40C 87 .JB TO. FAULT
0081 D2AO 88 SETB R_DASH
00B3 C2A2 89 CLR R_REAR AND R__REAR.
00B5 20B405 90 .JB TO. FAULT
0088 D2A2 91 SETB R_REAR
9;;1
93 WITH ALL COLLECTORS GROUNDED. TO SHOULD BE HIGH
94 IF SO. CONTINUE WITH INTERRUPT ROUTINE.
95
008A 20B402 96 .JB TO. TOSERV
008D B2A3 97 FAULT_ CPL S_FAIL ELECTRICAL FAILURE PROCESSING ROUTINE
98 (TOGGLE INDICATOR ONCE PEH SECOND)
99 +1 SE.JECT
203830-27
--
LoC DB.! LINE
100
101
102
103
SOURCE
II
CONTINUE WITH INTERRUPT I'RoCESSING:
COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON.
II cf
OOBF A201 104 TOSERV: l'IOV C.SUB_DIV I START WITH 50 PERCENT.
0091 B200 105 ANL C.SUB_DIV 0 MASK ·DOWN TO 25· PERCENT.
0093 7202 lOb ORL C. SUB_DIV 2 BUILD BACK TO b2. 5 PERCENT.
0095 B292 107 ANL C.PARK GATE WITH PARKING LIGHT SWITCH.
0097 92DI lOB 1'I0V DII'I.i; AND SAVE IN TEMP. IIARIABLE.
109
110 21 COMPUTE AND OUTPUT LEFT~iAND DASHBOARD INDICATOR.
III
0099 A293 112 1'I0V C. L_TURN SET CARRY IF TURN
009B 7291 113 ORL C.EI'IERG OR EMERGENCY SELECTED.
009D B207 114 ANL C.Lo_FREG IF SO. GATE IN I HZ SIGNAL
009F 9297 115 1'I0V L_DASH. C AND OUTPUT TO DASHBOARD.
lib
117 31 COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL.
liB
OOAI 92D5 119 l'IOV FO.C SAllE FUNCTION SO FAR.
00A3 72DI 120 ORL C.DII'I ADD IN PARKING LIGHT FUNCTION
00A5 9295 121 l'IOV L_FRNT. C ; AND OUTPUT TO TURN .SIGNAL.
122
..... 123 41 COMPUTE AND OUTPUT LEFT-liAND REAR TURN SIGNAL. :.
9 124 'U
•
....
I\)
....
U1
00A7
00A9
OOAB
A2'10
BO'13
72D5
125
126
127
1'I0V
ANL
oRL
C.BRAKE
C./L_TURN
C.FO
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.
INCLUDE TEMP. VARIABLE FROM DASH
II e
OOAD 72DI 12B ORL C.DII'I AND PARKING LIGHT FUNCTION
OOAF 92AI 129 1'I0V L_REAR. C AND OUTPUT TO TURN SIGNAL.
130
131 51 REPEAT ·ALL OF ABOIIE FOR IUGHT-HAND COUNTERPARTS.
132
0081 A294 133 MOil C:R_TURN SET CARRY IF ·TURN
00B3 7291 134 ORL C"-EI'IERG OR EMERGENCY SELECTED.
00B5 8207 135 ANL C. LO_FREG IF SO; GATE IN I HZ SIGNAL
00B7 92AO 13b MOil R_DASH. C AND OUTPUT TO DASHBOARD.
00B9 92D5 137 MOil FO.C SAVE FUNCTION SO FAR.
OOBB 72Dl 13B ORL C.DII'I ADD IN PARKING LIGHT FUNCTION
OOBD 929b 139 1'I0V R_FRNT. C AND OUTPUT TO TURN SIGNAL.
OOBF A290 140 l'IOV C.BRAKE GATE BRAKE PEDAL SWITCH
OOCI B094 141 ANL C./R_TURN WITH TURN LEVER.
00C3 72D5 142 oRL C.FO INCLUDE TEMP. VARIABLE FROM DASI!
DOCS 72Dl 143 ORL C.DII'I AND PARKING LIGHT FUNCTION
·00C7 92A2 144 1'I0V· R_REAR. C AND OUTPUT TO TURN SIGNAL.
145
14b RESTOR·E STATUS REGISTER AND RETURN.
147
00C9 DODO 14B POP PSW RESTORE PSW
OOCB 32 149 RETI ; AND RETURN FROM INTERRUPT ROUTINE
150
!51 END
203830-28
_.
XREF SYMBOL TABLE LISTING
NAME TYPE VALUE AND REFERENCES
ct
BRAKE N BSEG 0090H 2011 125 140
DIM N BSEG OODIH 4511 lOB 120 12B 13B 143
EA N BSEG OOAFH 64
EMERG N BSEG 0091H 2111 113 134
ETa N BSEG 00A9H 63
FO N BSEG 00D5H 119 127 137 142
FAULT L CSEG OOBDH 75 7B BI B4 B7 90 9711
HI_FRE<l N BSEG OOOOH 42#
INIT. L CSEG 0040H 50 5BII
L_DASH. N BSEG 0097H 3211 77 79 lIS
L_FRNT. N BSEG 0095H 3011 74 76 121
L_REAR. N BSEG OOAIH 34# 80 82 129
L_TURN. N BSEG 0093H 23ft 112 126
LO FRE<l N BSEG 0007H 4311 114 13~
PI:- N DSEG 0090H 20 21 22 23 24 30 31 32 72
P2. N DSEG OOAOH 33 34 35 37 73
PARK N BSEG 0092H 22* 107
PSW N DSEG OODOH 45 54 14B
<?
R_DASH ..
R_FRNT
N
N
BSEG
BSEG
OOAOH
0096H
3311 B6 BB 136
3111 B3 B5 139
»
"tI
I\)
R_REAR N BSEG OOA2H 3511 B9 91 144 •
.....
01
01 R_TURN
S_FAIL.
N
N
BSEG
BSEG
0094H
00A3H
2411 133 141
3711 97
I I C
SUB_DIV N DSEG 0020H 4111 42 43 62 69 70 104 105 106
TO. N BSEG 00B4H 75 7B BI B4 B7 90 96
TOSERV. L CSEG OOBFH 69 96 10411
THO N DSEG OOBCH 53 59
TLO N DSEG OOBAH 5B
TMOD N DSEG 00B9H 60
TRO N BSEG OOBCH 65
UPDATE L CSEG 0054H :;5 6911
ASSEMBLY COMPLETE. NO ERRORS FOUND
203830-29
APPLICATION AP-125
NOTE
November 1986
Designing Mi,crocontroller
Systems for Electrically
Noisy Environments
TOM WILLIAMSON
MCO APPLICATIONS ENGINEER
Order Number: 210313-002
10-256
AP-125
Digital circuits are often thought of as being immune to Types and Sources of Electrical Noise
noise problems, but really they're not. Noises in digital
systems produce software upsets: program jumps to ap- The name given to electrical noises other than those
parently random locations in memory. Noise-induced that are inherent in the circuit components (such as
glitches in the signal lines can cause such problems, but thermal noise) is EMI: electromagnetic interference.
the supply voltage is more sensitive to glitches than the Motors, power switches, fluorescent lights, electrostatic
signal lines. discharges, etc., are sources of EM!. There is a veritable
alphabet soup of EMI types, and these are briefly de-
Severe noise conditions, those involving electrostatic scribed below.
discharges, or as found in automotive environments,
can do permanent damage to the hardware. Electrostat-
ic discharges can blow a crater in the silicon. In the SUPPLY LINE TRANSIENTS
automotive environment, in ordinary operation, the
Anything that switches heavy current loads onto or off
"12V" power line can shown + and -400V transients.
of AC or DC power lines will cause large transients in
This Application Note describes some electrical noises these power lines. Switching an electric typewriter on
or off, for example, can put a 1000Y spike onto the AC
and noise environments. Design considerations, along
the lines of PCB layout, power supply distribution and power lines.
decoupling, and shielding and grounding techniques,
The basic mechanism behind supply line transients is
that may help minimize noise susceptibility are re-
shown in Figure I. The battery represents any power
viewed. Special attention is given to the automotive and
source, AC or DC. The coils represent the line induc-
ESD environments.
tance between the power source and the switchable
loads Rl and R2. If both loads are drawing current, the
line current flowing through the line inductance estab-
Symptoms of Noise Problems lishes a magnetic field of some value. Then, when one
Noise problems are not usually encountered during the of the loads is switched off, the field due to that compo-
development phase of a microcontroller system. This is nent of the line current collapses, generating transient
because benches rarely simulate the system's intended voltages, v = L(dildt), which try to maintain the cur-
environment. Noise problems tend not to show up until rent at its original level. That's called an "inductive
the system is installed and operating in its intended en- kick." Because of contact bounce, transients are gener-
vironment. Then, after a few minutes or hours of nor- ated whether the switch is being opened or closed, but
mal operation the system finds itself someplace out in they're worse when the switch is being opened.
left field. Inputs are ignored and outputs are gibberish.
The system may respond to a reset, or it may have to be An inductive kick of one type or another is involved in
turned off physically and then back on again, at which most line transients, including those found in the auto-
point it commences operating as though nothing had motive environment. Other mechanisms for line tran-
happened. There may be an obvious cause, such as an sients exist, involving noise pickup on the lines. The
electrostatic discharge from somebody's finger to a key- noise voltages are then conducted to a susceptible cir-
board or the upset occurs every time a copier machine cuit right along with the power.
is turned on or off. Or there may be no obvious cause,
and nothing the operator can do will make the upset EMP AND RFI
repeat itself. But a few minutes, or a few hours, or a few
days later it happens again. Anything that produces arcs or sparks will radiate elec-
tromagnetic pulses (EMP) or radio-frequency interfer-
One symptom of electrical noise problems is random- ence (RFI).
ness, both in the occurrence of the problem and in what
the system does in its failure. All operational upsets
that occur at seemingly random intervals are not neces- L
sarily caused by noise in the system. Marginal VCC,
inadequate decoupling, rarely encountered software
conditions, or timing coincidences can produce upsets
that seem to occur randomly. On the other hand, some v -
noise sources can produce upsets downright periodical- Rl R2
ly. Nevertheless, the more difficult it is to characterize
an upset as to cause and effect, the more likely it is to
be a noise problem. 210313-1
Figure 1. Supply Line Transients
10-257
inter AP-125
Spark discharges have probably caused more software the classical "ground loop." By extension, the term is
upsets in digital equipment than any other single noise used to refer to any unwanted (and often unexpected)
source. The upsetting mechanism is the EMP produced currents in a ground line.
by the spark. The EMP induces transients in the cir-
cuit, which are what actually cause the upset.
"Radiated" and "Conducted" Noise
Arcs and sparks occur in automotive ignition systems,
electric motors, switches, static discharges, etc. Electric Radiated noise is noise that arrives at the victim circuit
motors that have commutator bars produce an arc as in the form of electromagnetic radiation, such as EMP
the brushes pass from one bar to the next. DC motors and RFI. It causes trouble by inducing extraneous volt-
and the "universal" (AC/DC) motors that are used to ages in the circuit. Conducted noise is noise that arrives
power hand tools are the kinds that have commutator at the victim circuit already in the form of an extrane-
bars. In switches, the same inductive kick that puts ous voltage, typically via the AC or DC power lines.
transients on the supply lines will cause an opening or
closing switch to throw a spark. One defends against radiated noise by care in designing
layouts and the use of effective shielding techniques.
One defends against conducted noise with filters and
ESD
Electrostatic discharge (ESD) is the spark that occurs
when a person picks up a static charge from walking 80
I , - - EXPERIMENTAL
across a carpet, and then discharges it into a keyboard, /
-Vo = 40
"kv, - - - ' CALCULATED
or whatever else can be touched. Walking across a car- I \
I \
pet in a dry climate, a person can accumulate a static \
60
voltage of 35kV. The current pulse· from an electrostat- \
\
en
ic discharge has an extremely fast risetime - typically, 11. \
\
< \
4A/ns. Figure 2 shows ESD waveforms thllt have been ==
z \
\
observed by some investigators of ESD phenomena. ;: 40 \ \
zw \ \
It is enlightening to calculate the L(di/dt) voltage re- ~
::>
quired to drive an ESD current pulse through a couple u
20
of inches of straight wire. Two inches of straight wire
has about SO nH of inductance. That's not very much,
but using SO nH for Land 4A/ns for di/dt gives an
L(di/dt) drop of about 200V. Recent observations .by
W.M. King suggest even faster risetimes (Figure 2b) o 10 20 30 40 50 60 70 80 90 100 110 120
and the occurrence of multiple discharges during a sin- TIME IN NANOSECONDS
gle discharge event. 210313-2
(a)
Obviously, ESD-sensitivity needs to. be considered in
the design of equipment that is going to be subjected to
it, such as office equipment.
GROUND NOISE
Vert: 5 Amps/DiY
Currents in ground lines are another source of noise. Time: 5 nSec/Diy
These can be 60 Hz currents from the power lines, or Displayed:
RF hash, or crosstalk from other signals that are shar- Ip: 40 Amps
Tr: 1 nSec
ing this particular wire as a signal return line. Noise in 500V
the ground lines is often referred to as a "ground loop" ,
problem. The basic concept of the ground loop is
shown in Figure 3. The problem is that true
earth-ground is not really at the same potential in all 210313-3
locations. If the two ends of a wire are earth-grounded (b)
at different locations, the voltage difference between the
two "ground" points can drive significant currents (sev- Figure 2. Waveforms of Electrostatic
eral amperes) through the wire. Consider the wire to be Discharge Currents From a
part of a loop which contains, in addition to the wire, a Hand-Held Metallic Object
voltage source that represents the difference in poten-
tial between the two ground points, and you have
10-258
AP-125
suppressors, although layouts and grounding tech- of the program to'some random location in memory.
niques.are important here, too. The person who has to iron out such problems is tempt-
ed to say the program counter went crazy. There is
usually no damage to the hardware, and normal opera-
Simulating the Environment tion can resume as soon as the EM! has passed or the
source is de-activated. Resuming normal operation usu-
Addressing noise problems after the design of a system ally requires manual or automatic reset, and possibly
has been completed is an expensive proposition. The ill re-entering of lost information.
will generated by failures in the field is not cheap either.
It's cheaper in the long run to invest a little time and Electrostatic discharges from operating personnel can
money in learning about noise and noise simulation cause not only software upsets, .but also permanent
equipment, so that controlled tests can be made on the ("hard") damage to the system. For this to happen the
bench as the design is developing. system doesn't even have to be in operation. Sometimes
the permanent damage is latent, meaning the initial
Simulating the intended noise environment is a two- damage may be marginal and require further aggrava-
step process: First you have to recognize what the noise tion through operating stress and time before perma-
environment is, that is, you have to know what kinds of nent failure takes place. Sometimes too the damage is
electrical noises are present, and which of them are go- . hidden.
ing to cause trouble. Don't ignore this first step, be-
cause it's important. If you invest in an induction coil One ESD-related failure mechanism that has been iden-
spark generator just because your application is auto- tified has to do with the bias voltage on the substrate of
motive, you'll be straining at the gnat and swallowing the chip. On some CPU chips the substrate is held at
the camel. Spark plug noise is the least of your worries - 2.5V by a phase-shift oscillator working into a capac-
in that environment. itor/diode clamping circuit. This is called a "charge
pump" in chip-design circles. If the substrate wanders
The second step is to generate the electrical noise in a too far in either direction, program read errors are not-
controlled manner. This is usually more difficult than ed. Some designs have been known to allow electrostat-
first imagined; one first imagines' the simulation in ic discharge currents to flow directly into port pins of
terms of a waveform generator and a few spare parts, an 8048. The resulting damage to the oxide causes an
and then finds that a wideband power amplifier with a increase in leakage current, which loads down the
200V dynamic range is als!, required. A good source of charge pump, reducing the substrate voltage to a mar-
information on who supplies what noise-simulating ginal or unacceptable level. The system is then unreli-
equipment is the 1981 "ITEM" Directory and Design able or completely inoperative until the CPU chip is
Guide (Reference 6). replaced. But if the CPU chip was subjected to a dis-
charge ~park once, it will eventually happen again.
Types of Failures and Failure Chips that have a grounded substrate, such as the 8748,
Mechanisms can sometimes sustain some oxide damage without ac-
tually becoming inoperative. In this case the damage is
A major problem that EMI can cause in digital systems present, and the increased leakage current is noted;
is intermittent operational malfunction. These software however, since the substrate voltage retains its design
upsets occur when the system is in operation at the time value, the damage is largely hidden.
an EMI source is activated, and are' usually character-
ized by a loss of information or a jump in the execution
EARTH-GROUND
ATB
\.POTENTIAL DIFFERENCE
BETWEEN A AND B
-GROUND LOOP"
210313-4
Figure 3. What a Ground Loop Is
10-259
intJ AP-125
It must therefore, be recognized that connecting port to minimize the generation of noise voltages in the cir-
pins unprotected to a keyboard or to anything else that cuit. These methods involve grounding, shielding, and
is subject to electrostatic discharges, makes an extreme- wiring techniques that are directed toward the mecha-
lydangerous configuration. It doesn't make any differ- nisms by which noise voltages are generated in the cir-
ence what CPU chip is being used, or who makes it. If cuit. We'll also discuss methods of decoupling. Then
it connects unprotected to a keyboard, it will eventually we'll look at some schemes for making a graceful recov-
be destroyed. Designing for an ESD-environment will ery from upsets that occur in spite of preventive mea-
be discussed further on. sures. Lastly, we'll take another look at two special
problem areas: electrostatic discharges and the automo-
We might note .here that MOS chips are not the only tive environment. '
components that are susceptible to permanent, ESD
damage. Bipolar and linear chips can also be damaged
in this way. PN junctions are subject to a hard failure Current Loops
mechanism called thermal secondary breakdown, in
which a current spike, such as from an electrostatic The first thing most people learn about electricity is
discharge, causes microscopically localized spots in the that current won't flow unless it can flow in a closed
junction to approach melt temperatures. Low power loop. This simple fact is sometimes temporarily forgot-
TIL chips are subject to this tyPe of damage, as are ten by the ,overworked engineer who has spent the past
op-arnps. Op-amps, in addition, often carry on-chip several years mastering the intricacies of the DO loop,
MOS capacitors which are directly across an external the timing loop, the feedback loop, and maybe even the
pin combination, and these are susceptible to dielectric ground loop. The simple current loop probably owes its
breakdown. apparent demise to the invention of the ground symbol.
By a stroke, of the pen one avoids, having to draw the
We return now to the subject of software upsets. Noise return paths of most of the current loops in the circuit.
transients can upset the chip through any pin, even an Then "ground" turns into an infinite current sink, so
output pin, because every pin on the chip connects to that any current that flows into it is gone and forgotten.
the substrate through apnjunction. However, the most Forgotten it may be, but it's not gone. It must return to
vulnerable pin is probably ,the VCe line, since it has its source, SO that its path will by all the laws of nature
direct access to all parts of the chip: every register, gate, form a closed loop.
flip-flop lind buffer. .
The physical geometry of a given current loop is the
The, menu of possible upset mechanisms is quite key to why it generates EMI, why it's susceptible to
lengthy. A transient on the ,substrate at the wrong time EMI, and how to shield it. Specifically, it's the area of
will generally cause a program read error. A false level the loop that matters.
at a control input can cause an extraneous or misdirect-
ed opcode fetch. A disturbance on the supply line can Any flow of current generates a magnetic field whose
flip a bit in the program counter or instruction register. intensity varies inversely to the distance from the wire
A short interruption or reversal of polarity 'on the sup- that carries the current. Two parallel wires conducting
ply line can actually turn the processor off, but not long currents + I and - I (as in signal feed and return lines)
enough for the power-up reset capacitor to discharge. would generate a nonzero magnetic field near the wires,
Thus when the transient ends, the chip starts up again where the distance from a given point to one wire is
without 'Ii reset. '. noticeably different from the distance to the other wire,
but farther away (relative to the wire spacing), where
A common failure mode is for the processor to lock the distances from a given point to either wire are about
itself into a tight loop. Here it may be executing the the saine, the fields from both wires tend to cancel out.
data in a table, or' the program counter may have Thus, maintaining proximity between feed and return
jumped a notch, so that the processor is now executing paths is an important way to minimize their interfer-
operands instead of opcodes, or it may be. trying to ence with other signals. The way to maintain their
fetch opcodes from a nonexistent external program proximity is essentially to minimize their loop area.
memory. And, because the mutual inductance from current loop
It should be emphasized that mechanisms for upsets A to current loop B is the same as the mutualinduc-
have to do with the arrival of noise-induced transients timce from current loop B to current loop A, a circuit
at the pins of the chips, rather than with the generation that doesn't radiate interference doesn't receive it ei-
of noise pulses within the chip itself, that is, it's not the ther.
chip that is picking up noise, it's the circuit.
Thus, from the standpoint of reducing both generation
of EMI and susceptibility to EMI, the hard rule is to
The Game Plan keep loop areas small. To say that loop areas should be
minimized is the same as saying the circuit inductance
Prevention is usually cheaper than suppression, so first
we'll consider some preventive methods that might help
10-260
inter AP-125
should be minimized. Inductance is by definition the Another application of the Faraday shield is in the elec-
constant of proportionality between current and the trostatically shielded transformer. Here, a conducting
magnetic field it produces: <P. = LI. Holding the feed foil is laid between the primary and secondary coils so
and return wires close together so as to promote field as to intercept the capacitive coupling between them. If
cancellation can be described either as minimizing the a system is being upset by AC line transients, this type
loop area or as minimizing L. It's the same thing. . of transformer may provide the fix. To be effective in
this application, the shield must be connected to· the
greenwire ground.
Shielding
There are three basic kinds of shields: shielding against SHIELDING AGAINST INDUCTIVE COUPLING
capacitive coupling, shielding against inductive cou-
pling, and RF shielding. Capacitive coupling is electric With inductive coupling, the physical mechanism in-
field coupling, so shielding against it amounts to shield- volved is a magnetic flux density B from some external
ing against electric fields. As will be seen, this is rela- interference source that links with a current loop in the
tively easy. Inductive coupling is magnetic field cou- victim circuit, and generates a voltage in the loop in
pling, so shielding against it is shielding against mag- accordance·with Lenz's law: v = -NA(dB/dt), where
netic fields. This is a little more difficult. Strangely in this case N = 1 and A is the area of the current loop
enough, this type of shielding does not in genc:ral in- in the victiin circuit.
volve the use of magnetic materials. RF shielding, the
classical "metallic barrier" against all sorts of electro- There are two aspects to defending a circuit against
magnetic fields, is what most people picture when they inductive pickup. One aspect is to try to minimize the
think about shielding. Its effectiveness depends partly offensive fields at their source. This is done by minimiz-
on the selection of the shielding material, but mostly, as ing the area of the current loop at the source so as to
it turns out, on the treatment of its seams and the ge- promote field· cancellation, as described in the section
ometry of its openirigs. on current loops. The other aspect is to minimize the
inductive pickup in the victim circuit by minimizing the
area of that current loop, since, from Lenz's law, the
SHIELDING AGAINST CAPACITIVE COUPLING induced voltage is proportional to this area. So the two
aspects really involve the same corrective action: mini-
Capacitive coupling involves the passage of interfering mize the areas of the current loops. In other words,
signals through mutual or stray capacitances that aren't minimizing the offensiveness of a circuit inherently
shown on the circuit diagram, but which the experi- minimizes its susceptibility.
enced engineer knows are there. Capacitive coupling to
one's body is what would cause an unstable oscillator to
change its frequency when the person reaches his hand
over the circuit, for example. More importantly, in a c.
digital system it causes crosstalk in multi-wire cables. NOISE
SOURCE ----11--- VICTIM
CKT
The way to block capacitive coupling is to enclose the
circuit or conductor you want to protect in a metal L. I
shield. That's called an electrostatic or Faraday shield.
If coverage is 100%, the shield does not have to be -4-
210313-5
grounded, but it usually is, to ensure that circuit-to-
shield capacitances go to signal reference ground rather (a) Capacitive Coupling
than act as feedback and crosstalk elements. Besides,
from a mechanical point of view, grounding it is almost /FARADAY SHIELD
inevitable.
A grounded Faraday shield can be used to break capac-
NOISE
SOURCE 11-- -11- VICTIM
CKT
itive coupling between a noisy circuit and a victim cir-
cuit, as shown in Figure 4. Figure 4a shows two circuits
capacitively coupled through the stray capacitance be- I I
tween them. In Figure 4b the stray capacitance is inter- ~
cepted by a grounded Faraday shield, so that interfer- 210313-6
ence currents are shunted to ground. For example, a
(b) Electrostatic Shielding
grounded plane can be inserted between PCBs (printed
circuit boards) to eliminate most of the capacitive cou- Figure 4. Use of. Faraday Shield
pling between them.
10-261
inter Ap·125
v. v.
I I------~---------
I -I
- - - / " ' " CURRENT LOOP
210313-7
Figure 5. External to the Shield, <p = 0
210313-8
Shielding against inductive coupling means nothing (a) Shield Has No Effect
more nor less than controlling the _dimensions of the
current loops in the circuit. We must look at four ex- I
amples of this type of "shielding": the coaxial cable, the I
I R
twisted pair, the ground plane, and the gridded-ground I
I ... - - - - - \ - - - - - - - - - ' - - - - ' I
PCB layout. I I I
~ ___ ) HIGH· FREQUENCY L __ _
CURRENT- PATH
The Coaxial Cable-Figure 5 shows a coaxial cable
carrying a current I from a signal source to a receiving ---------- ... ,..". ... ' ':'
load. The shield carries the same current as the center -)
I //
----
conductor. Outside the shield, the magnetic field pro- \ ~,' .
'- - ~ ~ "LOW.FREQUENCY
duced by + I flowing in the center conductor IS can- CURRENT PATH
celled by the field produced by - I flowing in the 210313-9
shield. To the extent that the cable is ideal.in producing (b) Two Return Paths
zero external magnetic field, it is immune to inductive
pickup from external sources. The cable adds effective- Figure 6. Use of Coaxial Cable
ly zero area to the loop. This is true only if the shield
carries the same-current as the center conductor. minimum loop area. Hence, for higher frequencies the
shield carries virtually- the same current as the center
In the real world, both the signal source and the receiv- conductor, and is therefore effective against both gener-
ing load are likely to have one end connected to a com- ation and reception of EMI.
mon signal ground. In that case, should the cable be
grounded at one end, both ends, or neither end? The Note that we have now introduced the famous "ground
answer is that it should be grounded at both ends. Fig- loop" problem, as shown in Figure 7a. Fortunately, a
ure 6a shows the situation when the cable shield is digital system has some built-in immunity to moderate
grounded at only one end. In that case the current loop ground loop noise. In a noisy environment, however,
runs down the center conductor of the cable, then back one can break the ground loop, and still maintain the
through the common ground connection. The loop area shielding effectiveness of the coaxial cable, by inserting
is not well defined. The shield not only does not carry an optical coupler, as shown in Figure 7b. What the
the same current as the center conductor, but it doesn't optical coupler does, basically, is allow us to re-define
carry any current at all. There is no field cancellation at the signal source as being ungrounded, so that that end
all. The shield has no effect whatsoever on either the of the cable need not be grounded, and still lets the
generation of EMI or susCeptibility to EM!. (It is, how- shield carry the same current as the center conductor.
ever, still effective as an electrostatic shield, or at least Obviously, if the signal source weren't grounded in the
it would be if the shield coverage were 100%.) first place, the optical coupler wouldn't be needed.
Figure 6b shows the situation when the cable is ground- The Twisted Pair-A cheaper way to minimize loop
ed at both ends. Does the shield carry all of the return area is to run the feed and return' wires right next to
current, or only a portion of it on account of the shunt- each other. This isn't as effective as a coaxial cable in
ing effect of the common ground connection? The an- minimizing loop area. An ideal coaxial cable adds zero
swer to that question depends on the frequency content area to the loop, whereas merely keeping the feed and
of the signal. In general, the current loop will follow the return wires next to each other is bound to add a finite
path of least impedance. At low frequencies, 0 Hz to area.
several kHz, where the inductive reactance is insignifi-
cant, the current will follow the path of least resistance. However, two things work to make this cheaper meth-
Above a few kHz, where inductive reactance predomi- od almost as good as a coaxial cable. First, real coaxial
nates, the current will follow the path of least induc- cables are not ideal. If the shield current isn't evenly
tance. The path of least inductance is the path of distributed around the center conductor at every cross-
10-262
AP-125
POTENTIAL DIFFERENCE
BETWEEN THE TWO
GROUND POINTS
(a) The Ground Loop
IOPTICAL COUPLER +5V
v.
r---~..., J f--"\
I
_____ J I
I
I
I
I
I
--_/
210313-11
(b) Breaking the Ground Loop
Figure 7. Use of Optical Coupler
section of the cable (it isn't), then field cancellation ex- Thus, if the feed path for a given signal zigzags its way
ternal to the shield is incomplete. If field cancellation is across the PCB, the return path for this signal is free to
incomplete, then the effective area added to the loop by zigzag right along beneath it on the ground plarie, in
the cable isn't zero. Second, in the cheaper method the such a configuration as to minimize the energy stored
feed and return wires can be twisted together. This not in the magnetic field produced by this current loop.
only maintains their proximity, but the noise picked up Minimal magnetic flux means minimal effective loop
in one twist tends to cancel out the noise picked up in area and minimal susceptibility to inductive coupling.
the next twist down the line. Thus the "twisted pair"
turns out to be about as good a shield against inductive The Gridded-Ground PCB Layout-The next best
coupling as coaxial cable is. thing to a ground plane is to layout the ground traces
on a PCB in the form of a grid structure, as shown in
The twisted pair does not, however, provide electrostat- Figure 8. Laying horizontal traces on one side of the
ic shielding (Le., shielding against capacitive coupling). board and vertical traces on the other side allows the
Another operational difference between them is that passage of signal and power traces. Wherever vertical
the coaxial cable works better at higher frequencies. and horizontal ground traces cross, they must be con-
This is primarily because the twisted pair adds more nected by a feed-through.
capacitive loading to the signal source than the coaxial
cable does. The twisted pair is normally considered use- Have we not created here a network of "ground loops"?
ful up to only about 1 MHz, as opposed to near a GHz Yes, in the literal sense of the word, but loops in the
for the coaxial cable. ground layout on a PCB are not to be feared. Such
inoffensive little loops have never caused as much noise
The Ground Plane-The best way to minimize loop pickup as their avoidance has. Trying to avoid innocent
areas when many current loops are involved is to use a little loops in the ground layout, PCB designers have
ground plane. A ground plane is a conducting surface forced current loops into geometries that could swallow
that is to serve as a return conductor for all the current a whale. That is exactly the wrong thing to do.
loops in the circuit. Normally, it would be one or more
layers of a multilayer PCB. All ground points in the The gridded ground structure works almost as well as
circuit go not to a grounded trace on the PCB, but the ground plane, as far as minimizing loop area is con-
directly to the ground plane. This leaves each current cerned. For a given' current loop, the primary return
loop in the circuit free to complete itself in whatever path may have to zig once in a while where its feed path
configuration yields minimum loop area (for frequen- zags, but you still get a mathematically optimal dis-
cies wherein the ground path impedance is primarily
inductive).
10-263
inter AP-125
against RF interference from a whip antenna .. A grid-
ded-ground,structure would be less effective.
In the near field of a loop antenna, the EIH ratio is
lower than 3770, which means it's mainly an H-field
generator. Any current loop is a loop antenna. Interfer-
ence from a loop antenna would be by magnetic field
coupling, which is basically the same as inductive cou-
pling. Methods to protect a circuit from inductive cou-
pling, such as a gridded-ground structure, would be ef-
fective against RF interference from a loop antenna. A
Faraday shield would be less effective.
A more difficult case of RF interference, near field or
far field, may require a genuine metallic RF shield. The
c:::3 DIP 0 g~~~g~~~G _ GROUND e E~Efp~'l:~~~C idea behind RF shielding is that time-varying EMI
fields induce currents in the shielding material. The in-
210.313-12 duced currents dissipate energy in two ways: J2R losses
in the shielding material and radiation losses as they re-
Figure 8. PCB with Gridded Ground radiate their own EM fields. The energy for both of
these mechanisms is drawn from the impinging EMi
tribution of currents in the grid structure, such that the fields. Hence the EMI is weakened as it penetrates the
current loop produces less magnetic flux than if the shield.
return path were restrained to follow any single given
ground trace. The key to attaining minimum loop areas More formally, the J2R losses are referred to as absorp-
for all the current loops together is to let the ground tion loss, and the re-radiation is called reflection loss.
currents distribute themselves around the entire area, of As it turns out, absorption loss is. the primary shielding
the board as freely as 'possible. They want to minimize mechanism for H-fields, and reflection loss is the pri-
their own magnetic field. Just let them. mary shielding mechanism for E-fields. Reflection loss,
being a surface phenomenon, is pretty much indepen-
RF SHIELDING dent of the thickness of the shielding material. Both
loss mechanisms, however, are dependent on the fre-
A time-varying electric field generates a time-varying quency (00) of the impinging EMI field, and on the
magnetic field, and vice versa. Far from the source of a permeability ("") and conductivity (0-) of the shielding
time-varying EM field, the ratio of the amplitudes of material. These loss mechanisms vary approximately as
the electric and magnetic fields is always 3770. Up follows:
close to the source of the fields, however, this ratio can 0-
reflection loss to an E-field (in dB) - log-
be quite different, and dependent on the nature of the 00""
source. Where the ratio is near 3770 is called the far
field, and where the ratio is significantly different from absorption loss to an H-field (in dB) - t~ooo-""
3770 is called the near field. The ratio itself is called
the wave impedance, E/H. where t is the thickness of the shielding material.
The near field goes out about 1/6 of a wavelength from The first expression indicates that E-field shielding is
the .source. At I MHz this is about 150 feet, and at 10 more effective if the shield material is highly conduc-
MHz it's about 15 feet. That means if an EMI source is tive, and less effective if the shield if ferromagnetic, and
in the same room with the victim circuit, it's likely to that low-frequency fields are easier to block than high-
be a near field problem. The reason this matters is that frequency fields. This is shown in Figure 9.
in the near field an RF interference problem could be
almost entirely due to E-field coupling or H-field cou- m 150
~
pling, and that could influence the choice of an RF II: 125
iii
shield or whether an RF shield will help at all. U>
0 100
.J
Z 75
In the near field of a whip antenna, the E/H ratio is 0
;::. 50
higher than 3770, which means it's mainly an E-field ...
U 25
generator. A wire-wrap post can be a whip antenna.
Interference from a whip antenna would be by electric
..
.J
II: 0.01 0.1 1.0 10 100 1000 10.000
field coupling, which is basically capacitive coupling. FREQUENCY (KILOHERTZ)
Methods to protect a circuit from capacitive coupling, 210.313-13
such as a Faraday shield, would be effective
Figure 9. E-Field Shielding
10-264
inter AP·125
175.-----------r-------r-r-------~
300,-----------------------------~
150 !
'" 250
PLANE WAVE
III
!
'111
~
200 .
150 .,,
,
,,
I
,"
Cl
z
9 100 ----""'-
REFLECTION ----I--
%
III
,,
~ 50 ,.'
25 I!
f:! "
_-----ABSORPTION
O+----.----~-~-~-~--;-~---_.----_r--~
0.01 0.1 1.0 10 100 1000 10.000
10 10' 10 1 10~ 10$ 10' 10' .FREQUENCY (KILOHERTZ)
FREQUENCY (HERTZ) 210313-15
210313-14
Figure 10. H·Field Shielding Figure 11. E· and H·Field Shielding
Copper and aluminum both have the same permeabili- rents must be allowed to flow freely. If they have to
ty, but copper is slightly more conductive, and so pro- detour around slots and holes, as shown in Figure 12,
vides slightly greater reflection loss to an E-field. Steel the shield loses much of its effectiveness.
is less effective for two reasons. First, it has a somewhat
elevated permeability due to its iron content, and sec- As can be seen in Figure 12, the severity of the detour
ond, as tends to be the case with magnetic materials, it has less to do with the area of the hole than it does with
is less conductive. the geometry of the hole. Comparing Figure 12c with
12d shows that a long narrow discontinuity such as a
On the other hand, according to the expression for ab~ seam can cause more RF leakage than a line of holes
sorption loss to an H-field, H-field shielding is more with larger total area. A person who is responsible for
effective at higher frequencies and with shield material designing or selecting rack or chassis enclosures for an
that has both high conductivity and high permeability. EMI environment needs to be familiar with the tech-
In practice, however, selecting steel for its high perme- niques that are available for maintaining electrical con-
ability involves some compromise in conductivity. But tinuity across seams. Information on these techniques is
the increase in permeability more than makes up for the available in the references.
decrease in conductivity, as can be seen in Figure 10.
This figure also shows the effect of shield thickness.
Grounds
A composite of E-field and H-field shielding is shown
in Figure 11. However, this type of data is meaningful There are two kinds of grounds: earth-ground and sig-
only in the far field. In the near field the EMI could be nal ground. The earth is not an equipotential surface, so
90% H-fie1d, in which case the reflection loss is irrele- earth ground potential varies. That and its other electri-
vant. It would be advisable then to beef up the absorp- cal properties are not conducive to its use as a return
tion loss, at the expense of reflection loss, by choosing 'conductor in a circuit. However, circuits are often con-
steel. A better conductor than steel might be less expen- nected to earth ground for protection against shock
sive, but quite ineffective. hazards. The other kind of ground, signal ground, is an
arbitrarily selected reference node in a circuit-the
A different shielding mechanism that can be taken ad- node with respect to which other node voltages in the
vantage of for low frequency magnetic fields is the abili- circuit are measured.
ty of a high permeability material such as. mumetal to
divert the field by presenting a very low reluctance path
SAFETY GROUND
to the magnetic flux. Above a few kHz, however, the
permeability of such materials is the same as steel. The standard 3-wire single-phase AC power distribu-
tion system is represented in Figure 13: The white wire
In actual fact the selection of a shielding material turns is earth-grounded at the service entrance. If a load cir-
out to be less important than the presence of seams, cuit has a metal enclosure or chassis, and if the black
joints and holes in the physical structure of the enclo- wire develops a short to the enclosure, there will be a
sure. The shielding mechanisms are related to the in- shock hazard to operating personnel, unless the enclo-
duction of currents in the shield material, but the cur- sure itself is earth-grounded. If the enclosure is earth-
10-265
intJ AP-125
~~1
__ INDUCED _ - RECT:LNO;ULAR
SHIELD
CURRENTS·
--SECTION OF
SHIELD
(-) (b)
(e) (d)
210313-16
Figure 12. Effect of Shield Discontinuity on Magnetically Induced Shield Current
grounded, a short results in a blown fuse rather than a SIGNAL GROUND
"hot" enclosure. The earth-ground connection to the
enclosure is called a safety ground; The advantage of Signal ground is a single point in a' circuit that is desig-
the. 3-\...ire power system .is that it distributes a safety nated to pe the reference node for the circuit. Common-
ground along with the power. ly, wires that connect to this single point are also re-
ferred to as "signal ground." In some circles "power
Note that the safety-ground wire carries no current, supply common" or PSC is the preferred terminology
except in case of a fault, so that at least for low frequen- for these conductors. In any case, the manner in which
cies it's at earth-ground potential. along its entire these wires connect to the actual reference point is the
length. The white wire, on the other. hand, may be sev- basis of distinction among· three kinds of signal-ground
eral volts off ground, due to the IR drop along its wiring methods: series, parallel, and multipoint. These
length. methods are shown in Figure 14.
The series connection is pretty common because it's
SERVICE METAL simple imd economical. It's the noisiest of the three,
(ENTRANCE ( ENCLOSURE
(-----:--" BLACK 1'"--------, however, due to common ground impedance coupling
I
I between the circuits. When several circuits share a
I
I
I
I ground wire, currents from one circuit, flowing through
I LOAD : the finite impedance of ihe common ground line, cause
I CKT I
I . I vari/l,tions in the ground potential of the other circuits.
: WHITE·
I Given that the currents in a digital system tend to be
I
·1
I ..... __ .- ----) spiked, and that the common impedance is mainly in-
ductive reactance, the variations could be bad enough
I GREEN
I~ ___ - to cause bit errors in high current or particularly noisy
situations. . ,
EARTH-GROUND The parallel connection eliminates common ground im-
210313-17 pedanceproblems, but uses a lot of wire. Other disad-
vantages are ·that the impedance of the individual
Figure 13. Single-Phase Power Distribution ground Jines can be very high, and .the. ground lines
themselves can become sources of EMI, .
10-266
inter AP-125
In the multipoint system, ground impedance is mini- QUIET NOISY HARDWARE
mized by using a ground plane with the various circuits SIGNAL
GROUND
AND HIGH
CURRENT
GROUND
connected to it by very short ground leads. This type of SIGNAL
GROUND
connection would be used mainly in RF circuits above
10 MHz.
PRACTICAL GROUNDING ' - - REF. POINT
A combination of series and parallel ground-wiring GREEN·WIRE
methods can be used to trade off economic and the GROUND
210313-21
various electrical considerations. The idea is to run se-
ries connections for circuits that have similar noise Figure 15. Parallel Connection
properties, and connect them at a single reference of Series Grounds
point, as in the parallel method, as shown in Figure 15. Screws and bolts don't always make good electrical
connections because of galvanic action, corrosion, and
In Figure 15, "noisy signal ground" connects to things dirt. These kinds of connections may work well at first,
like motors and relays. Hardware ground is the safety and then cause mysterious maladies as the system ages.
ground connection to chassis, racks, and cabinets. It's a
mistake to use the hardware ground as a return path for Figure 16 illustrates a grounding system for a 9-track
signal currents because it's fairly noisy (for example, digital tape recorder, showing an application of the se-
it's the hardware ground that receives an ESD spark) ries/parallel ground-wiring method.
and tends to have high resistance. due to joints and
seams. Figure 17 shows a similar separation of grounds at the
PCB leveL Currents in multiplexed LED displays tend
to put a lot of noise on the ground and supply lines
because of the constant switching and changing in-
volved in the scanning process. The segment driver
ground is relatively quiet, since it doesn't conduct the
LED currents. The digit driver ground is noisier, and
should be provided with a separate path to the PCB
ground terminal, even if the PCB ground layout is grid-
\GROUNDLINE \ ded. The LED feed and return current paths should be
REF. POINT
laid out on opposite sides of the board like parallel flat
210313-18 conductors.
Series Connection
Figure 18 shows right and wrong ways to make ground
connections in racks. Note that the safety ground con-
nections from panel to rack are made through ground
straps, not panel screws. Rack 1 correctly connects sig·
nal ground to rack ground only at the single reference
point. Rack 2 incorrectly connects signal ground to
rack ground at two points, creating a ground loop
around points I, 2, 3, 4, 1.
210313-19 Breaking the "electronics ground" connection to point
Parallel Connection 1 eliminates the ground loop, but leaves signal ground
in rack 2 sharing a ground impedance with the relative-
ly noisy hardware ground to the reference point; in fact,
it may end up using hardware ground as a return path
for signal and power supply currents. This will proba-
bly cause more problems than the ground loop.
BRAIDED CABLE
REF. POINT Ground impedance problems can be virtually eliminat-
210313-20 ed by using braided cable. The reduction in impedance
Multipoint Connection is due to skin effect: At higher frequencies the current
tends to flow along the surface of a conductor rather
Figure 14. Three Ways to Wire the Grounds
10-267
intJ AP-125
------------------------1
1 t( t( t( ~~_~M i
I 1
9 "WRITE" CIRCUITS
.
SIGNAL GROUNOS"
t
GREEN-WIRE
GROUND
210313-22
Figure 16. Ground System in a 9-Track Digital Recorder
CONTROL FUNCTIONS
CONTROLLER
I----.....--~~
'----~--~~----GROUND
210313-23
Figure 17. Separate Ground for Multiplexed LED Display
10-268
AP-125
RACK 1 RACK 2
P:6~~~Y c'JIf'=-_ _ _ _ _ _ _ _ _ _ _ _-'-ElECTRONICS GROUND
GROUND
GREEN-WIRE GROUND
21.0313-24
Figure 18_ Electronic Circuits Mounted in Equipment Racks Should Have Separate Ground
Connections_ Rack 1 Shows Correct Grounding, Rack 2 Shows Incorrect Grounding_
than uniformly threugh its bulk_ While this effect tends higher frequency cemponents .of EMI. This is illustrat-
to increase the impedance of a given conductor, it also ed in Figure 19b, which shows the capacitor supplying
indicates the way to minimize impedance, and that is to the current spike, during which VCC drops from 5V by
manipulate the shape of the cress-sectien se as te pre- the amount indicated in the figure. Between current
vide mere surface area. Fer its bulk, braided cable is spikes the capacitor recovers through the line imped-
almost pure surface. ance.
'One should resist the temptation to add a resistor or an
Power Supply Distribution and inductor to the decoupler so as to ferm a genuine RC .or
Decoupling LC low-pass filter because that slows down the speed
with which the decoupler cap can be refreshed. Good
The main consideratien for power supply distributien filtering and goed decoupling are not necessarily the
lines is, as for signal lines, to minimize the areas of the same thing.
current loops. But the power supply lines take on an
importance that no signal line has when one censiders The current loop for the higher frequency currents,
the fact that these lines have access to every PC board then, is defined by the decoupling cap and the load
in the system. The very extensiveness of the supply cur- circuit, rather than by the power supply and the load
rent loops makes it difficult to keep loop areas small. circuit. For the decoupling cap to be able to previde the
And, a noise glitch en a supply line is a glitch delivered current spikes required by the load, the inductance of
to every' board in the system. this current loop must be kept small, which is the same
as saying the leop area must be kept small. This is also
The power supply provides low-frequency current to the requirement for minimizing inductive pick-up in
the load, but the inductance of the board-te-board and the leop.
chip-to-chip distribution network makes it difficult for
the power supply to maintain VCC specs on the chip There are two kinds of decoupling caps: beard decou-
while providing the current spikes that a digital system pIers and chip deceuplers. A board decoupler will nor-
requires. In addition, the power supply current loop is a mally be a 10 te 100 p,F electrolytic capacitor placed
very large one, which means there will be a let of noise near to where the power supply enters the PC board,
pick-up. Figure 19a shows a load circuit trying to draw but its placement is relatively non-critical. The purpose
current spikes from a supply voltage through the line of the board decoupler is to refresh the charge on the
impedance. To the VCC waveform shown in that figure chip deceuplers. The chip decouplers are what actually
should be added the inductive pick-up associated with a provide the current spikes to the chips. A chip decou-
large loop area. pIer will normally be a 0.1 to 1 ,..,F ceramic capacitor
placed near the chip and connected to the chip by
Adding a decoupling capaciter selves two problems: traces that minimize the area of the loop formed by the
The capacitor acts as a nearby source of charge to sup- cap and the chip. If a chip decoupler is not properly
ply the current spikes through a smaller line imped- placed en the board, it will be ineffective as a decoupler
ance, and it defines a much smaller loop area for the
10-269
intJ AP-125
Vcc:
--------~-----------------. t
210313-25 210313-26
(a) Drawing Current Spikes (b) Drawing Current Spikes
through the Line Impedance from a Decoupllng Capacitor
Figure 19. What a Decoupling Capacitor Does
and will serve only to increase the cost of the board. ably so that each power trace is on the direct opposite
Good and bad placement of decoupling capacitors are side of the board from a ground trace.
illustrated in Figure 20.
Special-purpose power supply distribution buses which
Power distribution traces on the PC board need to be mount on the PCB are available. The buses use a paral-
laid out so as to obtain minimal area (miilimal induc- lel flat conductor configuration, one conductor being a
tance) in the loops formed by each chip and its decou- VCC line and the other a ground line. Used in conjunc-
pier, and by the chip decouplers and the board decou- tion with a gridded ground layout, they not only pro-
pier. One way to accomplish this goal is to use a power vide a' low-inductance distribution system, but can
plane. A power plane is the same as a ground plane, but themselves form part of the ground grid, thus facilitat-
at VCC potential. More economically, a power grid ing. the PCB layout. The buses are available with and
similar to the ground grid previously discussed (Figure without enhanced bus capacitance, under the names
8) can be used. Actually, if the chip decoupling loops MinilBus® and Q/PAC® from Rogers Corp. (5750 E.
are small, other aspects of the power layout are less . McKellips, Mesa, AZ 85205).
critical. In other words, power planes and power grid-
ding aren't needed, but power traces should be laid in .
the closest possible proximity to ground traces, prefer- SELECTING THE VALUE OF THE
DECOUPLING CAP
There must be a very low Inductance between decoupling capacitor
and the IC. The effectiveness of the decoupling cap has a lot to do
with the way the power and ground traces connect this
Poo,PI.cemen, ~I capacitor to the chip. In fact; the area formed by this
loop is more important than the value of the capaci-
~vcc
tance. Then, given that the area of this loop is indeed
miilimal, it can generally be said that the larger the
Better Pllleement value of the decoupling cap, the more effective it is, if
the cap has a mica, ceramic, glass, or polystyrene di-
electric.
. 210313-27 It's often said, and not altogether accurately, that the
The decreased area of loop between capacitor & IC decreases
, inductance. chip decoupler shouldn't have too large a value. There
are two reasons for this statement. One is that some
.Figure 20. Placement of Decoupllng Capacitors capacitors, because of the nature of their dielectrics,
tend to become inductive or lossy at higher frequencies.
This is true of electrolytic capacitors, but mica, glass,
10-270
inter AP-125
ceramic, and polystyrene dielectrics work well to sever- CPU chip and the PCB (or between the CPU socket
al hundred MHz. The other reason cited for not using and the PCB), it makes connection to pins 40 and 20,
too large a capacitance has to do with lead inductance. forming a leadless decoupling capacitor. It is obviously
a configuration of minimal inductance. Unfortunately,
The capacitor with its lead inductance forms a series the particular sample tested had only 0.07 J.tF of capac-
LC circuit. Below the frequency of series resonance, the itance and so was unable to prevent the 1 MHz ripple
net impedance of the combination is capacitive. Above as effectively as the configuration of Figure 21 d. It
that frequency, the net impedance is inductive. Thus a seems apparent, though, that with more capacitance
decoupling capacitor is capacitive only below the fre- this part will alleviate a lot of decoupling problems.
quency of series resonance. The frequency is given by
1 THE CASE FOR ON-BOARD VOLTAGE
fo = 21TM REGULATION
To complicate matters, supply line glitches aren't al-
where C is the decoupling capacitance and L is the lead ways picked up in the distribution networks, but can
inductance between the capacitor and the chip. On a come from the power supply circuit itself. In that case,
PC board this inductance is determined by the layout, a well-designed distribution network faithfully delivers
and is the same whether the capacitor dropped into the the glitch throughout the system. The VCC glitch in
PCB holes is 0.001 J.tF or 1 J.tF. Thus, increasing the Figure 22 was found to be coming from within a bench
capacitance lowers the series resonant frequency. In power supply in response to the EMP produced by an
fact, according to the resonant frequency formula, in- induction coil spark generator that was being used at
creasing C by a factor of 100 lowers the resonant fre- Intel during a study ·of noise sensitivity. The VCC
quency by a factor of 10. glitch is about 400 mV high and some 20 J.ts in dura-
tion. Normal board decoupling techniques were ineffec-
Figures quoted on the series resonant frequency of. a tive in removing it, but adding an on-board voltage reg-
0.01 J.tF capacitor run from 10 to 15 MHz, depending ulator chip did the job.
on the lead length. If these numbers were accurate, a
1 J.tF capacitpr in the same position on the board would Thus, a good case can be made in. favor of using a
have a resonant frequency of 1.0 to 1.5 MHz, and as a voltage regulator chip on each PCB, instead of doing all
decoupler would do more harm than good. However, the voltage regulation at the supply circuit. This eases
the numbers are based on a presumed inductance of a requirements on the heat-sinking· at the supply circuit,
given length of wire (the lead length). It should be not- and alleviates much of the distribution and board de-
ed that a "length of wire" has no inductance at all, coupling headaches. However, it also brings in the pos-
strictly speaking. Only a complete current loop has in- sibility that different boards would be operating at
ductance, and the inductance depends on the geometry slightly different VCC levels due to tolerance in the
of the loop. Figures quoted on the inductance of a regulator chips; this then leads to slightly different logic
iength of wire are based on a presumably "very large" levels from board to board. The implications of that
loop area, such that the magnetic field produced by the may vary from nothing to latch-up, depending on what
return current has no cancellation effect on the field kinds of chips are on the boards, and how they react to
produced by the current in the given length of wire. an input "high" that is perhaps O.4V higher than local
Such a loop geometry is not and should not be the case VCC. .
with the decoupling loop.
Figure 21 shows VCC waveforms, measured between Recovering Gracefully from a Software
pins 40 and 20 (VCC and VSS) of an 8751 CPU, for Upset .
several conditions of decoupling on a PC board that has·
a decoupling loop area slightly larger ihim necessary. Even when one follows all the best guidelines for de-
These photographs show the effects of increasing the signing for a noisy environment, it's always possible for
decoupling capacitance and decreasing the area of. the a noise transient to occur which exceeds the circuit's
decoupling loop. The indications are that a 1 J.tF capac- immunity level. In that case, one can strive at least for a
itor is better than a 0.1 J.tF capacitor,which in turn is graceful recovery.
better than nothing, and that the board should have
been laid out with more attention paid to the ·area of the Graceful recovery schemes involve additional hardware
decoupling loop. and/or software which is supposed to return the system
to a normal operating mode after a software upset has
Figure 21e was obtained using a special-purpose experi- occurred. Two decisions have to be made: How to rec-
mental capacitor designed by Rogers Corp. (Q-Pac Di- ognize when an upset has occurred, and what to do
vision, Mesa, AZ) for use as a decoupler. It consists of about it.
two parallel plates, the length of a 40-pin DIP, separat-
ed by a ceramic dielectric. Sandwiched between the
10-271
inter AP-125
PIN 40
PIN 40
. . . ALE
5CtrV 5V L _ "__
210313-28
(a) No Decoupllng Cap
PIN 40
5CmV 5V 501r.V 5V .
~ -~.
210313-'30 210313:'31 '
(c) 0.1 p.F Decoupler Stretched Directly' (d) 1.0 p.F Decoupler Stretched Directly
from Pin 40 to Pin 20, under the Socket. from Pin 40 to pin 20, under the Socket.
(The difference between this and 21b is (This prevents the 1 MHz,rlpple, but there's
due only to the change in loop geometry. no reduction In higher frequency components.
Also shown is the upward slope of a ripple Further Increases In capacitance
in VCC. The ripple frequency Is effected no further Improvement.)
1 MHz, the same as ALE.)
PIN 40
ALE
*' SV
210313-32
(e) Special-Purpose Decoupling Cap
under Development by Rogers Corp.
(Further discussion in text.)
Figure 21. Noise on VCC Line
10-272
inter AP-125
I
L t -f-· - .- - -.: ~ -~
I 1 • i
, I'
r-- -.. -T T .
r I ,
SPARK PROBE 50mV (TRIGGER)
Vee 500mV
210313-33
Figure 22. EMP-Induced Glitch
If the designer knows what kinds and combinations of NOPs and JMPs. It's still possible, of course, to get
outputs can legally be generated by the system, he can hung up in a data table or something. But you get a lot
use gates to recognize and flag the occurrence of an of protection, for the cost.
illegal state of affairs. The flag can then trigger a jump
to a recovery routine which then may check or re-ini- Further discussion of graceful recovery schemes can be
tialize data, perhaps output an error message, or gener- found in Reference 13.
ate a simple reset.
The most reliable scheme is to use a so-called watchdog Special Problem Areas
circuit. Here the CPU is programmed to generate a
periodic signal as long as the system is executing in- ESD
structionsin an expected manner. The periodic signal is
then used to hold off a circuit that will trigger a jump to MOS chips have some built-in protection against a stat-
a recovery routine. The periodic signal needs to be AC- ic charge build-up on the pins, as would occur during
coupled to the trigger circuit so that a "stuck-at" fault normal handling, but there's no protection against the
won't continue to hold off the trigger. Then, if the proc- kinds of current levels and rise times that occur in a
essor locks up someplace, the periodic signal is lost and genuine electrostatic spark. These kinds of discharges
the watchdog triggers a reset_ can blow a crater in the silicon.
In practice, it may be convenient to drive the watchdog It must be recognized that connecting CPU pins unpro-
circuit with a signal which is being generated anyway tected to a keyboard ()r to anything else that is subject
by the system. One needs to be careful, however, that to electrostatic discharges makes an extremely fragile
an upset does in fact discontinue that signal. Specifical- configuration. Buffering them is the very least one can
ly, for example, one could· use one of the digit drive do. But buffering doesn't completely solve the problem,
signals going to a multiplexed display. But display because then the buffer chips will sustain the damage
scanning is often handled in response to a timer-inter- (even TTL); therefore, one might consider mounting
rupt, whieh may continue operating even though the the buffer chips in sockets for ease of replacement.
main program is in a failure mode. Even so, with a little
extra software, the signal can be used to control the Transient suppressors, such as the TranZorbs® made
watchdog (see Reference 8 on this). by General Semiconductor Industries (Tempe, AZ),
may in the long run provide the cheapest protection if
Simpler schemes can work well for simpler systems. their "zero inductance" structure is used. The structure
For example, if a CPU isn't doing anything but scan- and circuit application are shown in Figure 23.
ning and decoding a keyboard, there's little to lose and The suppressor element is a pn junction that operates
much to gain by simply resetting it periodically with an like a Zener diode. Back-to-back units are available for
astable multivibrator. It only takes about 13 f.Ls (at 6 AC operation. The element is more or less an open
MHz) to reset an 8048 if the clock oscillator is already circuit at normal system voltage (the standoff voltage
running. rating for the device), and conducts like a Zener diode
at the clamping voltage.
A zero-cost measure is simply to fill all unused pro-
gram memory with NOPs and JMPs to a recovery rou- The lead inductance in the conventional transient sup-
tine. The effectiveness of this method is increased by pressor package makes the conventional package essen-
writing the program in segments that are separated by
10-273
inter AP-125
PULSE DIGITAL
H-r~--tB
FUNCTIONAL
H+,..,.--tc DECODER
H+-hr-:--tD
L ____ J
Patent Pending 210313-34 COMMON
(a) 210313-35
(b)
Figure 23. "Zero~lnductance" Structure and Use in Circuit
tially useless' for protection against ESD pulses, owing
to the fast rise of these pulses. The "zero inductance" Ambient Temperature
Grade
units are available singly in a 4-pin DIP, and in arrays Min Max
of four to a 16-pin DIP for PCB level protection. In
that application they should be mounted in close prox- Commercial 0 70
imity to the chips they protect. Industrial -40 +85
Automotive -40 +110
In addition,' metal enclosures or frames or parts that Military -55 +125,
can receive an ESD spark should be connected by
braided cable to the green-wire ground. Because of the The different product grades are actually the same
ground impedance, ESD current shouldn't be allowed chip, but tested according to different standards. Thus,
to flow through any signal ground, even if the chips are a given commercial-grade chip might actually pass mil-
protected by transient suppressors. A 35 kV ESD spark itary temperature requirements, but not have been test-
can always spare a few hundred volts to drive a fast ed,fcr it. (Of course, there are other differences in 'grud-
current pulse down a signal ground line if it can't find a ing requirements having to do with packaging, bum-in,
braided cable to follow. Think how delighted your 8048 traceability, etc.)
will be to find its VSS pin 250V higher than VCC for a
few lOs of nanoseconds. In any case, it's apparent that commercial-grade chips
can't. be used safely in automotive applications, not
THE AUTOMOTIVE ENVIRONMENT even in the passenger compartment. Industrial-grade
chips can be used in the passenger compartment, and
The automobile presents an extremely hostile environ- automotive or military chips are required in under-the~
ment for electronic systems. There are several parts to hood applications.
it:
1. Temperature extremes from -4Q°C to + 125°C (un- Ignition noise, CB radios, and that sort of thing are
der the hood) or + 85°C (in the passenger compart- probably the least of your worries. In a poorly designed
ment) system, or in .one that has not been adequately tested
for the automotive environment, ,this type of EMI
2. Electromagnetic pulses from the ignition system might cause a few software upsets, but not destroy
3. Supply line transients that will knock your socks off chips.
One needs to take a long, careful look at the tempera- The major problem, and the one that seems to come as
ture extremes. The allowable storage temperature range the biggest surprise to most people, is the line tran-
for most Intel MOS chips is -65°t to + 1500C, al" sients. Regrettably, the 12V battery is not. actually the
though some chips have a maximum storage tempera- source of power when the car is running. The charging
ture rating of + 125°C. In operation (or "under bias," system is, and it's not very clean. The only time the
as the data sheets say) the allowable ambient tempera- battery is the real source of power is when the car is
ture range, depends on the product grade, as follows: first being started, and in that condition the battery
terminals may be delivering about5V or 6V. As follows
is a brief description of the major idiosyncracies of the
"12V" automotive power line.
10·274
inter AP-125
60
50
ENGINE SPEED 3000 RPM
iii' ALTERNATOR LOAD 55 AMPERES
!:i 40
0
~
w 30
Q
:;)
5
Do 20
::E
'" 10
a
a ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
TIME (MILLISECONDS)
210313-36
Figure 24. Typical Load Dump Transients
• An abrupt reduction in the alternator load causes a • Mutual coupling between unshielded wires in long
positive voltage transient called "load dump." In a harnesses can induce 100V and 200V transients in
load dump transient the line voltage rises to 20V or unprotected circuits.
30V in a few /ks, then decays exponentially with a
time constant of about 100 J.Ls, as shown in Figure What all this adds up to is that people in the business of
24. Much higher peak voltages and longer decay building systems for automotive applications need a
times have also been reported. The worst case load comprehensive testing program. An SAE guideline
dump is caused by disconnecting a low battery from which describes the automotive environment is avail-
the alternator circuit while the alternator is running. able to designers: SAE Jl21l, "Recommended Envi-
NormallY.this would happen intermittently when ronmental Practices for Electronic Equipment Design,"
the battery terminal connections are defective. 1980 SAE Handbook, Part I, pp. 22.80-22.96.
• When the ignition is turned off, as the field excita-
tion decays, the line voltage' can go to between Some suggestions for protecting circuitry are shown in
-40V and -IOOV for 100 J.Ls or more. Figure 26. A transient suppressor is placed in front of
the regulator chip to protect it. Since the rise times in
• Miscellaneous solenoid switching transients, such as these transients are not like those in ESD pulses, lead
the one shown in Figure 25, can drive the line to + inductance is less critical and conventional devices can
or - 200V to 400V for several J.Ls. be used. The regulator itself is pretty much of a necessi-
ty, since a load dump transient is simply not going to be
removed by any conventional LC or RC filter.
OSEe.
t
OVOLTS -
-100 VOLTS/DIV
10ps/DIV --
210313-37
Figure 25. Transient Created by De-energizing an Air Conditioning Clutch Solenoid
10-275
inter AP·125
AUTOMOTIVE ON BOARD COMPUTER
.-.. . -"""'1----- +5V
ACCESSORY
+12V
o-J'l1J'......-r-t--'VI."'''..---I
.....---...- TO" PROCESSOR
~ 115V
DISTANCE
MEASURING COIL
,-0---------""',...._,.",-_ TO" pROCESSOR
5V
210313-38
Figure 26. Use of Transient Suppressors in Automotive Applications
Spe2ial I/O interfacing is aJso required, because of the The EMC Education committee has available a video
need for high tolerance to cvoltage transients, input tape: "Introduction to EMC-A Video Training
noise, input/output isolation, etc. In addition, switches Tape," by Henry Ott. Don White Consultants offers a
cthat are being monitored or driven by these buffers are series of training courses on many different aspects of
usually referenced to chassis ground instead of signal electromagnetic compatibility. Most organizations that
ground) and in a. ca.r there ca..'1 be ma.."lY volts difference sponsor El".fC courses also (jff~r in-plant presentatiuns.
between the two. I/O interfacing is discussed in Refer-
ence 2.
Parting Thoughts
The main sources of information cfor this Application
Note were the references by Ott and by White. Refer-
ence 5 is probably the finest treatment currently avail-
able on the subject. The other references provided spe-
cific information as cited in the text.
Courses and seminars on the subject of electromagnetic
interference are given regularly throughout the year.
Information on these can be obtained from:
IEEE Electromagnetic Compatibility Society
EMC Education Committee
345 East 47th Street
New York, NY 10017
Don White Consultants, Inc.
International Training Centre
P.O. BoxD
Gainesville, VA 22065
Phone: (703) 347-0030
10-276
inter Ap·125
REFERENCES 7. SAE J1211, "Recommended Environmental Prac-
tices for Electronic Equipment Design," 1980 SAE
1. Clark, O.M., "Electrostatic Discharge Protection Handbook, Part 1, pp. 22.80-22.96.
Using Silicon Transient Suppressors," Proceedings of
the Electrical Overstress/Electrostatic Discharge Sympo- 8. Smith, L., "A Watchdog Circuit for Microcomput-
sium. Reliability Analysis Center, Rome Air Develop- er Based Systems," Digital Design, pp. 78, 79, Nov.
ment Center, 1979. 1979.
2. Kearney, M; Shreve, J.; and Vincent, W., "Micro- 9. TranZorb Quick Reference Guide. General Semi-
processor Based Systems in the Automobile: Custom conductor Industries, P.O. Box 3078, Tempe, AZ
Integrated Circuits Provide an Effective Interface," 85281.
Electronic Engine Management and Driveline Control
Systems, SAE Publication SP-481, 810160, pp. 93-102. 10. Tucker, T.I., "Spark Initiation Requirements of a
Secondary Explosive," Annals of the New York Acade-
3. King, W.M. and Reynolds, D., "Personnel Electro- my of Sciences, Vol 152, Article I, pp. 643-653, 1968.
static Discharge: Impulse Waveforms Resulting From
ESD of Humans Directly and Through Small Hand- 11. White, D., Electromagnetic Interference and Com-
Held Metallic Objects Intervening in the Discharge patibility, Vol. 3: EMI Control Methods and Techniques.
Path," Proceedings of the IEEE Symposium on Electro- Don White Consultants, 1973.
magnetic Compatibility, pp. 577-590, Aug. 1981. .
12. White, D., EMI Control in the Design of Printed
4. Ott, H., "Digital Circuit Grounding and Intercon- Circuit Boards and Backplanes. Don White Consul-
nection," Proceedings of the IEEE Symposium on Elec-· tants, 1981.
tromagnetic Compatibility, pp. 292-297, Aug. 1981.
13. Yarkoni, B. and Wharton, J., "Designing Reliable
5. Ott, H., Noise Reduction Techniques in Electronic Software for Automotive Applications," SAE Transac-
Systems. New York: Wiley, 1976. tions, 790237, July 1979.
6. 1981 Interference Technology Engineers' Master
(ITEM) Directory and Design Guide. R. and B. Enter-
prises, P.O. Box 328, Plymouth Meeting, PA 19426.
10-277
intJ APpLICATION
NOTE
AP-155
December 1986
Oscillators
for Microcontrollers
TOM WILLIAMSON
MICROCONTROLLER
TECHNICAL MARKETING
Order Number: 230659-001
10-278
AP-155
INTRODUCTION This Application Note is intended to provide such as-
sistance in the design of oscillator circuits for micro-
Intel's microcontroller families (MCS®-48, MCS®-51, controller systems. Its purpose is to describe in a practi-
and iACX-96) contain a circuit that is commonly re- cal manner how oscillators work, how crystals and ce-
ferred to as the "on-chip oscillator". The on-chip cir- ramic resonators work, (and thus how to spec them),
cuitry is not itself an oscillator, of course, but an ampli- and what the on-chip amplifier looks like electronically
fier that is suitable for use as the amplifier part of a and what its operating characteristics are. A BASIC
feedback oscillator. The data sheets and Microcontoller program is provided in Appendix II to assist the de-
Handbook show how the on-chip amplifier and several signer in determining the effects of changing individual
off-chip components can be used to design a working parameters. Suggestions are provided for establishing a
oscillator. With proper selection of off-chip compo- pre-production test program.
nents, these oscillator circuits will perform better than
almost any other type of clock oscillator, and by almost
any criterion of excellence. The suggested circuits are FEEDBACK OSCILLATORS
simple, economical, stable, and reliable.
We offer assistance to our customers in selecting suit- Loop Gain
able off-chip components to work with the on-chip os-
cillator circuitry. It should be noted, however, that In- Figure I shows an amplifier whose output line goes into
tel cannot assume the, resp.onsibility of writing specifi- some passive network. If the input signal to the amplifi-
cations for the off-chip components of the complete os- er is VI, then the output signal from the amplifer is v2
cillator circuit, nor of guaranteeing the performance of = AVI and the output signal from the passive network
the finished design in production, anymore than a tran- is v3 = {3v2 = {3Avl. Thus {3A is the overall gain
sistor manufacturer, whose data sheets show a number from terminal 1 to terminal 3.
of suggested amplifier circuits, can assume responsibili-
ty for the operation, in production, of any of them.
We are often asked why we don't publish a list of re-
quired crystal or ceramic resonator specifications, and
recommend values for the other off-chip components.
This has been done in the past, but sometimes with
consequences that were not intended. '230659-1
Suppose we suggest a maximum crystal resistance of 30 Figure 1. Factors in Loop Gain
ohms for some given frequency. Then your crystal sup-
plier tells you the 30-ohm crystals are going to cost Now connect terminal 1 to terminal 3, so that the sig-
twice as much as 50-ohm crystals. Fearing that Intel nalpath forms a loop: 1 to 2 to 3, which is also 1. Now
will not "guarantee operation" with 50-ohm crsytals, we have a feedback loop, and the gain factor {3A is
you order the expensive ones. In fact, Intel guarantees called the loop gain.
only what is embodied within an Intel product. Besides,
there is no reaSon why 50-ohm crystals couldn't be Gain factors are complex numbers., That means they
used, if the other off-chip components are suitably ad- have a magnitude and a phase angle, both of which
justed. ' vary with frequency. When writing a complex number,
one must specify both quantities, magnitude and angle.
Should we recommend values for the other off-chip A number whose magnitude is 3, and whose angle is 45
components? Should we do it for 50-ohm crystals or 30- . degrees is commonly written this way: 3L45·. The num-
ohm crystals? With respect to what should we optimize ber 1 is, in complex number notation, !LO·, while -1 is
their selection?' Should we minimize start-up time or !LI80·.
maximize frequency stability? In many applications,
neither start-up time nor frequency stability are partic- By closing the feedback loop in Figure 1, we force the
ularly critical, and our "recommendations" are only're- equality
stricting your system to unnecessary tolerances. It all
depends on the application.
Although we will neither "specify" nor "recommend" This equation has two solutions:
specific off-chip components, we do offer assistance in
these tasks. Intel application engineers are available to 1) "1 = 0;
provide whatever technical assistance may be needed or
desired by our customers in designing with Intel prod- 2) fjA = UO·.
ucts.
10-279
inter AP-155
In a given circuit, either or both of the solutions may be In order for the loop gain to have zero phase angle it is
in effect. In the first solution the circuit is quiescent (no necessary that the feedback element Zr have a positive
output signal). If you're trying to make an oscillator, a reactance. That is, it must be inductive. Then, the fre-
no-signal condition is unacceptable. There are ways to quency at which the phase angle is zero is approximate-
guarantee t,hat the second solution is the one that will ly the frequency at which
be in effect, and that the quiescent condition will be
excluded.
How Feedback Oscillators Work where Xr is the reactance of Zr (the total Zr being Rr +
jXr, and C is the series combination of Cx! and CX2.
A feedback oscillator amplifies its own noise and feeds
it back to itself in exactly the right phase, at the oscilla- c= CXl CX2
tion frequency, to build up and reinforce the desired , CXl + CX2
oscillations. Its ability to do that depends on its loop
gain. First, oscillations can occur only at the frequency In other words, Zr and C form·a parallel resonant cir-
for which the loop gain has a phase angle of 0 degrees. cuit.
Second build-up of oscillations will occur only if the
loop gain exceeds I at the frequency. Build-up contin- If Zr is an inductor, then Xr = wL; and the frequency
ues until nonlinearities in the circuit reduce the average at which the loop gain has zero phase is the frequency
value of the loop gain to exactly 1. at which
Start-up characteristics depend on the small-signal 1
properties of the circuit, specifically, the small-signal wL=-
wC
loop gain. Steady-state characteristics of the oscillator
depend on the large-signal properties of the circuit, or
such as' the transfer curve (output voltage vs. input
voltage) of the amplifier, and the clamping effect of the 1
input protection devices. These things will be discussed w = .J[C
mere fully further on. First \ve \"/i11 leek nt the basic
operation of the particular oscillator circuit, called the Noi'm3.lly, Zr is neit an inductor, but it must still have a
"positive reactance" oscillator. positive reactance in order for the circuit to oscillate.
There are some piezoelectric devices on the market that
show a positive reactance, and provide a more stable
The Positive Reactance Oscillator oscillation frequency than an inductor will. Quartz
crystals can be, used where the oscillation frequency is
Figure 2 shows the configuration of the positive reac-
critical, and lower cost ceramic res_onators can be used
tance oscillator. The inverting amplifier, working into
w4ere the frequency is less critical.
the impedance of the feedback network,' produces' an
output signal that is nominally 180 degrees out of phase When the feedback element is a piezoelectric device,
with its input. The feedback network must provide an
this circuit configuration is called a Pierce oscillator.
additional 180 degrees phase shift, such that the overall
The advantage of piezoelectric resonators lies in their
loop gain has zero (or 360) degrees phase shift at the
property of providing a wide range of positive teactimce
oscillation frequency.
values over a very narrow range Qf frequencies. The
reactance will equal 1/wC at some frequency within
this range, so the oscillation frequency will be within
the same range. Typically, the width of this range is
I 230659-2
Figure 2~ Positive Reactance Oscillator
10-280
AP-155
only 0.3% of the nominal frequency of a quartz crystal, To assure that an oscillator starts in the desired mode
and about 3% of the nominal frequency of. a ceramic on power-up, something must be done to suppress the
resonator. With relatively little design effort, frequency loop gain in the undesired frequency ranges. The crys-
accuracies of 0.03% or better -can be obtained with tal itself provides some protection against unwanted
quartz crystals, and 0.3% or better with ceramic reso- modes of oscillation; too much resistance in that mode,
nators. for example. Additionally, junction capacitances in the
amplifying devices tend to reduce the gain at higher
frequencies, and thus may discriminate against unwant-
QUARTZ CRYSTALS ed modes. In some cases a circuit fix is necessary, such
as inserting a trap, a phase shifter, or ferrite beads to
The crystal resonator is a thin slice of quartz sand- kill oscillations in unwanted modes.
wiched between two electrodes. Electrically, the device
looks pretty -much like a 5 or 6 pF capacitor, except
that over certain ranges of frequencies the crystal has a Crystal Parameters
positive (i.e., inductive) reactance.
The ranges of positive reactance originat~ in the piezo- Equivalent Circuit
electric property of quartz: Squeezing the crystal gener-
Figure 4 shows an equivalent circuit that is used to
ates an internal E-field. The effect is reversible: Apply-
represent the crystal for circuit analysis.
ing an AC E-field causes the crystal to vibrate. At cer-
tain vibrational frequencies there is a mechanical reso-
The Rl-Ll-Cl branch is called the motivational arm of
nance. As the E-field frequency approaches a frequency the crystal. The values of these parameters derive from
of mechanical resonance, the measured reactance of the
the mechanical properties of the crystal and are con-
crystal becomes positive, as shown in Figure 3.
stant for a given mode of vibration. Typical values for
various nominal frequencies are shown in Table 1.
SPURIOUS
-
JX RESPONSES
FREQUENCY
/ \ ---11'01-1- -
SYMBOL
-JX
Xeo
FUNDAMENTAL
/
FIFTH MECHANICAL
OVERTONE
THIRD MECHANICAL
-C:t:*J-
EQUIVALENT CIRCUIT
230659-4
OVERTONE
230659-3
Figure 4. Quartz Crystal: Symbol and
Equivalent Circuit
Figure 3. Crystal Reactance vs. Frequency
Co is called the shunt capacitance of the crystal. This is
Typically there are several ranges of frequencies where- the capacitance of the crystal's electrodes and the me-
in the reactance of the crystal is positive. Each range chanical holder. If one were to measure the reactance of
corresponds to a different mode of vibration in the crys- the crystal at a: freuqency far removed from a resonance
tal. The main resonsances are the so-called fundamen- frequency, it is the reactance of this capacitance that
tal resp9nse and the third and fifth overtone responses. would be measured. It's normally 3 to 7 pF.
Table 1. Typical Crystal Parameters
The overtone responses shouldn't be confused with the
harmonics of the fundamental. They're not harmonics, Frequency R1 L1 C1 Co
but different vibrational modes. They're not in general MHz ohms mH pF pF
at exact integer multiples of the fundamental frequency.
2 100 520 0.012 4
There will also be "spurious" responses, occurring typi-
cally a few hundred KHz above each main response. 4.608 36 117 0.010 2.9
11.25 19 8.38 0.024 5.4
10-281
AP-155
The series resonant frequency of the crystal is the fre- the antiresonant frequency of the parallel combination
quency at which LI and CI are in resonance. This fre~ of the crystal and CL. This frequency is given by
quency is given by .
1
fs=---
21T~L1C1
These frequency formulas are derived (in Appendix A)
At this frequency the impedance of the crystal is R I in from the equivalent circuit of the crystal, using the as-
parallel with the reactance of Co. For most purposes, sumptions that the Q of the crystal is extremely high,
this impedance is taken. to be just R J, since the reac- and that the circuit external to the crystal has no effect
tance of Co is so much larger than RI. on the frequency other than to·.provide the load capaci-
tance CL. The latter assumption is not precisely true,
but it is close enough for present ·purposes.
Load Capacitance
A crystal oscillator circuit such as the one shown in "Series" vs. "Parallel" Crystals
Figure 2 (redrawn in Figure 5) operates at the frequen-
cy for which the crystal is IlIltiresonant (ie, paral1el~res There is no such thing as a "series cut" crystal as op-
onant) ,with the total capacitance across the crystal ter- posed to. a "parallel cut" crystal. There are different
minals external to the crystal. This total capacitance cuts of crystal, having to do with the parameters of its
external to the crystal is called the load capacitance. . motional arm .jn various frequency ranges,. but there is
no special cut for series or parallel operation.
As shown in Figure 5, the load capacitance is given by
An oscillator is series resonant if the oscillation fre-
CX1 CX2 .. quency is fs of the crystal. To operate the crystal at fs,
CL = C C
X1 + X2
+ Cstray the amplifier has to be noninverting. When buying a
crystal for such an oscillator, one does not specify a
The crystal manufacturer needs to know the value of load c.apacitance. Rather, one specifies the loading con-
CL in order to adjust the crystal to the specified fre- dition as "series." '
.quency.
If a "series" crystal is put into an oscillator that has an
.inverting amplifier, it will oscillate in parallel resonance
with the load capacitance presented to the crystal by
the oscillator circuit, at a frequency slightly above fs. In
fact, at approximately .
r--------c-----------l et C~ C.0»)
!
I
-----------~~,---------
e" ex.
~
I
fa = fs ( 1+ 2(C
L
II I 1:
. .,...
) iI This frequency would typically be about 0.02% above
f s·
~--------------------~
. CRYSTAL
r---------~~---------~
Equivalent Series Resistance
II R, L, C, I
I The "series resistance" often listed on quartz' crystal
I I data sheets is the real part of the crystal impedance at
~--------------~-~--~ the crystal's calibration frequency. This will be Rl if
230659-6
the calibration frequency 18 the series resonant frequen-
Figure 5. Load CapaCitance cy of the crystal. If the crystal is calibrated for parallel
resonance with a load capacitance CL, the equivalent
The adjustment involves putting the cryst~l.in .series series resistance will be
\ .
with the specified CL, and then "trimming" the crystal
to obtain resonance of the series combination of the ESR = R1 ( 1 + ~~r
crystal and CL at the specified frequency. Because of
the high Q of the crystal, the resonant frequency of the
series combination of the crystal and CL is the same as The crystal manufacturer measures this resistance at
the calibration frequency during the same operation in
which the crystal is adjusted to the calibration frequen-
cy.
10-282
inter AP·155
Frequency Tolerance In a positive reactance oscillator, if one assumes the
peak voltage across the crystal to be something in the
Frequency tolerance as discussed here is not a require- neighborhood of Vee, the power dissipation can be ap-
ment on the crystal, but on the complete oscillator. proximated as
There are two types of frequency tolerances on oscilla-
tors: frequency acccuracy and frequency stability. Fre-
quency accuracy refers to the oscillator's ability to run
at an exact specified frequency. Frequency stability re- This formula is derived in Appendix A. In a 5V system,
fers to the constancy of the oscillation frequency. P rarely evaluates to more than a milliwatt. Crystals
with a standard 1 or 2 mW drive level rating can be
Frequency accuracy requires mainly that the oscillator used in most digital systems.
circuit present to the crystal the same load capacitance
that it was adjusted for. Frequency stability requires
mainly that the load capacitance be constant. MT - 51 R3.58M
In most digital applications the accuracy and stability 100000
requirements on the oscillator are so wide that it makes
very little difference what load capacitance the crystal
was adjusted to, or what load capacitance the circuit
actually presents to the crystal. For example, if a crys-
tal was calibrated to a load capacitance of 25 pF, and is
used in a circuit whose actual load capacitance is 50 pF,
the frequency error on that account would be less than
10
0.01%.
1
':-O-'--2000-'-~4000~"""6000-'--'-""6000"""'~'-.,..JOOOO
In a positive reactance oscillator, the crystal only needs
to be in the intended response mode for the oscillator to FREQUENCY (KHz)
satisfy a 0.5% or better frequency tolerance. That's be- 230659-7
cause for any load capacitance the oscillation frequency
is certain to be between the crystal's resonant and anti- Figure 6. Ceramic Resonator Impedance vs.
resonant frequencies. Frequency (Test Data Supplied by NTK
Technical Ceramics)
Phase shifts that take place within the amplifier part of
the oscillator will also affect frequency accuracy and
stability. These phase shifts can normally be modeled as CERAMIC RESONATORS
an "output capacitance" that, in the positive reactance
oscillator, parallels CX2. The predictability and con- Ceramic resonators operate on the same basic princi-
stancy of this output capacitance over temperature and ples as a quartz crsytal. Like quartz crsytals, they are
device sample will be the limiting factor in determining piezoelectric, have a reactance versus frequency curve
the tolerances that the circuit is capable of holding. similar to a crystal's, and an equivalent circuit that
looks just like a crystal's (with different parameter val-
ues, however).
Drive Level
The frequency tolerance of a ceramic resonator is about
Drive level refers to the power dissipation in the crys- two orders of magnitude wider than a crystal's, but the
tal. There are two reasons for specifying it. One is that ceramic is somewhat cheaper than a crystal. It may be
the parameters in the equivalent circuit are somewhat noted for comparison that quartz crystals with relaxed
dependent on the drive level at which the crystal is tolerances cost about twice as much as ceramic resona-
calibrated. The other is that if the application circuit tors. For purposes of clocking a microcontroller, the
exceeds the test drive level by too much, the crystal frequency tolerance is often relatively noncritical, and
may be damaged. Note that the terms "test drive level" the economic consideration becomes the dominant fac-
and "rated drive level" both refer to the drive level at tor.
which the crystal is calibrated. Normally, in a micro-
controller system, neither the frequency tolerances nor Figure 6 shows a graph of impedance magnitude versus
the power levels justify much concern for this specifica- frequency for a 3.58 MHz ceramic resonator. (Note
tion. Some crystal manufacturers don't even require it that Figure 6 is a graph of Izrl versus frequency, where
for microprocessor crystals.
10-283
inter AP-155
as Figure 3 is a'graph ofXrversus frequency.) Anum- frequency and the chip you want it to work with ..
ber of spurious responses are apparent in Figure 6. The They'll supply the resonators, a circuit diagram show-
manufacturers state that spurious responses are more ing the positions and -values of 'other external compo-
prevalent in the lower frequency resonators (kHz nents that may be required and a: guarantee that the
range) than in the higher frequency units (MHz range). circuit will work properly at the ,specified frequency.
For our purposes only the MHz range ceramics need to
be considered.
OSCILLATOR DESIGN
CONSIDERATIONS
----iIOI-I- - -
SYMBOL Designers of microcontroller systems have a number of
options to choose from for clocking the system. The
main decision is whether to use the "on-chip" oscillator
or an external oscillator. If the choice is to use the on-
chip oscillator, what kinds of external components are
EQUIVALENT CIRCUIT
needed to make it operate as advertised? If the choice is
230659-8 to use an external oscillator, what type of oscillator
should it be?
Figure 7. Ceramic Resonator: Symbol and
Equivalent Circuit The decisions have to be based on both economic and
technical requirements. In this section we'll discuss
Figure 7 shows the symbol and equivalent circuit for
r.l1..' \i
some of the factors that should be considered.
the ceramic resonator, both of which are the same as
for the crystal. The parameters have different values,
however, as listed in Table 2.
TALl
Table 2. Typical Ceramic Parameters ------1
Frequency R1 L1 C1 Co , '0 .
MHz ohms mH pF pF c __ T . .
3.56 7. 0.; ;3 ,19.6 140 .,!,.L..:.- I XTAL2I' ,
,I----.,.-.J
6.0 8 0.094 8.3 60
8.0 7 0.092 4.6 40 230659-9
11.0 10 0.057 3.9 30 Figure 8. Using the "On-Chip" Oscillator
Note that the motional arm of the ceramic resonator
tends to have less resistance than the quartz crystal and On-Chip Oscillators
also a vastly reduced L,/C, ratio. This results. in the
motional arm having a Q (given by (l/R,) ~L,/C,) that IiI most cases, the on-chip amplifier with the appropri-
is typically two orders of magnitude lower than that of ate external components provides the most economical
a quartz crystal. The lower Q makes for a faster startup solution to the clocking problem. Exceptions may arise
of the oscilaltor and for a less closely controlled fre- in severe environments when frequency tolerances are
quency (meaning that circuitry external to the resona- tighter than about 0.01 %.
tor will have more influence on the frequency than with
a quartz crystal). The external components that ,need to be added are a
positive reactance (normally a crystal or ceramic reso-
Another major difference is that the shunt capacitance nator) and the two capacitors Cx, and CX2, as shown
of the ceramic resonator.is an order of magnitude high- in Figure 8.
er than Co of the quartz crystal and more dependent on
the frequency of the resonator. . ' -
Crystal Specifications
The implications of these differences are not all obvi-
ous, but some will be indicated in the section on Oscil- Specificati()ns for an appropriate crystal are not ver'l
lator Calculations. critical, unless the frequency is. Any fundamental-mode
crystal of med.ium or better quality can be used.
Specifications for Ceramic Resonators
Ceramic resonators are easier to specify than quartz
crystals. All the vendor wants to know is the desired
10-284
AP-155
We are often asked what maximum crystal resistance tor is being used, and also on application-specific re-
should be specified. The best answer to this question is quirements on start-up time and frequency tolerance.
the lower the better, but use what's available. The crys-
tal resistance will have some effect on start-up time and Start-up time is sometimes more critical in microcon-
steady-state amplitude, but not so much that it can't be troller systems than frequency stability, because ofvari-
comperisated for by appropriate selection of the capaci- ous reset and initialization requirements.
tances CX! and CX2.
Less commonly, accuracy of the oscillator frequency is
Similar questions are asked about specifications of load also critical, for example, when the oscillator is being
capacitance and shunt capacitance. The best advice we used as a time base. As a general rule, fast start-up and
can give is to understand what these parameters mean stable frequency tend to pull the oscillator design in
and how they affect the operation of the circuit (that opposite directions.
being the purpose of this Application Note), and then
decide for yourself if such specifications are meaningful Considerations of both start-up time and frequency sta-
in your application or not. Normally, they're not, un- bility over temperature suggest that CX! and CX2
less your frequency tolerances are tighter than about should be about equal and at least 20 pF. (But they
0.1%. don't have to be either.) Increasing the value of these
capacitances above some 40 or SO pF improves frequen-
Part of the problem is that crystal manufacturers are cy stability. It also tends to increase the start-up time.
accustomed to talking "ppm" tolerances with radio en- There is a maximum value (several hundred pF, de-
gineers and simply won't take your order until you've pending on the value of R! of the quartz or ceramic
filled out their list of specifications. It will help if you resonator) above which the oscillator won't start up at
define your actual frequency tolerance requirements, all.
both for yourself and to the .crystal manufacturer.
Don't pay for 0.003% crystals if your actual frequency If the on-chip amplifier is a simple inverter, such as in
tolerance is 1%. . the 80SI, the user can select values for CX!and CX2
between some 20 and 100 pF, depending on whether
start-up time or frequency stability is the more critical
Oscillation Frequency parameter in a specific application. If the on-chip am-
plifier is a Schmitt Trigger, such as in the 8048, smaller
The oscillation frequency is determined 99.S% by the values of CX! must be used (S to 30 pF), in order to
crystal and up to about O.S% by the circuit external to prevent the oscillator from running in a relaxation
the crystal. The on-chip amplifier has little effect on the mode.
frequency, which is as it should be, since. the amplifier
parameters are temperature and process dependent. Later sections in this Application Note will discuss the
effects of varying CX! and CX2 (as well as other param-
The influence of the on-chip amplifier on the frequency eters), and will have more to say on their selection.
is by means of its input and output (pin-to-ground) ca-
pacitances, which parallel CX! and CX2, and the
XTALI-to-XTAL2 (pin-to-pin) capacitance, which Placement of Components
parallels the crystal. The input and pin-to-pin capaci-
tances are about 7 pF each. Internal phase deviations Noise glitches arriving at XTALI or XTAL2 pins at
from the nominal 180· can be modeled as an output the wrong time can cause a miscount in the internal
capacitance of 2S to 30 pF. These deviations from the clock-generating circuitry. These kinds of glitches can
ideal have less effect in the positive reactance oscillator be produced through capacitive coupling between the
(with the inverting amplifer) than in a comparable se- oscillator components and PCB traces carrying digital
ries resonant oscillator (with the noninverting amplifi- signals with fast rise and fall times. For this reason, the
er) for two reasons: first, the effect of the output capaci- oscillator components should be mounted close to the
tance is lessened, if not swamped, by the off-chip capac- chip and have short, direct traces to the XTALI,
itor; secondly, the positive' reactance oscillator is less XTAL2, and VSS pins.
sensitive, frequency-wise, to such phase errors.
Clocking Other Chips
Selection of CX1 and CX2 There are times when it would be desirable to use the
on-chip oscillator to clock other chips in the system.
Optimal values for the capacitors CX! and CX2 depend
on whether a quartz crystal or ceramic resona-
10-285
inter AP-155
This can be done if an appropriate buffer is used. A
VCC TTL buffer puts too much load on the on-chip amplifi-
er for reliable start-up. A CMOS buffer (such as the
CLOCK 74HC04) can be used, if it's fast enough and if its VIH
OUT and VIL specs are compatible with the available signal
::t-_-'W~-_...j XTAL2 amplitudes. Circuits such as shown in Figure 9 might
also be considered for these types of applications.
C..
Clock-related signals are available at the TO pin in the
t---iI--4-...jXTALl MCS-48 products, at ALE in the MCS-48 and MCS-51
lines, and the iACX-96 controllers provide a CLKOUT
230659-10
signal. .
A) DRIVING FROM XTAL2
VCC External OSCillators
CLOCK
OUT
lK
n~
-::
C
12 0
XTAL2
When technical requirements dictate the use of an ex-
ternal oscillator, the external drive requirements for the
XTALI microcontroller, as published in the data sheet, must be
C.. carefully noted. The logic levels are not in general TTL-
compatible. And each controller has its idiosyncracies
in this regard. The 8048, for example, re.quires that
both XTAL1 and XTAL2 be driven. The 8051 can be
230659-11 driven that way, but the data sheet suggest the simpler
B) DRIVING FROM XTAL 1
method of grounding XTAL1 and driving XTAL2. For
Figure 9. Using the On-Chip Oscillator this method, the driving source must be capable of sink-
to Drive Other Chips
ing some current when XTAL2 is being driven low.
For the external oscillator itself, there are basically two
choices: ready-made and home-grown.
10-286
inter AP-155
TTL Crystal Clock Oscillator Frequency Tolerance: ± 0.1 % Overall O·C-70·C
The HS-l00, HS-200, & HS-500 all-metal package se-
ries of oscillators are TTL compatible & fit a DIP Hermetically Sealed Package
layout. Standard electrical specifications are shown Mass spectrometer leak rate max.
below. Variations are available for special applica- 1 X 10- 8 atmos. cc/sec: of helium
tions.
Frequency Range: HS-100-3.5 MHz to 30 MHz Output Waveform
HS-200-225 KHz to 3.S MHz -[TAt- -1TF-
HS-S00-25 MHz to 60 MHz
- -~
=~ ----
[E-
- - - - ---2.4 VDe
- - - ----14 VDe
___ _ ___ 0.4 VDe
--VOL
.0 VDe
60% Max
230659-12
INPUT
HS-100 HS-200 HS-500
3.5 MHz-20 MHz 20 + MHz-30 MHz 225 KHz-4.0 MHz 25 MHz-SO MHz
Supply Voltage
(Vcd 5V ±10% 5V ±10% 5V ±10% 5V ±10%
Supply Current
(Icd max. 30mA 40mA 85mA 50mA
OUTPUT
HS-100 HS-200 HS-500
3.5 MHz-20 MHz 20 + MHz-30 MHz 225 KHz-4.0 MHz 25 MHz-SO MHz
VOH (Logic "1 ") +2.4Vmin. 1 +2.7Vmin.2 +2.4V min.l +2.7V min. 2
VOL (Logic "0") +O.4V max. 3 +0.5V max. 4 +0.4Vmax. 3 +0.5V max. 4
Symmetry S0/40%5 S0/40%5 55/45%5 60/40%5
TR, TF (Rise &
Fall Time) < 10 ns 6 < 5 ns6 < 15 ns 6 < 5 ns 6
Output Short
Circuit Current 18 mA min. 40 mAmin. 18mAmin. 40mAmin.
Output Load 1 to 10 TTL Loads 7 1 t9 10 TTL Loads8 1 to 10 TTL Loads 7 1 to 10 TTL Loads 8
CONDITIONS
110 source = - 400 p.A max. 410 sink = 20.00 mA max. 71.6 mA per load
210 source = -1;0 mA max. 5Vo = 1.4V 82.0 mA per load
310 sink = 1S.0 mA max. 6(0.4V to 2.4V)
Figure 10.l;Ire-Packaged Oscillator Data·
"Reprinted with the permission of @Midland·Ross Corporation 1982.
10-287
inter Ap·155
Prepackaged oscillators are available from most crystal The feedback resistance has to be quite low, however,
manufacturers, and have the advantage that the system since it must conduct current sourced by the input pin
designer can treat the oscillator as a black box whose without allowing the DC input voltage to get too far
performance is guaranteed by, people who carry many above the DC output voltage. For biasing purposes, the
years of experience in designing and' building oscilla- feedback resistance should not exceed a- few k-ohms.
tors. Figure 10 shows a typical' data sheet for some But shunting the crystal with such a low resistance does
prepackaged oscillators. Oscillators are also available not encourage, start-up:
with complementary outputs.
If the oscillator is to drive the microcontroller directly, lK lK
one will want to make a careful comparison between
the external drive requirements in the microcontroller
data sheet and the oscillator's output logic levels and
1. 01 ",
74LS04
test conditions.
OUTPUT
If oscillator stability is less critical than cost, the user
may prefer to go with an in-house design. Not without Rx
(SEVERAL kO)
some precautions, however.
It's easy to design oscillators that work. Almost all of ex. en
them do work, even if the designer isn't too clear on 230659-13
why. The key point here is that almost all of them A) TTL OSCILLATOR
work. The problems begin when the system goes into
production, and marginal units commence malfunc- lMU
tioning in the field. Most digital designers, after all, are 74e04
not very adept at designing oscillators lor production.
OUTPUT
Oscillator design is somewhat of a black art, with the
quality of the finished product being very dependent on
the designer's experience and intuition. For that reason
the most important consideration in any design is to
have an adequate preproduction test program. Prepro-
duction tests are discussed later in this Application 230659-14
Note. Here we will discuss some of the design options B) CMOS OSCILLATOR
and take a look at some commonly used configurations.
Figure 11. Commonly Used Gate Oscillators
Consequently, the configuration in Figure llA might
Gate Oscillators versus Discrete be suggested. By breaking Rr into two parts and AC-
Devices grounding the midpoint, one achieves the DC feedback
required to hold the inverter in its active region, but
Digital systems designers are understandably reluctant
to get involved with discrete devices and their peculiari- without the negative signal feedback that is in effect
telling the circuit not to oscillate. However, this biasing
ties (biasing techniques, etc.). Besides, the component
count for these circuits tends to be quite a bit higher scheme will increase the start-up time, and relaxation-
type oscillations are also possible.
than what a digital designer is used to seeing for that
amount of functionality. Nevertheless, if there are un-
usual requirements on the accuracy and stability of the, A CMOS inverter, such as the 74HC04, might work
clock frequency, it should be noted that discrete device better in this application; since a larger Rr can be used
to hold the inverter in its linear region.
oscillators can be tailored to suit the exact needs of the
application and perfected to a level that would be diffi-
, Logic gates tend to have a fairly low output resistance,
cult for a gate oscillator to approach.
which destabilizes the oscillator. For that reason a re-
In most cases, when an external oscillator is needed, the sistor Rx is often added to the feedback network, as
shown in Figures IIA and B. At higher frequencies a
designer tends to rely on some form of a gate oscillator.
20 or 30 pF capacitor is sometimes used in the Rx posi-
A TTL inverter with a resistor connecting the output to
the input makes a suitable inverting amplifier. The re- tion, to compensate for some of the internal propaga-
sistor holds the inverter in the transition region be- tion delay.
tween logical high and low, so that at least for start-up
purposes the inverter is a linear amplifier. Reference I contains an excellent discussion of gate os-
cillators, and a number of design examples.
10-288
AP-155
Fundamental versus Overtone Operation
It's easier to design an oscillator circuit to operate in
the resonator's fundamental response mode than to de-
sign one for overtone operation. A quartz crystal whose
fundamental response mode covers the desired frequen-
cy can be obtained up to some 30 MHz. For frequencies
above that, the crystal might be used in an overtone 230659-15
mode.
Figure 12. "Series Resonant" Gate Oscillator
Several problems arise in the design of an overtone os-
cillator. One is to stop the circuit from oscillating in the Positive reactance oscillators ("parallel resonant") use
fundamental mode, which is what it would really rather inverting amplifiers. A single logic inverter can be used
do, for a number of reasons, involving both the amplify- for the amplifier, as in Figure II. The amplifier's phase
ing device and the crystal. Ail additional problem with shift is less critical, ,?ompared to a series resonant cir-
overtone operation is an increased tendency to spurious cuit, and since only one inverter is involved there's less
oscillations. That is because the Rl of various spurious phase error anyway. The oscillation frequency is effec-
modes is likely to be about the same as Rl of the in- tively bounded by the resonant and antiresonant fre-
tended overtone response. It may be necessary, as sug- quencies of the crystal itself. In addition, the feedback
gested in Reference I, to specify a "spurious-to-main- network includes capacitors that parallel the input and
response" resistance ratio to avoid the possibility of output terminals of the amplifier, thus reducing the ef-
trouble. fect of unpredictable capacitances at these points.
Overtone oscillators are not to be taken lightly. One
would be well advised to consult with an engineer who MORE ABOUT USING THE "ON-CHIP"
is knowledgeable in the subject during the design phase
OSCILLATORS
of such a circuit.
In this section we will describe the on-chip inverters on
selected microcontrollers in some detail, and discuss
Series versus Parallel Operation
criteria for selecting components to work with them.
Series resonant oscillators use noninverting amplifiers. Future data sheets will supplement this discussion with
To make a noninverting amplifier out of logic gates updates and information pertinent to the use of each
requires that two inverters be used, as shown in Figure chip's oscillator circuitry.
12.
This type of circuit tends to be inaccurate and unstable Oscillator Calculations
in frequency over variations in temperature and Vee. It
has a tendency to oscillate at overtones, and to oscillate Oscillator design, though aided by theory, is still largely
through Co of the crystal or some stray capacitance an empirical exercise. The circuit is inherently nonlin-
rather than as controlled by the mechanical resonance ear, and the normal analysis parameters vary with in-
of the crystal. stantaneous voltage. In addition, when dealing with the
on-chip circuitry, we have FETs being used as resistors,
The demon in series resonant oscillators is the phase resistors being used as interconnects, distributed delays,
shift in the amplifier. The series resonant oscillator input protection devices, parasitic junctions, and pro-
wants more than just a "noninverting" amplifier-it cessing variations.
wants a zero phase-shift amplifier. Multistage nonin-
verting amplifiers tend to have a considerably lagging Consequently, oscillator calculations are never very
phase shift, such that the crystal reactance must be ca- precise. They can be useful, however, if they will at
pacitive in order to bring the total phase shift around least indicate the effects of variations in the circuit pa-
the feedback loop back up to O. In this mode, a "12 rameters on start-up time, oscillation frequency, and
MHz" crystal may be running at 8 or 9 MHz. One can steady-state amplitude. Start-up time, for example, can
put a capacitor in series with the crystal to relieve the be taken as an indication of start-up reliability. If pre-
crystill of having to produce all of the required phase production tests indicate a possible start-up problem, a
shift, and bring the oscillation frequency closer to fs. relatively inexperienced designer can at least be made
However, to further complicate the situation, the am- aware of what parameter may be causing the marginali-
plifier's phase shift is strongly dependent on frequency, ty, and what direction to go in to fix it.
temperature, VCC, and device sample.
10-289
inter Ap·155
vee PHASE
.1 00'.j:--:---_
50'
F. MHz
0' ~--+---_\+_----+-
4.607, 4.609
-50'
XTALl XTAL2
", . 230659-16 . MAGNITUDE
A) 8081-Type Circuit Configuration during Start-Up. 20
(Excludes Input Protection Devices.) '.
15
~~r----~-------I
~
Z, ______
r---------,
I! I
' I I
10
-'
Ro
~I' lit
1
I I'
I 5
I I
z,---.- :---1
L.._ • ..l I
I 4.607 4.609 4.609
v, I--lkHz-1
c.. I CXI I
L. _____________,.JI
I
L._
___ ..II
I
! Figure 14; Loop Gain versus Frequency
230659-18
(4.608 MHz Crystal)
230659-17
8) AC-Equlvalent Of (A) The gain of the feedback network is
Figure 13. Oscillator Circuit Model Used
In Start-Up Calculations
The analysis used here is mathematically straightfor- And the loop gain is
ward but algebraically intractable. That means it's rela-
tively easy to understand andprogr8.Jll into a computer, , Zj AvZL
but it will not yield a neat formula that gives, say, f3A = ~j + Zt x ZL + Ro
steady-state amplitudl; as ,a function of this or that list
of parameters. A listing of a BASIC program that im- The impedances ZL, Zr, and Zj are defined in Figure
plements the analysis will be found in Appendix II. 13B. .
When the circuit is first powered, up, and before' the Figure 14 shows the way the loop gain thus calculated
oscillations have commenced(and if the oscillations/ail (using typical 805 I-type parameters and a 4.60~ MHz
to commence), the oscillator can be treated as a small crystal) varies with frequency. The frequency ofmterest
signal linear amplifier with feedback. In that case, stan- is the one for which the phase of the loop gain is zero.
dard small-signal analysis techniques can be used to The accepted criterion for start-up is that the magni-
determine start-up characteristics. The circuit model tude of the loop gain must exceed unity atthis frequen-
used in this analysis is shown in Figure 13. cy. This is the frequency at which· the circuit is in reso-
nance. It cOrresponds very closely with the antiresonant
The circuit approximates that there are no high~f~e frequency of the motional arm of the crystal in parallel
quency effects within the amplifier itslef, such that. Its with CL. ' .
high-frequency behavior is dominated by the load Im-
pedance ZL. This is a reasonable approximation for sin" Figure 15 shows the way the loop gain varies with fre-
gle-stage amplifiers of the type used in BOSl-type devic- quency when the parameters of a 3.58 MHz cei'~ic
es. Then the gain of the amplifier as 'a function of fre- resonator are used in place of a crystal (the amplifier
quency is parameters being typical 8051, as in Figure 14). Note
the different frequency scales.
10-290
AP-155
PHASE I...
x ,·pl.".
-8 a Af\Of\".1
SO'
x
\]V \TV 4
O'+---+--t---<--+",,""+---+--t-__
230659-20
-50' A) Poles In Ihe Left-Hall Plane: 1(1) - e- at sin (",I + 8)
J...
'"P"'" X
+a a
MAGNITUDE
20
X
15
230659-21
10 B) Poles In Ihe Right-Hail Plane: I(t) - e+ 8t sin (",t + 8)
f\f\f\f\f\.t
3.55
~~
3.57 3.59 F,MHz
V VVV \
230659-19
230659-22
Figure 15. Loop Gain versus Frequency C) Poles the J", Axis: I(t) - sin (",t + 8)
(3.58 MHz Ceramic)
Figure 16. Do You Know Where Your
Poles Are Tonight?
Start-Up Characteristics
The gain function of interest in oscillators is 1/(1
It is common, in studies of feedback systems, to exam- fJA). Its poles are at the complex frequencies where fJA
ine. the behavior of the closed loop gain as a function of = 1LO", because that value of fJA causes the gain func-
complex frequency s = CT + jCll; specifically, to deter- tion to go to infinity. The oscillator will start up if the
mine the location of its poles in the complex plane. A real part of the pole frequency is positive. More impor-
pole is a point on the complex plane where the gain tantly, the rate at which it starts up is indicated by how
function goes to infinity. Knowledge of its location can much greater than 0 the real part of the pole frequency
be used to predict the response of the system to an is.
input disturbance.
The circuit in Figure 13B can be used to find the pole
The way that the response function depends on the lo- frequencies of the oscillator gain function. All that
cation of the poles is shown in Figure 16. Poles in the needs to be done is evaluate the impedances at complex
left-half plane cause the ·response function to take the frequencies CT + jCll rather than just at CIl, and find the
form of a damped sinusoid. Poles in the right-half plane value of CT + jCll for which fJA = 1LO·. The larger that
cause the response function to take the form of an expo- value of CT is, the faster the oscillator will start up.
nentially growing sinusoid. In general,
Of course, other things besides pole frequencies, things
vet) - eat sin (wt + 8) like the VCC rise time, are at work in determining the
start-up time. But to the extend that the pole frequen-
where a is the real part of the pole frequency. Thus if cies do affect start-up time, we can obtain results like
the pole is in the right-half plane, a is positive and the those in Figures 17 and 18.
sinusoid grows. If the pole is in the left-half plane, a is
negative and the sinusoid is damped. To obtain these figures the pole frequencies were com-
puted for various values of capacitance Cx from
The same type of analysis can usefully be applied to XTAL1 and XTAL2 to ground (thus CX! = CX2 =
oscillators. In this case, however, rather than trying to ex). Then a "time constant" for start-up was calculat-
ensure that the poles are in the left-half plane, we 1
ed as Ts = - where CT is the real part of the pole fre-
would seek to ensure that they're in the right-half plane. CT
An exponentially growing sinusoid is exactly what is quency (rad/sec), and this time constant is plotted ver-
wanted from an oscillator that has just been powered sus Cx.
up.
10-291
inter AP-155
As 'previously mentioned, start-up time can be taken as
TB• MILLISECONDS
an indication of start-up reliability. Start-up problems
.5 are normally associated with CXl and CX2 being too
small or too large for a given resonator. If the parame-
.4 ters of the resonator are known, curves such as in Fig-
ure 17 or 18 can be generated to define acceptable
.3 ranges of values for these capacitors.
.2 As the oscillations grow in amplitude, they reach a lev-
el at which they undergo severe clipping within the am-
.1
plifier, in effect reducing the amplifier gain. As the am-
Cx.pF plifier gain decreases, the poles move towards the jCLI
axis. In steady-state, the poles are on the jCLI axis and
10 30 50 70 90 110 the amplitude of the oscillations is constant. .'
vee:
IE ---
... .... .... .
230659-23
c:;
•
TB• ,.sEC
50
-
i
I
It
~
• I
I
:40
30
I 20
~
--
X2: ~
III ...
·' ·
··· n 10 Cx-pF
[1.
- II
230559-24
o.~-+
40 , 60
__ ~
60
__
100
+-~
120
__~__~__
140 160
230659-26
vec:
X2:
230659-25
Figure 17. Oscillator Start-Up (4;608 MHz Crystal
from Standard Crystal Corp.)
A short time constant means faster: startCup. A long
time constant means slow start-up. Observations of ace
tual start-ups are shown in the figures. Figure 17 is for
a typical 8051 with a 4.608 MHz crystal supplied by
Standard Crystal Corp .• and Figure 18 is for a typical
8051 with a 3.58 MHz ceramic resonator supplied by
NTK Technical Ceramics, Ltd. .
It can be seen in Figure 17 that, for this crystal, values
of Cx between 30 and 50 pF minimize start-up time, 230659-28
but that the exact value in this range is not particularly
important, even if the start-up time itself is .critical.. Figure 18. Oscillator Start-Up (3.58 MHz Ceramic
. Resonator from NTK Technical Ceramics)
10-292
inter AP-155
and source connected to ground (VSS), as shown in
VOLTS Figure 20 for the 8051, and in Figure 21 for the 8048.
1c~a XTAL2
Its function is to limit the positive voltage at the gate of
o 8051
the input FET to the avalanche voltage of the drain
junction. If the input pin is driven below VSS, the drain
XTALI
"::" C.
and source of the protection FET interchange roles, so
its gate is connected to what is now the drain. In this
• condition the device resembles a diode with the anode
connected to VSS.
20 40 60 80 100 120 140
There is a parasitic pn junction between the ohmic re-
·160 180 200 220
-1 sistor and the substrate. In the ROM parts (8015, 8048,
Ca-pF
etc.) the substrate is held at approximately - 3V by the
-2
on-chip back-bias generator. In the EPROM parts
230659-29
A) Signal Levels at XTAL 1
(8751, 8748, etc.) the substrate is connected to VSS.
VOLTS
The effect of the input protection circuitry on the oscil-
5
__ calculated lator is that if the XTALI signal goes negative, its nega-
• experimental tive peak is clamped to - VDS of the protection FET in
pol,n'. the ROM parts, and to about -0.5V in the EPROM
parts. These negative voltages on XTALI are in this
application self-limiting and nondestructive.
VOL at XTAL2
The clamping action does, however, raise the DC level
at XTALl, which in turn tends to reduce the positive
20 40 60 80 100 120 140 160 180 200 220
-1
peak at XTAL2. The waveform at XTAL2 resembles a
230659-30
sinusoid riding on a DC level, and whose negative
B) Signal Levels at XTAL2' peaks are clipped off at zero.
Figure 19. Calculated and Experimental Steady- Since it's normally the XTAL2 signal that drives the
State Amplitudes vs. Bulk Capacitance from internal clocking circuitry, the question naturally arises
XTAL 1 and XTAL2 to Ground as to how large this signal must be to reliably do its job.
In fact, the XTAL2 signal doesn't have to meet the
same VIH and VIL specifications that an external driv-
Steady·State Characteristics er would have to. That's because as long as the oscilla-
tor is working, the on-chip amplifier is driving itself
Steady-state analysis is greatly complicated by the fact through its own 0-to-1 transition region, which is very
that we are dealing with large signals and nonlinear nearly the same as the O-to-l transition region in the
circuit response. The circuit parameters vary with in- internal buffer that follows the oscillator. If some pro-
stantaneous voltage, and a number of clamping and cessing variations move the transition level higher or
clipping mechanisms come into play. Analyses that lower, the on-chip amplifier tends to compensate for it
take all these things into account are too complicated to by the fact that its own transition level is correspond-
be of general use, and analyses that don't take them ingly higher or lower. (In the 8096, it's the XTAL1
into account are too inaccurate to justify the effort. signal that drives the internal clocking circuitry, but the
same concept applies.)
. There is a steady-state analysis in Appendix B that
takes some of the complications into account and ig- The main concern about the XTAL2 signal amplitude
nores others. Figure 19 shows the way the steady-state is an indication of the general health of the oscillator.
amplitudes thus calculated (using typical 8051 parame- An amplitude of less than about 2.5V peak-to-peak in-
ters and a 4.608 MHz crystal) vary with equal bulk dicates that start-up problems could develop in some
capacitance placed from XTALl and XTAL2 to units (with low gain) with some crystals (with high R!).
'ground. Experimental results are shown for compari- The remedy is to either adjust the values of CX! and/or
son. CX2 or use a crystal,with a lower R!.
The waveform at XTALl is a fairly clean sinusoid. Its The amplitudes at XTALl and XTAL2 can be adjusted
negative peak is normally somewhat below zero, at a by changing the ratio of the capacitors from XTAL1
level which is determined mainly by the input protec- and XTAL2 to ground. Increasing the XTAL2 capaci-
tion circuitry at XTAL 1. tance, for example, decreases the amplitude at XTAL2
and increases the amplitude at XTALI by about the
The input protection circuitry consists of an ohmic re- same amount. Decreasing both caps increases both am-
sistor and an enhancement-mode FET with the gate plitudes.
10-293
inter AP·155
Pin Capacitance used than those which minimize start-up time: Larger
values than those can be used in applications where
Internal pin-to-ground and pin-to-pin capacitances at increased frequency stability is desired, at some sacri-
XTALl and XTAL2 will have some effect on the oscil- fice in start-up time.
lator. These capacitances are normally taken to be in
the range of 5 to 10 pF, but they are extremely difficult Standard Crystal Corp. (Reference B) studied the use of
to evaluate. Any measurement of one such capacitance their crystals with the MCS-51 family using skew sam-
will necessarily include effects from the others. One ad- ple supplied by Intel. They suggest putting 30 pF ca~
vantage of the positive reactance oscillator is that the pacitors from XTALl and XTAL2 to ground, if the
pin-to-ground capacitances are paralleled by external crystal is specified as described in Reference B. They
bulk capacitors, so a precise determination of their val~ noted that in that configuration and with crystals thus
ue is unnecessary. We would suggest that there is little specified, the frequency accuracy was ± 0.01 % and the
justification for more precision than to assign them a frequency stability was ± 0.005%, and that a frequency
value of 7 pF (XTAL1-to-ground and XTAL1-to- accuracy of ±0.005% could be obtained by substitut-
XTAL2). This value is probably not in error by J:l1ore ing a 25 pF fixed cap in parallel with a 5-20 pF trim-
than 3 or 4 pF. mer for one of the 30 pF caps.
The XTAL2-to-ground capacitance is not entirely "pin MCS-51 skew samples have 'also been supplied to a
capacitance," but more like an "equivalent output ca- number of ceramic resonator manufacturers for charac-
pacitance" of some 25 to 30 pF, having to include the terization with their products. These companies should
effect of internal phase delays. This value will vary to be contacted for application information on their prod-
some extent with temperature, processing, and frequen- ucts. In general, however, ceramics tend to want some-
cy. what larger values for CX! and CX2 than quartz crys-
tals do. As shown in Figure 1B, they start up a lot faster
that way.
MCS®·51 Oscillator
The on-chip amplifier on the HMOS MCS-51 family is In some application the actual frequency tolerance re-
shown in Figure 20. The drain load and feedback "re- quired is only 1% or so, the user being concerned main-
sistors" are seen to be field-effect transistors. The drain ly that the circuit will osci!!ate. In that case, eXt and
load FET, RD, is typically equivalent to about lK to 3 Cxz can be selected rather freely in the range of 20 to
K-ohms. As an ,amplifier, the low frequency voltage BOpF.
gain is normally between - 10 and - 20, and the out-
put resistance is effectively RD. As you can see, "best" values for these components and
their tolerances are strongly dependent on the applica-
,tion and its requirements. In any case, their suitability
VCC
should be verified by environmental testing before the
design is submitted to production.
MCS®·48 OSCillator "
TO INTERNAL The NMOS and HMOS MCS-4B oscillator is shown in
CIRCUITRY
Figure 21. It differs from the B051 in that its inverting
VCC
XTAL2
230659-31
TO INTERNAL
CIRCUITRY
Figure 20_ MCS®·51 Oscillator Amplifier
The B0151 oscillator is normally used with equal bulk
capacitors placed externally from XTALl to ground
and from XTAL2 to ground.'To determine a reason-
able value of capacitance to use in these positions, given
a crystal of ceramic resonator of known parameters, XTAL2
one can use the BASIC analysis in Appendix II to gen- 230659-,32
erate curves such as in Figures 17 and lB. This proce-
dure will define a range of values that will minimize Figure 21. MCS®·48 OSCillator Amplifier
start-up time. We don't suggest that smaller values be
10-294
AP-155
more slowly, but it eventually takes over and dominates
v.
~ hysteresis the operation of the cirucit. This is shown in Figure
23A.
5V
Due to processing variations, some units seem to have a
harder time coming out of the relaxation mode, partic-
ularly at low temperatures. In some cases the resonator
oscillations may fail entirely, and leave the device in the
relaxation mode. Most units will stick in the relaxation
mode at any temperature if Cx! is larger than about 50
.2V pF. Therefore, Cx! should be chosen with some care,
particularly if the system must operate at lower temper-
v, atures.
LTP UTP
230659-33 One method that has proven effective in all units to
-40·C is to put 5 pF from XTALI to ground and 20
Figure 22. Schmitt Trigger Characteristic pF from XTAL2 to ground. Unfortunately, while this
method does discourage the relaxation mode, it is not
amplifier is a Schmitt Trigger. This configuration was an optimal choice for the resonator mode. For one
chosen to prevent crosstalk from the TO pin, which is thing, it does not swamp the pin capacitance. Also, it
adjacent to the XTALI pin. makes for a rather high signal level at XTALI (8 or 9
volts peak-to-peak).
All Schmitt Trigger circuits exhibit a hysteresis effect,
as shown in Figure 22. The hysteresis is what makes it The question arises as to whether that level of signal at
less sensitive to noise. The same hysteresis allows any XTLAI might damage the chip. Not to worry. The
Schmitt Trigger to be used as a relaxation oscillator. negative peaks are self-limiting and nondestructive. The
All you have to do is connect a resistor from output to positive peaks could conceivably damage the oxide, but
input, and a capacitor from input to ground, and the in fact, NMOS chips (eg, 8048) and HMOS chips (eg,
circuit oscillates in a relaxation mode as follows. 8048H) are tested to a much higher voltage than that.
The technology trend, of course, is to thinner oxides, as
If the Schmitt Trigger output is at a logic high, the the devices shrink in size. For an extra margin of safety,
capacitor commences charging through the feedback the HMOS II chips (eg, 8048AH) have an internal di-
resistor. When the capacitor voltage reaches the upper ode clamp at XTALI to VCC.
trigger point (UTP), the Schmitt Trigger output
switches to a logic low and the capacitor commences In reality, Cx! doesn't have to be quite so small to
discharging through the same resistor. When the capac- avoid relaxation oscillations, if the minimum operating
itor voltage reaches the lower trigger point (LTP), the temperature is not - 40·C. For less severe temperature
Schmitt Trigger output switches to a logic high again, requirements, values of capacitance selected in much
and the sequence repeats. The oscillation frequency is the same way as for an ,80S I can be used. The circuit
determined by the RC time constant and the hysteresis should be tested, however, at the system's lowest tem-
voltage, UTP-LTP. perature limit.
The 8048 can oscillate in this mode. It has an internal Additional security against relaxation oscillations can
feedback resistor. All that's needed is an external ca-
be obtained by putting a 1M-ohm (or larger) resistor
pacitor from XTAL I to ground. In fact, if a smaller from XTALI to VCC. Pulling up the XTALI pin this
external feedback resistor is added, an 8048 system
way seems to discourage relaxation oscillations as effec-
could be designed to run in this mode. Do it at your own tively as any other method (Figure 23B).
risk! This mode of operation is not tested, specified,
documented, or encouraged in any way by Intel for the
Another thing that discourages relaxation oscillations is
8048. Future steppings of the device might have a dif-
low VCC. The resonator mode, on the other hand is
ferent type of inverting amplifier (one more like the
much less sensitive to VCC. Thus if VCC comes up
8051). The CHMOS members of the MCS-48 family do
relatively slowly (several milliseconds rise time), the
not use a Schmitt Trigger as the inverting amplifier. resonator mode is normally up and running before the
relaxation mode starts (in fact, before VCC has even
Relaxation oscillations in the 8048 must be avoided,
reached operating specs). This is shown in Figure 23C.
and this is the major objective in selecting the off-chip
components needed to complete the oscillator circuit.
A secondary effect of the hysteresis is a shift in the
When an 8048 is powered up, if VCC has a short rise oscillation frequency. At low frequencies, the output
time, the relaxation mode starts first. The frequency is signal from an inverter without hysteresis leads (or
normally about 50 KHz. The resonator mode builds lags) the input by '180 degrees. The hysteresis in a
Schmitt Trigger, however, causes the output to lead the
10-295
inter AP-155
input by less than 180 degrees (or lag by more than ISO Kyocera, a ceramic resonator manufacturer, studied
degrees), by an amount that depends on the signal am- the use of some of their resonators (at 6.0 MHz, S.O
plitude, as shown in Figure 24. At higher frequencies, MHz, and 11.0 MHz) with the S049H. Their conclu-
there are additional phase shifts due to the various reac- sion as to the value of capacitance to use at XTAL 1 and
tances in the circuit, but the phase shift due to the hys- XTAL2 was that 33 pF is appropriate at all three fre-
teresis is still present. Since the total phase shift in the quencies. One should probably follow the manufactur-
oscillator's loop gain is necessarily 0 or 360 degrees, it er's recommendations in this matter, since they will
is apparent that as the oscillations build up, the fre- guarantee operation.
quency has to change to allow the reactances to com-
pensate for the hysteresis. In normal operation, this ad- Whether one should accept these recommendations and
ditional phase shift due to hysteresis does not exceed a guarantees without further testing is, however, another
few degrees, and the resulting frequency shift is negligi- matter. Not all users have found the recommendations
ble. to be without occasional problems. If you run into diffi-
27pF
h~
XTALI
VCC:
0 8048
XTAL2
230659-34 XTAL2:
A) When VCC Comes Up Fast, Relaxation Oscillations '
Start First. But Then the Crystal Takes Over.
230659-37
vee
h
lMIl
27pF VCC:
XTALI
, 0 8048
1--6----l XTAL2
.... 27pF XTAL2:
230659-35
B) Weak Pullup (1 Mn or More) on XTAL 1
Discourages Relaxation Mode.
230659-38
27pF
XTALI VCC:
h"
8048
XTAL2
230659-36 XTAL2:
C) No Relaxation Oscillations When VCC Comes Up
More Slowly.
230659-39
Figure 23. Relaxation Oscillations in the 8048
10-296
inter AP-155
culties using their recommendations, both Intel and the It will be helpful to build a test jig that will allow the
ceramic resonator manufacturer want to know about it. oscillator circuit to be tested independently of the rest
It is to their interest, and ours, that such problems be of the system. Both start-up and steady-state character-
resolved. istics should be tested. Figure 25 shows the circuit that
A) Software for Oscillator Test
SOURCE
ORG 0000 H
JMP START
ORG OOOB H ;TlMER 0 INTERRUPT:
CPL Tl ; TOGGLE Tl
RETI
ORG 0001BH ;TIMER 1 INTERRUPT:
CPL Pl.l TOGGLE CRO TRIGGER
DJNZ P2,$ DELAY
CPL Pl.0 TOGGLE VCC CONTROL
RETI
START: MOV TH1, #OFAH ;TIMER 1 RELOAD VALUE
MOV TL1, #OFAH ;START TLl AT RELOAD VALU
MOV TMOD, # 61H ;TlMER 1 TO COUNTER, AUTO
;RELOAD
230659-40
A) Inverter Without Hysteresis: Output Leads Input by 180'. ;TIMER 0 TO TIMER, 16-BIT
MOV IE, # BAH ;ENABLE TIMER. INTERRUPTS
;ONLY
MOV TCON, #50H ;TURN ON BOTH TIMERS
JMP S ;IDLE
END
.+5V
PI.G vee
P1.1
230659-41
B) Inverter With Hysteresis: Output Leads
Input by Less than 180'.
Figure 24. Amplitude-Dependent Phase
f
Shift in Schmitt Trigger
Preproduction Tests
PI.Gor P1.1 vee
TO
An oscillator design should never be considered ready OSCILLOSCOPE
for production until it has proven its ability to function TRIGGER 8051
acceptably well under worst-case environmental condi- Ell
tions and with parameters at their worst-case tolerance ALE
TO FREQ.
limits. Unexpected temperature effects in parts that COUNTER
may already be near their tolerance limits can prevent
start-up of an oscillator that works perfectly well on the
bench. For example, designers often overlook tempera-
ture effects in ceramic capacitors. (Some ceramics are
down to 50% of their room"temperature values at 230659-42
- 20"C and + 60°C). The problem here isn't just one of B) Oscillator Test Circuit (Shown for 8051 Test)
frequency stability, but also involves start-up time and
steady-state amplitude. There may also be temperature Figure 25. Oscillator Test Circuit and Software
effects in the resonator and amplifier.
10-297
AP-155
was used to obtain the oscillator start-up photographs Frequency checks should be made with only the oscilla-
in this Application Note. This circuit or a modified tor circuitry connected to XTALI and ·XTAL2. The
version of it would make a convenient test-vehicle. The ALE frequency can be counted, and the oscillator fre-
oscillator and its relevant components can be physically quency derived from that. In systems where the fre-
separated from the control circuitry, and placed in a quency tolerance is only "nominal," the frequency
temperature chamber. should still be checked to ascertain that the oscillator
isn't running in a spurious resonance or relaxation
Start-up should be observed under a variety of condi- mode. Switching VCC off and on ag~n repeatedly will
tions, including low VCC and using slow and fast VCC help reveal a tendency to go into unwanted modes of
rise times. The oscillator should not be reluctant to oscillation.
start up even when VCC is below its spec value for the
rest of the chip. (The rest of the chip may not function, The operation of the oscillator should then be verified
but the oscillator should work.) It should also be veri- under actual system running conditions. By this stage
fied that start-up occurs when the resonator has more one will be able to have some confidence that the basic
than its upper tolerance limit of series resistance. (Put selection of components for the oscillator itself is suit~
some resistance in series with the resonator for this able, so if the oscillator appears to malfunction in the
test.) The bulk capacitors from XTALI and XTAL2 to system the fault is not in the selection of these compo-
ground should also be varied to their tolerance limits. nents.
The same circuit, with appropriate changes in the soft-
ware to lengthen the "on" time, can be used to test the Troubleshooting Oscillator Problems
steady-state characteristics of the oscillator, specifically
the frequency, frequency stability, and amplitudes at The first thing to consider in case of difficulty is that
XTALl and XTAL2. between the test jig and the actual application there
may be significant differences. in stray capacitances,
As previously noted, the voltage swings at these pins particularly if the actual application is on a multi-layer
are not critical, but they should be checked at the syS" board.
tem's temperature limits to ensure that they are in good
health. ObserVing these signals necessarily changes Noise glitches, that aren't present in the test jig but are
them somewhat. Observing the signal at XTAL2 reo. in the application board, are another possibility. Capac-
quires that the capacitor at that pin be reduced to ac- itive coupling between the oscillator circuitry and other
count for the oscilloscope probe capacitance. Observing signal has already been mentioned as a source of mis-
the signal at XTALl requires the same consideration, counts in the internal clocking circuitry. Inductive cou-
plus a blocking capacitor (switch the oscilloscope input pling is also possible, if there are strong currents near-
to AC), so as to not disturb the DC level at that pin. by. These problems are a function of the PCB layout.
Alternatively, a MOSFET buffer such as the one shown
in Figure 26 can be used. It should be verified by direct Surrounding the oscillator components with "quiet"
measurement that the ground clip on the scope probe is traces (VCC and ground, for example) will alleviate ca-
ohmically cQnnected to the scope chassis (probes are pacitive coupling to signals that have fast transition
incredibly fragile in this respect), and the observations times. To minimize inductive coupling, the PCB layout
should be made with the ground clip on the VSS pin, or should minimize the areas of the loops formed by the
very close to it. If the probe shield isn't operational and oscillator components. These are the loops that should
in use, the observations are worthless. be checked:
XTALl through the resonator to XTAL2;
+12V . XTALl through CX! to the VSS pin;
XTAL2 through CX2 to the VSS pin.
Ic1MFE3005
XTALl
,b IL...
c.:::\
or -5V It is not unusual to find that the grounded ends of CX!
XTAL2
and CX2 eventually connect up to the VSS pin only
I
TO after looping around the farthest ends ofthe board. Not
'0---+-- OSCILLOSCOPE good.
JUMPER FOR
GATE PROTECTION Finally, it should not be overlooked that software prob-
lems sometimes imitate the symptoms of a slow-starting
oscillator or incorrect frequency. Never underestimate
-'-
-5V the perversity of a software problem.
230659-43
Figure 26. MOSFET Buffer for Observing
Oscillator Signals
10-298
inter AP-155
REFERENCES
1. Frerking, M. E., Crystal Oscillator Design and Tem- 7. Eaton, S. S., Micropower Crystal-Controlled Oscilla-
perature Compensation. Van Nostrand Reinhold, 1978. tor Design Using RCA COS/MOS Inverters. RCA Ap-
plication Note ICAN-6539.
2. Bottom, V., "The Crystal Unit as a Circuit Compo-
nent," Ch. 7, Introduction to Quartz Crystal Unit De- 8. Fisher, J. B., Crystal Specifications Jor the Intel
sign. Van Nostrand Reinhold, 1982. 8031/8051/8751 Microcontrollers. Standard Crystal
Corp. Design Data Note #2F.
3. Parzen, B., Design oj Crystal and Other Harmonic
Oscillators. John Wiley & Sons, 1983. 9. Murata Mfg. Co., Ltd., Ceramic Resonator
"Cera lock " Application Manual
4. Holmbeck, J. D., "Frequency Tolerance Limitations
with Logic Gate Clock Oscillators, 31st Annual Fre- 10. Kyoto Ceramic Co., Ltd., Adaptability Test Between
quency Control Symposium. June, 1977. Intel 8049H and Kyocera Ceramic Resonators.
5. Roberge, J. K., "Nonlinear Systems," Ch. 6, 11. Kyoto Ceramic Co., Ltd., Technical Data on Ce-
Operational Amplifiers: Theory and Practice. Wiley, ramic Resonator Model KBR-6.0M, KBR-8.0M, KBR-
1975. l1.0M Application Jar 8051 (Intel).
6. Eaton, S. S. Timekeeping Advances Through 12. NTK Technical Ceramic Division, NGK Spark
COS/MOS Technology. RCA Application Note ICAN- Plug Co., Ltd., NTKK Ceramic Resonator Manual
6086.
10-299
intJ AP-155
APPENDIX A
QUARTZ AND CERAMIC RESONATOR FORMULAS
Based on the equivalent circuit of the crystal, the im-
pedance of the. crystal is
(R1 + jwL1 + 1/jwC1)(1/jwCo)
ZXTAL = R1 + jwL1 + 1/jwC1 + 1/jwCo
After some algebraic manipulation, this calculation can OOR1C'T
8XTAL +CL = arctan 2L C'
be written in the form o 1 - 00 1 T
where CT is the capacitance of Cl in series with Co: The resonant ("series· resonant") frequency is the fre-
quency at which the phase angle is zero and the imped-
ance is low. The antiresonant ("parallel resonant") fre-
quency is the frequency at which the phase angle is zero
and the impedance is high.
The impedance of the crystal in parallel with an exter-
nal load capacitance CL is the same expression, but Each of the above 8-expressions contains two arctan
with Co + CL substituted for Co: functions. Setting the denominator of the argument of
the first arctan function to zero gives (approximately)
Z II 1 1 - w2L1C1 + j ooR 1C1 the "series resonant" frequency for that configuration.
XTAL CL = jOO(C1 + Co + CLl • 1 - oo2L1C'T + jooR1C'T Setting the denominator of the argument of the second
arctan function to zero gives (approximately) the "par-
where C'T is the capacitance of Cl in series with (Co + allel resonant" frequency for that configuration.
Cd:
For example, the resonant frequency of the crystal is
C'T';' C1(CO + CLl the frequency at which
C1+ CO+ CL
1 - oo2L1C1 = 0
The impedance of the crystal in series with the load
capacitance is Thus
1
ZXTAL + CL = ZXTAL + ~C 1
jW L or f ----
s - 2'ITA1C1
= CL + C1 + Co. 1 - oo2L1C'T + jooR1C'T
jooCL (C1 + Co) 1 - oo2L1CT + jooR1CT
where CT and C'T are as defined above.
The phase angles of these impedances are readily ob-
tained from the impedance expressions themselves:
OOR1C1
8XTAL = arctan
1 -w2L1C1
10-300
infef AP·155
It will be noted that the series resonant frequency of the Equivalent Series Resistance
"XTAL+ CL" configuration (crystal in series with CL)
is the same as the parallel resonant frequency of the ESR is the real part of ZXTAL at the oscillation fre-
"XTALllcL" configuration (crystal in parallel with quency. The oscillation frequency is the parallel reso-
Cd. This is the frequency at which nant frequency of the "XTALllcL" configuration
(which is the same as the series resonant frequency of
the "XTAL + CL" configuration). Substituting this fre-
quency into the ZXTAL expression yields, after some
Thus algebraic manipulation,
or
This fact is used by crystal manufacturers in the pro-
cess of calibrating a crystal to a specified load capaci- Co)2
tance. "" R1 ( 1 + CL
By subtracting the resonant frequency of the crystal
from its antiresonant frequency, one can calculate the Drive Level
range of frequencies over which the crystal reactance is
positive: The power dissipated by the crystal is I~RJ, where II is
the RMS current in the motional arm of the crystal.
fa - fs = fs(~1 + C1/CO - 1 This current is given by vx/lz\l, where Vx is the RMS
voltage across the crystal, and Izd is the magnitude of
fS(2~J the impedance of the motional arm. At the oscillation
frequency, the motional arm is a positive (inductive)
. reactance in parallel resonance with (Co + CL)' There-
Given typical values for CI and Co, this range can fore IZII is approximately equal to the magnitude of the
hardly exceed 0.5% offs. Unless the inverting amplifier reactance of (Co + CL):
in the positive reactance oscillator is doing something
very strange indeed, the oscillation frequency is bound 1
to be accurate to that percentage whether the crystal IZ 11 = 21ff(Co + CLl
was calibrated for series operation or to any unspecified
load capacitance. where f is the oscillation frequency. Then,
p = I~ R1 = (I~~I r R1
= [21ff (Co + CLl Vx12 R1
The waveform of the voltage across the crystal
(XTALl to XTAL2) is approximately sinusoidal. If its
peak value is VCC, then Vx is VCCI{i. Therefore,
P = 2R1 [1ff (Co + CLl VCC1 2
10-301
AP·155
APPENDIX B
OSCILLATOR ANALYSIS PROGRAM·
The program is written in BASIC. BASIC is excruciat- It should be noted that the analysis ignores a number of
ingly slow, but it has some advantages. For one thing, important items, such as high-frequency effects in the
more people know BASIC than FORTRAN. In addi- on-chip circuitry. These effects are difficult to predict,
tion, a BASIC program is easy to develop, modify, and and are no doubt dependent on temperature, frequency,
"fiddle around" with. Another important advantage is and device sample. However, they can be simulated to a
that a BASIC program can run on practically any small reasonable degree by adding an "output capacitance" of
computer system. about 20 pF to the circuit model (i.e" in parallel with
CX2) as described below.
Its slowness is a problem, however. For example, the
routine which calculates the "start-up time constant"
discussed in the text may take several hours to com- Notes on Using the Program
plete. A person who finds this program useful may pre-
fer to convert it to FORTAN, if the facilities are avail- The program asks·the user to input values for various
able. circuit parameters. First the crystal (or ceramic resona-
tor) parameters are asked for. These are RI, LI, CI,
and CO. The manufacturer can supply these values for
Limitations of the Program selected samples. To obtain any kind of correlation be-
tween calculation and experiment,· the values of these
The program was developed with specific reference to parameters must be known for the specific sample in
805 I-type oscillator circuitry. That means the on-chip the test circuit. The value that should be entered for CO
amplifier is a simple inverter, and not a Schmitt Trig- is the CO of the crystal itself plus an estimated 7 pF to
ger. The 8096, the 80C51, the 80C48 and 80C49 all account for theXTALI-to-XTAL2 pin capacitance,
have simple inverters. The 8096 oscillator is almost plus any other stray capacitance paralleling the crystal
identical to the 8051, differing mainly in the input pro- that the user may feel is significant enough to beinclud-
tection circuitry. The CHMOS amplifiers have some- ed.
what different parameters (higher gain, for example),
and different transition levels than the 8051. Then the program asks for the values of the XTALI-to-
ground and XTAL2-to-ground capacitances. For.
The MCS-48 family is specifically included in the pro- CXTALl, enter the value of the externally connected
gram only to the extent that the input-output curve bulk capacitor plus an estimated 7 pF for pin capaci-
used in the steady-state analysis is that of a Schmitt tance. For CXTAL2, enter the value of the externally
Trigger, if the user identifies the device under analysis connected bulk capacitor plus an estimated 7 pF for pin
as an MCS-48 device. The analysis does not include the capacitance plus about 20 pF to simulate high-frequen-
voltage dependent phase shift of the Schmitt Trigger. cy roll-off and phase shifts in the on-chip circuitry.
The clamping action of the input protection circuitry is Next the program asks for values for the small-signal
important in determining the steady-state amplitudes. parameters of the on-chip amplifier. Typically, for the
The steady-state routine accounts for it by setting the 8051/8751,
negative peak of the XTALl signal at a level which Amplifier Gain Magnitude = IS
depends on the amplitude of the XTALl signal in ac- Feedback Resistance = 2300 Kn
cordance with experimental observations. It's an exer- Output Resistance = 2 Kn
cise in curve-fitting. A user may fmd a different type of
curve works better. Later steppings of the chips may The same values can be used for MCS-48 (NMOS and
behave differently in this respect, having somewhat dif- HMOS) devices, but they are difficult to verify, because
ferenf types of input protection circuitry. the Schmitt Trigger does not lend itself to small-signal
measurements.
10-302
AP-155
100 DEFDBL C.D.F.G.L.P.R.S.X
200 REM APRIL B. 19B3
300 REM **********.*.*.***.*************** •••• *********** ••• *.**.*** •••••••• ***
400 REM
500 REM FUNCTIONS
600 REM
700 REM
BOO REM FNZM(R.X) MAGNITUDE OF A COMPLEX NUMBER. :R+jX:
900 DEF FNZM(R.X) SOR (R····2+X ..... 2)
1000 REr1
1100 REM FNZP(R.X) ANGLE OF A COMPLE~ NUMBER
1200 REM 180/PI*ARCTANIX/R) IF R)O
1300 REM 180/P I*ARCTANI X/R I + IBO IF R',O AND X>O
1400 REM 180/PI*ARCTANIX/RI - 180 IF R<:O AND X(O
1500 DEF FNZP(R.X) 180/PI*ATN(X/R) - ISGNIR)-I)*SGNIX)*90
1600 REM
1700 REM INDUCTIVE IMPEDANCE AT C0I1PLEX FREQUENCY S+jF 1HZ)
IBOO REM Z =- 2*PI*S*L + J2*PI*F*L
1900 REM FNRL(S.LI + jFNXLIF.L)
2000 DEF FNRLISL.LL) = 2_*PI*SL*LL
2100 DEF FNXLIFL.LL) = 2_*PI*FL*LL
2200 REM
2300 REM CAPACITIVE IMPEDANCE AT COMPLEX FREQUENCY S+jF 1HZ)
2400 REM Z = 1/[2*PI*(S+jF)*Cl
2500 REM = S/C2*PI*CS"2+F"2)*Cl + J(-F)/C2.PI*CS ..... 2+F·..·2)Cl
2600 REM = FNRCIS.F.C) + jFNXCIS.F.CI
2700 DEF FNRC ISC. FC. CC I = SCI 12_*PI* ISC "'2+FC"'2)*CC I
2800 DEF FNXC ISC. FC. CC) = -FCII2_*PI*(SC"'2+FC"'21*CC I
2900 REM
3000 REM RATIO OF TWO COMPLEX NUMBERS
3100 REM RA+jXA ,RA*RB+XA*XB
3200 REM + j
3300 REM RB+ .rX3 RB-2+XB-2 RB-2+XB-2
3400 REM FNRRIRA.XA.RB.XB) + jFNXR(RA.XA.RB.XB)
3500 DEF FNRR(RA.XA.RB. XB) = (RA*RB+XA*XB)/(RB A 2+XB-2)
3600 DEF FNXR(RA.XA.RB. XBI = IXA*RB-XB*RA)/(RB"2+XB A 2)
3700 REM
3800 REM PRODUCT OF TWO COMPLEX NUMBERS
3900 REM (RA+jXA)*IRB+jXB) RA*RD-XA*XB + jIXA*RB+RA*XB)
4000 REM FNRM(RA.XA.RB.XB) + jFNXMIRA.XA.RB.XB)
4100 DEF FNRM(RA.XA.RB.XBI RA*RD - XA*XB
4200 DEF FNXM(RA.XA.RB. XBI RA*XD + RB*XA
4300 REM
4400 REM
4500 REM PARALLEL 1I1PEDANCE.S
4600. REM
4700 REM IRA+jXA): :(RD+jXB)
4800 REM RA+RD +jIXA+XB)
4900 RE'M
5000 REM
5100 REM +
5200 REM (RA+RD) "2 + (XA+XB)-2
5300 REM
5400 REM FNRPIRA.XA.RD.XDI + jFNXP(RA.XA.RD.XB)
5500 DEF FNRPIRA.XA.RB.XD) IRA*IRB"2+XB"'21 + RD*(RA"2+XA-211/«RA+RBI-2 + (XA+XBI-21
5600 DEF FNXPIRA. XA. RB. XDI = (XA*(RB"'2+XD"21 + XB*(RA-2+XA-2) 1/( (RA+RBI-2 + (XA+XBI-2)
5700 REM
~BOO REM ******** •• ********.***************** •• ************************.******.
5900 REM
6000 REM BEGIN COMPUTATIONS
6100 REM
6200 LET PI = 3.141592654_
6300 REM
6400 REM DEFINE CIRCUIT PARAMETERS
6500 Q05UB 14~OO
6600 REM
6700 REM ESTABLISH r~or"INAL RESONANT ANI) ANT I RESONANT CRYSTAL FREGUENCIES
6800 FS = FIX(1/(2*PI-SQR(Ll*Cllll
6900 FA = FIX(1/12*PI*SQR(Ll*CI*CO/(CI'~Oi)l)
7000 PRINT
7100 PRINT "XTAL 15 SERIES RESONANT AT ".FS." HZ"
7200 PRINT" PARALLEL RESONANT AT ".FA." HZ"
7300 PRINT
7400 PR INT "SELECT: 1. LIST PARAMETERS"
7500 PR INT 2. CIRCUIT ANALYSIS;'
7600 PRINT " 3. OSCILLATION FREQUENC't"
7700 PRINT" 4. START'·UP TiME CONSTANT"
'800 PRINT 5. STEADY-STATE ANAl.YSIS"
230659-44
10-303
inter Ap·155
7900 PRINT
8000 INPUT N
8100 IF N=I THEN PRINT ELSE 8600
8200 REM
8300 REM ------------- ------.- LIST PARAMETERS ---.-----------------------.--
8400 (lOSUS 17100
8500 OOTO 6800
8600 IF N-2 THEN PRINT ELSE 9400
8700 REM
8800 REM - --.---------------.--- CIRCUIT ANALYSIS - --------------------------
,8900 PRINT " FREQUENCY' S-+,}F TVPE CS I, IF I "
9000 INPUT SQ.FQ
9100 (lOSUS 20200
9200 (lOSUS 26600
9300 (lOTO 6800
9400 IF N=3 THEN 10300 ELSE 11000
9500 REM
9600 REM ------------------ OSCILLATION FREQUENCY ------------------------
9700 CL • CX*CY/CCX+C~1 + CO
9800 FO = FIXC I/C2*PI4S0RCL1*CI*CL/CCl-+CU I I)
9900 SO ~ 0
10000 DF= FIXCIO A INTCLOGCFA-FSI/LOOCIOI-2)+. 5)
10100 DS • 0
10200 RETURN
10300 (lOSUS 9700
10400 (lOSUS 30300
10500 PRINT
10600 PRINT
10700 PRINT "FREOUENCY AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE. "
10800 (lOSUB 26600
10900 (lOTO 6800
11000 IF N=4 THEN PRINT ELSE 12200
IIIOO·REM
11200 REM ---------------- START-UP TIME CONSTANT -------------------------
11300 PRINT "THIS WILL TAV.E SOME TIME
11400 (lOSUB 9700
11500 (lOSUB 37700
11600 PRINT
11700 PRINT
11800 PRINT "FREQUENCV AT WHICH LOOP GAIN = I AT 0 DEGREES:"
11900 (lOSUB 26600
12000 PRINT: PRINT "THIS YIELDS A START-UP TIME CONSTANT OF "i CSNGCIOOOOOO!/C2*PHSQ))i" MICROSECS"
12100 (lOTO 6800 ~
12200 IF N=5 THEN PRINT ELSE 7300
12300 REM
12400 REM ---------------- STEADY-STATE ANALYSIS ---------------------------
12500 PRINT "STEADY-STATE ANALYSIS"
12600 PRINT
12700 PRINT "SELECT: 1. 803118051"
12800 PRINT 2. 8751"
12900 PRINT " 3. 8035/8039/8040/8048/8049"
13000 PRINT 4. 8748/8749"
13100 INPUT ICiI
13200 IF ICX<I OR ICX)'; THEN 12600
13300 (lOSUB 46900
13400 (lOTO 7300
13500 REM SUBROUTINE 3ELOW DEFINES INPUT-OUTPUT CURVE OF OSCILLATOR CV.T
13600 IF ICiI>2 AND VO=5 AND VI'~2 THEN RETURN
13700 VO= -IO*VI + 15
13800 IF va>' THEN va = 5
13900 IF VO<.2 THEN va = 2
14000 IF ICiI>2 AND VO>2 THEN VO = 5
14100 RETURN
14200 REM
14300 REM ******.************************ .... **+ .... ***.*.****.*.*********
14400 REM
14500 REM DEFINE CIRCUIT PARAMETERS
14600 REM
14700 INPUT" Rl COHMS)"iRI
14800 INPUT" Ll (HENRY) "i Ll
1490'0 INPUT" CI (PF) "i X
15000 Cl • X*IE-12
15100 INPUT" 'CO (PF) "i X
15200 CO = X*IE-12
15300 INPUT" CXTALI (PF)"iX
15400 CX = X*IE-12
15500 INPUT" CXTAL2 (PF)"i X
15600 CV • X*IE-12
230659-45
10-304
inter Ap·155
1~700 INPUT" GAIN FACTOR MAGNITUDE";AVII
15800 INPUT" AMP FEEDDACK RESISTANCE CK-OHMs,",X
15900 RX = ~*IOOOII
16000 INPUT" AMP OUTPUT RESISTANCE CK-OHr1s,"; X
16100 RO = ~*IOOOII
16200 REM
16300 REM
16400 REM L!S! CURRENT PARAMETER VALUES
16500 GOsUD 17100
16600 RETURN
16700 REr1
16800 REM
16900 REM *.*******.*4~.***4**.4~4***~*~*4._~.*********.******** ********
17000 REI1
17100 REI'o LIST CURr~ENT PARAMETER VALUES
17200 REM
17300 PRINT
17400 PRINT "CURRENT PARAMETER VALUES RI "i RI," OHMS"
17500 PRINT" 2 LI ", CSNGCLI)i" HENRY"
17600 PRINT" 3 CI "i CsNGCCI*IE+12)i" PF"
17700 PRINT" 4 CO ", CsNGCCO*IE+12)i" PF"
17800 PRINT" 5 CXTAL! = ",CsNG(CX*IE+12)i" PF"
17900 PRINT" 6 CXTAL2 = ",CsNG(CY.IE+12);" PF"
18000 PRINT " 7. AMPLIFIER GAIN MAGNITUDE "i AVII
18100 PRINT 8. FEEDBAC" RESISTANCE "i CsNGCRX* OOI)i" K-OHMS"
18200 PRINT 9. OUTPUT RESISTANCE "i CsNG (RD •. 001) i" K-OHMs"
18300 PRINT
18400 PRINT "TO CHANGE A PARAMETER VALUE, TYPE CPARAM NO ), CNEW VALUE>' "
18500 PRINT "OTHEIlWIsE, TYPE O,C- "
18600 INPUT NX,X
18700 IF NX=O THEN RETURN
18800 IF NX=I THEN RI X
18900 IF NX=2 THEN LI X
19000 IF NX=3 THEN CI X*IE-12
19100 IF NX=4 THEN CO X*IE-12
19200 IF NX=5 THEN CX X*IE-12
19300 IF NX=6 THEN CV X*lE-12
19400 IF NX=7 THEN AVII = X
19500 IF NX=8 THEN RX X*IOOO'
19600 IF NX=9 THEN RO = X*IOOO'
19700 GOTO 17400
19800 REM
19900 REM
20000 REM ***********4******************-*******************************
20100 REM
20200 REM CIRCUIT ANALYSIS
20300 REM
20400 REM This Tout in. calculate. the loop gain at complex frequenc~ SG+JFG.
20500 REM
20600 REM I. Crystal ,"'pedance RE + JXE
20700 REM
20800 XI = FNXL(FQ,LII + FNXC(SQ,FQ,Cll
20900 RE = FNRP«RI+FNRL(SQ,LI)+FNRCcsQ,FQ,CI»,XI,FNRC(SQ,FQ,CO),FNXC(SQ,FQ,CO»
21000 XE = FNXP«RI+FNRLCSQ,LI)+FNRCCSQ,FQ,CI»,XI,FNRC(SQ,FQ,CO),FNXC(sQ,FQ,CO»
21100 REM
21200 REM 2. RF + JXF (RE+JXE): :Campli'ler feedback resistance)
21300 REM
21400 RF = FNRP(RX,O,RE,XE'
21500 XF = FNXP(RX,O,RE,XE)
21600 REM
21700 REM 3. Input impedance. 7.l RI + JXI impedance of CXTALl
21800 REM
21900 RI = FNRC (sG, FG, C'')
22000 XI = FNXC (sG, FG, C:<.>
22100 REM
22200 REM 4 Load impedance: ZL = Ilmpedance of CXTAL2):: [(RF+RIl+J(XF+XIll
·22300 REM
22400 RL = FNRP«RF+RI). (XF+XI),FNRC(SO.FIJ,CY),FNXC(SQ,FG,CY»
22500 XL = FNXP«RF+RIl,(XF+XIl,FNRCCSQ,r'G,CY),F'NXCCsG,FQ,CY»
22600 REM
22700 REM 5 AmpllflOr ga,n A = -AV*ZL/iZL+RO)
22800 REM = At rlial) + JA( Imag Inary)
22900 REM
23000 ARII = -AVII*FNRRCRL, XL, (RO+RL), ~Ll
23100 AlII = -AVII.FNXRCRL, XL, CR(J+RL), 'Ll
23200 REM
23300 REM 6 Feedbatlt ratio J,t.-?tai lJiJ+JXlil((RF+RI)-t.tCXF+Xt)J
23400 REM B'r~alJ ~ JE(lma~ln~ry)
230659-46
10·305
inter AP-155
23500 REM
23600 DRII = FNRR(RI. XI. IRI+RF). CXI+XF) I
23700 Bill = FNXRCRI.XI. (RI+RFI. (XI+XF))
23800 REM
23900 REM 7. Amplifier gain ill magnitu"de/phase form" AR+JAI A at AP d~grees
24000 REM
24100 A = FNZMCARII.AIII)
24200 AP = FNZP(ARII.AI.)
24300 REM
24400 REM 8 Cbeta).n magnitude/phase form D~+JBI B at BP deg . . es
24500 REM
24600 B = FNZMCDR •• DI.)
24700 UP = FNZPCBR •• BI.)
24800 REM
24900 REM 9 Loop ga.n 'G = CB~+JBI).tAR+JAI)
25000 REM = G(real) • JG( lmag inartj)
25100 REM
25200 GR = FNRMCAR •• AI •• BR •• BI.)
25300 GI = FNXM(AR •• AI •• BR •• BI.)
25400 REM
25500 REM 10. Loop 951n in magnitude/p~ase form. GR+JGI AL at AB degrees
25600 REM
25700 AL = FNZM(GR.GI)
25800 AO = FNZP(GR.GI!
25900 RETURN
26000 REM
26100 REM
26200 REM ************_**_********._ ••• ****************************** •••
26300 REM
26400 REM PRINT CIRCUIT ANALYSIS RESULTS
26500 REM
26600 PRINT
26700 PRINT" FREOUENCY = "'SO," + J",FO," HZ"
26800 PRINT" HAL IMPEDANCE = ".FNZM(RE.XE)," OHMS.AT ",FNZPCRE.XE)," DEGREES"
26900 PRINT" CRE = ",CSNG(RE)," OHMS)"
27000 PRINT" (XE = ", CSNG(XE), " OHMS)"
27100 PRINT" LOAD IMPEDANCE = ",FNZMCRL.Xl), " OHMS AT ",FNZP(RL.XL), " DEGREES"
27200 PRINT" AMPLIFIER GAIN = ", A," AT ", AP, ,,' DEGREES"
27300 PRINT" FEEDBACK RATIO = ".D." AT ",BP," DEGREES"
27400 PRINT" LOOP GAIN = ", AL," AT ",.AQ," DEGREES"
27500 RETURN
27600 REM
27700 REM
27800 REM ***************************************************.**********
27900 REM
28000 REM SEARCH FOR FREOUENCY CS+JF)
28100 REM AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE
28200 REM
28300 REM This routine s.arc~e5 for the fre~uenc~ at which the imaginar~ part
28400 REM of the loop gain is zero. The algorithm is as fDl1a~s:
28500 REM 1. Calculate the sign of the ima91nar~ part of the loop gain (01),
28600 REM 2. Increment the fre~uency.
28700 REM 3. Calculate the sIgn of GI at the incremented frequency.
28800 REM 4. If the sign of GI has not changed. go back to 2.
28900 REM 5. If th@ sign of GI ha!> ct'tanged. and this frequenc~ is lIIithin
29000 REM 1Hz of the previous Sign-change. exit the routine.
29100 REM 6. Otherlilise. divide the frequency increment b~ -10.
29200 REM 7. Go back to 2.
29300 REM The routine is entered lIIlth the starting frequency SO+JFO and
29400 REM starting increment DS+JDF already defined by the calling program.
29500 REM In actual use either DS or DF is·zero. so the routine sear~hes·.fDr
29600 REM a GI=O pOInt by lncrementlng either SO Dr FO while holding the other
29700 REM constant. It returns control to t~e calling program ~ith the
29800 REM increm~nted part of the frequency being within 1Hz of the actual
29900 REM GI=O point.
30000 REM
30100 REM 1. CALCULATE THE SIGN OF THE !l1AGINARY PART OF THE LOOP GAIN (GI).
30200 REM
30300 GOSUU 20200
30400 GOSUB 26600
30500 IF GI=O THEN RETL'RN
30600 SXX = INT(SGNCGI))
30700 IF SXX=+I THEN OS -OS
30800 REM (REVERSAL OF OS FO~ GIOO IS FOR THE POLE-SEARCH ROUTINE. )
30900 REM
31000 REM 2 INCREMENT THE FREQUENCY.
31100 REM
31200 SP =50
230659-47
10,306
AP-155
31300 FP = FQ
31400 Sel = sa ? OS
31500 Fel ~ FQ + OF
31600 REt1
31700 REM 3 CALCULATE THE SIGll OF GI AT THE INCREMENTED FREOUENCY.
31800 REM
31900 GOSUB 20200
32000 GOSUB 26600
32100 IF INTISGNIGI))=O THEN RETURN
32200 REM
32300 REM 4 IF THE SIGN OF III HAS Imr CHANGE!), GO BACK TO 2.
32400 REM
32~00 IF SX7.?INT(SGN(GI))=O THEN PRINT ELSE 31400
32600 SX7. = -SX7.
32700 REM
32800 REM 5 IF THE SIGN OF GI f(AS CHANGED, ANO .IF THIS FREOUENCY IS WITHIN
32900 REM 1HZ OF 'T'"4E PREVIOUS SIGN-CHANGE; AND !F G! IS NEGATIVE. THEN
33000 REM EXIT THE ROUTINE CTHF ADDITIONAL REClUIREMENT FOR NEGATIVE GI
33100 REM IS FOR THt:: POLE-SEARCH ROUTINE. t
33200 REt1
33300 IF ABS(5P-50)<:1 AND ADS(FP-FO)<:1 AND 5X'l.=-1 THEN RETURN
33400 REM
33500 REM 6. DIVIDE THE FREQUI::NCY INCREt1ENT BY -10
33600 REM
33700 OS = -05/10.
33800 OF = -DF/IO.
33900 REM
34000 REM 7. GO BACK TO 2
34100 REM
34200 GOTO 31200
34300 REM
34400 REM
34500 REM •• * ••••• ***** ••••• ** ••••• ** ••••• ** •••• **** •• ** ••• ** ••• ********
34600 REM
34700 REM SEARCH FOR POLE FREQUENCY
34800 REM
34900 REM This routine searches for the frequency at which the loop gain = 1
35000 REM at 0 degrees. That fre~uency 1~ t~e pole frequency of the closed-
35100 REM loop gain function. The pole frequl"ncy is a complex number, SO+JFG
35200 REM CHz). Oscillator start-up ensues 1f 5Q~O. The algorithm is based on
3~300 REM the calculated behaVior of the phase angle of the loop gain in the
3~400 REM reglon of interest on the complex plane. The locus of points of zero
35500 REM phase angle crosses the J-axis at the oscillation frequenc~ and at
35600 REM some higher irequency. In between these two crossings of the J-axis.
35700 REM the locus lies in Quadrant I of the comple, plane. forming an
35800 REM approximate parabola which opens to the left. The basic plan is to
35900 REM follow the locus from where, It crosses the J-axis at the oscillation
36000 REM frequenc~. into Quadrant I. and find the point on that locus where
36100 REM the loop gain has a magnltude of 1. The algorithm' is as follows:
36200 REM 1. Find thi' oscillation freQ.uency. O+JFG.
36300 REM 2. At thlS frequenc~ calculate the sign of (AL-l) (AL = magnitude
36400 REM of loop gain. )
36500 REM· 3. IneTement FQ.
36600 REM 4. For this value of FQ, find the value of SQ for which the loop
36700 REM gain has zero phase
36800 REM 5. For this value of SQ+JFQ, calculate the sign of (AL-11.
36900 REM 6. If the sign of (AL-l) t'las not changed, go back to 3.
37000 REM 7. If the sign of CAL-I) has changed. and this value of FO is
37100 REM within 1Hz of the previous slgn-change, exit the routine.
37200 REM S. OtherWlse, dIvide the FO-increment by -10.
37300 REM 9. Go bat\!: to 3
37400 REM
37500 REM I. FIND THE OSCILLATION FREQUENCY, O"'JFCl
37600 REM
37700 GOSUB 9700
37800 GOSUB 30300
37900 REM
38000 REM 2. AT THIS FREQUENCY, CA'-CUL.ATE THE SIGN OF (AL··I)
38100 REM
38200 SY7. = INTlSGN(AL··I'))
38300 IF SY7.=-1 THEN STOP
38400 REM ESTABLISH INITIAL INCREMEIHAT ION VALUE FOR FO
38500 FI = FO
38600 OF = (FA-Flt/IO.
38700 GOSUB 30300
38800 DE (FQ-Flt/IO.
38900 OF 0
39000 FQ FI
230659-48
10-307
intJ AP-155
39100 REM
39200 REM 3. INCREMENT FO
39300 REM
39400 Fa - Fa + DE
39:100 REM
39600-REM 4. FOR THIS VALUE OF FO. FIND THE VALUE OF SO FOR WHICH THE LOOP
39700 REM GAIN HAS ZERO PHASE. CTHE ROUTINE WHICH DOES THAT NEEDS OF • O.
39BOO REM 50 THAT IT CAN HOLD FO CONSTAr~T. AND NEEDS AN INITIAL VALUE FOR
39"00 REM OS. WHICH IS ARBITRARILY SET TO 05 c 1000. I .
40000 REM
40100 OS c 1000.
40200 SO • 0
40300 GOSUB 30300
40400 IF AL-I! THEN RETURN
40500 REM
40600 REM 5. FOR THIS VALUE OF SO+.iFO. CALCULATE THE SIGN OF CAL-II.
40700 REM 6. IF THE SIGN OF CAL-II HAS NOT CHANGED. GO BACK TO 3.
40BOO REM
40900 IF SYX+INTCSGNCAL-I!II=O THEN PRINT ELSE 39400
41000· REM
41100 REM 7. IF THE SIGN OF CAL-II HAS CHANGED. AND THIS VALUE OF Fa IS WITHIN
41200 REM 1HZ OF THE PREVIOUS SIGN-CHANGE. EXIT THE ROUTINE.
41300 REM
41400 IF ABSCFI-FOI<I THEN RETURN
41500 REM
41600 REM 8. DIVIDE THE Fa-INCREMENT BY -10.
41700 REM
41BOO DE - -DEliO.
41900 FI • FO
42000 BYX • -SYX
42100 REM
42200 REM 9. GO BACK TO 3.
42300 REM
42400 GOTO 39400
42500 REM
42600 REM
42700 REH ••••• * ••• * ••••••••••• ** •••• *** ••••••••••••••••••••••••• *.****••
42800 REM
42900 REM STEADY-STATE ANALYSIS
43000 REM
43100 REM The circuit model. u~ed in this anal~sis is similar to the Dn~ used
43200 REM in the small-signal anal~si5j but differs from it in twa respects.
43300 REM First, it includes clamping and clipping effects described in the
43400 REM text. Second, the voltage source in th'. Theve"i" equivalent of the
43500 REM .mplifier is controlled b~ t~e input voltage in accordance with an
43600 REM input-output curve defined' elsewhere in the program.
43700 REM The analvsis applies a sinusoidal "input signal of arbitraT~
43800 REM amplitude, at the oscillation freq,uency, to the XTALl pin, then
43900 REM calculates the resulting lafaveform from ·the voltage source. Using
44000 REM standard Fourier techni~ues, the fundamental frequency component of
44100 REM this waveform is extracted. This fre~uency component is then
44200 REM multiplied by the factor :ZL/(ZL+RO):. and the result is taken to be
44300 REM the signal appearing at the XTAL2 pin. This signal is ·then
44400 REM mU,ltiplied by the feedback ratiO (beta), and the result is taken to
44500 REM be the signal .. ppe-aring at the XTALl p.in. The algorithm is no ...
44600 REM repeated using this co'mputed XTALI signal a5 the assumed input
44700 REM sinusoid. Every time the algorithm is repeated, nt'I&I,v.alue. appear at
44BOO REM XTALI and XTAL2, but the values cl1ange less and less ",ith· each
44900 REM repetition, Eventually tl1ey stop changing. ,This is the steady-stat~.
45000 REM The algortthm is as fo1101&15; ,
45100 REM 1. Compute approximate oscillation f~equency,
45200 REM 2. Call a circuit analysts at this frequency.
45300 REM 3. Find the ~uie5cent levels at XTALI and XTAL2 cto .stablish the
45400 REM beginning DC level at XTALl). .
45500 REM 4. Assume an initial amplitude far the XTALI signal.
45600 REM 5. Correct the DC l.vel at XTALI for clamping effects; if neces •• rv.
45700 REM 6. Using th9 appropriate input-out'put curve, extract a DC level and
45BOO REM the fundamental frequency component Cmult1plying the latter by
45900 REM :ZL/CZL+ROI: I.
. 46000 REM 7. Clip Qff the negatlv~ portion of this output sig~.l, if the
46100 REM neqative peak fa!l~ below zero.
46200 REM 8 If thi~ s1gnaL multiplied by <beta). differs from the input
46300 REM amplltude by less than JmV· or 1f the algorithm has been repeated
46400 REM 10 times. v.it the routine
46500 REM or. Otherlalise. multipl~ the X1A!....i2 amplitude by (beta) and feed it
46600 REM baclI: to )t'TALl. and go bactr to 5.
46700 REM
46BOO REM 1. COMPUTE APPROXIMATE OSCILLATION FREOUENCY.
230659-49
10-308
AP-155
46900 GOSUS 9700
47000 REM
47100 REM 2. CALL A CIRCUIT ANALYSIS AT THIS FREQUENCY.
47200 GOSUS 20800
47300 PRINT : PRINT PRINT "ASSUMED OSCILLATION FREQUENCY: n
47400 GOSUS 26600
47500 PRINT PRINT
47600 REM
47700 REM 3. FINO QUIESCENT POINT
47800 REM IAt quiescence the voltage. at XTALI and XTAL2 ne "quill. This
47900 REM volt.g. level is found by trlal-a~d-.rror. based on the input-
480'00 REM output curve, sa that a person can change the input-output curve
48100 REM as desired without haVIng to re-calculate the qUIescent point. )
48200 VI ~ 0
48300 VB = I
48400 1'.1= I
48500 VI = VI + VB
48600 GOSUB 13600
48700 IF ASSIVO-VI)<..OOI THEN 49200
48800 IF Kl+SGNIVO-VI)=O THEN 48900 ELSE 48500
48900 1'.1 - SGNIVO-VI)
49000 VB - -VB/IO
49100 GOTO 48500
49200 VB = VI
49300 PRINT "QUIESCENT POINT = ",VB
49400 REM
49500 REM 4. ASSUME AN INITIAL AMPLITUDE FOR THE XTALI SIGNAL.
49600 EI - .01
49700 NRX = 0
49800 REM
49900 REM 5. CORRECT FOR CLAMP ING EFFECTS, IF NEC·ESSARY.
50000 REM II'.I ilnd 1'.2 are curve-fitting parameter. for the ROM p"rt •.
50100 1'.1 (2.5-VB)/13-VB)
502001'.2 = (VB-I. 25)/13-VO)
50300 IF ICXa 2 OR ICX-4 THEN IF EI<'(VO+. 5) THEN EO = VB ELSE EO - EI - .5
50400 IF ICX=I OR ICX~3 THEN IF EI<.IVO+. 5) THEN EO VB ELSE EO = KI*EI+K2
50500 NRX = NRX + I
50600 REM
50700 REM 6. DERIVE XTAL2 AMPLITUDE
50800 VO = 0
50900 VC - O·
51000 VS - 0
51100 FOR NX = -25 TO +24
51200 VI • EO - EI*COSIPI*NX/25)
51300 GOSUe 13600
51400 VO = VO + VO
51500 VC = VC + VO*COSIPI*NX/25)
51600 VS = VS + VO*SINIPI*NX/25)
51700 NEXT NX .
51800 VO = VO/50
51900 VI = SQRIVC~2+VSA2)/25*FNZM(RL,XL)/FNZMIIRL+RO),XL)
52000 REM
52100 REM 7. CLIP XTAL2 SIGNAL.
52200 IF VO-Vl<'O THEN VL = 0 ELSE VL = VO-VI
52300 PRINT =
PRINT "XTALI SWING ",EO-EI," TO ",EO+EI
52400 PRINT "XTAL2 SWING = ",VL, ,. TO ",VO+VI
52500 REM .
52600 REM 8. TEST FOR TERMINATION.
:52700 IF. I\IlS!EI-\i.l*I!J<. 001 OR II'R7.=IO THEN REn'~"I
52800 REM
52900 REM 9. FEED BACK TO XTALI AND REPEAT
53000 EI = VI*O
53100 GOTO 50300
230659-50
10·309
APPLICATION AP-252
NOTE
September 1987
Designing With The 80C51 BH
TOM WILLIAMSON
MCO APPLICATIONS ENGINEER
Order Number: 270068-002
10-310
inter AP-252
CMOS EVOLVES substrate. Both processes have their advantages and
disadvantages, which are largely transparent to the
The original CMOS logic families were the 4000-series user.
and the 74C-series circuits. The 74C-series circuits are
functional equivalents to the corresponding numbered Lower operating voltages are easier to obtain with the
74-series TTL circuits, but have CMOS logic levels and powell structure than with the n-well structure. But the
. retain the other well known characteristics of CMOS powell structure does not easily adapt to an EPROM
logic. which would be pin-for-pin compatible with HMOS
EPROMs. On the other hand the n-well structure can
These characteristics are: low power consumption, high be based on the solidly founded HMOS process, in
noise immunity, and slow speed. The low power con- which nFETs are built into a p-type substrate. This
sumption is inherent to the nature of the CMOS circuit. allows somewhat more than half of the transistors in a
The noise immunity is due partly to the CMOS logic CHMOS chip to be constructed by processes that are
levels, and partly to the slowness of the circuits. The already well characterized. "
slow speed is due to the technology used to construct
the transistors in the circuit. Currently Intel's CHMOS microcontrollers and memo-
ry products are n-well devices, whereas CHMOS mi-
The technology used is called metal-gate CMOS, be- croprocessors are powell devices.
cause the transistor gates are foryned by metal deposi-
tion. More importantly, the gates are formed after the Further discussion of the CHMOS technology is pro-
drain and source regions have been defined, and must vided in References I and 2 (which are reprinted in the
overlap the source and drain somewhat to allow for Microcontroller Handbook).
alignment tolerances. This overlap plus the relatively
large size of the transistors themselves result in high
electrode capacitance, and that is what limits the speed THE MCS®-51 FAMILY IN CHMOS
of the circuit.
The 80C51BH is the CHMOS version of Intel's original
High speed CMOS became feasible with the develop- 8051. The 80C31BH is the ROMless 80C51BH, equiva-
ment ofthe self-aligning silicon gate technology. In this lent to the 8031. These CHMOS devices are architec-
process polysilicon gates are deposited before the turally identical with their HMOS counterparts, except
source and drain regions are defined. Then the source that they have two added features for reduced power.
and drain regions are formed by ion implantation using These are the Idle and Power Down modes of opera-
the gate itself as a mask for the implantation. This elim- tion.
inates most of the overlap capacitance. In addition, the
process allows smaller transistors. The result is a signif- In most cases, an 80C51BH can directly replace the
icant increase in circuit speed. The 74HC-series of 8051 in "existing applications. It can execute thl'; same
CMOS logic circuits is based on this technology, and code at the same speed, accept signals from the same
has speeds comparable to LS TTL, which is to say sources, and drive the same loads. However, the
about 10 times faster than the 74C-series circuits. 80C51BH covers a wider range of speeds, will emit
CMOS logic levels to CMOS loads, and will draw about
The size reduction that contributes to the higher speed 1/10 the current of an 8051 (and less yet in the reduced
also demands an accompanying reduction in the maxi- power modes). Interchangeability between the HMOS
mum supply voltage. High-speed CMOS is generally and CHMOS devices is discussed in more detail in the
limited to 6V. final section of this Application Note.
It should be noted that the 80C51BH CPU is not static.
WHAT IS CHMOS? That means if the clock frequency is too low, the CPU
might forget what it was doing. This is because the
CHMOS is the name given to Intel's high-speed CMOS circuitry uses a number of dynamic nodes. A dynamic
processes. There are two CHMOS processes, "one based node is one that uses the note-to-ground capacitance to
on an n-well structure and one based on a powell struc- form a temporary storage cell. Dynamic nodes are used
ture. In the n-well structure, n-type wells are diffused to reduce the transistor count, and hence the chip area,
into a p-type substrate. Then the n-channel transistors thus to produce a more economical device.
" (nFETs) are built into the substrate and pFETs are
built into the n-wells. In the powell structure, p-type This is not to say that the on-chip RAM in CHMOS
wells are diffused into an n-type substrate. Then the microcontrollers is dynamic. It's not. It's the CPU that
nFETs are built into the wells and pFETs, into the is dynamic, and that is what imposes the minimum
clock frequency specification.
"10-311
inter Ap·252
LATCHUP First, for equal supply voltages, CMOS gives (andre-
quires) a higher "logic 1" level than TTL. Secondly,
Latchup is an SCR-type turn-on phenomenon that is CMOS logic levels are Vee (or VDD) dependent,
the traditional nemesis of CMOS systems. The sub- whereas guaranteed TTL logic levels are fixed when
strate, the wells, and the transistors form parasitic pnpn Vee is within TTL specs.
structures within the device. These parasitic structures
tum on like an SCR if a sufficient amount of forward Standard .74HC logic levels are as follows:
current is driven through one of the junctions. From
the circuit designer~s point of view it can happen when- VIHMIN = 70% of Vee
ever an input or output pin is externally driven a diode VILMAX = 20% of Vee'
drop above Vee or below Vss, by a source that is capa- VOHMIN = Vee - 0.1v.lloHI ~ 20 p.A
ble of supplying the required trigger current. VOLMAX = o.W. lIod ~ 20 IJA
Figure I compares 74HC, LS TTL, and 74HCT logic
However much of a problem latchup has been in the
levels with those of the HMOS 8051 and the CHMOS
past, it is good to know that in most recently developed
CMOS devices, and specifically in CHMOS deyices, the 80C5IBH for Vee = 5V.
current required to trigger latchup is typically well. over Output logic levels depend of course on load current,
100 mAo The 80C5IBH is virtually immune to latchup. and are normally specified at sever8I load currents.
(References I and 2 present a discussion of the latchup
When CMOS and TTL are powered by the same Vee,
mechanisms and the steps that are taken on the chip to the logic levels guaranteed on the data sheets indicate
guard against it.) Modern CMOS is not absolutely im-
that CMOS can drive TTL, but TTL can't drive
mune to latchup, but with trigger currents in the hun- CMOS. The incompatibility is that the TTL circuit's
dreds of mA, latchup is certainly a lot easier to avoid VOH level is too low to reliably be recognized by the
than it once was.
CMOS circuit as a valid VIH.
A careless power-up sequence might trigger a latchup Since HMOS circuits were designed to be TTL-compat-
in the older CMOS families, but it's unlikely to be a ible, they have the same incompatibility.
major problem in high-speed CMOS or in CHMOS.
There is still some risk incurred in inserting or remov- Fortunately, 74HCT-series circuits are available to ease
ing chips or boards in a CMOS system while the power these interfacing problems. They have TTL-compatible
is on. Also, severe transients, such as inductive kicks or logic levels at the inputs and standard CMOS levels at
momentary short-circuits, can exceed the trigger cur- the outputs.
rent for latchup. .
The 80C51BH is designed to work with either TTL or
For applications in which some latchtip risk'seems un- CMOS. Therefore its logic levels are specified very
avoidabie, you can put a small resistor (lOOn or so) in much like 74HCT circuits. That is, its input logic levels
series with signal lines to ensure that the trigger current are TTL-compatible, and its output characteristics are
will never be reached. This also helps to control over- like standard high-speed CMOS.
shoot and RFI. . .
NOISE CONSIDERATIONS
LOGIC LEVELS AND INTERFACING
One of the major reasons for going to CMOS has tradi-
PROBLEMS tionally been that CMOS is less susceptible to noise. As
CMOS logic levels. differ from TTL levels in two ways. previously noted, its low susceptibility to noise is
Vee = 5V
Logic State
74HC 74HCT LSTTL 8051 80C51BH
VIH 3.5V 2.0V 2.0V 2.0V 1.9V
VIL 1.0V O.SV O.SV O.SV 0.9V
VOH 4.9V 4.9V 2.7V 2.4V 4.5V
VOL O.W O.W 0.5V 0.45V 0.45V
Figure 1. Logic Level Comparison. (Output voltage levels depend on load current.
, Data sheets list guaranteed output levels for several load currents. The output
levels listed here are for minimum loading.)
10-312,
inter AP-252
partly due to superior noise margins, and partly due to current in extremely sharp spikes at the clock edges.
its slow speed. The VHF and UHF components of these spikes are not
drawn from the power supply, but from the decoupling
Noise margin is the difference between VOL and VIL, capacitor. If the decoupling circuit is not sufficiently
or between VOH and VIH. If VOH from a driving cir- low in inductance, Vee will glitch at each clock edge.
cuit is 2.7V and VIH to the driven circuit is 2.0V, then We suggest that a 0.1 J.LF decoupler cap be used in a
the driven circuit has 0.7V of noise margin at the logic minimum-inductance configuration with the microcon-
high level. These kinds of comparisons show that an troller. A minimum-inductance configuration is one
all-CMOS system has wider noise margins than an all- that minimizes the area of the loop formed by the chip
TTL system. (Vee to Vss), the traces to the decoupler cap, and the
decoupler cap. PCB designers too often fail to under-
Figure 2 shows noise margins in CMOS and LS TTL , stand that if the traces that connect the decoupler cap
systems when both have Vee = 5V. It can be seen that to the Vee and Vss pins aren't short and direct, the
CMOS/CMOS and CMOS/CHMOS systems have an decoupler loses much of its effectiveness.
edge over LS TTL in this respect.
Overshoot and ringing in signal lines are potential
Noise margins can be 'misleading, however, because sources of logic upsets. These can largely be controlled
they don't say how much noise energy it takes to induce by circuit layout. Inserting small resistors (about 1000.)
in the circuit a noise voltage of sufficient amplitude to in series with signal lines that seem to need them will
cause a logic error. This would involve consideration of also help.
the width of the noise pulse as compared with the cir-
cuit's response speed, and the impedance to ground The sharp edges produced by high-speed CMOS can
from the point of noise introduction in the circuit. cause RFI problems. The severity of these problems is
largely a function of the PCB layout. We don't mean to
When these considerations are included, it is seen that imply that all RFI problems can be solved by a better
using the slower 74C- and 4000-series circuits with a 12 PCB layout; It may well be, for example, that in some
or 15V supply voltage does offer a truly improved level RFI-sensitive designs high-speed CMOS is simply not
of noise immunity, but that high-speed CMOS at 5V is the answer. But circuit layout is a critical factor in the
not significantly better than TTL. noise performance of any electronic system, and more
so in high-speed CMOS systems than others.
One should not mistake the wider supply voltage toler-
ance of high-speed CMOS for Vee glitch immunity. Circuit layout techniques for minimizing noise suscepti-
Supply voltage tolerance is a DC rating, not a glitch bility and generation are discussed in References 3
rating. through 6.
For any'c1ocked CMOS; and most especially for VLSI
CMOS, Vee decoupling is critical. CHMOS draws UNUSED PINS
CMOS input pins should not be left to float, but should
Noise Margin for always be pulled to one logic level or the other. If they
Vee = 5V float, they tend to float into the transition region be-
Interface
Logic Low Logic High tween 0 and I, where the pullup and pulldown devices
VIL-VOL VOH-VIH
in the input buffer are both conductive. This causes a
significant increase in Icc. A similar effect exists in
74HCto74HC O.9V 1.4V HMOS circuits, but with less noticeable results.
LSTTL to LSTTL 0.3V 0.7V
In 80C51BH and 80C3lBH designs, unused pins of
LSTTL to 74HCT O.3V O.7V Ports I, 2, and 3 can be ignored, because they have
internal pUllups that will hold them at a valid Logic I
LSTTL to 80C51 BH 0.3V O.7V
level. Port 0 pins are different, however, in not having
74HC to 80C51 BH O.8V 3.0V internal pullups (except during bus operations).
80C51BH to 74HC 0.8V 1.0V When the 80C5IBH is in reset, the Port 0 pins are in a
Figure 2. Noise Margins for CMOS float state unless they are externally pulled up or down.
and LS TTL Circuits If it's going to be held in reset for just a short time, the
transient float state can probably be ignored. When it
comes out of reset, the pins stay afloat unless
10-313
AP-252
they are externally pulled either up or down. Alterna- PULLUP RESISTORS
tively, the software can internally write Os to whatever
Port·O pins may be unused. If a pullup resistor is to be used on a Port 0 pin, its
minimum value is determined by IOL requirements. If
The same considerations are applicable to the the pin is trying to emit a 0, then it will have to sink the
80C31BH with regards to reset. But when the current from the pullup resistor plus whatever other
80C3IBH comes out of reset, it commences bus opera- current may be sourced by'other loads connected to the
tions, during which the logic levels at the pins are al~ pin, as shown in Figure 3a, while maintaining a valid
ways well defined as high or low. output low (VOL)' To guarantee that the 'pin voltage
will not exceed 0.45V, the resistor should be selected so
Consider the 80C3IBH in the Power Down or Idle that IOL doesn't exceed the value specified on the data
modes, however. In those modes it is not fetching in- sheet. In most CMOS applications, the minimum value
structions, and the Port 0 pins will float if not external- would be about 2k .0.
ly pulled high or low. The choice of whether to pull
them high or low is the designer's. Normally it is suffi- The maximum value you could use depends on how
cient to pull them up to Vee with 10k resistors. But if fast you want the pin' to pull up after bus operations
power is going to be removed from circuits that are have ceased, and how high you want the VOH level to
connected to the bus, it will be advisable to pull the bus be. The smaller the resistor the faster it pulls up. Its
pins down (normally with 10k resistors). Considera- effect on the VOH level is that VOH = Vee - (ILl +
tions involved in selecting pUllup and pulldown resistor IIH) X R. ILl is the input leakage current to the Port 0
values are as follows. pin, and IIH is the input high current to the external
loads, as shown in Figure 3b.Normally VOH can be
expected to reach 0.9 Vee if the pullup resistance does
VCC not exceed about 50k .0.
8DC51BH
R
..JQ!:. ..J!h- Pulldown Resistors
po.x t---.......- - - E~1J:Jls"L
If a pulldown resistor is to be used on a Port 0 pin, its
minimum value is determined by VOH. requirements
10L = vcc + ilL
R during bus operations, and its maximum value is in
270068-1 most cases determined by leakage current.
Figure 3a. Conditions defining the minimum During bus operations. the port uses internal pullups to
value for R. PO. X is emitting a logic low. R must emit Is. The D.C. Characteristics in the data sheet list
be large enough to not cause IOL to exceed guaranteed VOH levels for given IOH currents. (The "-"
data sheet specifications. sign in the IOH value means the pin is sourcing that
current to the external load, as shown in Figure 4.) To
ensure the VOH level listed in the data sheet, the resis-
80C51BH
R
I 80C51 BH ~ -1!!!..
~ .JJtt... Po.xt---_o----- E~1J:J4s'L
po.x t---_----E~1,E:~L
R
VOH = VCC -(ILl + IIH) xR
270068-2 IOH = YOH + nf!
·R
270068-3
Figure 3b. Conditions defining the maximum
value for R. PO.X is in a high Impedance Figure 4a. Conditions defining the minimum
state. R must be small enough to keep value for R. PO.X is emitting a 1 in a bus
VOH acceptably high. operation. R must be large enough to not cause
IOH to exceed data ~heet specifications.
10-314
inter Ap·252
VOH
- + I I
IIH:5: IOH DRIVE CAPABILITY OF THE
R INTERNAL PULLUPS
tor has to satisfy where I IH is the input high current to There's an important difference between HMOS and
the external loads. CHMOS port drivers. The pins of Ports 1, 2, and 3 of
the CHMOS parts each have three pullups: strong, nor-
When the pin goes into a high impedance state, the mal, and weak, as shown in Figure S. The strong pullup
pulldown resistor will have to sink leakage current (p 1) is only used during O-to-l transitions, to hasten the
from the pin, plus whatever other current may be transition. The weak pullup (p2) is on whenever the bit
sourced by other loads connected to the pin, as shown latch contains a 1. The "normal" pullup (p3) is con-
in Figure 4b. The Port 0 leakage current is ILl on the trolled by the pin voltage itself.
data sheet. The resistor should be selected so that the
voltage developed across it by. these currents will be The reason that p3 is controlled by the pin voltage is
seen as a logic low by whatever circuits are connected that if the pin is being used as an input, and the external
to it (including the 80CSIBH). In CMOS/CHMOS ap- source pulls it to a low, then turning offp3 makes for a
plications, SOk .n is normally a reasonable maximum lower IlL. The data sheet shows an "ITL" specification.
value. This is the current that p3 will source during the time
the pin voltage is making its I-to-O transition. This is
what IlL would be if an input low at the pin didn't tum
80C51BH ...!!:!..... p3 off.
po.xt---.....- - - - E~1J:~:L Note, however, that this p3 tum-off mechanism puts a
restriction on the drive capacity of the pin if it's being
R used as an output. If you're trying to output a logic
high, and the external load pulls the pin voltage below
the pin's YIHMIN spec, p3 might tum off, leaving only
VOL =(ILl + ilL) x R the weak p2 to provide drive to the load. To prevent
this happening, you need to ensure that the load doesn't
270068-4
draw more than the IOH spec for a valid YOH. The idea
Figure 4b. Conditions defining the maximum is to make sure the pin voltage never falls below its own
value for R. PO.X is In a high impedance state. YIHMIN ,specification.
R must be small enough to keep VOL
acceptably low.
vee vec vee
Q
FROM PORT
LATCH
READ
PO AT PIN
270068-5
Figure 5. 80C51BH Output Drivers for Ports 1,2 and 3
10-315
inter AP-252
POWER CONSUMPTION CMOS circuits draw current in sharp spikes during log-
ical transitions. These current spikes are made up of
The main reason for going to CMOS, of course, is to two components. One is the current that flows during
conserve power. (There are other reasons, but this is the the transition time when pullup and pulldown FETs are
main one.) Conserving power doesn't mean just reduc- both active. The average (DC) value of this component
ing your electric bill. Nor does it necessarily relate to is larger when the transition times of the input signals
battery operation, although battery operation without are longer. For this reason, if the current draw is a
CMOS is pretty unhandy. The main reason for conserv- critical factor in the design, slow rise and fall times
ing power is to be able to put more functionality into a should be~voided, even when the system speed doesn't
smaller space. The reduced power consumption allows seem to justify a need for nanosecond switching speeds.
the use of smaller and lighter power supplies, and less
heat being generated allows denser packaging of circuit The other component is the current that charges stray
components. Expensive fans and blowers can usually be and. load capacitance at the nodes of a CMOS logic
eliminated. . gate. The average value of this current spike is its area
(integral over time) multiplied by its rep rate. Its area is
A cooler running chip is also more reliable, since most the amount of charge it takes to raise the node capaci-
random and wearout failures relate to gie temperature. tance, C, to Vee. That amount of charge is just C )Ii
And finally, the lower power dissipation will allow Vee. So the average value of the current spike is C x
more functions to be integrated onto the chip. Vee x f, where f is the clock frequency.
The reason CMOS consumes less power than NMOS is This component of current increases linearly with clock
that when it's in a stable state there is no path of con- frequency. For minimal current draw, the 80CS2BH-2
duction from Vee to Vss except through various leak- is spec'd to run at frequencies as low as 500 kHz.
age paths. CMOS does draw current when it's changing
states. How much current it draws depends on how Keep in mind, though, that other component of current
often and how quickly it changes states. that is due to slow rise and fall times. A sinusoid is not
the optimal waveform to drive the XTALI pin with.
Yet crystal oscillators, including the one on the
80C5lBH, generate sinusoidal waveforms. Therefore, if
the on-chip oscillator is being used, you can expect the
device to draw more current at 500 kHz, than it does at
1.5 MHz, as shown in Figure 6. If you derive a good
sharp square wave from an external oscillator, and use
ICC
that to drive XTALI, then the niicrocontroller will
draw less current. But the external oscillator will prob-
ably make up the difference.
The 80C5lBH has two power-saving features not avail-
able in the HMOS devices. These are the Idle and Pow-
-1.SMHz CLOCKFREQ er Down modes of operation. Theon,chip hardware
270068-6 that implements these reduced .power modes is shown
in Figure 7. Both modes are invoked by software.
Figure 6. 80C51BH ICC vs. Clock Frequency
CPU
INTERRUPT
SERIAL PORT .
TIMER/COUNTERS
270068-7
Figure 7. Oscillator and Clock Circuitry Showing Idle and Power Down Hardware
10-316
Ap·252
Idle: In the Idle Mode (IDL = 0 in Figure 7), the CPU There are two ways to terminate Idle. Activation 'of any
puts itself to sleep by gating off its own clock. It doesn't enabled interrupt will cause the hardware to clear bit 0
stop the oscillator. It just stops the internal clock signal of the PCON register, terminating the Idle mode. The
from getting to the CPU. Since the CPU draws SO to 90 interrupt will be serviced, and following RETI the next
percent of the chip's power, shutting it off represents a instruction to be executed will be the one following the
fairly significant power savings. The on-chip periperals instruction that invoked Idle.
(timers, serial port, interrupts, etc.) and RAM continue
to function as normal. The CPU status is preserved in The other way is with a hardware reset. Since the clock
its entirety: the Stack Pointer, Program Counter, Pro- oscillator is still running, RST only needs to be held
gram Status Word, Accumulator, and all other regis- active for two machine cycles (24 oscillator periods) to
ters maintain their data during Idle. complete the reset. Note that this exit from Idle writes
Is to all the ports, initializes all SFRs to their reset
The Idle Mode is invoked by setting bit 0 (IDL) of the values, and restarts program execution from location O.
PCON register. PCON is not bit-addressable, so the bit
has to be set by a byte operation, such as Power Down: In the Power Down Mode (PD = 0 in
Figure 7), the CPU puts the whole chip to sleep by
ORL PCON,#l turning off the oscillator. In case it was running from
an external oscillator, it also gates off the path to the
The PCON register also contains flag bits GFO and internal phase generators, so no internal clock is gener-
GFl, which can be used for any general purposes, or to ated even if the external oscillator is still running. The
give an indication if an interrupt occurred during nor- on-chip RAM, however, saves its data, as long as Vee
mal operation or during Idle. In this application, the is maintained. In this mode the only IcC that flows is
instruction that invokes Idle also sets one or both of the leakage, which is normally in the micro-amp range.
flag bits. Their status can then be checked in the inter-
rupt routines. The Power Down Mode is invoked by setting bit 1 in
the PCON register, using a byte instruction such as
While the device is in the Idle Mode, ALE and PSEN
emit logic high (VOH), as shown in Figure S. This is so ORL PCON,#2
external EPROM can be deselected and have its output
disabled. While the device is in Power Down, ALE and' PSEN
emit lows (VOU, as shown in Figure S. The reason they
The port pins hold the logical states they had at the are designed to emit lows is so that power can be re-
time the Idle was activated. If the device was executing moved from the rest of the circuit, if desired, while the
out of external program memory, Port 0 is left in a high SOCS51BH is in its Power Down mode.
impedance state and Port 2 continues to emit the high
byte of the program counter (using the strong pullups The port pins continue to emit whatever data was writ-
to emit Is). If the device was executing out of internal ten to them. Note that Port 2 emits its P2 register data
program memory, Ports 0 and 2 continue to emit what- even if execution was from external program memory.
ever is in the PO and P2 registers.
Internal Execution External Execution
Pin
Idle Power Down Idle Power Down
ALE 1 0 1 0
PSENI 1 0 1 0
PO SFR Data SFR Data High-Z High-Z
P1 SFR Data SFR Data SFR Data SFR Data
P2 SFR Data SFR Data PCH SFR Data
P3 SFR Data SFR Data SFR Data SFR Data
Figure 8_ Status of Pins in Idle and Power Down Modes. "SFR data" means the port pins emit their
internal register data. "PCH" is the high byte of the Program Counter.
10-317
AP-252
Port 0 also emits its PO register data, but if execution If Vee is going to be held to the entire circuit, one
was from external program memory, the PO register would want to write values to the port latches that
data is FF. The oscillator is stopped, and the part re- would deselect peripherals before invoking Power
mains in this stl\te as long as Vee is held, and until it Down. For example, if external memory is being used,
receives an external reset signal. the P2 SFR should be loaded with a value which will
not generate an active chip select to any- memory de-
The only exit from Power Down is a hardware reset. vice.
Since the oscillator was stopped, RST must be held ac-
tive long enough for the oscillator to re-start and stabi- In some applications, Vee to part of the system may be
lize. Then the reset function initializes all the Special shut. off during Power Down, so that even quiescent
Function Registers (ports, timers, etc.) to their reset and standby currents are eliminated. Signal lines that
values, and re-starts the program from location o. connect to those chips must be brought to a logic low,
Therefore, timer reloads, interrupt enables, baud rates, whether the chip in question is CMOS, NMOS, or
port status, etc. need to be re-established. Reset does TTL, before Vee is shut off, to them. CMOS pins have
not affect the·content of the on-chip data RAM. If Vee parasitic pn junctions to Vee, which will be forward
was held .during Power Down, the RAM data is still biased if Vee is reduced to zero while the pin is held at
good. a logic high. NMOS pins often have FETs that look
like diodes to Vee. TTL circuits may actually be dam-
aged by an input high if Vee = o. That's why the
USING THE POWER DOWN MODE 80C5IBH outputs lows at ALE and PSEN during Pow-
er Down.
The software-invoked Power Down feature offers a
means of reducing the power consumption to a mere Figure 9 shows a circuit that can be used to tum Vee
trickle in systems which are to remain dormant for off to part of the system during Power Down. The cir-
some period of time, while retaining important data. cuit will ensure that the secondary circuit is not de-en-
ergized until after the 80C31BH is in Power Down, and
The user should give some thought to what state the that the 80C3lBH does not receive a reset (terminating
port pins should be left in during the time the clock is the Power Down mode) before the secondary circuit is
stopped, and write those values to the port latches be- re-energized. Therefore, the program memory itself can
fore invoking Power Down. be part of the secondary circuit.
VCC1
C1
1,.1
R VCC2
20K
270068-8
Figure 9. The 80C31BH de-energizes part of the circuit (VCC2) when it goes into Power Down.
Selections of R arid Q2 depend on VCC2 current draw.
10-318
AP-252
In Figure 9, when Vee is switched on to the 80C31BH, USING POWER MOSFETs to
capacitor CI provides a power-on reset. The reset func-
tion writes Is to all the port pins. The I at P2.6 turns
CONTROL VCC
Q Ion, enabling Vee to the secondary circuit through Power MOSFETs are gaining in popularity (and avail-
transistor Q2. As the 80C3IBH comes out of reset, Port ability). The easiest way to control Vee is with a Logic
2 commences emitting the high byte of the Program Level pFET, as shown in Figure lOa. This circuit al-
Counter, which results in the P2.7 and P2.6 pins out- lows the full Vee to be used to turn the device on.
putting Os. The 0 at P2.7 ensures continuation of Vee Unfortunately, power pFETs are not economically
to the secondary circuit. competitive with bipolar transistors of comparable rat-
ings.
The system software must now write a I to P2.7 and a 0
to P2.6 in the Port 2 SFR, P2. These values will not Power nFETs are both economical and available, and
appear at the Port 2 pins as long as the device is fetch- can be used in this application if a DC supply of higher
ing instructions from external program memory. How- voltage is available to drive the gate. Figure lOb shows
ever, whenever the 80C31BH goes into Power Down, how to implement aVec switch using a power nFET
these values will appear at the port pins, and will shut and a (nominally) + 12V supply. The problem here is
off both transistors, disabling Vee to the secondary cir- that if the device is on, its source voltage is + SV. To
cuit. maintain the on state, the gate has to be another 5 or
lOY above that. The "12V" supply is not particularly
Closing the switch Sire-energizes the secondary cir- critical. A minimally filtered, unregulated rectifier will
cuit, and at the same time sends a reset through C2 to suffice.
the 80C31BH to wake it up. The diode Dl is to prevent
Cl from hogging current from C2 during this second-
ary reset. D2 prevents C2 from discharging through the BATTERY BACKUP SYSTEMS
RST pin when Vee to the secondary circuit goes to
zero. Here we consider circuits that normally draw power
from the AC line, but switch to battery operation in the
event of a power failure. We assume that in battery
operation high-current loads will be allowed to die
along with the AC power. The system may continue
then with reduced functionality, monitoring a control
transducer, perhaps, or driving an LCD. Or it may go
into a bare-bones survival mode, in which critical data
is saved but nothing else happens till AC power is re-
stored.
In any case it is necessary to have some early warning
of an impending power failure so that the system can
270068-9 arrange an orderly transfer to battery power. Early
a. Using a pFET warning systems can operate by monitoring either the
AC line voltage or the unregulated rectifier output, or
+12V'
even by monitoring the regulated DC voltage.
Monitoring the AC line voltage gives the earliest warn-
12K
ing. That way you can know within one or two half-cy-
cles of line frequency that AC power is down. In most
cases you then have at least another half-cycle of line
frequency before the regulated Vee starts to fall. In a
half-cycle of line frequency an 80C51BH can execute
about 5,000 instructions-plenty of time to arrange an
orderly transfer of power.
The circuit in Figure II uses a Zener diode to test the
270068-28
line voltage each half-cycle, and a junction transistor to
b. Using an nFET pass the information on to the 80C5IBH. (Obviously a
voltage comparator with a suitable reference source can
Figure 10. Using Power MOSFETs
to Control VCC2
10-319
inter AP-252
~II~
VCC2
VCC
t----!
: BACKUP
BATTERY
80C51BH
80C31BH
t--.......- - - - t I N T O
Zl
.01,,1
Ql
2N3904
OR EQUIV. VSS
270068-10
Figure 11. Power Failure Detector with Battery Backup. When AC power fails,
VCC1 goes down and VCC2 is held.
perform the same function, if one prefers.) The way it Automatic wake~up on power restoration is also possi-
works is if the line voltage reaches an acceptably high ble. If the CPU is in Idle, it can continue to respond to
level, it breaks over Zl, drives QI to saturation, and any interrupts that might be generated by QI. The in-
interrupts the 80C51BH. The interrupt would be tran- terrupt service routine determines from the status of
sition-activated, in this application. The interrupt serv- flag bits GFO and GFI in PCON that it is in Idle be-
ice routine reloads one of the C5IBH's timers to a value cause there was a power outage. It can then sample
that will make it roll over in something between one Veel through a voltage comparator similar to ZI, QI
and two half-cycles of line frequency. As long as the in Figure II. A satisfactory level of Veel would be
line voltage is healthy, the timer never rolls over, be- indicated by the transistor being in saturation.
cause it is reloaded every half-cycle. If there is a single
half-cycle in which the line voltage doesn't reach a high But perhaps you can't spare the timer that is the key to
enough level to generate the interrupt, the timer rolls the operation of the circuit in Figure II. In that case a
over and generates a timer interrupt. retriggerable one-shot, triggered by the AC line voltage,
can perform essentially the same function. Figure 12
The timer interrupt then commences the transition to shows an example of this type of power failure detector.
battery backup. Critical data needs to be copied into A retriggerable one-shot (one half of a 74HC123) moni-
protected RAM. Signals to circuits that are going to tors the AC line voltage through transistor QI. QI re-
lose power must be written to logic low. Protected cir- triggers the one-shot every half-cycle of line frequency.
cuits (those powered by Vee2) that communicate with If the output pulse width is between one and two half-
unprotected circuits must be deselected. The microcon- cycles of line frequency, then a single missing or low
troller itself may be put into Idle, so that it can contin- half-cycle will generate an active low warning flag,
ue some level of interrupt-driven functionality, or it which can be used to interrupt the microcontroller.
may be put into Power Down.
The interrupt routine takes care of the transition to
Note that if the CPU is going to invoke Power Down, battery backup. From this point Veel mayor may not
the Special Function Registers may also need to be cop- actually drop out: The missing half-cycle of line voltage
ied into protected RAM, since the reset that terminates that caused the power down sequence may have been
the Power Down mode will also intialize all the SFRs nothing more than a short glitch. If the AC line comes
to their reset values. back strong enough to trigger the one-shot while Veel
is still up (as indicated by the state of transistor Q2),
The circuit in Figure II does not show a wake-up then the other half of the 74HCI23 will generate a
mechanism. A number of choices are available, howev- wake-up signal.
er. A pushbutton could be used to generate an inter-
rupt, if the CPU is in Idle, or to activate reset, if the
CPU is in Power Down.
10-320
Ap·252
VCCI VCC2 BACKUP
BATTERY
1/1/1/1
20K
12K
47K 1,,1
VCC2
Y.z74HC123
RIC C
Q CLR Q WAKE·UP
a Q WAKE·UP
A VSS
'f.!74HC123
1,,1
INTO
(80C51BH)
270068-11
Figure 12. Power Failure Detector uses retriggerable one-shots to flag impending power outage and
generate automatic wake-up when power returns.
Having been awakened, the 80C51BH will stay awake POWER SWITCHOVER CIRCUITS
for at least another half-cycle of line frequency (another
5,000 or so instructions) before possibly being told to Battery backup systems need to have a way for the
arrange another transfer of power. Consequently, if the protected circuits to draw power from the line-operated
line ,voltage is jittering erratically around the switch- power supply when that source is available, and to
over point (determined by diode ZI), the system will switch over to battery power when required. The
limp along executing in half-cycle units of line frequen- switchover circuit is simple if the entire system is to be
cy. battery powered in the event of a line power outage. In
that case a pair of diodes suffice, as shown in Figure 12,
On the other hand, if the power outage is real and provided Vee MIN specs are still met after the diode
lengthy, Veel will eventually fall below the level at drop has been subtracted from its respective power
which the backup battery takes over. The backup bat- source.
tery maintains power to the 80C5lBH, and to the
74HC123, and to whatever other circuits are being pro- The situation becomes more complicated when part of
tected during this outage. The battery voltage must be the circuit is going to be allowed to die when the AC
high enough to maintain VeeMIN specs to the power goes out. In that case it is difficult to maintain
80C5lBH. equal Vees to protected and unprotected circuits (and
possibly dangerous not to).
If the microcontroller is an 80C3lBH, executing out of
external ROM, and if the C3lBH is put into Idle dur- The problem can be alleviated by using a Schottky di-
ing the power outage, then the external ROM must also ode instead of a lN4001, for its lower forward voltage
be supplied by the battery. On the other hand, if the drop. The IN5820, for example, has a foward drop of
C31BH is put into Power Down during the outage, about 0.35V at lA.
then the ROM can be allowed to die with the AC pow-
er. The considerations here are the same as in Figure 9: Other solutions are to use a transistor or power MOS-
Vee to the ROM is still up at the time Power Down is FET switch, as shown in Figure 13. With minor modifi-
invoked, and we must ensure (through selection of di- cations this switch can be controlled by port pins.
ode Z2 in Figure 12) that the 80C31BH is not awak-
ened till ROM power is back in spec.
10~321
inter AP-252
cations, the 2764's Chip Enable (CE) pin is hardwired
to ground (since it's normally the only program memo~
ry on the bus). This can be done with the CHMOS
VCC1
versions as well, but there is some advantage in con-
necting CE t6 ALE, as shown in Figure 14a. The ad-
vantage is that if the 80C3IBH is put into Idle mode,
since ALE goes to a 1 in that mode, the 27C64 will be
deselected and go into a low current standby mode.
270068-27
The timing waveforms for this configuration are shown
in Figure 14b. In Figure 14b the signals and timing
a. Using a pnp Transistor . parameters in parenthesis are those of the 27C64, and
the others are of the 80C31BH, except Tprop is a pa-
rameter of the address latch. The requirements for tim-
ing compatibility are
TAVIV - Tprop > tACC
TLLlV> tCE
TPLlV> tOE
TPXIZ> tDF
270068-12 If the application is going to use the Power Down mode
b. Using a Power MOSFET then we have another consideration: In Idle, ALE =
PSEN = 1, and in Power Down, ALE = PSEN = o.
Figure 13. Power Switchover Ckts. In a realistic application there are likely to be more
chips in the circuit than are shown in Figure 14, and it
is likely that the nonessential ones will have their Vee
80C31BH + CHMOS EPROM removed while the CPU is in Power Down. In that case
the EPROM and the address latch should be among
The 27C64 and 87C64 are Intel's 8K byte CHMOS the chips that have Vee removed, and logic lows are
EPROMs. The 27C64 requires an external address exactly what are· required at ALE and PSEN.
latch, and .can be used with the 80C31BH as. shown in
Figure 14a. In most 8031 + 2764 (HMOS) appli- But if Vee is going to be maintained to the EPROM
during Power Down, then it will be necessary to· de-
8OC31BH 27C64
~----------~--------~CE
P~EN~----~--~----------~Oi
270068-26
Figure 14a. 80C31BH + 27C64
10-322
inter AP-252
The 87C64 is like the 27C64 except that it has an on-
chip address latch. The Port 0 pins are tied to both
address and data pins of the 87C64, as shown in Figure,
16a. ALE drives the EPROM's ALE/CS input. During
ALE high, the address information is allowed to flow
into the EPROM and begin ;lccessing the code byte. On
the falling edge of ALE the address byte is internally
latched. The AO-A7 inputs are then ignored and the
same bus lines are used to transmit the fetched code
byte from the 00-07 pins back to the 80C3lBH.
The timing waveforms for this configuration are shown
in Figure 16b. In Figure 16b the signals and timing
parameters in parentheses are those of the 87C64, and
the others are of the 80C3lBH. The requirements for
timing compatibility are
270066-13
TLHLL> tLL
Figure 14b. Timing Waveforms for 80C31BH +
27C64 TAVLL> tAL
select the EPROM when the CPU is in Power Down. If TLLAX> tLA
Idle is never invoked, CE of the EPROM can be con- TLLlV> tACL
nected to P2.7 of the 80C3lBH, as shown in Figure
15a. In normal operation, P2.7 will be emitting the TPLlV> tOE
MSB of the Program Counter, which is 0 if the pro-
gram contains less than 32K of code. Then when the TLLPL> tCOE
CPU goes into Power Down, the Port 2 pins emit P2
SFR data, which puts a 1 at P2.7, thus deselecting the TPXIZ> tOHZ
EPROM.
The same considerations apply to the 87C64 as to the
If Idle and Power Down are both going to be used, CE 27C64 with regards to the Idle and Power Down
of the EPROM can be driven by the logical OR of ALE modes. Basically you want CS = 1 if Vee is main-
and P2.7, as shown in Figure 15b. In Idle, ALE = I tained to the EPROM, and CS = OE = 0 if Vee is
will deselect the EPROM, and in Power Down, P2.7 = removed.
1 will deselect it.
SCANNING A KEYBOARD
P2.7 FE
of - - - - - . . . ; . . . . . of There are many different kinds of keyboards, but alpha-
80C31 BH 27C64
numeric keyboards generally consist of a matrix of 8
270068-14 scan lines and 8 receive lines as shown in Figure 17.
a. Power Down Is used but not Idle. Each set of lines connects to one port of the microcon-
troller. The software has written Os to the scan lines,
of
80C31BH
{ALE~ CE
P2.7~ 27~64
_ and Is to the receive lines. Pressing a key connects a
scan line to a receive line, thus pulling the receive line'
270068-15 to a logic low.
b. Idle and Power Down both used.
The 8 receive lines are ANDed to one of the external
Figure 15. Modifications to 80C31BH/27C64 interrupt pins, so that pulling any of the receive lines
Interface low generates an interrupt. The interrupt service rou-
tine has to identify the pressed key, if only one key is
Pulldown resistors are shown in Figure 14a under the down, and convert that information to some useful out-
assumption that something on the bus is going to have put. If more than one key in the line matrix is found to
its Vee removed during Power Down. If this is not the be pressed, no action is taken. (This is a "two key lock-
case, pullups can be used as well as pulldowns. out" scheme.)
10-323
inter AP-252
On some keyboards, certain keys (Shift, Control, Es- terrupt, which terminates the Idle. The interrupt serv-
cape, etc.) are not a part of the line matrix. These keys ice routine would first call a 30 ms (or so) delay to
would connect directly to a port pin on the microcon- debounce the key, and then set about the task of identi-
troller, and would not cause lock-out if pressed simulta- fying which key is down.
neously with a matrix key, nor generate an interrup,t if
pressed singly. First, the current state of the receive lines is latched
into an internal register. If a single key is down, all but
Normally the microcontroller would be in- idle mode one of the lines would be read as Is. Then Os are written
when a key has not been pressed, and another task is to the receive lines and 1s to the scan lines, and the scan
not in progress. Pressing a matrix key generates an in- lines are read. If a single key is down, all but one of
r
10K XI
PO /8 0.-0,
...
8OC31BH 87C64
/8 ArA,
P2
/5 -I ArAI~
ALE FE
PSEN OE
270068-16
Figure 16a. 80C31BH + 87C64
270068-17
Figure 16b. Timing Waveforms for 80C31BH + 87C64
10-324
intJ AP-252
these lines would be read as Is. By locating the single 0 RESPONSE_TO_KEY_CLOSURE:
in each set of lines, the pressed key can be identified. If CALL DEB OUNCE_DELAY
more than one matrix key is down, one or both sets of .MOV LINE, P1; ;See Figure 17.
lines will contain multiple Os. ·CALL SCAN
DJNZ ZERO_COUNTER, REJECT
A subroutine is used to determine which of 8 bits in MOV ADDRESS, ZERO_BIT
either set of lines is 0, and whether more than one bit is MOV P2,#OFFH; ;See Figure 17.
O. Figure 18 shows a subroutine (SCAN) which does MOV P1,#O
that using the 8051 's bit-addressing capability. To use MOV LINE,P2
the subroutine, move the line data into a bit-address- .CALL SCAN
able RAM location named LINE, and call the SCAN DJNZ ZERO_COUNTER, REJECT
routine. The number of LINE bits which are zero is XCH A, ZERO_BIT
returned in ZERO_COUNTER. If only one bit is SWAP A
zero, its number (1 through 8) is returned in ZERO_ ORL ADDRESS,A
BIT. XCH A, ZERO_BIT
MOV P1,#OFFH
The interrupt service routine that is executed in re- MOV P2,#O
sponse to a key closure might then be as follows: REJECT: CLR EXO
RETI
SCAN LINES
rC RECEIVE
LINES
aOCSleH
'-- f----"
- I-------"
)Pl P2
INTO
270068-18
Figure 17. Scanning a Keyboard
10-325
inter AP-252
SCAN: MOV ZERO_COUNTER. 110 ZERO_COUNTER caunts the number of Os in LINE.
JB LINE.O.ONE Tnt LINE bit O.
INC ZERO_COUNTER If LINE. 0 ~ O. incre~ent ZERO_COUNTER
MOV ZERO_BIT. 411 and reco'l'd th.t 1 ine numb.r I t. active.
ONE: JB LINE. I. TWO P1'ocedure continues fa,. other LINE bits.
INC
MOV
ZERO_COUNTER
ZERO_BIT. 412 , Line number 2 is active.
TWO: JB LINE. 2. THREE
INC ZERO_COUNTER
MOV ZERO_BIT. 413 , Line number 3 is active.
THREE: JB LINE. 3. FOUR
INC
MOV
ZERO_COUNTER
ZERO_BIT. 414 , Line number 4 is active.
FOUR: JB LINE.4.FIVE
INC ZERO_COUNTER
MOV ZEROJlIT.4IS Line number 5 is active.
FIVE: JB LINE.5.SIX
INC ZERO_COUNTER
MOV ZERO_BIT.4Ib L.ine number 6 i's active.
SIX: JB LINE. b. SEVEN
INC ZERO_COUNTER
MOV ZERO_BIT. 117 Line number 7 is active.
SEVEN: JB LINE. 7. EIGHT
INC ZER030UNTER
MOV ZERO_BIT.4Ie Line number 8 i'i active.
EIGHT: RET
270068-19
Figure 18. Subroutine SCAN Determines Which of 8 Bits in LINE is Zero
Notice that RESPONSE_TO~EY_CLOSURE For example, with.a 3.58 MHz oscillator frequency, a
does not change the Accumulator, the PSW, nor any of 30 ms delay could be obtained using a preload value of
the registers RO through R7. Neither do SCAN or DE- - 8950, or DDOA, in hex digits.
BOUNCE_DELAY.
In the debounce delay routine (Figure 19), the timer
What we come out with then is a one-byte key address interrupt is enabled'and set to a higher priority than the
(ADDRESS) which identifies the pressed key. The keyboard interrupt, because as we invoke Idle, the key-
key's scan line number is in the upper nibble of AD- board .interrupt is still "in progress". An interrupt of
DRESS, and its receive line number is in the lower the same priority will not be acknowledged, and will
nibble. ADDRESS can be used in a look-up table to not terminate the Idle mode. With the timer interrupt
generate a key code to transmit to a host computer, set to priority 1, while the keyboard interrupt is a prior-
and/or to a display device. ity 0, the timer interrupt, when it occurs, will be ac-
knowledged and will wake up the CPU. The timer in-
The keyboard interrupt itself'must be edge-triggered, terrupt service routine does not itself have to do any-
rather than level-activated, so that the interrupt routine thing. The service routine might be nothing more than
is invoked when a key is pressed, and is not constantly a single RETI instruction. RETI from the timer inter-
being repeated as long as the key is held down. In edge- rupt service routine then returns execution to the de-
triggered mode, the on-chip hardware clears the inter- bounce delay routine, which shuts down the timer and
rupt flag (EXO, in this case) as the service routine is returns execution to the keyboard service routine.
being vectored to. In this application, however, contact
bounce will cause several more edges to occur after the
service routine has been vectored to,· during the DE- DRIVING AN LCD
BOUNCE_DELAY routine. Consequently it is neces-
sary to clear EXO again in software before executing An LCD (Liquid Crystal Display) consists of a back-
RETI. plane arid any number of segments or dots which will
be used to form the image being displayed. Applying a
The debounce delay routine also takes advantage of the voltage (nominally 4 or 5V) between any segment and
Idle mode. In this routine a timer must be preloaded the backplane causes the segment to darken. The only
with a value appropriate to the desired length of delay. catch is that the polarity of the applied voltage has to
This would be be periodically reversed, or else a chemical reac-
. I d (ose kHz) x (delay time ms)
timer pre oa = 12
10-326
inter AP-252
DEBOUNCE_DELAY:
MOV TLI, ..TLI_PRELOAD ; Preload low blJte.
MDV TH1,4tTH1JRELOAD j Preload high byte.
SETB ETI Enable Timer 1 interrupt.
SETB PTt Set TimeT' 1 intel'T"upt to high priority.
SETB TR1 Start timer l'unning.
ORL peON. ttl j Invoke Idle mode.
The next instruction will not be executed until the delay times out.
CLR TRI Stop the timer.
CLR PT1 Back to priority 0 (if desired).
CLR ET1 Disab Ie Timer 1 interrupt (if desired),
RET J Continue keyboard scan.
270068-20
Figure 19. Subroutine DEBOUNCLDELAY Puts the 80C51BH Into Idle During the Delay Time
tion takes place in the LCD which causes deterioration tasks are not requiring servicing. When the timer rolls
and eventual failure of the liquid crystal. over it generates an interrupt, which brings the
80C5IBH out of Idle. The service routine reloads the
To prevent this happening, the backplane and all the timer (for the next rollover), and inverts the logic levels
segments are driven with an AC signal, which is de- of all the pins that are connected to the LCD. It might
rived from a rectangular voltage waveform. If a seg- look like this:
ment is to be "off" it is driven by the same waveform as
the backplane. Thus it is always at backplane potential. LCD_DRIVE_INTERRUPT:
If the segment is to be "on" it is driven with a wave- MOV TL1,#LOW( - XTAL_FREQI
form that is the inverse of the backplane waveform. MOV TH1,#HIGH( - XTAL_FREQI
Thus it has about 5V of periodically changing polarity XRL TENS_DIGIT,#OFFH
between it and the backplane. XRL ONES_DIGIT,#OFFH
RETI
With a little software overhead, the 80C51BH can per-
form this task without the need for additional LCD To update the display, one would use a look-up table to
drivers. The only drawback is that each LCD segment generate the characters. In the table, "on" segments are
uses up one port pin, and the backplane uses one more. represented as Is, and "off" segments as Os. The back-
If more than, say, two 7-segment digits are being driv- plane bit is represented as a O. The quantity to be dis-
en, there aren't many port pins left for other tasks. played is stored in RAM as a BCD value. The look-up
Nevertheless, assuming a given application leaves table operates on the low nibble of the BCD value, and
enough port pins available to support this task, the con- produces the bit pattern that is to be written to either
siderations for driving the LCD are as follows. the ones digit or the tens digit. Before the new patterns
can be written to the LCD, the LCD drive interrupt has
Suppose, for example, it is a 2-digit display with a deci- to be disabled. That is to prevent a polarity reversal
mal point. One port (TENS_DIGIT) connects to the 7 from taking place between the times the two digits are
segments of the tens digit plus the backplane. Another written. An update subroutine is shown in Figure 20.
port (ONES~IGIT) connects to a decimal point plus
.the 7 segments of the ones digit.
USING AN LCD DRIVER
One of the 80C5IBH's timers is used to mark off half-
periods of the drive voltage waveform. The LCD drive As was noted, driving an LCD directly with an
waveform should have a rep rate between 30 and 100 80C51BH uses a lot of port pins. LCD drivers are avail-
Hz, but it's not very critical. A half-period of 12 ms will able in CMOS to interface an 80C5IBH to a 4-digit
set the rep rate to about 42 Hz. The preload/reload display using only 7 of the C5IBH's I/O pins. Basical-
value to get 12 ms to rollover is the 2's complement ly, the C51BH tells the LCD driver what digit is to be
negative of the oscillator frequency in kHz: if the oscil- displayed (4 bits) and what position it is to be displayed
lator frequency is 3.58 MHz, the reload value is in (2 bits), and toggles a Chip Select pin to tell the
- 3580, or F204 in hex digits. driver to latch this information. The LCD driver gener-
ates the display characters (hex digits), and takes care
Now, the 80C51BH would normally be in Idle, to con- of the polarity reversals using its own RC oscillator to
serve power, during the time that the LCD and other generate the timing.
10-327
Ap·252
Figure 25 shows an 80C51BH working with an When the frequency or period measurement is complet-
ICM72llM to drive a 4-digit LCD, and the software ed, the C5IBH wakes itself up for a very short time to
that updates the display. perform a sanity check on the measurement and con-
vert it in software to any scaling of the measured quan-
One could equally well send information to the LCD tity that may be desired. The software conversion can
driver over the bus. In that case, one would set up the include corrections for nonlinearities in the transduc-
Accumulator with the digit select and data input bits, er's transfer function.
and execute a MOVX@ RO,A instruction. The LCD
driver's chip select would be driven by the CPU's WR Resolution is also controlled by software, and can even
signal. This is a little easier in software than the direct be dynamically varied to meet changing needs as a situ-
bit manipulation shown in Figure 21. However, it uses ation becomes more critical. For example, in a process
more I/O pins, unless there is already some external controller you can increase your resolution ("fine tune"
memory involved. In that case, no extra pins are used the control, as it were) as the process approaches its
up by adding the LCD driver to the bus. target.
The nominal reference frequency of the output signal
RESONANT TRANSDUCERS from these devices is in the range of 20 Hz to 500 kHz,
depending on the design. Transducers are available that
Analog transducers are often used to convert the value have a full scale frequency shift 2 to 1. The transducer
.of a physical property, such as temperature, pressure, operates from a supply voltage range of 3V to 20V,
etc., to an analog voltage. These kinds of transducers which means it can operate from the same supply volt-
then require an analog-to-digital converter to put the age as the 80C51BH. At 5V, the transducer draws less
measurement into a form that is compatible with a digi- than 5 rnA (Reference 7). It can normally be connected
tal control system. Another kind of transducer is now directly to one of the C5IBH's port pins, as shown in
becoming available that encodes the value of the physi- Figure 22.
cal property into a signal that can be directly read by a
digital control system. These devices are called reso-
nant transducers. FREQUENCY MEASUREMENTS
Resonant transducers are oscillators whose frequency Measuring a frequency .means counting pulses for a
depends in a known way on the physical property being known sample time. Two timer/counters can be used,
IIleasured. These devices output a train of rectangular one to mark off the sample time and one to count puls-
pulses whose repetition rate encodes the value of the es. If the frequency being counted doesn't exceed 50
quantity being measured. The pulses can in most cases kHz or so, one may equally well connect the transducer
be fed directly into the 80C51BH,which then measures signal to one of the external interrupt pins, and count
either the frequency or period of the incoming signal, pulses in software. That frees up one timer, with very
basing the measurement on the accuracy of its own little cost in CPU time.
clock oscillator. The 80C51BH can even do.this in its
sleep; that is, in Idle. The count that is directly obtained is TxF, where T is
the sample time and F is the frequency. The full scale
UPDATE_LCD:
CLR ETl Disable LCD drive interrupt.
MOV DPTR. !lTABLE_ADDRESS Look-up table begins at TABL.E_ADDRESS
MOV A. BCD_VALUE Digits to be ,displayed.
SWAP A Move tens digit to low nibble.
ANL A.!lOFH Mask off high nibble.
MOVC A.C!!A+DPTR Tens digit pattl'r" to accumulator:
MOV TENS_DIGIT. A Update LCD tens digit.
MOV A. BCD_VALUE Digits to be displayed.
ANL A,4tOFH Mask off tens digit.
MOVC A,@A+DPTR Ones digit pattern to accum'ulator.
MOV C. DECIMAL_POINT Add 'dec 1mal point to segment
MOV ACC.7.C pattern. Update LCD decimal point
MOV ONES_DIGIT. A and ones di"git.
SETB ETl Re-enable LCD drive inteT'T'upt.
RET
270068-21
Figure 20. UPDATE_LCD Routine Writes Two Digits to an LCD
10-328
AP-252
range is Tx(Fmax-Fmin). For n-bit resolution For example, 8-bit resolution in the measurement of a
frequency that varies between 7 kHz and 9 kHz would
1 LSB = Tx(Fmax-Fmin) require, according to this formula; a sample time of 128
2" ms. The maximum acceptable frequency count would
be 128 ms X 9 kHz = 1152 counts. The minimum
Therefore the sample time required for n-bit resolution would be 896 counts. Subtracting 896 from each fre-
is quency count (or presetting the frequency counter to
- 896 = OFC80H) would allow the frequency to be
2" reported on a scale of 0 to FF in hex digits.
T = ::---=-=,---,--
Fmax-Fmin
BOC51BH
1 ) DIGIT )
{
2 SELECT
,.,
PORT
M}
B1
B2
DATA
INPUT
-v
)
L.
C.
D.
B3 v
"-
cs v
270068-22
Figure 21a. Using an LCD Driver
UPDATE_LCD:
MOV A. DISPLAY _HI High byte of 4-digit display.
SETB DIGIT _SELECT _2 Select leftmost digit of LCD,
SETB DIGIT SELECT 1 (Digit address = lIB.)
CALL SHIFT -AND LOAD High nibble of high byte to selected digit
CLR DIGIT:=SELECT_1 Select second digit of LCD (address = lOB)
CALL SHIFT _AND_LOAD Low nibble of high byte to selected digit.
MOV A. DISPLAY LO Low byte of 4-digit display.
CLR DIGIT _SELECT_2 Select third digit of LCD.
SETB DIGIT _SELECT_1 (Digit address = DIE. 1
CALL SHIFT _AND_LOAD Hlgh nibble of low byte to selected digit.
CLR DIGIT _SELECT_1 Select fourth digit (address = OOBl.
CALL SHIFT_AND_LOAD Low nibble of low byte to selected digit.
RET
SHIFT _AND_LOAD:
RLC A MSB to carry bit (CY>
MOV DATA INPUT _B3. C CY to Oata Input pin B3.
RLC A Next bit to CY.
MOIJ DATA WPUT_B2. C CY to Oata Input pin B2.
RLC A
- Next bit to CV
DATA INPUT _E 1, C CV to Data Input pln 81.
MOV
RLC A
- Last bit to CV.
MOV DATA_INPUT_BO.C CV to Data Input pin eo.
CLR CHIP _SELECT Toggle Chip Select.
SETB CHIP _SELECT O-to-1 transition latches info.
RET
270068-23
Figure 21b. UPDATE_LCD Routine Writes 4 Digits to an LCD Driver
10-329
inter AP-252
At this point the value of the frequency of the transduc-
VCC er signal, measured to 8 bit resolution, is contained in
FREQUENCY. Note that the timer can be reloaded on
the fly. Note too that the timer can be reloaded on the
fly. Note too that for 8·bit resolution only the low byte
VCC of the frequency counter needs to be read, since the
80CS1BH high byte is necessarily O. However, one may want to
RESONANT INTO test the high byte to ensure that it is zero, as a sanity
TRANSDUCER 1-----1 OR check on the data. Both bytes, of course must be re-
TO
loaded.
VSS
PERIOD MEASUREMENTS
270068-24 Measuring the period of the transducer signal means
measuring the total elapsed time over a known number,
Figure 22. Resonant Transducer Does Not N, of transducer pulses. The quantity that is directly
Require an AID Converter measured is NT, where T is the period of the transduc-
er signal in machine cycles. The relationship between T
To implement the measurement, one timer is used to in machine cycles and the transducer frequency F in
establish the sample time. The timer is preset to a value arbitrary frequency units is
that causes it to roll over at the end of the sample time,
generating an interrupt and waking the CPU from its Fxtal
Idle mode. The required preset value is the 2's comple· T = -F- x (1/12).
ment negative of the sample time measured in machine
cycles. The conversion from sample time to machine where Fxtal is the SOCS IBH clock frequency, in the
cycles is to multiply it by 1/12 the clock frequency. For same units as F.
example, if the cloqk frequency is 12 MHz, then a sam-
ple time of 128 ms is The full scale range then is Nx (Tmax-Tmin). For
n-bit resolution.
(128 ms) x (12000 kHz)/12 = 128000 machine cycles.
1 LSB = Ns(Tmax-Tmin).
Then the required preset value to cause the timer to roll 2n
over in 128 ms is '
Therefore the number of periods over which the elapsed
- 128000 = FEOCOO, in hex digits.
time should be measured is
Note that the preset value is 3 bytes wide whereas the 2n
timer is only 2 bytes wide. This means the timer must N = =T-m-ax-.=Tm---:-in
be augmented in software in the timer interrupt routine
to three bytes. The SOCS IBH has a DJNZ instruction
However, N must also be an integer. It is logical to
(decrement and jump if not zero) that makes it easier to
evaluate the above formula (don't forget Tmax and
code the third timer byte to count down instead of up.
Tmin have to be in machine cycles) and select for N the
If the third timer byte counts down, its reload value is
next higher integer. This selection gives a period mea-
the 2's complement of what it would be for an up-coun-
surement that has somewhat more than n-bit resolu-
ter. For example, if the 2's complement of the sample
tion, but it can be scaled back if desired.
time is FEOCOO, then the reload value for the third
timer byte would be 02, instead of FE. The timer inter-
For example, suppose we want 8-bit resolution in the
rupt routine might then be:
measurement of the period of a signal whose frequency
varies from 7.1 kHz to 9 ~Hz. If the clock frequency is
TIMER_INTERRUPT_ROUTINE:
12 MHz, then Tmax is (12000 kHz/1.1 kHz) x (1/12)
DNJZ THIRD_TIMER_BYTE,OUT
= 141 machine cycles. Tmin is 111 machine cycles.
MOV TLO,#O
The required value for N, then, is 256/(141-111) =
MOV THO,#OCH
8.53 periods, according to the formula. Using N = 9
MOV THIRD_TIMERBYTE,#2
periods will give a maximum NT value of 141 x 9 =
MOV FREQUENCY,COUNTER_LO
1269 machine cycles. The minimum NT will be III X
;Preset COUNTER to -896:
9 = 999 machine cycles. A lookup table can be used to
MOV COUNTER_LO,#80H
MOV COUNTER_HI,#OFCH
OUT: RETI
10·330
intJ AP-252
scale these values back to a range of 0 to 255, giving ADDC A,NT_HI
precisely the 8-bit resolution desired. MOV DPH,A
CLR A
To implement the measurement, one timer is used to MOVC A,@A+DTPR
measure the elapsed time, NT. The transducer is con- MOV PERIOD,A
nected to one of the external interrupt pins, and this POP PSW
interrupt is configured to the transition-activated mode. POP ACC
In the transition-activated mode every I-to-O transition RET
in the transducer output will generate an interrupt. The
interrupt routine counts transducer pulses, and when it At this point the value of the period of the transducer
gets to the predetermined N, it reads and clears the signal, measured to 8 bit resolution, is contained in PE-
timer. For the specific example cited above, the inter- RIOD.
rupt routine might be:
INTERRUPT_RESPONSE: PULSE WIDTH MEASUREMENTS
DJNZ N,OUT
MOV N,#9 The 80C5lBH timers have an operating mode which is
CLR EA particularly suited to pulse width measurements, and
CLR TRI will be useful in these applications if the transducer
MOV NT_LO,TLI signal has a fixed duty cycle.
MOV NT_HI,THI
MOV TLl,#9 In this mode the timer is turned on by the on-chip
MOV THl,#O circuitry in response to an input high at the external
SETB TRI interrupt pin, and offby an input low, and it can do this
SETB EA while the 80C51BH is in Idle. (The "GATE" mode of
CALL LOOKUP_TABLE timer operation is described in the Intel Microcontrol-
OUT: RETI ler Handbook.) The external interrupt itself can be en-
abled, so the same I-to-O transition from the transducer
In this routine a pulse counter N is decremented from that turns off the timer also generates an interrupt. The
its preset value, 9, to zero. When the counter gets to interrupt routine then reads and resets the timer.
zero it is reloaded to 9. Then all interrupts are blocked
for a short time while the timer is read and cleared. The The advantage of this method is that the transducer
timer is stopped during the read and clear operations, signal has direct access to the timer gate, with the result
so "clearing" it actually means presetting it to 9, to that variations in interrupt response time have no effect
make up for the 9 machine cycles that are missed while on the measurement.
the timer is stopped.
Resonant transducers that are designed to fully exploit
The subroutine LOOKUP_TABLE is used to scale the GATE mode have an internal divide-by-N circuit
the measurement back to the desired 8-bit resolution. It that fixes the duty cycle at 50% and lowers the output
can also include built-in corrections for errors or non- frequency to the range of 250 to 500 Hz (to control
linearities in the transducer's transfer function. RFI). The transfer function between transducer period
and measurand is approximately linear, with known
The subroutine uses the MOVC A, @ A + DPTR and repeatable error functions.
instruction to access the table, which contains 270 en-
tries commencing at the 16-bit address referred to as
TABLE. The subroutine must compute the address of HMOS/CHMOS Interchangeability
the table entry that corresponds to the measured value
of NT. This address is The CHMOS version of the 8051 is architecturally
identical with the HMOS version, but there are never-
DPTR = TABL + NT - NTMIN, theless some important differences between them which
the designer should be aware of. In .addition, some ap-
where NTMIN = 999, in this specific example. plications require interchangeability between .HMOS
and CHMOS parts. The differences that need to be con-
LOOKUP_TABLE: sidered are as follows:
PUSH ACC
PUSH PSW External Clock Drive: To drive the HMOS 8051 with
MOV A,#LOWCTABLE-NTMINI an external clock signal, one normally grounds the
ADD A,NT_LO XTALI pin and drives the XTAL2 pin. To drive the
MOV DPL,A ,CHMOS 8051 with an external clock signal, one must
MOV A,#HIGHCTABLE-NMTINI drive the XTALl pin and leave the XTAL2 pin uncon-
nected. The reason for the difference is that in the
10-331
AP-252
HMOS 8051, it is the XTAL2 pin that drives the inter-
nal clocking circuits, whereas in the CHMOS version it
is the XTALI pin that drives the internal clocking cir-
cuits. HMOS
There are several ways to design an external clock drive
to work with both types. For low clock frequencies (be-
low 6 MHz), the HMOS 8051 can be driven in the same
way as the CHMOS version, namely, throu~h XTA~I
with XTAL2 unconnected. Another way IS to dnve
270068-25
both XTALI and XTAL2; that is, drive XTALI and
use and external inverter to derive from XTALI a sig- Figure 23. O-to-1 Transition Shows Unspec'd
nal with which to drive XT AL2.
Delay (At) in HMOS to 74HC Logic
In either case, a 74HC or 74HCT circuit makes an ex-
wishes to preserve the capability of interchanging
cellent driver for XTALI and/or XTAL2, because nei- HMOS and CHMOS 8051s the software has to be de-
ther the HMOS nor the CHMOS XTAL pins have
signed so that the HMOS parts will respond in an ac-
TTL-like input logic levels.
ceptable manner when a CHMOS reduced power mode
is invoked. '
Unused Pins: Unused pins of Ports I, 2 and 3 can be
ignored in both HMOS and CHMOS designs. The in-
For example, an instruction that invokes Power Down
ternal pullups will put them into a defined state. Un-
can be followed by a "JMP $":
used Port 0 pins in 8051 applications can be ignored,
even if they're floating. But in 80C5IBH applications,
CLR EA
these pins should not be left afloat. They can be exter-
ORL PCON.#2
nally pulled up or down, or they can be internally
pulled down by writing Os to them.
JMP $
The CHMOS and HMOS parts will respond to this
8031180C3IBH designs mayor may not need pullups sequence of code differently. The CHMOS part: going
on Port O. Pullups aren't needed for program fetches,
into a normal CHMOS Power Down Mode, w!ll stop
because in bus operations the pins are actively pulled fetching instructions until it gets a hardware reset. The
high or low by either the 8031 or the external program
HMOS part. will go through the motions of executing
memory. But they are needed for the CHMOS part if
the ORL instruction, and then fetch the JMP instruc-
the Idle or Power Down mode is invoked, because in tion. It will continue fetching and executing JMP $ un-
these modes Port 0 floats. til hardware reset.
Logic Levels: If Vee is between 4.5V and 5.5V, an Maintaining HMOS/CHMOS 8051 interchangeability
input signal that meets the HMOS 8051's input logic
in response to Idle requires more planning. The HMOS
levels will also meet the CHMOS 80C5IBH's input log-
part will not respond to the instruction that puts the
ic levels (except for XTALl/XTAL2 and RST). For
CHMOS part into Idle, so that instruction needs.to.be
the same Vee condition, the CHMOS device will reach
followed by a software idle. This would be an 'Idlmg
or surpass the output logic levels of the HMOS device. loop which would be terminated by the same conditions
The HMOS device will not necessarily reach the output
that would terminate the CHMOS's hardware Idle.
logic levels of the CHMOS device. T~is is an impor~~nt Then when the CHMOS device goes into Idle, the
consideration if HMOS/CHMOS mterchangeablhty
HMOS version executes the idling loop, until either a
must be maintained in an otherwise CMOS system.
hardware reset or an enabled interrupt is received. Now
if Idle is terminated by an interrupt, execution for the
HMOS 8051 outputs that have internal pullups (Ports CHMOS device will proceed after RETI from the in-
1,2, and 3) "typically" reach 4V or more ifiOH i~ zero, struction following the one that invoked Idle. The in-
but not fast enough to meet timing specs. Addmg an struction following the one that invoked Idle is the
external pullup resistor will ensure the logic level, but
idling loop that was inserted for the HMOS device. At
still not the timing, as shown in Figure 23. If timing is
this point, both the HMOS and CHMC?S devices ~ust
an issue, the best way to interface HMOS to CMOS is
be able to fall through the loop to contmue execution.
through a 74HCT circuit.
Idle and Power Down: The Idle and Power Down
modes exist only on the CHMOS devices, but if one
10-332
AP-252
One way to achieve the desired effect is to define a REFERENCES
"fake" Idle flag, and set it just before going into Idle. 1. Pawlowski, Moroyan, Alnether, "Inside CMOS'
The instruction that invoked Idle is followed by a soft- Technology," BYTE magazine, Sept., 1983. Avail-
ware idle: able as Article Reprint AR-302.
SETB IDLE 2. Kokkonen, Pashley, "Modular Approach to C-MOS
ORL PCON,#l Technology Tailors Process to Application,"
JB IDLE, $ Electronics, May, 1984. Available as Article Reprint
AR-332.
Now the interrupt that terminates the CHMOS's Idle 3. Williamson, T., Designing Microcontroller Systems
must also break the software idle. It does so by clearing for Electrically Noisy Environments. Intel Applica-
the "Idle" bit: tion Note AP-125, Feb. 1982.
4. Williamson, T., "PC Layout Techniques for Mini-
mizing Noise," Mini-Micro Southeast. Session 9,
CLR IDLE
Jan., 1984.
RETI
5. Alnether, J., High Speed Memory System Design Us-
Note too that the PCON register in the HMOS 8051 ing 2147H. Intel Application Note AP-74. March
contains only one bit, SMOD, whereas the PCON reg- 1980.
ister in CHMOS contains SMOD plus four other bits. 6. Ott, H., "Digital Circuit Grounding and Intercon-
Two of those other bits are general purpose flags. Main- nection," Proceedings of the IEEE Symposium on
taining HMOS/CHMOS interchangeability requires Electromagnetic Compatibility. pp. 292-297, Aug.
that these flags not be used. 1981.
7. Digital Sensors by Technar. Technar Inc., 205 North
2nd Ave.,-Arcadia, CA 91006.
10-333
APPLICATION AP-281
NOTE
July 1986
UPI-4S2 Accelerates iAPX 286
Bus Performance
CHRISTOPHER SCOTT
TECHNICAL MARKETING ENGINEER
INTEL CORPORATION
Order Number: 292018-001
10-334
AP·281
INTRODUCTION HOST·UPI·452 FIFO SLAVE
The UPI-452 targets the leading problem in peripheral INTERFACE
to host interfacing, the interface of a slow peripheral The UPI-452 FIFO acts as a buffer between the exter-
with a fast Host or "bus utilization". The solution is nal Host 80286 and the internal CPU. The FIFO allows
data buffering to reduce the delay and overhead of the Host - peripheral interface to achieve maximum de-
transferring data between the Host microprocessor and coupling of the interface. Each of the two FIFO chan-
I/O subsystem. The Intel CMOS UPI-452 solves this nels is fully user programmable. The FIFO buffer en-
problem by combining a sophisticated programmable sures that the respective CPU, Host or internal CPU,
FIFO buffer and a slave interface with an MSC-51 receives data in the same order as transmitted. Three
based microcontroller. slave bus interface handshake methods are supported
The UPI-452 is Intel's newest Universal Peripheral In- by the UPI-452; DMA, Interrupt and Polled.
terface family member. The UPI-452 FIFO buffer en-
ables Host-peripheral communications to be through The interface between the Host 80286 and the UPI-452
streams or bursts of data rather than by individual is accomplished with a minimum of signals. The 8 bit
bytes. In addition the FIFO provides a means of em- data bus plus READ, WRITE, CS, and AO-2 provide
bedding cpmmands within a stream or block of data. access to all of the externally addressable UPI-452 reg-
This enables the system designer to manage data and isters including the two FIFO channels. Interrupt and
commands to further off-load the Host. DMA handshaking pins are tied directly to the inter-
rupt controller and DMA controller respectively.
The UPI-452 interfaces to the iAPX 286 microproces-
sor as a standard Intel slave peripheral device. READ, DMA transfers between the Host and UPI-452 are con-
WRITE, CS and address lines from the Host are used trolled by the Host processors DMA controller. In the
to access all of the Host addressable UPI-452 Special example shown in Figure I, the Host DMA controller
Function Registers (SFR). is the 82258 Advanced DMA Controller. An internal
DMA transfer to or from the FIFO, as well as between
The UPI-452 combines an MSC-51 microcontroller, other internal elements, is controlled by the UPI-452
with 256 bytes. of on-chip RAM and 8K bytes of internal DMA processor. The internal DMA processor
EPROM/ROM, twice that of the SOC5l, a two channel can also transfer data between Input and Output FIFO
DMA controller and a sophisticated 128 byte, two channels directly. The description that follows details
channel, bidirectional FIFO in a single device. The the UPI-452 interface from both the Host processor's
UPI-452 retains all of the 80C5l architecture, and is and the UPI-452's internal CPU perspective.
fully compatible with the MSC-5.1 instruction set.
One of the unique features of the UPI-452 FIFO is its
This application note is a description of an iAPX 286 to ability to distinguish between commands and data em-
UPI-452 slave interface. Included is a discussion of the bedded in the same data block. Both interrupts and
respective timings and design considerations. This ap- status flags are provided to support this operation in
plication note is meant as a supplement to the UPI-452 either direction of data transfer. These flags and inter-
Advance Data Sheet. The user should consult the data rupts are triggered by the FIFO logic independent of,
sheet for addi·tional details on the various UPI-452 and transparent to either the Host or internal CPUs;
functions and features. Commands embedded in the data block, or stream, are
called Data Stream Commands. 0
UPI·452 iAPX 286 SYSTEM Programmable FIFO channel Thr~sholds are another
CONFIGURATION unique feature of the UPI-452. The Thresholds provide
for interrupting the Host only when the Threshold
The interface described in this application note is number of bytes can be read or written to the FIFO
shown in Figure I, iAPX 286 UPI-452 System Block
buffer. This further decouples the Host UPI-452 inter"
Diagram. The iAPX 286 system is configured in a local face by relieving the Host of polling the buffer to deter-
bus architecture design. DMA between the Host and mine the number of bytes that can be read or written. It
the UPI-452 is supported by the 82258 Advanced also red \Ices the chances of overrun and underrun er-
DMA Controller. The Host microprocessor accesses all rors which must be processed.
UPI-452 externally addressable registers through ad-
o dress decoding (see Table 3, UPI-452 External Address The UPI-452 also provides a means of bypassing the
Decoding). The timings and interface descriptions be- FIFO, in both directions, for an immediate interrupt of
low are given in equation form with examples of specif- either the Host or internal CPU. These commands are
ic calculations. The goal of this application note is a set called Immediate Commands. A complete description
of interface analysis equations. These equations are the of the internal FIFO logic operation is given in the
tools a system designer can use to fully utilize the fea- FIFO Data Structure section.
tures of the UPI-452 to achieve maximum system per-
formance.
10-335
l
- PCLK
READY
CLK
RST
h
r°'-'
MRDC
MWRC
WAIT
STATE ~
X2 XI -
10RC
10WC
h GENERATOR
~ MRDC
50,51
M/iO II MWRC
:!II
ID
RE' . E T t l
RES READY
50,51 DEN
READY DT/R I •
...
C
CD
1 CLK
RESET
PCLK
-
-
CLK
82288
ALE
INTA
I ADDRESS
"
RAM/EPROM
cs
-
:'" I II I •
.
DECODE
~ 82284 LOGIC ,...., ~
_rD~
"U
>< l ......
~
RESET PORTO
-I/o PORTS
~
I\) RST
III
aI ~~ READ PORTI OR
-LOCAL
~..
- Milo WRITE
I:: EXPANSION
....
0
c.,
:!!
J,.
en
80286
.£t
STB
OE
-
.,....-- P CS
AO-A2
PORT2
PORT3
BUS
-ALTERNATE
FUNCTIONS .
»
."
t.) I\)
en
AI5-AO -- LATCH PORT4
N
....
Q)
-
Ol BHE
UPI-452
'<
III HLD/ IN~
HLDA DO-DI5
DACK I-
CD DRQIN/
3 INTRQIN
~
UI DRQOUT!
0- TRAN5CEIVER INTRQOUT
n
;0;-
C ""! LL"[I ~ OE
00-07
...s-i
INTRQ
bk:
SO,S I HLDA DO
iii' ........ READY EN
ID ' - - ........ CL~ AI5-AO,,_
iii ...... M/IO
0!CS
3 RO
ViR IRO
82258
OMA
AO-Al IRI f+-1
INTA IR2
INT
8259A
ORQO
ORQl
~
OACK 0,1
292018-1
AP-281
UPI-4S2 INITIALIZATION Host read/write access of the FIFO. The internal CPU
sets the Slave Control (SLCON) SFR FIFO DMA
The UPI-4S2 at power-on reset automatically performs Freeze/Normal Mode (FRZ) bit high (= 1) to activate
a minimum initialization of itself. The UPI-4S2 notifies Normal Mode. Ths causes the Slave Status (SSTAT)
the Host that it is in the process of initialization by and Host Status (HSTAT) SFR FIFO DMA Freeze
setting a Host Status SFR bit. The user UPI-4S2 pro- Mode bits to be set to Normal Mode. Table 2, UPI-4S2
gram must release the UPI-4S2 from initialization for Initialization Event Sequence Example, shows a sum-
the FIFO to be accessible by the Host. This is the mini- mary of the initialization events described above.
mum Host to UPI-4S2 initialization sequence. All fur-
ther initialization and configuration of the UPI-4S2, in- Table 1. FIFO SpeCial Function
cluding the FIFO, is done by the internal CPU under Register Default Values
user program control. No interaction or programming
Reset
is required by the Host 80286 for UPI-4S2 initializa- SFR Name Label
Value
tion.
Channel Boundary Pointer CBP 40H/640
At power-on reset the UPI-4S2 automatically enters Output Channel Read Pointer ORPR 40H/640
Output Channel Write Pointer OWPR 40H/640
FIFO DMA Freeze Mode by resetting the Slave Con-
Input Channel Read Pointer IRPR OOH/DO
trol (SLCON) SFR FIFO DMA Freeze/Normal Mode Input Channel Write Pointer IWPR DOH/OO
bit to FIFO DMA Freeze Mode (FRZ = "0"). This Input Threshold ITH DOH/OO
forces the Slave Status (SSTAT) and Host Status Output Threshold OTH 01 H/1 0
(HSTAT) SFR FIFO DMA Freeze/Normal Mode bits
to FIFO DMA Freeze Mode In Progress. FIFO DMA Table 2. UPI-452 Initialization
Freeze Mode allows the FIFO interface to be config- Event Sequence Example
ured, by the internal CPU, while inhibiting Host access
Event Description SFR/bit
to the FIFO.
Power-on Reset
The MODE SFR is forced to zero at reset. This dis- UPI-4S2 forces FIFO OMA SLCON FRZ = 0
ables, (tri-states) the DRQIN/INTRQIN, DRQOUT/ Freeze Mode (Host access to
INTRQOUT and INTRQ output pins. INTRQ is in- FIFO inhibited)
hibited from going active to reflect the fact that a 'Host UPI-4S2 forces Slave Status and SSTAT SSTS = 0
Status SFR bit, FIFO DMA Freeze Mode, is active. If Host Status SFR to FIFO OMA HSTAT HST1 = 1
the MODE SFR INTRQ configure bit is enabled Freeze Mode In Progress
(= 'I '), before the Slave Control and Host Status SFR
FIFO DMA Freeze/Normal Mode bit is set to Normal UPI-4S2 forces all SFRs,
Mode, INTRQ will go active immediately. including FIFO SFRs, to default
values.
The first action by the Host following reset is to read • UPI-4S2 user program enables MOOEM04 = 1
the UPI-4S2 Host Status SFR Freeze/Normal Mode INTRa, INTRa goes active, high
bit to determine the status of the interface. This may be • Host READ's UPI-4S2 Host
done in response to a UPI-4S2 INTRQ interrupt, or by Status (HSTAT) SFR to
polling the Host Status SFR. Reading the Host Status determine interrupt source,
SFR resets the INTRQ line low. INTRa goes low
Any of the five FIFO interface SFRs, as well as a vari- • UPI-4S2 user program initializes
ety of additional features, may be programmed by the any other SFRs; FIFO, Interrupts,
internal CPU following reset. At power-on reset, the Timers/Counters, etc.
five FIFO Special Function Registers are set to their User program sets Slave Control SLCON FRZ = 1
default values as listed in Table 1. All reserved location SFR to Normal Mode (Host
bits are set to one, all other bits are set to zero in these access to FIFO enabled)
three SFRs. The FIFO SFRs listed in Table I can be UPI-4S2 forces Slave and Host SSTAT SST5 = 1
programmed only while the UPI-4S2 is in FIFO DMA Status $FRs bits to Normal HSTAT HST1 = 0
Freeze Mode. The balance of the UPI-4S2 SFRs default Operation
values and descriptions are listed in the UPI-4S2 Ad-
• Host polls Host Status SFR to
vance Data Sheet in the Intel Microsystems Compo- determine when it can access the
nent Handbook Volume II and Microcontroller Hand- FIFO
book. -or-
• Host waits for UPI-4S2 Request
The above sequence is the minimum UPI-4S2 internal for Service interrupt to access
initialization required. The last initialization instruction
FIFO
must always set the UPI-4S2 to Normal Mode. This
causes the UPI-4S2 to exit Freeze Mode and enables • user option
10-337
AP-281
FIFO DATA STRUCTURES Commands can be used to structure or dispatch the
data by defining the start and end of data blocks or
packets, or how the data following a DSC is to be pro-
Overview cessed.
The UPI-4S2 provides three means of communication A Data Stream Command (DSC) acts as an internal
between the Host microprocessor and the UPI-4S2 in service routine vector. The DSC generates an interrupt
either direction; to a service routine which reads the DSC. The DSC
byte acts as an address vector to a user defined service
Data routine. The address can be any program or data mem-
Data Stream Commands ory location with no restriction on the number of DSCs
Immediate Commands or address boundaries.
Data and Data Stream Commands (DSC) are trans- A Data Stream Command (DSC) can also be used to
ferred between the Host and UPI-4S2 through the UPI- clear data from the FIFO or "FLUSH" the FIFO. This
4S2 FIFO buffer. The third, Immediate Commands, is done by appending a DSC to the end of a block of
provides a means of bypassing the FIFO entirely. These data entered in the FIFO which is less than the pro-
three data types are in addition to direct access by ei- grammed threshold number of bytes. The DSC will
ther Host or Internal CPU of dedicated Status and cause an interrupt, if enabled, to the respective receiv-
Control Special Function Registers (SFR). ing CPU. This ensures that a less than Thresholdnum-
ber of bytes in the FIFO will be read. Two conditions
The FIFO appears to both the Host 80286 and the in- force a Request for Service interrupt, if enabled, to the
ternal CPU as 8 bits wide. Internally the FIFO is logi- Host. The first is due to a Threshold number of bytes
cally nine bits wide. The ninth bit indicates whether the having been written to the FIFO Output channel; the
byte is a data or a Data Stream Command (DSC) byte; second is if a DSC is written to the Output FIFO chan-
o = data, 1 = DSC. The ninth bit is set by the FIFO nel. Ifiess than the Threshold number of bytes are writ-
logic in response to the address specified when writing ten to the Output FIFO channel, the Host Status SFR
to the FIFO by either Host or internal CPU. The FIFO flag will not be set, and a Request for Service interrupt
uses the ninth bit to condition the UPI-4S2 interrupts will not be generated, if enabled. By appending a DSC
and status flags as a byte is made available for a Host or to end of the data block, the FIFO Request for Service
internal CPU read from the FIFO. Figures 2 and 3 flag and/or interrupt will be generated.
show the structure of each FIFO channel and the logi-
cal ninth bit. An example of a FIFO Flush application is a mass stor-
age subsystem. The UPI-4S2 provides the system inter-
It is important to note that both data and DSCs are face to a subsystem which supports tape and disk stor-
actually entered into the FIFO buffer (see Figures 2 age. The FIFO size is dynamically changed to provide
and 3). External addressing of the FIFO determines the the maximum buffer size for the direction of transfer.
state ofthe internal FIFO logic ninth bit. Tabie 3 shows Large data blocks are the norm in this application. The
the UPI-4S2 External Address Decoding used by the FIFO Flush provides a means of purging the FIFO of
Host and the corresponding action. The internal CPU the last bytes of a transfer. This guarantees that the
interface to the FIFO is essentially identical to the ex- block, no matter what its size, will be transmitted out of
ternal Host interface. Dedicated internal Special Func- the FIFO.
tion Registers provide the interface between the FIFO,
internal CPU and the internal two channel DMA proc- Immediate Commands allow more direct communica-
essor. FIFO read and write operations by the Host and tion between the Host processor and the UPI-4S2 by
internal CPU are interleaved by the UPI-4S2 so they bypassing the FIFO in either direction. The Immediate
appear to be occurring simultaneously. Command IN and OUT SFRs are two more unique
address locations externally and internally addressable.
The ninth bit provides a means of supporting two data Both DSCs and Immediate Commands have internal
types within the FIFO buffer. This feature enables the interrupts and interrupt priorities associated with their
Host and UPI-4S2 to transfer both commands and data operation. The interrupts are enabled or disabled by
while maintaining the decoupled interface a FIFO buff- setting corresponding bits in the Slave Control
. er provides. The logical ninth bit provides both a means (SLCON), Interrupt Enable (IEC), Interrupt Priority
of embedding commands within a block of data and a (IPC) and Interrupt Enable and Priority (IEP) SFRs. A
means for the internal CPU, or external Host, to dis- detailed description of each of these may be found in
criminate between data and commands. Data or DSCs the UPI-4S2 Advance Information Data Sheet.
may be written in any order desired. Data Stream
10-338
AP-281
o
i3
g
..J
o
a::
9TH I-
z
INPUT o
FIFO
o
B
I CHANNEL '-
T
INTERNAL CPU
(DATA PROCESSOR)
292018-2
Figure 2. Input FIFO Channel Functional Diagram
10-339
intJ AP-281
o
§
...J
o
9TH e:z
OUTPUT
B rlFO 8
I
T
CHANNEL
"....
01----------......
§
o
~I¢:==:~
;;:
INTERNAL CPU
(DATA PROCESSOR)
292018-3
Figure 3. Output FIFO Channel Functional Diagram
10-340
AP-281
Table 3. UPI-452 External Address Decoding
DACK CS A2 A1 AD READ WRITE
1 1 X X X No Operation No Operation
1 0 0 0 0 Data or DMA from Data or DMA to
Output FIFO Channel Input FIFO Channel
1 0 0 0 1 Data Stream Command Data Stream Command
from Output FIFO to Input FIFO
Channel Channel
1 0 0 1 0 Host Status SFR Reserved
Read
1 0 0 1 1 Host Control SFR Host Control SFR
Read Write
1 0 1 0 0 Immediate Command Immediate Command
SFR Read SFRWrite
1 0 1 1 X Reserved Reserved
0 X X X X DMA Data from DMA Data to Input
Output FIFO Channel FIFO Channel
Below is a detailed description of each FIFO channel's UPI-4S2 Internal Write to the FIFO
operation, including the FIFO logic response to the
ninth bit, as a byte moves through the channel. The The internal CPU writes data and Data Stream Com-
description covers each of the three data types for each mands into the FIFO through the FIFO OUT (FOUT)
channel. The details below provide a picture of the vari- and Command OUT (COUT) SFRs. Wh,~n a Thresh-
ous FIFO features and operation. By understanding the old number of bytes has been written, the Host Status
FIFO structure and operation the user can optimize the SFR Output FIFO Request for Service bit is set and an
interface to meet the requirements of an individual de- interrupt, if enabled, is generated to the Host. Either
sign. the INTRQ or DRQOUT/INTRQOUT output pins
can be used for this interrupt as determined by the
MODE and Host Control (HCON) SFR setting. The
OUTPUT CHANNEL Host responds to the Request for Service interrupt by
reading the Host Status (HSTAT) SFR to determine
This section covers the data path from the internal the source of the interrupt. The Host then reads the
CPU to the HOST. Data Stream Command or Immedi- Threshold number of bytes from the FIFO. The inter-
ate Command processing during ,Host DMA Opera- nal CPU may continue to write to the FIFO during the
tions is covered in the DMA section. Host read of the FIFO Output channel.
10-341
AP-281
Data Stream Commands may be written to the Output The most efficient Host read operation of the FIFO
FIFO channel at any time during a write of data bytes. Output channel is through the use of Host DMA. The
The write instruction need only specify the Command UPI-452 fully supports external DMA handshaking.
Out (coUT) SFR in the direct register instruction The MODE and Host Control SFRs control the config-
used. Immediate Commands may also be written at any uration of UPI-452 Host DMA handshake outputs. If
time to the Immediate Command OUT (IMOUT) SFR. Host DMA is used the Threshold Request for Service
The Host reads Immediate Commands from the Imme- interrupt asserts the UPI-452 DMA Request
diate Command OUT (IMOUT). (DRQOUT) output. The Host DMA processor ac-
knowledges with DACK which acts as a chip select of
The internal CPU can determine the number of bytes to the FIFO channels. The DMA transfer would stop
write to the FIFO Output channel in one of three ways. when either the threshold byte count had been read, as
The first, and most efficient, is by utilizing the internal programmed in the Host DMA processor, or when the
DMA processor which will automatically manage the DRQOUT output is brought inactive by the UPI-452.
writing of data to avoid Underrun or 'Overrun Errors.
The second is for the internal CPU to read the Output
FIFO channels Read and Write Pointers and compare INPUT CHANNEL
their values to determine the available space. The third
method for determining the available FIFO space is to This section covers the data path from the HOST to the
always write the programmed channel size number of internal CPU or internal DMA processor. The details
bytes to the Output FIFO. This method would use the of. Data Stream Command or Immediate Command
Overrun Error flag and interrupt to halt FIFO writing processing during internal DMA operations are cov-
whenever the available space was less than the channel ered in the DMA section below.
size. The interrupt service routine could read the chan-
nel pointers to determine or monitor the available chan-
nel space. The time required for the internal CPU to Host Write to the FIFO
write data to the Output FIFO channel is a function of
the individual instruction cycle time and the number of The Host writes data and Data Stream Commands into
bytes to be written. the FIFO through the FIFO IN (FIN) and Command
IN (CIN) SFRs. When a Threshold number of bytes
has been read out of the Input FIFO channel by the
Host Read from the FIFO internal CPU, the Host Status SFR Input FIFO Re-
quest for Service bit is set and an interrupt, if enabled,
The Host reads data or Data Stream Commands (DSC) is generated to the Host. The Input. FIFO Threshold
from the FIFO in response to the Host Status interrupt tells the Host that it may write the next block
(HSTAT) SFR flags and interrupts, if enabled. All of data into the FIFO. Either the INTRQ or DRQIN/
Host read operations access the same UPI-452 internal INTRQIN output pins can be used for this interrupi as
I/O ButTer Latch. At the end of the previous Host determined by the MODE and Host Control (HCON)
FIFO read' cycle a byte is loaded from the FIFO into SFR settings. The Host may continue to write to the
the I/O Buffer Latch and Host Status (HSTA T) SFR FIFO Input channel during the internal CPU read of
bit 5 is set or cleared (I = DSC, 0 = data) to reflect the FIFO. Data Stream Commands may be written to
the state of the byte'S FIFO ninth bit. If the FIFO ninth the FIFO Input channel at any time during a write of
bit is set (= 1) indicating a DSC, an interrupt is gener- data bytes. Immediate Commands may also be written
ated to the external Host via INTRQ pin or at any time to the Immediate Command IN (IMIN)
INTRQIN/INTRQOUT pins as determined by Host SFR.
Control (HCON) SFR bit 1. The Host then reads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.
10-342
inter AP-281
The Host also has three methods for determining the reads the Slave Status (SSTAT) SFR to determine the
available FIFO space. Two are essentially identical to source of the interrupt and service the Immediate Com-
that of the internal CPU. They involve reading the mand.
FIFO Input channel pointers and using the Host Status
SFR Underrun and Overrun Error flags and Request
for Service interrupts these would generate, if enabled FIFO INPUTIOUTPUT CHANNEL SIZE
in combination. The third involves using the UPI-4S2
Host DMA controller handshake signals and the pro-
grammed Input FIFO Threshold. The Host would re- Host
ceive a Request for Service interrupt when an Input
FIFO channel has a Theshold number of bytes able to The Host does not have direct control of the FIFO
be written by the Host. The Host service routine would Input or Output channel sizes or configuration. The
then write the Threshold number of bytes to the FIFO. Host can, however, issue Data Stream Commands or
Immediate Commands to the UPI-4S2 instructing the
If a Host DMA is used to write to the FIFO Input UPI-4S2 to reconfigure the FIFO interface by invoking
channel, the Threshold Request for Service interrupt FIFO DMA Freeze Mode. The Data Stream Com-
could assert the UPI-4S2 DRQIN output. The Host mand or Immediate Command would be a vector to a
DMA processor would assert DACK and the FIFO service routine which performs the specific reconfigura-
write would be completed by Host the DMA processor. tion.
The DMA transfer would stop when either the Thresh-
old byte count had been written or the DRQIN output
was removed by the UPI-4S2. Additional details on UPI-452 Internal
Host and internal DMA operation is given below.
The default power-on reset FIFO channel sizes are list-
ed in the "Initialization" section and can be set only by
Internal Read of the FIFO the internal CPU during FIFO DMA Frcczc Mode.
The FIFO channel size is selected 10 ac:hicve Ihe opli-
At the end of an internal CPU read cycle a byte is mum application performance. The enlirc 12H hyle
loaded from the FIFO buffer into the FIFO IN/Com- FIFO can be allocated to either the Input or Output
mand IN SFR and Slave Status (SSTAT) SFR bit lis . channel. In this case the other channel consists of a
set or cleared (I = data, 0 = DSC) to reflect the state single SFR; FIFO IN/Command IN or FIFO OUT/
of the FIFO ninth bit. If the byte is a DSC, the FIFO Command OUT SFR. Figure 4 shows a FIFO division
ninth bit is set (= I) and an interrupt is generated, if with a portion devoted to each channel. Figure 5 shows
enabled, to the Internal CPU. The internal CPU then a FIFO configuration with a11128 bytes assigned to the
reads the Slave Status (SSTAT) SFR to determine the Output channel.
source of the interrupt.
The FIFO channel Threshold feature allows the user to
Immediate Commands are written by the Host and match the .FIFO channel size and the performance of
read by the internal CPU through the Immediate Com- the internal and Host data transfer rates. The pro-
mand IN (IMIN) SFR. Once written, an Immediate grammed Threshold provides an elasticity to the data
Command sets the Slave Status (SSTAT) SFR flag bit transfer operation. An example is if the Host FIFO
and generates an interrupt, if enabled, to the internal
CPU. In response to the interrupt the internal CPU
HOST CPU
FIFO
INPUT FIFOINSFR ~
CHANNEL CHANNEL
INTERNAL
BOUNDRY ~.t---"'" CPU
POINTER FIFO
(CBP) OUTPUT FIFO OUT SFR
CHANNEL
HOST CPU
292018-4
Figure 4. Full Duplex FIFO Operation
10-343
AP-281
CHANNEL
HOST cpu-+I FIFO IN SFR 1-+
INTERNAL
BOUNDRY -+ CPU
POINTER FIFO
(CBP) INPUT
CHANNEL
H fiFO OUT SFR . J+-
~
HOST CPU
292018-5
Figure 5. Entire FIFO Assigned to Output Channel
data transfer rate is twice as fast as the internal FIFO this example the default 64 bytes per channel might be
DMA data transfer rate. In this example the FIFO In- adequate for both channels.
put channel size is programmed to be 64 bytes and the
Input channel Threshold is programmed to be 20 bytes.
The Host writes the first 64 bytes to the Input FIFO. INTERRUPT RESPONSE TIMING
When the internal DMA processor has read 20 bytes
the Threshold interrupt, or DMA request (DRQIN), is Interrupts enable the Host UPI"452 FIFO buffer inter-
generated to signal the Host.to begin writing.more data face and the internal CPU FIFO buffer interface to
to the Input FIFO channel. The internal DMA proces- operate with a minimum of overhead on the respective
sor continues to read data from the Input channel as CPU. Each CPU is "interrupted" to service the FIFO
the Host, or Host DMA processor, writes to the FIFO. on an as needed basis only. In configuring the FIFO
The Host can write 40 bytes to the FIFO Input chan- buffer Thresholds and choosing the appropriate inter-
nels in the time it takes for the internal DMA processor nal DMA Mode the user must take into account the
to read 20 more bytes from it. This will keep both the interrupt response time for both CPUs. These response
Host and internal DMA operating at their maximum times will affect the DMA transfer rates for each chan-
rates without forcing one to wait for the other. nel. By choosing FIFO channel Thresholds which re-
flect both the respective DMA transfer rate and the
Two methods of managing the FIFO size are possible; interrupt response time the user will achieve the maxi-
fixed and variable channel size. A fixed channel size is mum data throughput and system bus decoupling. This
one where the channel is configured at initialization in turn will mean the overall available system bus band-
and remains unchanged throughout program execution. width will increase.
In a variable FIFO channel size. the configuration is
changed dynamically to meet the data transmission re- The following section describes the FIFO interrupt in-
quirements as needed. An example of a variable chan- terface to the Host and internal CPU. It also describes
nel size application is the mass storage subsystem de- an analysis of sample interrupt response times for the
scribed earlier. To meet the demands of a large data Host and UPI-452 internal cpu. These equations and
block transfer the FIFO size could be fully allocated to the example times shown are then used in the DMA
the Input or Output channel as needed. The Thresholds section to further analyze an optimum Host UPI-452
are also reprogrammed to match the respective data interface.
transfer rates.
An example of a fixed channel size application might be HOST
one which uses the UPI-452 to directly control a series
of stepper motors. The UPI-452 manages the motor Interrupts to the Host processor are supported by the
operation and status as required. This would include three UPI-452 output pins; INTRQ, DRQINI
pulse train, acceleration, deceleration and feedback. INTRQIN and DRQOUT/INTRQOUT. INTRQ is a
The Host transmits motor commands to the UPI-452 in general purpose Request For Service interrupt output.
blocks of 6-10 bytes. Each block of motor command DRQIN/INTRQIN and DRQOUT/INRQOUT pins
data is preceded by a command to the QPI-452 which are multiplexed to provide two special "Request for
selects a specific motor. The UPI-452 transmits blocks Service" FIFO interrupt request lines when DMA is
of data to the Host which provides motor and overall disabled. A FIFO Input or Output channel Request for
system status. The data and embedded commands Service interrupt is generated based upon the value pro-
structure, indicating the specific motor, is the same. In grammed in the respective channel's Threshold SFRs;
Input Threshold (ITHR), and Output Threshold
10-344
AP-281
(OTHR) SFRs. Additional interrupts are provided for To initiate the interrupt the UPI-452 activates the
FIFO Underrun and Overrun Errors, Data Stream INTRQ output. The interrupt acknowledge sequence
Commands, and Immediate Commands. Table 4 lis~s requires two bus cycles, 400 ns (10 MHz iAPX 286),
the eight UPI-452 interrupt sources as they appear In for the two INTA pulse sequence.
the HSTAT SFR to the Host processor. Equation 1. Host Interrupt Response Time
Table 4 UPI-4S2 to Host Interrupt Sources
Bus
HSTAT Action Time
Interrupt Source Cycles'
SFR Bit Current instruction execution
HST7 Output FIFO Underrun Error completion 800 ns 4
HST6 Immediate Command Out SFR Status INTA sequence 400 ns .2
Interrupt service routine (time
HST5 Data Stream Command/Data at Output to host first READ of UPI-452) 2000 ns 10
FIFO Status
Total Interrupt Response Time 2.3/Ls 16
HST4 Output FIFO Request for Service Status
HST3 Input FIFO Overrun Error Condition NOTE:
10 MHz iAPX 286 bus cycle, 200 ns each
HST2 Immediate Comamnd In SFR Status
HST1 FIFO DMA FreezelNormal Mode
Status UPI-4S2 Internal
HSTO Input FIFO Request for Service
The internal CPU FIFO interrupt interface is essential-
ly identical to that of the Host to the FIFO. T~ree
. The interrupt response time required by the Host proc- internal interrupt sources support the FIFO operatIOn;
essor is application and system specific. In general, a FIFO-Slave bus Interface Buffer, DMA Channel 0 and
typical sequence of Host interrupt response eve~ts a~d DMA Channell Requests. These interrupts provide a
the approximate times associated with each are listed In maximum decoupling of the FIFO buffer and the inter-
Equation 1. nal CPU. The four different internal DMA Modes
available add flexibility to the interface.
The example assumes the hardware configuration
shown in Fjgure 1, iAPX 286IUPI-452 Block Diagram, The FIFO-Slave Bus Interface interrupt response is
with an 8259A Programmable Interrupt Controller. also similar to the Host response to an INTRQ Request
The timing analysis in Equation I also assumes the fol- for Service interrupt. The internal CPU responds to the
lowing; no other interrupt is either in process or pend- interrupt by reading the Slave Status (SSTAT) SFR to
ing, nor is the 286 in a LOCK condition. The current determine the source of the interrupt. This allows the
instruction completion time is 8 clock cycles (800 ns @ user to prioritize the Slave Status flag response to meet
10 MHz), or 4 bus cycles. The interrupt service routine the users application needs.
first executes a PUSHA instruction, PUSH All General
Registers, to save all iAPX 286 internal registers. This The internal interrupt response time is dependent on
requires 19 clocks (or 2.0 /Ls @ 10 MHz), or 10 bus the current instruction execution, whether the interrupt
cycles (rounded to complete bus cycle). The next serv- is enabled, and the interrupt priority. In general, to fin-
ice routine instruction reads the UPI-452 Host Status ish execution of the current instruction, respond to the
SFR to determine the interrupt source. interrupt request,·push the Program Counter (PC) and
vector to the first instruction of the interrupt service
It is important to note that any UPI-452 INTRQ inter- routine requires from 38 to 86 oscillator periods (2.38
rupt service routine should ALWAYS mask for the to 5.38 /Ls @ 16 MHz). If the interrupt is due to an
Freeze Mode bit first. This will insure that Freeze Immediate Command or DSC, additional time is re-
Mode always has the highest priority. This will also quired to read t.he Immediate Command or DSC SFR
save the time required to mask for bits which are forced and vector to the appropriate service routine. This
inactive during Freeze Mode, before checking the means two service routines back to back. One service
Freeze Mode bit. Access to the FIFO channels by the routine to read the Slave Status (SSTAT) SFR to deter-
Host is inhibited during Freeze Mode. Freeze Mode is mine the source of the Request for Service interrupt,
covered in more detail below. and second the service routine pointed to by the Imme-
diate Command or DSC byte read from the respective
SFR.
10-345
inter Ap-281
DMA Table 5. Host UPI-452
Data Transfer Performance
DMA is the fastest and most efficient way for the Host
or internal CPU to communicate with the FIFO buffer. Wait States:
DMA:
The UPI-452 provides support for both of these DMA Processor & Back to Back Two
Single
paths. The two DMA paths and operations are fully Speed READI Cycie
independent of each other and can function simulta- Cycle
WRITE's
neously. While the Host DMA processor is performing
a DMA transfer to Qr from the FIFO, the UPI-452 iAPX-186* 8MHz 0 N/A' 0
internal DMA processor can be doing the same. 10 MHz 0 N/A' 0
12.5 MHz 1 N/A* 0
Below are descriptions of both the Host and internal iAPX-286*' 6 MHz 0 0 0
DMA operations. Both DMA paths can operate asyn- 8MHz 1 1 0
chronously and at different transfer rates. In order to
make the most of this simultaneous asynchronous oper- 10 MHz 2 2 0
ation it is necessary to calculate the two transfer rates
NOTES:
and accurately match their operations. Matching the • iAPX 186 On-chip DMA processor is two cycle operation
different transfer rates is done by a combination of ac- only.
curately programmed FIFO channel size and channel •• iAPX 286 assumes 82258 ADMA (or other DMA) run-
Thresholds. This provid~s the maximum Host and in- ning 286 bus cycles at 286 clo,ck rate.
ternal CPU to FIFO buffer interface decoupling. Below
is a description of each of the two DMA operations and In this application note system example, shown in Fig-
sample calculations for determining transfer rates. The ure I, DMA operation is assumed to be two bus cycle.
next section of this application note, "Interface Laten- I/O to memory or memory to I/O,' Two cycle DMA
cy", details the considerations involved in analyzing ef- consists of a fetch bus cycle from the source and a store
fective transfer rates when the overhead associated with bus cycle to the destination. The data is stored in the
each transfer is considered. DMA controller's registers before being sent to the des-
tination. Single cycle DMA transfers involve a simulta-
neous fetch from the source and store to the destina-
HOST FIFO· DMA tion. As the most common method of I/O-memory
DMA operation, two cycle DMA transfers are the fo-
DMA transfers between the Host and UPI-452 FIFO cus of this application note analysis. Equation 2 illus-
buffer are controlled by the Host CPU's DMA control- trates a calculation of the overall transfer rate between
ler, and is independent of the UPl c452's internal two the FIFO buffer and external Host for a maximum
channel DMA processor. The UPI-452's internal DMA FIFO size transfer. The equation does not account for
processor supports data transfers between the UPI-452 the latency of initiating the DMA transfer. '
internal RAM, external RAM (via the Local Expansion
Bus) and the various Special Function Registers includ- Equation 2. Host FIFO DMA Transfer
ing the FIFO Input imd Output channel SFRs. Rate--:lnput or Output Channel
The maximum DMA transfer rate is achieved by the 2 Cycle DMA Transfer-I/O (UPI-452) to System
minimum DMA transfer cycle time to accomplish a Memory
source to destination move. The minimum Host UPI- FIFO channel size' (DMA READ/WRITE
452 FIFO DMA cycle time possible is determined by FIFO time + DMA WRITE/READ Memory
the READ and WRITE pulse widths, UPI-452 com- Time)
mand recovery times in relation to the DMA transfer 128 bytes' (200 ns + 200 ns)
timing and DMA controller transfer mode used. Table 51.2 Jks
5 shows the relationship between the iAPX-286, iAPX- 256 bus cycles'
186 and UPI-452 for various DMA as well as non-
DMA byte by byte transfer modes versus processor fre- NOTES:
quencies. '10 MHz iAPX 286, 200 ns bus cycles.
Host processor speed vs wait states required with UPI- The UPI-452 design is optimized for high speed DMA
452 running at 16 MHz: ' transfers between the Host and the FIFO buffer. The
10-346
intJ AP-281
UPI-452 internal FIFO buffer control logic provides The third handshake signal pin is DACK which is used
the necessary synchronization of the external Host as a chip select during DMA data transfers. The UPI-
event and the internal CPU machine cycle during 452 Host READ and WRITE input signals select the
UPI-452 RD/WR accesses. This internal synchroniza- respective Input and Output FIFO channel during
tion is addressed by the TCC AC specification of the DMA transfers. The CS and address lines provide
UPI-452 shown in Figure 6. TCC is the time from the DMA acknowledge for processors with onboard DMA
leading or trailing edge of a UPI-452 RD/WR to the controllers which do not generate a DACK signal.
same edge of the next UPI-452 RD/WR. The TCC
time is effectively another way of measuring the system The iAPX 286 Block I/O Instructions provide an alter-
bus cycle time with reference to UPI-452 accesses. native to two cycle DMA data transfers with approxi-
mately the same data rate. The String Input and Out-
In the iAPX-286 10 MHz system depicted in this appli- put instructions (INS & OUTS) when combined with
cation note the bus cycle time is 200 ns. Alternate cycle the Repeat (REP) prefix, modifies INS and OUTS to
accesses of the UPI-452 during two cycle DMA opera- provide a means of transferring blocks of data between
tion yields a TCC time of 400 ns which is more than the I/O and Memory. The data transfer rate using REP
TCC minimum time of 375 ns. Back to back Host INS/OUTS instructions is calculated in the same way
UPI-452 READ/WRITE accesses may require wait as two cycle DMA transfer times. Each READ or
states as shown in Table 5. The difference between 10 WRITE would be 200 ns in a 10 MHz iAPX 286 sys-
MHz iAPX-186 and 10 MHz iAPX 286 required wait tem. The maximum transfer rate possible is 2.5
states is due to the number of clock cycles in the respec- MBytes/second. The Block I/O FIFO data transfer
tive bus cycle timings. The four clocks in a 10 MHz calculation is the same as that shown in Equation 2 for
iAPX 186 bus cycle means a minimum TCC time of two cycle DMA data transfers including TCC timing
400 ns versus 200 ns for a 10 MHz iAPX 286 with two effects.
clock cycle zero wait state bus cycle.
DMA handshaking between the Host DMA controller FIFO Data Structure and Host DMA
and the UPI-452 is supported by three pins on the UPI-
452; DRQIN/INTRQIN, DRQOUT/INTRQOUT During a Host DMA write to the FIFO, if a DSC is to
and DACK. The DRQIN/INTRQIN and DRQOUT/ be written, the DMA transfer is stopped, the DSC is
INTRQOUT outputs are two multiplexed DMA or in- written and the DMA restarted. During a Host DMA
terrupt request pins. The function of these pins is con- read from the FIFO, if a DSC is loaded into the I/O
trolled by MODE SFR bit 6 (MD6). DRQIN and Buffer Latch the DMA request, DRQOUT, will be de-
DRQOUT provide a direct interface to the Host system activated (see Figure 2 above). The Host Status
DMA controller (see Figure 1). In response to a (HSTAT) SFR Data Stream Command bit is set and
DRQIN or DRQOUT request, the Host DMA control- the INTRQ interrupt output goes active, if enabled.
ler initiates control of the system bus using HLD/ The Host responds to the interrupt as described above.
HLDA. The FIFO Input or Output channel transfer is
accomplished with a minimum of Host overhead and
system bus bandwidth.
cs# , \ -_ _---J 1 , \ -_ _---J 1
I-I·----TCC----~'I
RD#/WR# ----J-\~ I I ~
____T_R_V_~ TRR/TWW, ~
TRR/TWW \-4t
292018-6
Symbol Description Var.Osc. @16MHz
TCC Command Cycle 6 * Tclcl 375 ns min
Time
TRV Command Recovery 75 75 ns min
Time
Figure 6. UPI-4S2 Command Cycle Timing
10-347
inter AP-281
Once INTRQ is deactivated and the DSC·has been read (Memory Mapped or I/O) to 286 System Memory
by the Host, the DMA request,DRQOUT, is reassert- transfer as described earlier. The equations do not ac-
ed by the UPI-452. The DMA request then remains count for the latency of intiating the DMA transfer.
active until the transfer is complete or another DSC is
loaded into the I/O Buffer Latch. Equation 3. Minimum host FIFO DMA Transfer
Rate Including Data Stream Command(s)
An Immediate Command written by the internal CPU
during a Host riMA FIFO transfer also causes the Minimum Host/FIFO DMA Transfer Rate wI DSC
Host- Status flag and INTRQ to go active ifenabled. In FIFO size· Host DMA 2 cycle time transfer rate
this case the Immediate Command would not terminate + iAPX 286 interrupt response time (Eq. # 1)
the DMA transfer unless terminated by the Host. The (32 bytes· (200 ns + 200ns)) + 2.3 p.s
INTRQ line remains active until the Hostreads the 15.1 p.s -
Host Status (HSTAT) SFR to determine the source of 75.5 bus cycles (@10 MHz iAPX286, 200ns
the interrupt. bus cycle)
The net effect ora Data Stream Command (DSC) on
DMA data transfer rates is to add an additional factor UPI-4S2 INTERNAL DMA PROCESSOR-
to the data transfer rate equation. This added factor is
shown in Equation 3. An Immediate Command has the The two identical internal DMA channels allow high
same effect on the data transfer rate if the Immediate speed data transfers from one UPI-452 writable memo-
Command interrupt is recognized by the Host during a ry space to another. The following UPI-452 memory
DMA transfer. If the DMA transfer is completed be- spaces can be used with internal DMA channels:
fore the Immediate Command interrupt is recognized,
the effect on the DMA transfer rate depends on wheth- Internal Data Memory (RAM)
er the block being transmitted is larger than the FIFO External Data Memory (RAM)
channel size. If the block is larger than the pro- Special Function Registers (SFR)
grammed FIFO channel size the transfer rate depends
on whether the Immediate Command flag or interrupt The FIFO can be accessed during internal DMA opera-
is recognized between partial block transfers. tions by specifying the FIFO IN (FIN) SFR as ti).e
DMA Source Address (SAR) or the FIFO OUT
The FIFO configuration shown in Equation 3 is arbi- (FOUT) SFR as the Destination Address (DAR). Ta-
trary since there is no way of predicting the size relative ble 6 lists the four types of internal DMA transfers and
to when a DSC would be loaded into the I/O Buffer their respective timings.
Latch. The Host DMA rate shown is for a UPI-452
Table 6. UPI-452 Internal DMA Controller Cycle Timings
Machine
Source Destination @12MHz @16MHz
Cycles'·
Internal Data Internal Data
Mem.orSFR Mem.orSFR 1 1 p.s 750 ns
Internal Data External Data
Mem.orSFR Mem. 1 1 p.s 750 ns
External Data Internal Data
Mem. Mem.orSFR 1 1 p.s 750ns
·External Data External Data
Memory Memory 2 2 p.s 1.5 p.s
. NOTES:
"External Data Memory DMA transfer applies to UPI-4S2 Local Bus only.
··MSC-S1 Machine cycle = 12 clock cycles (TCLCL).
10-348
inter AP-281
FIFO Data Structure and Internal DMA INTERFACE LATENCY
The effect of Data Stream Commands and Immediate The interface latency is the time required to accommo-
Commands on the internal DMA transfers is essentially date all of the overhead associated with an individual
the same as the effect on Host FIFO DMA transfers. data transfer. Data transfer rates between the Host sys-
Recognition also depends upon the programmed DMA tem and UPI-452 FIFO, with a block size less than or
Mode, the interrupts enabled, and their priorities. The equal to the programmed FIFO channel size, are calcu-
net internal effect is the same for each possible internal lated using the Host system DMA rate. (see Host
case. The time required to respond to the Immediate or. DMA description above). In this case, the entire block
Data Stream Command is a function of the instruction could be transferred in one operation. The total latency
time required. This must be calculated by the user is the time required to accomplish the block DMA
based on the instruction cycle time given in the MSC- transfer, the interrupt response or poll of the Host
51 Instruction Set description in the Intel Microcon- Status SFR response time, and the time required to ini-
troller Handbook. tate the Host DMA processor~
It is important to note that the internal DMA processor A DMA transfer between the Host and UPI-452 FIFO
modes and the internal FIFO logic work together to with a block size greater than the programmed FIFO
automatically manage internal DMA transfers as data channel size introduces additional overhead. This addi-
moves into and out of the FIFO.· The two most appro- tional overhead is from three sources; first, is the time
priate internal DMA processor modes for the FIFO are to actually perform the DMA transfer. Second, the
FIFO Demand Mode and FIFO Alternate Cycle Mode. overhead of initializing the DMA processor, third; the
In FIFO Demand Mode, once the correct Slave Con- handshaking between each FIFO block required to
trol and DMA Mode bits are set, the internal Input transfer the entire data block. This could be time to
FIFO channel DMA transfer occurs whenever the wait for the FIFO to be emptied and/or the interrupt
Slave Control Input FIFO Request for Service flag is response time to restart the DMA transfer of the next
set. The DMA transfer continues until the flag is portion of the block. A fourth component may also be
cleared or when the Input FIFO Read Pointer SFR the time required to respond to Underrun and Overrun
(IRPR) equals zero. If data continues to be entered by FIFO Errors.
the Host, the internal DMA continues until an internal
interrupt of higher priority, if enabled, interrupts the Table 7 shows six typical FIFO Input/Output channel
DMA transfer, the internal DMA byte count reaches sizes and the Host DMA transfers times for each. The
zero or until the Input FIFO Read Pointer equals zero. timings shown reflect a 10 MHz system bus two cycle
A complete description of interrupts and DMA Modes I/O tq Memory DMA transfer rate of 2.5 MBytes/sec-
can be found in the UPI-452 Data Sheet. ond as shown in Equation 1. The times given would be
the same for iAPX 286 I/O block move instructions
REP INS and REP OUTS as described earlier..
DMAModes
Table 7_ Host DMA FIFO Data Transfer Times
The internal DMA processor has four modes of opera-
tion. Each DMA channel is software programmable to FIFO Size: 32 43 64 85 96 128 I bytes
operate in either Block Mode or Demand Mode. De- Full or Empty % % % % % Full or Empty
mand Mode may be further programmed to operate in Time 12.8 1i2 25.6 34.0 38.4 51.21 /Ls
Burst or Alternate Cycle Mode. Burst Mode causes the
internal processor to halt its execution and dedicate its
resources exclusively to the DMA transfer. Alternate Table 8 shows six typical FIFO Input/Output channel
Cycle Mode causes DMA cycles and instruction cycles sizes and the internal DMA processor data transfers
to occur alternately. A detailed description of each times for each. The timings shown are for a UPI-452
DMA Mode can be found in the UPI-452 Data Sheet. single cycle Burst Mode transfer at 16 MHz or 750 ns
per machine cycle in or out of the FIFO channels. The
10-349
inter AP-281
machine cycle time is that of the MSC-51 CPU; 6 channel. As described above in the FIFO Data Struc-
states, 2 XTAL2 clock cycles each or 12 clock cycles ture section, the block size would have to be deter-
per machine cycle. Details on the MSC-51 machine cy- mined by reading the channel read and write pointer
cle timings and operation may be found in the Intel and calculating the space available. Another alternative
Microcontroller Handbook. uses the FIFO Overrun and Underrun Error flags to
manage the tr~sfers by accepting error flags. In either
Table 8. UPI-452 Internal DMA FIFO case the instructions needed have a significant impact
Data Transfer Times on the internal FIFO data transfer rate latency equa-
tion.
FIFO Size: 32 43 64 85 96 I
128 bytes
Full or Empty 114 113 % % % Full or Empty A typical effective internal FIFO channel transfer rate
Time 24.0 32.3 48.0 64.6 72.0 96.0 I /Ls using internal DMA is shown in Equation 4. Equation
5 shows the latency using byte by byte transfers with an
arbitrary factor added for internal CPU block size cal-
A larger than programmed FIFO channel size data culation. These two equations contrast the effective
block internal DMA transfer requires internal arbitra- transfer rates when using internal DMA versus individ-
tion. The UPI-452 provides a variety of features which ual instructions to transfer 128 bytes. The effective
support arbitration between the two internal DMA transfer rate is approximately four times as fast using
channels and the FIFO. An example is the internal DMA versus using individual instructions (96 /Ls with
DMA processor FIFO Demand Mode described above. DMA versus 492 /Ls non-DMA).
FIFO Demand Mode DMA transfers occur continu-
ously until the Slave Status Request for Service Flag is Equation 4. Effective Internal FIFO
deactivated. Demand Mode is especially useful for con-
Transfer Time Using Internal DMA
tinuous data transfers requiring immediate attention.
FIFO Alternate Cycle Mode provides for interleaving Effective Internal FiFO Transfer Rate with DMA
DMA transfers and instruction cycles to achieve a FiFO channel size • Internal DMA Burst Mode
maximum of software flexibility. Both iriternal DMA Single Cycle DMA Time
channels can be used simultaneously to provide contin- 128 Bytes • 750 ns
uous transfer for both Input and Output FIFO chan- 96/Ls
nels.
Equation 5. Effective FIFO Transfer
Byte by byte transfers between the FIFO and internal Time Using Individual Instructions
CPU timing is a function of the specific instruction cy- Effective Internal FIFO Transfer Rate without DMA
cle time. Of the 111 MCS-51 instructions, 64 require 12 FIFO channel size * Instruction Cycle Time +
clock cycles, 45 require 24 clock cycles and 2 require 48 Block size calculation Time
clock cycles. Most instructions involving SFRs are 24 128 Bytes • (24 oscillator periods @ 16 MHz) +
clock cycles except accumulator (for example, MOV 20 instructions (24 oscillator period each .
direct, A) or logical operations (ANL direct, A). Typi- @ 16MHz)
cal instruction imd their timings are shown in Table 9. 128 *1.5 /Ls + 300 /Ls
492/Ls .
Oscillator Period: @ 12 MHz = 83.3 ns
@ 16 MHz = 62.5 ns
'FIFO DMA FREEZE MODE
Table 9. Typical Instruction Cycle Timings INTERFACE
OSCillator FIFO DMA Freeze Mode provides a means of locking
Instruction @12MHz @16MHz the Host out of the FIFO Input and Output channels.
Periods
FIFO DMAFreeze Mode can be invoked for a variety
MOV directt, A 12 1 /Ls 750 ns of reasons, for example, to reconfigure the UPI-452 Lo-
MOV direct, direct 24 2/Ls 1.5/Ls cal Expansion Bus, or change the baud rate on the seri-
al channel. The primary reason the FIFO DMA Freeze
NOTE: Mode is provided is to ensure that the Host does not
t Direct = a·bit internal datil locations address. This could read from or write to the FIFO while the FIFO inter-
be an Internal Data RAM location (0-255) or a SFR Ii.e., II face is being altered. ONLY the internal CPU has the
o port, control register, etc.]
capability of altering the FIFO Special Function Regis-
ters, and these SFRs can ONLY be altered during
Byte by byte FIFO data transfers introduce an addi- FIFO DMA Freeze Mode. FIFO DMA Freeze Mode
tional overhead factor not found in internal DMA op- inhibits Host access of the FIFO while the internal
erations. This factor is the FIFO block size to be trans- CPU reconfigures the FIFO.
ferred; the number of empty locations in the Output
channel, or the number of bytes in the Input FIFO
10-350
infef Ap·281
FIFO DMA Freeze Mode should not be arbitrarily in- operations described in this section are only valid after
voked while the UPI-452 is in normal operation. Be- SST5 is cleared.
cause the external CPU runs asynchronously to the in-
ternal CPU, invoking freeze mode without first proper- Either. the Host or internal CPU can request FIFO
ly resolving the FIFO Host interface may have serious DMA Freeze Mode. The first step is to issue an Imme-
consequences. Freeze Mode may be invoked only by diate Command indicating that FIFO DMA Freeze
the internal CPU. Mode will be invoked. Upon receiving the Immediate
Command, the external CPU should complete servicing
The internal CPU invokes Freeze Mode by setting bit 3 all pending interrupts and DMA requests, then send an
of the Slave Control SFR (SC3). This automatically Immediate Command back to the internal CPU ac-
forces the Slave and Host Status SFR FIFO DMA knowledging the FIFO DMA Freeze Mode request.
Freeze Mode to In Progress (SSTAT SST5 =. 0, After issuing the first Immediate Command, the inter-
HSTAT SFR HSTl = 1). INTRQ goes active, if en- nal CPU should not perform any action on the FIFO
abled by MODE SFR bit 4, whenever FIFO DMA until FIFO DMA Freeze Mode is invoked. The hand-
Freeze Mode is invoked to notify the Host. The Host shaking is the same in reverse if the HOST CPU initi-
reads the Host Status SFR to determine the source of ates FIFO DMA Freeze Mode.
the interrupt. INTRQ and the Slave and Host Status
FIFO DMA Freeze Mode bits are reset by the Host After the slave bus interface is frozen, the internal CPU
READ of the Host Status SFR. can perform the operations listed below on the FIFO
Special Function Registers. These operations are al-
During FIFO DMA Freeze Mode the Host has access lowed only during FIFO DMA Freeze Mode. Table 11
to the Host Status and Control SFRs. All other Host summarizes the characteristics of all the FIFO Special
FIFO interface access is inhibited. Table 10 lists the Function Registers during Normal and FIFO DMA
FIFO DMA Freeze Mode status of all slave bus inter- Freeze Modes.
face Special Function Registers. The internal DMA
processor is disabled during FIFO DMA Freeze Mode For FIFO 1. Changing the Channel Boundary
and the internal CPU has write access to all of the Reconfiguration Pointer SFR.
FIFO control SFRs (Table 11). 2. Changing the Input and Output
Threshold SFR.
If FIFO DMA Freeze Mode is invoked without stop-
ping the host, only the last two bytes of data written To Enhance the 3. Writing to the read and write
into or read from the FIFO will be valid. The timing testability pointers of the Input and Output
diagram for disabling the FIFO module to the external FIFO's.
Host interface is illustrated in Figure 7. Due to this 4. Writing to and reading the Host
synchronization sequence, the UPI-452 might not go Control SFRs.
into FIFO DMA Freeze Mode immediately after the 5. Controlling some bits of Host and
Slave Control SFR FIFO 7 DMA Freeze Mode bit Slave Status SFRs.
(SC3) is set = 0. A special bit in the Slave Status SFR
(SST5) is provided to indicate the status of the FIFO 6. Reading the Immediate Command
DMA Freeze Mode. The FIFO DMA Freeze Mode Out SFR and Writing to the 1m,
mediate Command in SFR.
INTRQ OR
DRaIN/DRaoUT
..J
RD#/WR# :: : A FIFO RD/WR AFTER
I • - • INTERFACE FREEZE IS
INVOKED WILL CAUSE
HST3 OR HST7 TO BE SET
INTRa J .......S.. ____ .. ____ ... _. __
SC3
HSTl _ _ _ _ _ _ _ _ _ _ _ _ _ _..1 SET
292018-7
NOTE:
Timing Diagram of disabling of FIFO Module-External Host Interface.
Figure 7. Disabling FIFO to Host Slave Interface Timing Diagram
10-351
AP-281
The sequence of events for invoking FIFO DMA 4. The Immediate Command interrupt is responded to
Freeze Mode are listed in Figure 8. immediately-highest priority-by Host and inter-
nal CPU.
1. Immediate Command to request FIFO DMA 5. Respective interrupt response times
Freeze Mode (interrupt) a. Host (Equation 3 above)=approximately 1.6 pos
b. Internal CPU is 86 oscillator periods or approxi-
2. Host/internal CPU interrupt response/service
mately 5.38 pos worst case.
3. Host/internal CPU clear/service all pending
interrupts and FIFO data Event Time
4. Internal CPU sets Slave Control (SLCON) Immediate'Command from Host 0.30 pos
FIFO DMA to UPI-452 to request FIFO DMA -
Freeze Mode bit ,:: 0, FIFO DMA Freeze Freeze Mode (iAPX286 WRITE)
Mode, Host Status SFR FIFO DMA Freeze Internal CPU interrupt response/ 5.38 pos
Mode Status bit = 1, INTRQ active (high) service
5. Host READ Host Status SFR Internal CPU clears FIFO-128 96.00 pos
6. Internal CPU reconfigures FIFO SFRs bytes DMA
7. Internal CPU resets Slave Control (SLCON) Internal CPU sets Slave Control 0.75 pos
FIFO DMA Freeze Mode bit
Freeze Mode bit = 1, Normal Mode, Host Immediate Command to Host- 2.3 pos
Status FIFO DMA Freeze Mode Status bit = Freeze Mode in progress Host
O. Immediate Command interrupt
response
8. Internal CPU issues Immediate Command to
Host indicating that FIFO DMA Freeze Mode is Internal CPU reconfigures FIFO
complete ; SFRs
Channel Boundary Pointer SFR 0.75 pos
or InputThreshold SFR 0.75 pos
Host polls Host Status SFR FIFO DMA Freeze Output Threshold SFR 0.75 pos
Mode bit to determine end of reconfiguration Internal CPU resets Slave 2.3 pos
Figure 8. Sequence of Events to Invoke Control (SLCON) Freeze Mode
bit = 1, Normal Mode, and
FIFO DMAFreeze Mode automatically resets Host Status
FIFO DMA Freeze Mode bit
EXAMPLE CONFIGURATION Internal CPU writes Immediate 0.75 pos
Command Out
An example of the time required to reconfigure the Host Immediate Command 2.3 pos
FIFO 180 degrees, for example from 128 bytes Input to interrupt service -
128 bytes Output, is shown in Figure 9. The example
Total Minimum Time to 112.33 pos
approximates the time based on several assumptions;
Reconfigure FIFO
1. The FIFO Input channel isfull-128 bytes of data
2. Output FIFO channel is empty-1 byte Figure 9. Sequence of Events to Invoke FIFO
DMA Freeze Mode and Timings
3. No Data Stream Commands in the FIFO.
10-352
intJ AP-281
Table 10. Slave Bus Interface Status During FIFO DMA Freezer Mode
Interface Pins; Operation In Status In
DACK CS . A2 A1 AO READ WRITE Normal Mode Freeze Mode
1 0 0 1 0 0 1 Read Host Status SFR Operational
1 0 0 1 1 0 1 Read Host Control SFR Operational
1 0 0 1 1 1 0 Write Host Control SFR Disabled
1 0 0 0 0 0 1 Data or DMA data from Disabled
Output Channel
1 0 0 0 0 1 0 Data or DMA data to Disabled
Input Channel
1 0 0 0 1 0 1 Data Stream Command from Disabled
Output Channel
1 0 0 0 1 1 0 Data Stream Command to Disabled
Input Channel
1 0 1 0 0 0 1 Read Immediate Command Disabled
Out from Output Channel
1 0 1 0 0 1 0 Write Immediate Command Disabled
In to Input Channel
0 X X X X 0 1 DMA Data from Output Disabled
Channel
0 X X X X 1 0 DMA Data to Input Channel Disabled
NOTE:
X = don't care
Table 11. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Normal Freeze Mode
Label Name Operation Operation
(SST5 = 1) (SST5 = 0)
HCON Host Control Not Accessible Read & Write
HSTAT Host Status Read Only Read & Write
SLCON Slave Control Read & Write Read & Write
SSTAT Slave Status Read Only Read & Write
IEP Interrupt Enable
& Priority Read & Write Read & Write
MODE Mode Register Read & Write Read & Write
IWPR Input FIFO Write Pointer Read Only Read & Write
IRPR Input FIFO Read Pointer Read Only Read & Write
OWPR Output FIFO Write Pointer Read Only Read & Write
ORPR Output FIFO Read Pointer Read Only Read & Write
CBP Channel Boundary Pointer Read Only Read & Write
IMIN Immediate Command In Read Only Read & Write
IMONT Immediate Command Out Read & Write Read & Write
FIN FIFO IN Read Only Read Only
CIN COMMAND IN Read Only Read Only
FOUT FIFO OUT Read & Write Read & Write
COUT COMMAND OUT Read & Write Read & Write
ITHR Input FIFO Threshold Read Only Read & Write
OTHR Other FIFO Threshold Read Only Read & Write
10-353
inter ARTICLE
REPRINT
AR-409
October 1985
© INTEL CORPORATION, 1985 ORDER NUMBER: 270126-001
Reprinted from Design News, 8-19-85
270126-1
10-354
inter AR·409
INCREASED FUNCTIONS
IN CHIP RESULt IN
LIGHTER,
LESS COSTLY PORTABLE
COMPUTER
Jafar Modares, Applications Engineer, Intel Corp., Chandler, AZ
Advances in technology have made it communicates with the host computer at displaying the same number of charac-
possible to reduce the size and increase very high BAUD rates, and displays ters as a typical CRT, and it is not as
the functionality and performance of information on the screen at slower rates bulky or heavy as the latter.
computers and computer peripherals. for human beings. The chip also moni- LCDs can be divided into two large
With the help of microtechnology it is tors the power supply for switching to categories: smart LCDs and dumb
possible to construct a computer termi- the battery in case of power failure to LCDs. Those displays that have the
nal that is smaller and lighter than a save valuable data and computer time. capability to receive a byte of ASCII and
briefcase, and that can be connected to The prototype is currently under futher translate it into a displayed character are
a mainframe from almost anywhere. development at Intel's Microcontroller considered smart. On the other hand.
As more portable computers are intro- Division. dumb displays are only a matrix of dots.
duced to the marketplace, the demand Introducing the 80C51BH The former type has some kind of con-
for lighter and even smaller systems at Very new in the market, the 80CSI 8H troller of its own plus a small memory
a lower cost are inevitable. To meet this is a member of Intel's MCS-SI family. to hold the look-up table of characters
demand changes in the architecture are The MCS-SI is a group of 8-bit micro- (character generator). When using a
necessary. controllers that are extremely powerful dumb display the microcontroller has to
With Intel's recently introduced because of their 110 structure and their address and tum on the correct dots to
80C51 BH microcontroller several obsta- bit manipulating capabilities. The make a character. this means more 1/0
cles in the design of the portable com- 80C51 BH has 4 Kbytes of on-chip pro- pins will be required. However, it gives
puter have been overcome. The gram memory with the capability to extra capabilities such as graphic dis-
80C51 BH is a single chip 8-bit micro- address another 60 Kbytes of external plays and special or custom character
controller that requires a single 5V program memory. In addition it has 128 generation.
power supply. It has 32 110 lines. Its bytes of on-chip RAM and can access Both types of displays normally
functionalities include excellent bit and 64 Kbytes of external data memory. accept data through an 8-bit bus.
byte manipulation capability at Since the 80CSIBH is CMOS. it has Although the LCD is relatively slow. it
extremely high speeds as well as inter- very low power consumption (IS mA at can still share the bus with a memory
facing flexibilities through the serial and 5V. 12 MHz). In addition, it has two device without any degradation of the
parallel channels to intelligent and unin- power saving features not available in system performance.
telligent devices. It can carry its own HMOS versions of the family. These are Keyboard
program memory up to 4 Kbytes and has the Idle and Power Down modes.,which Depending on their task arid purpose.
various tools and support systems. are controlled by software and further keyboards vary in shape. size. and the
This article discusses the implemen- reduce power comsumption. These number of keypads. The keyboard for a
tation of a prototype portable terminal power saving features make it ideal for computer terminal, as a minimum.
based on Intel's new 8OC51 BH micro- battery-operated backed-up systems. should have all the alphanumeric keys
controller, and introduces the tools and Display device (standard typewriter) plus a Control. an
techniques available to build such a com- The display device of this portable ter- Escape. and optionally. some Function
puter terminal. In the application dis- minal'is a 25-line x 80-character Liquid keys.
cussed. the chip monitors the keyboard. Crystal Display (LCD). It is capable of As the diagram in Figure I shows a
270126-2
10-355
inter AR-409
typical keyboard consists of a matrix of
Vee
eight scan lines and eight receive lines. RECEIVE LINES
The scan lim,s are connecied to Port 0
H
-I
of the microcontroller, and receive lines
are connected to Port I.' The software
writes Os to Port 0 to hold the scan lines
at a logic Low, and it writes I s to Port SCAN I PORT
(DAT~BUS)
l
LINES.
I to hold the receive lines at a logic ~
CONTROL KEY ~
High. Pressing one of the keys connects
-~lr
a scan line to receive a line and pulls
that receive line Low .
. Besides being used for the scan lines, TO THE EXTERNAL
INTERRUPT PIN
Port 0 is also the bus for the data buffer >--~
RAM and the display unit. While the
controller is talking to the RAM or to
TO PORT 1
the display, the bus must not be used.by TO P3.4
ANO P3.S
other devices or bus contention can
occur. Since the microcontoller initiates
Figure 1
the access to the display and to the data
buffer RAM, no conflict can occur
between them. However, if more than mately 25 msec (to debounce the·.key), the terminal is to he connected directly
one key on the same receive line is held and to perform' the task of identifying to the mainframe, a simple circuit trans-
down simultaneously while the RAMor which key is down. lates the TTL levels to the RS232 level.
the display is being accessed, it is pos- There are a number of ways that the The circuit also eliminates the need for
sible to foul up the information being interrupt service routine can identify the the - 12V supply required for R02J2.
transferred. Thus, to avoid bus ~onten press key. One way is to utilize the bit- The circuit diagram is shown in Figure
tion, diodes 0 I through 08 are placed addressing capabilities of the 80C51 BH 2.
on the scan lines, as shown in Figure I. to test each bit of the receive lines for a However, the primary application of
All the receive lines are ANOed to zero, which generated the interrupt, and this terminal is to be the traveling per-
External Interrupt I, so that pulling any' records the bit position. Then write Os son's window to the central system from
of the receive lines Low will generate an to the receive lines, Is to the scan lines, any remote location. In this application
interrupt. The interrupt service routine, test the scan lines for a zero, and record a modem is needed. There are many
adapts the "two key lock.out." system its position. If the controller finds more types of modems available. Some are on
and identities the pressed key. This sys- than one zero on each port, it will dis- PC boards for OEM use and others arc
tem allows only one key to be pressed continue any further processing and ready to connect directly to the telephone
simultaneously, all of them will be return to the main program. by the user. They also vary in size, pet-
ignored. Once the bit positions that contain 0 formance, and the way they communi-
On some keyboards, certain keys are recorded, they are used as the address cate. A proper modem for the portable
(such as Shift, Control or Escape) are for the characters in the look-up table. terminal should be small enough to carry
not a part of the line matrix. These keys The subroutine tinds the character that in a briefcase and preferdbly be a low-
connect directly to a port pin on the corresponds to' the. pressed key. The power device. When an ASCII code is
microcontroller. They would not cause character is represented in ASCII code. received by the host computer, it records
lock-out if pressed simultaneously with The look-up table is a list of the ASCII that code and echoes it back to the micro-
a matrix key, nor generate an interrupt representation of each keypad character, controller which displays it on the LCD.
if pressed singly. However, if they are and is stored in 'the program memory .. The serial port of the 80C51 BH can
part of the miltrix, then the software has The order in which they sit corresponds generate interrupts every time il receives
to recognize those keys and take proper to the address generated by the scan sub- or transmils information. The serial port
action depending on the function of the routine when that character is pressed on interrupt must have service priority over
pressed key. the keyboard. the external interrupt generated by the
Normally, when a key is pressed, the Serial communication keyboard. The high priority enables the
microcontroller is in the Idle mode and Once the 80C51 BH has' the ASCII serial port' to receive data any time the
no other task is in progress. Pressing a code generated from a key closure, it can computer addresses the terminal and
key on the matrix generates an interrupt, send it through its Serial' Channel to the transmits data.
which terminates the Idle mode. The host computer. The serial port of the ,The serial port interrupt service rou:
interrupt service routine tirst calls a sub: microcontroller can be programmed for tine transfers the received data to the
routine to provide a delay of approxi- all of the standard rates up to 375K. If display or to a memory buffer, depend-
270126-3
10-356
inter AR-409
ficient for buffering large blocks of data its own internal clock and goes to sleep.
MICROCONTROLLER storage. The serial port interrupt service Since the CPU consumes about 90% of
routine takes the data from the SBUF the chip's power. this process saves a
register and writes it to the iRAM. Two significant amount of power. More
ing on the mode selected by a function index pointers in the serial port interrupt importantly the on chip peripherals and
key. One mode of this function key teUs service routine help keep track of the the RAM continue their normal func-
the controller to move the received data incoming and outgoing iRAM data. tions independently of the CPU. Since
directly to the display. The other mode There are times the controller has to the oscillator is still running. any ena-
stores pages of the information in the wait for reasons such as the debounce bled interrupt (internal or external) will
buffer RAM. so that the user can edit or delay in the scan subroutine or when wake the CPU up from its sleep. and it
display the data. one page a,t a time. on writing to the display. and must slow will start executing instructions from the
the LCD without using the main sys- down. While the 80CSI BH is waiting. interrupt service routine.
tem's CPU time. it goes into the Idle mode until one of A true portable terminal should be
Data buffer memory the timers. which programmed to run. capable of operating from a battery
The data buffer RAM is temporary' times out and generates an interrupt. The source. There are occasions when one
storage for the information which is interrupt service routine for this type of would like to use the terminal at a loca-
either generated at the terminal or interrupt is a short one. it sets or clears tion where an electric outlet is not readily
retrieved from the central system. The one or more flags and returns to continue available. But the main purpose of the
user can display portions of the stored the task that was in progress before going battery supply is to save the data. which
information or scroll through it. The user into the Idle mode. has been entered and stored in the buffer
can also alter the data on the terminal The controller is also in the Idle mode RAM. in the case of an unexpected
and transmit it back to the computer in when there is no activity in the terminal. power failure.
a block form. i.e .• no data is being received or trans- While performing all of the previously
A suitable device for this purpose is mitted. and the keyboard is not being mentioned tasks. the gOCSI B H can
the SIC86 iRAM. This device is a used. Therefore. is is appropriate to say monitor its power supply: detect a power
pseudo-static dynamic RAM that has a that when power is applied to the ter- loss in its earliest stages. and initiate a
built-in address latch. An internal high- minal. the controller spends more than power Down to save the data of the inter-
speed arbitration circuit resolves any 90% of its time in the Idle mode. nal and external RAM.
potential conflict arising between read/ What is the Idle mode? One method for the 80CSI BH to mon-
write arid internal refresh cycles. When Bit 0 in the Special Function itor its power supply is to have the pos-
This iRAM is 8K x 8-bit and is suf- Register PCON is set. the CPU gates off itive half-cycles of the power supply
transformer fed to the External Interrupt
o pin (Figure 3). In the level activated
mode. this pin generates an interrupt
+SV every time there is a high to low tran-
sition. The interrupt service routine
R1
reloads Timer 0 to a value.that will make
it overflow sometime between one and
two periods of the line frequency. As
long as the half cycles keep coming in.
the timer never overflows. because it is
reloaded every half a cycle. If there is a.
single half a cycle in which the line volt-
+SV
age does not reach a high enough level
to generate the interrupt. the timer rolls
over and generates a timer interrupt.
The interrupt service routine for
Timer 0 saves the critical data of some
of the internal registers and puts the con-
SERIAL
OUTPUT troller into a Power down mode. A reset
RS button restarts the microcontroller to
02 resume operation when power is
restored.
In this mode the CPU and all of the
Figure 2 on-chip peripherals go to sleep. The
device stops its oscillator. freezes all the
270126-4
10·357
inter AR·409
Down mode is the last one executed. The
only way for the part to exit this mode
is with a hardware reset.
AC311
RECTIFIER
AND A prototype of this terminal was built
REGULATOR and connecled to a MDS 800 develope-
ment system. The terminal communi-
Rl R2 cated with the host computer through the
serial channel at the rate of 2400 baud.
The 80C51 BH was emulated using
Vee
Cl Intel's ICE-51 in circuit emulator. The
.--It--+--l INT. 0 block diagram of the terminal is shown
aoC51BH J in Figure 4.
The CHMOS controller and LCD
.
combination provides a system that
requires only a single voltage power -
Figure 3
supply, and consumes less than 200
mW. The system's low power con-
activities and saves the information in its current in this mode is normally 10 to sumption eliminates the need for com-
internal RAM for as long as the supply 50 j.LA. plex, voltage-regulating hardware, and
voltage can be reduced to as low· as 2 Bit I of the Special Function Register cooling fans. The result is a lighter and
volts without running any risks of losing PCON controls this mode. The instruc- smaller computer terminal at a very low
the internal RAM information. Supply tion that puts the device in the Power cost. 0
II
KEYBOARD
, vi 80C51BH
vJ :::)
I'r
RAM
INT. 1
COMMUNICATION
LINE TO HOST I MODEM l SERIAL CHANNEL
COMPUTER
t
INT. 0 --)
.,.
DISPLAY
POWER FAILURE
DETECTOR
I
Figure 4
270126-5
10-358
li·I·I· IR,\NSt\t·/lo1\ .... ()~" 1:'>oIH SrRIAI. II.I·C!fW;\.IC\ Veil II \~ ..... o -I. NOVI MBE·R I'IH~
Using the 8051 Microcontroller with Resonant
Transducers
TOM WILLIAMSON
Abstract-Having to interface an analog Iransducer 10 a digilal conlrol transducer signal docs not restrict itself to the voltage range of
system Ihrough an analog-Io-digilal converter represents an expensive -0.5 to +5.5 V.
bOllleneck in Ihe development of many systems. Some transducer The 8051 is not sensitive to the rise and fall times of its input
companies are addressing this prohlem by developing proprietar) families
of resonant transducers.
signals. It detects transitions by sampling its pon pins at fixed
Resonant transducers are oscillators whose frequency depends in some intervals (once per machine cycle). and responds to a change
known wa)" on Ihe physical propl."rty being mrasured. The tledrical in the sequence of samples. If the slew rate of the transducer
output from these devices Is a train of rectangular pulses whose repelition signal is extremely slow. noise superimposed on the signal
nte encodes the value of the measurand. Changes in the measurand cause could cause the sequence of samples to show false transitions.
the frequ"ncy to shifl. The microcontroller detecls the frequency shift,
runs a uhdily check on iI. and cURve rio; it in software to the measurand
There could on that account be situations in which the
nlue. transducer signal should be buffered through a Schmitt Trigger
This paper discusses software interfacing techniques between resonant to square it up.
transducers and the 8051. Techniques for measuring frequency and
period are diS('ussed and compared for resolution and interrogation time. III. TIMER/COUNTER STRUCTURE IN THE 8051
The 80~1 is capable of performing these tasks in extremely short CPU
time. Requirements for obtaining n-bit resolution in the measurement are
The 8051 has two 16-bit timer/counters: Timer 0 and Timer
discussed. It Is determined Ihat it is always faster 10 evaluate the I. Both can be configured in software to operate either as
measurand 10 a jil;inn level of resolution by meMsurinjil; the period rather timers or as event counters.
than the frequency, even if the me-asurand is_ proportional to the In the "timer" function. the register is automatically
frequency rather than to th~ period. Numerical and softwar~ ~xamples are
incremented every machine cycle. Since a machine cycle in
prestnted to illustrate Ihe c·oncepls.
the 805 I consists of 12 clock periods. the timer is being
I. RESONANT TRANSDUCERS incremented at a constant rate of 1/12 the clock frequency.
M OST sensing transducers are not directly compatible
with digital controllers. because they generate analog
In the "counter" function. the register is incremented in
response to a I-to-O transition at its corresponding external
signals. A few transducer companies are developing proprie- input pin (7U or TI). The way this function works is the
tary families of sensors which generate signals that are more external input pin is sampled once each machine cycle (once
directly compatible with digital systems. These are not analog every 12 clock periods). and when the samples show a high in
sensors with built-in A-D conversion. but oscillators whose one cycle and a low in the next. the count is incremented.
frequency depends in some known way on the physical Note too that since it takes two machine cycles (24 clock
propeny being measured. periods) to recognize a I-to-O transition. the maximum count
The technology is applicable to vinually any type of rate is 1124 the clock frequency. If the clock frequency is 12
measurand: pressure. gas density. position. temperature. MHz. the maximum count rate is 500 kHz. There are no
force. etc. The sensor and microcontroller can operate from requirements on the duty cycle of the signal being counted.
the same supply voltage. so the sensor can in most cases The 8052. an enhanced version of the 8051 . has three 16-bit
connect directly to a pon pin on the microcontroller. timer/counters. two of which are identical to those in the 8051.
The nominal reference frequency of the output signal from· The third timer/counter can operate either as a 16-bit timer/
these devices is in the range of 20 Hz-500 kHz. depending on counter with automatic reload to a preset 16-bit value on
the design. A change in the measurand away from the rollover. or as a 16-bit timer/counter with a "capture" mode.
reference condition causes the frequency to shili by an amount In the capture mode a I-to-O transition at the T2EX pin causes
that is related to the change in the Illeasurand value. the current value in the counting register to the "captured"
Transducers are available that have a full-scale frequency shift into RAM. The third timer makes the 8052 panicularly easy to
of 2-1. The microcontroller detects the change in frequency or interface with resonant transducers.
period and ,'onvens it in soliware to the Illeasurand value.
IV. WHETHER TO MEASURE FREQUENCY OR PERIOO
II. CONNFl'IINl; IHE DI(;ITAL TRANSIlIIl'rR TO tHE 8051 Measuring the frequency requires counting transducer
Normally the transducer output can be connected directly to pulses for a lixed sample time. Measuring the period requires
one. of the 8051 pon pins. An exception would occur when the measuring elapsed 'time for a fixed number of transducer
pulses. For a given level of accuracy in the determination of
Manu~l.:rip( n!l'eivcd Cktohc:r ~5, 1984. the value of the measurand. it is usually faster to measure the
The authur is with Intel Corporalion. Chandler. AZ 85224. period. rather than the frequency. even if the measurand is
© 1985 IEEE
270434-1
10-359
intJ 8051 MICROCONTROLLER
WILLIAMSON' USING THE 8051 MICROCONTROLLER
proportional to frequency rather than period. However. both bytes wide. can be augmented in software in the timer
types of measurements will be discussed here. interrupt routine to three bytes. The 8051 has a DJNZ
Two timer/counters can be used. one to mark time and the instruction (decrement and jump if not zero) which makes it
other to count transducer pulses. If the frequency being easier to code the third timer byte to count down instead of up.
counted does not exceed 50 kHz or so. one may equally well If the third timer byte counts down. its reload value is the
connect the transducer signal to an external interrupt pin. and two's complement of what it would be for an up-counter. For
count transducer pulses in software. That frees one timer. with example. if the two's complement of the sample time is
very little cost in CPU time. FEOCOOH. then the reload value for the third timer byte would
be 02. instead of FE. The timer interrupt routine might then be
V. How TO MEASURE TRANSDUCER FREQUENCY
DJNZ THIRn.J'IMER..BYTE.OUT
Measuring the frequency means counting transducer pulses
MOV TLO.IIO
for some desired sample time. The count that is directly
MOV THO.IIOCH
obtained is T x F, where T is the sample time and F is the
MOV THIRn.J'IMER..BYTE.1I02
frequency. The full scale range is T x. (Fmax - Fmin). For
(Now read and clear the
n-bit resolution
transducer pulse counter.)
I LSB = Tx (Fmax - Fmin) . OUT: RETI
2" Interrupt latency will have no effect on the measurement if the
latency is the same for every sample time.
Therefore. the sample time required for n-bit resolution is The trouble with measuring the frequency is it is not only
2" slow. but a waste of the resolving power of the 805 I's timers.
T A timer with microsecond resolution is being used to mark off
Fmax-Fmin
100-ms time periods. The technique is nevertheless useful if
For example, 8-bit resolution in the measurement of a the timer is already serving other purposes (servicing a
frequency that varies between 5 and 10 kHz would require, display, perhaps), so that the sample time is coming relatively
according to this formula, a sample time of 51.2 ms. The free of charge. But in most cases it is faster and equally
maximum acceptable frequency count would be 51.2 ms x 10 accurate to measure the frequency by deriving it from a
kHz = 512 counts. The minimum would be 256 counts. measurement of the period.
Subtracting 256 from each frequency count would allow the
VI. How TO MEASURE THE PERIOD
frequency to be reported on a scale of 0 to FF in hex digits.
If Fmin and Fmax are closer together it takes more time to Measuring the period of the transducer signal means
resolve them. 8-bit resolution in the measurement of a measuring the total elapsed time over N-transducer pulses ..
frequency that varies between 7 and 9 kHz would require a The quantity that is directly measured is N x T, where T is
sample time of 128 ms. The maximum and minimum the period of the transducer sig~al in machine cycles. The
acceptable counts would be 1152 and 896. Subtracting 896 relationship between T in machine cycles and the transducer
from each frequency count would allow the frequency to be frequency F in arbitrary frequency units is
reported on a: scale of 0 to FF in hex digits.
To implement the measurement, one timer is used to Fxtal .
T=--pX(1/12)
establish the sample time. In this function it autoincrements
every machine cycle. A machine cycle consists of 12 periods
of the clock oscill~tor. The sample time can be converted to where Fxtal is the 805 I clock frequency. in.the same unit as F.
machine cycles by multiplying it by (Fxtal)/ I2, where Fxtal is The full scale range then is N x (Tmax - Tmin). For n-bit
the 805 I clock frequency. The timer needs to be preset so that resolution
it rolls over at the end of each sample time. Then it generates
all interrupt, and the interrupt routine reads and clears the Nx (Tmax - Tmin)
transducer pulse counter, and then reloads the timer with the I LSB=· .
2"
correct preset value.
The preset or reload value is the two's complement negative Therefore. the number of periods over which the elapsed time
of the sample time in machine cycles. For example, with a 12- should be measured is
MHz clock frequency, the reload value required to establish a
5 I. 2 ms sample time is 2"
N
Tmax-Tmin
(51.2 ms) x (12000 kHz)
-51200=3800 H.
12 However. N must also be an integer. It is logical to evaluate
the above formula (do not forget that Tmax and Tmin have to
In many cases the required sample time exceeds the capacity of be in machine cycles) and select for N the next higher integer.
a 16-bit timer. For example, establishing a 128 ms sample This selection gives a period measurement that has somewhat
time with a 12-MHz clock frequency requires a 3-byte timer more than n-bit resolution. which mayor may not be
with a reload of FEOCOOH. The 8051 timer, being only 2: acceptable. depending on the overall requirements of the
270434-2
10-360
intJ 8051 MICROCONTROLLER
IEEF. TRANSACTIONS 0'/ INDUSTRIAL ELECTRONICS. VOL. IE·l2. NO.4. NOVEMBER 19R5
system. It can be scaled back to n-bit resolution, if necessary, timer also generates an interrupt. The interrupt routine would
by the following computation: then read and reset the timer.
NT-NTmin The advantage of this method is thaI the transducer signal
reported value = NTmax ~ NTmin has direct access to the timer gate, with the result that
variations in the interrupt response time cease to be a fact"r
where NT is the elapsed time measured 'over N periods. The timer can be read and cleared any time before the next
The computation can be done in math if a suitable divide high in the transducer output.
routine is available in the software. For 8-bit resolution it is
entirely reasonable to find the reported value in a look-up VIII. DERIVING FREQUENCY FROM A PERIOD MEASUREMENT
table, which would take up somewhat more than one page in We now consider the problem of measuring the transducer
ROM. In fact, the look-up table would contain NTmax - frequency to n-bit resolution by deriving it from a direct
NTmin entries. measurement of the period. The advantage of this technique is
For example, suppose we want 8-bit resolution in the speed. It is always faster to measure period than frequency.
measurement of the period of a signal whose frequency varies But il is important 10 end up with a frequency value that has the
from 5 to 10 kHz. If the clock frequency is 12 MHz, then same resolution and accuracy as a directly measured fre-
Tmax is (12 000 kHz)I(12 x 5 kHz) = 200 machine cycles, quency. Two questions need to be addressed.
and Tmin is 100 machine cycles. The timer needs to be on then
I) To achieve n-bit resolution in the calculated frequency,
for N = 2.56 periods, according to the formula. Using N = 3
how much resolution is required in the period?
periods will give maximum and minimum NT values of 600
2) Having measured the period to the required resolution,
and 300 machine cycles. This is somewhat more than 8-bit
what is the most efficient way to calculate the frequency?
resolution. It can be scaled to 8 bits with a 300-byte look-up
table, if desired. These questions will be addressed one at a time.
To implement the measurement, one timer is used to
measure the elapsed time NT. Enabling its interrupt is IX. RESOLUTION REQUIREMENTS
optional. The timer interrupt could be used to indicate a short In general, n-bit resolution in the frequency derivation
or open in the transducer circuit. requires somewhat more than n-bit resolution in the period
Then the transducer is connected to one of the external measurement. How much more? It will be demonstrated
interrupt pins (INTO or INTI), and this interrupt is configured' presently that if the transducer frequency varies over a 2-to-1
to the transition-activated mode. In the transition-activated range, the frequency can be calculated with n-bit resolution
mode every I-to-O transition in the transducer output will from period measurements that have (n + I I-bit resolution.
generate an interrupt. The interrupt routine counts transducer The more practical form of the question is over how many
pulses, and when it gets to the predetermined N. it reads and periods (N) must the transducer signal be sampled to' obtain
clears the timer. For example the required resolution in F? And so, we commence a
calculation of N.
DJNZ PULSES ,OUT The basic calculation of frequency from N x T (which we
MOV PULSES,fi..PERlODS shall call NT) is straightforward:
(Read and clear timer.)
OUT: RETI F=N/(NT).
If other interrupts are also to be enabled, the one connected to The relationship between an increment dF in the calculated
the transducer should be set to Priority I, and the others to frequency due to an increment d(NT) in the measured period
Priority O. This is to control the interrupt response time. The is, therefore,
response time will not affect the measurement if it is the same
for every measurement. Variations in the response time will, N
dF= - - - d(NT)
however, affect the measurement. Selling the pulse-counter . (NT)2
interrupt to Pnority I and all others to Priority 0 will minimize
variations in the response time. The response time will then be F2
limited to range from 3 to 8 machine cycles. =-'N d(NT).
VII. PuLSEWIDTH MEASUREMENTS
This equation says the value of an LSB in the calculated
The 80S I timers have an operating mode which is particu- frequency is (F2)/ N x the value of an LSD in NT. Then tile
larly suited' to pulsewidth measurements, and may be useful maximum value that an LSB in the calculated frequency can
here if the transducer has a fix~d duty cycle, or if the have is (Fmax)1/N x the value of an LSB in NT. For the
transducer output is pulsewidth modulated instead of fre- calculated frequency to have n-bit resolution over the entire
quency modulated by the measurand. range of frequencies, the value of its LSD must never exceed
. In this mode the timer is turned on by the on-chip circuitry (Fmax - Fmin)12". Therefore, the measurement requires
in response to an input high at the external interrupt pin, and
off by an input low. The external interrupt itself is enabled, so (Fmax)1 . Fmax - Fmin
the same I-to-O transition from the transducer that turns off the
--N-X(I LSB in NT)s 2"
270434-3
10-361
8051 MICROCONTROLLER
WILLIAMSON, USING THE BOll MICROCONTROLLER
The required resolution in NT is. therefore. X. COMPUTING ·THE FREQUENCY FROM THE PERIOD
Nx (Fmax - Fmin) The periOd measurement leaves one with a 16-bit integer,
I LSD in NTs l . which is N x T (or NT) in machine cycles. The conversion to
2" x (Fmax) frequency is straightforward:
Now. to say that NTis measured with m-bit resolution means F=N/(NT) periods/machine cycle.
I LSD in NT= NX(lIFmin-I/Fmax) .
The quantity of interest is probably not F, but a normalized
2m measure of the amount by which F exceeds .its. minimum
Substituting. this value for I LSD into the .required resolution acceptable value. This quantity represents, through the trans-
and sol ving for 2m yields ducer's transfer function, the "reported value" of the
measurand, and this quantity is an n-bit integer whose value
Fmax ranges from 0 (all bits = 0) to full scale (all bits. = I). This
2m~-.-x2".
Fmm normalized frequency is
Then the requirement on m is F-Fmin
f= Fmax-Fmin
m ~ n + _I_n...:(Fi_m_a_x_/Fm_i....:n):....
In (2) . Fmin
= x(FIFmin-1\
Fmax-Fmin .
It can be stated with some certainty. then. that if the transducer
frequency varies over a range of 2-to-I, the frequency can be Using F = NI(NT) and F min = NI(NT max) a1low~ the
calculated with 8~bit resolution from a period measurement normalized frequency to be written .
that has 9-bit resolution. If the frequency variation is less than
2-to-I, another full bit of resolution in the period measurement f Fmin' x NTmax - NT
is not needed. Fmax - Fmin NT
To obtain m-bit resolution in NT, N must satisfy
To get a handle on what kinds of numbers are involved here,
.2 m , consider the situation where 8-bit resolution is required in f,
N~ -T!=ma-x--"'"'"-=:Tm,.-:-in- and in which Fxtal = 12 MHz, Fmax = 10 kHz, and Fmin
= S kHz. We have previously determined that for this set of
Substituting for 2"', and using Tmax = IIFmin and Tmin = conditions, N = 6 periods gives sufficient resolution in the
IIF max, gives the result that period measurement to satisfy the resolution requirement in F
.(and inf)o With a 12 MHz clock frequency, Tmax in machine
N~ (Fmax)l. x 2". cycles is (12 000 kHz)/(l2 x S kHz) = 200 machine cycles,
Fmax-Fmin so NTrnax is 6 x 200 = 1200 machine cycles. The
calculation for f then becomes
It should be nOted that the units'· of frequency here are
periods/machine cycle, since the 80S I measures time by f= 1200-NT.
counting machine cycles. The conversion factor between Hz NT
and periods/machine cycle is 12/(c1ock frequency). So the
requirement on N can also be written . The minimum acceptable value that NT can have is (N x
7inin + I), where Tmin = (12000 kHz)/(12 x 10 kHz) =
Fmax Fmax 100 machine cycles. Then N x Tmin ;" 6 x 100 = 600
N~ x--x 12x2" machine cycles. The allowable values for NT are then 601-
Fmax - Fmin Fxtal 1200 machine cycles, II total of 599 different values.
The fastest way to "calculate" f would be with a S99-byte
where Fxtal is the 80S I clock frequency in the same units as
look-up table. This method has the added advantage that
Fmax and Fmin. This is the number of transducer pulses over
nonlinearities in the transfer function between frequency and
which the transducer signal must be sampled to achieve the
measurand can be built into the table. Look-up tables are
required solution in F.
facilitated in the 805 I by the MOVe A,@A+ PC, and Move
For example, suppose that 8-bit resolution is required in F,
A,@A+DPTR instructions. DPTR is a 16-bit "data pointer"
where Fmax = 10 kHz and Fmin = S kHz, and that Fxtal
register in the 80S I. Its two bytes can be individually
= 12 MHz. Then the above calculation shows that N = 6
addressed as DPL (low byte) and DPH (high byte). .
periods gives sufficient resolution in the periOd measurement
In the example under discussion, it will be necessary to load
to satisfy the resolution requirement in F. Six periods will take
DPTR with the address of the first byte of the look-up table,
0.6-1.2 ms of sampling time, on that frequency range. Recall
less 601, plus ·the 2-byte value of NT. The software that
that the sample time for a direct frequency measurement of the
accesses the table might then take the following form:
same signal and to the same resolution was earlier calculated
to be SI.2 ma. . 'rABLE EQU (address of first table entry)
270434-4
10-362
inter 8051 MICROCONTROLLER
WHo I'RASS,\('fIOSS os INUl','iTRIAI. U.J:('TRONICS. VCJI. If:· 1.2. NO ~. ,~OVEMHf-:R I"'H~
c-IVI[)f. HDI)lINf:
·,,;mf"'dt.,.
'lo..ot I",nl
.,.'nUfTllnoit oJ"
I" ... tll.n " .."nfOrdtOI ".nOlftlnator iol'"
;'1" Intll!'~.r • .. nil
" .... '"l'r-t~."· dt'nOll'llnat.'Jr Uu"t.fO"t 1\ c.f th. flJrm
-,
;,., • III.. mt'roltnr
If numl!'rolt(1I dpnomlflator 4 " " CJ '!'I~. qn ... 1
,; qn '" 0 thlll numpratC'r 2 nume-ratar
pi '!.e numf'rotltor "" 2 I nutnf'ratol'" • dlo'nOmlnatol
lnrrpmt'nt n
~n~... t'llp
Fig. I. A divide algurilhm.
MOV A,NLOW(TABLE-601) Since the clock signal is normally generated by a crystal
ADD A,N'[J.O oscillator, the oscillator accuracy normally far exceeds the
MOV DPL,A quantizing error inherent in the finite (n-bit) resolution.
MOV A,NHIGH(TABLE-60I) As was previously mentioned, interrupt response time does
ADDC A,NUiI not introduce an error into the measurement itself, but
MOV DPH,A variations in the interrupt response time can. Interrupt
CLR A response time in the 8051 can vary from 3 to 8 machine cycles,
MOVC A,@A+DPTR_ depending on what instruction is in progress at the time the
interrupt is generated. This would represeill an error of ± 5
At this point the accumulator contains the 8-bit value of f-
counts in the measured value of NT during a period
It is perfectly reasonable to decide that a 599-byte look-up
measurement. An error of ± 5 counts in NT does not
table is unwieldy. Its advantages are speed and built-in error
necessarily. translate to ± 5 LSB's in the final result, but it
correction. But a reasonably fast divide algorithm can be
might still represent an error that exceeds the resolution.
written to this specific purpose, making use of a priori
In a direct frequency measurement variations in the inter-
knowledge about the sizes of the numbers that are involved in
rupt response time would represent an error of ± 5 p.s in the
the computation. It helps to know that in this example the
sample time.
numerator is never going to be larger than 599 and the
If these kil.ds of errors are unacceptable there are ways to
denominator is always greater than the numerator.
deal with them. In period measurements, if the duty cycle of
A complete discusSion of divide routines is beyond the
the transducer is constant, the pulsewidth measurement
scope of this paper, but a suitable divide algorithm for this
technique, previously described, can be used. Its advantage is
specific application is shown in Fig. I. Reference [II calls this
that it gates the timer off when the interrupt is generated,
the Restoring division algorithm. It is particularly well suite~
rather .than when the interrupt is responded to.
to the 8051, because" <" comparisons are greatly facilitated
In other cases one can simply increase the sample time
by the 8051's CJNE (compare and jump if not equal)
above the minimum required to obtain the desired resolution.
instruction. CJNE A ,B,rel, executes a relative jump if A does
For example, if the measurement requires 8-bit resolution, one
not equal B. More importantly to this application, the
can design the software for an II-bit resolution and truncate
instruction sets the carry flag if A < B.
the result to 8 bits.
XI. ACCURACY AND RESOLUTION
The accuracy with which the 8051 will measure the
frequency or period of the transducer signal depends on two R~F~R~Nns
things: the accuracy of the clock oscillator and variations in III Davil' tl al.. 1);l{ilu/ S)'.'i/ems wilh Algorithm Implementation.
the interrupt response time. New Ynrk: Wiley. 19K.I.
270434-5
10-363
8051
SOFTWARE PACKAGES
• Choice of hosts: • LlB51 Librarian which lets
PCDOS 3.0 based IBM* PC XT/AT*, programmers create and maintain
iRMX®06, iPDSTM System, Series II, libraries of software object modules
Series III, and Series IV
0051 Software Development Package
• Supports all members of the Intel Contains the following:
MCS® -51 architecture
• 0051 Macro Assembler which gives
PL/M51 Software Package Contains the symbolic access to 0051 hardware
following: features
• PL/M51 Compiler which is designed to • RL51 Linker and Relocator program
support all phases of software which links modules generated by the
implementation assembler
.RL5.1 Linker and Relocator,which • LlB51 Librarian which lets
enables programmers to develop programmers create and maintain
software in a. modular fashion libraries of· software object modules
LEGEND
D INTEL DEVELOPMENT
TOOLS AHDOTMER
-----.
10'
I,, _____ 1I
PRODUCTS
MCS"aS1
SOFTWARE TOOLS •
o USEA-CODED
SOFTWARE
162771-1
Figure 1. MCS® -51 Program Development Process
·IBM and AT are registered trademarks of International Business Machine Corporation.
October 1987
10-364 Order Number: 162771-005
8051 Software Packages
PL/M 51 SOFTWARE PACKAGE
• High-level programming language for
the Intel MCS® -51 single-chip • Allows programmer to have complete
control of microcomputer resources
microcomputer family
• Compatible with PL/M 80 assuring • Extends high-level language
programming advantages to
MCS® -80/85 design portability microcontroller software development
• Enhanced to support boolean
processing • Improved reliability, lower maintenance
costs, increased programmer
• Tailored to provide an optimum.
balance among on-chip RAM usage,
•
productivity and software portability
Includes the linking and relocating
code size and code execution time utility and the library manager
• Produces relocatable object code
which is linkable to object modules • MCS®
Supports all members of the Intel
-51 architecture
generated by all other 8051 translators
PL/M 51 is a structured, high-level programming language for the Intel MCS-51 family of microcomputers. The
PL/M 51 language and compiler have been desi!'jned to support the unique software development require-
ments of the single-chip microcomputer environment. The PL/M language has been enhanced to support
Boolean processing and· efficient access to the microcomputer functions. New compiler controls allow the
programmer complete control over what microcomputer resources are u~ed by PLIM programs.
PLIM 51 is largely compatible with PL/M 80 and PLIM 86. A significant proportion of existing PLIM software
can be ported to the MCS-51 with modifications to support the MCS-51 architecture. Existing PLIM program-
mers can start programming for the MCS-51 with a small relearning effort.
PL/M 51 is the high-level alternative to assembly language programmi~g for the MCS-51. When code size and
code execution speed are not critical factors, ·PL/M 51 is the cost-effective approach to developing reliable,
maintainable software.
The PL/M 51 compiler has been designed to support efficiently all phases of software implementation with
features like a syntax checker, multiple levels of optimization, cross-reference generation and debug record
generation. . .
ICETM 5100, ICE 51, and EMV51 are available for on-target debugging ..
Software available for PC DOS 3.0 based IBM· PC XT/AT* Systems.
LI!GEND
o USEA-CODED
SOFlWARE
Figure 2: PL/M51 Software Package
162771-2
10-365
intJ 8051 Software Packages
PL/M 51 COMPILER
FEATURES Interrupt Handling
Major features of the Intel PLIM 51 compiler and A procedure may be defined with the INTERRUPT
programming language include: attribute. The compiler will generate code to save
and restore the processor status, for execution of
the user-defined interrupt handler routines.
Structured Programming
PL/M source code is developed in a series of rriod- Compiler Controls
ules, 'procedures, and blocks. Encouraging program
modularity in this manner makes programs more The PLIM 51 compiler offers controls that facilitate
readable, and easier to, maintain and debug. The such features as:
language becomes more flexible, by clearly defining - Including additional PL/M 51 source files from
the scope of user variables (local to a private proce- disk
dure, for example).
- Cross-reference
- Corresponding assembly language code in the
Language Compatibility listing file
PL/M 51 object modules are compatible with object
modules generated by all other MCS-51 'translators. Program Addressing Control
This means that PLIM programs may be linked to
programs written in any other MCS-51 language. The PL/M 51 compiler takes full advantage of pro-
gram addressing with the ROM (SMALL/MEDIUMI
Object modules are compatible with In-Circuit Emu- LARGE) control. Programs with less than 2 KB code
lators and Emulation Vehicles for MCS-51 proces- space can use the SMALL or MEDIUM option to
sors: the DEBUG compiler control provides these generate optimum addressing instructions. Larger
tools with symbolic debugging capabilities. ' programs can address over the full 64 KB range.
Supports Three Data Types Code Optimization
PL/M makes use of three data types for various ap- The PL/M 51 compiler offers four levels of optimiza-
plications. These data types range from one to six- tion for significantly reducing overall program size.
teen bits and facilitate various arithmetic, logic; and :..... Combination or "folding" of constant expres-
address functions: sions; "Strength reductions" (a shift left rather
- Bit: a binary digit than multiply by 2)
- Byte: 8-bit unsigned number or, - Machine code optimizations;. elimination of su-
- Word: 16-bit unsigned number. perfluous branches
- Automatic overlaying of on-chip RAM variables
Another powerful facility allows the use of BASED - Register history: an off-chip variable will not be
variables that map !'(lore than one variable to the reloaded if its value is available in a register.
same memory location. This is especially useful for
passing parameters, relative and absolute address-
ing, and memory allocation.
Error Checking
The PLIM 51 compiler has a very powerful feature
Two Data Structuring Facilities to speed up compilations. If a syntax or program er-
ror is detected, the compiler will skip the codegen-
PLIM 51 supports two data structuring facilities. eration and optimization passes. This usually yields
These add flexibility to the referencing of data stored a 2X performance increase for compilation of pro-
in large groups. grams with errors.
- Array: Indexed list of same type data elements
- Structure: Named collection of same or different A fully detailed set of programming and compilation
type data elements error messages is provided by the compiler and us-
er's guide.
- Combinations of Both: Arrays of. structures or
structures of arrays.
10-366
intJ 8051 Software Packages
BENEFITS Lower Development Cost
PLIM 51 is designed to be an efficient, cost-effec- Increases in programmer productivity translate im-
tive solution to the special requirements of MCS-51 mediately into lower software development costs
Microsystem Software Development, as illustrated because less programming resources are required
by the following benefits of PL/M use: for a given programmed function.
Low Learning Effort Increased Reliability
PLIM 51 is easy to learn and to use, even for the PLIM 51 is designed to aid in the development of
novice programmer. reliable software (PL/M programs are. simple state-
ments of the program algorithm). This substantially
reduces the risk of costly correction of errors in sys-
Earlier Project Completion tems that have already reached full production
status, as the more simply stated the program is, the
Critical projects are completed much earlier than more likely it is to perform its intended function.
otherwise possible because PL/M 51, a structured
high-level language, increases programmer produc-
tivity. Easier Enhancements and
Maintenance
Programs written in PL/M tend to be self-document-
ing, thus easier to read and understand. This means
it is easier to enhance and maintain PLIM programs
as the system capabilities expand and future prod-
ucts are developed. .
RL51 LINKER AND RELOCATOR
• Links modules generated by the • Enables modular programming of
assembler and the PL/M compiler software-efficient program
• Locates the linked object to absolute development
memory locations· • Modular programs. are easy to
understand, maintainable and reliable
The MCS-51 linker and relocator (RL51) is a utility which enables MCS-51 programmers to develop software in
a modular fashion. The utility resolves all references between modules and assigns absolute memory loca-
tions to all the relocatable segments, combining relocatable partial segments with the same name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The total number of allowed symbols in user-developed software is very large because the assembler number
of symbols' limit applies only per module, not to the entire program. Therefore programs can be more readable
and better documented. RL51 can be invoked either manually or through a batch file for improved productivity.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
maintained. .
RL51 produces two files. The absolute object module file can be directly executed by the MCS-51 family. The
listing file shows the results of the Iink/\locate process.
10-367
inter 8051 Software Packages
LIB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to call only object modules that are required to satisfy
create and maintain libraries of software object mod- external references.
ules. With this utility, the customer can develop stan-
dard software modules and place them in libraries, .Consequently, the librarian enables the customer to
which programs can access through a standard in- port and reuse software on different projects-there-
terface. When using object libraries, the linker will by maintaining the customer's software investment.
ORDERING INFORMATION
Order Code Operating Environment
D86PLM51 PL/M51 Software for PC DOS 3.0 Systems
R86PLM51 PL/M51 Software for iRMX 86 Systems
Documentation Package SUPPORT:
PLIM 51 User's Guide Hotline Telephone Support, Software Performance
Report (SPR), Software Updates, Technical Re-
MCS-51 Utilities User's GLiide ports, and monthly Technical Newsletters are avail-
able.
10-368
inter .8051 Software Packages
8051 SOFTWARE DEVELOPMENT PACKAGE
• Symbolic relocatable assembly • Encourage modular program design for
language programming for 8051 maintainability and reliability
microcontrollers
• Macro Assembler features conditional
• Extends Intellec® Microcomputer assembly and macro capabilities
Development System to support 8051
• Supports all members of the Intel
program development MCS® 51 architecture
• Produces Relocatable Object Code
which is linkable to other 8051 Object
Modules
The 8051 software development package provides development system support for the powerful 8051 family
of single chip microcomputers. The package contains a symbolic .macro assembler and relocation/linkage
utilities.
The assembler produces relocatable object modules from 8051 macro assembly language instructions. The
object code modules can be linked and located to absolute memory locations. This absolute object code may
be used to program the 8751 EPROM version of the chip. The assembler output may also be debugged using
the new family of ICE 5100 emulators or with the ICE-51TM in-circuit emulator.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide soft-
ware compatibility-between the two families of microcontroliers.
Software available for PC DOS 3.0 based IBM" PC XT/AT Systems.
162771-3
10-369
8051 Software Packages
8051·MACRO ASSEMBLER
• Supports 8051 family program • Object files are linkable and locatable
development on Intellec® ,
• Provides software support for many
Microcomputer Development Systems addressing and data allocation
• Gives symbolic access to powerful capabilities
8051 hardware features
• Symbolic Assembler supports' symbol
• Produces object file, listing file and table, cross-reference, macro
error diagnostics capabilities, and conditional assembly
The 805.1 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language modules into link-
able and locatable object code modules. Assembly language mnemonics are easier to program and are more
readable than binary or hexadecimal machine instructions. By allowing the programmer to give symbolic
names to memory locations rather than absolute addresses, software design and debug are performed more
quickly and reliably. Furthermore, since modules are linkable and relocatable, the programmer can do his
software in modular fashion. This makes programs easy to understand, maintainable and reliable.
The assembler supports macro definitions and calls. This is a convenient way to program a frequently used
code sequence only once. The assembler also provides conditional assembly capabilities. .
Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was
defined and referenced.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These
features include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic.
The assembler also provides symbolic access to hardware registers, 1/0 ports, control bits, and RAM address-
es. ASM51 can support all memberS of the 8051 family.
Math routines are enhanced by the. MUltiply and DIVide instructions.
If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which
are included in the assembly listing or on another file. Program testing may be performed by using the iUP
Universal Programmer and iUP F87/51 personality module to program the 8751 EPROM version of the chip.
ICE 5100, ICE51 a~d EMV51 are available for program debugging.
RL51 LINKER ANDRELOCATOR PROGRAM
• Links modules generated by the • Enables modular programming of
assembler software for efficient program
• Locates the linked object to absolute development
memory locations • Modular programs are easy to
understand, maintainable and reliable
The 8051 linker and relocator (RL51) is a utility which enables 8051 programmers to develop software in a
modular fashion. The linker resolves all references between modules and the relocator assigns absolute
memory locations to all the relocatable segments, combining relocatable partial segments with the same
name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The number of symbols in the software is very large because the assembler symbol limit applies only per
module not the entire program. Therefore programs can be more readable and better documented;
Modules can be saved and used on different programs. Therefore the software investment of ·the customer is
maintained.
10-370
intJ 8051 Software Packages
RL51 produces two files. The absolute object module file can be directly executed by the 8051 family. The
listing file shows the results of the link/locate process.
LIB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to create and maintain libraries of software object modules.
With this utility, the customer can develop standard software modules and place them in libraries, which
programs can access through a standard interface. When using object libraries, the linker will call only object
modules that are required to satisfy external references.
Consequently, the librarian enables the customer to port and reuse software on different projects-thereby
maintaining the customer's software investment.
ORDERING INFORMATION
Order Code Operating Environment
D86ASM51 8051 Assembler for PCDOS 3.0 Systems
R86ASM51 8051 Assembler for iRMX 86 Systems
Documentation Package: SUPPORT:
MeS-51 Macro Assembler User's Guide Hotline Telephone Support, Software Performance
Reporting (SPR), Software Updates, Technical Re-
MeS-51 Utilities User's Guide for 8080/8085 ports, Monthly Newsletter available.
Based Development System
MeS-51 8048-to-8051 Assembly Language Con-
verter Operating Instructions for ISIS-II Users
10-371
inter iDCX 51
DISTRIBUTED CONTROL EXECUTIVE
• Supports MCS®-S1 and RUPITM-44 ,
• Small-2.2K Bytes.
•
Familes of 8-Bit Microcontrollers
• Reliable
.Real-Time, Multitasking Executive
- Supports up to 8 Tasks at Four • Simple User Interface
Priority Levels • Dynamic Reconflguration Capability
• Local and Remote Task Communication • Compatible with BITBU5TM/Distributed
Control Modules (iDCM) Product Line
The iDCX 51 Executive is compact, easy to use software for development and implementation of applications
using the high performance 8-bit family of 8051 microcontrollers, including the 8051,8044, and 8052. Like the
8051 family, the iDCX 51 Executive is tuned for real-time control applications requiring manipulation and
scheduling of more than one task, and fast response to external stimuli.
The MCS-51 microcontroller family coupled with iDCX 51 is a natural combinati(;m for applications such as data
acquisition and monitoring, process control, robotics, and machine control. The iDCX 51 Executive can signifi-
cantly reduce applications development time; particuladyBITBUS distributed control environments. .
The iDCX 51 Executive is available in two forms, either as configurable software on diskette or as preconfig-
ured firmware within the 8044 BEM BITBUS microcontroller.
280176-1
Figure 1. iDCX 51 Distributed Control Executive
·XENIXTM is a trademark of Microsoft Corporation.
October 1987
10-372 Order Number: 280176-003
inter iDCX51
MICROCONTROLLER SUPPORT events: interrupts, timers, and messages ensuring
the application system always responds to the envi-
The iDCX 51 Executive is designed to support the ronment appropriately.
MCS-51 and RUPI-44 families of 8-bit microcontrol-
lers. MCS-51 microcontrollers that are supported in-
clude the 8051, 80C51 , 8052, 8031, 8032, and 8751 Task Management
devices. The· RUPI"44 microcontrollers include the
8044, 8344, and 8744 devices. All of these micro- A task is a program defined by the user to execute a
controllers share a common 8051 core. particular control function or functions. Multiple pro-
grams or tasks may be required to implement a par-
ticular function such as "controlling Heater 1". The
ARCHITECTURE iDCX 51 Executive recognizes three different task
states as one of the mechanisms to accomplish
scheduling of up to eight tasks. Figure 2 illustrates
Real-time and Multitasking the different task states and their relationship to one
another.
Real-time control applications must be responsive to
the external environment and typically involve the The scheduling of tasks is priority based. The user
execution of more than one activity (task or set of can prioritize tasks to reflect their relative impor-
tasks) in response to different external stimuli. Con- tance within the overall control scheme. For in-
trol of an industrial drying process is an example. stance, if Heater 1 must go off line prior to Heater 2
This process could require monitoring of multiple then the task associated with Heater 1 shutdown
temperatures and humidity; control of fans, heaters, could be assigned a higher priority ensuring the cor-
and motors that must respond accordingly to a vari- rect shutdown sequence. The RQ WAIT system call
ety of inputs. The iDCX 51 Executive fully supports is also a scheduling tool. In this example the task
applications requiring response to stimuli as they oc- implementing Heater 2 shutdown could include an
cur, i.e., in real-time. This real-time response is sup- instruction to wait for completion of the task that im-
ported ·for inultiple tasks often needed to implement plements Heater 1 shutdown.
a control application.
The iDCX 51 Executive allows for PREEMPTION of
Some of the facilities precisely tailored for develop- a task that is currently being executed. This means
ment and implementation of real-time control appli- that if some external elient occurs such as a cata-
cation systems provided by the iDCX 51 Executive strophic failure of Heater 1; a higher priority task as-
are: task management, interrupt handling, message sociated with the interrupt, message, or timeout re-
passing, and when integrated with communications sulting from the failure will·preempt the running task.
support, message passing with different microcon- Preemption ensures the emergency will be respond-
trollers. Also, the iDCX 51· Executive is driven by ed to immediately. This is crucial for real-time control
application systems.
Running Task Executes ROWAIT or RODELETE
I 1_--:::--:-'::-_--:--,-_-:-::-::---=--:--:-_ _-11 . RUNNING
READY/+-
Event Occurs Assoc. wi Asleep Task wi
.Higher Priority Than Running Task.
J
Event Occurs Assoc.
wlAsleepTask wi
Lower Priority
Than Running
Task
Event Occurs Assoc. wi Asleep Task wi
I ASLEEP 1
Higher Priority Than Running Task
Running Task Executes ROWAIT
280176-2
Figure 2. Task State Transition Diagram
10-373
iDCX 51
Interrupt Handling REMOTE TASK COMMUNICATION
The iDCX 51 Executive supports five interrupt The iDCX 51 Executive, system calls can support
sources as shown in Table 1. Four of these interrupt communication to tasks on remote controllers. This
sources, excluding timer 0, can be assigned to a feature makes the iDCX 51 Executive ideal for appli-
task. When one of the interrupts occurs the task as- cations using distributed architectures. Providing
sociated with it becomes a running task (if it were communication support saves significant application
the highest priority task in a ready state). In this way, development time and allows for more effective use
the iDCX 51 Executive responds to a number of in- of this time. Intel's iDCM product line combines
ternal and external stimuli including time intervals hardware and software to provide this function.
desig'ned by the user.
In an iDCM system, communication between nodes
Table 1.IDCX 51 Interrupt Sources occurs via the BITBUS microcontroller interconnect.
The BITBUS microcontroller interconnect is a high
Interrupt Source Interrupt Number performance serial control bus specifically intended
External Request 0 OOH for use in applications built on distributed architec-
tures. The iDCX 51 Executive provides BITBUS sup-
Timer 0 01H port.
External Request 1 02H
Timer 1 03H BITBUSTM/iDCM COMPATIBLE
Internal Serial Port 1 04H
A pre-configured version of the iDCX 51 Executive
implements the BITBUS message format and pro-
vides all iDCX 51 facilities mentioned previously:
Message Passing task management, interrupt handling, and message
passing. This version of the Executive is supplied in
The iDCX 51 Executive allows tasks to interface with firmware on the 8044 BEM with the iDCM hardware
one another via a simple message passing facility. products: the iSBXTM 344A BITBUS Controller MUL-
This message passing facility can be extended to TIMODULETM; the iDCX 344A BITBUS controller
different processors when communications support board for the PC; and the iRCB boards.
is integrated within a BITBUS/iDCM system, for ex-
ample. This facility provides the user with the ability DeSigners who want tO',use the iDCX executive on
to link different functions or tasks. Linkage between an Intel BITBUS board should purchase either
tasks/functions is typically required to support de- DCS110 or DSC120 BITBUS software. Both of these
velopment of complex control applications with mul- products include an interface library to iDCX 51 pro-
tiple sensors (input variables) and drivers (output cedures and other development files. It is not neces-
variables). For instance, the industrial drying process sary to purchase the iDCX 51 Executive.
might require a dozen temperature inputs, six mois-
ture readings,' and control of: three fans, two con~
veyor motors, a dryer motor, and a pneumatic con- , SIMPLE USER INTERFACE
veyor. The data gathered from both the temperature
and humidity sensors could be processed. Two The iDCX 51 Executive's capabilities are utlilized
tasks might be required to gather the data and pro- through system calls. These interfaces have been
cess it. One task could perform a part of the analy- defined for ease of use and simplicity. Table 2 in-
sis, then include a pointer to the next task to com- cludes a listing of these calls and their functions.
plete the next part of the analysis. The tasks could Note that tasks may be created at system initializa-
continue to move between one another. tion or run-time using the CREATE TASK call.
Other Functions such as GET FUNCTION IDS, AL-
LOCATE/DEALLOCATE BUFFER, and SEND MES-
SAGE, support communication for distributed archi-
tectures.
10-374
intJ iDCX 51
Table 2.IDCX 51 System Calls
Call Name Description
TASK MANAGEMENT CALLS
RQ$CREATE$TASK Create and schedule a new task.
RQ$DELETE$TASK Delete specified task from system.
RQ$GET$FUNCTION$IDS Obtain the function IDs of tasks currently in the system.
RQ$ALLOCATE Obtain a message buffer from the system buffer pool.
RQ$DEALLOCATE Return a message buffer to the system buffer pool.
RQ$SEND$MESSAGE Send a message to specified task.
RQ$WAIT Wait for a message event.
MEMORY MANAGEMENT CALLS
RQ$GET$MEM Get available system memory pool memory.
RQ$RELEASE$MEM Release system memory pool memory.
INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT Temporarily disable an interrupt.
RQ$ENABLE$INTERRUPT Re-enable an interrupt.
RQ$WAIT Wait for an interrupt event.
TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL Establish a time interval.
RQ$WAIT Wait for an interval event.
Another feature that eases application -development gether, then when the system is initialized, all four -
is automatic register bank allocation. The Executive tasks will be put into a READY state. Then, the high-
will assig'n tasks to register banks automatically un- est priority task will run.
less a specific request is made. The iDCX 51 Execu-
tive keeps track of the register assignments allowing The DCX 51 user cian control several system con-
the user to concentrate on other activities. stants during the configuration process (Table 3).
Most of these constants are fixed, but by including
an Initial Data Descriptor (100) in an ITO chain, the
SYSTEM CONFIGURATION system clock priority, clock time unit, and buffer size
can be modified at run-time.
The user configures an iDCX 51 system simply by
specifying the initial set of task descriptors and con- This feature is useful for products that use the same
figuration values, and linking the system via the software core, but need minor modification of the
RL 51 Linker and Locator Program with user pro- executive to better match the end application. The
grams. initial data descriptor also allows the designer, who
is using an 8044 BEM BITBUS Microcontroller, to
Each task that will be running under control of the modify the preconfigured (on-chip) iDCX 51 Execu-
executive has an Initial Task Description (ITO) that tive.
describes it. The ITO specifies to the executive the
amount of stack space to reserve, the priority level Programs may be written in ASM 51 or PL/M 51.
of the task (1-4), the internal memory register bank Intel's 8051 Software Development Package con-
to be associated with the task, the internal or exter- tains both ASM 51 and RL 51. Figure 3 shows the
nal interrupt associated with the task, and a function software generation process.
10 (assigned by the user) that uniquely labels the
task. The ITO can also include a pointer to the ITO
for the next task. In this wayan ITO "chain" can be
formed. For example, if four ITO's are chained to-
10-375
inter IDCX51
Table 3. DCX 51 Configuration Constants
Constant Name Description
RO CLOCK PRIORITY The priority level of the system clock.
RO CLOCK TICK The number of time cycles in the system clock basic time unit (a "tick").
ROFIRSTITD The absolute address of the first ITO in the ITO chain.
RO MEM POOL ADR The start address of the System Memory Pool (SMP) in Internal Data RAM.
RO MEM POOL LEN The length of the SMP.
RORAMIDD The absolute RAM address of where iDCX 51 checks for an Initial Data
Descriptor (100) during initialization.
RO SYS BUF SIZE The size, in bytes, of each buffer in the system buffer pool.
WRITE ASSEMBLE/ LlNK/ LOAD/EXECUTE
SOURCE CODE COMPILE LOCATE
AEDIT
INSTALL EMULATOR
r-~---...., PROBE IN
ICETt.l5100 SERIES, MICROCONTROLLER
ICETt.t 44 ,ICE51, SITE
EMV44,OR EMV51.1--.....,
EMULATORS
TARGET
BOARD
IUP-200A/201A WITH
UNIVERSAL PROM \-----1I-H MCS® 51/
PROGRAMMER INSTALL RUPITII44
EPROM . MICRO-
IN CODE CONTROLLER
SITE
INSTALL SRAM
IN CODE SITE
0""'"
D
FILE
SOFTWARE TOOL
280176-3
NOTE:
*RL 51 is included with ASM51 and PLIM 51; OBJHEX and the BITBUS Monitor are part of the DCS100 BITBUS
Toolbox.
Figure 3. Software Generation Process
10-376
inter iDCX 51
SOPHISTICATED INTERNAL MEMORY cated from any remaining memory. These buffers
MANAGEMENT . form the System Buffer Pool (SBP) that can be used
to create additional stack space or to . locate mes-
The amount of internal memory available ranges sages sent between tasks.
from 128 to 256 bytes depending on the type of mi-
crocontroller used. During run-time, the iOCX 51 Executive dynamically
manages this space. If a task is deleted, its stack
Internal memory is used for the executive, stack space is returned to the System Buffer Pool for use
spare for "running" tasks, space for message buff- by other tasks or as a message buffer.
ers, and reserved memory for variables storage.
Other memory is used for register space. Except for As new tasks are dynamicallly created, the execu-
register space, the allocation of internal memory is tive reserves the needed stack space. If no space is
controlled by. the executive, user-specified task/data available, the executive deallocates a buffer from
descriptors and system configuration constants. the System Buffer Pool and then allocates the need-
ed stack space.
To optimize use of this limited resource, iOCX 51
provides dynamic (run-time) memory management. To send or receive a message, the executive allo-
cates one or more buffers from the SBP for space to
locate the message, With iOCX 51, messages can
INITIALIZATION AND DYNAMIC be optionally located in external (off-chip) memory.
The pre-configured executive in the 8044 BEM
MEMORY MANAGEMENT
BITBUS microcontroller, however, always locates
At initialization (see Figure 4), the iOCX 51 Executive messages in internal memory.
creates the System Memory Pool (SMP) out of the
remaining initial free space (i.e. memory not used by
the iOCX 51 Executive or for register space). Next, RELIABLE
stack space is created for each of the initial tasks
that will be running on the system. If reserved mem- Real-time control applications require reliability. The
ory is requested (using an 100), that memory is also nucleus requires about 2.2K bytes of code space, 40
set aside. Finally, multiple buffers (size specified dur- bytes on-chip RAM, and 218 bytes external RAM.
ingiOCX 51 configuration or using an 100) are allo-
DCX 51 Initialization
Task 0
Task 1
Task 2
Task 3
},
Unallocated
STEPS:
1. Create system memory pool from the initial free memo
Initial ory space.
Free 2. Allocate stack space (space for 4 tasks shown).
Memory I 3. Allocate user-reserved memory (per the 100).
Space SBP 4 4. Allocate equal-size buffers to form the system buffer
pool.
I
I
User
Memory
Figure 4. iDCX 51 Initialization of Internal Memory
10-377
intJ iDCX 51
Streamlined code increases performance and reli- DEVELOPMENT ENVIRONMENT
ability, and flexibility is not sacrificed as code may be
added to either on-chip or external memory. Intel provides a complete development environment
for the MCS-51 and RUPI-44 families of microcon"
The iDCX 51 architecture and simple user interface trollers. The iDCX 51 Executive is only one of many
further enhance reliability and lower cost. For exam- of the software development products available. The
ple, the straightforward structure of the user inter- executive is compatible with the following software
faces, and the transparent nature of the scheduling development utilities available from Intel:
process contribute to reliability of the overall system • 8051 Macro Assembler (ASM 51)
by minimizing programming effort. Also, modularity • PLIM 51 Compiler
increases reliability of the system and lowers cost by • RL.51 Linker and Relocator Program
allowing user tasks to be refined independent of the • LIB 51
system. In this way, errors are identified earlier and
can be easily corrected in each isolated module. Intel hardware development tools currently available
for MCS-51 and RUPI-44 microcontroller develop-
In addition, users can assign tasks a Function ·ID ment are:
that allows tracking of the tasks associated with a • ICE-51 00/252 Emulator for the MCS-51 farrlilyof
particular control/monitorig function. This feature re- microcontrollers
duces maintenance and trouble shooting time thus
increasing system run time and decreasing cost. • ICE-5100/044 Emulator for the RUPI-44 family of
microcontrollers (8044, 8344, 8744)
• iUP-200A/201A PROM Programmer, 21X soft-
OPERATING ENVIRONMENT ware, and iUP programming modules
The iDCX 51 Executive supports applications devel- The DCX 51 Executive is also compatible with older
opment based on any member of the ,high perform- hardware development tools (no longer available),
ance 8051 family of microcontrollers. The Executive which include:
is available on diskette with user linkable libraries or • EMV-51 144 Emulation Vehicles
in the 8044 BITBUS Enhanced Microcontroller pre- .• ICE-51/44 In"Circuit Emulators
configured in on-chip ROM. (The 8044 BEM is an
8044 component that consists of an 8051 microcon- Table 4 shows the possible MGS-51 and RUPI-44
troller and SDLC controller on one chip with integral families development environments: host systems,
firmware.) operating systems, available software utilities, and
hardware debug tools.
When in the iDCM environment (Figure 5), the pre-
configured iDCX 51 Executive can communicate
with other BITBUS series controller boards. The
BITBUS board at the master node can be associat-
ed with either an iRMXTM, PC-DOS or XENIX· host
system.
MASTER
REMOTE NODES
(SLAVES)
280176-4
Figure 5. IDeM Operating Environment
10-378
inter iDCX51
SPECIFICATIONS Reference Manual (Supplied)
460367-001- iDCX 51 Distributes Control Execu-
Supported Microcontrollers tive User's Guide for Release 2.0.
8031 80C31
8051 80C51 ORDERING INFORMATION
8032 8751
8744 8044 Part Number Description
8344 8052 DCX51SU Executive for 8051 Family of Micro-
controllers. Single User License, De-
velopment Only. Media Supplied for
Compatible DCM BITBUSTM Software All Host Systems (Table 3).
DCS 100 BITBUS Toolbox Host Software Utilities DCX51RF Royalty (Incorporation) Fee for iDCX
Executive. Set of 50 incorporations.
DCS 110 BITWARE DCM44 Code for BITBUS em- IDCX 51 RF does not ship with soft-
ulation
ware (Order DCX 51SU).
Table 4. MCS®-S1/RUPITM-44 Families Development Environments
Host Systems
Development Utilities Intellec®
PC/MS-DOS iRMX® 86 iPDSTM
Series II Series III/IV
SOFTWARE
ASM 51 + Utilities(1) ",. ",. ",. ",. ",.
PL/M 51 + Utilities(1) ",. ",. ",. ",. ",.
iDCX 51 Executive ",. ",. ",. ",.
HARDWARE
ICE-51 00/044/252 ",. ",.
iUP-200Al201 A ",. ",.
EMV-5H2). EMV-44(2) ",. ",.
ICE-51 (2), ICE-44(2) ",. ",.
iPDS + iUP-F87/44A PROM Programmer ",.
NOTES:
1. Utilities include RL 51, LIB 51, and AEDIT. Software for Series II systems is down-revision version.
2. These products are no longer available.
10-379
inter ICETM-5100/252
In,;,Ch"cuit Emulator for the
MCS®-51 Family of Microc()ntrollers
• Precise, Full-Speed, Real-Time • Symbolic Debugging Enables Access to
Emulation of Selected MCS-51 Memory Locations and Program
Microcontroller Components at Speeds Variables
Up to and Including 16 MHz • Four Address Breakpoints with In-
• 64 KB of Mappable High-Speed Range, Out-Of-Range, and Page Breaks
Emulation Memory
I". ' • Equipped with the Integrated Command
• 254 24-Bit Frames of Trace Memory (16 Directory (ICDTM) that Includes:
Bits Trace Program E,xecution - On~Line Help, .
Addresses and 8 Bits Trace External ..:... Syr1tax Guidance arid Checking
Events) .. - Dynamic Command-Entry
• Serial Li'nk to the IBM* PC AT, PC XT - Error Checking
(and DOS Compatibles), and the ' - Command Recall
Intellec® Series III/IV ' " • On-Line Disassembler and Single-Line
• ASM-51 and PL/M-51 'Language Assembler to Help with Code Patching
Support • Built-In CRT-Oriented Text Editor
The ICETM-5100i252 in-circuit emulator is a high-level, interactive debugging system that is used to develop
and test the hardware and software of a target system based on the MCS®-51 family of microcontrollers,The
ICE-51 00/252 emulator can be serially linked to an IBM PC AT or PC XT, or an Intellec Series III/IV. The
emulator can communicate with the host system at standard baud rates up to 19.2K. The design of 'the
emulator supports selected MCS-51 microcontroller components at speeds up to and including 16 MHz:
280200-1
·IBM is a registered trademark of International Business Machines Corporation.
November 1987
10-380 Order Number: 280200-002
inter ICETM·5100/252 EMULATOR
PRODUCT OVERVIEW System Integration
The ICE-5100/252 emulator provides full emulation Integration of software and hardware can begin
support for the MCS®-51 family members listed in when the emulator is plugged into the micro control-
Table 1. . ler socket of the prototype system hardware. Hard-
ware can be added, modified, and tested immediate-
The ICE-5100/252 emulator enables hardware and ly. As each section of the user's hardware is com-
software development to proceed simultaneously. pleted, it can be added to the prototype. Thus, the
With the ICE-5100/252 emulator, prototype hard- hardware and software can be system tested in real-
ware can be added to the system as it is designed time operation as each section becomes available.
and software can be developed prior to the comple-
tion of the hardware prototype. Software and hard-
ware integration can occur while the product IS being System Test
developed.
When the prototype is complete, it is tested with the
The· ICE-51 00/252 emulator assists four stages of final version of the system software. The ICE-51001
development: 252 emulator is then used for real-time emulation of
the microcontroller to debug the system as a com-
• Software debugging
pleted unit.
• Hardware debugging
• System integration The final product verification test can be performed
using the ROM or EPROM version of the microcon-
• System test
troller. Thus, the ICE-5100/252 emulator provides
the ability to debug a prototype or production system
at any stage in its development without introducing
Software Debugging extraneous hardware or software test tools.
The ICE-5100/252 emulator can be operated with-
out being connected to the target system or before
any of the user's hardware is available (provided ex- PHYSICAL DESCRIPTION
ternal data RAM is not needed). In this stand-alone
mode, the ICE-5100/252 emulator can be used to The ICE-5100/252 emulator consists of the follow-
ing components (see Figure 1):
facilitate program development.
• Power supply
• AC and DC power cables
Hardware Debugging • Controller pod
.The ICE-5100/252 emulator'S AC/DC parametric • Serial cable (host-specific)
characteristics match the microcontroller's. The em- • User probe assembly (consisting of the proces-
ulator's full-speed operation makes it a valuable tool sor module and the user cable)
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces. • Crystal power accessory (CPA)
Table 1. MCS®-51 Family Support Offered by the ICETM-5100/252 Emulator
Part On-Chip Program Memory On-Chip Data Memory
8031 None .. 128 bytes
80C31 . None 128 bytes
8032 None 256 bytes
8051 4 KB-ROM 128 bytes
80C51 4KB-ROM 128 bytes
8052 8KB-ROM 256 bytes
80C252 None 256 bytes
83C252 8 KB-ROM 256 bytes
8751 4 KB-EPROM 128 bytes
87C51 4 KB-EPROM 128 bytes
8752 8 KB-EPROM 256. bytes
87C252 8 KB-EPROM 256 bytes
10-381
ICETM·5100/252 EMULATOR
• 40-pin DIP target adaptor stand-alone mode. The target adaptor plugs into the
• Clips assembly socket on the CPA; the CPA then supplies clock and
power to the user probe.
• Software (includes the ICE-5100/252 emulator
software, diagnostic software, and tutorial) The clips assembly enables the user to trace exter-
nal events. Eight bits of data are gathered on the
The controller pod contains 64 K8 of emulation rising edge of. PSEN during opcode fetches. The
memory, 254- by 24-bit frames of trace memory, and clips information can be displayed using the CLIPS
the control processor. In addition, the controller pod option with the PRINT command. Trace qualification
houses a 8NC connector that can be used to con- input and output lines are also provided on the clips
nect up to 10 multi-ICE compatible emulators to- pod for connection to test equipment.
gether for synchronous starting and stopping of em-
ulation. The ICE-51 00/252 emulator software supports mne-
monics, object file formats, and symbolic references
The serial cable connects the host system to the generated by Intel's ASM-51 and PL/M-51 program-
controller pod. The serial cable supports a subset of ming languages. Along with the ICE-5100/252 emu-
the RS-232C signals. lator software is a customer confidence test disk
with diagnostic routines that check the operation of
The user probe assembly consists of a user cable the hardware.
and a processor module. The processor module
houses the emulation processor and the interface The on~line tutorial is written in the ICE-5100 com-
logic. The target adaptor connects to the processor mand language. Thus, the user is ,able to interact
module and provides an electrical and mechanical with and use the ICE-51 00/252 emulator while exe-
interface to the target microcontroller socket. cuting the tutorial.
The crystal power accessory (CPA) is a small de- A comprehensive set of documentation is included
tachable board that connects to the controller pod with the ICE-51 00/252 emulator.
and enables the ICE-5100/252 emulator to run in
';,.,,-
"f
280200-2
Figure 1. The ICETM-5100/252 System Hardware
10-382
inter ICETM·5100/252 EMULATOR
ICETM·5100/252 EMULATOR ICE-5100/252 emulator commands that access
memory use one of the special prefixes (e.g., CODE)
FEATURES
to specify the memory space.
The ICE-51 00/252 emulator has been created to as-
sist a product designer in developing,' debugging, The microcontroller's special function registers and
and testing designs incorporating the MCS®-51 fam- register bits can be accessed mnemonically (e.g.,
ily of microcontrollers. The following sections detail DPL, TCON, CY) with the ICE-5100/252 emulator
some of the ICE-5100/252 emulator features. software.
Data can be displayed or modified in one of three
Processor Selection bases: hexadecimal, decimal, and binary. Data can
also be displayed or modified in one of two formats:
The ICE-51 00/252 emulator emulates the microcon- ASCII and unsigned integer. Program code can be
trollers listed in Table 1. Selecting a processor type disassembled and displayed as ASM-51 assem-
changes the following characteristics to match the bler mnemonics. Code can be modified with stan-
microcontroller selected: dard ASM-51 statements using the built-in single-
line assembler.
• Internal RAM size
• Internal ROM size Symbolic references can be used to specify memory
• Idle and power down mode enable locations. A symbolic reference is a procedure
name, line number, program variable, or label in the
• Special function register symbolic map
user program that corresponds to a location.
• Memory map
• Latched or unlatched EA Some typical symbolic functions include:
• Serial port framing and error detection • Changing or inspecting the value of a program
variable by using the symbolic name to access
the memory location.
Emulation • Defining break and trace events using symbolic
references. .
Emulation is the controlled execution of the user's
software in the target hardware or in an artificial • Referencing variables as primitive data types.
hardware environment that duplicates the microcon- The primitive data types are ADDRESS, BIT.
troller of the target system. Emulation is a transpar- BOOLEAN, BYTE, CHAR (character), and
ent process that happens in real-time. The execution WORD.
of the user software is facilitated with the ICE-51001
252 command language. The ICE-51 00/252 emulator maintains a virtual sym-
bol table (VST) for program symbols. A maximum of
61 KB of host memory space is available for the
Memory Mapping VST. If the VST is larger than 61 KB, the excess is
stored on available host system disk space and is
There is 64 KB of memory that can be _mapped to paged in and out as needed. The size of the VST is
the CODE memory space in 4 KB blocks on 4 KB limited only by the disk capacity of the host system.
boundaries. By mapping memory to the ICE-51001
252 emulator, software development can proceed
before the user hardware is available. Breakpoint Specifications
Breakpoints are used to halt a user program in order
, Memory Examination and Modification to examine the effect of the program's execution on
the target system. The ICE-5100/252 emulator sup-
The memory space. for the MCS®-51 component(s) ports three different types of break specifications:
and its target hardware is fully accessible through • Specific address break - A single address can
the emulator. The ICE-5100/252 emulator refers to be specified to halt emulation.
four physically distinct memory spaces, as follows:
• CODE - references program memory
• IDATA - references internal data memory
• RDATA - references special function register
memory
• XDATA - references external data memory
10-383
inter ICETM~5100/252 EMULATOR
• Range break - An arbitrary range of addresses Procedures
can be specified to halt emulation. Program exe-
cution within or, optionally, outside the range Debugging procedures (PROCs) are a user-named
halts emulation. group of ICE-51 00/252 emulator commands that are
• Page break - Up to 256 page breaks· can be executed as one command. PROCs enable the user
specified. A page break is defined as a range of to define several commands in a named block struc-
addresses that is 256-bytes long and begins on a ture. The commands are executed by entering the
256-byte address boundary. name of thePROC. The PROC bodies are a simple
DO... END construct.
Break registers are IJs~r-defined debug definitions
used to create and store breakpoint definitions. PROCs can simulate missing hardware or software,
Break registers can contain multiple breakpoint defi- collect debug information, and execute high-level
nitions and can optionally call debug procedures software patches. PROCs can be copied to text files
when emulation halts. on disk, then recalled for use in later test sessions.
PROCs can also serve as program diagnostics, im-
plementing ICE-5100/252 emulator commands or
Trace Specifications user-defined definitions for special purposes.
PROCs can also be used to set breakpoints.
Tracing can be triggered using specifications similar
to those used for breaking. Normally, the ICE-51 001
252 emulator traces program activity while the user On-Line Syntax Menu
program .is .executing. With a trace specification,
tracing can be triggered to occur only when specific A special menu, called the Integrated Command Di-
conditions are met during execution. Up to 254 rectory (ICD), similar to the one used for the 121CETM
24-bit frames of trace information are collected in system and the VLSiCE-96 emulator, aids in creating
the buffer during emulation. Sixteen of the 24 bits syntactically correct command lines. Figure 3 shows
trace instruction execution addresses, and 8 bits an example of the ICD and how it changes to reflect
capture external events (CLIPS). the options available for the GO command.
The trace buffer display is similar to an ASM-51 pro-
gram listing shown in Figure 2. The PRINT command Help
enables the user to selectively display the contents
of the trace buffer. The user has the option of dis- The HELP command provides ICE-51 00/252 emula-
playing the clips information as well as disassem- tion command assistance via the host system termi-
bled instructions. nal. On-line HELP is available for the ICE-5100/252
emulator commands shown in Figure 4.
hlt>PRINT NEWEST 4 1* Print newest four instructions in
buffer *1 .
FRAME ADDRESS CODE INSTRUCTION
(028) 300A C02A PUSH 2AH
(03i:J) 300C 2532 ADD· A,32H
(032) 300E F52A MOV 2AH,A
(034) 3010 853210 CJNE A,32H,$+10H
hIt>
hI t>PRINT CLIPS OLDEST 2 1* Buffer display showing clips *1
FRAME ADDRESS CODE INSTRUCTION CLIPS (76543210)
(ODD) 300A C02A PUSH 2AH 01110011
(001) 300C 2532 ADD A,32H 11110101
hIt>
280200-3
Figure 2. Selected Trace Buffer Displays
10-384
intJ ICETM·5100/252 EMULATOR
Design Considerations Allow at least 1-% inches (3.8 cm) of space to fit the
processor module and target adaptor. Figure 5
The height of the processor module and the target shows the dimensions of the processor module.
adaptor need to be considered for target systems.
hI t> GO
FROM ARM FOREVER TIL USING TRACE <execute>
l hIt> GOFROM
<expr>
---------~
)
hI t> GO FROM J.3H
<operator> ARM FOREVER TIL USING TRACE <execute>
l hI t> GO FROM J.3H USING
BRKREG <brkreg name>
---------~
)
l hI t> GO FROM J.3H USING brl.
~ TRACE
--------~~
~ < execute>
)
l hlt> GO FROM J.3H USING brl. TRACE traceit
~ <execute>
---------~
)
280200-4
Figure 3. The Integrated Command Directory for the GO Command
hlt>HELP
HELP is available for:
ADDRESS APPEND ASM BASE BIT BOOLEAN
BRKREG BYTE CHAR CI CNTL_C COMMENTS
CONSTRUCTS COUNT CPU CURHOME CURX CURY
DCI DEBUG DEFINE DIR DISPLAY. DO
DYNASCOPE EDIT ERROR EVAL EXIT EXPRESSION
GO HELP IF INCLUDE INVOCATION ISTEP
KEYS LABEL LINES LIST LITERALLY LOAD
LSTEP MAP MENU MODIFY MODULE MSPACE
MTYPE NAMESCOPE OPERATOR PAGING PARTITION PRINT
PROC PSEUDO_VAR PUT REFERENCE REGS REMOVE
REPEAT RESET RETURN SAVE STRING SYMBOLIC
SYNCSTART TEMPCHECK TRCREG TYPES VARIABLE VERIFY
VERSION WAIT· WORD WRITE
hlt>
280200-5
Figure 4. HELP Menu
10-385
inter ICETM·5100/252 EMULATOR
PROCESSOR MODULE~ PIN 1
TOP VIEW
. A
~~ZT
n H
0"
~~:iI ~ ~f ~
m~~ I"~i
gx;
.~.-
&:il!; 0
~.G'I. Z
.r~. .
~.
~;.'
--1 3 13ft."
(9.7 em)
I
CABLE BODY
39"
(99 em) I 4"
(10.2 em)
----I
..,.,
SIDE VIEW
PROCESSOR MODULE
".
~u51X.
TARGET ~
ADAPTOR
280200-6
Figure 5. Processor Module Dimensions
ELECTRICAL CONSIDERATIONS
The emulation processor's user-pin timings and loadings are identical to the 80C252 component except as
follows.
Maximum Operating ICC and Idle ICC (ma)'
Maximum Operating ICC (ma)' Maximum Idle ICC (ma)'
Vee 4V 5V 6V 4V 5V 6V
Frequency
0.5 MHz 0.87 1.62 3.0 0.58 1.21 2.5
3.5 MHz 4.8 6.82 9.76 2.2 4.97 6.33
8.0 MHz 10.5 15.0 20.5 6.0 8.98- 11.76
12.0 MHz 15.2 22.2 30.2 9.2 13.34 17.46
16.0 MHz 19.4 28.6 38.7 11.8 17.4 23.4
• ICC is measured with all output pins disconnected.
XTAL 1 driven with TCLCH, TCHCL= 10ns,Vn=Vss + .5V, Vih=Vcc-.5V. XTAL2 not connected.
For maximum operating ICC .
EA = RST = PortO = Vcc.
For maximum idle ICC
• EA=PortO=Vcc;RST=Vcc, internal clock to PCA gated off .
• Up to 25 pf of additional pin capacitance is con- • Pins 18 and 19, XTAL1 and XTAL2, respectively,
tributed by the processor module and target have approximately 15 to 16 pf of additional ca-
adaptor assemblies. pacitance when configured for crystal operation.
• Pin 31, EA, has approximately 32 pf of additional
capacitance loading due to sensing circuitry.
10-386
infef ICETM·5100/252 EMULATOR
Table 2. CHMOS and HMOS Design Differences
Chip Function HMOS Component 8031 CHMOS Component 80C31
RST trigger threshold 2.5V 70% Vcc (3.5V @ Vcc = 5V)
RST input impedance 4K - 10K ohms 50K - 150K ohms
Port Iii -800/LA -50/LA
Clock threshold 2.5V 70% Vcc (3.5V @ Vcc = 5V)
Emulating HMOS Components EMULATOR PERFORMANCE
The ICE-5100/252 emulator is based on a CHMOS
emulation processor. There are minor differences Memory
between how the ICE-5100/252 emulator supports Mappable full- 64 KB Mappable to user or
CHMOS and HMOS designs as shown in Table 2. ICE-51 00/252
speed emulation
code memory emulator memory in
Refer to the Microcontrol/er Handbook, order num-
4 KB blocks on
ber 210918, for further information on CHMOS and 4 KB boundaries.
HMOS design considerations.
Trace Buffer 254- by 24- bit frames
HOST REQUIREMENTS Virtual Symbol A maximum of 61
• IBM PC AT or PC XT (or PC-DOS compatible) Table KB of host memory
with 512 KB of RAM and a hard disk running un- space is available
der the DOS 3.0 (or later) operating system. for the Virtual Sym-
bol Table (VST).
• Intellec Series III/IV Microcomputer Development The rest of the
System running under the ISIS or iNDX operating VST resides on
system respectively, with at least 512 KB of appli- disk anct is paged
cation memory resident. in and out as need-
Disk drives - Dual floppy or one hard disk and ed.
one floppy drive required.
PHYSICAL CHARACTERISTICS
ICETM·5100/252 SYSTEM SOFTWARE
PACKAGE
Controller Pod
• ICE-51 00/252 emulator software
Width 8%" (21 cm)
• ICE-51 00/252 confidence tests
Height 1%" (3.8cm)
• ICE-5100/252 tutorial softy,lare Depth 13%" (34.3 cm)
Weight 4 Ibs (1.85 kg)
User Cable
The user cable is 3 feet (approximately 1 m).
Processor Module
(with the target adaptor attached)
Width 310/,6" (9.7 cm)
Length 1%" (3.8 cm)
Height 1%" (3.8 cm)
10-387
inter ICETM·5100/252 EMULATOR
Power Supply pl252KITAs This· kit contains the ICE-51 00/252
user probe assembly~ power supply
Width 7%"(18.1 cm) and cables, serial cables, target
Height 4" (10.06 CITl) . adaptor, CPA, ICE-5100 controller
Depth 11" (27.97 cm) pod, software, and documentation for
Weight 151bs (6.1 kg) use with Intel hosts (Series III, IV).
The kit also includes the 8051 Soft-
ware Development Package and the
Serial Cable AEDIT text editor for use on Series
III/IV. [Requires software license.)
The serial cable is 12 feet (3.6m). pl252KITs . 'This . kit is the same 'as the
pl252KITAs kit excluding the 8051
Software Development Package and
ELECTRICAL CHARACTERISTICS the AEDIT text edito~. [Requires. soft-
ware license.)
Power Supply
100 - 120V or 200 - 240V (selectable) Software Only
50-60Hz Order Code Description
2 amps (AC max) @ 120V psA252D This kit contains the host, probe, di-
1 amp (AC max) @ 240V agnostic and tutorial software on
51.4" disks for use on an IBM PC'AT
or PC XT (requires DOS 3.0 or later).
ENVIRONMENTAL ,[Requires software license.)
CHARACTERISTICS psA252s This kit· contains the host, probe, di-
'. agnostic and tutorial software on 8"
Operating temperature + 10° C to + 40°C (50°F to : disks (both single"density and double-
104°F)
density) for use on a Series III., and on
Operating humidity Maximum of 85% relative 51.4" disks for use· on a Series W.
humidity, non-condensing [Requires software license.)
ORDERING INFORMATIO~ Other Useful Intel Debug and
Development SupportPro~ucts
Order Code 'Descrlptlon .
Emulator Hardware and Software
Order Code Description pD86AsM51 8051 Software Developm~nt Pack-
age (DOS version) - Consists of the
pl252KITAD This kit contains: ICE-5100/252 user AsM-51 .' macro assembler· which
probe assembly, power supply and gives symbolic access to 8051 hard-
cables, serial cables, target adaptor, ware features; the RL51 linker and re-
CPA, ICE-5100 controiler pod, soft- locator program that links modules
ware, and documentation for use with generated by AsM-51; CONV51
an IBM PC AT or PC XT. The kit also which enables software written for
includes the 8051 Software Develop- the MCs-48 family to be up-graded to
ment Package and the AEDIT text ed- run on the 8051, and the LlB51 li-
itor for use' on DOS systems. [Re~ brarian which programmers can use
quires software license.) to create and maintain libraries of
pl252KITD This kit is the same as the software object modules. Use with
pl252KITAD kit excluding the 8051 the DOS operating system (version
Software Development Package. and 3.0 or later)~
the AEDIT text editor. [Requires soft-
ware license.)
to-388
inter ICETM·5100/252 EMULATOR
pD86PLM51 PL/M-51 Software Package (DOS pl86ASM51 8051 Software Development Pack-
version) - Consists of the PL/M-51 age (ISIS version) - Same as the
compiler which provides high-level pD86ASM51 package except this one
programming language support; the is for use with the Series III.
LlB51 utility that creates and main- pl86PLM51 PL/M-51 Software Package - Same
tains libraries of software object mod- as the pD86PLM51 package except
ules, and the RL51 linker and reloca- this one is for use with the Series III
tor program that links modules gener- and Series IV.
ated by ASM-51 and PL/M-51 and lo-
cates the linked object modules to pD86EDIEU AEDIT text editor for use with the
absolute memory locations. Use the DOS operating system.
DOS operating system (version 3.0 or
later).
10-389
MCS®-S1 INDEX
8
8031AH,5-2 CPL, 5~12, 6-6, 9-34
8032AH,5-2 CPU Timing, 5-14
8051, 5-2 Crystal, 5-14, 6-27, 6-28
8051AH,5-2
8052AH,5-2
8052AH-BASIC, 5-2 D
DA A, 5-8, 9-35
80C31BH, 5-2
Data Memory, 5-4, 5-5, 5-11, 6-6, 6-30, 9-3
80C5IBH, 5-2, 6-28
Read Cycle, 6-31
80C51FA, 5-2, 7-1
Write Cycle, 6-31
83C51FA, 5-2, 7-1
Data Pointer, 6-2
80C152, 5-3
Data Transfers, 5-9
83C152, 5-3
DEC, 6-6, 9-37
8751H, 5-2, 6-25, 6-26
Direct Addressing, 5-7, 9-3, 9-5
8752BH, 5-2, 6-26
DIV AB, 5-8, 6-22, 9-38
87C51, 5-2, 6~26, 6-27
DINZ, 5-14, 6-6, 9-39
87C51FA, 5-2, 7-1
E .
A EA (External Access), 5-4, 6-6, 6-21, 6-26, 6-30
AC (Auxiliary Carry) Flag, 6-3, 9-10
Encryption Array, 6-26
ACALL, 5-13, 9-24
EPROM Programming, 6-26, 6-30
Accumulator, 6-2
EPROM Verifying, 6-26
ADD, 9-25, 9-35
Execution Times, 5-7
ADDC, 9-26, 9-35
External Clock, 6-28, 6-29
. ADDRESS/DATA Bus, 6-4, 6-5
External Program Execution, 54
Addressing
Broadcast, 7-8
Given, 7-8 F .
AJMP, 5-13, 9-28 Fetch/ExecutlOn Sequence, 5-15
ALE, 5-16, 6-6, 6-30 Framing Error Detection, 7-8
ANL, 5-12, 6-6, 9-28
Arithmetic Instructions, 5-7
ASM51,5-6 H
High Speed Output, 7-4, 7-7
Automatic Address Recognition, 7-8
I
B I/O ButTers, 6-3, 6-4
B Register, 6-2 Idle Mode, 5-2, 6-24, 6-25, 7-9, 9-10
Baud Rate, 6-12, 6-13, 6-14, 6-17 IE (Interrupt Enable), 5-17, 6-2, 6-20, 7-13, 9-11
BCD, 5-8, 5-10 Immediate Constants, 5-7
Bit Addressable, 9-5 INC, 6-6, 9-40
Boolean Instructions, 5-11, 5-12 Indexed Addressing, 5-7
Bus Cycle Indirect Addressing, 5-7, 9-3, 9-5
Data Memory, 5-16 Instruction Set, 5-6, 9-20
Program Memory, 5-16 Interrupt Response Time, 6-21, 6-22
Byte Addressable, 9-7 Interrupts, 5-4, 5-17, 6-20,7-11,9-11
External, 6-22, 9-11
c IP (Interrupt Priority), 5-17, 6-2, 6-21, 7-13, 9-12
C (Carry) Flag, 5-6, 5-12,6-3, 9-10
Capture Mode, 7-4
Capture Registers, 6-2
J .
m, 5-12, 9-42
Case Jump, 5-7, 5-13 JBC, 5-12, 6-6, 9-42
Ceramic Resonator, 5-14, 6-28 JC, 5-12, 9-43
CINE, 5-14, 9-31 JMP, 5-13, 944
CLR, 5-12, 6-6, 9-33
Compare Mode, 7-6
Control Registers, 6-2
10-390
J (Continued) R
JND, 5-12, 9-45 RD Signal, 5-4, 6-6
JNC, 5-12, 9-45 Register Banks, 5-7, 6-3, 9-5, 9-10
JNZ, 9-46 Register Instructions, 5-7
Jump Instructions, 5-13 Register-Specific Instructions, 5-7
JZ,9-46 Relative Offset, 5-12
Reset, 6-23, 6-30, 9-8
Power-On, 6-24
L RET, 5-13, 6-22, 9-61
LCALL, 5-13, 9-47
RET!, 5-13, 6-21, 6-22, 9-61
UMP, 5-13, 9-47
Lock Bits, 6-26 RI (Receive Interrupt) Flag, 6-12, 6-14, 6-17, 6-20, 9-18
RL,9-62
Logical Instructions, 5-9
Lookup Tables, 5-7, 5-11 RLC, 9-62
RR,9-63
RRC, 9-63
M
Machine Cycle, 5-15
MOV, 5-12, 6-6, 9-48 S
16-Bit, 5-10 SBUF, 6-2, 6-10, 6-14
MOVC, 5-11, 9-53 SCON, 6-2, 6-11, 6-14, 6-17, 9-18
MOVX, 5-11, 5-16, 9-54 Serial Port, 6-10, 6-15, 7-8, 9-10, 9-12, 9-16, 9-18, 9-19
MUL AB, 5-7, 6-22, 9-56 SET,6-6
SETB, 5-12, 9-64
Multiprocessor Communication, 6-11
SFRs, 5-6, 6-1, 6-2, 6-4, 7-15, 9-4, 9-5, 9-7
SJMP, 5-13, 9-65
N Software Timer, 7-4, 7-6
Ninth Data Bit, 6-11, 6-17 Stack Pointer, 6-2, 9-5
NOP, 9-56 Start Bit, 6-11, 6-14, 6-17
State Time, 5-15
Status Flags, 5-7
o Stop Bit, 6-11, 6-14, 6-17
ONCE (On-Circuit Emulation) Mode, 6-27
ORL, 5-12, 6-6, 9-57 SUBB,9-66
Oscillator, 5-14, 6-23, 6-27 SWAP A, 5-9, 9-67
External, 5-15
Oscillator Frequency, 6-12 T
OV (Overflow) Flag, 6-3, 9-10 T2CON, 6-2, 6-9, 6-10, 6-13, 9-16, 9-17
TCON, 6-2, 6-7, 6-8, 6-22, 9-11, 9-13
p Third Priority Level, 5-18
P (parity) Flag, 5-7, 6-3, 9-10 T! (Transmit Interrupt) Flag, 6-12, 6-14, 6-17, 6-20,
PCA Timer/Counter, 7-1, 7-5 9-18
PCON, 6-2, 6-12, 6-24, 9-10, 9-19 Timer/Counters, 6-2, 6-6, 9-13
Polling Sequence, 5-17 Up/Down, 7-9
POP, 5-9, 9-60 TMOD, 6-2, 6-7, 9-13, 9-14, 9-17
Port Bit Latch, 6-3, 6-4
Ports, 6-2, 6-3, 6-29 v
Power Down Mode, 5-2,6-24, 6-25, 7-9, 9-10 Vpp, 6-26, 6-30
Power Off Flag, 7-9
PROG,6-30
Program Memory, 5-3, 5-4, 6-6, 6-26, 9-2 W
Program Memory Locks, 6-26 Watch Dog Timer, 7-3, 7-8
Programmable Counter Array (PCA), 7-1 WR Signal, 5-4, 6-6
PSEN, 5-4, 5-16, 6-6, 6~30
PSW (program Status Word), 5-6, 6-2, 9-10 X
Pulse Width Modulator (PWM), 7-4, 7-7 XCH, 5-10, 9-68
PUSH, 5-9, 9-60 XCHD, 5-10, 9-69
XRL, 5-L2, 6-6, 9-69
XTALl, 5-14, 5-15, 6-28, 6-29, 6-30
Q
Quick-Pulse Programming Algorithm, 6-26 XTAL2, 5-14, 5-15, 6-28, 6-29, 6-30
10-391
80C152 INDEX
A
A, 8-4, 8-6 Bit Addressable Memory, 8-6
Abort, 8-29, 8-30 Bit Addresses, 8-7
Acknowledgement, 8-15, 8-16, 8-24, 8-25, 8-30 Bit Addresses (Symbolic), 8-8
Acquisition Time, 8-21 Bit Rate, 8-17
Address, 8-18, 8-25, 8-30, 8-35 Bit Stripping, 8-25, 8-29, 8-37
Address Assignment, 8-34, 8-35 Bit Stuffing, 8-25, 8-29, 8-35, 8-37
Address Length Bit Time, 8-21
see AL BKOFF, 8-3, 8-4, 8-(;, 8-41
Address Mask Registers Block Diagram, 8-2
seeAMSKn BOF, 8-17, 8-18, 8-20, 8-25, 8-37, 8-39
Address Match Registers Broadcast Address, 8-18, 8-25
see ADRn Burst Mode, 8-46, 8-51, 8-52
Address Negotiation, 8-34 Byte Count, 8-33
Address Recognition, 8-15, 8-16, 8-18
ADRO, 8-3, 8-4, 8-6, 8-41
ADR1, 8-3, 8-4, 8-6, 8-41 C
Clock Recovery, 8-17, 8-37, 8-38
ADR2, 8-3, 8-4, 8-6, 8-41
Collision, 8-17, 8-20, 8-39
ADR3, 8-3, 8-4, 8-6, 8-41
Collision Fragment, 8-21
AE,8-3, 8-9, 8-43 Collision Resolution, 8-15, 8-16, 8-19, 8-21
AL, 8-3, 8-18, 8-41
Command,8-26
ALE, 8-13, 8-49
Control Field, 8-25, 8-26, 8-28, 8-30
ALE Switch, 8-49 CRC, 8-3, 8-15, 8-16, 8-18, 8-21, 8-24, 8-25, 8-28, 8-32,
Alignment Error
8-35, 8-37, 8-44
see AE
CRC Error
Alternate Backoff, 8-15, 8-16, 8-19, 8-21, 8-22, 8-23,
8-40 . see CRCE
CRC Generating Polynomial, 8-18, 8-28
Alternate Cycle Mode, 8-46, 8-52
CRC Jam, 8-15, 8-16
AMSKO, 8-3, 8-4, 8-6, 8-41
CRC Remainder, 8-18, 8-28
AMSKl, 8-3, 8-4, 8-6, 8-41
CRC Type
ARB, 8-49, 8-52
see CT
Arbiter CRCE, 8-3, 8-9, 8-43
see ARB Crystal Selection, 8-17
Arbiter Mode, 8-47, 8-48, 8-49 CSMA/CD, 8-14, 8-15, 8-16, 8-17, 8-34, 8-35, 8-37,
8-40
B CSMA/CD Frame
B, 8-4, 8-6 see Frame Format
Backoff Algorithm, 8-19, 8-20, 8-39, 8-40 CT, 8-3, 8-41
Backoff Mode . Cyclic Redundancy Check
see MO, Ml see CRC
Backoff Timer
see BKOFF
Back-to-Back Frames, 8-42 o
DARHO, 8-3, 8-4, 8-6, 8-45
Balanced, 8-30
DARH1, 8-3, 8-4, 8-6, 8-45
Baud, 8-3, 8-4, 8-6, 8-20, 8-41 DARLO, 8-3, 8-4, 8-6, 8-45
Baud Rate, 8-17, 8-34 DARLl, 8-3, 8-4, 8-6, 8-45
Baud Rate Generator DAS, 8-3, 8-45, 8-52
see Baud Data Encoding, 8-15, 8-16, 8-29, 8-34
BCRHO, 8-3, 8-4, 8-6, 8-45, 8-46
Data Memory, 8-5
BCRH1, 8-3, 8-4, 8-6, 8-45, 8-46
DC Jam, 8-15, 8-16, 8-21
BCRLO, 8-3, 8-4, 8-6, 8-45, 8-46 DC Jam (Bit)
BCRL1, 8-3, 8-4, 8-6, 8-45, 8-46
see DCJ
Beginning of Frame Flag DCJ, 8-3, 8-21, 8-42
see BOF DCONO, 8-3, 8-4, 8-6, 8-33, 8-45, 8-46, 8-52
DCONl, 8-3, 8-4, 8-6, 8-33, 8-45, 8-46, 8-52
DCR, 8-3, 8-42
10-392
D (Continued) ETO,8-1O
Deference, 8-17 ETl, 8-10
Demand Mode, 8-46, 8-51, 8-52 EXO,8-1O
Demand Mode (Bit) EXI,8-IO
seeDM Extended Address, 8-18
DEN, 8-11, 8-13, 8-29, 8-35, 8-44 External Clocking of GSC, 8-15, 8-16, 8-17, 8-37
Destination Address Space External Demand Mode, 8-46
see DAS External Driver, 8-35
Deterministic Backoff, 8-15, 8-16, 8-17, 8-19, 8-21, External Transmit Clock
8-22, 8-23, 8-40, 8-43 seeXTCLK
Deterministic Collision Resolution (Bit)
see DCR
Direct Memory Access F
FIFO Pointer, 8-43
see DMA Flags, 8-15, 8-16, 8-35
DM, 8-3, 8-46, 8-52 Frame Format, 8-17, 8-25
DMA,8-24
Full Duplex, 8-15, 8-16, 8-24, 8-30,8-32, 8-34, 8-37
DMA Arbitration, 8-51
DMA Control Bits, 8-52
DMA Control Register G
see DCONn Garen, 8-42
DMA Cycle, 8-45, 8-46, 8-47, 8-51 GFO, 8-1, 8-5
DMA Precedence, 8-51 GFl, 8-1, 8-5
DMA Register, 8-45 GFIEN, 8-1, 8-5, 8-42
DMA Register Access, 8-51 Global Serial Channel
DMA Select see GSC
see DMA (Bit) Glossary, 8-52
DMA Serial Demand Mode GMOD, 8-3, 8-4, 8-6, 8-41
see GSC, Servicing of GO, 8-3, 8-46, 8-52
DMA Timing, 8-47 GREN, 8-3, 8-24, 8-39, 8-40, 8-43
DMA Transfer, 8-44, 8-45, 8-47, 8-48 Group Address
DMA (Bit), 8-9, 8-33, 8-43 see Multicast Address
DMAO,8-44 GRXD,8-13
DMAI,8-44 GSC, 8-14, 8-46
DONE, 8-3, 8-9, 8-33,8-46, 8-52 GSC
DPH, 8-4, 8-6 Servicing of (CPU), 8-32, 8-39
DPL, 8-4, 8-6 Servicing of (DMA), 8-15, 8-16, 8-32, 8-33, 8-39
DPTR,8-6 Servicing of (GSC), 8-15, 8-16
Duplex GSC Auxiliary Receiver Enable
see Full Duplex seeGAREN
GSC External Receive Clock Enable
seeXRCLK
L GSC Idle Flag Enable
EA,8-13 see GFIEN
EDMAO, 8-9, 8-10 GSC Mode
EDMAI, 8-9, 8-10 see GMOD
EGSRE, 8-9, 8-10, 8-20, 8-33 GSC Operation, 8-37
EGSRV, 8-9, 8-10, 8-33 GSC Receive Enable
EGSTE, 8-9, 8-10, 8-20, 8-33 see GREN
EGSTV, 8-9, 8-10, 8-33 GSC Register Descriptions, 8-41
End of Frame Flag GSC Sampling Rate, 8-20, 8-37
- see EOF GSC Transmit FIFO
Ending Reception, 8-40 see TFIFO
Ending Transmission, '8-40 GTXD,8-13
EOF, 8-17, 8-18, 8-25, 8-29, 8-40
Error Reporting, 8-25
ES,8-1O
10-393
H M .
HABEN, 8-3, 8-24, 8-39, 8-43 MO, 8-3, 8-35, 8-40, 8-41
Half Duplex, 8-15, 8-16, 8-24, 8-30, 8-32, 8-34, 8-37 Ml, 8-3, 8-35, 8-40, 8-41
Hardware Based Acknowledge Enable Manchester, 8-15, 8-16, 8-17, 8-20,8-24, 8-35, 8-37
see HABEN Master Station
Hardware Based Acknowledgement see Primary Station
see HBA Memory Space, 8-1
HBA, 8-15, 8-16, 8-24, 8-30 Misalignment, 8-24
HDLC, 8-30, 8-37 Mode, 8-26
HLDA, 8-13, 8-44, 8-47,8-48, 8-49, 8-52 Modulo, 8, 8-30
HOLD, 8-13, 8-44, 8-47, 8-48, 8-49, 8-52 Modulo, 128, 8-30
Hold Acknowledge Monitoring Link, 8-40
see HLDA MOVX, 8-49
Hold Request Multi-Drop Configuration, 8-30, 8-31
see HOLD Myslot, 8-3, 8-4, 8-6, 8-22, 8-42
I N
IDA, 8-3, 8-45, 8-52 Network Changes, 8-32
Idle, 8-14, 8-40 Network Expansion, 8-32
Idle Fill Flags, 8-42 No Acknowledgement
Idle (GSC), 8-30 see NOACK
IE, 8-4, 8-6, 8-10 NOACK, 8-5, 8-9, 8-24, 8-44
IENl, 8-3, 8-4, 8-6, 8-9, 8-10 Nonsequenced Frame
IFS, 8-3, 8-4, 8-6, 8-19, 8-29, 8-41, 8-42 see Unnumbered Frame
Increment Destination Address Normal Backoff, 8-15, 8-16, 8-19, 8-21, 8-22, 8-23, 8-40
see IDA NRZ, 8-15, 8-16, 8-17, 8-24, 8-35, 8-37
Increment Source Address NRZI, 8-15, 8-16, 8-29, 8-35, 8-37
see ISA Number of Stations, 8-40
Information Field, 8-18, 8-25, 8-28
Information Frame, 8-25, 8-26
Initialization (GSC), 8-34, 8-35 o
Overflow, 8-24
INTO, 8-13, 8-46
Overrun
INTI, 8-13, 8-46
see OVR
Interframe Space, 8-17, 8-19, 8-22, 8-24, 8-32, 8-40
OVR, 8-3, 8-9, 8-43
Interrrame Space (Register),
see IPS
Internal Clocking of GSC, 8-15, 8-16 P
Interrupt Structure, 8-9 . PO
IP, 8-4, 8-6, 8-10 see PORTO
IPNl, 8-3, 8-4, 8~6, 8-9, 8-10 PI
ISA, 8-45, 8-52 see PORTI
P2
see PORT2
J P3
Jam, 8-15, 8-16, 8-17, 8-21, 8-22, 8-40
see PORT3
Jam Time, 8-21 P4 '
Jitter, 8-35, 8-36
see PORT4
Package, 8-11
L PCON, 8-4, 8-6, 8-42, 8-48, 8-49, 8-52
Line Discipline, 8-30, 8-34, 8-37 PDMAO, 8-9, 8-10
Line Idle PDMAl, 8-9, 8-10
see LNI PGSRE, 8-9, 8-10
LNI, 8-5, 8-30, 8-44 PGSRV, 8-9, 8-10
Local Serial Channel PGSTE, 8-9, 8-10
see LSC PGSTV, 8-9, 8-10
Loop Configuration, 8-30 Pin Description, 8-12
Loopback, 8-35 Pin Out (DIP), 8-11
LSC, 8-14, 8-46 Pin Out (PLCC), 8-12
PLO, 8-3, 8-41
PLl, 8-3, 8-41
10-394
P (Continued) RFIFO Time Delay, 8-20
Pomt-to-Point Configuration, 8-30, 8-31 RFNE, 8-3, 8-9, 8-33, 8-39, 8-43, 8-46
PoJl/Final Bit RI,8-46
see P/F Bit Ring Configuration, 8-30, 8-31
PORTO, 8-4, 8-6, 8-12, 8-44 Round-Trip Propagation, 8-21
PORTI, 8-4, 8-6, 8-12 RSTAT, 8-3, 8-4, 8-6, 8-43
PORT2, 8-4, 8-6, 8-13, 8-44 RXC,8-37
PORT3, 8-4, 8-6, 8-13 RXD,8-13
PORT4, 8-3, 8-4, 8-6, 8-11, 8-13
Power Down, 8-14
PR, 8-3, 8-41 S
SARHO, 8-3, 8-4, 8-6, 8-33, 8-45
PRBS, 8-3, 8-4, 8-6, 8-22, 8-42
SARHl, 8-~, 8-4, 8-6, 8-45
Preamble, 8-15, 8-16, 8-17, 8-18, 8-24, 8-35, 8-37
SARLO, 8-3, 8-4, 8-6, 8-33, 8-45
Preamble Length
SARLI, 8-3, 8-4, 8-6, 8-45
see PL
SAS, 8-3, 8-45, 8-52
Primary Station, 8-24, 8-25, .8-30
SBUF, 8-4, 8-6, 8-46
Program Memory, 8-8
SCON, 8-4, 8-6
Program Verification, 8-12, 8-13 SDLC, 8-14, 8-15, 8-16, 8-24, 8-30, 8-34, 8-35, 8-37,
Promiscuous Address, 8-25
8-40
Protocol (Bit)
SDLC Commands, 8-27
see PR
SDLCFrame
PS,8-1O
see Frame Format
PSEN,8-13
Secondary Station, 8-24, 8-25, 8-30
Pseudo Random Binary Sequence
Sending Sequence, 8-26
see PRBS
Separation of Busses, 8-50
PSW, 8-4, 8-6
Sequence Count, 8-25, 8-30
PTO,8-1O
Serial Backplane, 8-44
PT!,8-1O
Serial Port Demand Mode, 8-46
PXO,8-1O
SFRS
PXI,8-10
see Special Function Registers
P IF Bit, 8-25, 8-26
Slave Station
see Secondary Station
R Slot Address, 8-42
Raw Receive, 8-15, 8-16, 8-17, 8-35 Slot Address Register
Raw Transmit, 8-15, 8-16, 8-17, 8-29, 8-35 see Myslot
RCABT, 8-3, 8-9, 8-20, 8-29, 8-39, 8-40, 8-43 Slot Assignment, 8-17
RD, 8-13, 8-44, 8-47, 8-51 Slot Time, 8-21, 8-22, 8-32, 8-40
RDN, 8-3, 8-9, 8-33, 8-39, 8-40, 8-43 Slot Time (Register)
Receive Count, 8-30 see SLOTTM
Receive FIFO SLOTTM, 8-3, 8-4, 8-6, 8-21, 8-43
see RFIFO Source Address Space
Receive FIFO Not Ready see SAS
seeRFNE SP, 8-4, 8-6
Receive Status Register Special Function Registers, 8-3, 8-6
see RSTAT Supervisory Frame, 8-25, 8-26
Receiver Collision!Abort Detect
see RCABT
Receiver Done T
seeRDN TO,8-13
Reception Sequence, 8-26 T!, 8-13
REN, 8-20, 8-40 TCDCNT, 8-3, 8-4, 8-6, 8-22, 8-39, 8-40, 8-43
REQ, 8-49, 8-52 TCDT, 8-5, 8-9, 8-20, 8-39, 8-40, 8-44
Requester Mode, 8-47, 8-48, 8-49 TCON, 8-4, 8-6
Requester (Bit) TDN, 8-5, 8-9, 8-24, 8-33, 8-39, 8-40, 8-43, 8-44
see REQ TEN, 8-5, 8-29, 8-39, 8-40, 8-43, 8-44
Reset, 8-1, 8-10, 8-11, 8-13, 8-14, 8-19, 8-42 Test Modes, 8-35
Resolution Phase, 8-17, 8-21, 8-23 TFIFO, 8-4, 8-5, 8-6, 8-29, 8-32, 8-33, 8-39, 8-40, 8-43,
Response, 8-26 8-44,8-46
Retransmission, 8-39 TFNF, 8-5, 8-9, 8-39, 8-44, 8-46
RFIFO, 8-3, 8-4, 8-6, 8-20, 8-32, 8-33, 8-39, 8-40, 8-43, THO, 8-4, 8-6
8-46 THl, 8-4, 8-6
10-395
T (Continued) U
TI,8-46 UART
Timer/Counters, 8-11 see LSC
TLO, 8-4, 8-6 Unbalanced, 8-30
TL1~ 8-4, 8-6 Underrun
TM, 8-3,8-46, 8-52 seeUR
TMOD, 8-4, 8-6 Unnumbered Frame, 8-25, 8~26, 8-27, 8-28
Transfer Mode Unused SFR Addresses, 8-5
seeTM UR, 8-5, 8-9, 8-43, 8-44
Transmission During Resolution, 8-40 User Defined Protocols, 8-30
Transmit Collision Detect Using GSC, 8-30
see TCDT .... Using HLDA, 8-49
Transmit Collision Detect Count Using HOLD, 8-, 8-49
see TCDCNT .
Transmit Done
see TDN v
Transmit Enable
Vee, 8-12
see TEN
Vss, 8-12
Transmit FIFO Not Full
see TFNF W
Transmit Status Register WR, 8-13, 8-44, 8-47, 8-51
see TSTAT
Transmit Waveforms, 8-37
TSTAT, 8-4, 8-5, 8-6, 8-43 X
XRCLK, 8-1, 8-5, 8-37, 8-42
Turn-Around Time, 8-19 XTAL1,8-12
TXC, 8-3, 8-37 XTAL2,8-12
TXD,8-13 XTCLK, 8-37, 8-41
10-396
RUPITM..44 Family
.11
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THE RUPITM·44 FAMILY:
MICROCONTROLLER WITH ON·CHIP
COMMUNICATION CONTROLLER
INTRODUCTION real-time control applications such as instrumentation,
industrial control, and intelligent computer peripherals.
The RUPI-44 family is designed for applications re- The microcontroller features on-chip peripherals such
quiring local intelligence at remote nodes, and commu- as two 16-bit timer/counters and 5 source interrupt ca-
nication capability among these distributed nodes. The pability with programmable priority levels. The micro-
RUPI-44 integrates onto a single chip Intel's highest controller's high performance CPU executes most in-
performance microcontroller, the 8051-core, with an structions in 1 microsecond, and can perform an 8 X 8
intelligent and high performance Serial communication multiply in 4 microseconds. The CPU features a Boole-
controller, called the Serial Interface Unit, or SIU. See an processor that can perform operations on 256 direct-
Figure 1. This dual controller architecture allows com- ly addressable bits. 192 bytes of on-chip data RAM can
plex control and high speed data communication func- . be extended to 64K bytes externally. 4K bytes of on-
tions to be realized cost effectively~ chip program ROM can be extended to 64K bytes ex-
. ternally. The CPU and SIU run concurrently. See Fig-
The R~PI-44 family consists of three pin compatible ure 2.
parts:
• 8344-8051 Microcontroller with SIU The SIU is designed to perform serial communications
with little or no CPU involvement. The SIU supports
• 8044-An 8344 with 4K bytes of on-chip ROM pro- data rates up to 2.4 Mbps, externally clocked, and
gram memory 375 Kbps self clocked (i.e., the data clock is recovered
• 8744-An 8344 with 4K bytes of on-chip EPROM by an on-chip digital phase locked loop). SIU hardware
program memory supports the HDLC/SDLC protowl: zero bit inser-
tion/deletion, address recognition, cycli.: rcdundan.:y
. check, aI\d frame number sequence check arc automati-
1.0 ARCHITECTURE OVERVIEW cally performed.
The 8044's dual controller architecture enables the The SIU's Auto mode greatly reduces communication
RUpj to perform complex control tasks and high speed software overhead. The AUTO mode supports the
communication in a distributed network environment. SDLC Normal Response Mode, by performing second-
ary station responses in hardware without any CPU
The 8044 microcontroller is the 805I-core, and main- involvement .. The Auto mode's interrupt control and
tains complete software compatibility with it. The mi- frame sequence numbering capability eliminates soft-
crocontroller contains a powerful CPU with on-chip ware overhead normally required in conventional sys-
peripherals, making it capable of serving sophisticated tems. By using the Auto mode, the CPU is free to con-
centrate on real time control of the application_
,--------------------,
I
H '= H
I
~~ ~ L ____________ ~ _______
~I",1---+1--·· COM,,!:~o;cTlON
~
296163-1
Figure 1. RUPITM-44 Dual Controller Architecture
11-1 Order Number: 296163-001
THE RUPITM·44 FAMILY
r---------- ----, "
I I
I I
.I I
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j
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'----.I I
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:r-.
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Ig )
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1
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1 I
1 I
1 - r
I I-- 1
J ~ f---' I
I ~ -I
1
il r----
u 1
, I I
I
II. -
_ _ _ _ _ _ _ _ _ _ _ _ _ _ .J I
I
.:
II
!Ii
Figure 2. Simplified 8044 Block Diagram
11-2
intJ THE RUPITM-44 FAMILY
2.0 THE HOLC/SOLC PROTOCOLS • EFFICIENT: Well Oefined Message-Level Opera-
tion
• RELIABLE: Frame Check Sequence and Frame
2.1 HOLC/SOLC Advantages over Numbering
Async
The SOLC reduces system complexity. HOLC/SOLC
The High Level Oata Link Control, HOLC, is a stan- are "data transparent" protocols. Oata transparency
dard communication link control established by the In- means that an arbitrary data stream can be sent with-
ternational Standards Organization (ISO). SOLC is a out concern that some of the data could be mistaken for
subset of HOLC. a' protocol controller. Data transparency relieves the
communication controller having to detect special
HOLC and SOLC are both well recognized standard characters.
serial protocols. The Synchronous Oata Link Control,
SOLC. is an IBM standard communication protocol. SOLC/HOLC provides more data tllroughout than
IBM originally developed SOLC to provide efficient. Async. SOLC/HOLC runs atMessage-leve~ Operation
reliable and simple communication between terminals which transmits multiple l-ytes within the frame.
and computers. whereas Async is based on character-level ?peration.
Async transmits or receives a character at a tine. Since
The major advantages of SOLC/HOLC over Asyn- Async requires start and stop bits in every ransmis-
chronous communications protocol (Async): sion. there is a considerable waste of overhad com-
• SIMPLE: Oata Transparency pared to SOLC/HOLe.
-
I PRIMARY
I- i
"' Point to Point. Half Duplox
8044 CONTROLLED
SECONDARY
I :IOt,lli:J-3
Ii PRIMARY
J
I
t
8044 CONTROLLED·
,
8044 CONTROLLED
I
1044 CONTROLLO
SECONDARY SECONDARY SECONDARY
J
25163··'\
b) Multipoint, Half Duplex
~ ~
PRIMARY
1044 CONTROLLED 1044 CONTROLLED
SECONDARY SECONDARY
t ~
1044 CONTROLLED
SECONDARY r- 1044 CONTROLLED
SECONDARY
296163-5
c) SDLC Loop Configuration
Figure 3. RUPITM-44 Supported Network Configurations
11-3
inter THE RUPITM-44 FAMILY
Due to SOLC/HOLC's well delineated field (see Fig- 2.3 Frames
ure 4) the CPU does not have to interpret ~haracter.by
character to detcrmine control field and mformatlOn An HOLC/SOLC frame consists of five basic fields:
field. In the case of Async, CPU must look at each Flag, Address, Control, Oata and Error Oetection. A
character to interpret what it means. The practical ad- frame is bounded by flags-opening,and c1o~ing flags.
vantage of such feature is straight forward use of OMA An address field is 8 bits wide in SOLC, extendable to 2
for information transfer. or more bytes in HOLC. The control field is also 8 bits
wide,extendable to two bytes in HOLC. The SOLC
In addition, SOLC,IHOLCfurther improves Oata data field or information field may be any number of
throughput using implied Acknowledgement of trans. bytes. The HOLC data field mayor may notbeon an 8
ferred information. A station using SOLC/HOLC may bit boundary. A powerful error detection code called
acknowledge previously received information while Frame Check Sequence contains the calculated CRC
transmitting different information in the same frame. (Cycle Redundancy Code) for all the bits between the
In addition, up to 7 messages may be outstanding be- flags. See Figure 4.
fore an acknowledgement is required.
In HOLC and SOLC are three types of frames; an In-
The HOLC/SOLC protocol can be used to realize reli- formation Frame is used to transfer data, a Supervisory
able datalinks. Reliable Oata transmission is ensured at Frame is used for control purposes, and a Nonse-
the bit lerel by sending a frame check sequence, cyclic quenced Frame is used for initialization and control of
redudan<v. checking, within the frame. Reliuhleframe the secondary stations.
transmision is ensured by sending a frame number
idcntificaion with each frame. This means that a re- For a more detailed discussion of higher level protocol
ceiver ca sequentially count received frames ~nd at functions interested readers may refer to the references
any tinwnfer what the number of the next frame to be listed in Section 2.6.
received should be. More important, it provides a
means till the receiver to identify to the serider sorne
particularfrallle that it wishes to have resent because of 2.4 Zero Bit Insertion
errors.
In data communications, it is desirable to transmit data
which can be of arbitrary content. Arbitrary data trans- .
2.2 HOLe/SOLe Networks mission requires that the data field cannot contain
characters which arc defined to assist the transmission
In hOI II lhe H J) LC and SOLC line protocols a (Master) protocol (like opening flag in HOLC/SOLC communi-
primary station controls the overall network (data link) cations). This property is referred to as "data transpar-
and issuescollllllands to the secondary (Slave) stations. ency". In HOLC/SOLC, this code transparency is
The lattercomplies with instructions and .responds by made possible by Zero Bit Insertion (ZBI).
sending rupropriate responses. Whenever a transmit-
ting station must end transmission prematurely, it The flag has a unique bit pattern: 01111110 (7E HEX).
sends an mort character. Upon detecting an abort char- To eliminate the possibility of the data field containing
acler, a re:eiving station ignores the transmission block a 7E HEX pattern, a bit stuffing technique called Zero
called a fnme. Bit Insertion is used; This technique specifies that dur-
ing transmission, a binary 0 be inserted by the transmit-
~UI)I-44 supported HOLC/SOLC network configura- ter after any succession of five contiguous binary 1'so
tIons are point to point (half duplex) multipoint (half This will ensure that no pattern of 0 1 1 1 1 1 lOis ever
duplex), and loop. In the loop configuration the sta- transmitted between flags. On the receiving side, after
tions themselves act as repeaters, so that long links can receiving the flag, the receiver hardware automatically
he easily realized, see Figure 3. deletes any 0 following five consecutive 1'so The 8044
performs zero bit insertion and deletion automatically.
OPENING ADDRESS CONTROL INFORMATION FRAME CHECK CLOSING
FLAG FIELD FIELD ' FIELD SEQUENCE (FCS) FLAG
01111110 8 BITS VARIABLE LENGTH 18alTS 01111110
BaITS (ONLY tN t FRAMES)
296163-6
Figure 4. Frame Format
11-4
THE RUPITM·44 FAMILY
2.5 Non·return to Zero Inverted (NR21)
NRZI is a method of clock and data encoding that is
well suited to the HDLC/SDLC protocol. It allows
HDLC/SDLC protocols to be used with low cost asyn-
chronous modems. NRZI coding is done at the trans-
mitter to enable clock recovery from the data at the
receiver terminal by using standard digital phase locked
loop (DPLL) techniques. NRZI coding specifies that
the signal condition does not change for transmitting a
1, while a 0 causes a change of state. NRZI coding
ensures that an active data line will have a transition at
least every 5-bit times (recall Zero Bit Insertion), while
contiguous O's will cause a change of state. Thus, ZBI
and NRZI encoding makes it possible for the 8044's on-
chip DPLL to recover a receive clock (from received
data) synchronized to the received data and at the same
time ensure data transparency.
296163-7
2.6 References Figure 5. RUPITM-44 Development Support
Configuration Intellec® System, ICETM·44 Buffer
1. IBM Synchronous Data Link Control General Infor-
Box, and ICE-44 Module Plugged
mation GA27-3093-2 File No. GENL-09.
into a User Prototype Board
2. Standard Network Access Protocol Specification, DA-
TAPAC Trans-Canada Telephone System CCG]]1. A primary tool is the 8044 In CircUit Emulator, called
3. IBM 3650 Retail- Store System Loop Interface OEM ICE-44. See Figure 5. In conjunction with Intel's Intel-
Information, IBM, GA27-3098-0. lec® Microprocessor Development System, the ICE-44
4. Guidebook to Data Communications, Training Man- emulator allows hardware and software development to
ual, Hewlett-Packard 5955-1715. proceed interactively. This approach is more effective
than the traditional method of independent hardware
5. ''Serial Backplane Suits Multiprocessor Architec- and software development followed by system integra-
tures'~ Mike Webb, Computer Design, July 1984, pp.
tion. With the ICE-44 module, prototype hardware can
85-96. be added to the system as it is designed. Software and
6. ''Serial Bus Simplifies Distributed Control': P.D. hardware integration occurs while the product is being
MacWilliams, Control Engineering, June 1984, pp. developed.
101-104.
7. "Chips Support Two Local Area Networks'~ Bob The ICE-44 emulator assists four stages of develop-
Dahlberg, Computer Design, May 1984, pp. 107-114. ment:
8. ''Build a VLSI-based Workstation for the Ethernet 1) Software Debugging
Environment': Mike Webb, EDN. 23 February 1984. It can be operated without being connected to the
pp.297-307. user's system before any of the user's hardware is
9. "Networking With the 8044': Young Sohn & Charles available. In this stage ICE-44 debugging capabilities
Gopen, Digital Design, May 1984, pp. 136-137. can be used in conjunction with the Intellec text edi-
tor and 8044 macroassembler to facilitate program
development.
3.0 RUPITM·44 DESIGN SUPPORT 2) Hardware Development
The ICE-44 module's precise emulation characteris-
tics and full-speed program RAM make it a valuable
3.1 Design Tool Support tool for debugging hardware, including the time-crit-
A critical design consideration is time to market. Intel ical SDLC serial port, parallel port, and timer inter-
provides a sophisticated set of design tools to speed faces.
hardware and software development time of 8044 based
products. These include ICE-44, ASM-51, PL/M-51,
and EMV-44.
11-5
inter THE RUPITM~44 FAMILY
3) System Integration
Integration of software and hardware can begin
when any functionale1ement of the user, system
hardware is connected to the 8044 socket. As each
section of the user~s hardware is completed, it is add-
ed to the prototype. Thus, each section of the hard-
ware and software' is system tested in real-time oper-
ation as it becomes available.
4) System, Test
When the user's prototype is complete, it is tested
with the final version' of the user system software.
The ICE-44 module is then used for real-time emula-
tion of the 8044 to debug the system as a completed
unit.
'The final product verification test may be performed 296163-8
using the 8744 EPROM version of the 8044 micro-
computer. Thus, the ICE-44 module provides the Figure 6. RUPI-44 iPDS Personal Development
user'with the ability to debug a prototype or produc- System, EMV-44 Buffer Box, and EMV-44 Module
tion system at any stage in its development. Plugged into a User Prototype Board
A conversion kit, ICE-44 CON, is available to upgrade Integration, and System Test. The iPDS's rugged porta-
an ICE-51 module to ICE-44. bility and ease of use also make it an ideal system for
production tests and field service of your finished de-
Intel's ASM-Sl Assembler supports the 8044 special sign. In addition, the iPDS offers EPROM program-
function registers and assembly program development. ming module for the 8744, and direct communications
PL/M-SI provides designers with a high levellanguagc; with the 8044-based BITBUS via an optional iSBX-344
for the 8044. Programming in PL/M can greatly re- distributed control module.
duce development time, and ensure quick time to mar-
ket.
These tool~ have recently been expanded with the addi- 3.28051 Workshop
tion of the EMV-44CON. This conversion kit allows Intel provides 8051 training to its customers through
you to convert an EMV-Sl into an EMV-44 emulation the S-day 80S 1 workshop. Familiarity with the 8051
vehicle. The resultant low cost emulator is designed for and 8044 is achieved through a combination of lecture
use with an iPDS Personal Development System, which and laboratory exercises.
also supports the ASM-51 assembler and PL/M-Sl. See
Figure 6. For designers not familiar with the 8051, the workshop
is an effective way to become proficient with the 8051
Emulation support is similar to the ICE~44 with sup- architecture and capabilities.
port for Software and Hardware Development, System
11-6
8044 Architecture 12
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8044 ARCHITECTURE
GENERAL same byte as the opcode of an instruction. Thus, a large
number of instructions are one-byte instructions.
The 8044 is based on the 8051 core. The 8044 replaces
the 8051's serial port with an intelligent HDLC/SDLC The qext higher 16 bytes of the internal RAM (loca-
controller called the Serial Interface or SIU. Thus the tions 20H through 2FH) have individualiy addressable
differences between the two result from the 8044's in- bits. These are provided for use as software flags or for
creased on-chip RAM (192 bytes) and additional spe- one-bit (Boolean) processing. This bit-addressing capa-
cial function registers necessary to control the SIU. bility is an important feature of the 8044. In addition to
Aside from the increased memory, the SIU itself, and the 128 individually addressable bits in RAM, twelve of
differences in 5 pins (for the serial port), the 8044 and the Special Function Registers also have individually
8051 are compatible. addressable bits.
This chapter describes the differences between the 8044 A memory map is shown in Figure 2.
and 8051. Information pertaining to the 8051 core, ego
instruction set, port operation, EPROM programming,
etc. is located in the 8051 sections of this manual. 1.1 SpeCial Function Registers
A block diagram ofthe 8044 is shown in Figure 1. The The Special Function Registers are as follows:
pinpoint is shown on the inside front cover. • ACC Accumulator (A Register)
• B B Register
• PSW Program Status Word
1.0 MEMORY ORGANIZATION SP Stack Pointer
DPTR Data Pointer (consisting of DPH
OVERVIEW AND DPL)
o PO Port 0
The 8044 maintains separate address spaces for Pro-
gram Memory and Data Memory. The Program Mem- • PI Port 1
ory can be up to 64K bytes long, of which the lowest o P2 Port 2
4K bytes are in the on-chip ROM. o P3 Port 3
o IP Interrupt Priority
If the EA pin is held high, the· 8044 executes out of olE Interrupt Enable
internal ROM unlwess the Program Counter exceeds TMOD Timer/Counter Mode
OFFFH. Fetches from locations l000H through • TCON Timer/Counter Control
FFFFH are directed to external Program Memory. THO Timer/Counter 0 (high byte)
TLO Timer/Counter 0 (low byte)
If the EA pin is held low, the 8044 fetches all instruc- THI Timer/Counter 1 (high byte)
tions from external.Program Memory. TLl Timer/Counter 1 (low byte)
SMD Serial Mode
The Data Memory consists of 192 bytes of on-chip • STS Status/Command
RAM, plus 35 Special Function Registers, in addition • NSNR Send/Receive Count
to which the device is capable of accessing up to 64K STAD Station Address
bytes of external data memory .. TBS Transmit Buffer Start Address
TBL Transmit Buffer Length
The Program Memory uses 16-bit addresses. The exter- TCB Transmit Control Byte
nal Data Memory can use erither 8-bit or 16-bit ad- RBS .Receive Buffer Start Address
dresses. The internal Data Memory uses 8-bit address- RBL Receive Buffer Length
es, which provide a 256-location address space. The RFL Received Field Length
lower 192 addresses access the on-chip RAM .. The Spe- RCB Received Control Byte
cial Function Registers occupy various locations in the DMACNT DMA Count
upper 128 bytes of the same address space. FIFO FIFO (three bytes)
SIUST SIU State Counter
The lowest 32 bytes in the internal RAM (locations 00 PCON Power Control
through IFH) are divided into 4 banks of registers,
each bank consisting of 8 bytes. Anyone of these banks The registers marked with • are both byte- and bit-ad-
can be selected to be the "working registers" of the dressable.
CPU, and can be accessed by a 3-bit address in the
12-1 Order Number: 296164-001
PSEN ALE
l
r 1
csc
&
TIMING 1·5.0
I
PROGRAM
TIMERI INTERRUPT
,--- CPU COUNTERS INT1. CONTROL
MEMORY
"T1
C·
...
c
I RD.WR t TO, n INTO
INn
ID
:-'" ( )
-'-
:rJ
c:
"
"::j 11 ] IJ I 11 :II
c::
"U
I\)
'"
I:
all A )RII/O V- ~ .
':::j
iii!:
0"
()
;0;-
c
( PORT
0
I~
---'\
PORT
2
SIU
HARDWARE
REGISTERS
~
PORT
3
r-
"""
PORT
1 t=J1 ~
~
iii' rI
...
ce INTERNAL
I»
3
(
TWO PORT
DATA
RAM
51
fl P3
ADDRIDATA/IIO
SCLR
DATA
I/O
51U
1 RTS
CTS
296164-1
inter RUPITM_44
FFFF
FFFF
EXTERNAL
1000
( 1- - - ,
iiFFF r - -......
OFFF
/ \ OVERLAPPED
I " SPACE
I
- II
INTERNAL EXTERNAL
(EA 1) (EA 0)
-CO
FF . - - - - - - - - - , SPECIAL
FUNCTION
,-..:::RE~GI:::.ST~ER:;:S:.-...
SF INTERNAL
0000'-_ _ _ _-' 00 DATA RAM 0000
~'-----~ ,
'-----------~T~------------JI T
I ..
EXTERNAL
PROGRAM MEMORY INTERNAL DATA
DATA MEMORY MEMORY
296164-2
Figure 2. RUPITM-44 Memory Map
Stack Pointer External Interrupt control· bits ITO and ITl are in
TCON.O and TCON.2, respectively. Reset leaves all
The Stack Pointer is S bits wide. The stack can reside flags inactive, with ITO and ITl cleared.
anywhere in the 192 bytes of on-chip RAM. When the
S044 is reset, the. stack pointer is initialized to 07H. All the interrupt flags can be set or cleared by software,
When executing a PUSH or a CALL, the stack pointer with the same effect as by hardware.
is incremented before data is stored, so the stack would
begin at location OSH. The Enable and Priority Control Registers are shown
below. All of these control bits are set or cleared by
software. All are cleared by reset.
1.2 Interrupt Control Registers
The Interrupt Request Flags are as listed below: IE: Interrupt Enable Register (bit-addressable)
Bit:765432 0
Source Request Flag Location
I I
EA X X ES ET1 EX1 ETO EXO
External Interrupt 0 INTO, if ITO = 0 P3.2
lEO, if ITO = 1 TCON.I where:
eEA disables all interrupts. If EA = 0, no interrupt
Timer 0 Overflow TFO TCON.5 will be acknowledged. If EA = 1, each inter-
rupt source is individually enabled or disabled
External Interrupt 1 INTl, if ITl = 0 P3.3 by setting or clearing its enable bit.
lEI, if ITl = 1 TCON.3
eES enables or disables the SeriaI'Interface Unit in-
Timer 1 Overflow TFI TCON.7 terrupt. If ES = 0, the Serial Interface Unit
interrupt is disabled.
Serial Interface Unit SI STS.4 enables or disables the Timer 1 Overflow inter-
rupt. If ETl = 0, the Timer·I interrupt is
disabled.
12-3
intJ RUPITM·44
• EXI enables or disables External Interrupt 1. If all Program Memory fetches are from external memo-
EXI = 0, External Interrupt I is disabled. ry. The execution speed of the 8044 is the same regard-
• ETO enables or disables the Timer 0 Overflow inter- less of whether fetches are from internal or external
rupt. If ETO = 0, the Timer 0 interrupt is Program Memory. If all program storage is on-chip,
disabled. byte location 4095 should be left vacant to prevent an
undesired prefetch from external Program Memory ad-
dress 4096.
IP: Interrupt Priority Register (bit-addressable)
Bit: 765 4 2 o Certain locations in Program Memory are reserved for
specific programs. Locations 0000 through 0002 are re-
x, x x PS PT1 PX1 PTO PXO , served for the initialization program. Following reset,
, the CPU always begins execution at location 0000. Lo-
where: cations 0003 through 0042 are reserved for the five in-
• PS defines the Serial Interface Unit interrupt pri- terrupt-request service programs. Each resource that
ority level. PS = I programs it' to the higher can request an interrupt requires that its service pro-
priority level. gram be stored 'at its reserve<t location.
defines the Timer I interrupt priority level. The 64K-byte External Data Memory address space is
PTI = I programs it to the higher priority automatically accessed when the MOVX instruction is
level. executed.
• PXI defines the External Interrupt priority level.
PXI = I programs it to the higher priority Functionally the Internal Data, Memory is the most
level. flexible of the address spaces. The Internal Data Mem-
• PTO defines the Timer 0' interrupt priority level. ory space is subdivided' into a 256-byte Internal Data
PTO = I programs it to the higher priority RAM address space and a 128-byte Special Function
level. Register address space as shown in Figure 3.
• PXO defmes the External Interrupt o,priority level. SPECIAL
PXO = I programs it to the higher priority FUNCTION
REGISTERS
level. ~
25s 255 248 FBH
FOH
E8H
2.0 MEMORY ORGANIZATION EOH
D8H
DETAILS RAM DOH
ADDRESS-
D
In the 8044 family the memory is organized over three ~m ~~ ABLE
BITS IN
SFR_
address spaces and the program counter. The memory BOH (128 BITS)
spaces shown in Figure 2 are the: A8H
AOH
• 64K-byte Program Memory address space 98H
90H
• 64K-byte External Data Memory address space 88H
-=~12=8~1~3,,-5_1~28::.1 aOH
• 320-byte Internal Data Memory address space 127 r
The 16-bit Program Counter register provides the 8044 ADDRESS- !! b=-=
with its 64K addressing capabilities. The Program ABLE 127 120
BITS IN
Counter allows the user to execute calls and branches SFRo 32 7 0
(128 BITS) - R7
to any location within the Program Memory space. 24 RO BANK3
There are no instructions that permit program execu- - R7 BANK2
tion to move from the Program Memory space to any REGISTERS :!!I!lR!-_-I
of the data memory spaces. 8 :~BANKl
- R7 BANKO
~ 0
In the 8044 and 8744 the lower 4K of the 64K Program
Memory address space is filled by internal ROM and INTERNAL SPECIAL FUNCnON
EPROM, respectively. By tying the EA pin high, the DATA RAM REGISTERS
processor can be forced to fetch from the internal 296164-3
ROM/EPROM for Program Memory addresses 0
through 4K. Bus expansion for accessing Program Figure 3. Internal Data Memory Address Space
Memory beyond 4K is automatic since externalinstruc-
tion fetches occur automatically when the 'Program
Counter increases above 4095. If the EA pin is tied low
12-4
RUPITM-44
The Internal Data RAM address space is 0 to 255. access the SFR's. The SFR's at addresses 192-255 are
Four 8-Register Banks occupy locations 0 through 3l. also accessed using direct addressing. The Special
The stack can be located anywhere in the Internal Data Function Registers are listed in Figure 4. Their map-
RAM address space. In addition, 128 bit locations of ping in the Special Function Register address space is
the on-chip RAM are accessible through Direct Ad- shown in Figures 5 and 6.
dressing. These bits reside in Internal Data RAM at
byte locations 32 through 47. Currently locations 0 Performing a read from a location of the Internal Data
through 191 of the Internal Data RAM address space memory where neither a byte of Internal Data RAM
are filled with on-chip RAM. (i.e., RAM addresses 192-255) nor a Special Function
Register exists will access data of indeterminable value.
The stack depth is limited only by the available Internal
Data RAM, thanks to an 8-bit reloadable Stack Point- Architecturally, each memory space is a linear se-.
er. The stack is used for storing the Program Counter quence of 8-bit wide bytes. By Intel convention the
during subroutine calls and may be used for passing storage of multi-byte address and data operands in pro-
parameters. Any byte of Internal Data RAM or Special gram and data memories is the least significant byte at
Function Register accessible though Direct Addressing the low-order address and the most significant byte at
can be· pushed/popped. the high-order address. Within byte X, the most signifi-
cant bit is represented by X.7 while the least significant
The Special Function Register address space is 128 to bit is X.D. Any deviation from these conventions will be
255. All registers except the Program Counter and the explicitly stated in the text.
four 8-Register· Banks reside here. Memory mapping
the Special Function Registers allows them to be ac-
cessed as easily as internal RAM. As such, they can be 2.1 Operand Addressing
operated on by most instructions. In the overlapping
memory space (address 128-191), indirect addressing is There are five methods of addressing source operands.
used to access RAM, and direct addressing is used to They are Register Addressing, Direct Addressing,
Register-Indirect Addressing, Immediate Addressing
ARITHMETIC REGISTERS: ARITHMETIC REGISTERS:
Accumulator', B register", Accumulator', B register',
Program Status Word' Program Status Word'
POINTERS: POINTERS:
Stack Pointer, Data Pointer (high & low) Stack Pointer, Data Pointer (high & low)
PARALLEL I/O PORTS: PARALLEL I/O PORTS:
Port 3*, Port 2", Port 1*, Port O' Port 3', Port 2', Port 1', Port 0"
INTERRUPT SYSTEM: INTERRUPT SYSTEM:
Interrupt Priority Control", Interrupt Priority Control',
Interrupt Enable Control" Interrupt Enable Control'
TIMERS: TIMERS:
Timer Mode, Timer Control', Timer 1 Timer Mode, Timer Control', Timer 1
(high & low), Timer 0 (high & low) (high & low), Timer 0 (high & low)
SERIAL INTERFACE UNIT: SERIAL INTERFACE UNIT:
, Transmit Buffer Start, Serial Mode, Status/Command',
Transmit Buffer Length, SendIReceive COunt', Station Address,
Transmit Control Byte, Transmit Buffer Start Address,
Send Count Receive Count', Transmit Buffer Length,
DMACount, Transmit Control Byte,
Station Address Receive Buffer Start Address,
Receive Field Length Receive Buffer Length,
Receive Buffer Start. Receive Field Length,
Receive Buffer Length Receive Control Byte,
Receive Control Byte, DMA Count,
Serial Mode, . FIFO (three bytes),
Status Register.' SIU Controller State Counter
• Bits in these registers are bit addressable. . 'Bits in these registers are bit-addressable.
Figure 4. Special Function Registers Figure 5. Mapping of Special Function Registers
12-5
RUPITM·44
and Base-Register-plus Index-Register-Indirect Adc 2.2 Register Addressing
dressing. The first three of these methods can also be
used to address a destination· operand. Since operations Register Addressing perniits access to the' eight regis-
in the 8044 require O(NOP only), I, 2, 3 or 4 operands, ters (R7-RO) of the selected Register Bank (RB). One of
these five addressing methods are used in combinations the four 8-Register Banks is selected by a two-bit field
to provide the 8044 with its 21 addressing modes. in the PSW. The registers may also be accessed through
Direct Addressing and Register-Indirect Addressing,
Most instructions have a "destination, source" field since the four Register Banks are mapped into the low-
that specifies the data type, addressing methods and est 32 bytes of internal Data RAM as shown in Figures
operands involved. For operations other than moves, 9 and 10. Other Internal Data Memory'locations that
the destination operand is also a source operand. For are addressed as registers are A, B, C, AB and DPTR.
example, in "subtract-with-borrow A, # 5" the A regis-
ter receives the result of the value in register A minuS" 5,
minus C. . 2.3 Direct Addressing
Most operations' involve operands that are located in Direct Addressing provides the only means of accessing
Internal Data Memory; The selection of the Program the memory-mapped byte-wide Special Function Regis-
Memory space or External Data Memory space for a ters and memory mapped bits within the Special Func-
second operand is determined by the operation mne- tion Registers and Internal Data RAM. Direct Ad-
monic unless it is an immediate operand. The subset of dressing of bytes may also be used to ~ccess the lower
the Internal Data Memory being addressed is deter- 128 bytes of Internal Data RAM. Direct Addressing of
mined by the addressing method and address value. For bits gains access to a 128 bit subset ofthe Special Furtc-
example, the Special Function Registers can be ac- tion Registers as shown in Figures 5, 6,9, and 10.
cessed only through Direct Addressing with an address
of '128-255. A summary of the operand addressing
methods is shown in Figure 6. The following para-
graphs describe the five addressing methods.
SYMBOLIC BYTE
REGISTER NAMES ADDRESS BIT ADDRESS ADDRESS
~
B REGISTER B 240 (FOH)
ACCUMULATOR ACC 224 (EOH)
·THREE BYTE FIFO FIFO 223 (DFH)
FIFO 222 (DEH)
FIFO 221 (DDH)
TRANSMIT BUFFER START TBS 220 (DCH)
TRANSMIT BUFFER LENGTH TBL 219 (DBHI
TRANSMIT CONTROL BYTE .TCB 218 (DAH)
·SIU STATE COUNTER SIUST 217 (DBHI
SEND COUNT RECEIVE COUNT NSNR 216 (D6H)
PROGRAM STATUS WORD PSW 208 (DOH)
·DMACOUNT DMACNT 207· (CFH)
STATION ADDRESS STAD 206 (CEH)
RECEIVE FIELD LENGTH RFL 205 (CDH)
RECEIVE BUFFER START RBS 204 (CCH)
RECEIVE BUFFER LENGTH RBL 203 (CBH) SFR'. CONTAINING
RECEIVE CONTROL BYTE. RCB 202 (CAH) DIRECT ADDRESSABLE BITS
SERIAL MODE SMD 201 (CBH)
STATUS REGISTER STS 200 (CBH)
INTERRUPT PRIORITY CONTROL IP 184 (B6H)
PORT 3 P3 176 (BDH)
INTERRUPT ENABLE CONTROL IE' 166 (ASH)
PORT 2 P2 160 (AOH)
PORT 1 PI. 144 (SOH)
TIMER HIGH 1 THI 141 (BDH)
TIMER HIGH 0 THO 140 (&CH)
TIMER LOW 1 TLI 139 (BBH)
TIMER LOW 0 TLO 138 (BAH)
TIMER MODE TMOD 137 (89HI
TIMER CONTROL TCON 136. (89H)
DATA POINTER HIGH DPH 131 (83H)
DATA POINTER LOW DPL 130 (82H)
STACK POINTER SP 129 (81 H)
PORTO PO 12B (60H)
·296164-'4
Figure 6. Mapping of SpeCial Function Registers
12-6
intJ RUPITM~44
Direct Bit Address Hardware
• Register Addressing
Byte Register R7-RO
Address (MSB) (lSB) Symbol
~ A, B, C (bit), AB (two bytes), DPTR (double
240 F7 I F6 I FS I F4 I F3 I F2 I Fl I FO 8 byte)
• Direct Addressing
224 E7 I E6 I ES I E4 I E3 I E2 I El I EO ACC
Lower 128 bytes of Internal Data RAM
NS2 NSI NSO SES NR2 NRI NRO SER
216 OF I DE I DO I DC I DB I OA I 09 I 08 NSNR Special Function Registers
CY AC FO RSI RSO OV P 128 bits in subset of Special Function Register
204 D7 I D6 I OS I 04 I 03 I 02 I 01 I DO PSW address space
TBF RE RTS 51 BV CPB AM RBP
200 CF I CE I CD I CC I CB I CA I C9 I C8 STS
• Register-Indirect Addressing
PS PTI PXl PTO PXO Internal Data RAM [@Rl, @RO, @SP (PUSH
184 - I - I - I BC I BB I BA I B9 I B8 lP and POP only)]
Least Significant Nibbles in Internal Data
176 B7 I 86 I B5 I 84 I 83 I B2 I Bl I 80 P3 RAM (@Rl, @RO)
EA ES ETI EXI ETO EXO
168 AF I - I - I AC I AB I AA I A9 I AS IE
External Data Memory (@Rl, @RO, @DPTR)
• Immediate Addressing
160 A7 ~A6L ASJ A41 A3 L A2J All AO P2
- Program Memory (in-code constant)
144 97 I 96 I 9S I 94 I 93 I 92 I 91 I 90 PI • Base-Register·plus Index-Register-Indirect Ad-
TFI TRI TFO TRO lEI ITI lEO ITO dressing .
136 8F I 8E L80 I 8G I 8B I SA I 89 I 88 TCON Program Memory (@ DPTR + A, @ PC + A)
128 87 I 86 I 8S I 84 I 83 I 82 I 81 I 80 PO Figure 8. Operand Addressing Methods
Figure 7. Special Function Register Bit Address
SPECIAL
FUNCTION
.AM REGISTERS
BVTE IM5B) (LSI)
BfH
I 1 191
r-"----.
255 255
'41
. 240
.. F8H
FOH
...
23, .'H
.OH
.." .. .. ,..
70 7C 7B
2fH
" " ". D8H
... .. ..
[iiiO
n
>EH
" " " " 70 DOH
CIH
,..
'OH Of .0 'C' 'B 'A IS '00 DIRECT
'CH
" " " "so 50 44 ", COH
ADDRESS-
,..
BlH 'NG
. .. -
so .OH (IITS)
" Sf SC S. SA 43
-
'BH 51 178
AlH
.. .... so
"
55
"H 57 54
" "
"H 'f '0 'C 'B 'A 41
INDIREC
ADDO·T~" ,.
'80
'52
IOH
..
.
,. ,. " '38
27H 3f 3E lO lC 19 30 19
, 121 135 , IIH
80H
.
~
2&H 31 18
lS l4 II l2
" 30 117
2SH
24H
2lH
"
" ..
'f
'0
"
'C
24
'B
2l
.
22
"
"
31
30
lS DIRECT
.!!
'27 ,..
." "
'B
" ADDRESSING
22H
"H
'OH
Of
07 .. DO
..
OC 0.
Ol
OA
0'
09
0'
..
"
00
l4
II
l2
CIITS)
.!!
l!
7
07
O.
BANK 3
0
"H " Rl lANK 2
"H
81"113
&.nk 2
24
2l
REGISTER
ADDRESSING
.!!
...!. .
O•
07
lANK 1
:: BANK 0
'OH ...!.
a.nll I
"" '-----;--y---J
OIH ~ DIRECT ADDRESSING
07H STACK-POINTER REGISTER·INDIRECT AND
alnkO REGISTER·INDIRECT ADDRESSING
296164-6
296164-S
Figure 10. Addressing Operands
Figure 9. RAM Bit Address in Internal Data Memory
12-7
inter RUPITM_44
Register-Indirect Addressing using the content of Rl TBS OOH
or RO in the selected Register Bank, or using the con- TBL OOH
tent of the Stack Pointer (pUSH and POP only), ad- TCB OOH
dresSes the Internal Data RAM. Register-Indirect Ad- RBS OOH
dressing is also used for accessing the External Data
Memory. In this case, either Rl or RO in the selected RBL OOH
Register Bank may be used for accessing locations RFL OOH
within a 256-byte block. The block number can be pre- RCB OOH
selected by the contents of a port. The 16-bit Data DMACNT OOH
Pointer may be used for accessing any location within FIF01 OOH
the full 64K external address space. FIF02 OOH
FIF03 OOH
SIUST 01H
3.0 RESET PCON (OXXXXXXX)
Reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while The internal RAM is not affected by reset. When VCC
the oscillator is running. The CPU responds by execut- is turned on, the RAM content is indeterminate unless
ing an internal reset. It also configures the ALE and VPD was applied prior to VCC being turned off (see
PSEN pins as inputs. (They are quasi-bidirectional.) Power Down Operation.)
The internal reset is executed during the second cycle in
which RST is high and is repeated every cycle until
RSt goes low. It leaves the internal registers as follows: 4.0 RUPITM·44 FAMILY PIN
Register Content DESCRIPTION
PC OOOOH VSS: Circuit ground potential.
A OOH
B OOH VCC: Supply voltage during programming (of the
PSW OOH 8744), verification (of the 8044 or 8744), andnorinal
SP 07H operation.
DPTR OOOOH
PO-P3 OFFH Port 0: Port 0 is an 8-bit open drain bidirectional I/O
IP (XXXOOOOO) port. It is also the multiplexed low-order address and
data bus during accessses to external memory (during
IE (OXXOOOOO) which accesses it activates internal pullups). It also out-
TMOD OOH puts instruction bytes during program verification. (Ex-
TCON OOH ternal pullups are required during program verifi-
THO OOH cation.) Port 0 can sink eight LS TIL inputs.
TLO OOH
TH1 OOH Port 1: Port 1 is an 8-bit bidirectional I/O port with
TL1 OOH internal pUllups. It receives the low-order address byte
SMD OOH during program verification in the 8044 or 8744. Port 1
STS OOH can sink/source four LS TIL inputs, It can drive MOS
inputs without external pullups.
NSNR OOH
STAD OOH Two of the Port 1 pins serve alternate functions, as
listed below:
Port Pin Alternate Function
P1.6 RTS (Request to Send). In a non-loop configu-
ration, RTS signals that the 8044 is ready to
transmit data.
12-8
8044 Serial Interface 13
THE RUPITM-44 SERIAL INTERFACE UNIT
SERIAL INTERFACE Externally Clocked Mode
The serial interface provides a high-performance com- In the externally clocked mode, a common Serial Data
munication link. The protocol used for this communi- Clock (SCLK on pin 15) synchronizes the serial bit
cation is based on the IBM Synchronous Data Link stream. This clock signal may come from the master
Control (SDLC). The serial interface also supports a CPU or primary station, or from an external phase-
subset of the ISO HDLC (International Standards Or- locked loop local to the 8044. Figure 3 illustrates the
ganization High-Level Data Link Control) protocol. timing relationships for the serial interface signals when
the externally clocked mode is used in point-to-point
The SDLCIHDLC protocols have been accepted as and multipoint data link configurations.
standard protocols for many high-level teleprocessing
systems. The serial interface performs many of the Incoming data is sampled at the rising edge of SCLK,
functions required to service the data link without in- and outgoing data is shifted out at the falling edge of
tervention from the 8044's own CPU. The programmer SCLK. More detailed timing information is given in the
is free to concentrate on the 8044's function as a periph- 8044 data sheet.
eral controller, rather than having to deal with the de-
tails of the communication process.
Self Clocked (Asynchronous) Mode
Five pins on the 8044 are involved with the serial inter-
face: The self clocked mode allows data transfer without a
Pin 7 RTS/P16 common system data clock. Using an on-chip DPLL
(digital phase locked loop) the serial interface recovers
Pin 8 CTS/P17 the data clock from the data stream itself. The DPLL
Pin 10 I/O/RXD/P30 requires a reference clock equal to either 16 times or 32
Pin 11 DATA/TXD/P31 times the data rate. This reference clock may be exter-
nally supplied or internally generated. When the serial
Pin 15 SCLK/Tl//P35 interface generates this clock internally, it uses either
the 8044's internal logic Clock (half the crystal frequen-
Figure 1 is a functional block diagram of the serial in- cy's PH2) or the "timer 1" overflow. Figure 4 shows
terface unit (SIU). More details on the SIU hardware the serial interface signal timing relationships for the
are given later in this chapter. loop configuration, when the unclocked mode is used.
The DPLL monitors the received data in order to de-
1.0 DATA LINK CONFIGURATIONS rive a data clock that is centered on the received bits.
Centering is achieved by detecting all transitions of the
The serial interface is capable of operating in three seri- received data, and then adjusting the clock transition
al data link configurations: (in increments of '1.8 bit period) toward the center of
. 1) Half-Duplex, point-to-point the received bit. The DPLL converges to the nominal
. 2) Half-Duplex, multipoint (with a half-duplex or full- bit center within eight bit transitions, worst case.
duplex primary)
To aid in the phase locked loop capture process, the
3) Loop 8044 has a NRZI (non-return-to-zero inverted) data en-
coding and decoding option. NRZI coding specifies
Figure 2 shows these three configurations. The RTS that a signal does not change state for a transmitted
(Request to Send) and CTS (Clear to Send) hand-shak- binary 1, but does change state for a binary O. Using the
ing signals are available in the point-to~point and multi- NRZI coding with zero-bit insertion, it can be guaran-
point configurations. teed that an active signal line undergoes a transition at
least every six bit times.
2.0 DATA CLOCKING OPTIONS
The serial interface can operate in an externally clocked 3.0 DATA RATES
mode or in a self clocked mode. The maximum data rate in the externally clocked mode
is 2.4M bits per second (bps) a half-duplex configura-
tion, and l.OM in a loop configuration.
13-1 Order Number: 296165-001
BIT PROCESSOR BYTE PROCESSOR
l
SYNCHRONIZED
a
DIGITAL
PHASE
LOCI(
LOOP
Rxe:> ., CONTROL
"1'1
c·
...
c
CD TXD SRlST XI
;'" c:
en "U
..... 2:
c.:>
r\3 0"
(')
m .
"::j
;;:
........
;0;-
en
S!
DI
2
...DI
CD
3 I
I
I
I SIU
I INTERNAL
HARDWARE
REGISTER
-TWO
I PORT
(2 PORT)
RAM
I
I
I
I
I
)
18 \. 296165-1
RUPITM-44 SIU
8044
MASTERI CONTROLLED
PRIMARY
SECONDARY
296165-2
1) HALF·DUPLEX, POINT·TO·POINT
MASTERI
PRIMARY -
~ ~
8044 8044
CONTROLLED CONTROLLED
SECONDARY SECONDARY
296165-3
2) HALF·DUPLEX, MULTIPOINT
MASTERI
PRIMARY
8044 8044
CONTROLLED CONTROLLED
SECONDARY SECONDARY
8044
CONTROLLED
SECONDARY
296165-4
3) LOOP
Figure 2. RUPI-44 Data Link Configurations
13-3
· RUPITM·44SIU
In the self clocked mode with an external reference 4.1 AUTO Mode
dock, the maximum data rate is 375K bps.
To enable the SIU to receive a frame in AUTO mode,
In the self clocked mode with an internally generated the 8044 CPU sets up a receive buffer. This is done by
reference clock, and the 8044 operating With a 12 MHz writing two registers-Receive Buffer Start (RBS) Ad-
crystal, the available data rates are 244 bps ·to 62.5K dress and Receive Buffer Length (RBL).
bps, 187.5K bps and 375K bps.
The SIU receives the frame, examines the control byte,
For more details see the table in the SMD register de- and takes the appropriate action. If the frame is an
scription, below. information frame, the.SIU will load the receive buffer,
interrupt the CPU (to have the receive buffer read), and
make the required acknowledgement to the primary
4.0 OPERATIONAL MODES station. Details on these processes are given in the Op-
eration section, below.
The Serial Interface Unit (SIU) can operate in either of
two response modes: In addition to receiving the information frames, the
SIU in AUTO mode is capable of responding to the
1) AUTO mode following commands (found in the control field of su-
2) FLEXIBLE (NON-AUTO) mode pervisory frames) from the primary station:
In the AUTO mode, the stu performs iIi hardware a RR (Receive Ready): Acknowledges that the Primary
subset of the SDLC protocol called the. normal re- station has correctly received numbered frames up
sponse mode. The AUTO mode enables the SIU to rec- through NR - 1; and that it is ready to receive frame
ognize and respond to certain kinds of SDLC frames NR·
without intervention from the 8044's CPU. AUTO
mode provides a faster turnaround time and a simpli- RNR (Receive Not Ready): Indicates a temporary busy
fied software interface, whereas NON-AUTO mode condition (at the primary station) due to buffering or
provides a greater flexibility with regard to the kinds of other internal constraints. The quantity NR in the con-
operation permitted. trol. field indicates the number of the frame expected
after the busy condition ends, and may be used to ac-
In AUTO mode, the 8044 can act only as a normal knowledge the correct reception of the frames up
response mode secondary station-that is, it can trans- through NR - 1.
mit only when instructed to do so by the primary sta-
tion. All such AUTO mode responses adhere strictly to REI (Reject): Acknowledges the correct reception of
IBM's SDLC definitions. frames up through NR - I, and requests transmission
or retransmission starting at frame. NR. The 8044 is
In the FLEXIBLE mode,reception or transmission of capable of retransmitting at most the previous frame,
each frame by the SIU is performed under the control and then only if it is still available in the trarismit buff-
of the CPU. In this mode the 8044 can be either a er.
primary station or a secondary station.
UP (Unnumbered Poll): Also called NSP (Non-Se-
In both AUTO and FLEXIBLE modes, short frames, . quenced Poll) or ORP (Optional Response Poll). This
aborted frames, or frames which have had CRC's are· command is used in the loop configuration.
ignored by the SIU.
To enable the SIU to transmit an information frame in
The basic format of an SDLC frame is as follows: AUTO mode, the CPU sets up a transmit buffer. This
is done by writing two registers-Transmit Buffer Start
! Flag! Address! Control! Information! FCS ! Flag I (TBS) Address and Transmit Buffer Length (TBL), and
filling the transmit buffer with the information to be
transmitted.
Format variatio~s consist of omitting one or more of
the fields in the SDLC frame. For example, a superviso- When the transmit buffer is full, the SIU can automati-
ry frame is formed by omitting theinformation field. cally (without CPU intervention) send an information
Supervisory frames are used to confirm received frame (I-frame) with the appropriate sequence num-
frames, indicate ready or busy conditions, and to report bers, when the data link becomes available (when the
errors. More details on frame formats are given in the 8044 is polled for information). After the SIU has
SDLC Frame Format Options section, below. transmitted the I-frame, it waits for acknowledgement
from the receiving station. If the acknowledgement is
13-4
RUPITM_44 SIU
negative, the SIU retransmits the frame. If the ac- CPU, to indicate that the transmit buffer may be re-
knowledgement is positive, the SIU interrupts the loaded with new information.
\J
iiTs 7
CTs
TRANSCEIVER/BUFFER 8
I/O 8044
10
J
-
C> DATA
11
<J
SCLK
15
296165-5
DATA RECEIVE DATA XMITDTA RECEIVE DATA XMIT RECEIVE
I'
I/O
- ).. / \"
.~
iiTS
- l \
~
/
ffi
- \ I~
TRANSMIT
ABORTED BY
C'i'S-1
296165-6
Figure 3. Serial Interface Timing-Clocked Mode
13-5
l
8044
:II RXD
10
ca
...c
CD
~ TXD
11
en
...
CD
e: 16X/32X
1S
5'
S' ::D
:::1
DI c::
n 'U
......~.
..... CD 296165-7
CfJ ::!
0) a
5'
en
1 2
[.~ X X
CD
:;: DATA GA
X ONE'S
X SHUT-OFF SEQ DATA
~
n
0 1 1 1 1 1 1 0 1 1 1 1 1 1 1. 1 1 1 1 1 1 1 0 0 0 o 0 0 0 0 1 1 1 1 1
;-
a.
iii:
0
a. DATA (BIT-DELAYED) GA CHANGED TO FLAG TRANSMIT FRAME DATA (BIT-DELAYED)
CD
[nw 0 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 A D D R E S S CON T R 0 L 1 1 1 1
TRANSMISSION
,. ABORTED BY
EXTRA "1" SHUT-OFF
INSERTED SEQUENCE
296165-8
---- --
infef RUPITM·44 SIU
In addition to transmitting the information frames, the SMD Bit 1: NB (Non-Buffered Mode-No Control
SIU in AUTO mode is capable of sending the following Field)
responses to the primary station: STS Bit 1: AM (AUTO Mode or Addressed Mode)
RR (Receive Ready): Acknowledges that the 8044 has Figure 5 shows how these three bits control the frame
correctly received numbered frames up through format.
NR - 1, and that it is ready to receive frame NR.
The following paragraphs discuss some properties of
RNR (Receive Not Ready): Indicates a temporary busy the standard SOLC format, and the significance of
condition (at the 8044) due to buffering or other inter- omitting some of the fields.
nal constraints. The quantity NR in the control field
indicates the number of the frame expected after the
busy condition ends, and acknowledges the correct re- 5.1 Standard SOLC Format
ception of the frames up through NR - 1.
The standard SOLC format consists of an opening flag,
an 8-bit address field, an 8-bit control field, an n-byte
4.2 FLEXIBLE Mode information field, a 16-bit Frame Check Sequence
(FCS), and a closing flag. The FCS is based on the
In the FLEXIBLE (or non-auto) mode, all reception CCITI-CRC polynominal (X16 + X12 + X5 + 1).
and transmission is under the control of the CPU. The The address and control fields may -not be extended.
full SOLC and HOLC protocols can be implemented, Within the 8044, the address field is held in the Station
as well as any bit-synchronous variants of these proto- Address (STAO) register, and the control field is held
cols. in the Receive Control Byte (RCB) or Transmit Con-
trol Byte (TCB) register. The standard SOLC format
FLEXIBLE mode provides more flexibility than may be used in either AUTO mode or FLEXIBLE
AUTO mode, but it requires more CPU overhead, and mode.
much longer recognition and response times. This is
especially true when the CPU is servicing an interrupt
that has higher priority than the interrupts from the 5.2 No Control Field (Non·Buffered
SIV. Mode)
In FLEXIBLE mode, when the SIU receives a frame, it When the control field is not present, the RCB and
interrupts the CPU. The CPU then reads the control TCB registers are not used. The information field be-
byte from the Receive Control Byte (RCB) register. If gins immediately after the address field, or, if the ad-
the received frame is an information frame, the CPU dress field is also absent, immediately after the opening
also reads the information from the receive buffer, ac- flag. The entire information field is stored in the 8044's
cording to the values in the Receive Buffer Start (RBS) on-chip RAM. If there is no control field, FLEXIBLE
address register and the Received Field Length (RFL) mode must be used. Control information may, of
register. course, be present in the information field, and in this
manner the No Control Field option may be used for
In FLEXIBLE mode, the 8044 can initiate transmis- implementing extended control fields.
sions without being polled, and thus it can act as the
primary station. To initiate transmission or to generate 5.3 No Control Field and No Address
a response, the CPU sets up and enables the SIU. The
SIU then formats and transmits the desired frame. Field
Upon completion of the transmission, without waiting The No Address I'"ield option is available only in con-
for a positive acknowledgement from the receiving sta- juction with the No Control Field option. The STAO,
tion, the SIU interrupts the CPU. RCB, and TCB registers are not used. When both these
fields are absent, the information field begins immedi-
ately after the opening flag. The entire information field
5.0 8044 FRAME FORMAT OPTIONS is stored in on-chip RAM. FLEXIBLE mode must be
used. Formats without an address field have the follow-
As mentioned above, variations on the basic SOLC ing applications:
frame consist of omitting one or more of the fields. The
choice of which fields to omit, as well as the selection of Point-to-point data links (where no addressing is neces-
AUTO mode versus FLEXIBLE mode, is specified by sary)
the settings of the following three bits in the Serial
Mode Register (SMO) and the Status/COntrol Register Monitoring line activity (receiving all messages regard-
(STS): less of the address field)
SMO Bit 0: NFCS (No Frame Check Sequence) Extended addressing
13-7
inter RUPITM_44 SIU
FRAME OPTION NFCS NB AM FRAME FORMAT
Standard SOLC 0 0 0 F A C FCS F
FLEXIBLE Mode
Standard SOLC 0' 0 F A C FCS F
AUTO Mode
No Control Field
FLEXIBLE Mode
0 F A I FCS F
No Control Field 0 0 F FCS F
No Address Field
FLEXIBLE Mode
No FCS Field o o F A C F
FLEXIBLE Mode
NoFCS Field o F A C I F
AUTO Mode
NoFCS Field F A F
No Control Field
FLEXIBLE Mode
No FCSField o F F
No Control Field
No Address Field
FLEXIBLE Mode
Key to Abbreviations:
F= Flag (01111110)
A= Address Field
C= Control Field
1= Information Field
FCS = Frame Check Sequence
NOTE:
The AM bit is AUTO m<,>de control bit when NB = 0, and Address Mode control bit when NB = 1.
Figure 5. Frame Format Options
5.4 No FCS Field in the on-chip RAM. No FCS checking is done on the
received frames, and no FCS is generated for the trans-
In the normal case (NFCS = 0), the last 16 bits before mitted frames. The No FCS Field option may be used
the closing flag are the Frame Check Sequence (FCS) in conjunction with any of the other options. It is typi-
field. These bits are not stored in the· 8044's RAM. cally used in FLEXIBLE mode, although it does not
Rather, they are used to compute a cyclic redundancy strictly include AUTO mode. Use of the No FCS Field
check (CRC) on the data in the rest of the frame. A option AUTO Mode may, however, result in SDLC
received frame with a CRC error (incorrect FCS) is protocol violations, since the data integrity is not
ignored. In transmission, the FCS field is automatically checked by the sm.
computed by the SIU, and placed in the transmitted
frame just prior to the closing flag. Formats without an FCS field have the following appli-
cations:
The NFCS bit (SMDBit 0) gives the user the capability
of overriding this automatic feature. When this bit is set Receiving and transmitting frames without verifying
(NFCS = I), all bits from the beginning of the infor- data integrity.
mation field to the beginning of the closing flag are
treated as part of the information field, and are stored Using an alternate data verification algorithm.
13-8
RUPITM·44 SIU
Using an alternate CRC-16 polynomial (such as XI6 + SMD: SERIAL MODE REGISTER
XIS + X2 + I), or a 32-bit CRC (BYTE-ADDRESSABLE)
Bit: 7 6 5 4 3 2 1 0
Performing data link diagnosis by forcing false CRCs
to test error detection mechanisms I SCM21 SCM1 I SCMO I NRZII LOOP I PFS I NB I NFCS I
In addition to the applications mentioned above, all of The Serial Mode Register (Address C9H) selects the
the format variations are useful in the support of non- operational modes of the SIU. The 8044 CPU can both
standard bit-synchronous protocols. read and write SMD. The SIU can read SMD but can-
not write to it. To prevent conflict between CPU and
SIU access to SMD, the CPU should write SMD only
6.0 HOLC when the Request To Send (RTS) and Receive Buffer
Empty (RBE) bits (in the STS register) are both false
In addition to its support of SDLC communications, (0). Normally, SMD is accessed only during initializa-
the 8044 also supports some of the capabilities of tion.
HDLC. The following remarks indicate the principal
differences between SDLC and HDLC. The individual bits of the Serial Mode Register are as
follows:
HDLC permits any number of bits in the information Blt# Name Description
field, whereas SDLC requires a byte structure (multiple
of 8 bits). The 8044 itself operates on byte boundaries, SMD.O NFCS No FCS field in the SDLC
frame.
and thus it restricts fields to multiples of 8 bits.
SMD.1 NB Noon-Buffered mode. No
control field in the SDLC
HDLC provides functional extensions to SDLC: an un- frame.
limited address field is allowed, and extended frame
SMD.2 PFS Pre-Frame Sync mode. In
number sequencing. this mode, the 8044
transmits two bytes before
HDLC does not support operation in loop configura- the first flag of a frame, for·
tions. DPLL synchronization. If
NRZI is enabled, OOH is
sent; otherwise, 55H is sent.
7.0 SIU SPECIAL FUNCTION In either case, 16 pre-frame
transitions are guaranteed.
REGISTERS SMD.3 LOOP Loop configuration.
The 8044 CPU communicates with and controls the SMD.4 NRZI NRZI coding option.
SIU through hardware registers. These registers are ac- SMD.5 SCMO Select Clock Mode-Bit 0
cessed using direct addressing. The SIU special func- SMD.6 SCM1 Select Clock Mode-Bit 1·
tion registers (SIU SFRs) are of three types: SMD.7 SCM2 Select Clock Mode-Bit 2
Control and Status Registers The SCM bits decode as follows:
Parameter Registers SCM
Clock Mode Data Rate
ICE Support Registers (Bits/sec)·
210
000 Externally clocked 0-204M··
7.1 Control and Status Registers 001 Undefined
010 Self clocked, timer overflow 244-62.5K
There are three SIU Control and Status Registers:
011 Undefined
Serial Mode Register (SMD) 1 00 Self clocked, external 16x 0-375K
1 0 1 Self clocked, external 32x 0-187.5K
Status/Command Register (STS)
1 1 0 Self clocked, internal fixed 375K
Send/Receive Count Register (NSNR) 111 Self clocked, internal fixed 187.5K
The SMD, STS, and NSNR registers are all cleared by ·Based on a 12 MHz crystal frequency
• ·0-1 M bps in loop configuration
system reset. This assures that the SIUwill power up in
an idle state (neither receiving nor transmitting).
These registers and their bit assignments are described
below (see also the More Details on Registers section).
13-9
intJ RUPITM_44 SIU
STS: STATUS/COMMAND REGISTER, Bit# Name Description
(BIT-ADDRESSABLE) STS.7 TBF Transmit Buffer Fu". Written by
Bit: 7 6 5 4 3 2' 1 0 the CPU to indicate that it has ,
I rBF I RBE I Rrs I 51 I BOV I OPB I AM I RBP I filled the transmit buffer. TBF
may be cleared by the SIU.,
The Status/Command Register (Address CSH) pro~
vides operational control of the SIU by the S044 CPU,
NSNR: SEND/RECEIVE COUNT REGISTER
and enables the SIU to post status information Jor the
(BIT-ADDRESSABLE)
CPU's access. 'The SIU can read STS: and can alter B~ 7 6 5 4 3 2 1 0
certain bits, as indicated below. The CPU,can both read
and write STS asynchronously. However, 2-cycle in- INS21 NS1 INSO ISES I NR21 NR1 INRO ISER I
structions that access STS during both cycles ('JBC/B,
REL' and 'MOY /B,C.') should not be used, since the The SendlReceive Count Register (Address DSH) con-
SIU may write to STS between the two CPU accesses. tains the transmit and receive sequence numbers, plus
tally error' indications. The SIU can both read and
The individual bits of the Status/Command Register write NSNR. The S044CPU can both read and write
are as follows: NSNR asynchronously. However, 2-cycle instructions
Bit#' Name Description that access NSNR during both cycles (,JBC /B, REL',
STS.O' RBP Receive Buffer Protect. Inhibits and 'MOY /B,C') should not be used, since the SIU
writing of data into the receive may write to NSNR between the two S044 CPU access-
buffer. In AUTO mode, RBP es.
forces an RNR response
instead of an RR. The individual bits of the SendlReceive Count Register
are as follows:
STS.1AM, AUTO ModelAddressed Mode.
Selects AUTO mode where Bit# Name Description
AUTO mode is allowed. If NB is NSNR.O SER Receive Sequence Error:
, true; (= 1), the AM bit selects NS (P)* NR (S)
, the addressed mode. AM may
be cleared by the SIU. NSNR.1 NRO Receive Sequence Counter-Bit 0
STS.2 OPB Optional Po" Bit. Determines NSNR.2 NR1 Receive Sequence Counter-Bit 1
whether the SIU will generate NSNR.3 NR2 Receive Sequence Counter-Bit 2
an AUTO response to an
NSNR.4 SES Send Sequence Error:
optional po" (UP with P = 0). NR (P) * NS (S) and
OPB may be set or cleared by NR (P)* NS (S) + 1
the SIU ..
NSNR.5 NSO Send Sequence Counter-Bit 0
STS.3 BOV Receive Buffer Overrun. BOV
may be set or cleared by the NSNR.6 NS1 Send Sequence Counter-"-Bit 1
SIU. NSNR.7 NS2 Send Sequence Counter-Bit 2
STS.4 SI SIU Interrupt This is one of the
five interrupt sources to the
CPU. The vector location =
23H. SI may beset by the SIU. 7.2 Parameter Registers
It should be cleared by the CPU There are eight, parameter registers that are used in
before returning fron'! an ' connection, with SIUoperation. All eight registers may,
interrupt routine. be read or written by the S044 CPU. RFL and RCB are
STS.5 RTS Request To Send. Indicates normally ,loaded by the, SIU.
tnat the 8044 is ready to '
transmit or is transmitting. RTS The eight parameter registers are as follows:
may be read or written by the
CPU. RTS may be read by the
SIU, and in AUTO mode may STAD: STATION ADDRESS REGISTER
be written by the SIU. (BYTE-ADDRESSABLE)
STS.6 RBEReceive Buffer Empty. RBE
can be thought of as Receive' The Station Address register (Address CEH) cOntains
Enable. RBE is set to one by the station address. To prevent access conflict, the CPU
the CPU when it is ready to
receive a frame, or has just
read the buffer, and to zero by
the SIU when a frame has been
received.
13-10
RUPITM_44 SIU
should access STAD only when the sm is idle (RTS = RFL: RECEIVE FIELD LENGTH REGISTER
o and RBE = 0). Normally, STAD is accessed only (BYTE-ADDRESSABLE)
during initialization.
The Received Field Length register (Address CDH)
contains the length (in bytes) of the received I-field that
TBS: TRANSMIT BUFFER START ADDRESS has just been loaded into on-chip RAM. RFL is loaded
REGISTER (BYTE-ADDRESSABLE) by the sm. RFL = 0 is valid. RFL should be accessed
The Transmit Buffer Start address register (Address by the CPU only when RBE = O.
DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmitted. RCB: RECEIVE CONTROL BYTE REGISTER
The CPU should access TBS only when the SIU is not (BYTE-ADDRESSABLE)
transmitting a frame (when TBF = 0).
The Received Control Byte register (Address CAH)
contains the control field of the frame that has just been
TBL: TRANSMIT BUFFER LENGTH REGISTER received. RCB is loaded by the sm. The CPU can only
(BYTE-ADDRESSABLE) read RCB, and should only access RCB when RBE =
The Transmit Buffer Length register (Address DBH) O.
contains the length (in bytes) of the I-field to be trans-
mitted. A blank I-field (TBL = 0) is valid. The CPU
should access TBL only when the SIU is not transmit- 7.3 ICE Support Registers
ting a frame (when TBF = 0). The 8044 In-Circuit Emulator (ICE-44) allows the user
to exercise the 8044 application system and monitor the
NOTE: execution of instructions in real time.
The transmit and receive buffers are not allowed to
"wrap around" in the on-chip RAM. A "buffer end" The emulator operates with Intel's Intellec® develop-
is automatically generated if address 191 (BFH) is ment system. The development system interfaces with
reached. the user's 8044 system through an in-cable buffer box.
The cable terminates in a 8044 pin-compatible plug,
TCB: TRANSMIT CONTROL BYTE REGISTER which fits into the 8044 socket in the user's system.
(BYTE-ADDRESSABLE) With the emulator plug in place, the user can exercise
his system in real time while collecting up to 255 in-
The Transmit Control Byte register (Address DAH) struction cycles of real-time data. In addition, he can
contains the byte which is to be placed in the control single-step the program.
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB only Static RAM is available (in the in-cable buffer box) to
when the SIU is not transmitting a frame (when TBF emulate the 8044 internal and external program memo-
= 0). The Ns and NR counters are not used in the ry and external data memory. The designer can display
NON-AUTO mode. and alter the contents of 'the replacement memory in
the buffer box, the internal data memory, and the inter-
nal 8044 registers, including the SFRs.
RBS: RECEIVE BUFFER START ADDRESS
REGISTER (BYTE-ADDRESSABLE) Among the SIU SFRs are the following registers that
The Receive Buffer Start address register (Address support the operation of the ICE:
CCH) points to the location in on-chip RAM where the
beginning of the I-field of the frame being received is to DMA CNT: DMA COUNT REGISTER
be stored. The CPU should write RBS only when the (BYTE-ADDRESSABLE)
SIU is not receiving a frame (when RBE = 0).
The DMA Count register (Address CFH) indicates the
number of bytes remaining in the information block
RBL: RECEIVE BUFFER LENGTH REGISTER that is currently being used.
(BYTE-ADDRESSABLE)
The Receive Buffer Length register (A.ddress CBH) FIFO: THREE-BYTE (BYTE-ADDRESSABLE)
contains the length (in bytes) of the area in on-chip
RAM allocated for the received I-field. RBL = 0 is The Three-Byte FIFO (Address DDH, DEH, and
valid. The CPU should write RBL only when RBE = DFH) is used between the eight-bit shift register and
O. the information buffer when an information block is
received.
13-11
inter RUPITM_44 SIU
SIUST: SIU STATE COUNTER (BYTE- SIUST
ADDRESSABLE) , Function
Value
The SIU Suite Counter (Address D9H) reflects the 2SH Waiting for I field byte. This state can be
state of the internal logic which is under SIU control. entered from state 20H or from states
01 H, OSH, or 10H depending upon the
Therefore, care must be taken not to write into this
register. SIU's mode configuration. (Each time a
byte is received, it is pushed onto the top
of the FIFO and the byte at the bottom is
The SIUST register can serve as a helpful aid to deter-
put into memory. For no FOS formatted
mine which field of a receive frame that the SIU ex-
pects next. The table below will help in debugging 8044 frames, the FIFO is collapsed into a
reception problems. single register).
30H Waiting for the closing flag after having
SIUST overflowed the receive buffer. Note that
Function even if the receive frame overflows the
Value
assigned receive buffer length, the FOS
01H Waiting for opening flag.
is still checked.
OSH Waiting for address field.
10H Waiting for control field. Examples of SIUST status sequences for different frame
lSH Waiting for first byte of I field. This state formats are shown below. Note.that status changes af-
is only entered if a FOS is expected. It ter acceptance of the received field byte.
pushes the received byte onto the top of
the FIFO. . .
20H Waiting for second byte of I field. This
state always follows state lSH.
Table 1 SIUST Status Sequences
Frame Option
NFCS NB AM~
Example 1:
Frame Format I o o
SIUSTValue
Example 2:
Frame Format 1 (Idle) 1 F 1 A 1 I 1 F0 S I. F 1 o
2S
SIUST Value _0_1:...,..J.L...0-=-1:..L.:.OS::..J....:1~S...JI...:2:.:0:..L1...:2::S:...J,-'::::::"":_L.::0:.:.
L, 1__
Example 3:
Frame Format I o o
SIUSTValue
Example 4:
Frame Format I (Idle) I F I A I I I F I
SIUSTValue I 01 I 01 I OS I 2S I 01 I
Example 5:
Frame Format t.!.(I"..dl,..;e)+1 _:...1_-I-I_F~I
",:-F-+I.;..' o
SIUST Value . L_ _0_1_J...,_01.;....L._~2.:.S_.L-=0~1...J
ExampleS:
Frame Format 1 (Idle) -, F l'
I .' 1 I OVERFLOW I FOS 1 F 1 o o
SIUSTValue 1 01 1 0111s120 12s1 30 1 .30 1011
13-12
intJ RUPITM-44 SIU
8.0 OPERATION TBS, TBL - to define the area in RAM allocated for
the Transmit Buffer.
The SIU is initialized by a reset signal (on pin 9), fol-
lowed by write operations to the SIU SFRs. Once ini- Once these registers have been initialized, the user may
tialized, the SIU can function in AUTO mode or NON- write to the STS register to enable the SIU to leave the
AUTO mode. Details are given beiow. ' idle state, and to begin transmits and/or receives.
Setting RBE to 1 enables the SIU for receive. When
8.1 Initialization RBE = I, the SIU monitors the received data stream
for a flag pattern. When a flag pattern is found, the SIU
Figure 6 is the SIU. Registers SMD, STS, and NSNR enters Receive mode and receives the frame.
are cleared by reset. This puts the 8044 into an idle
state-neither receiving nor transmitting. The follow- Setting RTS to 1 enables the SIU for t~ansmit. When
ing registers must be initialized before the 8044 leaves RTS = I, the SIU monitors the received data stream
the idle state: for a GA pattern (loop configuration) or waits for a
STAD - to establish the 8044's SDLC station ad- CTS (non-loop configuration). When the GA or CTS
dress. arrives, the SIU ·enters Transmit mode and transmits a
frame.
SMD - To configure the 8044 for the proper op-
erating mode. In AUTO mode, the SIU sets RTS to enable automatic
RBS, RBL - to define' the area in RAM allocated for. transmissions of appropriate responses.
. the Receive Buffer. .
END-OF-
FRAME
FLEXIBLE
MODE
STRTREC STRTXMIT
FLEXIBLE
MODE
END-OF·FRAME
AUTO MODE
STRT REC = RBE. FLAG
STRT XMIT = RTS. (CTS. LOOP + GA.LOOP)
WAIT = NOT (STRT REC + STRTXMIT) . 296165-9
Figure 6. SIU State Diagram
13-13
inter RUPITM-44 SIU
8.2 AUTO Mode 2) In a non-loop configuration, one to eight extra drib-
ble bits are transmitted after the closing flag. These
Figure 7 illustrates the receive operations in AUTO· bits are a zero followed by ones.
mode. The overall operation is shown in Figure 7a. Par- 3) In a loop configuration, when a GA is' received and
ticular cases are illustrated in Figures 7b through 7j. If the 8044 begins transmitting, the sequence is
any Unnumbered Command other than UP is received, 01111110101111110 ... (FLAG, I, FLAG, AD-
the AM bit is cleared and the SIU responds as if in the DRESS, etc.). The first flag is created from the GA.
FLEXIBLE mode, by interrupting the CPU for super- The second flag begins the message.
vision. This will also happen if a BOV or SES condition
occurs. If the received. frame contains a poll, the SIU 4) CTS is sampled after the rising edge of the serial
sets the RTS bit to generate a response. data, at about the center of the bit cell, except dur-
ing a non-loop, externally clocked mode transmit, in
Figure 8 illustrates the transmit operations in AUTO which case it is sampled just after the falling edge.
mode. When the SIU gets the opportunity to transmit, 5) The SIU does not check for illegal I-fields. In partic-
and if the transmit buffer is full, it sends an I-frame. ular, if a supervisory command is received in AUTO
Otherwise, it sends an RR if the buffer is free, or an mode, and if there is also an I-field, it will be loaded
RNR if the buffer is protected. The sequence counters into the receive buffer (if RBP = 0), but it cannot
NS and NR are used to construct the appropriate con- cause a BOV.
trol fields. 6) In relation to the Receive Buffer Protect facility, the
user should set RFL to 0 when clearing RBP, such
Figure 9 shows how the CPU respoilds to an SI (serial that, if the SIU is in the process of receiving a
interrupt) in AUTO mode. The CPU tests the AM bit frame, RFL will indicate the proper value when re-
(in the STS register), If AM = I, it indicates that the ception of the frame has been completed.
SIU has receivc:d either an I-frame, or a positive re-
sponse to a previously transmitted I-frame.
8.5 Turn Around Timing
8.3 FLEXIBLE Mode In AUTO mode, the SIU generates an RTS immediate-
ly upon being polled. Assuming that the 8044 sends an
Figure 10 illustrates the receive operations in NON- information frame in response to the poll, the primary
AUTO mode. When the SIU successfully completes a station sends back an acknowledgement. If, in this ac-
task, it clears RBF and interrupts the CPU by setting knowledgement, the 8044 is polled again, a response
SI to 1. The exact CPU response to SI is determined by may be generated even before the CPU gets around to
software. A typical response is shown in Figure 11. processing the interrupt caused by the acknowledge. In
such a case, the response would be an RR (or RNR),
Figure 12 illustrates the transmit operations in FLEX- since TBF would have been set to 0 by the SIU, due to
IBLE mode. The SIU does not wait for a positive ac- the acknowledge.
knowledge response to the transmitted frame. Rather, it
interrupts the CPU (by setting SI to 1) as soon as it IT the system designer does not wish to take up channel
finishes transmitting the frame. The exact CPU re- time with RR responses, but prefers to generate a new
sponse to SI is determined by software. A typical re- I-frame as a response, there are several ways to accom-
sponse is shown in Figure 13. This response results in plish this:
another transmit frame being set up. The sequence of
operations shown in Figure 13 can also be initi.ated by 1) Operate the 8044 in FLEXIBLE mode.
. the CPU, without an SI. Thus the CPU can initiate a 2) Specify that the master should never acknowledge
transmission in FLEXIBLE mode without a poll, sim- and poll in one message. This is typically how a loop
ply by setting the RTS bit in the STS register. The RTS system operates, with the poll operation confined to
bit is always used to initiate a transmission, but it is the UP command. This leaves plenty of time for the
applied to the RTS pin only when a non-loop configu- 8044 to get.its transmit buffer loaded with new in-
ration is used. formation after an acknowledge.
3) The 8044 CPU can clear RTS. This will prevent a
response from being sent, or abort it if it is already
8.4 8044 Data Link Particulars in progress. A system using external RTS/CTS
handshaking could use a. one-shot delay RTS or
The following facts should be noted: CTS, thereby giving the CPU more time to disable
1) In a non-loop configuration, one or two bits are the reSponse.
transmitted before -the opening flag. This is neces-
sary for NRZI synchronization.
13-14
RUPITM~44 SIU
RECEIVE
NEXTBYTE
NO
AlIORT, SHORT FRAME,
OR INVALID
I FRAME CTRL FIELD .. RCI
NO
YES
I'IELD .. RFC aUF
lAO
s •• Figure, 7c thru 7)
296165-10
Figure 7a. SIU AUTO Mode Receive Flowchart-General
13-15
inter RUPITM~44 SIU
uAM" ......
uSI" -4-1
"RBE tI. . - •
..SES......
uSER"~'
296165-11
Figure 7b. SIU AUTO Mode Receive Flowchart-Unknown Command
13-16
RUPITM·44 SIU
.IIAMn~o
"RBE"..-O
"SI" .... 1
296165-12
Figure 7c. SIU AUTO Mode Receive Flowchart-Unnumbered Poll
13-17
inter RUPITM·44 SIU
NO
296165-13
Figure 7d. SIU AUTO Mode Receive Flowchart--Supervlsory Command
13-18
inter RUPITM_44 SIU
BAD
I COMMAND
NRi~
N P --NRS
NllSl + 1
,,~ '- 1, "Na" - •
"RBE"_'
"TBF"_'
Ns-Ns+1
"5ES"_.
"SER"_'
"SI" _1
296165-14
Figure 7e. SIU AUTO Mode Receive Flowchart-I Command: Prior
Transmitted I-Field Confirmed, Current Received I-Field In Sequence
13-19
intJ RUPITM·44 SIU
BAD
ICpMMAND
NRIP) ~ HsIS)
HsIP) ~ HRIS)
"AM" = ,,"Nan ....
.. RBE...... .
.. SES...... .
.. SER ...... .
"SI" .... 1
296165-15
Figure 7f. SIU AUTO Mode Receive Flowchart-I Command: Prior..
Transmitted I-Field Not Confirmed, Current Received I-Field In Sequence
13-20
intJ RUPITM·44 SIU
BAD
I COMMAND
NAIP) " NsIS) + ,
NRIP) '" NsIS)
NsIP) - NAIS)
"AM" - " "NB" =0
"AM" ....
"SES"-+-'
"SER"-+-O
"RBE"_O
"51" ... ,
296165-16
Figure 7g. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error S",nd, Current Received I·Fleld In Sequence
13-21
inter RUPITM-44 SIU
BAD
I COMMAND
NR(P) - NS(S) + 1
NS(P) .. NR(S)
"AM" = 1, "NB" = 0
.. BOV..... 1
"AM" ....
..RBE.. ·....
"TBF"_.
NS~NS+l
"SES"_'
"SER" .... 1
"SI" _1
296165-17
Figure 7h. SIU AUTO Mode Receive Flowchart-I Command:
Prior Transmitted I-Field Confirmed Sequence Error Receive
13-22
RUPITM·44 SIU
BAD
I COMMAND
NRIP) - NsIS)
NsIP) .. NRIS)
"AM" "'" 1, "NB" = 0
"AM" _ _ "BOY"_1
"AM" _ _
"RBE" _ _ "RBE" . . _
SI _1
uSI" -4-1
296165-18
Figure 7i. SIU AUTO Mode Receive Flowchart-I Command:
Prior Transmitted I·Field Not Confirmed, Sequence Error Receive
13-23
inter RUPITM·44 SIU
BAD
I COMMAND
HAIPI" Ha\SI + 1
NRP "NaS
NaIP)" NR P)
"AM" - 1. nNB" .. 0
UAM" ....
"RBE"'-'
"SES"'-l
"SER"~1
1181" ..... 1
296165-19
Figure 7J. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error Send and Sequence Error Receive
13·24
intJ RUPITM·44 SIU
X MIT X MIT X MIT
I RR RNR
FRAME FRAME FRAME
296165-20
Figure 8. Siu AUTO Mode Transmit Flowchart
13-25
RUPITM-44 SIU
LOAD I-FIELD
INTO
XMITBUFFER
PROCESS
INFORMATION
OR
SET "RBP"
296165-21
Figure 9. AUTO Mode Response to "SI"
13-26
inter RUPITM_44 SIU
RECEIVE
NEXT BYTE
NO -----j
I
YES
I
I
ABORT,
SHORT FRAME
I
OR INVALID I
RECEIVE MESSAGE
CTRL FIELD ....RCB,
- - -
I RBE ~.
.... (ABORT FROM CPU)
I FIELD .... REC BUF,
SET BOV ON OVERRUN
BAD
GOOD
CLEAR "RBE"
SET "SI"
L----------toII-------...J
296165-22
Figure 10. SIU FLEXIBLE Mode Receive Flowchart
13-27
inter RUPITM-44 SIU
PROCESS MESSAGE,
SeT UP RESPONSE
IF NECESS;ARY
296165-23
Figure 11. FLEXIBLE Mode Response to Receive "51"
13-28
inter RUPITM-44 SIU
~UT-OFF - LOOP) +
CTS-LOOP
r - - - - -=.- - -
TRANSMIT MESSAGE
USING TCB FOR
CONTROL FIELD
----,
[ABORT FROM PRIMARY]
I TBF
(ABORT FROM CPU)
I
I I
~ I
I
CLEAR "TBF"
I
~=~l_ _~_ _ _ _ _ _ _ _~~~~~ ______ J
CLEAR "RTS"
SET "SI"
TRANSMIT
ABORT
SEQUENCE
296165-24
Figure 12. SIU FLEXIBLE Mode Transmit Flowchart
13-29
inter RUPITM·44 Slu
CLEAR"SI"
lIMIT
= I,PENDING
TBF INDICATEB
BUFFULL LAST TRANSMIT
ABORTED IV CPU
ORPR_V.
BUFEMPTY
CTRL FIELD . .TCI
I-FIELD .. XMIT aUF
SET"TI"
SET "ATS·
296165-25
FIgure 13" FLEXIBLE Mode Re.ponse to Transmit "SI" .
13·30
intJ RUPITM-44 SIU
9.0 MORE DETAILS ON SIU The zero insert/delete circuitry (ZID) performs zero
HARDWARE insertion/deletion, and also detects flags, GA's (Go-
Ahead's), and aborts (same as GA's) in· the data
The SIU divides functionally into two sections-a bit stream. The pattern 1111110 is detected as an early
processor (BIP) and a byte processor (BYP~haring GA, so that the GA may be turned into a flag for loop
some common timing and control logic. As shown in mode transmission.
Figure 14, the BIP operates between the serial port pins
and the SIU bus, and performs all functions necessary The shut-off detector monitors the receive data stream
to transmit/receive a byte of data to/from the serial for a sequence of eight zeros, which is a shut-off com-
data stream. These operations include shifting, NRZI mand for loop mode transmissions. The shut-off detec-
encoding/decoding, zero insertion/deletion, and FCS tor is a three-bit counter which is cleared whenever a
generation/checking. The BYP manipulates bytes of one is found in the receive data stream. Note that the
data to perform message formatting, and other trans- ZID logic could not be used for this purpose, because
mitting and receiving functions. It operates between the the receive data must be monitored even when the ZID
SIU bus (SIB) and the 8044's internal bus (IB). The is being used for transmission.
interface between the SIU and the CPU involves an
interrupt and some locations in on-chip RAM space As an example of the operation of the bit processor, the
which are managed by the BYP. following sequence occurs in relation to the receive
data:
The maximum possible data rate for the serial port is 1) RXD is sampled by SCLK, and then synchronized
limited to '12 the internal clock rate. This limit is im- to the internal processor clock (IPC).
posed by both the maximum rate of DMA to the on- 2) If the NRZI mode is selected, the incoming data is
chip RAM, and by the requirements of synchronizing NRZI decoded.
to an external clock. The internal clock rate for an 8044
running on a 12 MHz crystal is 6 MHz. Thus the maxi- 3) When receiving other than the flag pattern, the ZID
mum· 8044 serial data rate is 3 MHz. This data rate deletes the '0' after 5 consecutive 'l's (during trans-
drops down to 2.4 MHz when time is allowed for exter- mission this zero is inserted). The ZID locates the
nal clock synchronization. byte boundary for the rest ofthe circuitry. The ZID
deletes the 'O's by preventing the SR (shift register)
from receiving a clocking pulse.
9.1 The Bit Processor 4) The FCS (which is a function of the data between
the flags-notincluding the flags) is initialized and
In the asynchronous (self clocked) modes the clock is started at the detection of the byte boundary at the
extracted from the data stream using the on-chip digital end of the opening flag. The FCS is computed each
phase-locked-loop (DPLL). The DPLL requires a clock bit boundary until the closing flag is detected. Note
input at 16 times the data rate. This 16 X clock may that the received FCS has gone through the ZID
originate from SCLK, Timer 1 Overflow, or PH2 (one during transmission.
half the oscillator frequency). The extra divide by-two
described above allows these sources to be treated alter-
natively as 32 X clocks. 9.2 The Byte Processor
The DPLL is a free-running four-bit counter running Figure 15 is a block diagram of the byte processor
off the 16 X clock. When a transition is detected in the (BYP). The BYP contains the registers and controllers
receive data stream, a count is dropped (by suppressing necessary to perform the data manipulations associated
the carry-in) if the current count value is greater than 8. with SDLC communications. TheBYP registers may
A count is added (by injecting a carry into the second be read or written by the CPU over the 8044's internal
stage rather than the first) if the count is less than 8. No bus (IB), using standard 8044 hardware register opera-
adjustment is made if the transition occurS at the count tions. The 8044 register select PLA controls these oper-
of 8. In this manner the counter locks in on the point at ations. Three of the BYP registers connect to the IB
which transitions in the data stream occur at the count through the IBS, a sub-bus which also connects to the
of 8, and a clock pulse is generated when the count CPU interrupt control registers.
overflows to O.
In order to perform NRZI decoding, the NRZI decod-
er compares each bit of input data to the previous bit.
There are no clock delays in going through the NRZI
decoder. .
13-31
RUPITM·44 SIU
INTERRUPT
IB'
1
RAM CPU
r - ---- ------- i-------------Siij..,
I
I
-1 ~ I
SHARED
REGISTERS
I
I 1/01RXD
- BYP BIP I DA'J:AITXD
SIB I
I
L _____________ ~ _________ ~---J
296165-26
Figure 14. The Bit and Byte Processors
Simultaneous access of a register by both the IB and the 2) Assuming that there is a control field in the frame,
SIB is prevented by timing. In particular, RAM access the BYP takes the next byte and loads it into the
is restricted to alternate internal processor cycles for RCB register. The RCB register has the logic to
the CPU and the SIU, in such a way that collisions do update the NSNR register (increment receive count,
not occur. set SES and SER flags, etc.).
3) Assuming thatthere is an information field, the next
As an example of the operation of'the byte processor, byte is dumped into RAM at the RBS location. The
the following sequence occurs in relation to the receive DMA CNT (RBL at the opening flag) is loaded
data: from the DMA CNT register into the RB register
1) Assuming that there is an address field in the frame, and decremented. The RFL is then loaded into the
the BYP takes the station address from ihe regist~ RB register, incremented, and stored back into the
me into temporary storage. After the opening flag, register me.
the next field (the address field) is compared to the 4) This process continues until the DMA CNT reache~
station address in the temporary storage. If a match zero, or until a closing flag is received. Upon either
occurs, the operation continues. event, the BYP updates the status, and, if the CRC
is good, the NSNR register.
13·32
intJ RUPITM·44 SIU
Ir----~----------,
RAM
SIB
BYP
TIMING SHARED IB
AND REGISTERS
CONTROL
I
I
I
~ I
I
L ______________ ~~
296165-27
Figure 15. The Byte Processor
10.0 DIAGNOSTICS stream to the SIU by writing to P3.0. The transmit data
stream can be monitored by reading P3.1. Each succes-
An SIU test mode has been provided, so that the on- sive bit is transmitted from the sm by writing to any
chip CPU can perform limited diagnostics on the SIU. bit in .Port 3, which generates SCLK.
The test mode utilizes the output latches for P3.0 and
P3.1 (pins 10 and II). These port 3 pins are not useful In test mode, the P3.0 and P3.1 pins are placed in a
as out-put ports, since the pins are taken up by the high voltage, high impedance state; When the CPU
serial port functions. Figure 16 shows the signal routing reads P3.0 and P3.1 the logic level applied to the pin
associated with the SIU test-mode. will be returned. In the test mode, when the CPU reads
3.1, the transmit data value will be returned, not the
Writing a 0 to P3.1 enables the serial test mode (P3.1 is voltage on the pin. The transmit dilta remains constant
set to I by reset). In test mode the P3.0 bit is mapped for a bit time. Writing to P3.0 will result in the signal
into the received data stream, and the 'write port 3' being outputted for a short period of time. However,
control signal is mapped into the SCLK path in place of since the signal is not latched, P3.0 will quickly return
TI. Thus, in test mode, the CPU can send a serial data to a high voltage, high impedance state.
13-33
.~. ..
!J
SCLKI
'5
~_'_-r_IQ-~~-~-H~DI_·~
----' 1 ~. ~ I _,_
SYSCLK
I l
..
L!J
'IN1"
~
,I
/1
A
PH
~§-
_.-
.. RXDI
...
~ •
~
f
__
~n ~
....
w .~
~.,..,...
c:i!:
en
2
READ PORT 3
WRITE PORT 3
PINII
DATAl SlU
TXDI TRANSMIT
P31 DATA
STREAM
296165-28
inter RUPITM_44 SIU
The serial test mode is disabled by writing a I to P3.1. transmits a supervisory frame. This frame consists of an
Care must be taken that a 0 is never written to P3.1 in opening flag, followed by the station address, a control
the course of normal operation, since this causes the field indicat~g that this is a supervisory frame with an
test mode to be entered. , RNR command, and then a closing flag.
Figure 17 is an example of a simple program segment Each byte of the frame is transmitted by writing that
that can be imbedded into the user's diagnostic pro- byte into the A register and then calling the subroutine
gram. That example shows how to put the 8044 into XMIT8~ Two additional SCLKs are generated to guar-
"Loop-back mode" to test the basic transmitting and antee that the last bits in the frame have been clocked
receiving functions of the SIU. into the SIU. Finally the CPU reads the status register
(STS). If the operation has proceeded correctly, the
Loop-back mode is functionally equivalent to a hard- status will be 072H. If it is not, the program jumps to
wire connection between pins 10 and 11 on the 8044. the ERROR loop and terminates.
In this example, the 8044 CPU plays the role of the The SIU generates an SI (SIU interrupt) to indicate
primary station. The SIU is in the AUTO mode. The that it has received a frame. The CPU clears this inter-
CPU sends the SIU a supervisory frame with the poll rupt, and then begins to monitor the data stream that is
bit set and an RNR command. TheSIU responds with being generated by the SIU in response to what it has
a supervisory frame with the poll bit set and an RR received. As each bit arrives (via P3.1), it is moved into
command. the accumulator, and the CPU compares the byte in the
accumulator with 07EH, which is the opening flag.
The operation proceeds as follows: When a match occurs, the CPU identifies this as byte
boundary, and thereafter processes the information
Interrupts are disabled, and the self test mode is en- byte-to-byte.
abled by writing a zero to P3.1. This establishes P3.0 as
the data path from the CPU to the SIU. CTS (clear-to- The CPU calls the RCV8 subroutine to gct each byte
send) is enabled by writiIjg a zero to P1.7. The station into the accumulator. The CPU performs compare op-
address is initialized by writing 08AH into the STAD er~tions on (successively) the station address, the con-
(station address register). trol field (which contains the RR response), and the
closing flag; If any of 'these do not compare, the pro-
The SIU is configured for receive operation in the gram jumps to the ERROR loop. If no error is, found,
clocked mode and in AUTO mode. The CPU then the program jumps to the DONE loop.
13-35
inter RUPITM.-44 SIU
, ISIS-II PICa-51 .....CRD .AS_I-ER 112,.0 .
DI~CT IIODULE PLACED IN· : Fl : DATA, DB"
ASSEttI.LIER 'INVOKED ,IV: .... 51: ,flo: ... t •. un d.vic.(44)
LDC DB" LIN!' SOURCE
I'
2
0000 7SCaOO '3 INIT: MOIl . BTS.IOOH
. DDQ3 C211 4 CLR P3,I I Enebl. ,.U t •• t Mod.
0005 C297 5 ,CLR PI.7 En.bl. eTa
0007 7SCEBA 6 .II1I\I 'STAD. lBAH J Int tiel i Ie .eld" •••
,7
8 J' CONFIGURE RECEIVE OPERATION
9
OODA "7'D86~ 10 11011 NBHR • • •AH NSCS)-3; SES-C. NR(9)-,. SER-O
DODD 7,C901 11 II1I\I BI1D, eolH NFee-t
0010 7'CaC2 12 ICIII aTB. eOC2H J TIF-l. RIE-l, Nt-l
13
14· TRMSI1IT A _ERIiISORV FR_ FRDI1 THE PRII1M~ STATION WITH.THE POLL.
15 8 IT SET AND A RNA CDI1IIAND
16
0013 747E 17 S~N~: ICI\I A. 17EH Th. SIU rec .. i V.I .. ne. ftT's.'"
0015 1200..6 18 CALL XI1ITS
oole 74.... 19 11011 A. laAH , The .dd" ••• is n •• t
OOIA 120066
OOID 7495
20
21
CIILL
II1I\I
XI'IIT&
A. 1095H , RNIt SUP FANE with P/F-l. NRCP)-4
OOIF 120066 22 CIILL
0022 747E 23 11011
XI'IIT8
A. 17EH , Receive clasing fie.
0024 120066 24 " CIILL 1"IT8
0027 D210 25
'.26
SETa P3,O O.n.".t ••• t".
SCUV. to
0029 D210 ··8ETI P3,O Initiate "eceive acUon
27
002a E,eB 28 "Oil It.,i 8T9 Chec II '0" .p,,,o,,,i.te st.tus
002D 14722A 29 CJNE A. .72H. ERROR
30
31 ; PREPIt.RE TO RECEIVE RUP!'. RESPONCE TO PRI"lt.Ry·S RNA
32
33
34
0030 ·C2CC 35 REClio CLA Cl •• " II
0032 7400. 36 IlO\l .Cl •• " ACC
0034 710C 37 ICI\I I T"II l2 ti •••
38
39 LIIOK. FOR THE OPENING FLAO
40
0036 D210 41 WFLIIO I: :SETB P3.0 I SCL.M.'
0038 A211 42 1'1011 C, P3.1 I T".n •• itt.1I d.t•
003A 13 43 . ', RRC A
0031 147E03 44 C.JNE AI .07EH. WFLO 1
OOlE 0:10046 45 JI'ff' CNTINU
0041 DIF3 46 WFLO I : D.JNZ R3. WFLAOI
0043 0200"'" 47 JI1P ERROR
48
49
0046 1200SC 50 CNTINU: CALL RCIIB O.t SIU'. T".n •• itted .dd" ••• U.U
004914_ 51 A. 1000H. ERROR
004C 1200SC 52
C"NE
CALL RCIIB , P"'··"II e.pect. ta ,..eceiv. RR '''D. SIU
oo4F 141108 53 C"NE A. 10BlH. ERROR
0052 I:IOOSC 54 CALL RCIIS Receive clasing fl ••
0055 147E02
005e aOFE
"56 C"NE A. 107EH. ERROR
57
58
DONE: "11P DONE
00"," 80FE 5. ERROR: JI1P ERROR
60
61
OO5C 7808 62 RCIIB: 11011 RO.108 , In' tieU I. the, b" cDunt."
oo5E D2ao 63 OETB I T: SETB P3,O SCLK
0060 A211 64 11011 C. P3, I I T"e".1111 tted d.t.
0062 13 65 RRC A
0063 D8F9 66 DJNZ RO. OETIIT
0065 22 67 RET
68
6"
70
0066 780" 71
0068 13 72
73
006" DBOI 74
0068 22 75
76
006C 4004 77
7a
006E C2BO 79
0070 BOF6 80
81
007~ D280 82
0074 8OF2 83
84
296165-29
Figure 17. Loop-Back Mode S~ftware
13-36
8044 Application Examples . 14
8044 APPLICATION EXAMPLES
1.0 INTERFACING THE 8044 TO A ure 3 shows the 8088 and support circuitry; the memo-
MICROPROCESSOR ry and decoders are not shown. It is a basic 8088 Min
Mode system with an 8237A DMA controller and an
The 8044 is designed to serve as an intelligent control- 8259A interrupt controller.
ler for remote peripherals. However, it can also be used
as an intelligent HDLC/SDLC front end for a micro- DMA Channel One transfers a block of memory to the
processor, capable of extensively off-loading link con- tri-state latch, while Channel Zero transfers a block of
trol functions for the CPU. In some applications, the data from the latch to 8088's memory. The. 8044's In-
8044 can even be used for communications preprocess- terrupt 0 signal vectors the CPU into a routine which
ing, in addition to data link control. reads from the internal RAM and writes to the latch.
The 8044's Interrupt 1 signal causes the chip to read
This section describes a sample hardware interface for from the latch and write to its on-chip data RAM. Both
attaching the 8044 to an 8088. It is general enough to DMA requests and acknowledges are active low.
be extended to other microprocessors such as the 8086 .
or the 80186. Initially, when the power is applied, a reset pulse com-
ing from the 8284A initializes the SR flip-flops. In this
initialization state, the 8044's transmit interrupt and
OVERVIEW the 8088's transmit DMA request are active; however,
the software keeps these signals disabled until either of
A sample interface is shown in Figure 1. Transmission the two processors are ready to transmit. The software
occurs when the 8088 loads a 64 byte block of memory leaves the receive signals enabled, unless the receive
with some known data. The 8088 then enables the buffers are full. In this way either the 8088 or the 8044
8237A to DMA this data to the 8044. When the 8044 are always ready to receive, but they must enable the
has received all of the data from the 8237A, it sends the transmit signal when they have prepared a block to
data in a SDLC frame. The frame is captured by the transmit. After a block has been transmitted or re-
Spectron Datascope™* which displays it on a CRT in ceived, the DMA and interrupt signals return to the
hex format. initial state.
In reception, the Datascope sends a SDLC information The receive and transmit buffer sizes for· the blocks of
frame to the 8044. The 8044 receives the SDLC frame, data sent between the 8044 and the 8088 have a maxi-
buffers it, and sends it to the 8088's memory. In this mum fixed length. In this case the buffer size was 64
e~ample the 8044 is being operated in the NON-AUTO
bytes. The buffer size must be less than 192 bytes to
mode; therefore, it does not need to be polled by a pri- enable 8044 to buffer the data in its on-chip RAM. This
mary station in order to transmit. design allows blocks of data that are less than (i4 bytes,
and accommodates networks that allow frames of vary-
THE INTERFACE ing size. The first byte transferred between the 8088
and the 8044 is the byte count to follow; thus the 8044
The 8044 does not have a parallel slave port. The knows how many bytes to receive before it transmits
8044's 32 I/O lines can be configured as a local micro- the SDLC frame. However, when the 8044 sends data
.processor bus master. In this configuration, the 8044 to the 8088's memory, the .8237A will not know if the
can expand the ROM and RAM memory, control pe- 8044 will send less than the count the 8237A was pro-
ripherals, and communicate with a microprocessor. grammed for. To solve this problem, the 8237A is oper-
ated in the single mode. The 8044 uses an I/O bit to
The 8044, like the 8051, does not have a Ready line, so generate an interrupt request to the 8259A. In the
there is no way to put the 8044 in wait state. The clock 8088's interrupt routine, the 8237A's receive DMA
on the 8044 cannot be stopped. Dual port RAM could channel is disabled, ~us allowing blocks of data less
still be used, however, software arbitration would be than 64 bytes to be received.
the only way to prevent collisions. Another way to in-
terface the 8044 with another CPU is to put a FIFO or
queue between the two processors, and this was the THE SOFTWARE
method chosen for this design. The software for the 8044 and the 8088 is shown in
Table 1. The 8088 software was written in PL/M86,
Figure 2 shows the schematic of the 8044/8088 inter- and the 8044. software was written in assembly lan-
face. It involves two 8-bit tri-state latches, two SR flip- guage.
flops, and some logic gates (6 TTL packs). The circuit-
ry implements a one byte FIFO. RS422 transceivers are The 8044 software begins by initializing the stack, in-
used, which can be connected to a multidrop link. Fig- terrupt priorities, and triggering types for the inter-
*Datascope is a trademark of Spectron Inc. rupts. At this point, the SIU parameter registers are
14-1
inter RUPITM_44
DATASCOPE
296166-1
Figure 1. Block Diagram of 8088/8044 Interface Test
initialized. The receive and transmit buffer starting ad- NormaIly this interrupt remains disabled. However, if a
dresses and lengths are loaded for the on-chip DMA. serial interrupt occurs, and the SERIAL INT routine
This DMA is for the serial port. The serial station ad- detects that a frame has been received, it caIls the
dress and the transmit control bytes are loaded too. SEND subroutine. The SEND subroutine loads the
. number of bytes which were received in the frame into
Once the initialization has taken place, the SIU inter- the receive buffer. Register RI points to the receive
rupt is enabled, and the external interrupt which· re- .buffer and R2 is loaded with the count. The TRANS-
ceives bytes from the 8088 is enabled. Setting the 8044's MIT DMA interrupt is enabled, and immediately upon
Receive Buffer Empty (RBE) bit enables the receiver. If returning from the SERIAL INT routine, the interrupt
thiS bit is reset, no serial data can be received. The 8044 is acknowledged. Each time the TRANSMIT DMA in-
then waits in a loop for either RECEIVE DMA inter- terrupt occurs, a byte is read from the receive buffer,
rupt or the SERIAL INT interrupt. written to the latch, and R2 is decremented. When R2
reaches 0, the TRANSMIT DMA interrupt is disabled,
The RECEIVE DMA interrupt occurs when the the SIU receiver is re-enabled, and the 8044 interrupts
8237A is transferring a block of data to the 8044. The the 8088.
first time this interrupt occurs, the 8044 reads the latch
and loads the count value into .the R2 register. On sub-
sequent interrupts, the 8044 reads the latch, loads the .CONCLUSION
data into the transmit buffer, and decrements R2. For the software shown in Table I, the transfer rate
When R2 reaches zero, the interrupt routine sends the from the 8088's memory to the 8044 was measured at
data in an SDLC frame, and disables the RECEIVE 75K bytes/sec. This transfer rate largely depends upon
DMA interrupt. After the frame has been transmitted, the number of instructions in the 8044's interrupt serv-
a serial interrupt is generated. The SERIAL INT rou- ice routine. Fewer instructions result in a higher trans-
tine detects that a frame has been transmitted and re- fer rate.
enables the RECEIVE DMA interrupt. Thus, while the
frame is being transmitted through the SIU, the 8237A There are many ways of interfacing the 8044 loca1ly to
is inhibited from sending data to the 8044's transmit another microprocessor: FIFO's, dual port RAM with
buffer. .
software arbitration, and 8255's are just a few. Alterna-
tive approaches, which may be more optimal for certain
The TRANSMIT DMA routine sends a block of data applications, are certainly possible.
from ·the 8044's receive buffer to the 8088's ~emory.
14-2
DACKI
l
"'II
c'
c
iil
!"
:g .
....
.... :D
..... 5'
....•
Co)
-
CD
::l.
c:
'U
~
~
CD
DACK,
•••
0'
if
CD
g
CD
Vee
RUPI EXPANSION BUS 2128
PI
296166-2
CS ~
~ "''''''
OBOOOFOH
·s
l
B3 6520
PCLK rr:==~:j:~
SEL
A3
g~03
04
MEMR
lOR
MEMW
M~ ~
CLK B1 5257 +5V
~ 03 ~
"1\
iFi ~ M~ {~
c
; r---~------------------------~8237CS
r----i> +5V
~ - 0 RESET
CO
~~ITn~~t~!f::~====~3~~~~ HlDA
g ...,b-:==.......Ir--. DACK. DACK.
XI
c:
..... CO +5 HOLO ALE Dt g~~~
DREQt g:~~l
DREQt
"U
3C CLK 8237-2 DREQ2 DREQ2
~
.j>.
.P.. S" RESEli OACK2
OREQ3
OACK2
I
~ INTR 01lio
g-
j
r
li
NMI
8088 AD7
r========~STB~-JOE""--'
017 D07 J1
~
AO-A7
01lio
B =
3 (MIN) :: g:: gg: F1
TEST g:; N ~
INTR ~g~ gl~ :s gw,
A15A~ll1~ADt Ott .. Dot (((((((( -ooo-D7
~
...J.
~~~ l{ D~M
•
OESTB~
DI7 007
015 DOS '
014 N 004
g~; gg~
011 DOl
Ott Oot1J
296166-3
intJ RUPITM-44
37 ;•••••••••••••••••••••••••• SUBROUTINES •••••••••••••••••••••••••••••••
38
0058 85CD29 39 SEND: MOV 41.RFL ; FIRST BYTE IN BLOCK IS COUNT
005B 7929 40 MOV RI. '41 ; POINT TO BLOCK OF DATA
005D AACD 41 MOV R2. RFL ; LOAD COUNT
005F OA 42 INC R2
0060 D2A8 43 SETB EXO ; ENABLE DMA TRANSMIT INTERRUPT
0062 22 44 RET
45
46
47
48 .;................... INTERRUPT SERVICE ROUTINES •••••••••••••••••••••
49
0063 50 LOLTMPSET $ ; SET UP INTERRUPT TABLE JUMP
0013 51 ORG .0013H
0013 020063 52 LJMP RECEIVE_DMA
0063 53 ORG LOLTMP
S4
55 RECEIVE-DMA:
296166-69
14-5
intJ RUPITM·44
Table 1. Transmit and Receive Software.for an S044/S0SS·System (Continued)
56
0063 IOOOOE 57 JBC FIRSLBYTE. LI ; THE FIRST BYTE TRANSFERRED IS THE COUNT
58
0066 EO 59 MOVX A.@DPTR ; READ THE LATCH
0067 F6 60 MOV @RO.A ; PUT IT IN TRANSMIT BUFFER
0068 08 61 INC RO
0069 DA08 62 DJNZ R2.L2 ; AFTER READING BYTES.
63
006B D2CF 64 SETB TBF ;SEND DATA
OO6D D2CD 65 SETB RTS
006F D200 66 SETB FIRSLBYTE
0071 C2AA 67 CLR EXI
68
0073 32 69 . L2: RETI
70
0074 78M 71 1I: . MOY RO.lI06 ; RO IS A POINTER TO THE TRANSMIT
72 ; BUFFER STARTING ADDRESS
0076 EO 73 .MOYX A.@DPTR ; PUT THE FIRST BYTE INTO
0077 FA 74 MOY R2. A ; R2 FOR THE COUNT
0078 32 75 RETI
76
0079 77 LOLTMPSET . $
0003 78 ORG ooom
0003 020079 79 LJMP TRANSMILDMA
0079 80 ORG LOLTMP
81
82 TRANSMILDMA
83
0079 E7 84 MOV A.@RI ; READ BYTE OUT OF THE RECEIVE BUFFER
007A FO 85 MOVX [email protected] ; WRITE IT TO THE LATCH
0078 09 86 INC RI
007C DA08 87 DJNZ R2.13 ; WHEN ALL 8YTES HAVE. BEEN SENT
88
007E C2A8 89 ClR IE.O ; DISABLE INTERRUPT
0080 C294 90 CLR PI.4 ; CAUSE 8088 INTERRUPT TO TERMINATE DMA
0082 D294 91 SETB PI. 4
0084 D2CE 92 SETB RBE ; ENABLE RECEIVER AGAIN
93
0086 32 94 13: RETI
95
96
97
0087 98 LOC-T~PSET S
0023 99 ORG 0023H
0023 020087 100 LJMP SERIALINT
0087 101 ORG LOC-TMP
102
103 SERIALINT:
104
0087 3OCE06· 105 JNB RBE.RCV ; WAS A FRAME RECEIVED
008A 30CFOB 106 JNB TBF.XMIT ; WAS A FRAME TRANSMITTED
008D 020056 107 LJMP ERROR ; IF NEITHER ERROR
108
00902OCBC3 109 RCV: JB BOV.ERROR ; IF BUFFER OVERRUN THEN ERROR
0093 1158 110 CALL SEND. . ; SEND THE FRAME TO THE 8088
0095 C2CC III CLR SI
0097 32 112 RETI
113
0098 C2CC 114 XMIT: CLR SI 296166-70
14-6
inter RUPITM-44
Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
009A D2AA 115 SETB EXI
009C 32 116 RET!
117
lIB END
SYMBOL TABLE LISTING
NAME TYPE VALUE ATTRIBUTES
BOV B ADDR OOCBH.3 A
ERROR C ADDR 0056H A
EXO B ADDR OOABH.O A
EXI B ADDR OOABH.2 A
FIRSLBYTE B ADDR 0020H.O A
IE D ADDR OOABH A
INIT C ADDR 0026H A
- IP D ADDR OOBBH A
LI C ADDR 0074H A
l2 C ADDR 0073H A
L3 C ADDR 00B6H A
lOCTMP C ADDR 00B7H A
PI D ADDR 0090H A
RBE B ADDR 00CBH.6 A
RBl D ADDR OOCBH A
RBS D ADDR OOCCH A
RCV C ADDR 0090H A
RECEIVLDMA C ADDR 0063H A
RFl D ADDR OOCDH A
RTS B ADDR OOCBH.5 A
SEND C ADDR 005BH A
SERIALINT C ADDR 0087H A
SI B ADDR OOCBH.4 A
SMD D AD DR 00C9H A
SP D ADDR 0081H A
STAD D ADDR OOCEH A
TBF B ADDR 00C8H.7 A
TBl D ADDR OODBH A
TBS D ADDR OODCH A
TCB D ADDR OODAH A
TCON D ADDR 0088H A
THI D ADDR 008DH A
TMOD D ADDR 0089H A
TRANSM IT_DMA C ADDR 0079H A
XMIT C ADDR 009BH A
REGISTER BANK(S) USED: 0, TARGET MACHINE(S): 8044
ASSEMBLY COMPLETE, NO ERRORS FOUND
296166-71
14-7
inter RUPITM-44
Table 2. PL/M-86 Compiler RUPI/8088 Interface Example
SERIES-III PL/~-B6 Vl.0 CO~PILATION OF ~ODULE RUPI_BB
OBJECT ~ODULE PLACED IN :Fl:RBB.OBJ
CO~PILER INVOKED BY: PL~B6.B6 :Fl:RBB.SRC
.DEBUg
.TITLE C'RUPI/BOBB INTERFACE EXA~PLE')
2 DECLARE
LIT LITERALLY 'LITERALLY',
TRUE LIT '01H',
FALSE LIT 'OOH',
RECV_BUFFER(64) BYTE,
X~IT_BUFFER(64) BYTE,
I BYTE,
WAIT BYTE,
'* 8237 PORTS*'
I'tASTER_CLEAR_37 LIT 'OFFDDH',
CO~AND_37 LIT 'OFFDBH',
ALL_~ASK_37 LIT 'OFFDFH',
SINQLE_I'tASK_37 LIT 'OFFDAH',
STATUS 37 LIT 'OFFDSH',
REQUEST_REg_37 LIT 'OFFD9H',
~DE_REg_37 LIT 'OFFDBH',
CLEAR_BYTE.fTR_37 LIT 'OFFDCH',
CHO_ADDR LIT .'OFFDOH',
CHO_COUNT LIT 'OFFDIH',
CHI_ADDR LIT 'OFFD2H',
CHI_COUNT LIT 'OFFD3H',
CH2_ADDR LIT 'OFFD4H',
CH2_COUNT LIT 'OFFD:»i',
CH3_ADDR LIT 'OFFD6H',
CH3_COUNT LIT 'OFFD7H',
'* S237 BIT ASSIQN~ENTS *'
CHO':'SEL LIT \ 'OOH'·,
CHI_BEL LIT .'OlH',
CH2_SEL LIT i02H~,
CH3_SEL LIT '03H',
WRITE_XFER LIT '·04H',
READ_X FER LIT 'OSH',
DEI1ANDJ10DE LIT 'OOH',
SINQLEJ10DE LIT '40H',
BLOCK_~ODE LIT 'BOH~,
SET_~ASK LIT '04H',
.EJECT
,. 8259 PORTS .,
STATUS_POLL_59 LIT 'OFFEOH',
ICWl_59 LIT 'OFFEOH',
OCWl_59 LIT 'OFFEIH',
OCW2_59 LIT 'OFFEOH', "
OCW3_59 LIT 'OFFEOH',
ICW2_59 LIT 'OFFEIH',
ICW3_59 LIT 'OFFEIH',
ICW4_59 LIT 'OFFEIH',
,. INTERRUPT SERVICE ROUTINE .,
OFF_RECVJ)I'IA: PROCEDURE INTERRUPT 32,
4 2 OUTPUTCSINQLEJ1ASK_37).40H,
5 2 WAIT-FALSE,
6 2 END,
296166-4
14-8
RUPITM-44
Table 2. PL/M-86 Compiler RUPII8088 Interface Example (Continued)
7 DISABLE.
'* INITIALIZE 8237 *'
8 I oUTPUTCMA8TER_CLEAR_37) -0.
9 I OUTPUT CCDHMAND_37) -04OH,
10 I OUTPUTCALL~ASK_37) -OFH.
II I OUTPUTCMDDE_REg_37) -C8INQLE~DE OR WRITE_XFER DR CHO_SEL),
12 I oUTPUTCMODEjREg_37) -CSINQLE_MDDE DR READ_XFER DR CHI_SEL),
13 I oUTPUTCCLEAR_BYTE-PTR_37) -0.
14 I oUTPUTCCHO~DDR) -OOH,
1:1 I oUTPUTCCHO~DDR) -40H.
16 I OUTPUTCCHO_COUNT) -64,
17 I OUTPUT CCHO_CoUNT) -00;
18 I OUTPUTCCHI_ADDR) -40H,
19 I oUTPUTCCHI_ADDR) -4OH,
20 I oUTPUTCCHI_COUNT) -64,
21 I OUTPUTCCHI_CoUNT) -00.
'* INITIALIZE 82:19 *'
22 oUTPUTCICWI_:l9) -13H. '*SINgLE MODE. EDQE TRIggERED
INPUT. 8086 INTERRUPT TYPE*'
23 OUTPUT« ICW2_:l9) -2OH. '*INTERRUPT TYPE 32*'
24 OUTPUT« ICW4_'9) -03H. '*AUTo-EoI*'
25 oUTPUTCoCWI_'9) -OFEH. '*ENABLE INTERRUPT LEYEL 0*'
.E.lECT
26 CALL SET. INTERRUPT
27 XMIT_BUFFERCO)-64, '*THE FIR8T BYTE IN THE BLoCK'oF DATA IS THE NUMBER
OF BYTES TO BE TRANSFERED. NOT INCLUDINg THE FIRST BYTE*'
28 I DO I- I TO 64. '* FILL UP THE XMIT-,UFFER WITH DATA *'
29 2 XMIT-,UFFERC I )-1.
30 2 END.
31 oUTPUTCALL_MASK_37)-DFCH, '*ENABLE CHANNEL I AND 2 *'
32 ENABLE,
33 I WAIT-TRUE,
34 I DO WHILE WAIll
3' 2 END, '* A BLOCK OF DATA WILL BE TRANSFERRED TO THE RUPI.
WHEN THE RUPI RECEIVES A BLOCK OF DATA IT WILL
SEND IT TO THE SOBS I1EI'IDRY AND INTERRUPT THE 8088.
THE INTERRUPT' SERYICE ROUTINE WILL SHUT OFF THE DMA
CONTROLLER AND SET 'WAIT' FALSE *'
36 I DO WHILE I,
37 2 END,
38
CODE AREA SIZE - 00D7H 21:10
CONSTANT AREA SIZE - OOOOH 00
YARIABLE AREA SIZE -'OOS2H 1300
MAXIMUM STACK SIZE - OOIEH 300
124 LINES READ
o PRogRAM WARNINQ8
o PROgRAM ERRORS
END OF PL'M-86 COMPILATION
296166-5
14-9
inter RUPITM·44
A HIGH PERFORMANCE NETWORK
USING THE 8044
2.0 INTRODUCTION The user interface to the driver provides four functions:
OPEN, CLOSE, TRANSMIT, and SIU_RECV. Us-
This section describes the design of an SOLC data link ing these four functions properly will allow any applica-
using the 8044 (RUPI) to implement a primary station tion software to communicate over this SOLC data link
and a secondary station. The design was implemented without knowing the details of SOLC. The secondary
and tested. The following discussion assumes that the station driver uses the 8044's AUTO mode.
reader understands the 8044 and SOLC. This section is
divided into two parts. First the data link design exam- The second module is ~n example of application soft-
ple is discussed. Second the software modules used to ware which is linked to the secondary station driver.
implement the data link are described. To help the This module drives the 8215A, butTers data, and inter-
reader understand the discussion of the software, flow faces with the secondary station driver's user interface.
charts and software listings are displayed in Appendix
A and Appendix B, respectively. The third module is a primary station, which is a stand-
alone program (i.e., it is not linked to any other mod-
ule). The primary station uses the 8044's NON-AUTO
APPLICATION DESCRIPTION or FLEXIBLE mode. In addition to controlling the
data link it acts as a message switch. Each time a sec-
This particular data link design example uses a: two ondary station transmits a frame, it places the destina-
wire half-duplex multidrop topology as shown in Fig- tion address of the frame in the first byte of the infor-
ure 4. In an SOLC multidrop topology the primary mation or I field. When the primary station receives a
station communicates with each secOndary station. The frame; it removes the first byte in the I field and re-
secondary stations communicate only to the primary. transmits the frame to the secondary station whose ad-
Because of this hierarchial architecture, the logical to- dress matches this byte.
pology for an SOLC multidrop is a star as shown in
Figure 5. Although the physical topology of this data This network provides two complete layers of the OS1
link is multidrop, the easiest way to understand the (Open Systems Interconnection) reference model: the
information flow is to think of the logical (star) topolo- physical layer and the data link layer. The physical lay-
'gy. The term data link in this case refers !o the logi.cal er implementation uses the RS-422 electrical interface.
communication pathways between the pnmary station The mechanical medium consists of ribbon cable and
and the secondary 'stations. The data links are shown in connectors. The data link layer is defmed by SOLC.
Figure 5 as two way ~rows. SOLC's use of acknowledgements and frame number- '
ing guarantees that messages will be received in the
The application example uses dumb async termina~ to same order in which they were sent. It also guarantees
interface to the SOLC network. Each secondary station message integrity over the data link. However this net-
has an async terminal comiected to it. The secondary work will not guarantee secondary to secondary mes-
stations are in etTect protocol converters which allows sage delivery, since there are acknowledgements be-
any async terminal to communicate with any other tween secondary stations.
async terminal on the network. The secondary stations
use an 8044 with a UART to convert SOLC to async.
Figure 6 displays a block diagram of the data link. The
primary station, controls the data link. In addition to 2.1 Hardware
data link control the primary provides a higher level The schematic of the hardware is given in Figure 7. The'
layer which is a path control function or networking 8251A is used as an async conimunications controller"
layer. The primary serves as a message exchange or in support· of the 8044. TxRDY and RxROY on the
switch. It receives information from one secondary sta- 8251A are both tied to the two available external inter-
tion and retransmits it to another secondary station. rupts of the 8044 since the secondary station driver is
Thus a virtual end to end connection is made between totally interrupt driven. The 8044 butTers the data and
any two secondary stations on the network. some variables in a 2016 (2K x 8 static RAM). The
8254 programmable interval timer is employed as a
Three separate software modules were.written for this programmable baud rate generator and system clock
network. The first module is a Secondary Station Oriv- driver for the 8251A. The third output from the 8254
er (SSO) which provides an SOLC data link interface could be used as an external baud rate generator for the
and a user interface. This module is a general purpose 8044. The 2732A shown in the diagram was not used
driver which requires application software, to run it.
14-10
inter RUPITM·44
since the software for both the primary and secondary 2.2 SOLe Basic Repertoire
stations used far less than the 4K bytes provided on the
8744. For the async interface, the standard RS-232 me- The SDLe commands and responses implemented in
chanical and electrical interface was used. For the the data link include the SDLe Basic Repertoire as
SDLe channel, a standard two wire three state RS-422 defined in the IBM SDLe General Information manu-
driver is used. A DIP switch connected to one of the al. Table 3 shows the commands and responses that the
available ports on the 8044 allows the baud rate, parity, primary and the secondary station in this data link de-
and stop bits to be changed on the async interface. The sign recognize and send.
primary station hardware does not use the USART,
8254, nor the RS-232 drivers.
PRIMARY
STATION
SECONDARY SECONDARY SECONDARY
STATION STATION STATION
296166-6
Figure 4. SDLC Multidrop Topology
SECONDARY SECONDARY
STATION STATION
PRIMARY
STATION
SECONDARY SECONDARY
STATION STATION
296166-.7
Figure 5. SDLC Logical Topology
14-11
RUPITM·44
CD
I
18
~
Figure 6. Block Diagram of the Data Link Application Example
14·12
intJ RUPITM·44
g'
• •
=
Figure 7. Schematic of Async/SDLC Secondary Station Protocol Converter
14·13
inter RUPITM·44
Table 3. Data Link Commands and naI. The SSD is independent of the main application, it
Responses Implemented for This Design just provides the SDLC communications. Existing 8051
applications 'could add high performance SDLC com-
Primary Station munications capability by linking the SSD to the exist-
ing software and providing additional software to be
Responses Commands able to communicate with the SSD.
Recognized S.ent
Unnumbered UA SNAM DATA LINK INTERFACE AND USER
DM DISC INTERFACE STATES
FAMA
*AD The SSD has two Software interfaces: a data link inter-
face and a user interface as shown in Figure 8. The data
Supervisory AA AA link interface is the part of the software which controls
ANA ANA the SDLC communications. It handles link access,
command recognition/response, acknowledgements,
Information I I
and. error recovery. The user interface· provides four
functions: OPEN, CLOSE, TRANSMIT, and SIU_
Secondary Station RECV. These are the only four functions which the
application software has to interface in order to com-
Commands Responses
municate using SDLC. These four functions are com-
Recognized Sent mon to many I/O drivers like floppy and hard disks,
Unnumbered SNAM UA keyboard/CRT, and async communication drivers.
DISC DM
·TEST FAMA The data link and the user interface each have their
own states. Each inierface can only be in one state at
*AD
any time. The SSD uses the states of these two interfac-
"TEST es to help synchronize the application module to the
Supervisory AA AA data link.
ANA ANA
AEJ There are three states which the secondary station data
link interface can be in: Logical Disconnect State
Information I I (L...J)J), Frame Reject State (FRMRJ), and the
"not included in the SOLe Basic Repertoire Information Transfer State (I_T_S). The Logical
Disconnect State is when .a station is physically con-
The term command specifically means all frames which nected to the channel but either the primary or second-
the primary station transmits and the secondary sta.- ary have not agreed to enter the Information Transfer
tions receive. Response refers to frames which the sec- State. Both the primary and the secondary stations syn-
ondary stations transmit and the primary station re- chronize to enter into the InfOl:mation Transfer State ..
ceives. Only when the secondary station is in the I_T_S is it
able to transfer data or information to the primary. The
Frame Reject State (FRMR-S) indicates that the sec-
NUMBER OF OUTSTANDING FRAMES ondary station has lost software synchronization with
the primary or encountered some kind of error condi-
This particular data link design only allows one out- tion. When the secondary station is in the FRMRJ,
standing frame before it must receive an acknowledge- the primary station must reset the secondary to resyn-
ment. Immediate acknowledgement allows the second- cbronize.
ary station drivers to use the AUTO mode. In addition,
one outstanding frame uses less memory for buffering, The user interface has two states, open or closed. In the
and the software becomes easier to manage. closed state, the user program does not want to com-
municate overthe network. The communications chan.'
nel is closed and not available for use. The secondary
2.3 Secondary Station Driver using station tells the prill1ary this by responding to all com-
AUTO Mode mands with DM. The primary continues to poll the
secondary in case it wants to enter the I_T_S state.
The 8044 secondary station driver (SSD) was written as When the user program begins communication over the
it general purpose SDLC driver. It was written to be data link it goes into the open state. It does this by
linked to an application module. The application soft- calling the OPEN procedure. When the user interface is
ware implements the actual application in addition to in the open state it may transfer information to the
interfacing to the SSD. The main application could be, primary.
a printer or plotter, a medical instrument, or a termi-
14-14
inter RUPITM-44
SECONDARY STATION
APPLICATION ··SECONDARY
MODULE STATION
DRIVER
MODULE
DATA
LINK
INTERFACE
SSD
INTERFACE USER DATA LINK
A JI. INTERFACE STATES
1. LOGICAL
r USER STATES DISCONNECT
SSD
t
INTERFACE
1. OPEN
2. CLOSED
STATE
2. INFORMATION
TRANSFER
STATE
PROCEDURES 3. FRAME
REJECT
STATE
OPEN
CLOSE
TRANSMIT ,
SIU RECV
296166-10
Figure 8. Secondary Station Software Modules
14-15
inter RUPITM·44
SECONDARY STATION COMMANDS, - There is a buffer overrun.
RESPONSES AND STATE TRANSITIONS - The Nr that was received from the 'primary station
is invalid.
Table 4 shows the commands which the secondary sta-
tion recognizes and the responses it generates. The first The secondary station cannot leave the FRM~S until
row in Table 4 displays commands the secondary sta- it receives a SNRM or a DISC command.
tion recognizes and each column shows the potential
responses with respect to secondary station. For exam-
ple, if the secondary is in the Logical Disconnect 'State SOFTWARE DESCRIPTION OF THE SSD
it will only respond with DM, unless it receives a
SNRM command and the user state is open. If this is To aid in following the description of the software, the
the case, then the response will be UA and the second- reader may either look at the flow charts which are
ary station will move into the I_T_S. given for each procedure, or read the PL/M-Sl listing
provided in Appendix A.
Figure 9 shows the state diagram of the secondary
station. When power is first applied to the secondary A block diagram of the software structure of the SSD is
station, it goes into the Logical Disconnect State. As given in Figure 10. A complete module is identified by
mentioned above, the I_T_S is entered when the sec- the dotted box, and a procedure is identified by the
ondary station receives a SNRM command and the solid box. Therefore the SIU_RECV procedure is not
user state is open. The secondary responds with UA to included in the SSD module, it exists in the application
let the primary know that it has accepted the SNRM software. Two or more procedures connected by a solid
and is entering the I_T_S. The I_T_S can go into line means the procedure above calls the procedure be-
either the L_D_S or the FRM~S. The I_T_S low. Transmit, Power_on_D, Close, and Open are all
goes into the L_D_S if the primary sends the second- called by the application software. Procedures without
ary DISC. The secondary has to respond with UA, and , any solid lines connected above are interrupt proce-
then goes into the L_D....:.S. If the user interface dures. The only interrupt procedure in the SSD module
changes, from open to' close state, then the secondary is the SIU_INT.
. sends RD. This causes the primary to send a DISC.
The entire SSD module is interrupt driven. Its design
The FRMR_S is entered when a secondary station is allows the application program to handle real time
in the I"":"T_S and either one of the following condi- , events or just dedicate more CPU time to the applica-
tions occurs. tion program. The SIU_INT is the only interrupt pro-
cedure in the SSD. It is automatically entered when an
- A command can not be recognized by the second- SIU interrupt occurs. This particular interrupt can be
ary station. the lowest priority interrupt in the system.
Table 4. Secondary Station Responses to Primary Station Commands
Data Link Primary Station-Commands
States
I RR RNR SNRM DISC TEST
Information I I I
Transfer State RR RR RR
RNR RNR RNR
RD RD RD RD RD
FRMR FRMR FRMR
UA UA
Test
Logical
Disconnect State DM DM DM DM DM DM
UA
Frame FRMR FRMR FRMR FRMR
Reject State UA UA
14-16
intJ RUPITM·44
DISC
UA
~~~ER ____________~
296166-11
Figure 9. State Diagram of Secondary Station
14-17
r------------------------------------~----- (
I I SIU_INT
II I II
1
I SIU_RECY I I
I I COMMAND_DECODE ' I I IN_FRMR_STATE I I IN_DISCONNECT_STATE
I
I
I I
I I
I I I
:!!
CI:I
C
I
I I XMIT_ FRMR I I SNRM_RESPONSE I
a; I
....
~
II
....
!
en
CD
g
:::J
i-J::i J
I XMIT_UNNUMBERED
l:I
c:
'0
':i
(XI
! r-------~---------~---------------------~-~
ill:
•
~
i
~
:::J
C
I POWER_ON_DI
::::!.
...~
.--~
!I OPEN I
I' _ . _ . _ . _ . _ . _ •...1
296166-12
inter RUPITM·44
SSD INITIALIZATION reasons for the SIU to automatically leave the AUTO
mode. The following is a list of these reasons, and the
Upon reset the application software is entered first. The responses given by the SSD based on each reason.
application software initializes its own variables then 1. The SIU has received a command field it does not
calls Power_On~ which is the SSD's initialization recognize.
routine. The SSD's initialization sets up the transmit
and receive data buffer pointers (TBS and RES), the Response: If the CPU recognizes the command, it
receive buffer length (RBL), and loads the State vari- generates the appropriate response. If neither the
ables. The STATION_STATE begins in the L_D_S SIU nor the CPU recognize the command, then a
state, and the USER--STATE begins in the closed FRMR response is sent.
state. Finally Power_OIL-D initializes XMIT_ 2. The SIU has received a Sequence Error Sent
BUFFER--EMPTY which is a bit flag. This flag (SES= 1 in NSNR register). Nr(p);6Ns(S)+ I, and
serves as a semaphore between the SSD and the appli- Nr(P);6Ns(S).
cation software to indicate the status of the on chip Response: Send FRMR.
transmit buffer. The SSD does not set' the station ad-
dress. It is the application software's responsibility to 3. A buffer overrun has occurred. BOV = 1 in STS reg-
do this. After initialization, the SSD is read to respond ister. '
to all of the primary station commands. Each time a Response: Send FRMR.
frame is received with a matching station address and a 4. An I frame with data was received while RPB = 1.
good CRC, the SIU_INT procedure is entered.
Response: Go back into AUTO mode and send an
AUTO mode response
SIU_INT PROCEDURE
In addition to the above reasons, there is one condition
The first thing the SIU_INT procedure clears is the where the CPU forces the SIU out of the AUTO mode.
serial interrupt_bit (SI) in the STS register. If the This is discussed in the SSD's User Interface Proce-
SIU_INT procedure returns with this bit set, another dures section in the CLOSED procedure description
SI interrupt will occur.
, Finally, case three is when the STATION_STATE is
The SIU_INT procedure is branches three indepen- in the I_T_S and the AUTO mode. The CPU frrst
dent cases. The first case is entered if the STATION_ looks at the TBF bit. If this bit is 0 then the interrupt
STATE is not in the 1_TJ . If this is true, then the may have been caused by a frame which was transmit-
SIU is not in the AUTO mode, and the CPU will have ted and acknowledged. Therefore the XMIT_BUFF-
to respond to the primary on its own. (Remember that ER--EMPTY flag is set again, indicating that the ap-
the AUTO mode is entered when the STATION_ plication software can transmit another frame.
STATE enters into LTJ.) If the STATION_
STATE is in the I_TJ, then either the SIU has just The other reason this section of code could be entered
left the AUTO mode, or is still in the AUTO mode. is if a valid I frame was received. When a good I frame
This is the second and third case, respectively. is received the RBE bit equals O. This means that the
receiver is disabled. If the primary were to poll the 8044
In the first case, if the STATIONJTATE is not in while'RBE=O, it would time out since no response
the I_T_S, then it must be in either the L~_S or would be given. Time outs reduce network throughput.
the FRMR--S. In either case a separate procedure is To improve network performance, the CPU first sets
called based on which state the station is in. The IlL- RBP, then sets RBE. Now when the primary polls the
Disconnect_State procedure sends to the primary a 8044 an immediate RNR response is given. At this
DM response, unless it received a SNRM command point the SSD calls the application software procedure
and the USER--STATE equals open. In that case the SIU~CV and passes the length of the data as a
SIU sends a UA and enters into the I_T_S. The IlL- parameter. The SIU_RECV procedure reads the data
FRMR--State procedure will send the primary the out of the receive buffer then returns to the SSD mod-
FRMR response unless it received either a DISC or an ule. Now that the receive information has been trans-
SNRM. If the primary's command was a DISC, then ferred, RBP can be cleared.
the secondary will send a UA and enter into the L_
D_S. If the primary's command was a SNRM, then
the secondary will send a UA, enter into the LT_S, COMMAND_DECODE PROCEDURE
and clear NSNR register.
The Command~ecode procedure is called from the
For the second case, if the STATION_STATE is in SIU_INT procedure when the STATION_STATE
the LT_S but the SIU left the AUTO mode, then t\le == I_TJ and the SIU left the AUTO mode as a
CPU must determine why the AUTO mode was exited, result of not being able to recognize the receive control
and generate a response to the primary. There are four byte. Commands which the SIU AUTO mode does not
14-19
inter RUPITM·44
C·FIELD OF THE REJECTED COMMAND, AS RECEIVED
I
THIS STATION'S PRESENT Ns
r ___
, 0
I THIS STATION'S PRESENT Nr
o
~
W X y Z
,
o o o o
,
HIGH·ORDER
RECEIVED DISAGREES WITH TRA NSMITTED Ns
I I
BUFFER OVERRUN (I·FIELD IS TOo LONG)
PROHIBITED I·FIELD RECEIVED
INVALID OR NONIMPLEMENTED COMMAND
296166-13
Figure 11. Information Field of the FRMR Response, as Transmitted
recognize are handled here. The commands recognized fteld. Figure 11 displays the format for the three data
in this procedure are: SNRM, DISC, and TEST. Any bytes in the I fteld of a FRMR response. The XMIT_
other command received will generate a Frame Reject FRMR procedure sets up the Frame Reject response
with the nonimplemented command bit set in the third frame based on the parameter' REASON which is
data byte of the FRMR frame. Any additional unnum- passed to it. Each place in the SSD code that calls the
bered frame commands which the secondary station is XMITJRMR procedure, passes the REASON that
going to implement, should be implemented in this pro- this procedure was called, which in tum is communi-
cedure. cated to the primary station. The XMITJRMR pro-
cedure uses three bytes of internal RAM which it ini-
IF an SNRM is received the command_decode proce- tializes for the correct response. The TBS and TBL reg-
dure calls the SNR~L•.Response procedure. The isters are then changed to point to the FRMR buffer so
SNR~esponse procedure sets the STATION_ that when a response is sent these three bytes will be
STATE = LTJ, clears the NSNR register and re- included in the I fteld.
sponds with a UA frame. If a DISC is received, the
comman~decode procedure sets the STATION_ The INJRMR-STATE procedure is called by the
STATE = L~J, and responds with a UA frame. SIU_INT procedure when the STATION_STATE
When a TEST frame is received, and there is no buffer already is in the FRMR state and a response is re-
overrun, the command_decode procedure responds quired. The INJRMR-STATE procedure will only
with a TEST frame retransmitting the same data it re- allow two commands to remove the secondary station
ceived. However if a TEST frame is received and there from the FRMR state: SNRM and DISC. Any other
is a buffer overrun, then a TEST frame will be sent command which is received while in the FRMR state
without any data, instead of a FRMR with the buffer will result in a FRMR response frame.
overrun bit set.
XMIT_UNNUMBERED PROCEDURE
FRAME REJECT PROCEDURES
This is a general purpose transmit procedure, used only
There are two .procedures which handle the FRMR in the FLEXIBLE mode, which sends unnumbered ·re-
state: XMIT~R and IN_FRMR-STATE. sponses to the primary. It accepts the control byte as a
XMITJRMR is entered when the secondary station parameter, and also expects the TBL register to be set
ftrst goes into the FRMR state. The frame reject re- before the procedure is called. This procedure waits un-
sponse frame contains the FRMR response in the com- til the frame has been transmitted beforeretuming. If
mand fteld plus three additional data bytes in the I
14-20
RUPITM-44
this procedure returned before the transmit interrupt application software thinks that the SDLC channel is
was generated, the SIU_INT routine would be en- now open and it can transmit. This is not the case. For
tered. The SIU_INT routine would not be able to dis- the channel to be open, the SSD must receive an
tinguish this condition. SNRM· from the primary and respond' with a UA.
However; the SSD does not want to hang up the appli-
SSD's User Interface Procedures-OPEN, CLOSE, cation software waiting for an SNRM from the primary
TRANSMIT, SIU_RECV-are discussed in the fol- before returning from the OPEN procedure. When the
lowing section. TRANSMIT procedure is called, the SSD expects the
STATION_STATE to be in the I_T_S. If it isn't,
The OPEN procedure is the simplest of all, it changes the SSD refuses to transmit the data. The TRANSMIT
the USE~STATE to OPEN_S then returns. This procedure first checks to see if the USE~STATE is
lets the SSD know that the user wants to open the open. If not, the USE~STATE_CLOSED parame-
channel for communications. When the SSD receives a ter is passed back to the application module. The next
SNRM command, it checks the USE~STATE. If the thing TRANSMIT checks is the STATION_STATE.
USE~STATE is open, then the SSD will respond If this is not open, then TRANSMIT passes back
with a UA, and the STATION_STATE enters the LINILJ)ISCONNECTED. This means that the
I_T_S. USE~STATE is open, but the SSD hasn't received
an SNRM command from the primary yet. Therefore,
The CLOSE procedure is also simple, it changes the the application software should wait awhile and try
USE~STATE to CLOSED_S and sets the AM bit again. Based on network performance, one knows the
to O. Note that when the CPU sets the AM bit to 0 it maximum amount of time it will take for a station to be
puts the SIU out of the AUTO mode. This event is polled. If the application software waits this length of
asynchronous to the events on the network. As a result time and tries again but still gets a LINILJ)ISCON-
an I frame can be lost. This is what can happen. NECTED parameter passed back, higher level recovery
1. AM is set to 0 by the CLOSE Procedure. must be implemented..
2. An I frame is received and an SI interrupt occurs. Before loading the transmit butTer and calling the
3. The SIU_INT procedure enters case 2 (STA- TRANSMIT procedure, the application software must
TION_STATE = I_T_S, and AM = 0). check to see that XMIT_BUFFE~EMPTY = 1.
4. Case ~ detects that the USE~STATE = This flag tells the application software that it can write
CLOSED_S, sends an RD response anl.i ignores the new data into the transmit buffer and call the TRANS-
fact that an I frame was received. MIT procedure. After the application software has ver-
ified that XMIT.-BUFFE~EMPTY = I, it fills the
Therefore it is advised to never call the CLOSE proce- transmit buffer with the data and calls the TRANS-
dure or take the SIU out of the AUTO mode when it is MIT procedure passing the length of the buffer as a
receiving I frames or an I frame will be lost. parameter. The TRANSMIT procedure checks for
three reasons why it might not be able to transmit the
For both the TRANSMIT and SIU_RECV proce- frame. If any of these three reasons are true, the
dures, it is the application software's job' to put data TRANSMIT procedure returns a parameter explaining
into the transmit buffer, and take data out of the re- why it couldn't send the frame. If the application soft-
ceive buffet. The SSD does not transfer data in or out ware receives one of these responses, it must rectify the
of its transmit or receive buffers because it does not problem and try again. Assuming these three condi-
know what kind of buffering the application software is tions are false, then the SSD clears XMIT_BUFF-
E~EMPTY, attempts to send the data and returns
implementing. What the SSD does do is notify the ap-
plication software when the transmit buffer is empty, the parameter DAT~TRANSMITTED. XMIT_
BUFFE~EMPTY will not be set to I again until the
XMIT_BUFFE~MPTY = I, and when the re-
ceive buffer is full. data has been transmitted and acknowledged.
One of the functions that the SSD performs to synchro- The SIU.-R,ECV procedure must be incorporated into
nize the application software to the SDLC data link. the application software module. When a valid I frame
However some of the synchronization must also be is received by the SIU, it calls the SIU_RECV proce-
done by the application software. Remember that the dure and passes the length of the received data as a
SSD does not want to hang up the application software parameter. The SIU.-R,ECV procedure must remove
waiting for some event to occur on the SDLC data link, all of the data from the receive butTer before returning
therefore the SSD always returns to· the application to the SIU_INT procedure.
software as soon as possible.
For example, when the application software calls the
OPEN procedure, the SSD returns immediately. The
14-21
inter RUPITM-44
LINKING UP TO THE SSD The SSD module uses the $REGISTERBANK(I) attri-
bute. Some procedures are modified with the USING
Figure 12 shows the necessary parts to include in a attribute based on the register bank Itwei of the calling
PL/M-51 application program that will be linked to the procedure. '
SSD module. RL51 is used to link and locate the SSD
and application modules. The command line used to do
this is: 2.4 Application Module; ASYNC to
SOLC Protocol Converter
RL51 SSD.obj ,filename.obj ,PLM51.LIB TO ,,' One of the purposes of this application module is to
filename & RAMSIZE(192) demonstrate how to interface software to the SSD. An-
other purpose is to implement and test a practical appli-
$registerbank(O) cation. This application software performs I/O with an
user$mod': do; async terminal through a USART, buffers data, and
$include (reg44.dcl) also performs I/O with the SSD. In addition, it allows
decl'are the user on the async terminal to: set the station ad-
lit literally 'literally', dress, set the dc:stination address, and go online lind
buffer_length lit '60', omine. Setting the station address sets the byte in the
SiU_lODit_buffer STAD register. The destination address is the first byte
(buffer_length) byte external idata, in the I field. Going online or otlline results in either
siu_recv_buffer calling the OPEN or CLOSE procedure respectively.
(buffer_length) byte external,
xmit_buffer_emptybit external; After the secondary station powers up, it enters the
'terminal mode', which accepts data from the terminal.
I' external procedures 'I, However, before any data is sent, the user must con-
figure the station. The station address and destination
power _on_d: procedure external,; address must be set, and the station must be placed
end power_on_d; oli1ine. To configure the station the ESC character is
entered at the terminal which puts the protocol con-
close: procedure external using 1; verter into the 'configure mode'. Figure 13 shows the
end close; menu which appears on the terminal screen.
open: procedure external uSing 1;
end open; (1)8044 Secondary Station
/
transmit: proce'dure
(lODit_buffer_length) byte external; 1- Set the Station Address
declare xmit_buffer_length byte; 2- Set the Destination Address
end transmit; 3- Go Online
4- Go Omine
/* local procedures' 'I 5- Return to terminal mode
Enter option _
siu_recv: procedure (length) uSing 1;
public Figure 13. Menu for the Protocol Converter
declare length byte,-
• In the terminal mode data is buffered up in the second~
• ary station. A Line Feed character 'LF' tells the sec-
• ondary station to send an I frame. If more than 60 bytes
are buffered in the secondary station when a 'LF' is
received, the applications software packetizes the data
Figure 12. Applications Module Link Information into 60 bytes or less per frame. If a LF is entered when
the station is omine, an error message comes on the
screen which says 'Unable to Get OIi1ine'.
PL/M-51 AND REGISTER BANKS
The 8044 has four register banks. PL/M-51 assumes The secondary station also does error checking on the
that an interrupt procedure never uses the same bank as async interface for Parity, Framing Error, and Overrun
the procedure it interrupts. The USING attribute of a Error. If one of these errors are detected, an error mes-
procedure, or the $REGISTERBANK control, can be sage is displayed on the terminal screen.
used to ensure that.
14-22
inter RUPITM·44
...
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Figure 14. Block Diagram of Secondary Station Protocol Converter illustrating Buffering
14-23
RUPITM.·44
BUFFERING next loop which polls the XMIT_BUFFER-EMP-
TY bit. When XMIT_BUFFBR-EMPTY equals 1,
There are two separate buffers in the application,mod- the SIU~MITJUFFER can be loaded. The first
ule: a transmit buffer and a receive buffer; The transmit byte in the buffer is loaded with the destination address
buffer receives data from the USART, and sends data while the rest of the buffer is loaded with the data.
to the SSD. The receive buffer receives data from the Bytes are removed from the transmit FIFO and placed'
SSD, and transmits data to the USART. Each buffer is -into the SIU~MITJUFFER until one of three'
a 256 byte software FIFO. If the transmit FIFO be- things happen: 1. a 'LF' character is read out of the
comes full and no 'LF' character is received, the sec-, , FIFO, 2. the number of bytes loaded equals the size of
ondary station automatically begins sending the data. the SIU_XMITJUFFER, or 3. the transmit FIFO
In addition, the application modules will shut off the ,is empty.
terminal's transmitter using CTS until the FIFO has
been partially emptied. A block diagram of the buffer- After the SIU~MITJUFFER is filled, the SSD
ing for the protocol converter is given in Figure 14. TRANSMIT procedure is called and the results from
the procedure are checked. Any result other than
DAT~TRANSMITTED will result in several retries
APPLICATION MODULE SOFTWARE within a finite amount of time. If all the retries fail,
A block diagram of the application module software is then the LINICJ)ISC procedure is called which sends
given in Figure IS. There are three interrupt routines iii a message to the terminal, 'Unable to Get Online'.
this module: USARTJECV_INT, USART_
XMIT_INT, and TIMER-OjNT. The first two are
for servicing the USART. TIMER-O~INT is used If
the TRANSMIT procedure in the SSD is called and When the 8251A receives a charaCter, the RxRDY pin
does not return with the DAT~TRANSMITTED on the 82~IA is activated, and this interrupt procedure
parameter. TIMER-OjNT employs Timer 0 to wait is entered: The routine reads the USART status register
a finite amount of time before trying to transmit again. to determine if there are any errors in the character
The highest priority interrupt is, USART_RECV_ received. If there are, the character is discarded and the
INT. The main program and all the procedures it calls ERROR .procedure is called which prints the type of
use register bank 0, USART~MITjNT and TIM- error on the screen. If there are no errors, the received
ER-O_INT and FIFO-R-OUT use bank' I, while character is checked to see if it's an ESC. If it is an
USARTJECV_INT and all the proCedures it calls ESC, the MENU procedure ~s called which allows the
use register bank 2. ' , 'user t6 charige the configuration. If neither one of these
two conditions exists, the received character is inserted
into the transmit FIFO: The received character mayor
POWER-ON PROCEDURE may not be echoed back to the terminal based on the
The Power_On procedure initializes all of the chips in dip switch settings.
the system including the 8044. The 8044 is initialized to
use the on-chip DPLL with NRZI coding, PreFrame TRANSMIT FIFO
Sync, and Timer I auto reload at a baud rate of
62.5 Kbps. The 8254 and the 8251A are initialized next The transmit FIFO consists of two' procedures: FIFO_
based on the DIP switch values attached to port I on L,3N and FIFO_T_OUT. FIFO_TjN inserts a
the 8044. Variables and pointers are initialized, then the character into the FIFO, and FIFO_T_OUT re-
SSD's Power-Up Procedure, Power_~, is called. moves a character from the FIFO. The FIFO itself is,
Finally, the interrupt system is enabled and the main an array of 256 bytes called FIFO_T. There are two
program is entered. pointers used as indexes in the array to address the
characters: IN_PTR-T and OUTJTR-T. IN_
PTR-T points to the location in the array which will.
MAIN PROGRAM store the next byte of data inserted. OUTJTR-T
The main program is a simple loop which waits for a points t~ the next byte of data removed from the array.
frame transmit command. A frame transmit command Both IN",-PTR-T and OUTJTR-T are declared
is indicated when the variable SEND~ATA is great- as bytes. The FIFO_TjN procedure receives a char-
er than O. The value of SEND~ATA equals the acter from the USART~ECV_INT procedure and
number of 'LF' characters in the transmit FIFO, hence stores it in the array location pointed to by IN_PTR-
it also indicates the number of frames pending trans- T, then INJTR-T is incremented. Similarly, when
FIFO_T~OUT is called by the main program, to
mission. Each time a frame is sent, SEND~ATA is
decremented by one. Thus when SEND~ATA is, 'load the SIU~MITJUFFER, the byte in the array
greater than 0, the main program falls down into the
14-24
r-------~-----------------------I
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296166-15
intJ RUPITM·44
pointed to by OUT~~T is read, then OUT_ stations and receives responses from them. The primary
PT~T is incremented; Since IN_PT~T and station controls link access, link level error recovery,
OVTJT~T are always incremented, they must be and the flow of information. Secondaries can only
able to roll over when they hit the top of the '256 byte transmit when polled by the primary.
address space. This is done automatically by having
both INJT~T and OUTJT~T declared as Most primary stations are either micro/minicomputers,
bytes. Each character inserted into the transmit FIFO or front end processors to a mainframe computer. The
is tested to see if it's a LF. If it is a LF, the variable example primary station in this design is standalone. It
SEND~ATA is incremented, which lets the main is possible for the 8044 to be used as an intelligent front
program know that it is time to send an I frame. Simi- end processor for a microprocessor, implementing the
larly each character removed from the FIFO is tested. primary station functions. This latter type of design
SEND_DATA is decremented for every LF character would extensively off-load link control functions for the
removed from the FIFO. microprocessor. The code listed in this paper can be
used as the basis for this primary station design. Addi-
INJT~T and OUT_PT~T are also used to in- tional software is required to interface to the micro-
dicate how many bytes are in the FIFO, and whether it processor. A hardware design example for interfacing
is full or empty. When a character is placed into the the 8044 to a microprocessor can be found in the appli-
FIFO and INJT~T is incremented, the FIFO is cations section of this handbook.
full if INJ~T equals OUTJT~T. When a
character is read from the FIFO and OUTJT~T The primary station must know the addresses of all the
is incremented, the FIFO is empty if OUT_PT~T stations which will be on the network. The software for
equals INJT~T. If the FIFO is neither full nor this primary needs to know this before it is compiled,
empty, then it is in use. A byte called BUFFE~ however a more flexible system would download these
STATUS_T is used to indicate one ofthese three con- parameters. '
ditions. The application module uses the buffer status
information to control the flow of data into and out of From the listing of the software it can be seen that the
the FIFO. When the transmit FIFO is empty, the main variable NUMBE~OF,,-STATIONS is a literal dec-
program must stop loading bytes into the SIU_ laration, which is 2 in this design example. There were
XMITJUFFER. Just before the FIFO is full, the three stations tested on this data link, two secondaries
async input must be shut off using CTS. Also, if the and one primary. Following the NUMBE~OF_
FIFO is full and SEND~ATA = 0, then SEND_ STATIONS declaration is a table, loaded into the ob-
DATA must be incremented to automatically send the ject code file at compile time, which lists the addresses
data without an LF. of each secondary station on the network.
RECEIVE FIFO REMOTE STATION DATABASE
The receive FIFO operates in a fashion similar to the The primary station keeps a record of each secondary
transmit FIFO. Data is inserted into the receive FIFO station on the network. This is called the Remote Sta-
from the SIUJECV procedure. The SIU_RECV tion Database (RSD). The RSD in this software is an
procedure is called by the SIUJNT procedure when a array of structures, which can be found in the listing
valid I frame is received. The SIU_RECV procedure and also in Figure 16. Each RSD stores the necessary
merely polls the receive FIFO status to see if it's full information about that secondary station.
before transferring each byte from the SIUJECV_
BUFFER into the receive FIFO. If the receive FIFO is To add additional secondary stations to the network,
full, the SIU_RECV procedure remains polling the one simply adjusts the NUMBE~OF_STATIONS
FIFO status until it can insert the rest of the data. In declaration, and adds the additional addresses to th~
the meantime, the SIU AUTO mode is responding to SECONDARY~DDRESSES table. The number of
all polls from the primary with a RNR supervisory RSDs is automatically allocated at compile time, and
frame. The USART~MIT_INT interrupt proce- the primary automatically polls each station whose ad-
dure removes data from the receive FIFO and trans- dress is in the SECONDARY~DDRESSES table.
mits it to the terminal. The USART transmit interrupt
remains enabled while the receive FIFO has data in it. Memory for the RSDs reSides in external RAM. Based
When the receive FIFO becomes empty, the USART on memory requirements for each RSD, the maximum
transmit interrupt is disabled. number of stations can be easily buffered in external
RAM. (254 secondary stations is the maximum number
SDLC will address on the data link; i.e. 8-bit address,
2.5 Primary Station FF H is the broadcast address, and 0 is the null ad-
dress. Each RSD uses 70 bytes of RAM. 70 x 254 =
The primary station is responsible for controlling the 17,780.)
data link.' It issues commands to the secondary
14-26
RUPITM·44
The station state, in the RSD structure, maintains the PRIMARY STATION SOFTWARE
status of the secondary. If this byte indicates that the
secondary is in the DISCONNECT_S, then the pri- A block diagram of the primary station software is
mary tries to put the station in the I_T_S by sending shown in Figure 17. The primary station software con-
an SNRM. If the response is a UA then the station sists of a main program, one interrupt routine, and sev-
state changes into the I_T_S. Any other frame re- eral procedures. The POWER-ON procedure begins
ceived results in the station state remaining in the DIS- by initializing the SIU's DMA and enabling the receiv-
CONNECT_S. When the RSD indicates that the sta- er. Then each RSD is initialized. The DPLL and the
tion state is in the LT_S, the primary will send either
an I, RR, or RNR command, depending on the local
°
timers are set, and finally the TIMER interrupt is
enabled.
and remote butTer status. When the station state equals
GO_TO_DISC the primary will send a DISC com- The main program consists of an iterative do loop with-
mand. If the response is a UA frame, the station state in a do. forever loop. The iterative do loop polls each
will change to DISCONNECT_S, else the station secondary station once through the do loop. The vari-
state will remain in GO_TO_DISC. The station state able STATION_NUMBER is the counter for the iter-
is set to GO_TO_DISC when one of the following ative do statement which is also used as an index to the .
responses occur: array of RSD structures. The primary station issues one
I. A receive butTer overrun in the primary. command and receives one response from every second-
ary station each time through the loop. The first state-
2. An I frame is received and Nr(P) =P Ns(S). ment in the loop loads the secondary station address,
3. An I frame or a Supervisory frame is received and indexed by STATION_NUMBER into the array of
Ns(P) + 1 =P Nr(S) and Ns(P) =P Nr(S). the RSD structures. Now when the primary sends a
4. A FRMR response is received. command, it will have the secondary's address in the
address field of the frame. The automatic address rec-
5. An RD response is received. ognition feature is used by the primary to recognize the
6. An unknown response is received. response from the secondary.
The send count (Ns) and receive count (Nr) are also Next, the main program determines the secondary sta-
maintained in the RSD. Each time an I frame is sent by tion's state. Based on this state, the primary knows
the primary and acknowledged by the secondary, Ns is what command to send. If the station is in the DIS-
incremented. Nr is incremented each time a valid I CONNECT_S, the primary calls the SNRM_P pro-
frame is received. BUFFER-STATUS indicates the cedure to try and put the secondary in the LT_S. If
status of the secondary station's butTer. If an RR re- the station state is in the GO_TO_DISC state, the
sponse is received, BUFFER-STATUS is set to DISCJ is called to try and put the secondary in the
BUFFER-READY. If a RNR response is received, L.-D_S. If the secondary is in neither one of the
BUFFER-STATUS is set to BUFFER-NOT_ above two states, then it is in the I_T_S. When the
READY. secondary is in the 1_T_S, the primary could send
one of three commands: I, RR, or RNR. If the RSD's
butTer has data in it, indicated by INFO_LENGTH
BUFFERING being greater than zero, and the secondary's BUFF-
The butTering for the primary station is as follows: ER-STATUS equals BUFFER-READY, then an I
within each RSD is a 64 byte array butTer which is frame will be sent. Else if RPB = 0, an RR supervisory
initially empty. When the primary receives an I frame, frame will be sent. If neither one of these cases is true..
it looks for a match between the first byte of the I frame then an RNR will be sent. The last statement in the
and the addresses of the secondaries on the network. If main program checks the RPB bit. If set to one, the
a match exists, the primary places the data in the RSD BUFFER-TRANSFER procedure is called, which
butTer of the destination station. The INFO_ transfers the data from the SIU receive butTer to the
LENGTH in the RSD indicates how many bytes are in appropriate RSD butTer.
the butTer. If INFOJENGTH equals 0, then the
butTer is empty. The primary can butTer only one I
frame per station. If a second I frame is received while
the addressed secondary's RSD butTer is full, the pri-
mary cannot receive any more I frames. At this point
the primary continues to poll the secondaries using
RNR supervisory frame. .
14-27
intJ RUPITM_44
maximum frame length time comes from the fact the
RSD STATION-ADDRESS 8044 does not generate an interrupt from a received
STATION-STATE frame until it has been completely received, and the
NS CRC is verified as correct. This means that the time-
out is bit rate dependent.
NR
BUFFER-STATUS
INFO-LENGTH Ns AND Nr CHECK PROCEDURES
DATA (0) Each time an I frame or supervisory frame is received,
the Nr field in the control byte must be checked. Since
this data link only allows one outstanding frame, a val-
id Nr would satisfy either one of two equations;
Ns(P) + I = Nr(S) the I frame previously sent by the
primary is acknowledged, Ns(P) = Nr(S) the I frame
previously sent is not acknowledged. If either one of
these two cases is true, the CHECLNR procedure
returns a parameter of TRUE; otherwise a FALSE pa-
rameter is returned. If an acknowledgement is received,
DATA (63)
the Ns byte in the RSD structure,is incremented, and
the Information buffer may be cleared. Otherwise the
Figure 16. Remote Station Database Structure information buffer remains full.
RECEIVE TIME OUT When an I frame is received, the Ns field has to be
checked also. If Nr(p) = Ns(S), then the procedure
Each, time a frame is transmitted, the primary sets a returns TRUE, otherwise a FALSE is returned.
receive time out timer; Timer O. If a response is not
received within a certain time, the primary returns to
the main program and continues polling the rest of the RECEIVE PROCEDURE
stations. The minimum length of time the primary The receive procedure is called when a supervisory or
should wait for a response can be calculated as the sum information frame is sent, and a response is received
of the following parameters. before the time-out period. The RECEIVE procedure
1. Propagation time to the secondary station can be broken down into three parts. the first, part is
2. Clear-to-send at the secondary station's DCE entered if an I frame is received. When an I frame is
received, Ns, Nr and buffer overrun are checked. If
3. Appropriate time for secondary station processing there is a buffer overrun, or there is an error in either
4. Propagation time from the secondary station Ns or Nr, then the station state is set to GO_TO~
5. Maximum frame length time DISC. Otherwise Nr in the RSD is incremented, the
receive field length is saved, and the RPB bit is set. By
The clear-to-send time and the propagation time are incrementing the Nr field, the I frame just received is
negligible for a local network at low bit rates. However, acknowledged the next time the primary polls the sec-
the turnaround time and the maximum frame length ondary with an I frame or a supervisory frame.' Setting
time are significant factors. Using the 8044 secondaries RBP protects the received data, and also tells the main
in the AUTO mode minimizes turnaround time. The program that there is data to transfer to one ofthe RSD
buffers.
14-28
inter RUPITM·44
MAIN PROGRAM
BUFFER TRANSFER
296166-16
Figure 17. Block Diagram of Primary Station Software Structure
If a supervisory frame is received, the Nr field is state is set to GO_TO~ISC. However, if the frame
checked. If a FALSE is returned, then the station state received is a FRMR, Nr in the second data byte of the I
is set to GO_TO_DISC. If the supervisory frame re- field is checked to see if the secondary acknowledged an
ceived was an RNR, buffer status is set to not ready. If I frame received before it went into the FRMR state. If
the response is not an I frame, nor a supervisory frame, this is not done and the secondary acknowledged an I
then it must be an Unnumbered franie: frame which the primary did not recognize, the pri-
mary transmits the I frame when the secondary returns
The only Unnumbered frames the primary recognizes to the I_T_S. In this case, the secondary would re-
are UA, DM, and FRMR. In any event, the ,station ceive duplicate I frames.
14-29
inter RUPITM·44
APPENDIX A
8044 SOFTWARE FLOWCHARTS
POWER-ON-D PROCEDURE
USER-STATE = CLOSED-S
STATION-STATION = DISCONNECT-S
TBS = S.IU-XMIT-BUFFER STARTING ADDRESS
RBS = SIU-RECV-BUFFER STARTING ADDRESS
RBl = BUFFER LENGTH
. ENABLE SIU RECEIVER: RBE =1
XMIT-BUFFER-EMPTY =1
RE.TURN
296166-17
CLOSE PROCEDURE
AM=O
RETURN
OPEN PROCEDURE
USER STATE = OPEN_S
RETURN
296166-18
Figure 18. Secondary Station Driver Flow Chart
14-30
infef RUPITM-44
XMIT-UNNUMBERED PROCEDURE
296166-19
TRANSMIT PROCEDURE
STATUS = USER·STATE·ClOSE
STATUS =
LINK_DISCONNECTED
STATUS =
?VERFlOW
XMIT·BUFFER·EMPTY =0
TBl = XMIT·BUFFER·lENGTH
I·FRAME·lENGTH = XMIT.BUFFER.lENGTH
STATUS = DATA· TRANSMITTED
296166-20
Figure 19. Secondary Station Driver Flow Chart
14-31
intJ RUPITM~44
XMIT-FRMR PROCEDURE
FRMR·BUFFER (2) = REASON
STATION·STATE = FRMR·S·
SEND FRMR
FRAME
296166-21
Figure 20. Secondary Station Driver Flow Chart
14-32
intJ RUPITM·44
IN·DISCONNECT·STATE PROCEDURE
296166-22
SNRM·RESPONSE PROCEDURE
296166-23
Figure 21. Secondary Station Driver Flow Chart
14·33
inter RUPITM-44
IN·FRMR·STATE PROCEDURE
296166-24
Figure 22. Secondary Station Driver Flow Chart
14·34
inter RUPITM·44
COMMANO DECODE PROCEDURE
296166-25
Figure 23. Secondary Station Driver Flow Chart
14-35
. SIII-INT PROCEDURE l
6c
I ~ y
y
iiJ
,.
N
y
~ I CALL COIIMAND-DECODE 11--------,
Ie
n XMIT·BUFFER·EMPTY
0 =1
:=I
a. CALL XMIT·UNNUMBERED 1 1
DI (REQ.DISC) • :II
.... .c!. N
c:
."
Sfl
t
<»
-
DI
is"
:=I
y
CALL XIIIT-FRMR
~
..•
...C
...<"
CD
•~
0
:r
DI CALL COMMAND DECODE
::I.
296166-26
RUPITM·44
MAIN PROGRAM
LOAD DESTINATION
ADDRESS IN FIRST
BYTE OF SIU-XMIT
BUFFER
LOAD INFORMATION
INTO SIU XMIT-BUFFER
SIU BUFFER LENGTH
OR FIFO-T EMPTY
OUTPUT MESSAGE
TO TERMINAL
'UNABLE TO GET ON LINE'
296166-27
Figure 25. Application Module Flow Chart
14-37
inter RUPITM·44
USART·RECV·INT INTERRUPT PROCEDURE
296166-28
Figure 26. Application Module Flow Chart
14·38
intJ RUPITM-44
MENU PROCEDURE
OUTPUT MENU
TO TERMINAL
CALL OUTPUT·MESSAGE
'ENTER THE STATION ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR
LOAD ADDRESS
INTO STAD
CALL OUTPUT·MESSAGE
'THE. NEW STATION ADDRESS:_'
CALL OUTPUT·MESSAGE
'ENTER THE DESTINATION ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR
LOAD ADDRESS
INTO DESTINATION·ADDRESS
CALL OUT·MESSAGE
'THE NEW DESTINATION ADDRESS IS:_'
RETURN
296166-29
Figure 27. Application Module Flow Chart
14-39
RUPITM·44
ERROR PROCEDURE
RESET ERROR FLAGS ON USART
296166-30
Figure 28. Application Module Flow Chart
14-40
RUPITM-44
FIFO·T-OUT PROCEDURE
296166-31
Figure 29. Application Module Flow Chart
14·41
RUPITM·44
FIFo-T·IN PROCEDURE
RETURN
296166-32
Figure 30. Application Module Flow. Chart
14-42
RUPITM·44
SIU·RECV PROCEDURE
296166-33
Figure 31. Application Module Flow Chart
POWER ON
I INITIALIZE SIU REGISTERSJ
I
FOR EACH STATION
INITIALIZE RSD RECORDS
1. STATlON·ADDRESS
3. BUFFER·STATE == =
2•.STATIQN·STATE DISCONNECT
BUFFER·NOT·READY
4. INFO-LENGTH 0
I
I RETURN I 296166-34
Figure 32. Primary Station Flow Charts
14·43
inter RUPITM_44
PRIMARY STATION MAIN PROGRAM
ADDRESS NEXT STATION
SETSTAD
Y
CALL SEND-SNRM
Y
CALL SEND-DISC
CALL XMIT I T S Y
(T-I-FRAME) - I---------.,.-C
CALL XMIT-I-T-S Y
(T-RR)
v
CALL BUFFER-TRANSFER
296166-35
Figure 33. Primary Station Flow Charts
14-44
RUPITM·44
SEND·SNRM PROCEDURE
296166-36
SEND-DISC PROCEDURE
STATION·STATE =
DISCONNECT·S
BUFFER·STATUS =
BUFFER-NOT·READY
296166-37
Figure 34. Primary Station Flow Charts
14·45
inter RUPITM·44
XMIT·ToS PROCEDURE
BUILD CONTROL
FIELD USING EITHER
I, RR, RNR
AND NR AND/OR NS
y
CALL RECEIVE
296166-38
XMIT PROCEDURE
296166-39
Figure 34. Prlr:nary Station Flow Charts
14-46
RUPITM·44
BUFFER·TRANSFER PROCEDURE
MOYE DATA FROM
SIU·RECY·BUFFER
TO RSD BUFFER
296166-40
Figure 36. Primary Station Flow Charts
14·47
intJ RUPITM_44
CHECK-NRPROCEDURE
RETURN
TRUE
296166-41
CHECK-NsPROCEDURE
296166':'42
Figure 37. Primary Station Flow Charts
14·48
l
REMOTE BUFFER-sTATUS = BUFFER-READY
.,..
ac
a;
Co»
PI
~
:u
~j c:
'U
J..
<0
se
III
g
RECEIVE-FIELD-LENGTH
• RFL -\ .
':j
~
~
i:
i9
.,
~.
III STATION-STATE
= Go.TO-OISC
296166-43
RUPITM·44
APPENDIX B
LISTINGS OF SOFTWARE MODULES
PL/....51 COf'PILER 20: 24: 47 09/20/83 PAGE
IBIB-U PL/II-51 111.0
CIlI1PILEA INIIOKED BV, ,Fa, PL"51 ,Fa, APNDTE. SRC
.TITLE ('R"'I-44 Sec and.,., St.UDn DT"iY.,,')
10£1\10
tREOISTERBANKUI
MINtMOD:
___ 1ST DOl
/. To ••V~ p.p.,.
the RUP] ,. •• ht.,. • • r. nat U.t.d, but tbis is the .t.t.... n'
u ••• to inc Iud. the.: .INCLUDE' (:F2: RE044. DCL) . /
5 DECLARE LIT LITERALLV 'LITERALLV',
TRUI! LIT 'OFFH'.
FALSE LIT 'OOH',
FDREVER LIT 'WHILE 1"
6 DECLARE BNR" LIT .'S3H',
UA LIT '73H',
DISC LIT '43H',
~ LIT '1FH'.
FR"" LIT '97H',
REG....DISC LIT '11314."
UP LIT '33H',
TEST LIT '0E3H' ,
OPENJI LIT 'OOH',
CLDSEDJI LIT '01H',
LIT
LIT
LIT
'OIH', , . FRNE RE..IECT STATE
'02H'.
*' . *',
'OOH', , . LOCnCALLY DISCa...e:CTED STATE*'
/. ItrFORPfATION TRANSFER STATE
USERJlTATEj:LOSED LIT 'DOH',
LINK....DISCDNNECTED LIT 'OtH',
OVERFLOW LIT 'OaH',
DATA_TltANSltJ"r;T&D LIT '03H',
/. '.,.••• h1'. p...... to XMIT...FRftR ./
UNIIBIIIGNED_C LIT 'OOH',
ND_I../'IELD.J\Ll.DWED LIT 'OIH',
BUFF....DIlERRUN LIT '021'1',
SEB...ERR LIT '03M',
296166-44
14-50
RUPITM-44
PL./tt-:U cOtP ILER 20: 24: 47 09/20/93 PAOE i2
USERJlTATE BYTE AUXILIARY.
STATJDNJ1TATE BVTE AUXILIARY.
IjAAMEJ.ENQTH IYTE AUXILIARY.
IUFFEAJ.ENOTH LIT 160',
SIU_XHITJlUFFER (IUFFEAJ.ENOTH) IYTE PUBLIC
SIUJlECYJlUFFEA (IUFFERJ.ENQTH) IYTE PUILIC.
FR""JtUFFER(3) BYTE.
/. Ft. • • • /
XHI TJlUFFER.POPTY 81T PUILIC.
7 2 SIUJlECY: PROCEDURE (LENOTH) EXTERNAL,
a 2 DECLARE LENGTH IYTE.
9 I END SIUJlECY,
10 2 OPEN: PROCEDURE PUBLIC USING 2.
II 2 UBERJlTATE-OPENJh
12 I END [PEN,
.3 2 CLOSE: PROCEDURE PUBLIC USING 2.
14 2 ,....·0.
"
16
2
I
UBERJlTATE-CLDSEDJI'
END CLOSE.
.7 2 PDWER_ONJ): PROCEDURE PUBLIC USINO 0,
la 2 USER.:,.sTATE-CL.OSED_S,
.9 2 BTItTIDN,JITItTE-DISCONNECT _BI
20 2 TI&-. SIUJlHITJlUFFEA(O),
21 2 AI&-. SIUJlECYJlUFFER(Oh
22 2 RIL-IUFFERJ.ENQTH,
23 2 ABE-I, /. En.bl. thl 8IU'. ,..edv.,. .,
24 2 X"ITJlUFFERJUPTY-l.
2' END PDWEA_ONJ),
26 2 TAANSHIT: PADCEDURE CXHITJlUFl'EAJ.ENOTH) IYTE PUBLIC USINII 0,
/. Uu" .us' chd XHITJlUFFER..,.E. . TY fl •• It •• o,.. C.Uinl this p,-oc.dur. *'
27 2 DECLARE XHITJlUFFEAJ.ENIITH IYTE,
I IYTE AUXILIARY.
STATUS IYTE AUXILIARY,
28 2 IF UBERJlTATE-CLDBED_S
THEN STATUs-uBER_BTATE_CLDBED'
30 2 ELSE IF STATrONJlTATE-DISCONtECT_S
THEN STATUs-LINKJ)ISCDNNECTED,
32 2 ELSE IF XHIT JlUFFERJ.ENIITIOIUFFERJ.ENIITH
THEN STATUS_FLOW,
34 3 ELSE DO.
296166-45
14-51
inter RUPITM·44
20: 24: 47 09/20/83 PAGE 3
35 3
36 3
37 3
38 3 TIF-S.
39 3 STATUllaMTA_TRANMITTEDI
40 3 END.
41 2 RETURN STATUS.
42 I 'END TR_IT.
43 2 X"IT_IN«IIIIIERED: PROCEDURE (CDNTROLJlVTEI •
44 2, DECLARE CDNTRDLJlVTE . BVTE.
45 2 TCB-CDNTRDLJlVTE.
46' 2 TIF-l.
47 2 RTs-1i
4B 3 DO WHILE MIT 81.
49 3 END.
iIO 2 81-0. '
51 END Xf1IT_UIIN.ItIEREDI
52 2 ~"~E.~: PROCE~E •
53 2 STATIONJTATE-I_T_BI
54 2 NsNR-O,
55 2 IF (RCI AND SOH) 0 0 , . R•• pond i' polhd . ,
THEN DO,
57 3 TlL-O,
H 3 CALL X"lT_UNNUI1IIEREDCUA),
59 3' ENDI
60 2 IF X"ITJI\FF'ER~TV-o
THEN DO,
,. If .n I frM • .,.. 1."
th.n r •• tor. U: *' p.ndj~. '".ndt •• tan
62 3 rlL.-IJRNEJ..ENQTH,
63 3 TlF-1,
64 3 ENDI
65 2
66
67 2 X"IT...FR~: PROCEDURE (REASONI I
68 2 DECLARE REASON IYTE,
69 2 TC • .p'R""h
70 2 TBg., FR~JlUFFER(OIo
71 2 T8L-3.
72 :I FR~JlUFFER (Ol-RCBI
/ ....., nnu •• In NaIR . /
73 :I FRI'tR __ t.PFERU)-CSHLtcNBNR MD 0EH),41 OR He (NSNR AND OEOH)"4»,
74
75
3
3
DO CASE REA. . .,
FR"J:UFFER(2)-oIH, /. UNASBIONED_C *'
296166-46
14-52
inter RUPITM_44
PL/f1-eU CDI1P J: LER 20: 24: 47 09/20/83 PAQE
*,- *'
76 3 FRI1RJUFFER C:2 J -02HI
77
78
3
3
FRtIR ..... UFFER (2) -o4H,
FRIIRJlUFFER cal-OSH.
'* BES~RR
1* ND_IJIELD.j&LLDWED
I-
lUFF OVERRUN
*1
79 3 END.
80 a STATIONJJTATE-FRf1RJJ'
81 a IF CRCI AND 10H. <>0
THEN DO.
B3 3 TIF-I,
84 3 RrS-11
8S 4 DO WHILE NOT 81.
B6
87 •
3
END.
SI-O,
as 3 END.
B9 I
90 a INJUSCONNECT_BTATE: PROCEDURE J '* C.U.d '''D. SIU_INT procedure . /
91 a IF CCU8ER_BTATE-OPEN_BJ AND «RCB AND OEFH)-SNRMJ)
THEN CALL SNR"-"EBPONBE,
93 a ELSE IF (RCB AND 10M) 00 0
TtEN DD.
9S 3 TIL-a,
96 3 CALL. XPtIT_UNt«JMBERED(DttJI
97 3 ENO.
98 I END INJllSCClNNECT_STATE.
a
99
*,
INjRKR_STATE: PROCEDURE I /* e.l hd b, SIU_INT .hen ,. , ...... " •• bun ,..cdv.d
..hen in th FR. . . t.t.
100 a IF CRCB AND OEFH)-SNAtt
TI£N DO,
loa 3
103
104
3
3 END.
CALL BNR"....RESPONSEI
Ta&-. BIU~"ITJlUFFER(OJJ 1* R•• ta .... ''riln •• U bu"." _,_"" .dd" ••• *'
lOS a ELSE IF (RCB AND OEFHJ-DISC
nEN DOl
107 3
109
109
3
3
STATIDNJJTATE-DISCDNNECT_SJ
TlS-. SIU~"ITJUFFERCO)1
IF CRCa AND IOH)<> 0
'* R•• tar. t".n •• U: bu,h" .t."t .dd" . . . .,
TtEN DOl
III 4 TaL-OI
lIa 4 CALL X"IT_UNNUI"I8EREDCUA)J
113 4 END.
114 3 END.
liS 3 ELSE DOl I . R.ceive cont:rol but. is sa •• thing oth." than D]SC a" SNR" . ,
116 3 IF CRCa AND 10tn 0 0
llEN DOl
118 4 TIF-.,
119 4 RT8-S,
296166-47
14-53
intJ RUPITM·44
PL/I'I-51 CDtPILER :20: 24: 47 0./20/83 PAGE
••
I~O DO WHILE NOT BI,
I~I END,
I~ 4 END,
1~3 3 END,
1~4 END INJR"'JlTATE,
I~' ~ CO.....NDJlECODE: PROCEDURE ,
126 ~ IF (RCB AND OEFHI-sNR"
THEN CALL SNR"JlEBPONBE,
1:111 ~ ELSE IF CRCI AND OEFH)-DlSC
THEN DO,
130 -3 STATIOtCSTATE-DIBCONNECT_9,
131 3 IF CRca AND IOH)OO
THEN DO. '
133 4 TBL-o,
134 4 CALL X"IT _UNNUIIIIERED (UA I,
131 4 END,
136 3 END,
137 ~ ELSE IF CRCB AND OEFH)-TEST
THEN 001
i.
139
141
3
4
IF CRCB AND lOH)>O
THEN 001
IF
/. FOR
caov-iou
An,.nd if ,alhd ./
BOY-I. BEND THe: TEST RESPONSE WITHOUT AN I FJELD *'
THEN DO,
••
143 TBL-eJ,
144 CALL XI'IIT_UNNU...EREDCTEST OR 1OH),
'END,
141
146
147
I
I
I
ELSE DO, '*
I f no BOY.
TIL....FL'
und received 1 flteld ... ck to pri ••,., *'
14B
•• TBS-R.S,
14. CALL. K"IT _UNNUPIIEREDCTEBT DR 10M) I
*'
••
ISO nB-.8IU_X"ITJlUFFERCOh /. R•• tD,.. TBS
1.1
I'~ 4
'* I'
END,
an I fir •••
IF Kf1IT JlUFFER..EftWITV-O
III., p.ndin,. ..t it II, _,.in .,
THEN DO,
1.4
I •• •
I-
TBL-IjRNE.-LENOTHI
TBF-l, .
1.6
117 •4 END,
I.B 3
II. 3
160 ~- ELSE IF CRCB AND OIH) • 0 /. Kich' out o. the AUTO .ode beceu ••
an 1 'ra...... received whUe RPB • 1 ./
llEN DOl
I~ 3 Apt. II
163 3 IF X"IT JlUFFER..EIPTV • I
16. 3
THEN TIL. O.
TBF • I. '* Send an AUTO .ad. 1" • • pon •• */
296166-48
14-54
RUPITM-44
PL., .... ,' CDI'tPILER 20: 24: 47 09/20/83 PAE 6
,....
167
3
3 END,
RTS - 11
168 2 ELSE CALL X"ITJRf'lRC!JNASBJONED_C), , . Rec.ived an undwf1n.d Dr nat tllpl ••• nte. co_and *'
169 END CDfl'tANDJ)ECODE.
170 2 StU_tNT: PROCEDURE INTERRUPT 4.
171 a DECLARE BYTE AUXILIARY,
172
173
2
a
SI-o.
IF STATJONJITATE<> I_T.-s /. Must b. In NON-AUTD,lIoda
THEN DO,
*'
175 3 IF R8£-0 '*
Received • •" ••• ? Qiv. " •• pon •• _,
,,,
THEN DO,
177 DO CASE STATIDNJlTATE.
I.
178 CALL IN...DISCONNECT ....sTATE.
179
180
181
,
4
END.
CALL INJRIIIJlTATE.
R8E-l,
4 END.
183 3 RETURN,
184 3 END.
/ . %f tt.. P"ol" ....... cb . . 'hie ,oint. STATIONJITATE-I_T...S
which •••na th BtU .Uhe........ 01' still h in the AUTO I1DDE *'
18' 2 IF A....o
THEN DO.
187 3 IF (RCB AND OEFH)-UIBC
THEN CALL COfI'IANDJ)ECODE.
189 3 ELSE IF USER....sTATE-CLOSED_S
Tt-EN DO,
191 4 T8L-D •
. 192 4 CALL XMIT_UM«JMIEREDCREGJ)ISC),
193 4 END.
194 3 ELSE IF BEB-I
TIEN CALL X"IT JRIIA(BES..ERRl.
196 3 ELSE IF BOY-I
THEN DO.,. DON1T SEND FA . . IF A TEST WAS RECEIYED4t1
198 4 IF CRCB AND OEFH)-TEST
THEN CALL C~...DECaDE.
aoo 4 a.BE CALL XMITJRrtR (BUFF_OVERRUN) I
201 4 END.
202 3 ELSE CALL CDf'l'fANDJ)ECQOE,
203 3 RIE-I,
204 3 END;
20'
206
3
3
ELSE DO, '* PIJ8T STILL. IE IN AUTO t100E . ,
IF TBF-o
THEN X.. ITJlUFFERj:MPTV-I, , . TRANSI'IITTEO It FRNE . ,
208 3 IF RBE-o
THEN DC,
296166-49
PL/tt-DI CCl'lPILER 20: 24: 47 09/.20/83 PAQE 7
.210 4 RIP-I, I. RNA STATE . ,
211 4 RIE-I, , . RE-ENABLE RECE1VEA . ,
212 4 CALL 81UJlECVCRFL.J
213 4 RIP-O, I. RR STATE . ,
214 4 END.
215 3 END.
216 I
217
_NlNOS:
4 IS TIE HIGHEST USED INTERRUPT
lIIIDULE IN'CRItATlON: eSTATlC+ClllERLAYABLEl
CaDE SIZE - O.i28FH 6550
CCNBTANT BIZE - OOOOH OD
DIRECT YARIABLE SIZE 3FH+02H 63D+ aD
INDIRECT YARIABLE SIZE 3CH+OOH 6OD+ 00
In aUE OIH+OOH tD+ 00
BIT-ADORESSABLE SIZE OOH+OOH OD+ 00
AUXILIARY YARIABLE 81ZE .OOODH 6D
MK Utu.. STACK 81 ZE .OOI7H .i23D
REOISTER-BANKeSl USED: 01 2
460 LINES READ
o PRDaR,," ERRORes)
END .IF PL'"-51 CCllPILATlON
296166-50
14-55
intJ RUPITM-44
18,~, 53 09/19/83 PACIE
181S-11 PL/....51 Yl.0
CDf'PlLEA INVOKED BY: : '2: pl_" : '2,: unat. .• T'C'
STITLE C~Applic.t:lon Module: Alunc/SDLe P"otoeat convert.,.' ~
t ... ltul
S"".,ilh,.'.n. CO)
u •• ,. ••ocl: do.
tNDLlBT
5 DECLARE LIT LITERALLY 'LITERALLY',
TRUE LIT 'OFFH'.
F ....SE LIT 'DOH',
FIlREVER LIT 'WHILE
,'18H',
1':
Eac LIT
LF LIT 'OAH',
.8
CR
IEL
LIT
LIT
LIT
'DOH',
'OSH',
'07H',
EN'TY LIT 'DOH',
INUBE LIT "OtH'.
PULL LIT '02.4'.
UBER_STATE_CLOBEO LIT '00II',
LINKJ)ISCONECTED LIT 'OSH',
IlllERFLOW LIT '02.4'.
DATA_TR_ITTED LIT '03H',
/ . BUFFERS . /
.YFFERJ.ENOTH LIT '60'.
8IU-,,"ITJlYFFERCBYFFERJ.ENOTH. .YTE. EXTERNAL
BIU.."RECYJlUFFERCBUFFERJ.ENOTH. BYTE EXTERNAL.
FIFD_Tea",. BYTE AUXll.IARY.
IN-'TR_T BYTE AUXILIARY,
OUT-'TR_T .YTE AUXILIARY,
IUFFERJlTATUB_T BYTE AUXILIARY,
FIFD.."RCa",. BYTE MJJClLIMY,
IN-'TR.."R BYTE AUXILIARV,
OUT-'TR.."R .YTE AUXILIARY,
.UFFERJlT...TU8.."R BYTE AUXILIARY.
LENGTH IYTE AUXILIARY,
CHAR IYTE AUXILIARY.
I BYTE AUXILIARY.
UBMT_CHD BYTE AUXILIARY.
DE8T1N1\TlDN~DREBa BYTE AUXILIARY,
IEND......T.. BYTE "UXlLIARY,
RESULT .YTE AUXILIARY,
PRJEBSAOE_INDEX BYTE AUXILIARY.
ERRJEBBAOE-'TR WORD MJXILJARV.
PMUTVe*) BYTE CCIGTANT(LF.CR. 'Pal'itlJ E,.,.o," netechd'.LF.CR,OOtU.
FRNEC_) BYTE CDNSTNfTCLF. CR. 'F"•• :ln, E""o1' D.tlct.d'. LF. CA. OOln.
296166-51
14-56
inter RUPITM·44
PL/tt-!U COI1PJLER Application t1odul.: ",..,nc/SDLt Protocol canve,.,!". IS: '0:'3 09/19/83 PAQE 2
OYERJtUNC.) BYTE CONSTANTCLF, CR. 'Ov.r ... un Error Dehc'hd I, LF. CR. 0)'
LINKe_» BYTE CONBTANTCLF.CR. 'Unable to Oet Onlin.'.LF.CR.OOH),
DE8Tj.DDRC*) BYTE CONSTANTCCR. LF. LF.·
'Ent.,-· the de.tination addre •• : _', as. 88. 0).
DJliDDRj.lCKC.) BYTE CONBTANT<CR. LF. LF.
'Th. n •• d •• tination addr ••• ts ',0).
BTATj.DDRC.) BYTE CDNSTANTCCR.LF.LF.
'Ent." the .t.tion .dd,. ••• : _', DS. BS, 0)'
S....ADDR..ACKC.) BYTE CONSTANTCCR. LF. LF.
'The n • .., ,t.tlon addre •• i . ' , 0).
ADDR..ACKJIN(.) BYTE CONSTANTC 'H',CR,LF,LF.OJ,
SloteoNe.) aVTE CDNSTANTCCR~ LF. LF.
'(\f) RUPJ-44 S.cond.,. ... Btatian', CR. LF.
, \/', CR. LF. LF.
, 1 - S.t the Station Add"e •• •• LF. CR.
'2 - S.t the D•• UnatiDn Add,. ••• ·, CR, LF,
'3 - GD OnUn.', CR, LF,
'4 - OD Offlin.·,CR,LF,
'S - R.tuT'n to t.,.,..in.l _Dd.', CA, LF, LF,
• Ent.,.. option: _'I BS, 0),
FINe.) BVTE CONSTANTtCR, LF, LF. 0),
HEX_TABLE(17) BYTE CONSTANT( '01234'67S9ABCDEF', BEL) •
. MENU_C.HAR(6) BVTE CONSTANTC'I234",BEL),
, . Fla •• and BU • •,
IMI TJlUFFER..EMPTY BIT EXTERNAL. I. S.m.phD,... ¥a,.. RUPl: SIOU TT'.n.lllit BuffeT' *1
STOP JIlT BIT AT(141) REO, 1* T.,...dn.I p.r ••• t." • •
1
ECHO BIT ATCOB4H) REO.
WAIT SIT. ,. n •• Dut fila. *1
ERRDRJ~Ao BIT. I . Erl'Dr III •••••• Fl •• *1
USART_STATUS BVTE ATCOB01H. AUXlLlARV,
U8ARTJlATA SYTE ATCOBOOH) AUXILIARV.
TIMER_CONTROL BYTE ATCI003H) AUXILIARY.
TlIER_O BYTE ATCtOOOH) AUXILIARY.
TIMER_I BYTE ATC1OOIH) AUXILIARY.
TlIlER..,.2 BYTE AT ClOOZU AUXILIARY.
296166-52
14-57
intJ RUPITM·44
PL/.... 51 CCJI'IIILER 18: 50: 53 09/19/83 PAGE 3
6 2 PDWERJlNJI: PROCEDURE EXTERNAL.
7 1 END PUWERJlNJI.
B 2 CLOSE: PROCEDURE EXTERNAL USINO ~2J
9 1 END CLOSE,
10 2 OPEN: PROCEDURE EXTERNAL USINO 2.
11 1 END OPEN,
12 2 TRANIII1IT: PROCEDURE CX"ITJUFFER~NOTH) BYTE EXTERNAL,
13 2 OECLARE X"IT JUFFER...LENOTH BYTE.
14 1 END TRANSMIT,
15 2 TlttER_O_INT: PROCEDURE INTERRUPT I UBINCI I,
16 2 WAIT-O,
17 1 E~ T:utER..q_lNT,
lB 2 PDWEA_I»I: PROCEDURE USING 0,
19 2 OECLNlE TEIIP BYTE AUXlLlARV,
20
21
22
2
2
2
"D-,4H1
TtUJD-21HI
TH1-OFFH,
'*
, . UU", DPLL. NRZI. PFa. TItER I • • 62. D Kbp. *1
Ti •• ,. 0 16 Ut, TI •• " 1 auto ,..10.d *'
23 2 TCON-4Oft,
24
25
2
2
TIPER-.CDNTRDL-37H,
TltER_o-o4H.
'* InUSaUI. USART~ • • ., . . . . clod, 8254 *'
~~=:=~.77H1
26
27
2
2 '* IniU.UI. TIC. RIC *'
,. Defl.nUion '0," di, ... nch Ued to PI.O to PI. it
I" Ra'. 3 2
300 on on
1200
2400
on
on
on
0" 0"on
4800
9600
on
0" 0"
on 0"on
19200 0" on 0"
stop Ut 4
1 on
2 0"
,.,.tt . 6
0"0" on
on
on
0"
0"
even 0"
0"
D.
0"
296166-53
14-58
RUPITM·44
PL/1I-51 CIIIPILEA "'pplie.tion P1oduh: "' ... nc/SDLe PTotocal conv."hT 18: '0: 53 09119/83 PAGE 4
Echo 7
on
0"
on
0" .,
28 TEI'P-Pl AND 07H. /. ft •• , the dip ... itch to ... tn.in. the bit r.h ./
a1'
31
""
3
IF TEI'I'>5
Tt£N TEI1P-o.
DO CASE TEI'IP I
, . 300 . /
32 4 00.
33 4 TlttER_S-a3H.
34 4 TIttER S-2OH,"
35 4 END. -
a., 4
37 4 TlI'IER_1-20H1
38 4 TIPIER_l-o'H.
39 4 END.
40
41
4
4
'* 2400./ DO.
TIPIER_I-bOH.
4" 4 lUtER_I-OaHI
43 4 END.
44 4 /. 4800./ DO.
45 4 TII'IER_l-:1OH.
46 4 TlI'1ER_l-olH.
47 4 END.
48 4 /. 9600./ DO.
...
49"
51
4
4
4 END.
TI"ER_l-o'HI
TII'IER_l-o.
52
53
4
4
/. 19200 *' DO.
TlttER_1-33H1
54 4 TIPIER_I-O.
55 4 END.
56 END.
57
118
USMT-.8TATUS-O,
USMT_BTATUB-O,
./. So,t.,.,.. pOIIIII.,.-on r . . . t fot' B25.1'" *'
59 USNIT_STATUS-O,
60 UIIMT_STATUB-4OH.
61 TEJIP~HI /. D.tel".ln. the per it, end. of stop bU • • /
62 TE".-TEIF OR (P, AND 3OHl,
63 IF STOP..In-I
THEN ~.TaP OR oea.."
65 ELSE TEtP-TEPIP OR 40H.
66
67
UBART..BTATUS-'EPIP, '*
USART "0111. Wa'r"cI *'
USMTJlTATUS. USART_CI'ID-27H'/ttUSMT Co . . . nd Ward RlB. RIE. DTA. l.EN-le,
68 STIID_FH.
296166-54
14-59
inter RUPITM-44
Applie.Uan t1aduh: ,.."nc/SOLC PT'otocol con..,.,.t.,. 18: 110:'3 09/19/83 PAGE 5
69 2 SENDJ)ATA-<J, /* Inti.Un Fh.s ./
70 2 INJ'TR_T. OUTJlTR_T. tHYTR..". OUTJ'TR..A • O,'*lniti.Uu FIFO PTR •• '
71 2 BUFFER..8TATUS_', 8UFFER':'STATUS..R- ENt,y,
72 2 CAU.. PDWER_tw_DI
73 2
'*
/* UBM,'. RIR." ,. the h1Ih •• ' P1'iD"U" *' *'
80th •• ,.,.n.l intel'f'upts .,.. I.Yel ''''1 •• '' ••
74 2' /. En.U. USMT RaR.,. SI . • nd '1me" 0 inh~"up·h./
75 2 ERRDRj'LAO-O.
76 END POWER_ONJ
77 2 FIFD..R_IN: PROCEDURE (CHAA. USINO 1,
7a 2 DECLARE CHAR BYTE.
79 2 FIFO-"C INJ'TR..Jt )-CHAR.
80 2 INJTR..R·INJTRJ'+ll
al 2 IF 8UFFER_BTATUS_R-EKPTV
THEN DO.
a3 3 EAoO.
84 3
as
86
3
3
EXt-I,
EA-l,
'*
BUFFERJlTATUS..A-INUSE,
Enilbh USART'. TID int.,.,.upt *'
a7 3 END.
aa 2 ELSE IF CCIUFFER..BTATUSJl-INUSEI AND ClNJ'TRJI-OUTJ'TRJlI I
THEN BUFFER_BTATUSJloFULL.
90 END FIFOJl_IN.
91 2 FIFO-"_OUT: PROCEDURE BYTE USINO ••
92 2 DECLARE CHAR ... aYTE AUXILIARY,
93 2 CHARoFIFOJlCOUTJ'TRJlI.
94 '2 DUTJTR...R-OUTJTRJt+II
9S 2 IF' OUTJ'TRJI-INJ'TRJI
THEN DO,
97
98
3
3
EX1-oJ , . Shut off rwD :l.nt.,.,.upt
IUFFER_BTATUBJ'-Et1PTY'
*'
9' 3 END, L
100 2 ELSE iF C(IUFFER_BTATUSJI-FULLI AND COUTJ'TRJI-:za-INJ'TRJI I I
TIEN BU~ER_BTATUB--"-INUBEI
102 2 RETURN CHAR,
103 END FIFOJlJlUT.
104 2 UBART_Xt1IT_INT: PROCEDURE INTERRUPT 2 USINg 11
296166-55
14-60
inter RUPITM_44
AppUc.Uan Module: A• ..,nc/SDLC PrDtocol canye,.hr 19: DO: 53 09/19/83 PAQE
.05 DECLARE
" PESSAQE BASED ERR_PEBSAOEJ'TR ( 1 J BYTE CONSTANT'
IF ERROR.,FLAO
'0'
.oa
"3 THEN DO,
IF t1EBSAQECERRJlESSAQE_INDEXJ<>O , . Thn continu. to . . nd the . . . . . . . _,
THEN DO,
llO 4 USARTJ)ATA. ftESSADECEARJ£SSADE_INDEXJ,
4
"'
ll2 4
ERR..,.MESSAQE_INDEX-EAR.)IEBSAOE_INDEX+I.
END,
ll3
ll4
4
4
ELSE DO, '*
I f •••••, . h dan. ,. ••• t ERRORJLAO .nd .hut aff int.,.rupt "
ERADAJLAQ-OI
FIFO,s ...ptU *'
ll5 4 IF BUFFER_STATUSJI • EMPTY
THEN Ext-O,
ll7 4 ENOl
ua 3 END.
U9 2 ELSE UBARTJJATAraFIFO-"_OUT.
,"0 END USART..x'UT_INTI
.".
.22
"
2
SIUJlECY: PROCEDURE (LENGTH) PUBLIC USING I,
DECLME LENGTH
I
BYTE.
BYTE AUXILIARY,
.23
.24
.25
3
4
4
DO 1-0 TO LENOTH-l,
DO WHILE BUFFER_SrArUSJlaFULL, , . Ch.d to . . . i f fUa h
END.
hll *'
126 3 CALL FIFD..JI_'NCSIU..JIECYJlUFFERU l l.
127 3 END.
129 END SIU..JIECY.
129 2 FIFO_T_IN: PROCEDURE (CHAR) USING .2,
130 2 DECLARE CHAR BYTE.
131 2 FIFD_TC IN""pTR_Tl-tHAR.
132 2 INJTR_T-INJlTR_T+:L1
133 2 IF CHM-LF
THEN BENDJ)ATA-SENDJ)ATA+l,
135 2 IF IUFFERJlTATUS_T-E. . TY
TfoEN 8UFFERJlTATUS_T-lNUSE,
137 2 ELSE IF CCIUFFER_STATUS_T-INUSE) AND CINJlTR_T+aO-OUT....pTR_T»
THEN DO, '* Stop ,..c.ption udnl eTa */
139 3 USAATJlTATUS, USART_CI'1D-USART_CI'1D AND NDT(20H),
140 3 IUFFERJJTATUS_T-FULL.
141 3 IF SENDJ)ATA-O
143 3
THEN SENDJ)ATA-:L,,*U ttl. buff.,. is full .nd na LF
END.
h•• b •• n ,..c.iv.d then •• nd d.t. *'
144 1
296166-56
14-61
intJ RUPITM_44
PL/.... I,. CDI'IP ILEA AppHe.tio" f1Dduh: .... unc/sDLe P'r'otocol cony_,.t.,. 18: :10: 53 09/19/83 PADE 7
14' 2 FIFD_T _OUT: PROCEDURE 8Y.TE I
146 2 DECLARE CHAR IYTE ,.UXILIARV,
147 2 CHM-FIFO_T([JUTJTR_T1 J
148
149
2
2
DUTJlTR_T-ouTJTR_T+11
IF ~T:Oi.INJTR_T '* Then FI~_T is ••pt'it *'
1S1 3 E"-O,
1'2 3 IUFFER_STATUB_T-EMPTY,
153 3 SEHD.J)ItTA-O.
1'4 3 E~ll
ISS 3 END.
1'6 2 ELSE IF CCIUFFER.-sTATUS_T-FULL) AHD CDUTjTR_T-ao-IN~TR_n)
THEN DO,
1118 3 USART.-sTATUS. USART_CHD-usART _CHD DR 2OH.
1'9 3 8UFFER-.sTATUB_'-INUSE, '
160 3 ENOl
161 2 IF (CHAR-LF AND SENDJ)ATA>O) TIEN SENDJ)ATA-SENDJ)ATA":I.
163 2 RETURN CHAR,
16~ 1 END FIFO_'_OUT.
16' 2 ERROR: PROCEDURE (STATUS) USINO 21
166 2 DECLARE STATUS BVTE,
167 2 IF (STATUS AND OBH)OO
TI£N ERRJlESBAOE-PTR-. PARITY.
169 2 ELSE IF (STATUS AND lOH)<>O
TI£N ERRJ£SSAOE..pTR-. OYER-"UN.
171 2 ELSE IF CSTATUS AHD 2011)00
TIEN ERR.JIEBSAOE..pTR-. FANE,
173 2 UBMT_STATUB-CUSART_Ctm OR IOHh /. R••• , .",.01" "*,. on USMT . ,
174 2 ERR..,.I'IE88AQE_INDEX • O.
175
176
2
2
ERRDRJ'LAo-l.
Ext-', '* TU'f'n on TI Int.rrupt- *'
177 END ERRDR.
178 2 LINKJUBC: PROCEDURE I
179 2 DECLARE HESSAOE"pTR WORD AUXILIARY.
fCESSAOE BASED ~8SACIE"pTR C1 ) BYTE CONSTANT,
oJ BVTE ~UXILIARY.
EXl_STORE BlT.
180 2 EXl_STOREaEUI /. Shut; off •• \lnc tr_n,.it int..,. ... upt . /
181 2 EXl-OJ
182 2 ~OEJTR-. LINK,
183 2 ~-O.
184 3 DO YULE (t£SSADE"'?<>O)J
296166-57
14-62
inter RUPITM·44
PL/I1-~l COttPtLER "'ppUCA'tiO" l1oduh: "s .. nc/SDLe Protocol convert.,- IB: SO: S3 09/19/83 PAGE 8
*'
••
.e DO WHILE WSART_BTATUS AND 01H)-O, /. W.U fa1' TIRDY on USART
.BO END,
.87 3 UBMTJ)ATA-P£SSAOEeJ) ,
.BB 3 oJ-..,+l •
• 89 3 END,
190 2 Ext-EX I_STORE, , . R•• to ........ nc trans.it intnrupt . /
'9' • END LINKJ)lSC.
.92 2 CD: PROCEDURE (CHAR) USING 21
.93 2 DECLARE CHAR BYTE,
'9. 3 DO WHILE CUBART_BTATUS AND DIH) • 0,
'9'
'90
3
2
ENOl
UBMT ..DATA-CHAR,
.97 END CO,
.98 2 CI: PROCEDURE BYTE U91NC1 2.
.....
200
3
3
DO WHILE CUSAAT _STATUS AND Q2H) •
ENOl
01
20. 2 RETURN USARTJ)AT/u
202 END ell
203 2 OETflX: PROCEDURE BYTE USJNQ 21
204 2 DECLARE CHAR BYTE AUXILIARY.
I BYTE AUXILIARY,
20' 2 LO: CIiNt-CI,
206 3 DO 1-0 TO Uh
207 3 IF CHAR-HEX_TABLE( I)
lIEN GOTO L1,
209 END,
2.0 2 Ll: CALL COCHEX_TABLE(I»I
211 2 IF 1-14.
THEN OOTO LO,
2.3 2 RETURN II
2 •• END GET.}<EX,
215 2 OUTPUT..JIEBBAOE: PROCEDURE <l'IESSAGE"'pTRI USING 2,
2 •• 2 DECLARE IlESBIIGE"'pTA WORD.
IIE_E BAIlED IlESSAGE"'pTRCll IYTE CONSTANT.
,I BYTE AUXILIARY'
2.7 2
2'B 3 DO WHILE I'IEBIIIOEC J) <> 0,
2.9 3 CALL CQCttEBSAOEC J))J
220 3 1-1+1,
296166-58
14-63
intJ RUPITM-44
PL/....II CIM'IU!R 18: SC!: 53 09/19/83 PIICIE 9
221 3 ENDI
222 END OUTPUTJEftAIlEI
223 2 f'ENU: PROCEDURE URINQ 2,
224 2 DECLARE I IYTE AUXlL.IARY,
CHAR BYTE AUXIL.IARY,
BTIlTlON.JIDIIRESS BYTE AUXILIARY,
22' 2 STMT:
CIILL OUTPUTJIIEIISIICIE (. BIONJINII
226 2
227 3 DO 1-<1 TO 41
228 3 IF CHARof1ENU_CHII/IUI
TlEN ODTO "I.
230 3 ENDI
231 2 "l: CALL COUENU_CHMCI)I
232 2 IF 1-'
ntEN IIIITD ItOI
234 3 DO CIISE II
235 4 DOl
236 4 CIILL DUTPUTJESSIICIEC.BTAT....ADDllII
237 4 .STATIDN.,ADDRESS-sHLCOETJEI, 4) I
238 4 STIlTION....ADDIIESSoCBTIlTION....ADDIIEBB DR IlET_HEXII
23'1 4 STAIIoSTIlTlON....ADDIIESSI
240 4 CIILL DUTPUTJEBSllClEC. S.JIDDlljlCKII
241 4 CALL COCtE'X_TMLE(SHIUSTATION.,.ADDRESS, 4)),
242 4 CIILL CDlHEX_TIllLEIOFH lIND BTIlTlON....ADDIIESSI II
243 4 CIILL DUTPUTJEBSIIOE('IIDDlljlCKJINJI
244 4 ENDI
24' 4 DOl
246 4 CIILL DUTPUTJtESSIIIIE(. DEBT.JIDDIIII
247 4 DE8T1""TIDN~J)DRESS"""COETjEX, 4),
248 4 DESTlNllTlON.JIDDIIESS-IDESTlNIITION.JIDDIIEBB DR IlETJEX II
249 CALL OUTPUTJ£B8I\CIE(. D.JIDDlljlCKli
296166-59
14-64
inter RUPITM_44
Appl'catlon Pladul.: " ... ne/BDLC P"o'ocol conv.,.t ... 18: ~Q: 53 09/19/83 PAGE 10
200 4 CM.L CDCHEX_TAlLECSHRCDEBTlNllTlDN.J'I)DREBB, 4J J)'
25,1 4 CALL COCHEX_TAIILECOFH AND DEBTINATlDN......DRESSII.
252 4 CALL DUTPUTJEBSAGEC, ADDR.J\CKJIN),
253 4 END.
254 4 DO.
255 4 CALL OUTPUT,.HESIlllQE C. FIN).
256 4 CALL OPEN,
257 4 END.
258 4 DQ.
259 4 CALL OUTPUT.,JESSAOEC. FIN),
260 4 CALL CLOSE'
261 4 END.
262 3 CALL DUTPUTftBBAGEC. FJN),
263 3 END. ,. DO CASE ./
264 END I'ENU.
260 2 USARTJlECY_INT: PROCEDURE INTERRUPT 0 USING 2,
266 2 DECLARE CHAR BYTE AUXILIARY.
STATUS BYTE AUXlL.IARY,
267 2 CHAR-uBARTJlATA.
268 2 STATUS-UllllRTJiTATUS AND 38H.
269 2 IF STATUSOO
THEN CALL ERRDRCSTATUSt,
271 2 Et.SE IF CHAR-ESC
THEN CALL PlENU.
273 3 ELSE DO,
274 3 CALL FIFO_T_INCCHAR',
275 3 IF ECHD-o
THEN CALL COCCHAR),
277 3 END.
278 END USART JlEC":'_INTI
279
2BO 2 DO FOREVER,
281 2 IF SENDJlATA)O
THEN DQ.
2B3 4 DO WHIL.E NOTCX"IT.JIUFFER~TV)I I.Wan until BIU_XPlIT_BUFFIf'
END. is •• p'" *'
284
285
2B6
4
3
3
LENGTH. CHAR -I.
SIU_X"IT..BUFFER CO'.DEBTIWATIQN..ADOREBB,
287 4 DO WHILE I CCHAR<>LFI AND CLENGTH<BUFFERJ.ENGTHI AND CBUFFER_STATUS_T<>EI1PTYII.
296166-60
14-65
intJ RUPITM·44
18: ~O: S3 0."9/83 PAGE 11
_ 4
CHAR-FIFO_T_OUT. .'
289 4 SIU_X"ITJlUFFERCLENIITH'oCHAII,
290 4 LENOTH-LENOTH+I.
291 4 END,
/. I f the Un • • nte" ••• , the ,.".In.1 .is ..... ,." than 8UFFER~NOTH ellar, ••nd the
Ll:
fh,t IUFFERJ.,ENOTH eb.,., n.n .. nd the " •• t, line. the SIU bu' f.,.
:Is an1u 8UFFERJ,.ENOTH ltV'.' . /
1-0, , . U.. J to cOUnt: the nUllb.,. of un.ute •• lul
:!92 3
tran •• Us ./
293
294
3
3
RETRY: JlESULT-TAANSMITCLENOTHJ I '*
Send th . . . . . . . . . ,
IF REBULT<>IUITA_TRANIIIIITTED
29. 4
,. w.n
THEN DD,
SO' ..I.e far Un. to connect then
WAIT-I,
1:", ••• in *'
297 4 THO-3CH,
29B 4 TLo-CMFlh
299 4 TRG-Il
300 S DO WHILE WAIT,
301 S END,
302 4 TRo-O.
303 4 1-1+1.
304 S IF 1)100 THEN DO. 1,* WaU 5 .. c to , . , on 1:I.n. et,.
'.nd ."1'01" ••••••• to t.rlllinel
~ S
and '''\1'
CALL LINKJ)ISC,
all*i" .,"
307 S GOTO Ll.
308 S END,
309
310
.-4 ODTO RETRY,
END,
311 3 END,
312 2
3'3 1
IIMNINOB:
2 ,IS THE HIOHEST USED INTERRUPT
IIDDULE .NFIIII....TICIN: (STATIC+OVERLAVAILE)
CODE B1ZE • 0612H 17141)
CONSTANT SIZE • OlC~ 4630
DIRECT VARIABLE SIZE OOH+OSH 00+ SD
INDIRECT VARIABLE B1ZE OOH+OOH OD+ OD
lIT S1ZE 02H+OIH 2D+ ID
IIT-ADDREBBABLE SIZE OOH+OOH OJ)+ OD
AUXILIARY YAlUABLE SIZE .021FH 543D
....XlIIUII STACK SIZE • OGaBH 400
,EOISTER-I_CB' USED: 012
713 LINES READ
o PRDORN'I ERROR CB.
END OF PL/"-SI CDIII'ILATlDN
296166-61
14-66
RUPITM_44
PL/H-Sl COI'fPILER RUPI-44 PrimaT'~ ShUan .:!O; 47: 13 09/26/83 PAGE
ISIS-II PL/I't-91 YI. 0
CDI'fPILER INYDKED BY; ; F2: PLH:51 : F2: PNDTE. SRC
'TITLE C 'RUPI-44 Prima,,\! ShUon')
.DEBUG
'REQIBTERBANJI,CO)
MAIN'MOD: DOl
und to include thelll: 'JNCLUDE (: f2: REQ44. Del) *'
/. To •• v. pape,. the RUPI registers are not listed. but this is the statement
aNOLIST
DECLARE LIT LITERALLY 'LITERALLV',
TRUE LIT 'OFFH',
FALSE LIT 'OOH',
FOREVER LIT 'WHILE 1'1
'* SDLe COMMANDS AND RESPONSES *'
DECL.ARE SNRM LIT '93H',
UA LIT '73H',
DISC LIT '53H',
DK LIT 'lFH'.
FRMR LIT '97H',
REO_DISC LIT '53H',
UP LIT '33H',
TEST LIT 'OF3H',
RR LIT 'ItH',
RNR LIT '15H'.
1* REMOTE STATION SUFFER STATUS *'
BUFFER..READY LIT '0',
BUFFER_NOT _READY LIT '1'.
'*
STATION STATES
DISCONNECT_S LIT
*' 'OOH'. 1* LOGICALLY DJSCONNECTED STATE*,
QO_TOJUSC L.IT '01H',
I_T _S L.IT '02H', /* INFORMATION TRANSFER STATE */
/* PARAMETERS PASSED TO XMIT _I_T _S */
T_I_FRAHE LIT 'OOH',
T-,RR LIT 'OIH',
T~NR L.IT '02H',
/* SECONDARV STATION IDENTIFICATION */
NUMBER_OF _STATIONS LIT '2',
SECONDARY _ADDRESSES(NUMBER_OF _STATIONS»
BYTE CONSTANT ( ~5H, 43H»,
296166-62
14-67
RUPITM·44
PL'f'I-:U COl1PILER RUPI-44 Prima,." Station' 20: 47: 13 09/26/93 P~gE 2
RSDCNUI'1BER_OF..sTATIONS) STRUCTURE
(STATION_ADDRESS BYTE.
STATION_STATE BYTE.
NS BYTE.
NR BYTE.
BUFFER_STATUS
INFO_LENGTH
BYTE.
BVTE.
'* The .. htu .. o. th • • • conh1'V .t.tiDn. bu'''" *'
DATIII(64) BYTE) AUXILIARY,
'*
VARIABLES
STATlDN_NUrlBER IVTE
*' AUXILIARY.
RECYJ'IELD_LENQTH BYTE AUXILIARY,
WAIT BIT.
'*
BUFFERS . ,
SIU_XMITJUFFER(04) BYTE IDATA.
SIU~ECYJlUFFER(64) BYTE,
POWER_ON: PROCEDURE J
9 2 DECLARE I BYTE AUXILIARY.
•
10
2
2
T8S-. SIU_X''lIT_BUFFERCOJi
RaS-. SIU..RECVJlUFFER(O),
11
12
2
2
R8L-64,
RBE-l,
'*/. En.bh tbl' SIU'. receiver*' ./
64 a"h reedv. buff.-r
13 00 1- 0 TO NUMBER_OF_STATIONS-I,
I" 3 RSDel). STAT]ON_ADDRESS.SECONDARY~DDRESSES( I),
15 3 RSDC I). STATION_SlATE-DISCONNECT_S;
16 3 RBD( I ). DUFFER_STATus-aUFFER_NOT-.READY'
17 3 RSD( I ). INFO_LENOTH-O,
18 ENOl
1.
20
2
2
SMD-54HI 1* Using DPLL, NAZI. PFS. nMER 1, • 62.5 Mltps
TI'IOD-21H;
*'
2.
22
23
"
2
2
TH1-OFFHI
TCON-4DH,
IE-82H;
'*
U~. timer 0 for receive tim. out. int~r"upt *'
2" END POWER_ON.
25 2 .MIT: PROCEDURE (CDNTRDL.-BVTE);
26 2 DECLARE CONTROL_BYTE BYTEi
27 2 TCa-CONTROL_BYTEi
2S 2 TBF-ll
296166-63
14-68
RUPITM_44
PL/M-51 CDMP ILER RUPI-44 PrilllArv Station 20: 47: 13 09/26/93 PAGE 3
29 2 RTS-.,
30 3 DC WHILE NOT SI;
3' 3 ENOl
32 2 BI-O,
33 END )1"11,
34 2 TlP1ER_O_INT: PROCEDURE INTERRUPT 1 USING II
35
36
2
, WAIT-O,
END TIMER_O_INTI
37 2 TIME_OUT: PROCEDURE BYTE, '* Tillie_out returns true if' there .... n't
.. flr.me rllceivlld within 200 m•• c.
38 2 DECLARE BYTE AUXILIARY,
If th.re w..... fr.lmll receivlld within
200 1II •• e then time_out returns , .. 1 ••. *'
39 DO 1-0 TO 3,
40 3 WAn-II
4, 3 THO-3CH,
42 3 TLO-OAFH,
43 3 TRO-I,
44 4 DO WHILE WAITI
45 4 IF SI-l
THEN COTD T _0 I,
47 4 END;
48 3 END,
49 RETURN TRUE,
50
Sl-Ol
51 2 RETURN FAL.Se,
52 END TU1E~OUT;
53 SEND_DISC: PROCEDURE,
54 2 TBlcO,
55 2 CALL XMIT(DISC),
56 2 IF TIME_our-FALSE
THEN IF RCO-UA OR Rca-OM
57 3 THEN 001
59 3 RSD C9TAT ION_NUt1BER). BUFFER_ST '\TUS·BUFFER~OT.-READY I
60 3 RBO( STATION..NUI'1BER). STATION_STATE=-OISCONNECT_51
6' 3 ENOl
62 2
63
64 2 SEND_SNR"': PROCEDURE;
65 2 TBl-Ol
296166-64
14-69
inter RUPITM-44
Pl/l'l-51 COMPILER RUPI-44 PrimarV Station 20: 47: 13 09/;!6/S3 PAGE
66 2 CALL XI'IITCSNRI'I).
67 2 IF CTIME_our-FALSE> AND CRCa-UA)
THEN DO;
69 3 RSDCSTATJON_NUf1BER1. STATION_STATE"'I_T _51
70 3 RSD(STATJON_NUf'lDER)' Ns.-OI
71 3 RSDCSTATlONJruI'1BER)' NAcO,
72 3 ENO,
73 2 RBE-',
7.
70 2 CHECK-fiS: PROCEDURE BYTE,
7. 2 IF (RSDCSTATION":'NUMBERL NR-(SHRIHCD.l) AND 07H»
THEN RETURN TRUE,
78 2 ELSE RETURN FALSEI
79 END CHECK_NS;
80 2 CHECK_NR: PROCEDURE BYTE,
_ls.
/ . Chu.k the Nt' f1hld of the ,.ltc:dvltd
h •• b •• n acknQlllhdgd.
,,..me.
If NsCP)+l-NrCS) then the frame
i f Ns(P)-NT'CS) then the fTame has not blten
ilcknollfledged. ehe r •• et th • • • conda,.v . /
8t 2 IF. «
(RSDCSlATION_NUMBER), NS + 1) AND 07H) • SHR(RCB, 5»
THEN DO;
83 3 RSD(STATIDN-.NUMBER). NS-' CRSDCSTATION.-NUI'IBER). NS+l) AND 07H),
a. 3 RSDCSTATlON_NUI'1BER). INFO_LENQTH-O;
ae 3 ENOl
a. 2 ELSE IF (RSDCSTATlON_NUf'fBERJ. NS <> SHRCRCB. 5J)
THEN RETURN FALSE,
as 2 RETURN TRUE,
a9 END CHECK-.NR,
90 2 RECElVE: PROCEDURE I
91 2 DECLARE BYTE AUXILIARY.
92 2 RSD (STATlON..NUMBER). BUFFER_STATUS-DUFFER_READV,
I . If .n RNR III.S ".C.~V.d buff.,. _,t.tus 111111 be ch.nged in the sup.,.viso,. ..
fI,. .... decode s.ction 'uth.,. dOllln in this p,.oc.du,. ••• nlJ oth.,. " •• pon5e
me.ns the r.mDte st.tiDns buff.,. is l'e.dlj *1
93
ge
2
3
IF (RCa AND 01H)-O
THEN DOl .1* I F,..me Rec.ived *,"
IF (CHECK_HB-TRUE AND BDV-O AND CHECK.flR-TRUEJ
97
9S •• THEN DOl RSD(STATlON..NUMBERL NR-( CRSDC"STATION_NUMBER). NR+!) AND 07H)1
RDP-1i
296166-65
14-70
intJ RUPITM-44
PL/M-51 COMPILER RUP]-44 Pri/llaT'~ Station 20: 47: 13 09/26/83 PAQE
••
100
RECV-FIELDJ.ENQTH-RFL-l;
ENOl
101 3 ELSE RSOCSTATION_NUMDER). STATIDN_STATE.aOD_TO_DISCi
102 3 END;
103 2 ELSE IF CRCB AND 03HI=OlH
10. 3
THEN DO; '*
Supervillory Frame received *1
IF CHECK_NR.zFALSE
THEN RSO(STATION_NUHBER I. STATION_STATE-QO_TOJHSCi
107 3 ELSE IF «RCB AND OFH)-O'H) 1* thlf" RNR *1
THEN RSDCSTATION_NUMDER). BUFFER_STATUS-BUFFER_NOT _READY;
10. 3 ENOl
110 3 ELSE DOi ,* Unnumber.d frame DT' unknown f,. .. m. received *'
III 3 IF RCB-FRMR
THEN Doi ,*.
*'
I f FRMR was received check NT' for an
ac:knollJledged I frallle
113 4 RCB-SIU_RECY_BUFFER( 1) I
114 4 I-CHECK_NRI
115 4 ENOl
tUt :3 RSO (STATION_NUMBER). STATIDN_STATE"OD_TOJ)I SCi
117 :3 ENOl
llS 2
II. END RECEIVE.
120 2
121 2 DECLARE TEMP BYTE;
122 IF TEl'IP-T_I_FRAME
THEN DOl
'* '* T1"an'lIit 1 frame *'
Transf.r the station buff.,. into int.rnal ram */
12. 4 DO TEI1P-O TO RBDCSTATIDNJlUI'1BER)' INFO_LENGTH-II
••
125 SIU_XMITJiUFFER (TEMP )"'RBOC STATJON-.NUMBER). DATA I TEMP) I
126 END;
, . Build the.l f"alll. control field . ,
127 3 TEMP.CSHLCRSOC'STATIONJlUI'IBER).NR.,:U OR SHLCRSDCSTATION_NUMDERI,NS.l1 011 WltI.
129 3 rpL=RSO(STATlON_NUMBER). INFOj.ENGTH,
12. 3 CALL XMlTCTEMPJi
130 3 IF TIME_OUT-FALSE
THEN CALL RECEIVE.
132 3 END.
133
13'
3
3
ELSE DO; '* Transmit RR or RNR.'
IF TEMP=T_RR
THEN TEMP-RRj
13' 3 ELSE TEHP ..RNRI
296166-66
14-71
inter RUPITM-44
PL,I'1-S1 COI1P]LER RUPI-44 Pri ... "u St.tion 20: 47: 13 09/26/83 PAOE 6
137 3 TEr1P.(SHL,tRSDCSTATlON_NUPtBEA), HR. 5) OR TEI1P),'
13B 3 TBL-OJ
139 3 CALL Xl'tITnEI'F),
140 3 IF T111E_OUT-FALSE
THEN CALL RECEIVEI
142 3 ENDI
143 I END X"lT_I_T_SJ
144 2 BUFFER_TRANSFER: PROCEDURE,
14~ a DECLARE I BYTE AUXILIARV.
oJ BYTE AUXILIARY,
146 3 DO 1-0 TO NUMBER_OF_STATlONB-l J .
147 3 IF RSDe J). BTATIONjlDDREBS-SIU..RECYJlUFFERCO)
THEN OOTO Ttl
149 3 ENDI
ISO 2 n: IF I-NUI'IBERJlF_STIITIDNS ,_ If th • • dll" . . . . d .t.UDn doe. not: nU ••
tllen diu,lt'd the data */
THEN DOl
IS2 3 RIP-OJ
IS3 3 RETURNI
1~4 3 ENDI
ISS 2 ELSE IF RSDel), INFDJ.ENOTH-O
liEN DOl
IS7 3 RSDe I). INFD_LENQTH-RECYjIELD..LEHGTHI
ISB 4 DO "-I TO RECYjIELD-.LENOTH,
IS9 4 RSD( I), DATAf.J-l J-SIU..REC"_BUFFERhJ)J
160 4 ENOl
161 3 RSP-O,
162 3 ENDI
163 END BUFFER_TRANSFER I
164 BEOIN:
CALL POWER_ONI
I.' a DO FOREvER I
I •• 3 DO STATlON_NUttBER-D TO NlR'tIER_OF'_STATIDNS-1J
,.7 3 STAD-RSDC STATION.JWt1BER). STATION..ADDRESSJ
16B 3 IF R9DCSTATION_NUf'IIBER). STATION_STATE. DISCONNECT_S
THEN CALL SEND~"J .
170 3 ELSE IF RSDCSTATIONJW"B~IU. BTATlON_STATE • OD_TOJUSC
THEN CALL SENDJlISC, .
172 3 ELSE IF CCRSDCSTATlDN_NUPlBERL IflFO-.LENQTH>OJ AND
CRSDCSTAnON~UMBER). 8UFFER..BTATUS-BUFFERJ'EADV»
THEN CALL XMIT_I_T_SCT_tJRAl'IEl,
174 3 ELSE IF RBP-O
THEN CALL XMJT_I_T_SCT_RR),
176 3 ELSE CALL XMIT_I_T_SCT_RNR);
177 3 IF RUP-1
THEN CALL BUFFER_TRANSFER,
296166-67
PL/I1-51 COMPILER 20: 47: 13 09/26/93 PAOE 7
17" ENOl
190 02 ENOl
IBI END MAI~MODI
WARNINgS:
1 IS- THE HIGHEST USED INTERRUPT
MODULE U"IIFORMAT10N: (STATIC+OYERLAVADLE)
CODe SIZE • 053DH 1341D
CONSTANT SIZE • 0002H 2D
DIRECT VARIABLE SIlE 40H+OiZH 64D+ iZD
INDIRECT VARIABLE SI ZE 4OH+00H 640+ OD
BIT SIZE 01H+00H 10+ 00
DIT-ADDRESSABLE SIZE OOH+OOH OD+ 00
AUXILIARV VARIABLE SIlE • 0093H 147D
MAXIr-ftJM STACK SUE • 0019H 25D
REC'HSTER-BANK(S) USED: o I
456 LINES READ
o PROORAM ERROR (S)
END OF PL/M-51 COI'IPILATION
296166-68
14-72
RUPITM Datasheet, 15
Application Note, Article
Reprint and Development
Support Tools
8044AH/8344AH/8744H
HIGH PERFORMANCE 8-BIT MICROCONTROLLER
WITH ON-CHIP SERIAL COMMUNICATION CONTROLLER
• 8044AH-lncludes Factory Mask Programmable ROM
• 8344AH-For Use with External Program Memory
• 8744H-lncludes User Programmable/Eraseable EPROM
. 8051 MICROCONTROLLER CORE SERIAL INTERFACE UNIT (SIU)
• Optimized for Real Time Control 12
MHz Clock, Priority Interrupts, 32 • Serial Communication Processor that
Operates Concurrently to CPU
Programmable I/O Lines, Two .16-bit
Timer/Counters • 2.4 Mbps Maximum Data Rate
• Boolean Processor • 375 Kbps using On-Chip Phase Locked
Loop
• 64K Accessible External Program
4K x 8 ROM, 192 x 8 RAM
• Communication Software in Silicon:
• Memory - Complete Data Link Functions
- Automatic Station Response
• 64K Accessible External Data Memory
• Operates as an SDLC Primary or
Secondary Station
• 4 ,..,s Multiply and Divide
The RUPI-44 family integrates a high performance 8-bit Microcontroller, the Intel 8051 Core, with an Intelli-
gent/high performance HDLC/SDLC serial communication controller, called the Serial Interface Unit (SIU).
See Figure 1. This dual architecture allows complex control and high speed data communication functions to
be realized cost effectively.
Specifically, the 8044's Microcontroller features: 4K byte On-Chip program memory space; 32 I/O lines; two
16-bit timer/event counters; a 5-source; 2-level interrupt structure; a full duplex serial channel; a Boolean
processor; and on-chip oscillator and clock circuitry. Standard TTL and most byte-oriented MCS-80 and MCS-
85 peripherals can be used for 1/0 amd memory expansion.
The Serial Interface Unit (SIU) manages the interface to a high speed serial link. The SIU offloads the On-Chip
8051 Microcontroller of communication tasks, thereby freeing t~e CPU to concentrate on real time control
tasks.
The RUPI-44 family consists of the 8044, 8744, and 8344. All three devices are identical except in respect of
on-chip program memory. The 8044 contains 4K bytes of mask-programmable ROM. User programmable
EPROM replaces ROM in the 8744. The 8344 addresses all program memory externally.
The RUPI-44 devices are fabricated with Intel's reliable + 5 volt, Silicon-gate HMOSII technology and pack-
aged in a 40-pin DIP.
The 8744H is available in a hermetically sealed, ceramic, 40-lead dual in-line package which includes a
window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics). During
normal op.eration, ambient light may adversely affect the functionality of the chip. Therefore applications which
expose the 8744H to ambient light may require an opaque label over the window.
8044's Dual Controller Architecture
HOLCI
SOLC
port
231663-1
Figure 1. Dual Controller Architecture
October 1987
15-1 Order Number: 231663-004
inter 8044AH/8344AH/8744H
Table 1. RUPITM-44 Family Pin Description
VSS - DATA TxD (P3.1) In point-to-pointor multipoint
configurations, this pin functions as data input!
Circuit ground potential. output. In loop mode, it serves as transmit pin.
A '0' written to this pin enables diagnostic.
mode.
vee
- INTO (P3.2).lnterrupt 0 input or gate control
+ 5V power supply during operation and program input for counter O.
verification. - INT1 (P3.3). Interrupt 1 input or gate control
input for counter 1.
PORTO - TO (P3.4): Input to counter O.
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and - SCLK T1 (P3.5). In addition to I/O, this pin pro-
data bus when using external memory. It is used vides input to counter 1 or serves as SCLK (se-
for data output during program verification. Port 0 rial clock) input.
can sink/source eight LS TTL loads (six in 8744). - WR (P3.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.
PORT 1
- RD (P3.7). The read control signal enables Ex-
Port 1 is an 8-bit quasi-bidirectional I/O port. It is ternal Data Memory to Port O.
used for the low-order address byte during pro-
gram verification. Port 1 can sink/source four LS
TTL loads. RST
A high on this pin for two machine cycles while the
In non-loop mode two of the I/O lines serve alter-
oscillator is running resets the device. A small ex-
nate functions: ternal pulldown ·resistor (::::::8.2K!l) from RST to
- RTS (P1.6). Request-to-Send output. A low in- Vss permits power-on reset when a capacitor
dicates that the RUPI-44 is ready to transmit. (:::::: 10p.f) is also connected from this pin to V cc.
- CTS (P1.7) Clear-to-Send input. A low indicates
that a receiving station is ready to receive.
ALE/PROG
Provides Address Latch Enable output used for
PORT 2 latching the address into external memory during
Port 2 is an 8-bit quasi-bidirection I/O port. It also normal operation. It is activated every six oscillator
emits the high-order address byte when accessing periods except during an external data memory ac-
external memory. It is used for the high-order ad- cess. It also receives the program pulse input for
dress and the control Signals during program verifi- programming the EPROM version.
cation. Port 2 can sink/source four LS TTL loads.
PSEN
PORT 3
The Program Store Enable output is a control sig-
Port 3 is an 8-bit quasi-bidirectional I/O port. It also nal that enables the external Program Memory to
contains the interrupt, timer, serial port and RD the bus during external fetch operations. It is acti-
and WR pins that are used by various options. The vated every six oscillator periods, except during
output latch corresponding to a secondary function external data memory accesses. Remains high
must be programmed to a one (1) for that function during internal program execution.
to operate. Port 3 can sink/source four LS LTT
loads.
EA/VPP
In addition to I/O, some of the pins also serve al- When held at a TTL high level, the RUPI-44 exe-
ternate functions as follows: . cutes instructions from the internal ROM when the
- I/O RxD (P3.0). In point-to-point or multipoint PC is less than 4096. When held at a TTL low
configurations, this pin controls the direction of level, the RUPI-44 fetches all instructions from ex-
pin P3.1. Serves as Receive Data input in loop ternal Program Memory. The pin also receives the
and diagnostic modes. 21V EPROM programming supply voltage on the
8744.
15-2
inter 8044AH/8344AH/8744H
Table 1. RUPITM-44 Family Pin Description (Continued)
XTAL 1 XTAL2
Input to the oscillator's high gain amplifier. Re- Output from the oscillator's amplifier. Input to the
quired when a crystal is used. Connect to VSS internal timing circuitry. A crystal or external source
when external source is used on XTAL 2. can be used.
Pl.0 vcc
'" P1.' PO.O ADO
PO.l AOI
f};
~:: c~
::a
Go
'"
iiTs
m
Pl1
P1 .•
Pl.S
Pl.7
PO.2
PO.3
PO••
PO.S
PO.I
A02
AD3
AOt
ADS
Alii
AST PO.7 A07
I/O Ii ·vpp
i[M:
RXD P3.0
DATA TXD P3.1 ALE PIIOG
INTO P3.2 mJii
l ".
INTI PU P2.7 A15
TO PU P2.I AU
_CTI
'" SCLK T1 P3.5 P2.5 AU
~ -~
Ii DATA TXD __ Wi P3.I P2.• A12
iiii P3.7 P2.3 All
-
Z INTO_ ..
~
~
i!I
iNfi.... ~
TO-., 0
SCLK..!!_ Go
=}@},...
"'-'"
2 _
. _
~
c
XTAL2
XTALI
VSS
P2.2
P2.1
P2.0
AID
A,
AI
~ WII_
~ iifi-- 231663-3
'" 231663-2
Figure 2. Logic Symbol Figure 3A. DIP Pin Configuration
"II;"'l<"'! C!CJ ()o Nt')
O::ii:a:a:a::~~g~~~
Pl.S 39 PO.4
P1.6 38 PO.S
P1.7 PO.6
RST/VPD PO.7
P3.0 EA
N/e N/e
P3.1 ALE
P3.2 PSEN
P3.3 P2.7
P3.4 P2.6
P3.S P2.S
231663-21
Figure 38. PLCC Pin Configuration
15-3 .
inter . 8044AH/8344AH/8744H
FREQUENCE
REFERENCE
r--
I DATA
I I-+I-----<'~~. 1/0
I~-"'" L-_~-...J I ~g~~DLC
I COMMUNICATIONS
I
I .........."r"I'"-.' I
I ~--¥..----.I
I TWO 16-BIT I
TIMER EVENT
I COUNTERS I
I
INTERRUPTS L---,r-T"-...J
L...-r-""'T-' I
,L
~--- ..J
INTERRUPTS CONTROL PARALLEL PORTS COUNTERS
ADDRESS DATA BUS
AND 1/0 PINS 231663-4
Figure 4. Block Diagram
FUNCTIONAL DESCRIPTION • 4K bytes of ROM
• 192 bytes of RAM
General • 32 I/O lines
The 8044 integrates the powerful 8051 microcontrol- • 64K address space for external Data Memoiy
lar with an intelligent Serial Communication Control- • 64K address space for external Program Memory
ler to provide a single-chip solution which will effi- • two,fully programmable 16-bit timer/counters
ciently implement a distributed processing or distrib-
uted control system. The microcontroller is a self- • a five-source interrupt structure with two priority
sufficient unit containing ROM, RAM, ALU, and its level,S
own peripherals. The 8044's architecture and in- • bit addressability for Boolean processing
struction set are identical to the 8051's. The 8044
replaces the 8051's serial interface with an intelli- SPEClAL
FUNCTION
gent SOLC/HOLC Serial Interface Unit (SIU). 64 REGISTERS
~
more bytes of RAM have been added to the 8051 iii 255 241 FlH
RAM array. The SIU can communicate at bit rates up Fo.
E••
to 2.4 M bps. The SIU works concurrently with the EO.
DB.
Microcontroller so that there is no throughput loss in , RAM DOlt
ClI.
~iii
{D
either unit. Since the SIU possesses its own intelli- co•
••H
gence, the CPU is off-loaded from many of the com- .0H
A.H
munications tasks, thus dedicating more of its com~
puting power to controlling local peripherals or some
INDIRECT.
ADORESS·
ING
'
.B.
ADH
ID.
00.
external process. ' !!! 135 128 IOH
DIRECT
127 ADDRESS-
ING
The Microcontroller
The microcontroller is a stand-alone high-perform-
:"~ES",
BITS IN
Bl:A.
(121 BITS)
t!!
32
- A7
24 AD BANK3
127 120
0
ance single-chip computer intended for use in so- - A7 BANK2
phisticated real-time application such as instrumen- REGISTERS !!. A7
, 8' AD BANtU
tation, industrial control, and intelligent computer pe-
~ :~
ripherals.
INTERNAL
BANKO
.
SPECIAL FUNCTION
The major features of the microcontroller are: DATA RAM REGISTERS 231663-5
• 8-bit CPU Figure 5. Internal Data Memory Address Space
• on-chip oscillatOr
15-4
8044AH/8344AH/8744H
• 1 p.s instruction cycle time for 60% of the instruc- Parallel 1/0
tions 2 p.s instruction cycle time for 40% of the
instructions The 8044 has 32 general-purpose I/O lines which
• 4 p.s cycle time for 8 by 8 bit unsigned Multiplyl are arranged into four groups of eight lines. Each
Divide group is called a port. Hence there are four ports;
Port 0, Port 1, Port 2, and Port 3. Up to five lines
from Port' 3 are dedicated to supporting the serial
INTERNAL DATA MEMORY channel when the SIU is invoked. Due to the nature
of the serial port, tWo of Port 3's lID lines (P3.0 and
Functionally the Internal Data Memory is the most P3.1) do not have latched outputs. This is true
flexible of the address spaces. The Internal Data whether or not the serial channel is used.
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-bit Special Port 0 and Port 2 also have an alternate dedicated
Function Register address space as shown in Figure function. When placed in the external access mode,
5. Port 0 and Port 2 become the means by which the
8044 communicates with external program memory.
The Internal Data RAM address space is 0 to 255. Port 0 and Port 2 are also the means by which the
Four 8-Register Sanks occupy locations 0 through 8044 communicates with external data memory. Pe-
31. The stack can be located anywhere in the Inter- ripherals can be memory mapped into the address
nal Data RAM address space. In addition, 128 bit space and controlled by the 8044.
locations of the on-chip RAM are accessible through
Direct Addressing. These bits reside in Internal Data
RAM at byte locations 32 through 47. Currently loca-
tions 0 through 191 of the Internal Data RAM ad-
dress space are filled with on-chip RAM.
Table 2. MCS®-S1Instruction Set Description
Mnemonic Description Byte Cyc Mnemonic Description Byte Cyc
ARITHMETIC OPERATIONS ARITHMETIC OPERATIONS (Continued)
ADD A,Rn Add register to SUSS A,@Ri Subtract indirect
Accumulator RAM from A with
ADD A,direct Add direct byte Sorrow
to Accumulator 2 SUBB A,#data Subtract immed
ADD A,@Ri Add indirect data from A with
RAM to Borrow 2
Accumulator INC A Increment
ADD A,#data Add immediate Accumulator
data to INC Rn Increment
Accumulator 2 register
ADDC A,Rn Add register to INC direct Increment direct
Accumulator byte 2
with Carry INC @Ri Increment
ADDC A,direct Add direct byte indirect RAM
to A with Carry INC DPTR Increment Data
flag 2 Pointer 2
ADDC A,@Ri Add indirect DEC A Decrement
RAM to A with Accumulator
Carry flag DEC Rn Decrement
AD DC A,#data Add immediate register
data to A with DEC direct Decrement
Carry flag 2 direct byte 2
SUBB A,Rn Subtract register DEC @Ri Decrement
from A with indirect RAM 1
Borrow MUL AB Multiply A & B 4
SUBB A,direct Subtract direct DIV AB DivideAbyB 4
byte from A with
DA A Decimal Adjust
Borrow 2
Accumulator
15-5
inter .8044AH/8344AH/8744H ~OOI§Il.DIMJDOO~OOW
Table 2. MCS@-51InstructlonSetDescrlptlon (Continued)
Mnemonic Description Byte Cyc Mnemonic Description Byte Cyc
LOGICAL OPERATIONS LOGICAL OPERATIONS (Continued)
ANL A,Rn AND register to RL A Rotate
Accumulator Accumulator
ANL A,direct AND direct byte Left
·to Accumulator 2 RLC A Rotate A Left
ANL A,@RI AND indirect through the
RAM to Carry flag
Accumulator RR A Rotate
ANL A,#data AND immediate Accumulator
data to Right
Accumulator 2 RRC A Rotate A Right
ANL direct,A AND through Carry
Accumulator to flag
direct byte 2 SWAP A Swap nibbles
ANL direct,#data AND immediate within the
data to direct Accumulator
byte 3 2 DATA TRANSFER
ORL A,Rn OR register to MOV A,Rn Move register to
Accumulator Accumulator
ORL A,direct OR direct byte to MOV A,direct Move direct byte
Accumulator 2 to Accumulator 2
ORL A,@Ri OR indirect RAM MOV A,@RI Move indirect
to Accumulator RAM to
ORL A,#data OR immediate Accumulator
data to MOV A,#data Move immediate
Accumulator 2 data to
ORL direct,A OR Accumulator Accumulator 2
to direct byte 2 MOV Rn,A Move
ORL direct,#data OR immediate Accumulator to
data to direct register
byte 3 2 MOV Rn,direct Move direct byte
XRL A,Rn Exclusive-OR to register 2 2
register to - MOV Rn,#data Move immediate'
Accumulator data to register 2
XRL A,direct Exclusive-OR MOV direct,A Move
direct byte to Accumulator to
Accumulator 2 direct byte 2
XRL A,@RI Exclusive-OR MOV direct,Rn Move register to
indirect RAM to direct byte 2 2
A MOV direct, direct Move direct byte
XRL A,#data Exclusive-OR to direct 3 2
immediate data MOV direct,@Ri Move indirect
toA 2 RAM to direct
XRL direct,A Exclusive-OR byte 2 2
Accumulator to MOV direct,#data Move immediate
direct byte 2 data to direct
XRL direct, # data Exclusive-OR byte 3 2
immediate data MOV @Ri,A . Move
to direct 3 2 Accumulator to
CLR A Clear' indirect RAM
. Accumulator MOV @Ri,direct Move direct byte
CPL A Complement to indirect RAM 2 2
Accumulator
15-6
intJ 8044AH/8344AH/8744H ~OO~!LOfMlOOO&'OOW
Table 2. MCS®-S1Instruction Set Description (Continued)
Mnemonic Description ByteCyc Mnemonic Description Byte Cyc
DATA TRANSFER (Continued) BOOLEAN VARIABLE MANIPULATION
MOV @Ri,#data Move immediate (Continued)
data to indirect ANL C,/bit AND
RAM 2 complement of
MOV DPTR,#data16Load Data direct bit to
Pointer with a Carry 2 2
16-bit constant 3 2 ORL C/bit OR direct bit to
MOVCA,@A+ DPTR Move Code byte Carry flag 2 2
relative to DPTR ORL C,/bit OR complement
toA 2 of direct bit to
MOVCA,@A+PC Move Code byte Carry 2 2
relative to PC to MOV C,/bit Move direct bit
A 2 to Carry flag 2
MOVXA,@Ri . Move External MOV bit,C Move Carry flag
RAM (8-bit addr) to direct bit 2 2
toA 2
MOVXA,@DPTR Move External PROGRAM AND MACHINE CONTROL
RAM (16-bit ACALL addr11 Absolute
addr) to A 2 Subroutine Cail 2 2
MOVX@Ri,A MoveAto LCALL addr16 Long Subroutine
External RAM Call 3 2
(8-bit addr) 2 RET Return from
MOVX@DPTR,A Move A to subroutine 2
PUSH direct
External RAM
(16-bit) addr
Push direct byte
2
RETI
" '. Return from
interrupt 1 2
AJMP addr11 Absolute Jump 2 2
onto stack 2 2
LJMP addr16 LOl']gJump 3 2
POP direct Pop direct byte
SJMP rei Short Jump
from stack 2 2
(relative addr) 2 2
XCH A,Rn Exchange
JMP @A + DPTR Jump indirect
register with
relative to the
Accumulator
DPTR 2
XCH A,direct Exchange direct
JZ rei Jump if
byte with
Accumulator is
Accumulator 2
Zero 2 2
XCH A,@Ri Exchange
JNZ rei Jump if
indirect RAM
Accumulator is
with A
Not Zero 2 2
XCHDA,@Ri Exchange low-
JC rei Jump if Carry
order Digit ind
flag is set 2· 2
RAMwA
JNC rei Jump if No Carry
flag 2 2
BOOLEAN VARIABLE MANIPULATION
JB bit,rel Jump if direct Bit
CLR C Clear Carry flag 1 set 3 2
CLR bit Clear direct bit 2 JNB bit,rel Jump if direct Bit
SETB C Set Carry Flag 1 Not set 3 2
SETB bit Set direct Bit 2 JBC bit,rel Jump if direct Bit
CPL C Complement is set & Clear bit 3 2
Carry Flag CJNE A,direct,rel Compare direct
CPL bit Complement toA&Jumpif
direct bit 2 Not Equal 3 2
ANL C,bit AND direct bit to CJNE A,#data,rel Comp, immed,
Carry flag 2 2 to A & Jump if
Not Equal 3 2
15-7
8044AH/8344AH/8744H
Table 2. MCS®·51 Instruction Set Description (Continued)
Mnemonic Description Byte eyc Notes on data addressing modes:
PROGRAM AND MACHINE CONTROL (Continued) ,
(Continued) # data - 8-bit constant included in instruction
CJNE Rn,#data,rel Comp, immed, #data16 - 16-bit constant included as bytes 2
to reg & Jump if & 3 of instruction
Not Equal 3 2 bit -128 software flags, any I/O pin, con-
CJNE @Ri,#.data, rei Comp, immed, troll or status bit
to indo & Jump if
Not Equal 3 2 Notes on program addressing modes:
DJNZ Rn,rel Decrement addr16 - Destination address for LCALL &
register & Jump LJMP may be anywhere within the
if Not Zero 2 2 64-K program memory address
DJNZ direct,rel Decrement space
direct & Jump if Addr11 - Destination address for ACALL &
Not Zero 3 2 AJMP will be within the same 2-K
NOP No operation page of program memory as the first
byte of the following instruction
Notes on da~a addressing modes: rei - SJMP and a/l conditional jumps in-
Rn - Working register RO-R7 clude an 8~bit offset byte, Range is
direct - 128 internal RAM locations, any I/O + 127 -128 bytes relative to first
port, control or status register byte of the following instruction
@Ri -Indirect internal RAM location ad- All mnemonic copyrighted@ Intel Corporation 1979
dressed by register RO or R1
Timer/Counters Serial Interface Unit (SIU)
The 8044 contains two 16-bit counters which can be The Serial Interface Unit is used for HDLC/SDLC
used for measuring time intervals, measuring pulse communications. It handles Zero Bit Insertion/Dele-
widths, counting events; generating precise periodic tion, Flags automatic access recognization, and a
interrupt requests, and clocking the serial communi- 16-bit cyclic redundancy check. In addition it imple-
cations. Internally the Timers are clocked at 1/12 of ments in hardware a subset of the SDLC protocol
the crystal frequency, which is the instruction cycle certain applications it is advantageous to have the
time. Externally the counters can run up to 500 KHz. CPU control the reception or transmission of every
single frame. For this reason the SIU has two modes
of operation: "AUTO" and "FLEXIBLE" (or "NON-
Interrupt System AUTO"). It is in the AUTO mode that the SIU re-
sponds toSDLG frames without CPU intervention;
External events and the real-time driven on-chip pe- whereas, in the FLEXIBLE mode the reception or
ripherals require service by the CPU asynchronous transmission of every single frame will be under CPU
to the execution of any particular section of code. To control.
tie the asynchronous activities of these functions to
normal program execution, a sophisticated multiple- There are three control registers and eight parame-
source,two priority level, nested interrupt system is ter registers that are used to operate the serial inter-
provided. Interrupt response latency ranges from 3 face. These registers are shown in Figure 5 and Fig-
,""sec to 7 ,""sec when using a 12 MHz clock. ure 6. The control register set the modes of opera-
tion and provide status information. The eight pa·
All five'interrupt sources can be mapped into one of rameter registers buffer the station address, receive
the two priority levels. Each interrupt source can be and transmit control bytes, and point to the on-chip
enabled or disabled individually or the entire inter- transmit and receive buffers.
rupt system can be enabled or disabled. The five
interrupt sources are: Serial Interface Unit, Timer 1, Data to be received or transmitted by the SIU must
Timer 2, and two external interrupts. The external be buffered anywhere within the 192 bytes of on-
interrupts can be either level or edge triggered. chip RAM. Transmit and receive buffers are not al-
lowed to "wrap around" in RAM; a "buffer end" is
generated after address 191 is reached.
15-8
inter 8044AH/8344AH/8744H
SYMBOLIC BYTE
REGISTER NAMES ADDRESS BIT ADDRESS ADDRESS
~
B REGISTER B 247 throuah 240 240 (FOH)
ACCUMULATOR ACC throuah 224 224 (EOH)
"THREE BYTE FIFO FIFO 223 (DFH)
FIFO 222 (DEH)
FIFO 221 (DDH)
TRANSMIT BUFFER START TBS 220 (DCH)
TRANSMIT BUFFER LENGTH TBL 219 (DBH)
TRANSMIT CONTROL BYTE TCB 218 (DAH)
, SIU STATE COUNTER SIUST 217 (D9H)
~
SEND CDUNT RECEIVE COUNT NSNR 216 (D8H)
PROGRAM STATUS WORD PSW 208 208 (DOH)
'DMA COUNT DMA CNT 207 (CFH)
STATION ADDRESS STAD 206 (CEH)
RECEIVE FIELD LENGTH RFL 205 (CDH)
RECEIVE BUFFER'START RBS 204 (CCH)
RECEIVE BUFFER LENGTH RBL 203 (CBH) SFR's CONTAINING
RECEIVE CONTROL BYTE RCB 202 (CAH) D)RECT ADDRESSABLE BITS
SERIAL MODE SMD 201 (C9H)
STATUS REGISTER STS throuah 200 (C8H)
INTERRUPT PRIORITY CONTROL IP throuah 184 (B8H)
PORT 3 P3 throuGh 176 (BOH)
INTERRUPT ENABLE CONTROL IE 168 (A8H)
PORT 2 P2 throuah 160 (AOH)
PORT 1 PI throuah 144 (90H)
TIMER HIGH 1 THI 141 (8DH)
TIMER HIGH 0 THO 140 (8CH)
TIMER LOW 1 TLI 139 (8BH)
TIMER LOW 0 TLO 138 (8AH)
TIMER MODE TMDD 137 (89H)
TIME'R CONTROL TCON 143 136 (88H)
DATA POINTER HIGH DPH 131 (83H)
DATA POINTER LOW DPt. 130 (82H)
STACK POINTER SP 129 (81H)
PORTO PO 135 throuah 128 128 (80H)
231663-6
NOTE:
'ICE Support Hardware registers, Under normal operating conditions there is no need for the CPU to access these
registers,
Figure 5. Mapping of Special Function Registers
SERIAL MODE REGISTER (SMD) SCM2 SCMl SCMO NRZI LOOP PFS NB NFCS
I '--- NO FRAME CHECK SEQUENCE
I I NON· BUFFERED
PRE· FRAME EYNC
LOOP
NON RETURN TO ZERO INVERTED
SELECT CLOCK MODE
STATUS REGISTER (STS) TBF RBE RTS SI BOV OPB AM RBP
~
I I
I RECEIVE BUFFER PROTECT
AUTO MODEIAODRESSED MODE
OPTIONAL POLL BIT
RECEIVE INFORMATION BUFFER OVERRUN
SERIAL INTERFACE UNIT INTERRUPT
REQUEST TO SEND
RECEIVE BUFFER EMPTY
TRANSMIT BUFFER FULL
SEND COUNT RECEIVE
COUNT REGISTER (NSNR) r-:=,.-r-:-::~...-:=,.-r""",,,,.-...-:=,.-r--..:~-r-,=...,.-,;;;:;;-,
SEQUENCE ERROR RECEIVED
L-_...L_---"L.._ _ _ RECEIVE SEQUENCE COUNTER
L-_______________________ SEQUENCEERRORSEND
L-_...L_---"_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEND SEQUENCE COUNTER
231663-7
Figure 6. Serial Interface Unit Control Registers
15·9
inter 8044AH/8344AH/8744H
With the addition of only a few bytes of code, the lowing responses without CPU intervention: I (Infor-
8044's frame size is not limited to the size of its mation), RR (Receive Ready), and RNR (Receive
internal RAM (192 bytes), but rather by the size of Not Ready).
external buffer with no degradation of the RUPI's
features (e.g. NRZI, zero bit insertion/deletion, ad- When the Receive Buffer Empty bit (RBE) indicates
dress recognition, cyclic redundancy check). There that the Receive Buffer is empty, the .receiver is en-
is a special function register called SIUST whose abled, and when the RBE bit indicates that the Re-
contents dictates the operation of the SIU. At low ceive Buffer is full, the receiver is disabled. Assum-
data rates, one section of the SIU (the Byte Proces- ing that the Receiver Buffer is empty, the SIU will
sor) performs no function during known intervals. respond to a poll with an I frame if the Transmit Buff~
For a given data rate, these intervals (stand-by er is full. If the Transmit Buffer is empty, the SIU will
mode) are fixed. The above characteristics make it respond to a poll with a RR command if the Receive
possible to program the CPU to move data to/from Buffer Protect bit (RBP) is cleared, or an RNR com-
external RAM and to force the SIU to perform some mand if RBP is set.
desired hardware tasks while transmission or recep-
tion is taking place. With these modifications, exter-
nal RAM can be utilized as a transmit and received FLEXIBLE (or NON-AUTO) Mode
buffer instead of the internal RAM.
In the FLEXIBLE mode all communications are un-
der control of the CPU. It is the CPU's task to en-
AUTO Mode code and decode control fields, manage acknowl-
edgements, and adhere to the requirements of the
In the AUTO mode the SIU implements in hardware HOLC/SOLC protocols. The 8044 can be used as a
a subset of the SOLC protocol such that it responds primary or a secondary station in this m9de.
to many SOLC frames without CPU intervention. All
AUTO mode responses to the primary station will To receive a frame in the FLEXIBLE mode, the CPU
comform to IBM's SOLC definition. The advantages must load the Receive Buffer Start register, the Re-
of the AUTO mode are that less software is required ceive Buffer Length register, clear the Receive Buff-
to implement a secondary station, and the hardware er Protect bit, and set the Receive Buffer Empty bit.
generated response to polls is much faster than do- If a valid opening flag is received and the address
ing it in software. However, the Auto mode can not field matches the byte in the Station Address regis-
be used at a primary station. ter or the address field contains a broadcast ad-
dress, the 8044 loads the control field in the receive
To transmit in the AUTO mode the CPU must load control byte register, and loads the I field in the re-
the Transmit Information Buffer, Transmit Buffer ceive buffer. If there is no CRC error, the SIU inter-
Start register, Transmit Buffer Length register, and rupts the CPU, indicating a frame has just been re-
set the Transmit Buffer Full bit. The SIU automatical- ceived. If there is a CRC error, no interrupt occurs.
ly responds to a poll by transmitting an information The Receive Field Length register provides the num-
frame with the P/F bit in the control field set. When ber of bytes that were received in the information
the SIU receives a positive acknowledgement from field.
the primary station, it automatically increments the
Ns field in the NSNR register and interrupts the To transmit a frame, the CPU must load the transmit
CPU. A negative acknowledgement would cause the information buffer, the Transmit Buffer Start register,
SIU to retransmit the frame. the Transmit Buffer Length register, the Transmit
Control Byte, and set the TBF and the RTS bit. The
To receive in the AUTO mode, the CPU loads the 81U, unsolicited by an HOLC/SOLC frame, will trans-
Receive Buffer Start register, the Receive Buffer mit the entire information frame, and interrupt the
Length register, clears the Receive Buffer Protect CPU, indicating the completion of transmission. For
bit, and sets the Receive Buffer Empty bit. If the SIU supervisory frames or· unnumbered frames, the
is polled in this state, and the TBF bit indicates that transmit buffer length would be O.
the Transmit Buffer is empty, an automatic RR re-
sponse will be generated. When a valid information
frame is received the SIU will automatically incre- CRC
ment Nr in the NSNR register and interrupt the CPU.
The FCS register is initially set to all 1's prior to cal-
While in the AUTO mode the SIU can recognize and culating the FCS field. The SIU will not interrupt the
respond to the following commands without CPU in- CPU if a CRC error occurs (in both AUTO and FLEX-
tervention: I (Information), RR (Receive Ready), IBLE modes). The CRC error is cleared upon receiv-
RNR (Receive Not Ready), REJ (Reject), .and UP ing of an opening flag.
(Unnumbered Poll). The SIU can generate the fol-
15-10
8044AH/8344AH/8744H
Frame Format Options be stored in the Transmit and Receive buffers. For
example, in the non-buffered mode the third byte is
In addition to the standard SDLC frame format, the treated as the beginning of the information field. In
8044 will support the frames displayed in Figure 7. the non-addressed mode, the information field be-
The standard SDLC frame is shown at the top of this gins after the opening flag. The mode bits to set the
figure. For the remaining frames the information field frame format options are found in the Serial Mode
will incorporate the control or address bytes and the register and the Status register.
frame check sequences; therefore these fields will
FRAME OPTION NFCS NB AM1 FRAME FORMAT
Standard SOLC
NON-AUTO Mode
0 0 0 IF IA IC I I I FCS I F I
Standard SOLC
AUTO Mode
0 0 1 IF IA IC I I I FCS I F I
Non-Buffered Mode
NON-AUTO Mode
0 1 1 IF IA I I I FCS I F I
Non-Addressed Mode
NON-AUTO Mode
0 1 0 I FI I
I FCS I F I
No FCS Field
NON-AUTO Mode
1 0 0 IF IA IC I I
I F I
No FCS Field
AUTO Mode
1 0 1 IF IA IC I I I F I
No FCSField
Non-Buffered Mode
1 1 1 IF IA I I
I F I
NON-AUTO Mode
No FCS Field
Non-Addressed Mode
1 1 0 IF I I I F I I
NON-AUTO Mode
Mode Bits:
AM - "AUTO" Mode/Addressed Mode
NB - Non-Buffered Mode
NFCS - No FCS Field Mode
Key to Abbreviations:
F = Flag (01111110) I = Information Field
A = Address Field FCS= Frame Check Sequence
C = Control Field
Note 1:
The AM bit function is controlled by the NB bit. When NB = 0, AM becomes AUTO mode select, when NB = 1, AM
becomes Address mode select.
Figure 7. Frame Format Options
15-11
inter 8044AH/8344AH/8744H
Extended Addressing transmit and receive data in this mode at rates up to
2.4 Mbps.
To realize an extended control field or an extended
address field using the HDLC protocol, the FLEX- This self clocked mode allows data transfer without
IBLEmode must be used; For an extended control a common system data clock.' An on-chip Digital
field, the SIUis programmed to be in the non-buff- Phase Locked Loop is employed to recover the data
ered mode. The extended control field will be the clock which is encoded in the data stream. The
first and second bytes in the Receive and Transmit DPLL will converge to the nominal bit center within
Buffers. For extended addressing the SIU is placed eight bit transitions, worst case. The DPLL requires a
in the non-addressed mode. In this mode the CPU reference clock of either 16 times (16x) or 32 times
must implement the address recognition for received (32x) the data rate. This reference clock may be ex-
frames. The addressing field will be the initial bytes ternally applied or internally generated. When inter-
in the Transmit and' Receive buffers followed by the nally generated either the 8044's internal logic clock
control field. (crystal frequency divided by two) or the timer 1
overflow is used as the reference clock. Using the
The SIU can transmit and receive only frames which internal timer 1 clock the data rates can vary from
are multiples of 8 bits. For frames received with oth- 244 to 62.5 Kbps. Using the'internal logic clock at a
er than 8-bit multiples, a CRC error will cause the 16x sampling rate, receive, data can either be 187.5
SIU to reject the frame. Kl;lps, or 375 Kbps. When the reference clock for the
DPLL is externally applied the data rates can vary
from 0 to 375 Kbps at a 16x sampling rate.
SOLC Loop Networks,
To aid in a Phase Locked Loop capture, the SIU has
The SIU can be used in an SDLC loop as a second- a NRZI (Non Return to Zero Inverted) data encoding
ary or primary station. When the SIU is placed in the and decoding option. Additionally the SIU has a pre-
Loop mode it receives the data on pin 10 and trans- frame sync option that transmits two bytes of alter-
mits the data one bit time delayed on pin 11. It can nating 1's and O's to ensure that the receive station
also recognize the Go ahead signal and change it DPLL will be synchronized with the data by the time
into a flag when it is ready ~o transmit. As a second- ,it receives the opening flag.
ary station the SIU can be used in the AUTO or
FLEXIBLE modes. As a primary station the FLEX-
IBLE mode is used; however, additional hardware is Control and Status Registers
required for generating the Go Ahead bit pattern. In
the Loop mode the maximum data rate is 1, Mbps There are three SIU Control and Status Registers:
clocked or 375 Kpbs self-clocked. Serial Mode Register (SMD)
Status/Command Register (STS)
SOLC Multidrop Networks Send/Receive Count Register (NSNR)
The SIU can be used in a SDLC non-loop configura- The SMD, STS, and NSNR, registers are all cleared
tion as a secondary or primary station. When the SIU by system reset. This assures that the SIU will power
is placed in the non-loop mode, data is received and up in an idle state (neither receiving nor transmit-
transmitted on pin 11, and pin 10 drives a tri-state ting).
buffer. In non-loop mode, modem interface pins,
RTS and CTS, become available. These registers and their bit assignments are de-
scribed below.
Data Clocking Options
SMD: Serial Mode Register (byte-addressable)
The 8044's serial port can operate in an externally Bit 7: 6 5 4 3 2 1 0
clocked or self clocked system. A clocked system
ISCM21sCM11sCMOINRZIILOOpi PFsl NBI NFcsl
provides to the 8044 a clock synchronization to the
data. A self-clocked system uses the 8044's on-chip
Digital Phase Locked Loop (DPLL) to recover the The Serial Mode Register (Address C9H) selects the
clock from the data, and clock this data into the Seri- operational modes of the SIU. The 8044 CPU can
al Receive Shift Register. both read and write SMD. The SIU can read SMD
but cannot write to it. To prevent conflict between
In this mode, a clock synchronized with the data is CPU and SIU access to SMD, the CPU should write
externally fed into the 8044. This clock may be gen- SMD only when the Request To Send (RTS) and
erated from an External Phase Locked Loop, or pos-
sibly supplied along with the data. The 8044 can
15-12
8044AH/8344AH/8744H
Receive Buffer Empty (RBE) bits (in the STS regis- CPU, and enables the SIU to post status information
ter) are both false (0). Normally, SMD is accessed for the CPU's access. The SIU can read STS, and
only during initialization. can alter certain bits, as indicated below. The CPU
can both read and write STS asynchronously. How-
The individual bits of the Serial Mode Register are as ever, 2-cycle instructions that access STS during
follows: both cycles ('JBC/B, REL' and 'MOV/B, C.') should
not be used, since the SIU may write to STS be-
Bit# Name Description tween the two CPU accesses.
SMD.O NFCS No FCS field in the SDLC frame. The individual bits of the Status/Command Register
SMD.1 NB Non-Buffered mode. No control are as follows:
field in the SDLC frame.
SMD.2 PFS Pre-Frame Sync mode. In this Bit# Name Description
mode, the 8044 transmits two STS.O RBP Receive Buffer Protect. Inhibits
bytes before the first flag of a writing of data into the receive
frame, for DPLL synchronization. buffer. In AUTO mode, RBP
If NRZI is enabled, OOH is sent; forces an RNR response instead
otherwise, 55H is sent. In either of an RR.
case, 16 preframe transitions are
guaranteed. STS.1 AM AUTO Mode/Addressed Mode.
Selects AUTO mode where
SMD.3 LOOP Loop configuration. AUTO mode is allowed. If NB is
SMD.4 NRZI NRZI coding option. If bit = 1, true, (= 1), the AM bit selects the
NRZI coding is used. If bit = 0, addressed mode. AM may be
then it is straight binary (NRZ). cleared by the SIU.
SMD.5 SCMO Select Clock Mode-Bit 0 STS.2 OPB Optional Poll Bit. Determines
SMD.6 SCM1 Select Clock Mode-Bit 1 whether the SIU will generate an
AUTO response to an optional
SMD.7 SCM2 Select Clock Mode-Bit 2 poll (UP with P = 0). OPM may
be set or cleared by the SII).
The SCM bits decode as follows: STS.3 BOV Receive Buffer Overrun. BOV
may be set or cleared by the SIU.
SCM Data Rate STSo4 SI SIU Interrupt. This is one of the
2 1 0 Clock Mode (Bits/sec)· five interrupt sources to the CPU.
0 0 0 Externally clocked 0-204M·· The vector location = 23H. SI
may be set by the SIU. It should
0 0 1 Reserved be cleared by the CPU before
0 1 0 Self clocked, timer overflow 244-62.5K returning from an interrupt
0 1 1 Reserved routine.
1 0 0 Self clocked, external16x 0-375K STS.5 RTS Request To Send. Indicates that
the 8044 is ready to transmit or is
1 0 1 Self clocked, external 32x 0-187.5K transmitting. RTS may be read or
1 1 0 Self clocked, internal fixed 375K written by the GPU. RTS may be
1 1 1 Self clocked, internal fixed 187.5K read by the SIU, and in AUTO
mode may be written by the SIU.
NOTES: STS.6 RBE Receive Buffer Empty. RBE can
• Based on a 12 Mhz crystal frequency be thought of as Receive Enable.
"0-1 M bps in loop configuration
RBE is set tq one by the CPU
when it is ready to receive a
STS: Status/Command Register (bit- frame, or has just read the buffer,
addressable) and to zero by the SIU when a
Bit: 7 6 5 4 3 2 1 0 frame has been received.
ITBF IRBE IRTS ISI IBOV IOPB IAM IRBP I S:rS.7 TBF Transmit Buffer Full. Written by
the ~U to indicate that it has
fille the transmit buffer. TBF may
The Status/Command Register (Address C8H) pro- be cleared by the SIU.
vides operational control of the SIU ~y the 8044
15-13
inter 8044AH/8344AH/8744H
NSNR: Send/Receive Count Register (blt- TBS: Transmit Buffer Start Address Register
addressable) (byte-addressable)
Bit:? 6 543210
The Transmit Buffer Start address register (Address
INs2INs1INsolsEslNR2INR1IN~0IsERI DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmit-
The Send/Receive Count Register (Address D8H) ted. The CPU should access TBS only when the SIU
contains the transmit and receive sequence num- is not transmitting a frame (when TBF = 0).
bers, plus tally error indications. The SIU can both
read and write NSNR. The 8044 CPU can both read TBl: Transmit Buffer Length Register
and write NSNR asynchronously. However, 2-cycle (byte = addressable)
instructions that access NSNR during both cycles
(,JBC /B, REl,' and 'MOV /B,C') should not be The Transmit Buffer length register (Address DB H)
used, since the SIU may write to NSMR between the contains the length (in bytes) of the I-field to be
two 8044 CPU accesses. transmitted. A blank I-field (TBl = 0) is valid. The
CPU should access TBl only when the SIU is not
The individual bits of the Send/Receive Count Reg- transmitting a frame (when TBF = 0).
ister are as follows:
NOTE:
Blt# Name Description
The transmit and receive buffers are not allowed to
NSNR.O SER Receive Sequence Error: "wrap around" in the on-chip RAM. A "buffer end"
NS (P) =1= NR (S) is automatically generated if address 191 (BFH) is
reached.
NSNR.1 NRO Receive Sequence Counter-Bit 0
NSNR.2 NR1 Receive Sequence Counter-Bit 1 TCB: Transmit Control Byte Register
NSNR.3 NR2 Receive Sequence Counter-Bit 2 (byte-addressable)
NSNR.4 SES Send Sequence Error: The Transmit Control Byte register (Address DAH)
NR (P) =1= NS (S) and contains the byte which is to be placed in the control
NR (P) =1= NS (S) + 1 field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB
NSNR.5 NSO Send Sequence Counter-Bit 0 only when the SIU is not transmitting a frame (when
NSNR.6 NS1 Send Sequence Counter-Bit 1 TBF = 0). The Nsand NR counters are not used in
the NON-AUTO mode.
NSNR.? NS2 Send Sequence Counter-Bit 2
RBS: Receive Buffer Start Address Register
(byte-addressable)
Parameter Registers
The Receive Buffer Start address register (Address
There are eight parameter registers that are used in CCH) points to the location in on-chip RAM where
connection with SIU operation. All eight registers the beginning of the I-field of the frame being re-
may be read or written by the 8044 CPU. RFl and ceived is to be stored. The CPU should write RBS
RCB are normally loaded by. the SIU. only when the SIU is not receiving a frame (when
RBE = 0).
The eight parameter registers are as follows:
RBL: Receive Buffer length Register
STAD: Station Address Register (byte-addressable)
(byte-addressable)
The Receive Buffer length register (Address CBH)
The Station Address register (Address CEH) con- contains the length (in .bytes) of the area in on-chip
tains the station address. To prevent acess conflict, RAM allocated for the received I-field. RBl=O is
the CPU should access STAD only when the SIU is valid. The CPU should write RBl only when RBE = O.
idle (RTS = 0 and RBE = 0). Normally, STAD is
accessed only during initialization.
15-14
intJ 8044AH/8344AH/8744H
RFL: Receive Field Length Register The emulator operates with Intel's Inteliec™ devel-
(byte-addressable) opment system. The development system interfaces
with the user's 8044 system through an in-cable
The Receive Field Length register (Address CD H) buffer box. The cable terminates in a 8044 pin-com-
contains the length (in bytes) of the received I-field patible plug, which fits into the 8044 socket in the
that has just been loaded into on-chip RAM. RFL is user's system. With the emulator plug in place, the
loaded by the SIU. RFL = 0 is valid. RFL should be user can excercise his system in real time while col-
accessed by the CPU only when RBE = O. lecting up to 255 instruction cycles of real-time data.
In addition, he can single-step the program.
RCB: Receive Control Byte Register Static RAM is available (in the in-cable buffer box) to
(byte-addressable) emulate the 8044 internal and external program
The Received Control Byte register (Address CAH) memory and external data memory. The designer
contains the control field of the frame that has just can display and alter the contents of the replace-
been received. RCB is loaded by the SIU. The CPU ment memory in the buffer box, the internal data
can only read RCB, and should only access RCB memory, and the internal 8044 registers, including
when RBE = O. the SFR's.
SIUST: SIU State Counter (byte-addressable)
ICE Support
The SIU State Counter (Address D9H) reflects the
The 8044 In-Circuit Emulator (ICE-44) allows the state of the internal logic which is under SIU control.
user to exercise the 8044 application system and Therefore, care must be taken not to write into this
monitor the execution of instructions in real time. register. This register provides a useful means for
debugging 8044 receiver problem.
15-15
inter 8044AH/8344AH/8744H
ABSOLUTE MAXIMUM RATINGS* *Notice: Stresses above those listed under 'i'\bso-
Ambient Temperature Under Bias ...... O°C to 70°C lute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
Storage Temperature ........... -65°C to -150°C
functional operation of the device at these or any
Voltage on EA, VPP Pin to VSS ... -0.5V to -21.5V other conditions above those indicated in the opera-
Voltage on Any Other Pin to VSS .... - 0.5V to -7V tional sections of this specification is not implied Ex-
Power Dissipation ........................... 2W posure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. CHARACTERISTICS TA = O°Cto 70°C, VCC = 5V = 10%, VSS = OV
Symbol Parameter Min Max Unit Test Conditions
VIL Input Low Voltage (Except EA Pin of 8744H) -0.5 0.8 V
VIL1 Input Low Voltage to EA Pin of 8744H 0 0.8 V
VIH Input High Voltage (Except XTAL2, RST) 2.0 VCC + 0.5 V
VIH1 Input High Voltage to XTAL2, RST 2.5 VCC + 0.5 V XTAL1 = VSS
VOL Output Low Voltage (Ports 1, 2, 3)* 0.45 V IOL = 1.6mA
VOL1 Output Low Voltage (Port O,ALE,PSEN)*
0.60 V IOL = 3.2 rnA
8744H
0.45 V IOL = 2.4 rnA
8044AH/8344AH 0.45 V IOL = 3.2 rnA
VOH Output High Voltage (Ports 1, 2, 3) 2.4 V IOH = -80/LA
VOH1 Output High Voltage (Port 0 in External 2.4 V IOH =-400 /LA
Bus Mode, ALE, PSEN)
ilL Logical 0 Input Current (Ports 1,2, 3) -500 /LA Yin = 0.45V
IlL 1 Logical 0 Input Current to EA Pin
-15 rnA
of 8744H only
IIL2 Logical 0 Input Current (XTAL2) -3.6 rnA Yin = 0.45V
III Input Leakage Current (Port 0)
8744H ±100 /LA 0.45 < Yin < VCC
8044AH/8344AH ±10 /LA 0.45 < Yin < VCC
IIH Logical 1 Input Current to EA Pin of 8744H 500 p.A
IIH1 Input Current to RST to Activate Reset 500 p.A Yin < (VCC - 1.5V)
ICC Power Supply Current: All Outputs Discon-
8744H 285 rnA nected: EA = VCC
8044AH/8344AH 170 rnA
CIO Pin Capacitance 10 pF Test Freq. = 1MHz(1)
'NOTES:
1. Sampled not 100% tested. T A = 25'C.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to ex1ernal bus capacitance discharging into the Port 0 and Port 2 pin when these pins make 1-to-
o transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
15-16
inter 8044AH/8344AH/8744H
A.C. CHARACTERISTICS
T A = O°C to + 70°C, VCC = 5V ± 10%, VSS = OV, Load Capacitance for Port 0, ALE, and PSEN = 100 pF,
Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Variable Clock
12 MHzOsc
Symbol Parameter 1/TCLCL = 3.5 MHz to 12 MHz Unit
Min Max Min Max
TLHLL ALE Pulse Width 127 2TCLCL·40 ns
TAVLL Address Valid to ALE Low 43 TCLCL·40 ns
TLLAX1 Address Hold After ALE Low 48 TCLCL·35 ns
TLLlV ALE Low to Valid Instr in ns
8744H 183 4TCLCL·150
8044AH/8344AH 233 4TCLCL·100
TLLPL ALE Low to PSEN Low 58 TCLCL·25 ns
TPLPH PSEN Pulse Width
8744H 190 3TCLCL·60 ns
8044AH/8344AH 215 3TCLCL·35 ns
TPLIV PSEN Low to Valid Instr in
8744H 100 3TCLCL·150 ns
8044AH/8344AH 125 3TCLCL·125 ns
TPXIX Input Instr Hold After PSEN 0 0 ns
TPXIZ2 Input Instr Float After PSEN 63 TCLCL·20 ns
TPXAV2 PSEN to Address Valid 75 TCLCL·8 ns
TAVIV Address to Valid Instr in
8744H 267 5TCLCL·150 ns
8044AH/8344AH 302 5TCLCL·115 ns
TAZPL Address Float to PSEN -25 -25 ns
NOTES:
1. TLLAX for access to program memory is different from TLLAX for data memory.
2. Interfacing RUPI·44 devices with float times up to 75ns is permissible. This limited bus contention will not cause any
damage to Port 0 drivers.
15·17
8044AH/8344AH/8744H
EXTERNAL DATA MEMORY CHARACTERISTICS
Variable Clock
12 MHzOsc
Symbol Parameter 1/TCLCL = 3.5 MHz to 12 MHz Unit
Min Max Min Max
TRLRH RD Pulse Width 400 6TCLCL-100 ns
TWLWH. WR Pulse Width 400 6TCLCL-100 ns
TLLAX Address Hold after ALE 48 TCLCL-35 ns
TRLDV RD Low to Valid Data in 252 5TCLCL-165 ns
TRHDX Data Hold After RD 0 0 ns
TRHDZ Data Float After RD 97 2TCLCL-70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL-150 ns
TAVDV Address to Valid Data In 585 9TCLCL"165 ns
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL-50 3TLCLCL+50 ns
TAVWL Address to RD or WR Low 203 4TCLCL-130 ns
TQVWX Data Valid to WR Transi~ion
8744H 13 TCLCL-70 ns
8044AH/8344AH 23 TCLCL-60 ns
TOVWH Data Setup Before WR High 433 7TCLCL-150 ns
TWHOX Data Held After WR 33 TCLCL-50 ns
TRLAZ RD Low to Address Float 25 25 ns
TWHLH RD or WR High to ALE High
8744H 33 133 TCLCL-50 TCLCL+50 ns
8044AH/8344AH 43 123 TCLCL-40 TCLCL+50 ns
NOTE:
1. TLLAX for access to program memory is different from TLLAX for access data memory.
Serial Interface Characteristics
Symbol Parameter Min Max Unit
TDCY Data Clock 420 ns
TDCL Data Clock Low 180 ns
TDCH Data Clock High 100 ns
tTD Transmit Data Delay 140 ns
tOSS Data Setup Time 40 ns
tOHS Data Hold Time 40 ns
15-18
inter 8044AH/8344AH/8744H
WAVEFORMS
Memory Access
PROGRAM MEMORY READ CYCLE
~-------------------------------TCV--------------------------~
ALE
PSEN .}~---+---.-f--:-.j TPXAV
A7-AD INSTRIN
PORTO
ADDRESS ADDRESS A1S-AS ADDRESS A 1S-AS
PORT2 OR SFR-P2
231663-8
DATA MEMORY READ CYCLE
TWHlH
~------"""" 1+------ TllDV------------~
ALE
PSEN
TllWl
RD ----------------~r_------------, ~~-----_+TRlRH------------~.__- - - - - -
TllAX TRHDX
A7-AO DATA IN
PORTO
TRlAZ
ADDRESS ADDRESS A1S-AS OR SFR-P2
PORT2 OR SFR-P2
231663-9
DATA MEMORY WRITE CYCLE
TWHLH
ALE
----------------4-----------~ 14-----------TWLWH------~--~~_____
TOVWH TWHQX
PORTO DATA OUT
PORT2 ADDRESS A1S-A8 OR SFR-P2
231663-10
15-19
inter- 8044AH/8344AH/8744H
SERIAL 1/0 WAVEFORMS
SYNCHRONOUS DATA TRANSMISSION
1-------,-----.;..- TDCy-------,----!
- - - - " " " ' " " I-----TDCL--~ r-----~
SCLK
' - - _ _ _ _ _.J I+--~TDCH--~ "------
DATA
TTD
231663-11
SYNCHRONOUS DATA RECEPTION
1--------'TDCy-------!
- - - - - - - - , . I------,--TDCL - - - + l r------"""
SCLK
i+---TDCH - - + I
DATA
TDSS I-----'---TDHS-------+I
231663-12
15-20
intJ 8044AH/8344AH/8744H
=x
AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS
INPUT/OUTPUT
r------------------------------,
FLOAT
2.4
0.45
20
TEST POINTS
2.0)<=.
-"0.:::.8_ _ _ _ _......::0::::..;.8
231663-13
2.4
~
j >-----FLOAT-------<t.j
2 _ . 0_ _
U
2.0 2.4
M ~
AC testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic 231663-14
"1" and 0.8V for a Logic "0".
EXTERNAL CLOCK DRIVE XTAL2
TCHCl
1-------- T C l C l - - - - - - - l
231663-15
Variable Clock
Symbol Parameter Freq = 3.5 MHz to 12 MHz Unit
Min Max
TClCl Oscillator Period 83.3 285.7 ns
TCHCX High Time 20 TClCl-TClCX ns
TClCX low Time 20 TCI,.Cl-TCHCX ns
TClCH Rise Time 20 ns
TCHCl Fall Time 20 ns
15-21
intJ 8044AH/8344AH/8744H
CLOCK WAVEFORMS
INTERNAL
CLOCK I STATE 4
Pl1p2
I STATE 5
Pl1p2
STATE 6
~I~
I STATE 1
~I~
I~I~
STATE 2 I
~I~
STATE 3 I STATE 4
~I~
I STATE 5
~I~
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
::2.
,---=_.......1 1 ' "
I I'
THESE SIGNALS ARE NOT
ACTIVATED DURING THE
I
EXECUTION OF A MOVX INSTRUCTION
I
L.I__
L
PO
P2(EXT) _ _ _ _ .-II INDICATES ADDRESS TRANSIONSI L._ _ _ _ _ _ _ _ _ _.....
READ CYCLE
RD
OOH IS EMITTED PCL OUT (IF PROGRAM
DURING THIS PERIOD MEMORY IS EXTERNAL)
PO
DPL OR RI
OUT ~¢' FLOATSr=O .n~
P2 INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
WRITE CYCLE
WR L._ _ _ _ _ _ _ _ _ _..... I PCl OUT(EVEN IF PROGRAM
MEMORY IS INTERNAL)
!. ~I~OGRAM
DPL OR Ri
PO OUT
DATA OUT .$--;-;I tCl OUT
MEMORY IS EXTERNAL)
P2 INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
PORT OPERATION
MOV PORT, SRC I
OLD DATA NEW DATA
MOV DEST. PO ~."""-:-~
~. f-4t
______. . ; . . . - - - - - - - - - - - - - . . . . . J - L P O PINS SAMPLED
MOV DEST, PORT (P1, P2. P3) PO PINS SAMPLED
(INCLUDES INTO. INTI. TO. TI) ~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....,j~
Pl. P2, P3 PINS SAMPLED Pl. P2. P3
SERIAL PORT SHIFT CLOCK PINS SAMPLED
J~gDE O)---------"~XD SAMPLED L.--------~~AMPlED
231663-16
This diagram indicates when signals are clocked internally. The time ittakes the signals to propagate to the
pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as tempera-
ture and pin loading. Propagation also varies from output to output and component to component. Typically
though, (TA' = 25°C, fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals
are typically 85 ns. Propagation delays are incorporated in the AC specifications.
15-22
inter 8044AH/8344AH/8744H
8744H EPROM CHARACTERISTICS ure 8. Detailed timing specifications are provided in
the EPROM Programming and Verification Charac-
teristics section of this data sheet.
Erasure Characteristics
Erasure of the 8744H Program Memory begins to Program Memory Security
occur when the chip is exposed to light with wave-
lengths shorter than approximately 4,000 Ang- The program memory security feature is developed
stroms. Since sunlight and fluorescent lighting have around a "security bit" in the 8744H EPROM array.
wavelengths in this range, constant exposure to Once this "hidden bit" is programmed, electrical ac-
these light sources over an extended period of time cess to the contents of the entire program memory
(about 1 week in sunlight, or 3 years in room-level array becomes impossible. Activation of this feature
fluorescent lighting) could cause unintentional era- is accomplished by programming the 8744H as de-
sure. If an application subjects the 8744H to this scribed in "Programming the EPROM" with the ex-
type of exposure, it is suggested that an opaque la- ception that P2.6 is held at a TTL high rather than a
bel be placed over the window. TTL low. In addition, Port 1 and P2.0-P2.3 may be in
any state. Figure 9 illustrates the security bit pro-
The recommended erasure procedure is exposure gramming configuration. Deactivating the security
to ultraviolet light (at 2537 Angstroms) to an integrat- feature, which again allows programmability of the
ed dose of at least 15 W-secl cm 2 rating for 20 to 30 EPROM, is accomplished by exposing the EPROM
minutes, at a distance of about 1 inch, should be to ultraviolet light. This exposure, as described in
sufficient. "Erasure Characteristics," erases the entire EPROM
array. Therefore, attempted retrieval of "protected
Erasure leaves the array in an all 1s state. code" results in its destruction.
Programming the EPROM Program Verification
To be programmed, the 8744H must be running with Program Memory may be read only when the "secu-
a 4 to 6 MHz oscillator. (The reason the oscillator rity feature" has not been activated. Refer to Figure
needs to be running is that the internal bus is being 10 for Program Verification setup. To read the Pro-
used to transfer address and program data to appro- gram Memory, the following procedure can be used.
priate registers.) The address of an EPROM location The unit must be running with a 4 to 6 MHz oscilla-
to be programmed is applied to Port 1 and pins P2.0- tor. The address of a Program Memory location to
P2.3 of Port 2, while the data byte is applied to Port be read is applied to Port 1 and pins P2.0-P2.3 of
O. Pins P2.4-P2.6 and PSEN should be held low, and Port 2. Pins P2.4-P2.6 and PSEN are held at TTL
P2.7 and RST high. (These are all TTL levels except low, while the ALE/PROG, RST, and EAIVPP pins
RST, which requires 2.5V for high.) EAIVPP is held are held at TTL high. (These are all TTL levels ex-
normally high, and is pulsed to +21V. While EAI cept RST, which requires 2.5V for high.) Port 0 will
VPP is at 21V, the ALE/PROG pin, which is normally be the data output lines. P2.7 can be used as a read
being held high, is pulsed low for 50 msec. Then strobe. While P2.7 is held high, the Port 0 pins float.
EAIVPP is returned to high. This is illustrated in Fig- When P2.7 is strobed low, the contents of the ad-
dressed location will appear at Port O. External pull-
ups (e.g., 10K) are required on Port 0 during program
verification.
15-23
intJ 8044AH/8344AH/8744H
+5V
ADDA. - - . . . - -...............1 Vee
PI
OOOOH- 8744H
OFFFH
P2.0- PO PGM DATA
P2.3
P2.4
P2.5 ALE - - ALE PFiOG
P2.6
P2.7
XTAL2 Eli --!A/VPP
XTALI AST VIHI
Vss PSEN
- 231663-17
Figure 8. Programming Configuration
+5V
Vee
He PI
8744H
P2.0- PO Ne
He P2.3
P2.4
P2.5 ALE _ _ _ ALE/PAOG 50 ms PULSE TO GND
P2.6
TTL HIGH P2.7
XTAL2 EA - - EII/VPP +21V PULSE
XTALI RST VIHI
VSS Prni
- 231663-18
Figure 9. Security Bit Programming Configuration
15-24
8044AH/8344AH/8744H
+SV
ADD R. -----,;-:--c.-:-'\l Vee
P1
OOOOH-
8744H
OFFFH t----~ PGM DATA
P2.0- PO (USE 10K PULLUPS)
P2.3
P2.4
P2.S
A~ TTTLH'GH
P2.6
ENABLE - - - - - I P2.7 EA
XTAL2 RST VIH1
XTAL1
VSS =
231663-19
Figure 10. Program Verification Configuration
EPROM PROGRAMMING, SECURITY BIT PROGRAMMING
AND VERIFICATION CHARACTERISTICS
TA = 21°C to 27~C, Vee = 4.5V to 5.5V, vss = ov
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 20.5 21.5 V
IPP Programming Current 30 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG 48TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG 48TCLCL
TGHDX Data Hold after PROG 48TCLCL
TEHSH ENABLE High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG 10 p.see
TGHSL Vpp Hold after PROG 10 p.see
TGLGH PROGWidth 45 55 msec
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE 0 48TCLCL
15-25
8044AH/8344AH/8744H
EPROM PROGRAMMING, SECURITY BIT PROGRAMMING
AND VERIFICATION WAVEFORMS
PROGRAMMING VERIFICATION
P1.0-P1.7
P2.0-PU ADDRESS ADDRESS "-
/
--
TAVOV
PORTO DATA IN DATA OUT
TDVGL -
TGHDX
TAVGL --
TGHAX
ALEPiffiG \
TSHGL "---...! ~
TGi:GH
21V ..SV
\
TT
~ TTL HIGH TTL HIGH TTL HIGH
D:vpp
___ )~
--
TEHSH
_ TELOV _ TEHOZ
P1.7)-_1
(ENAiiLE) i~ ..,J,
231663-20
15-26
inter APPLICATION
NOTE
AP-283
September 1986
Flexibility in Frame Size with the
8044
PARVIZ KHODADADI
APPLICATIONS ENGINEER
Order Number: 292019-001
15-27
FLEXIBILITY IN FRAME SIZE WITH THE 8044
1.0 INTRODUCTION suIDes that the reader is familiar with the 8044 data
sheet and the SDLC communications protocol.
The 8044 is a serial communication microcontroller
known as the RUPI (Remote Universal Peripheral In-
terface). It merges the popular 8051 8-bit microcontrol- 1.1 Normal Operation
ler with an intelligent, high performance HDLC/SDLC
serial communication controller called the Serial Inter- In Normal operation the on-chip CPU and the SIU
face Unit (SID). The chip provides all features of the operate in parallel. The SIU handles the serial commu-
microcontroller and supports the Synchronous Data nication task while the CPU processes the contents of
Link Control (SDLC) communications protocol. the on-chip transmit and receiver buffer,. services in~er
rupt routines, or performs the local real time processmg
There are two methods of operation relating to frame tasks.
size:
The 192 bytes of on-chip RAM serves as the interface
1) Normal operation (limited frame size) buffer between the CPU and the SIU, used by both as a
2) Expanded operation (unlimited frame size) receive and transmit buffer. Some of the internal RAM
space is used as general purpose registers (e.g. RO-R7).
In Normal operation the internal 192 byte RAM is . The remaining bytes may be divided into at least two
used as the receive and transmit buffer. In this opera- sections: one section for the transmit buffer and the
tion, the chip supports data rates up to 2.4 Mbps exter- other section for the receive buffer. In some applica-
nally clocked and 375 Kbps self-clocked. For frame tions, the 192 byte internal RAM size imposes a limita-
sizes greater than 192 bytes, Expanded operation is re- tion on the size of the information field of each frame,
quired. In Expanded operation the external RAM, in and, consequently, achieves less than optimal informa-
conjunction with the internal RAM, is used as the tion throughput.
transmit and receive buffer. In this operation, the chip
supports data rates up to 500 Kbps externally clocked Figure 1 illustrates the flow of data when internal
and 375 Kbps self-clocked. In both cases, the SIU han- RAM is used as the receive and transmit buffer. The
dles many of the data link functions in hardware, and on-chip CPU allocates a receive buffer in the internal
the chip can be configured in either Auto or Flexible RAM and enables the SIU. A receiving SDLC frame is
mode.
processed by the SIU and the information bytes of the
frame, if any, are stored in the internal RAM. Th~n,
The discussion that follows describes the operation of
the sm informs the CPU of the received bytes (Senal
the chip and the behavior of the serial interface unit. Channel interrupt). For transmission, the CPU loads
Both Normal and Expanded operations will be further· the transmitting bytes into the internal RAM and en-
explained with extra emphasis on Expanded operation
ables the SIU. The SIU transmits the information bytes
and its supporting software. Two examples of SDLC in SDLC format. '
communication systems will also be covered, where the
chip is used in Expanded operation. The discussion as-
----
TR~~;~~~ I F III
A C
---- I FCS1 I FCS2 II
F
SPECIAL ~UNCTION
REGjERS
OBFH
(
TRAJSMIT
BU1ER
..11. t
RECEIVE
v
/' BUFFER
t
t
GENERAL PURPOSE
-", - I FCS1 I FCS21 F I REGISTERS
t
---- INTERNAL RAM
OOH
, 292019-1
Figure 1. Transmission/Reception Data Flow Using Internal RAM
15-28
FLEXIBILITY IN FRAME SIZE WITH THE 8044
I rCSl I rCS2 I r I 16 •4K
RECEIVE I
I rCSl I rCS2 I r I i..._ _ _ _ _....J OOH
INTERNAL RAM
u~ EXTERNAL RAM
292019-2
Figure 2. Transmission/Reception Data Flow Using External RAM
1.2 Expanded Operation features of the 8044 which are necessary to further ex-
plain expanded operation.
In Expanded operation the on-chip CPU monitors the
state of the SIU, and moves data from/to external buff-
er to/from the internal RAM and registers while recep- 2.0 THE SERIAL INTERFACE UNIT
tion/transmission is taking place. If the CPU must
service an interrupt during transmission or reception of
a frame or transmit from internal RAM, the chip can 2.1 Hardware Description
shift to Normal 0l'eration.
The Serial Interface Unit (SIU) of the RUPI, shown in
There is a special function register called SIUST, the Figure 3, is divided functionally into a Bit Processor
contents of which dictate the operation of the SIU. (BIP) and a Byte Processor (BYP), each sharing some
Also, at data rates lower than 2.4 Mbps, one section of common timing and control logic. The bit processor is
the SIU, in fixed intervals during transmission and re- the interface between the SIU bus and the serial port
ception, is in the "standby" mode and performs no pins. It performs all functions necessary to transmit/re-
function. The above two characteristics make it possi- ceive a byte of data to/from the serial data line (shift-
ble to program the CPU to move data to/from external ing, NRZI coding, zero insertion/deletion, etc.). The
RAM and to force the SIU to repeat or skip some de- byte processor manipulates bytes of data to perform
sired hardware tasks while transmission or reception is message formatting, transmitting, and receiving func-
taking place. With these modifications, external .RAM tions. For example, moving bytes from/to the special
can be utilized as a transmit and receive buffer instead function registers to/from the bit processor.
of the internal RAM.
The byte processor is controlled by a Finite-State Ma-
Figure 2 graphically shows the flow of data when exter- chine (FSM). For every receiving/transmitting byte,
nal RAM is used. For reception, the receiving bytes are the byte processor executes one state. It then jumps to
loaded into the Receive Control Byte (RCB) register. the next state or repeats the same state. These states
Then, the data in RCB is moved to external RAM and will be explained in section 3. The status of the FSM is
the SIU is forced to load the next byte into the RCB kept in an 8-bit register called SIUST (SIU State Coun-
register - The chip believes it is receiving a control byte ter). This register is used to manipulate the behavior of
continuously. For transmission, Information bytes (1- the byte processor.
bytes) are loaded into a location in the internal RAM
and the chip is forced to transmit the contents of this As the name implies, the bit processor processes data
location repeatedly. one bit at a time. The speed of the bit processor is a
function of the serial channel data rate. When one byte
Discussion of expanded operation is continued in sec- of data is processed by the bit processor, a byte bounda-
tions 4 and 5. First, however, sections 2 and 3 describe
15-29
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
ry is reached. Each time a byte boundary is detected in block of data into the shift register. The serial data is
the serial data stream, a burst of clock cycles (16 CPU also shifted; through SR, to a l6-bit register called
states) is generated for the byte processor to execute "FCS GEN/CHK" for CRC checking. The byte proc-
one state of the state machine. When all the procedures essor takes the received address and control bytes from
in the state are executed, a wait signal is asserted to the SR shift register and moves them to the appropriate
terminate the burst, and the byte processor waits for· registers. If the contents of the shift register is expected
the next byte boundary (standby mode). The lower the to be an information byte, the byte processor moves
data rate, the longer the byte processor will stay in the them through a 3-byte FIFO to the internal RAM at a
standby mode. starting location addressed by the contents of the Re-
ceive Buffer Start (RBS) register.
2.2 Reception of Frames
2.3 Transmission of Frames
Incoming data is NRZI decoded by the on-chip decod-
er. It is then passed through the zero insertion/deletion In the transmit mode, the byte processor relinquishes a
(ZID) circuitry. The ZID not only performs zero inser- byte to the bit processor by moving it to a register
tion/deletion, but also detects flags and Go Aheads called RB (RAM buffer). The bit processor converts
(GA) in the data stream. The data bits are then loaded the data to serial form through the shift register, per-
into the shift register (SR) which performs serial to par- forms zero bit insertion, NRZI encoding, and sends the
allel conversion. When 8 bits of data are collected in the data to the serial port for transmission. Finally, the
shift register, the bit processor triggers the byte proces- contents of the FCS GEN/CHK and the closing flag
sor to process the byte, and it proceeds to load the next are routed to the serial port for transmission.
PH2
. - TIMER j
OVERFLOW
SClR
SPECIAL
FUNCTION
REGISTERS:
STAD TBl DUAL
RCB TCB PORT
RBl BCNT . RAM
RBS FIFOO
RFl FIF01 CONTROL <'
TBS 'FIF02 SIGNALS,
lB·
292019-3
Figure 3. SIU Block Diagram
15-30
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
3.0 TRANSMIT AND RECEIVE of the information field are pushed into the 3-byte
FIFO (FIFOO, FIF01, FIF02) and the Receive Field
STATES Length register (RFL) is set to zero. The 3-byte FIFO
The simplified receive and transmit state diagrams are is used as a pipeline to move received bytes into the
shown in Figures 4 and 5, respectively. The numbers on internal RAM. The FIFO prevents transfer of CRC
the left of each state represent the contents of the bytes and the closing flag to the receive buffer (i.e.,
SIUST register when the byte processor is in the stand- when the ending flag is received, the contents of FIFO
by mode, and the instructions on the right of each state are FLAG, FCS1, and FCSO.) The three byte FIFO is
represent the "state procedures" of that state. When the collapsed to one byte in No FCS mode.
byte processor executes these procedures the least three
significant bits of the SIUST register are being incre- In the DMA-LOOP state the byte processor pushes a
mented while the other bits remain unchanged. The byte from SR to FIFOO; moves the contents of FIF02
byte processor will jump from one state to another to the hiternal RAM addressed by the contents of
without going into the standby mode when a condition- SRAR, increments the SRAR and RFL registers, and
al jump procedure executed by the byte processor is decrements the DCNT register. If more information
true. - bytes are expected, the byte processor repeats this state
on the next byte boundaries until DMA Buffer End
occurs. The DMA Buffer End occurs if SRAR reaches
. 3.1 Receive State Sequence OBFH (192 decimal), DCNT reaches zero, or the RBP
bit of the STS register is set.
When an opening flag (7EH) is detected by the bit
processor, the byte processor is triggered to execute the The BOY-LOOP state, the last state, is executed if
procedures of the FLAG state. In the FLAG state, the there is a buffer overrun. Buffer overrun occurs when
byte processor loads the contents of the RBS register the number of information bytes received is larger than
into the Special RAM (SRAR) register. SRAR is the the length of the receive buffer (RFL > RBL). This
pointer to the internal RAM. The byte processor decre- state is executed until the closing flag is received.
ments the contents of the Receive Buffer Length (RBL)
register and loads them into the DMA Count (DCNT) At the end of reception, if the FCS option is used, the
register. The FCS GEN/CHK circuit is turned on to closing flag and the FCSbytes will remain in the 3-byte
monitor the serial data stream for Frame Check Se- FIFO. The contents of the RCB register are used to
querice functions as per SDLC specifications. update the NSNR (Receive/Send Count) register. The
SIU updates the STS register and sets the serial inter-
Assuming there is an address field in the frame, con- rupt.
tents of the SIUST register will then be. changed to
OSH, causing the byte processor to jump to the AD-
DRESS stl;lte ,and wait (standby) for the next byte 3.2 Transmit State Sequence
boundary. As soon as the bit processor moves the ad-
dress byte into the SR shift register, a byte boundary is Setting the RTS bit puts the SIU in the transmit mode ..
achieved and the byte processor is triggered to execute When the CTS pin goes active, the byte processor goes
the procedures in the ADDRESS state. into START-XMIT state. In this state the opening flag
is moved into the RAM Buffer (RB) register. The byte
In the ADDRESS state the received station address is processor jumps to the next state and goes into the
compared to the contents of the STAD register. If there standby mode.
is no match, or the address is not the broadcast address
(FFH), reception will be aborted (SIUST = 0IH). Oth- If the Pre-Frame Sync (PFS) option is selected, the
erwise, the byte processor jumps to the CONTROL PFSI and PFS2 states will be executed to transmit the
state (SIUST = lOH) and goes into standby mode. two Pre-Frame Sync bytes (OOH or 55H). In these two
states the contents of the Pre-Frame Sync generator are
The byte processor jumps to the CONTROL state if sent to the serial port while the Zero Insertion Circuit
there exists a control field in the receiving frame. In (ZID) is turned off. ZID is turned back on automatical-
this state the control byte is moved to the RCB register lyon the next byte boundary.
by the byte processor. Note that the only action taken
in this state is that a received byte, processed by the bit If the PFS option is not chosen, the byte processor
processor, is moved to RCB. There is no other hard- jumps to the FLAG state. In this state, the byte proces-
ware task performed, and DCNT and SRAR are not sor moves the contents of TBS into the SRAR register,
affected in this state. decrements TBL and moves the contents into the
DCNT register. The byte 'processor turns off the ZID
The next two states'-PUSH-I and PUSH-2, will be exe- and turns on FCS GEN/CHK. The contents of FCS
cuted if Frame check sequence (NFCS = 0) option is GEN/CHK are not transmitted unless the NFCS bit is
selected. In these two states the first and second bytes
15-31
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
SIUST STATE STATE PROCEDURE
01H ( FLAG J 01-1)
01-2)
(RBS)-SRAR
(RBL)-I-(DCNT)
01-3) TURN ON FCS GEN/CHK
0104) IF POINT TO POINT MODE.
GOTO 10-2
OBH' ( ADDRESS ) OB-l) SR-TMP
OB-2) (STAD)-RB
OB-3) IF RB.NE.TMP AND
FFH.NE.TMP THEI\I IDLE
08-4) IF NB=1 GOTO 10-2
10H ( CONTROL ) 10-1) SR-(RCB)
10-2) IF NFCS=1 GOTO 20-3
~,
lBH ( PUSH-l ) 18-1) SR-(FIFOO)
18-2) PUSH
~
20H ( PUSH-2 ) 20-1) SR-(FIFOO)
20-2) PUSH
20-2) (RFL)-OOH
20-4) IF DMA BUFFER END.
GOTO 28-7
20-5) (RCB)-RB
2BH ( DMA-LODP ) 28-1) IF END OF I-FIELD.
THEN IDLE
28-2) (FIF02)-@SRAR
28-3) SR- (FIFOO)
28-4) INC. SRAR
28-5) PUSH
2B-6) DEC; (DCNT)
2B-7) INC. (RfL)
2B-8) IF NOT DMA BUFFER END.
GOTO 2B-l
28-9) RCB)- RB
30H ( BOY-LOOP ) 30-1) SET BOY BIT (SRS.3)
30-2) (RCB)- RB
30-3) IF NOT END OF I-FIELD.
GOTO 30-1
30-4) IDLE
292019-4
Figure 4. Receive State Diagram
set. If a frame with the address field is chosen. it moves byte' boundaries until all the information bytes are
the contents of the STAD register into the RB register transmitted. '
for transmission. At the same time. the opening flag is
being transmitted by the bit processor. The FCSI and the FCS2 states are executed to transmit
the Frame Check Sequence bytes generated by the FCS
In the ADDRESS (SIUST = AOH) and CONTROL generator, and the END-FLAG state is executed to
(SIUST = ASH) states, TCB and the first information transmit the closing flag.
byte are loaded into the RB register for transmission,
respectively. Note that in the CONTROL state, none of The XMIT-ACTION and the ABORT-ACTION
the registers (e.g. DCNT, SRAR) are incremented, and states are executed by the byte processor to synchronize
ZID and FCS GEN/CHK are not turned on or off. the SIU with the CPU clock. The XMIT"ACTION or
the ABORT-ACTION state is repeated until the byte
The procedures in the DMA·LOOP state are similar to processor status is updated. At the end, the STS and the
the procedures of the DMA·LOOP in the receive state TMOD registers are updated.
diagram. The SRAR register pointer to the internal
RAM is incremented, and the DCNT register is decre- The two ABORT-SEQUENCE states (SIUST = EOH
mented. The contents of DCNT reach'zero when all the and SIUST = ESH) are executed only if transmission
information bytes froni the transmit buffer are trans- is aborted by the CPU (RTS or TBF bit of the STS
mitted. A byte from RAM is moved to the RB register register is cleared) or by the serial data link (CTS signal
for transmission. This state is executed on the following goes inactive or shut-off occurs in loop mode.)
15-32
FLEXIBILITY IN FRAME SIZE WITH THE 8044
SIUST STATE STATE PROCEDURE
87H B7-1) FLAG-- RB
J
88H B8-1) IF NO PFS (SMD.2=0).
GOTO 98-1
'B8-2) XMIT A PFS BYTE
BB-3) ZID OFF
90H ( PFS2 ) 90-1) XMIT A PFS BYTE
90-2) ZID OFF
98H
I
FLAG 9B-1) (TBS)--SRAR
98-2) ZID OFF
9B-3) (TBL)-I-- (DCNT)
98-4) TURN ON ,CS GEN/CHK
98-5) IF POINT TO POINT MODE.
GOTO A8-1
98-6) (STAD)-- RB
AOH AO-l) IF NB=1 GOTO A8-1
AO-2) IF AUTO MODE
CTRL--RB
AO-3) IF FLEXIBLE MODE
(TCB)--RB
A8H A8-1) IF DMA BUFFER END.
GOTO BO-3
A8-2) @SRAR--RB
BOH BO-1) INC. SRAR
BO-2) DEC. DCNT
BO-3) IF DMA BUFFER END
AND NFCS=I.
GOTO,CO-l
BO-4) @SRAR--RB
BO-5) GOTO BO-l
BBH BB-l) NO ACTION
COH
CBH CB-1) ZID OFF
DOH 00-1) REPEAT THIS STATE TILL SIU
IS IN SYNC. WITH CPU. THEN
IDLE. ZID OFF
EOH EO-1) NO ACTION
EBH EB-l) ZID OFF
FOH ,0-1 ) REPEAT ni IS STATE TILL SIU
IS IN SYNC. WITH CPU. THEN
IDLE. ZID OFF
292019-6
Figure 5. Transmit State Diagram
15-33
intJ FLEXIBILITY IN FRAME SIZE WITH THE 8044
4.0 TRANSMISSION/RECEPTION OF 4.2 SIU Registers
LONG FRAMES (EXPANDED·
OPERATION) . To write into the SIUST register, the data must be com-
plemented. For example, if you intend to write 18H
In this application note, a frame whose information into the SIUST register, you should write E7H to the
field is more than 192 bytes (size of on~chip RAM) is register. The data read from SIUST is, however, true
referred to as a long frame. The 8044 can access up to data (i.e. 18H).
64000 bytes of external RAM. Therefore, a long frame
can have up to 64000 information bytes. Read and write accesses to the SIUST, STAD, DCNT,
RCB, RBL;· RFL, TCB, TBL, TBS, and the 3-byte
FIFO registers are done on even and odd phases, re-
4.1 Description spectively. Therefore, there is no bus contention when
the CPU is monitoring the registers (e.g. SIUST), and
During transmission or reception of a frame, while the SIU is simultaneously writing into them.
bit processor is processing a byte, the byte processor,
after 16 CPU states, is in the standby mode, and the There is no need to change or reset the contents of any
internal registers and the internal bus are not used .. The SIU register while transmitting or receiving long
period between each byte boundary, when the byte frames, unless the. byte processor is forced to repeat a
processor is in the standby mode, can be used to move state in which the contents of theSe registers are modi-
data from external RAM to one of the byte processor fied. Note that the SRAR register can not be accessed
. registers for transmission and vice versa for receptioll. by the CPU; therefore, avoid repeating the DMA-
The contents of the SIUST register, which dictate the LOOP states. If SRAR increments to 192, the SIU will
state of the byte processor, can be monitored to recog- be interrupted and communication will be aborted.
nize the beginning of each SDLC field and the consecu-
tive byte boundaries.
4.3 Other Possibilities
By writing into the SIUST register, the byte processor
can be forced to repeat or skip a specific state. As an The internal RAM, in conjunction with an external
example, the SIU can be forced to repeatedly put the buffer (RAM orFIFOs), can be used as a transmit and
received bytes into the RCB register. This is. accom-· receive buffer. In other words, Expanded and Normal
plished by writing E7H into the SIUST register when operation can be used together. For example, if a frame
the byte processor goes into the standby mode. The with 300 Information bytes is received and only 255 of
byte processor, therefore, executes the CONTROL them are moved to an external buffer, the remaining
state at the next byte boundary. bytes (45 bytes) will be loaded into the internal RAM
by the SIU (assuming RBL is set to 45 or more).· The
For transmission, the byte processor is put in the trans- contents of RFL indicate the number of bytes stored in
mit mode. When transmission of a frame is initiated, the internal RAM. For transmission, the contents of
the user program calls a subroutine in which the state the external buffer can be transmitted followed by the
of the byte processor is monitored by checking the con- contents of the internal buffer.
tents of the SIUST register. When the byte processor
reaches a desired state and goes into standby, the CPU If the internal RAM is not used, contents of the RBL
loads the first byte of the internal RAM buffer with register can be 0 and contents of the TBL register must
data and moves the byte processor to the CONTROL be set to 1. The contents of the TBS register can be any
state. The routine is repeated for every byte. At the end, location in the internal RAM.
the program returns from the subroutine, and the SIU
finishes its task (see application examples). The transmission and reception procedures for long
frames with no FCS are similar to those with FCS. The
For reception, a software routine is executed to move exception is the contents of the SIUST register should
data to external RAM and to force the SIU to repeat be compared with· different values since the two FCS
the CONTROL state. The CONTROL state is repeated states of the transmit and receive flow charts are
because, as shown in the receive state diagram, the only skipped by the byte processor.
action taken by the byte processor, in the CONTROL
state, is to move the contents ofSR to the RCB register. If a frame format with no control byte is chosen, a
None of the registers (e.g. SRAR and DCNT) are in- location in the RAM addressed by TBS should be used
cremented. A similar comment justifies the use of the for transmission as with control byte format. The FIFO
CONTROL state for transmission. In the transmit can be used for reception. The STAD register can be
CONTROL state, contents of a location in the on-chip used for transmission if no zerq insertion is required.
RAM addressed by TBS is moved to RB for transmis-
sion.
15-34
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
If the RUPI is used in Auto mode (see Section 5), it 4.4 Maximum Data Rate in Expanded
will still respond to RR, RNR, REJ, and Unnumbered
Poll (UP) SDLC commands with RR or RNR auto-
Operation
matically, without using any transmit routine. For ex- Assuming there is no zero-insertion/deletion, the bit
.ample, if the on-chip CPU is busy performing some real processor requires eight serial clock periods to process
time operations, the SIU can transmit an information one block of data. The byte processor, running on the
frame from the internal buffer or transmit a supervisory CPU clock, processes one byte of data in 16 CPU states
frame without the help of CPU (Normal operation). (one state of the state diagrams). Each CPU state is two
oscillator periods. At an oscillator frequency of
Maximum data rate using this feature is limited primar- 12 MHz, the CPU clock is 6 MHz, and 16 CPU states
ily by the number of instructions needed to be executed is 2.7 /J-s. At a 3 Mbit rate with no zero-insertion/dele-
during the standby mode. tion, there is exactly enough time to execute one state
per byte (16 states at 6 MHz = 8 bits at 3M baud). In
Transmission or reception of a frame can be timed out other words, the standby time is zero.
so that the CPU will not hang up in the transmit or
receive procedures if a frame is aborted. Or, if the data Figure 6 demonstrates portions of the timing relation-
rate allows enough time (standby time is long enough), ship between the byte processor and the bit processor.
the CPU can monitor the SIUST register for idle mode In each state, the actions taken by the processors, plus
(SIUST = OIH). the contents of the SIUST register, are shown. When
the byte processor is running, the contents of SIUST
It is also possible to transmit multiple opening or clos- are unknown. However, when it is in the standby mode,
ing flags by forcing the byte processor to repeat the its contents are determinable.
END-FLAG state.
The maximum data rate for transmitting and receiving
long frames depends on the number of instructions
needed to be executed during standby, and is propor-
STATE: ADDRESS X CONTROL X PUSH-l X PUSH-2
BIP:
:J<
CRTL BYTE - SR
X 1st I-BYTE - SR X 2nd I-BYTE -.- SR
K:
BYP: :J<SR-TMPX STANDBY
X
SR~ RCB X STANDBY X SR - FIFOO ~
SIUST: ? 10H ? 18H ? 20H
292019-7
Sa. Reception
~______~CO_N_T_RO_L______~X~______
STATE: FLAG
X ADDRESS·
X
BIP: : J <_ _X_M_ITI_I_NG_FL_A_G_-,X",_ _X_M_ITI_IN_G_A_D_RS_BYT_E_ _-,X",_.;..XM_I_TI_IN_G_C_R_T_L_BYT_E_ _ K:
BYP: :J<STAD-RBX STANDBY X TCB - - RB X STANDBY X @SRAR - RB ~
SIUST: ? AOH ? AS H ? BOH
292019-8
Sb. Transmission
Figure S. Portions of the BIP/BVP Timing Relationship
15-35
FLEXIBILITY IN FRAME SIZE WITH THE 8044
tional to the oscillator frequency. The time the byte 5.2 Auto Mode
processor is in the standby mode, waiting for the bit
processor to deliver a processed byte, is at least equal to In the Auto mode, the 8044 can only be a secondary
eight serial clock periods minus 16 CPU states. If an station operating in the SOLC "Normal Response
inserted zero is in the block of data, the bit processor Mode". The 8044 in Auto mode does not transmit mes-
will process the byte in nine serial clock periods. sages unless it is polled by the primary.
The equation for theoretical maximum data rate is giv- For transmission of an information frame, the CPU al-
en as: locates space for the transmit buffer, loads the buffer
with data, and sets the TBF bit. The SIU will transmit
(2TCLCL) x (16 states) + (iI' of instruction cycles) x the frame when it receives a valid poll-frame. A frame
. (12TCLCL) = (BTOCy) Equation (1) whose poll bit of the control byte is set, is a poll-frame.
The poll bit causes the RTS bit to be set. If TBF were
Where: TCLCL is the oscillator period. not set, the SIU would respond with Receive Not
TOCY is the serial clock period. Ready (RNR) SOLC command if RBP = 1, or with
Receive Ready (RR) SOLC command if RBP = O.
At an oscillator frequency of 12 MHz and baud rate of After transmission RTS is cleared, and· the CPU is not
375 Kbps, about 18 instruction cycles can be executed interrupted.
when the byte processor is in the standby mode. At a
9600 baud rate, there is time to execute about 830 in- For reception, the procedure is the same as that of
struction cycles-plenty of time to service a long inter- Flexible mode. In addition, the SIU sets the RTS bit if
rupt routine or perform bit-manipulation or arithmetic the received frame is a poll-frame (causing an automat-
operations on the data while transmission or reception ic response) and increments the NS and NR counts
is taking place. accordingly.
5.0 MODES OF OPERATION 6.0 APPLICATION EXAMPLES
The 8044 has two modes: Flexible mode and Auto Two application examples are given to provide addi-
mode. In Auto mode, the chip responds to many SOLC tional details about the procedures used to transmit and
commands and keeps track of frame sequence number- receive long frames. In the first application example,
ing automatically without on-chip CPU intervention. procedures to construct receive and transmit software
In Flexible mode, communication tasks are under con- routines for the point-to-point frame format are de-
trol of the on-chip CPU. scribed. The point-to-point frame has the information
field and the FCS field enclosed between two flags (see
Figure 7). In the second example software code is gen-
5.1 Flexible Mode erated for reception and transmission of the standard
SOLC frame. The SOLC frame has the pattern: flag,
For transmission, the CPU allocates space for transmit address, control, information, FCS, flag ..
buffer by storing values for the starting location and
size of the transmit buffer in the TBS and the TBL
The first example focuses on the construction of trans-
registers. It loads the buffer with data, sets the TBF and mit and receive code which allow the chip to transmit
the RTS bits in the STS register, and proceeds to per-
and receive long frames. The second example shows
form other tasks. The SIU activates the RTS line.
how to make more use of the 8044 features, such as the
When the CTS signal goes active, the SIU transmits the
on-chip phase locked loop for clock recovery and.8uto-
frame. At the end of transmission, the SIU clears the
matic responses in the Auto mode to demonstrate the
RTS bit and interrupts the CPU (SI set).
capability of the 8044 to achieve high throughput when
Expanded operation is used.
For reception, the CPU allocates space for receive buff-
er by loading the beginning address and length of the
receive buffer into the RBS and RBL registers, sets the
RBE bit, and proceeds to perform other tasks. The 6.1 Point-to-Point Application
SIU, upon detection of an opening flag, checks the next Example
received byte. If it matches the station address,· it will
A point-to-point communication system was developed
load the received control byte into RCB, and received
to receive and transmit long frames. The system con-
information bytes into the receive buffer. At the end of
sists of one primary and one secondary station. Al-
reception, if the Frame Check Sequence (FCS) is cor-
though multiple secondary stations can be used in this
rect, the SIU clears RBE and interrupts the CPU.
15-36
infef FLEXIBILITY IN FRAME SIZE WITH THE 8044
~
FLAG F-I BYTE-FCS-F
ADDRESS BYTE
1
.~
INFORMATION
BYTES .~
1 CONTROL BYTE
INFORMATION
PRIMARY
F-255 I BYTES-FCS-F
SECONDARY
BYTES 292019-10
Figure 8. Secondary Responses to Primary
FRAME CHECK FRAME CHECK
SEQUENCE SEQUENCE Station Commands
FLAG FLAG
Point-to-Point Standard SDLe
292019-9
Figure 7. Point-to-Point and Standard SOLe
Frame Formats
system, one secondary is chosen to simplify the primary (DATA) being connected to pin 14 (TO). In the pri-
station's software and focus on the long frame software mary station, the 8044 is "interrupted when activity is
code. Both the primary and the secondary stations are detected on the communication line by the on-chip tim-
in Flexible mode and the external clock option is used er. (in counter mode). This is explained more later. The
for the serial channel. The maximum data rate is serial clock to both stations is supplied by a pulse gen-
500 Kbps. The FCS bytes are generated and checked erator. The output of the pulse generator (not shown in
automatically by both stations. the diagram) is connected to pin 15 of the 8044s. Since
the two stations are located near each other (le~s than 4
feet), line drivers are not used.
6.1.1 POLLING SEQUENCE
The polling sequence, shown in Figure 8, takes place The central processor of each station is the 8044. The
continuously between the primary and the secondary data link program is stored in. a 2Kx8 EPROM
stations. The primary transmits a frame with one infor- (2732A), and a 2Kx8 static RAM (AM9128) is used as
mation byte to the secondary. The information byte is the external transmit and receive buffer. The RTS pin is
used by the secondary as an address byte. The second- connected to the CTS pin. For simplicity, the stations
ary checks the received byte, and if the address are assumed to be in the SDLC Normal Respond Mode
matches, the secondary responds with a long frame. In after Hardware reset.
this example, the information field of the frame is cho-
sen to be 255 bytes long. Since there is only one second- 6.1.3 PRIMARY STATION SOFTWARE
ary station, the address always matches. Upon success-
ful reception of the long frame, the primary transmits .The assembly code for the primary station software is
another frame to the secondary ~tation. listed in Appendix A. The primary software consists of
the main routine, the SIU interrupt routine, and the
receive interrupt routine. The receive interrupt routine
6.1.2 HARDWARE is executed when a long frame is being received.
The schematic of the secondary station is given in Fig-
ure 9. The circuit of the primary station is identical to In the flow charts that follow, all actions taken by the
the secondary station with the exception of pin 11 SIU appear in squares, and actions taken by the on-chip
CPU appear in spheres.
15-37
j "' ~!'::1-<iI,;~" 1 --l ~
~".~
I
~
~,
ADO-7
~ '~ •..
I
l
,~ ~ OO,,~
,;.. "' "00
~ ~"
AM9128
10pF I ---,
828L....., 19 AO Al 7 Al 01 '11 02
1
SWI "' , 5 00 00 ,.. ""'" " '"
~
~---J.
tl ~400 1'
- '
~'''' ~ "~,,.
,.Xl
I" I"
'"""i91
- '."
"'''
A01, -- 02
"
02
~.
.;. '"
3 012
00'"
002. 1 "6 A3
;;: "
A4
~
'"
4 A4
",,~
04 15
"
OS
.,,~,/- oo~
M. '" "" " M .. '..
R2 .!. '" " " . " " 00. " " .. '.. "" 00
~ ~
- -",,, '" "" '" M " '., " "11
[= -'"'' ""'; '" """ ., .. ,,- .. J;;
I .. " .. ><
~
. -'" 00 00 '" ""
'"
c"
t: A07, OE 1 Al0 19 Al0
6i
F
iiJ '\7 r 2-!.o WE
~
.
11 STB
~, " .s - . ',j, "
!O
g»
() N/C --;s WR'
17
RO I 29 -'1 ~" " L _J
Z
"11
~,
o:::I . 14 TO V
::a
..... Q. . !.,. "'" .. -. m,. ~
~
------ lll1J",,, " , --, • 00 5:
"~"",
(J1 DI
Cu
00
<UI In
en
1
~"" .~""
00 '.. "
a
0"
...---
,..L,
-. ", " ..
'" _"
M ,
'.. "00,,,,,
'" " N
In
:::I.
:J:
.L "', "'" '., :e:::::j
DI "'" v "'J '.. " '.. '" ::z::
I A4
A5
A6
~
~
A4
A5
2 A6
. 04
05
06
'15
'16
'17
05
os
ii7
-I
::z::
In
CI)
o
"'"'""
A7 -;- A7
-::- 07 , ---4
A8 - .1.2 A8
A9 ~ A9
Al0 ~ Al0
.2!.. All
All
L----~--~==_~18~ CE
- 20 OE
~ l J
292019-11
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
Main Routine tasks. After reception of the long frame, the SIU inter-
rupt routine is executed again. This time, RTS, TBF,
First, the chip is initialized (see Figure 10). It is put in and RBE are set for another round of information ex-
Flexible mode, externally clocked, and "Flag-Informa- change between the two stations.
tion Field-FCS-Flag" frame format. Pre-Frame Sync
option (PFS = I) and automatic Frame Check Se- SIU never interrupts while reception or transmission is
quence generation/detection (NFCS = 0) are selected. taking place. The SIU registers are updated and the SI
The on-chip transmit buffer starts at location 20H and is set (serial interrupt) after the closing flag has been
the transmit buffer length is set to 1. This one byte received or transmitted. An SIU interrupt never occurs
buffer contains the address of the secondary station. if the receive interrupt routine or the transmit subrou-
There is no on-chip receive buffer since the long frame tine is being executed.
being received is moved to the external buffer. The
RTS, TBF, and RBE bits are set simultaneously. Set- Setting the RBE bit of the STS register puts the RUPI
ting the RTS and TBF bits causes the SIU to transmit in the receive mode. However, the jump to the receive
the contents of the transmit buffer. interrupt routine occurs only when a frame appears on
the serial port. Incoming frames can be detected using
the Pre-Frame Sync. option and one of the CPU timers
in counter mode. The counter external pin (TO) is con-
nected to the data line (pin 11 is tied to pin 14). Setting
the PFS (Pre-Frame Sync.) bit will guarantee 16 tran-
sitions before the opening' flag of a flame.
292019-12
Main Program
Figure 10. Primary Station Flow Charts
SIU Interrupt Routine
After transmission of the frame, the SIU interrupts the
on-chip CPU (SI is set). In the SIU interrupt service
routine, counter 0 is initialized and turned on (see Fig-
ure 11). The user program returns to perform other 292019-13
SIU Interrupt Routine
Figure 11. Primary Station Flow Charts
15-39
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
The counter registers are initialized such that the coun- 2) Monitor the SIUST register for standby in the
ter interrupt occurs,before the opening flag of a frame. PUSH-I state (SIUST = 18H). When the SIUST
When the PFS transitions appear on the, data line, the contents are 18H, the byte processor is waiting for
counter overflows and interrupts the CPU., The CPU the first information byte. The bit processor has al-
program jumps to the timer interrupt service routine ready recognized the flag and is processing the first
and executes the receive routine. In the receive routine, , information byte.
the received frame, isprocessed,and the information 3) In the standby mode, move the byte processor into
bytes are moved to the external RAM. Note that the the CONTROL state by writing "EFH" (comple-
maximum count ni.te of the 8051 counter is '124 of the ment of 10H) into the SIUST register. When the
oscillator frequency. At 12 MHz, the data rate is limit- next' byte boundary occurs, the bit processor has
ed to 500 Kbps. processed and moved a byte of data into the SR
register. The byte processor moves the contents of
Another method to detect a frame on the data line and SR into the RCB register, jumps to the PUSH-I
cause an interrupt is to use an external "Flag-Detect" state (SIUST ,;; 18H), and waits.
circuit to interrupt the CPU. The "Flag Detect" circuit
can be an 8-bit shift register plus some TTL chips. If 4) Monitor the SIUST register for standby in the
this option is used, the RUPI must operate in externally PUSH-l state. When the contents of SIUST be-
clocked mode because the clock is ,needed to shift the comes 18H, the contents of RCB are the first infor-
incoming data into the shift register. With this option, mation byte of the information field.
the maximum data rate is ,not limited by the maximum 5) While the byte processor is in the standby mode,
count rate of the 8051 counter. , move the contents of RCB to an external RAM or
an I/O port.
Receive Interrupt Routine 6) Check for the end of the information field. The end
can be detected by knowing the number of bytes
In Normal operation, the byte processor executes the transmitted, or by having a unique character at the
procedures of the FLAG state, jumps to the CON- end of information field. The length of the informa-
TROL state without going into the standby mode, and tion field can be loaded into the first byte(s) re-
executes 10-2 procedure of the state (see Figure 4). It ceived. The receive routine can load this byte into
then jumps to the PUSH-l state and goes into the the loop counter. ,
standby mode. At the following byte boundaries, the 7) If the byte receiv~ is not the last information byte,
byte processor executes the PUSH-I, PUSH-2, and move the byte processor back to standby in the
DMA-LOOP states, respectively. The receive interrupt CONTROL state and repeat steps 4 through 6. Oth-
routine as, shown iii the flow chart of Figure 12 and erwise, return from the interrupt routine.
described below forces the byte processot'to repeatedly
execute the CONTROL state before the PUSH-l state Upon returning from the receive interrupt routine, the
is executed. The following is the step by step procedure byte processor automatically executes the PUSH-I,
to receive long frames: PUSH-2, and DMA-LOOP before it stops. This causes
1) Turn off the CPU counter and save all the impor-, the remaining information bytes (if any) to be stored in
tant registers. Jump to the receive interrupt routine, the internal RAM at the starting location specified by
execution of the instructions to save regIsters, and the contents of RBS register. At the end of the cycle,
initialization of the receive buffer pointer take place the closing flag and the CRC bytes are left in the FIFO.
while the Pre-Frame Sync bytes and the opening The RFL register will be incremented by the number of
flag are being received. This is about three data byte bytes stored in the internal RAM. Then, the STS and
periods (48 CPU cycles at 500 Kbps). NSNR registers are updated, and an appropriate re-
sponse is generated by the SIU.
The software to perform the above task is given in Ta-
ble 1. In this example, the number of ittstruction cycles
executed during standby is 12 cycles.
15-40
FLEXIBILITY IN FRAME SIZE WITH THE 8044
Receive Codes Cycles
• •
• •
• •
REC: CLR TRO
MOV A,#18H
WAIT1: CJNE A, SIUST ,WAITl
NEXTI: MOV SIUST, #OEFH ••••••••••••••••••••••• 2
MOV A,#18H •••••••••••••••••••••••••••• l
WAIT2: CJNE A,SIUST,WAIT2 •••••••••••••••••••••• 2
MOV A,RCB •••••••••••••••••••••••••••••• 1
MOVX @DPTR,A ••••••••••••••••••••••••••• 2
INC DPTR •••• .'•••••••••••••••••••••••••• 2
DJNZ R5,NEXTI ••••••••••••••••••••••••••• 2
RET!.
END 12 Cycles
6.1.4 SECONDARY STATION SOFTWARE
The assembly code for the secondary station software is
given in Appendix A. The secondary station contains
the transmit subroutine which is called for transmission
of long frames.
Main Routine
As shown in the secondary station flow chart (Figure
13), the external transmit buffer (external RAM) is
loaded with the information data (FFH, FEH, FDH,
... ) at starting location 200H. The internal transmit
buffer (ori chip RAM) starts at location 20H (TBS =
20H), and the transmit buffer length (TBL) is set to 1.
The on-chip CPU, in the transmit subroutine, moves
the information bytes from the external RAM to this
one byte buffer for transmission. The receive buffer
starts at location IOH and the receiver buffer length is
1. This buffer is used to buffer the frame transmitted by
the primary. The received byte is used as an address
byte.
The Secondary is configured like the Primary station. It
is put in Flexible mode, externally clocked, Point-to-
point frame format. The PFS bit is set to transmit two
bytes before the first flag of a frame. The RBE bit is set
to put the chip in receive mode. Upon reception of a
valid frame, the SIU loads the received information
byte into the on-chip receive buffer and interrupts the
CPU.
SIU Interrupt Routine
In the serial interrupt routine, the RBE bit is checked
(see Figure 14). Since RBE is clear, a frame has been
292019-14 received. The received Information byte is compared
Receive Interrupt Routine with the contents of the Station Address (STAD) regis-
ter.
Figure 12. Primary Station FI.ow Charts
15-41
intJ FLEXIBILITY IN FRAME SIZE WITH THE 8044
= 1. FRAME XMlmD
ADDRESS NOT MATCHED
292019-15
292019-16
Main Program SIU Interrupt
Figure 13. Secondary Station Flow Charts Figure 14. Secondary Station Flow Charts
If they match,thesecondary will call the transmit sub· While the bit processor is transmitting the first Pre·
routine to transmit the long frame. Upon returning Frame Sync byte, the byte processor executes the PFS2
from the transmit subroutine, the RBE bit is set, and state and jumps to the standby mode in the FLAG
program returns from the SIU interrupt. Mter trans· state. The FLAG state is executed when the bit proces·
mission of the closing flag, sm interrupt occurs again. sor begins to transmit the sec9nd Pre·Frame Sync byte.
In the interrupt routine, the RBE is checked. Since the When the flag is being transmitted, the byte processor
RBE is' set, the program returns from the SIU interrupt executes the 98-1, 98-2, 98-3, and 98-4 procedures of
routine and waits until another long frame is received. the FLAG state, and jumps to execute the A8-1 proce-
dure of the CONTROL state. When the opening flag is
If the secondary were in Auto mode, the chip must be transmitted, the contents of RB are the fttst informa-
ready to execute the transmit routine upon reception of tion byte. (See transmit state diagram.)
a poll·frame; otherwise, the chip automatically trans·
mits the contents of the internal transmit buffer if the In the transmit subroutine (see Figure 15), the byte
TBF bit is set, or transmits a supervisory command processor is forced to repeat the CONTROL state be-
(RR or RNR) if TBF is clear. fore the DMA-LOOP state. In the CONTROL state,
the contents of a RAM location addressed by the TBS .
Transmit Subroutine register are moved to the RB register. The following is
the step by step procedure to transmit long frames:
In Normal operation the byte processor executes the 1) Put the chip in transmit mode by setting the ins
START·TRANSMIT state and jumps to the PFSI and TBF bits.
state. While the bit processor is transmitting some un· 2) Move an information byte from external RAM to a
wanted bits, the byte processor executes the PFSI state location in the internal RAM addressed by the con-
and jumps to the standby mode in the PFS2 state. tents of TBS.
15-42
infef FLEXIBILITY IN FRAME SIZE WITH THE 8044
3) Monitor the SIUST register for the standby mode in
the DMA-LOOP state (SIVST = BOH). When
SIUST is BOH, the opening flag has been transmit-
ted, and the first information byte is being transmit-
ted by the bit processor.
4) If there are more information bytes, move the byte
processor back to the CONTROL state, and repeat
steps 2 through 4. Otherwise, continue.
5) Move byte processor to the Standby mode in the
CONTROL state (SIUST = ASH) and return from
the subroutine.
The byte processor automatically executes the remain-
ing states to send the FCS bytes and the closing flag.
After the completion of transmission, SIU updates the
STS and NSNR registers and interrupts the CPU.
If the contents of the TBL register were more than I,
the SIV transmits (TBL)-I additional bytes from the
internal RAM at starting address (TBS) + I because it
executes the DMA-LOOP state (TBL) -I additional
times. The byte processor should' not be programmed to
skip the DMA-LOOP state, because the transmission of
FCS bytes is enabled in this state.
The maximum baud rate that can be used with these
codes is calculated by adding the number of instruction
cycles executed, during the standby mode, between
each byte boundaries (see Table 2) .
. Using Equation I, the maximum data rate, based on the
292019-17 transmit software, is 509 Kbps; However, the maxi-
Transmit Subroutine mum count rate of the counter limits the data rate to
500 Kbps.
Figure 15. Secondary Station Flow Charts
Table 2. Codes for Lon Frame Transmission
Transmit Codes Cycles
• •
• •
• •
TRAN: MOV DPTR.#200H
MOV R5. #OFFH
SETB TBF
SETB RTS
LOOP: MOVX A.@DPTR
MOV @Rl.A
MOV A. #OBOH
WAIT1: CJNE A.SIUST.WAIT1 •••••••••••••••••••• 2
INC DPTR ••••••••• ~ ••••••••••••••••••• 2
MOVX A,@DPTR ••••••••••••••••••••••••• 2
MOV @Rl.A ••••••••••••••••••••••••••• 1
DJNZ R5,NEXTI ••••••••••••••••••••••••• 2
MOV SIUST.#57H
RET
NEXTI: MOV SIUST. #57H •••••••••••••••••••••• 2
MOV A. #OBOH ••••••••••••••••••••••••• 1
JMP WAITl •••••••••••••••••••••••••••• 1
END
13 Cycles
15-43
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
6.2 Multidrop Application secondary stations, and acknowledges a previously re-
ceived frame simultaneously (see Figure 17). Both sec-
Performance of long frame in addition to the features of ondary stations, in Auto mode, detect the transmitted
the 8044 are described using a sUnple multidrop com- frame and check its address byte. One of the secondary
munication system in which three RUPIs, one as a stations receives the frame, stores the Iriformation bytes
master and the other two as secondary stations, trans- in an external RAM buffer, and transmits the same
mit and receive ICing frames alternately (see Figure 16). data back to the priinary. After reception of the frame,
All stations perform automatic Zero bit, insertion/dele- , the primary polls and transmits a long frame to the
tion, NRZI decoding/encoding, Frame Check Se- other secondary station which will' respond with the
quence (FCS) generation/detection, and on-chip clock same long frame. '
recovery at a data rate of 375 Kbps. '
6.2.2 HARDWARE
'The primary and the secondary station's software code
is giveri in Appendix B. These programs, for simplicity, The schematic of the secondary station hardware is
assume only reception of information and supervisory shown in Figure 18. The primary station's hardware is
frames. It is also assumed that the frames are received similar to the secondary station's hardware. The excep-
and transmitted in order: All stations use very similar tion is in secondary stations only, where the RTS signal
transmit and receive routines. This code is written for is inverted and tied to the interrupt 0 input pin (INTO).
standard SDLC frames (see Figure 7). In the primary station, RTS is tied to CTS. At each
station, software codes are stored in' external EPROM
6.2.1 POLLING SEQUENCE (2732A). Static RAM (2Kx8) is used as external trans-
mit/receive buffer. There is no hardware handshaking
The priinary station, in Flexible mode, transmits a long done between the stations, The serial clock is extracted
frame (for this example, 255 I-bytes), polls one of the from the data line using the on-chip phase locked loop.
PRIMARY
STATION
SECONDARY SECONDARY
STATION STATION
292019-18
Figure 16. SDLC Multidrop Application Example
PRIMARY
SECONDARY SECONDARY
292019-19
Figure 17. POlling Sequence Between the Primary and Secondary Stations
15-44
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292019-20
infef FLEXIBILITY IN FRAME SIZE WITH THE 8044
.6.2.3 PRIMARY SOFTWARE The station address register (STAD) is loaded with ad-
dress of one of the secondary stations. The RTS, TBF,
and RBE bits of the STS register are simultaneously set
Main Routine, and a call to the transmit routine follows. The transmit
During initialization (see Figure 19), the 8044 is set to routine transmits the contents of the external transmit
Flexible mode, internally clocked at 375 Kbps, and buffer. At the end of transmission, RTS and TBF are
configured to handle standard SDLC frames. The on- cleared by the SIU, and SIU interrupt occurs. In Flex-
chip receive and transmit buffer starting addresses and ible mode, SIU interrupt occurs after every transmis-
lengths are selected. The external transmit buffer is sion or reception of a frame.
chosen from physical location 200H to location 2FFH
(255 bytes). The external transmit buffer' (external SIU Interrupt Routine
RAM) is loaded with data (FFH, FEH, FDH, FCH,
... OOH). Timer 0 is put in counter mode and set to In the SIU interrupt service routine (see Figure 20), SI
priority I. The counter register (TLO) is loaded such is cleared and the RBE bit is checked. If RBE is set, a
that interrupt occurs after 8 transitions on the data line. long frame has been transmitted. The first time through
The Pre-Frame Sync option (setting bit 2 of the SMD the SIU interrupt service routine, the RBE test indi-
register) is selected to guarantee at least 16 transitions cates a long frame has been transmitted to one of the
before the opening flag of a frame. secondary stations. Therefore, the Counter is initialized
=1. FRAME XMITTED
292019-21 292019-22
Main Program SIU Interrupt
Figure 19. Primary Station Flow Charts Figure 20. Prirriary Station Flow Charts
15-46
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
and turned on. The program returns from the interrupt The secondary is configured to transmit an Information
routine before a frame appears on the communication frame every time it is polled. The RTS pin is inverted
channel. and tied to INTI pin. External interrupt 1 is enabled
and set to interrupt on low to high transition of the
When a frame appears on the communication line, RTS signal. This will cause an interrupt (EXI set) after
counter interrupt occurs and the receive routine is exe- a frame is transmitted. In the interrupt routine the CTS
cuted to move the incoming bytes into the external pin is cleared to prevent any automatic response from
RAM. After reception of the frame and return from the the secondary. If the CTS pin were not disabled, the
receive routine, SIU interrupt occurs again. secondary station would respond with a supervisory
frame (RNR) since the TBF is set to zero by the SIU
In the SIU interrupt routine, RBE is checked. Since the due to the acknowledge. In the SIU interrupt routine,
RBE bit is clear, a frame has been received. Therefore, the CTS pin is cleared after the TBF bit is set. If this
the appropriate NS and NR counters are incremented option is not used, the primary should acknowledge the
and loaded into the TCB register (two pairs of internal previously received frame and poll for the next frame in
RAM bytes keep track of NS and NR counts for the two separate transmissions.
two secondary stations). Transmission of a frame to the
next secondary station is enabled' by setting the RTS
and the TBF bits. The chip is also put in receive mode SIU Interrupt Routine
(RBE set), and a call to transmit routine is made. After When a frame is received, counter 0 iiIterrupt occurs
transmission, SIU interrupt occurs again, and the pro- and the receive routine is executed (see Figure 22). If
cess continues. the incoming frame is addressed to the station, the in-
formation bytes are stored in external RAM; Other-
6.2.4 SECONDARY SOFTWARE wise, the program returns from the receive routine to
perform other tasks. At the end of the frame, SIU inter-
rupt occurs. In Auto mode, SIU interrupt occurs when-
Main Routine ever an Information frame or a supervisory frame is
Both secondary stations have idep.tical software (Ap- received. Transmission will not cause an interrupt. In
pendix B). The only differences are the station address- the SIU interrupt service routine, the AM bit of the
es. Contents of the STAD register are 55H for one sta- STS is checked.
tion and 44H for the other.
If AM bit is set, the interrupt is due to a frame whose
address did not match with the address of the station.
In this case, NFCS, AM, and the BOY bits are cleared,
the RBE bit is set, the counter 0 is initialized and
turned on, and program returns from the interrupt rou-
tine.
SET UP ~XTERNAL AND INTERNAL
TRANSMIT AND RECEIVE BUFFERS If AM bit is not set, a valid frame has been received and
stored in the external RAM. TBF bit is set, CTS pin is
activated, counter 0 is disabled and a call to transmit
routine is made which transmits the contents of exter-
nal transmit buffer. This frame also acknowledges the
reception of the previously received frame (NS and NR
are automatically incremented). Upon return from the
transmit routine RBE is set and counter 0 is turned on,
thereby putting the chip in the receive mode for anoth-
er round of data exchange with the primary.
Note that, if the second station is in receive mode, and
292019-23 the counter is enabled and turned on, the CPU will be
Main Program interrupted each time a frame is on the communication
channel. If the frame is not addressed to the secondary
Figure 21. Secondary Station Flow Charts station, the chip enters the receive routine, executes
only a few lines of code (address comparison) and re-
During initialization, the chip is set to Auto mode, turns to perform other tasks. This interrupt will not
standard SDLC frame, and internally clocked at occupy the CPU for more than two data byte periods
375 Kbps (see Figure 21). Internal buffer registers: (43 microseconds at 375 Kbps). At the end of the
RBS, RBL, TBS, and TBL are initialized. The RBE bit frame, the BOY bit is set by the SIU, and the SIU
is set and the counter·.O is turned on. interrupt occurs. In the SIU interrupt service routine,
15-47
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
In tp.e receive interrupt service routine (see Figure 23),
counter 0 is turned off, important registers ·are saved,
receive buffer starting address and receive buffer length
of the external RAM are set (do not confuse the exter-
nal RAM settings with that of the internal RAM buff-
er.)
After reception of.an opening flag, the byte processor
jumps to the ADDRESS state and waits until the bit
processor processes and moves the receiving address
byte to SR. Then, the byte processor is triggered to
=I, ADDRESS MATCHED execute the state. In the secondary stations, the CPU
monitors the SIUST register for the ADDRESS state
(SIUST = OSH). When the ADDRESS state is
reached, the byte processor is moved to the next state
(CONTROL state), and the ADDRESS state is
skipped. Therefore, when the address byte is moved to
SR, the byte processor executes the CONTROL state
rather than the ADDRESS state and then jumps to the
PUSH-l state. The execution of the CONTROL state
causes the contents of SR (the received address byte) to
be loaded into the RCB register.
The CPU cheCks the contents of RCB with the contents
of the STAD (Station Address) register. If they match,
the receive routine continues to store the received In-
formation bytes in the external RAM buffer; Other-
wise, the byte processor is moved to the very last state
(BOY-LOOP); and the program returns from the rou-
tine to perform other tasks. The byte processor executes
the BOY-LOOP state in each byte boundary until the
closing flag of the frame is reached. It then sets the
BOY bit and interrupts the CPU (serial interrupt SI
set). In the serial interrupt routine the counter 0 is
turned back on, and the station is reset back. to the
receive mode (RBE set).
In Normal operation, in the ADDRESS state, the re-
ceived address byte is automatically compared with the
station address. If they match, the byte processor exe-
cutes the remaining states; otherwise, the byte proces- .
sor goes into the idle mode (SIUST = OIH) and waits
for the opening flag of the next frame. In the expanded
operation, this state is skipped to avoid idle mode. If
292019-24
the byte processor went into the idle mode, clocks
SIU Interrupt which run the byte processor would be turned off, and
Figure 22. Secondary Station Flow Charts the byte processor can not be moved to any other states
by the CPU. When the byte processor is in idle mode,
the RBE bit is set and the counter is turned on which counter 0 can not be turned on immediately because
counter interrupt occurs on the same frame, and pro-
put the chip back in the receive mode.
gram returns to the receive routine and stays there.
6.2.5 RECEIVE INTERRUPT ROUTINE If the address byte matches the station address, the byte
processor is moved to the CONTROL state again. This
Assembly code for the receive interrUpt routine can be time, after execution of the CONTROL state the con-
found in both primary and secondary software (Appen- tents of RCB are the received control byte. .
dix B). The receive interrupt routine of the primary
station is very similar to that of the primary station in CPU investigates the type of received frame by check-
example 1. In the following two sections the receive and ing the received control byte. If the receiving frame is
transmit routine of the secondary stations are dis- not an information frame (i.e. Supervisory frame), exe-
cussed. cution of receive routine will be terminated to free the
15-48
(
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292019-25
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
CPU. In Auto mode, the SIU checks the control byte byte from external RAM to the internal RAM location
and responds automatically in response to the supervi- addressed by TBS. The byte processor is then moved to
sory frame. CONTROL state. This will cause the byte processor, in
the next byte boundary, to move the contents of the
After the control byte is received, it is saved in the same location in the internal RAM to the RB register
stack. The byte processor is moved to the CONTROL (see transmit state diagram.)
state so that the next incoming byte will also be loaded
into the RCB register. The byte processor remains in When this byte is being transmitted, the byte processor
CONTROL state until a byte is processed by the bit jumps to the DMA-LOOP state (SIUST = BaH) and
processor and moved to SR. The byte processor is then waits. When the DMA-LOOP state is reached (CPU
triggered to move the contents of SR to the RCB regis- monitors SIUST for BOH), the CPU loads the next In-
ter. The CPU monitors SIUST and waits until the first formation byte into the same location -in the internal
Information byte is loaded into the RCB register. RAM and moves the byte processor to the CONTROL
state before it gets to execute the DMA-LOOP state.
When byte processor reaches the PUSH-I state (SIUST Note that the same location in the internal RAM is
= ISH), RCB contains the first Information byte. The used to transmit the subsequent Information bytes.
byte is moved to external RAM (receive buffer), and
the byte processor is moved back to the CONTROL When all the Information bytes from the external
state. The process continues until all of the Information RAM are transmitted, the byte processor is free to go
bytes are received. When all the Information bytes are through the remaining states so that it will transmit the
received, the program returns from the routine. The FCS bytes and the closing flag.
byte processor automatically goes through the remain-
ing states, updates the STS register, and interrupts the
CPU as it would in Normal operation. 7.0 CONCLUSIONS
The RUPI, with addition of only a few bytes of code,
6.2.6 TRANSMIT SUBROUTINE can accept and transmit large frames with some com-
promise in the maximum data rate. It can be used in
The transmit subroutine codes can be found in the pri- Auto or Flexible mode, with external or internal clock-
mary and the secondary software (Appendix B). The , ing, automatic CRe checking, and zero bit insertion/
transmit subroutines of the Primary and secondary sta-, deletion. In addition, almost all of the internal RAM is
tions are identical. A call to transmit routine is made available to be used as general purpose registers, or in
when the R TS and TBF bits of the STS register are set. conjunction with the external RAM as transmit and
In Auto mode, RTS is set automatically upon reception receive buffers.
of a poll-frame (poll bit of the control byte is set).
All in all, this feature opens up new areas of applica-
In the transmit routine (see Figure 15), the starting ad- tions for this device. Besides transmitting/receiving
dress and the transmit buffer length of the external long frames, it may now be possible to perform arith-
buffer are set. Then the CPU moiritors the SIUST regis- metic operations or bit manipulation (e.g. data scram-
ter for CONTROL state (SIUST = ASH). In the bling) while transmission or reception is taking place,
CONTROL' state the bit processor transmits the con-
resulting in high throughput. Transmission of continu-
trol byte, while the byte processor goes into the standby ous flags and transmission with no zero insertion are
mode after it has moved the contents of a location in also possible.
the internal RAM addressed by the contents of Trans-
mit Buffer Start (TBS) register to the RB register. In addition to unlimited frame size, an on-chip control-
ler, automatic SDLC responses, full support of SDLC
While the control byte is being transmitted' and the byte
protocol, 192 bytes of internal RAM, and the highest
processor is in standby, the CPU moves an Information data rate in self clocked mode compared to other chips
make this product very attractive. '
15-50
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
APPENDIX A
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 1
$DEBUG NOMOD5l.
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (POINT TO POINT)
FLEXIBLE MODE; FCS OPTION
ORG DOH LOCATIONS 00 THRU 26H ARE USED
SJMP INIT BY INTERRUPT SERVICE ROUTINES.
ORG OBH VECTOR ADDRESS FOR TlMERO INT.
JMP REC
ORG 23H VECTOR ADDRESS FOR SIU INT.
SJMP SIINT
; •• ***.*************** INITIALIZATION **** ••• ** ••••• ***.*** •••••
ORG 26H
INIT: MOV SMD, '00000110B EXT CLOCK; PFS=NB~l
MOV TBS,#20H INT TRANSMIT BUFFER START
MOV TBL,tOlH INT TRANSMIT BUFFER LENGTH
MOV 20H,#55H STATION ADDRESS
MOV THOD,'OOOOOlUB COUNTER FUNCTION; MODE
MOV IE,nOOlOOl.OB EA=l; SI=l.; ETO=l
MOV STS,#l.ll.OOOOOB TRANSMIT A FRAME
DOT: SJMP DOT WAIT FOR AN INTERRUPT
SIU TRANSMITS THE PFS BYTES, THE OPENNING FLAG, THE CONTENTS
OF LOCATION 20H, THE CALCULATED FCS-BYTES, AND THE CLOSING
FLAG. AT THE END OF TRANSMISSION, SIU INTERRUPT OCCURS.
;************* SERIAL CHANNEL INTERRUPT ROUTINE *.*.* •• *******.*
SIINT: CLR 81
JNB RaE,RECVED TRANSMITTED A FRAME ?
MOV TLO,'OF8H YES, INITIALIZE COUNTER REGISTER
MOV DPTR,'200H EXT RAM RECEIVE BUFFER START
MOV R5,'OFFH EXT RAM RECEIVE BUFFER LENGTH
SETS TRO TURN ON COUNTER 0
RETI RETURN 292019-28
WHEN A FRAME APPEARS ON THE SERIAL CHANNEL, COUNTER (RECEIVE)
INTERRUPT OCCURS. AFTER SERVICING THE INTERRUPT ROUTINE, SID
INTERRUPT OCCURS.
RECVED: MOV STS, 'l.ll.OOOOOB TRANSMIT A FRAME
RETI RETURN
,.*************** RECEIVE INTERRUPT ROUTINE .*****.*************
REC: .CLR TRO DISABLE THE COUNTER 0 INTERRUPT
MOV A,U8H PUSH-l STATE
WAITl: CJNE A, SIUST, WAITl
NEXTI: MOV SIUST, 'OEFH . MOVE BYP TO CONTROL STATE
MOV A,U8H PUSH-l STATE
WAIT2: CJNE A, SIUST, WAIT2
MOV A,Res MOVE RECEIVED BYTE INTO ACC.
MOVX @DPTR,A MOVE DATA TO EXT. RAM
INC DPTR INCREMENT POINTER TO EXT RAM
DJNZ R5,NEXTI LAST BYTE RECEIVED?
RETI YES, RETURN
END
292019-29
15-51
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
$DEBUG NOMOD51
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR SECONDARY STATION (POINT TO POINT)
FLEXIBLE MODEl FCS OPTION
ORG OOH
SJIIP INIT
ORG 23H ; VECTOR ADDRESS FOR SIU INT.
SJIIP SIINT
,*.t ••••••••••••• tpAD TRANSMIT BUFFER WITH DATA .t.t •••••••••
ORG 26H
INIT: MOV DPTR,#200H EXT RAM XHIT BUFFER START
MOV R3,tOFFH EXT RAM XHIT BUFFER LENGHT
LDRAM: MOV A,R3
MOVX @DPTR,A LOAD EXT BUFFER WITH FFH,FEH, •••
INC DPTR INCREMENT POINTER
DJNZ R3,LDRAM
;**** •• *************INITIALIZATION *tttt •••••••••• * •••••••••••
HOV SHU,IOOOOOllOB EXT CLOCK; PFS=lIB=l
HOV Rl,#lOH
MOV TBS,Rl INT RAM XHIT BUFFER START
MOV TBL,f01H INT RAM XHIT BUFFER LENGTH
MOV RBS,t20H INT RAM RECEIVE BUFFER START
MOV RBL,fOlH INT RAM RECEIVE BUFFER LENGTH
HOV STAD,USH STAD ADDRESS=55H
MOV TCON,tOOH RESET TCON REGISTER
MOV IE,U0010000B ENABLE SI INT. IEA=l
MOV IP,fOFFH ALL INTERRUPTS I PRIORITY 1
HOV STS,f01000000B RBE-l, RECEIVE A FRAME.
DOT: SJHP DOT WAIT FOR AN INTERRUPT
I SIU INTERRUPT OCCURS AT THE END OF A RECEIVED FRAME OR
; A TRANSMITTED FRAME. 292019-30
,******* ••• ***** SERIAL CHANNEL INTERRUPT ROUTINE tttttIA •••••
SIINT: CLR SI
JB RBE, RETlIN RECEIVED A FRAME?
HOV A,STAD YES
CJNE A,20H,NKACH STATION ADDRESS MATCHED?
ACALL TRAN YES, CALL TRANSMIT SUBROUTINE
TRANSMIT SUBROUTINE IS CALLED TO TRANSMIT A LONG FRAME.
AFTER TRANSMISSION, ,51 IS SET. SIU INTERRRUPT IS SERVICED
AFTER THE CURRENT ROUTINE (SIINT) IS COMPLETED.
NKACH: SETB RBE ; RBE~l, RECEIVE A FRAME
RETlIN: RETI ; RETURN
;.t •• t.A ••••••• TRANSMIT SUBROUTINE *ttttIA •••••••••••••••••••
TRAN: HOV DPTR,f200H EXT RAM RECEIVE BUFFER START
MOV RS,tOFFH EXT RAM RECEIVE BUFFER LENGTH
SETB TBF SET TRANSMIT BUFFER FULL
. SETB RTS ENABLE XHISSION OF AN I-FRAME
LOOP: MOVX A,@DPTR MOVE THE 1ST I-BYTE INTO ACC.
MOV @Rl,A THEN, MOVE TO INT. RAM @ (TBS)
MOV A,fOBOH DKA-LOOP STATE
WAIT1: CJNE A,SIUST,WAITl WAIT FOR XHISSION OF AN I-FRAME
INC DPTR INCREMENT POINTER TO EXT. RAM
DJNZ RS,NEXTI ALL BYTES XHITTED?
MOVX A,@DPTR YES, EXCEPT THE LAST BYTE.
HOV @Rl,A MOVE DATA INTO INT. RAM I! (TBS)
HOV SroST"S7H MOVE BYP TO CONTROL STATE
THE SIU TRANSMITS THE FCS-BYTES
AND THE CLOSING FLAG.
RET RETURN
NEXTI: MOV SIUST,'S7H MOVE BYP TO CONTROL STATE (ASH).
JIIP LOOP TRANSMIT THE NEXT BYTE
END
292019-31
15-52
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
APPENDIX B
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 2
$DEBUG NOMODSl
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (MULTIPOINT)
FLEXIBLE MODE; FCS OPTION
ORG OOH LOCATIONS 00 THRU 26H ARE USED
SJMP INIT BY INTERRUPT SERVICE ROUTINES.
ORG OBH VECTOR ADDRESS FOR TlMERO INT.
JMP REC
ORG 23H VECTOR ADDRESS FOR SIU INT.
SJMP SlINT
,******** •• ****** LOAD TRANSMIT BUFFER WITH DATA ••• *********
ORG 26H
INIT: MOV DPTR, f200H EXT RAM XMIT BUFFER START
MOV R3,#OFFH EXT RAM XMIT BUFFER LENGHT
LDRAM: MOV A,R3
MOVX @DPTR,A LOAD BUFFER WITH FFH,FEH, ••• OO
INC DPTR INCREMENT POINTER
DJNZ R3, LDRAM 292019-32
;********************* INITIALIZATION ******.*** •• **** •••• **.
MOV RO,#OBFH PUT ZEROS INTO INT. RAM
LOOP: MOV· A,tOOH FROM BFH TO 40H.
MOV @RO,A MOVE 0 INTO RAM ADDRESSD BY RO
DEC RO
CJNE RO,#4oH,LOOP
MOV 30H, 'OOH NS COUNTER FOR STAD=SS
MOV 31H, 'OOH NR COUNTER FOR STAD=SS
MOV 32H, #OFFH NS. COUNTER FOR STAD=44
MOV 33H, #OFFH NR COUNTER FOR STAD~44
MOV 34H, 'OlH PONITER TO SECONDARY STATIONS
MOV SMD,#llOlOlOOB INT. CLKED @ 37SK; NRZI=l; PFS=l
MOV RBS,flOH INT. RAM RECEIVE BUFFER STAR~lOH
MOV RBI., 'OOH INT. RAM RECEIVE BUFFER LENGTH=O
MOV Rl,#20H INT. RAM XMIT BUFFER START-20H
MOV TBS,Rl
MOV TBL, 'OlH INT. RAM XMIT BUFFER LENGTH=l
MOV NSNR, 'OOH NS=NR=O
KOV THOD,#OOOOOlllB COUNTER FUNCTION, MODE 3
MOV TCON,jOOH
MOV IE,#lOOlOOlOB EA-l; SI=ll ETO-i
MOV IP,#OOOOOOlOB TIMER 0 INT. PRIORITY 1
MOV TCB,#OOOlOOOOB I-FRAME W/POLL
MOV STAD, #SSH ADDRESS BYTE=SSH
MOV STS,tlllOOOOOB RBE=TBF-RTS=l
TRANSMIT A LONG FRAME WITH POLL BIT SET, WAIT FOR.A
RESPONSE.
ACALL TRAM CALL TRANSMIT ROUTINE
DOT: SJMP DOT WAIT FOR AN INTERRUPT
292019-33
15-53
inter FLEXIBILITY IN FRAME SIZE WITH THE 8044
;************* SERIAL INTERRUPT ROU~INE *****************.*.*
SIINT: CLR SI CLEAR SI
JB RBE, RETl1RII RECEIVED A FRAME ?'
MOV A,RCB YES, LOAD ACC WITH REC CNTRL BYTE
JB ACC.O,GETI IS IT AN I-FRAME ?
MOV A,f01H YES
CJNE A,34H,SKIP
MOV A,30H MOVE NS INTO ACC.
INC A INCREMENT NS
ANL A, #00000111B MASK OUT THE LEAST 3 SIG. BITS
MOV 30H,A SAVE NS
MOV A,.3lH MOVE NR INTO ACC.
INC A INCREMENT NR
ANL A, #00000111B MASK OUT THE LEAST SIG. BITS
MOV 31H,A SAVE NR
RL A SHIFT 4 BITS TO LEFT
RL A
RL A
RL A
ORL A,30H MOVE NS COUNT TO ACC.
RL A SHIFT 1 BIT TO LEFT
ORL A,.00010000B SET THE POLL BIT
MOV TeStA MOVE CONTROL BY'l'E INTO TCB REG.
'lCB: NR2,HRl,NRO,1,HS2,NS1,NSO,O
MOV STAD"SSH
MOV 34H,foOH
JMP GETI 292019-34
SKIP: MOV A,32H I MOVE NS INTO ACC.
INC A INCREMENT NS
ANL A, '00000111B MASK OUT THE LEAST 3 SIG. BITS
MOV 32H,A SAVE NS
MOV A,33H MOVE NR INTO ACC.
INC A INCREMENT NR
ANL A, #OOOOOll1B MASK OUT THE LEAST SIG. BITS
MOV 33H,A SAVE NR
RL A SHIFT 4 BITS TO LEFT
RL A
RL A
RL A
ORL A,33R MOVE NS COUNT TO ACC.
RL A SRIFT 1 BIT TO LEFT
ORL A,'OOO10000B SET THE POLL BIT
MOV TCB,A MOVE CONTROL BYTE INTO TCB
TeB: NR2,NR1,NRO,1,NS2,HSl,NSO,O
MOV STAD,#44R
MOV 34R,#01R
GETI: MOV STS, '11100000B ENABLE TRANSMISSION
ACALL TRAN CALL TRANSMIT ROUTINE
RETI
RETl1RII: CLR EA DISABLE ALL INTERRUPTS
MOV TLO,IOFBR INTERRUPT AFTER 8 COUNTS
SETB TRO Tl1RII ON COUNTER 0
SETB EA
RETI 292019-35
;.*****.**** ••• RECEIVE INTERRUPT ROUTINE ********.*.*.**.*.*
REC: CLR
MOV
TRO
DPTR,#400H
Tl1RII OFF COUNTER °
EXT. RAM RECEIVE BUFFER START
MOV RS,foFFH EXT. RAM RECEIVE BUFFER LENGTH
MOV A,U8H PUSH-l STATE
WAIT1: CJNE A,SIUST,WAITl WAIT FOR THE CONTROL BY'l'E
PUSH RCB SAVE RECEIVE CONTROL BYTE
NEXTI: MOV SIUST, 'OEFH PUSH "BYP" INTO CONTROL STATE (lOB) •
MOV A,U8H PUSR-l STATE
WAIT2: CJNE A, SIUST, WAIT2 WAIT FOR AN I-BYTE
MOV A,RCB MOVE RECEIVED I-BYTE INTO ACC.
MOVX @DPTR,A MOVE DATA TO EXT. RAM,
INC DPTR INCREMENT PTR TO EXTERNAL RAM
DJNZ RS,NEXTI IS IT THE LAST I-BYTE?
POP RCB YES, RESTORE THE CONTENTS OF RCB
RETI I RETl1RII
,* ••• *******.*** •• TRANSMIT SUBROUTINE *************.**** •• **
TRAN: MOV DPTR,#200R EXT. RAM TRANSMIT BUFFER START
MOV RS,#OFFH EXT. RAM TRANSMIT BUFFER LENGTH
MOV A,loASH CONTROL STATE
WA:IT: CJNE A,SIUST,WAIT WA:IT FOR CTRL BY'l'E XMISS:ION
MOVX A,@DPTR MOVE DATA FROM EXT. RAM TO Ace.
MOV @Rl,A MOVE DATA INTO :INT. RAM @ (TBS)
INC DPTR INCREMENT POINTER
DJNZ RS,NXTI IS :IT THE LAST :I-BYTE ?
MOV S:IUST,#57H NO.' XMIT THE LAST I-BYTE
RET RETl1RII.
NXTI: MOV S:IUST,#S7H KEEP "BYP" IN CONTROL STATE(A8H).
MOV A,.OBOH I DMA-LOOP STATE
JMP WAIT TRANSM:IT THE NEXT BYTE
END
292019-36
15-54
FLEXIBILITY IN FRAME SIZE WITH THE 8044
$DEBUG NOHODSl
$INCLUDE (REG44. PDF)
ASSEMBLY CODE FOR SECONDARY STATIONS (MULTIPOINT)
AUTO MODE; FCS OPTION
ORG OOH
SJHP INIT
ORG OBH VECTOR ADDRESS FOR TlHERO INT.
JHP REC
ORG 13H VECTOR ADDRESS FOR EXT. INT. 1
JHP XINTl
'ORG 23H VECTOR ADDRESS FOR SIU INTERRUPT
JHP SIINT
,********········***INITIALIZATION •••••••••••••••••••••••••••
ORG 26H
INIT: MOV SMD,U1010100B INT. CLKED @ 375KINRZI-l;PFS-l
HOV STAD,'SSH STATION ADDRESS; STAD-44H FOR THE
OTHER STATION
MOV RDS,UOH INT. RAN RECEIVE BUFFER START
MOV RBL, 'OOH INT. RAN RECEIVE BUFFER LENGTH
MOV Rl,#20H
MOV TBS,Rl INT. RAN XKIT BUFFER START
MOV TBL, 'OlH INT. RAN XKIT BUFFER LENGTH
MOV NSNR,tOOH NS~NR-O
MOV TCON,#OOOOOlOOBEXT. INT.: EDGE TRIGGERED
MOV IE,'OOOlOllOB SI~l; ETO~l; EXO=l
MOV IP"OOOOOOlOB TlHER 0: PRIORITY 1
MOV THOD,#OOOOOllB COUNTER FUNCTION: MODE
MOV STS,t01000010B RECEIVE I-FRAME.
MOV TLO"OF8H SET COUNTER TO OVERFLOW
AFTER B COUNTS
5ETB TRO TURN ON COUNTER
SETB EA I ENABLE ALL INTERRUPTS
DOT: SJHP DOT I WAIT FOR AN INTERRUPT. 292019-37
I CPU IS INTERRUPTED AT THE END OF RECEPTION (51 SET), AND AT.
; THE END OF LONG-FRAME TRANSMISSION (EXO SET). •
,****** •• *******EXTERNAL INTERRUPT •••••••••••••••••••••••••••
XINT1: SETB Pl. 7 ; DISABLE CTS PIN
RETI ; RETURN.
;•• *•••••••••••• SERIAL INTERRUPT ROUTINE ••••••••••••••••••••
SIINT: CLR SI
JB AM,HOP ADDRESS MATCHED?
CLR EA DISABLE ALL INTERRUPTS
MOV STS,#OlOOOOlOB RBE-l; NB=l
~OV TLO,#OF8H
SETB TRO TURN ON COUNTER 0
SETS EA ENABLE ALL INTERRUPTS
RETI RETURN.
;
HOP: JB TBF,GETI A FRAME TRANSMITTED?
SETB TBF ENABLE TRANSMISSION OF I-FRAME
CLR Pl.7 ENABLE CTS PIN
ACALL TRAN CALL TRANSMIT ROUTINE
GETI.: JB RBE,RETURN A FRAME RECEIVED?
CLR EA DISABLE ALL INTERRUPTS
SETB RBE PUT RUPI IN RECEIVE MODE
MOV TLO, ,OF8H
SETB THO TURN ON COUNTER 0
SETB EA ENABLE ALL INTERRUPTS
RETURN: RETI RETURN. 292019-38
,*.* •••••••••••••• TRANSMIT SUBROUTINE *.* ••••••••••••••••••••
TRAN: MOV DPTH,UOOH EXT. RAN TRANSMIT BUFFER START
MOV RS"OFFH EXT. RAN TRANSMIT BUFFER LENGTH
MOV A"OABH CONTHOL STATE
WAIT: CJNE A,SIUST,WAIT WAIT FOR CONTROL BYTE TRANSMISSION
MOVX A,@DPTR MOVE DATA FROM EXT. RAN TO ACC.
MOV @Rl,A MOVE DATA INTO INT. RAN AT @TDS
INC DPTH INCREMENT POINTER
DJNZ RS,NXTI IS IT THE LAST I-BYTE ?
MOV SIUST, '57H XMIT THE LAST I-BYTE
RET RETURN.
NXTI: MOV SIUST,157H KEEP "BYP" 'IN CONTROL STATE
MOV A,'OBOH DHA-LOOP STATE
JHP WAIT TRANSMIT THE NEXT BYTE
292019-39
15-55
FLEXIBILITY IN FRAME SIZE WITH THE 8044
,**********RECEIVE INTERRUPT ROUTINE ••••••••••••••••••••••••••
REC, CLR TaO TURN OFF COUNTER 0
MOV DPTR,f200H EXT. RAM RECEIVE BUFFER START
MOV RS,#OFFH EXT. RAM RECEIVE' BUFFER LENGTH
MOV A,I08H ADDRESS STATE
HOLD, CJNE A,SIUST,HOLD WAIT FOR ADDRESS BYTE
MOV SIUST,tOEFH MOVE "BYP" INTO CONTROL STA'l'E
SKIP THE ADDRESS STATE '.
MOV A,fl8H PUSH-l STATE
WAITl, CJNE A,SIUST,WAITl WAIT FOR THE ADDRESS BYTE
MOV A,RCB MOVE THE RECEIVED ADDRESS BYTE TO ACC.
CJNE A,STAD,WAIT2 ADDRESS MATCHED?
SJMP WAIT3 YES.
WAIT2, MOV RCB,'OOOlOOOOB MOVE INFO. CONTROL BYTE TO RCB
MOV SIUST,foCFH MOVE "BYP" INTO BOV-LOOP STATE
RETI RETURN
;
WAIT3' MOV SIUST,'OEFH MOVE "BYP" INTO CONTROL STATE
MOV A,#l8H PUSH-l STATE
WAIT4, CJNE A,SIUST,WAIT4 WAIT FOR THE CONTROL BYTE
MOV A,RCB MOVE RECEIVE CONTROL BYTE INTO ACC.
JB ACC.O,RTRN IF NOT AN I-FRAME RETURN
PUSH RCB SAVE RECEIVE CONTROL BYTE
NEXTI, MOV SlUST,'OEFH ·PUSH "BYP" INTO CONTROL STATE (lOH) •
MOV A,#l8H PUSH-l STATE
WAIT5, CJNE A,SIUST,WAIT5 WAIT FOR AN 'I-BYTE
MOV A,RCB MOVE RECEIVED I-BYTE INTO ACC.
MOVX @DPTR,A MOVE DATA TO EXT. RAM
INC DPTR INCREHBNT PTR TO EXTERNAL RAM
DJNZ R5,NEXTl IS IT THE LAST I-BYTE?
POP RCB YES. RESTORE THE CONTENTS OF RCB
RTRN, RETI RETURN
END
292019-40
15-56
intJ ARTICLE
REPRINT
AR-307
NOVEMBER 1983
January 1985
© INTEL CORPORATION ORDER NUMBER 230876-001
230876-1
15-57
intJ AR-307
SUMMARY acknowledgements, error checking/recovery, and data
The 8044 offers a lower cost and higher performance transparency are not standardized nor supported by
solution to networking microcontrollers than conven- available data comm chips. .
tionalsolutions. The system cost 'is lowered by
integrating an entire microcomputer with an intelligent
SDLC, Synchronous Data Link Control, meets the
HDLC/SDLC communication processor onto a single
requirements for communications link design. The
chip. 1'he higher performance is realized by integrating
physical medium can be used on two or four wire
two processors running concurrently on one chip; the
twisted pair with inexpensive transceivers and connec-
powerful 80S I microcontroller and the Serial Inter-
tors. It can also be interfaced through modems, which
face Unit. The 8051 microcontroller is substantially
allows it to be used on broadband networks, leased
off-loaded from the communication tasks when
or switched telephone lines. VLSI controllers have
using the AUTO mode. In the AUTO mode the SIU
been available from a number of vendors for years;
handles many of the data link functions in hardware.
higher performance and more user friendly SDLC con-
The advantages of the AUTO mode are: less software
trollers continue to appear. SDLC has also been
is required to implement a secondary station data link,
designed to be very reliable. A 16 bit CRC checks the
the 8051 CPU is offloaded, and the turn-around time
integrity of the received data, while frame number-
is reduced, thus increasing the network throughput.
ing and acknowledgements are also built in. Using
Currently the 8044 is' the only microcontroller with
SDLC, up to 254 stations can be uniquely addressed,
a sophisticated communications processor on-chip. In
while HDLC addressing is unlimited. If an RS-422
the future there will be more microcontrollers available
only requires a single +5 volt power supply.
following this trend.
INTRODUCTION What will the end user pay for the added value pro-
Today microcontrollers are being designed into vided by communications? The cost of the com-
virtually every type of equipment. For the household, munications hardware is not the only additional cost.
they are turning up in refrigerators, thermostats, There will be performance degradation in the main
burglar alarms, sprinklers, and even water softeners. application because the microcontroller now has
At work they are found in laboratory instruments, additional tasks to perform. There are two extremes
copiers, elevators, hospital equipment, and t~lephones. to the cost of adding communication capability. One
In addition, a lot of microcomputer equipment con- could spend very little by adding an I/O port and have
tains more than orie microcontroller. Applications the CPU handle everything from the baud rate to the
using multiple microcontrollers as well, as the office protocol. Of course the main application would be
and home, are now faced with the same requirements idle while the CPU was communicating. The other ex-
that laboratory instruments were faced with 12 years treme would be to add another microcontroller to
ago - they need to connect them together and have the system dedicated to communications. This
them communicate. This need was satisfied in the communications processor could interface to the main
laboratory with the IEEE-48B General· Purpose CPU through a high speed parallel link or dual port
Instrumentation Bus (GPIB). However, GPIB does RAM. This approach would maintain system per-
not meet the current design objectives for network- formance, but it would be costly.
ing microcontrollers.
Today there are many communications schemes and Adding HDLe/SDLC Networking Capability
protocols available; some of the popular ones are Figure I shows a microcamputer system with a can-
GPIB, Async, HDLC/SDLC, and Ethernet. Common ventianal HDLC, SDLC cammunications salutian.
design objectives of today's networks are: low cost, The additional hardware needed to realize the con-
reliable, efficient throughput, and expandable. In ventional design is: an HOLC SOLC communicatian
examining available solutions, GPIB does not meet chip. additional ROM for the communicatian saftware.
these design objectives; first, the cable is too expen- part af an interrupt cant railer. a baud rate generatar. a
sive (parallel communications), second, it can only be phase lacked laap. NRZI encaded decader. and a
cable driver lacked loap are used when the transmitter
used over a limited distance (20 meters), and third,
it can only handle a limited number of stations. For daes nat send the clack an a separate line fram the data
general networking, serial communications is (i.e. aver telephane lines. ar two. wire cable). the NRZI
encader decader is used in HOLC SDLC to. combine
preferable because of lower cable costs and higher
the clack into. the data line. A phase locked laap is used
reliability (fewer connections). While Ethernet pro-
to recaver the clock fram the data line.
vides very high performance, it is more of a system
backbone rather than a microcontroller interconnect.
Async, on the other hand, is inexpensive but it is not The majority of tire available communication chips
an efficient protocol for data block or file transfers. provide a limited number of data link control func-
Even with.some new modifications such as a 9 bit pro- tions. Most of them will handle Zero Bit Inser-
tocol for addressing, important functions such as tion/Deletion (ZBI/D), Flags, Aborts, Automatic
230876-2
15-58
inter AR-307
SERIAL
MICROCONTROLLER COMMUNICATIONS
SOLC/HOLe
BAUD
RATE
GENERATOR
Figure 1. Conventional mlcrocontroller networking solution
address recognition, and CRC generation and check- require I LSI chip and about 10 TTL chips. The cost
ing. It is the CPU's responsibility to manage of CPU throughput degradation can be even greater.
link access, command recognition and response, The percentage of time the CPU has to spend servic-
acknowledgements and error recovery. Handling these ing the communication tasks can be anywhere from
tasks can take a lot of CPU time. In addition, servic- 10-1001170, depending on the serial bit rate. These high
ing the transmission and reception of data bytes can costs will prevent consumer acceptance of network-
also be very time consuming depending on the method ing microcomputer equipment.
used.
A Highly Integrated, High Performance Solution
The 8044 reduces the cost of networking micro-
U sing a D M A controller ca n increase the overall system
controllers without compromising performance. It
performance. since it can transfer a block of data in
contains all of the hardware components necessary to
fewer clock cycles than a CPU. In addition. the CPU
implement a microcomputer system with communica-
and the DMA controller can mUltiplex their access to
tions capability, plus it reduces the CPU and software
the bus so that both can be running at virtually the same
overhead of implementing HDLC/SOLC. Figure 2
time. However. both the DMA controller and the CPU
shows a functional block diagram of the 8044.
are sharing the same bus. therefore. neither one get to
utlize IOO~; of the bus bandwidth. Microcontrollers
available today do not support DMA. therefore. they
The 8044 integrates the powerful 80S I microcontroller
would have to use interrupts. since' polling is with an intelligent Serial Interface Unit to provide a
unacceptable in a multitasking environment.
single chip solution which efficiently implements a
distributed processing or distributed control system.
The microcontroller is a self sufficient unit contain-
In an interrupt driven, the CPU has overhead in ad- ing ROM, RAM, ALU and its own peripherals. The
dition to servicing the interrupt. During each inter- 8044's architecture and instruction set are identical to
rupt request the' CPU has to save all of the important the 80S 1~s. The Serial Interface Unit (SIU) uses
registers, transfer a byte, update pointers and bit synchronous HOLC/SOLCprotocol and can com-
counters, then restore all of its registers. At low bit municate at bit rates up to 2.4 Mbps, externally
rates this overhead may be insignificant. However, the clocked, or up to 37S Kbps using the on-chip digital
percentage of overhead increases linearly with the bit phase locked loop. The SIU contains its own pro-
rate. At high bit rates this overhead would consume cessor, which operates concurrently with the micro-
all of the CPU's time. There is another nuisance fac- controller.
tor associated with interrupt driven systems, interrupt
latency .. Too much interrupt latency will cause data The CPU and the SIU, in the 8044, interface through
to be lost: from underrun and overrun errors. 192 bytes of dual port RAM. There is no hardware
arbitration in the dual port RAM. Both processor's
The additional hardware necessary to implement the memory access cycles are interlaced; each processor'
communications solution, as shown in Figure I, would has access every other clock cycle. Therefore, there
230876-3
15-59
inter AR-307
I
1 SIU
1
,..------'-.., .1
I HDLC/SDLC
COMMUNICATIONS
PROCESSOR
8051
MICRO-
CONTROLLER
DMA
CONTROLLER
L __________ ___ _ ~
Figure 2. 8044 single chip mlcrocontroller networking solution
is no throughput loss in either processor as a result transmitted or received. Also, the nuisance of over-
of the dual pon RAM, and execution times are deter- run and underrun errors is totally eliminated since the
ministic: Since this has· always been the method for dedicated DMA controller is guaranteed to meet the
memory access on the 8051 microcontroller, 8051 pro- maximum data rates. Having a dedicated DMA con-
grams have the same execution time in the 8044. iroller means that the .serial channel interrupt can be
the lowest priority, thus allowing the CPU to have
By integrating all of· the .communication· hardware higher priority real time interrupts.
onto the 8051 microcontroller, the hardware cost of
the system is reduced. ·Now several chips have been Figure 3 sho'ws a c~mparison between the.conventionai
integrated into a single chip. This means that the and the 8044 solution on the percentage of time the
system power is reduced, P.C. board space is re- CPU must spend sending data. This diagram was
duced, inventory and assembly is reduced, and derive.d by assuming a 64 byte information frame is
reliability is improved. The improvement in reli- being transmitted repeatedly. The conventional solu-
ability is a result of fewer chips and interconnections tion is interrupt driven, and each interrupt service
on the P.C.board. routine is assumed to take about 15 instructions with
a I /oIsec instruction cycle time. At 533 Kbps, an in-
As·mentioned before, there can be two extremes in terrupt would occur every 15 usec. Thus, the CPU
a design which adds communications to the microcom- becomes completely dedicated to servicing the serial
puter system. The 8044 solution uses the high end ex- communications. The conventional design could not
treme. The SIU on the 8044 contains its own processor support bit rates higher than this because of under-
which communicates with the 8051 processor through runs .and overruns. For the 8044 to repeatedly send
dual port RAM and control/status registers. While 64 byte frames, it simply has to reinitiaIize the DMA
the SIU is not a totally independent communications controller. As a result, the 8044 can support bit rates
processor, it substantially offloads the 805 I processor up to 2.4 Mbps.
from the communication tasks.
Some of the other communications tasks the CPU has
Tbe DMA on the 8044 is dedicated to the SIU. It can- to perform. such as link access. command recogni-
not access external RAM. By having a DMA controller tion/response. and acknowledgements. are per-
in the SIU, the 8051 CPU is oftloaded. Asa result formed automatically by the SIU in a mode called
of the dual pon RAM design, the DMA does not share "AUTO;" The combination of the dedicated DMA
the running at full speed while .the frames are being controller and the AUTO mode. substantially offload
230876-4
15-60
inter AR-307
• CONCURRENT PROCESSING
CONVENTIONAL
SOLUTION
90
80
70
PERCENTAGE OF 60
CPU TIME SPENT 50
SERVICING SOLC 40
30
20 80.44
SOLUTION
1~~__-=====================~
250 K 500 K 750K 1M
BIT RATE (BITS/SECOND)
Figure 3. SIU offloads CPU
the CPU, thus allowing it ,to devote more of its power can directly set a bit Which communicates to the
to other tasks, primary what its transmit and receive buffering status
is.
8044's Auto Mode
In the AUTO mode'the SlU implements in hardware When the CPU wants to send a frame, it loads the
a subset of the SOLC protocol such that it responds . transmit buffer with the data, loads the starting
to many SOLC commands without CPU intervention. address and the COUrit of the data into the SIU, then
All AUTO mode responses to the primary station con- sets TBF to transmit the frame. The SIU waits for the
form to IBM's SOLC definition. In the AUTO mode primary station to poll it with a RR command. After
the 8044 can only be a secondary station operating the SIU is polled, it automatically sends the informa-
in SOLC specified "Normal Response Mode." tion frame to the primary with the proper control field.
Normal Response Mode means that the secondary The SIU then waits for a positive acknowledgement·
station· can not transmit unless it is polled by the from the primary before incrementing the Ns field and
primary station. The SIU in the AUTO mode can interrupting the CPU for more data. If a negative
recognize and respond to the. following SOLC com- acknowledgement is received, the SIU automatically
mands without CPU intervention: I (Information), RR retransmits the frame.
(Receive Ready), RNR (Receive Not Ready), REJ (Re-
ject), and for loop mode UP (Unnllmbered Poll). The When the 8044 is ready to receive information, the
.SIU can generate the following responses without CPU loads the receive buffer starting address and the
CPU intervention: I, RR, and RNR. In addition, the buffer length into the SIU, then.enables the receiver.
SIU manages Ns and Nr in the control field. If it When a valid information frame with the correct
detects an error in either Ns or Nr, it interrupts 'the address and CRe is received, the SIU will increment
CPU for error recovery. the Nr field, disable the receiver and interrupt the CPU
indicating that a good I frame has been received. The
How does the SIU know what responses to send to CPU then sets RBP, reenables the receiver and pro-
the primary? It uses two status bits which are set by cesses the received data. By enabling the receiver with
the CPU. The two bits are TBF (Transmit Buffer Full) RBP set, the SIU will automatically respond to polls
and RBP (Receive Buffer Protect). TBF indicates that with a Receive Not Ready, thus keeping the link
the CPU wants to send data, and RBP indicates that moving rather than timing out the primary from a
the receive data buffer is full. Table I shows the disabled receiver, or interrupting the CPU with
responses the SIU will send based on these two status another poll before it has 'processed the data. After
bits. This is an innovative approach to communica- the data has been processed, the CPU clears RBP,
tion design, The CPU in the 8044 with one instruction returning to the Receive Ready responses.
230876-5
15-61
AR-307
Table 1. SIU's automatic responses II) auto mode
'STATUS BITS RESPONSE
TBF RBP
o o (RR) Receive ready
o 1 (RNR) Receive' not ready
1 o (I) Information
1 1 (I) ·Information
SDLC communications can be broken up into four In the Information Transfer State there are three com-'
states: Logical Disconnect State, Initialization State, mon events which occur as illustrated in Figure 4, they
Frame Reject State, and Information Transfer State. are: I) the primary polls the secondary and the secon-
Data can only be transferred in the Information dary is ready to receive but has nothing to send, 2)
Transfer State. More than 90070 of the time a station the primary sends the secondary information, and 3)
will be in the Information Transfer State, which is the secondary sends information to the primary.
where the SIU can run autonomously. In the other Figures 5, 6, and 7 compare the functions the con-
states, where error recovery, online/offline, and in- ventional design and the 8044 must execute in order
itialization takes place, the CPU manages the protocol. to respond to the primary for the cases in Figure 4.
PRIMARY
ISECONDARY I I SECONDARY I
Case 1. Primary polls secondary
secondary has nothing to send
. .
Command Response
RR
RR
Case 2. Primary polls secondary ,
secondary sends Information frame
Command Response
RR,NR ..
...
RR, NR+1 ..
Information frame
Case 3. Primary sends secondary information frame
Command Response
RR ..
...
Information frame
'RR,NR
. .
RR, NR+1
Not~: RR = Recelv.e ready
Figure 4. SDLC commands ,and responses in the Information transfer state
230876-6
15-62
intJ AR-307
CASE 1
8044 CONVENTIONAL
AUTO MODE PRIMARY DESIGN
-RR- Receive interrupts
Poll
Decode received control field
Check NR field
Load response into transmit control field
Send frame
Transmit interrupts
Figure 5. Primary polls secondary, secondary has· nothin~ to send
CASE 2
8044 CONVENTIONAL
·AUTO MODE PRIMARY DESIGN
Load transmit buffer Load transmit buffer and transmit
control byte
Set TBF bit
-.._ - RR _.- - 1 1...- Receive interrupts
poll Decode receive control byte
Check NR field
Send frame
Transmit interrupts
..........- - RR -___ Receive interrupts
poll Decode receive control byte
Transmit Interrupt Check NR field
Increment NS
Figure 6. Primary polls secondary. secondary sends information frame
230876-7
15-63
inter AR-307
CASE 3
8044 CONVENTIONAL
AUTO MODE PRIMARY' DESIGN
----RR~ Receive interrupts
poll Decode received control field
Check NR field
Load response into transmit control
field
Send frame
Transmit interrupts
Receive interrupt ~Iframe_ Receive interrupts
Decode receive control field
Check NS NR fields
Increment NR
Load response into transmit control
field
Send frame
Transmit Interrupts
,
Figure 7. Primary sends information frame to secondary
Using case 1 as an example, the conventional design . most critical parameter for calculating throughput on
first gets receive interrupts bringing the data from the any high speed network is the station turnaround time;
SOLC comm chip into memory. The CPU must then the time it takes a station to respond after receiving,
decode the command in the control field and deter- a frame. Since the 8044 handles all of the commands
mine the response. In addition, it must check the Nr and responses of the Information Transfer State in
field for any pending acknowledgements. The CPU hardware, the turnaround time is much faster than
loads the transmit buffer with the appropriate address handling it in software, hence a higher throughput.
and control field, then transmits the frame. When the
8044 receives this frame in AUTO mode, the CPU 8044's Flexible Mode
never gets an interrupt because the SIU handles the In the "NON-AUTO" mode or Flexible mode, the
entire frame reception and response automatically. SIU does not recognize or respond to any commands,
nor does it manage acknowledgements, which means
In SOLC networks, when there is no information the CPU must handle link access, command recogni-
transfers, case 1 is the activity on the line. Typically tion/response, acknowledgements and error recovery
this is 80010 of the network traffic. The CPU in the by itself. The Flexible mode allows the 8044 to have
conventional design would constantly be getting in- extended address fields and extended control fields,
terrupts and servicing the communications tasks, even thus providing HOLC support. In the Flexible mode
when it has nothing to send or receive. On the other the 8044 can operate as a primary station, since it can
hand, the 8044 CPU would only get involved in com- transmit without being polled.
municating when it has data to send pr receive.
Front End Communications Processor
Having the SIU implement a subset of the SOLC pro- Tile 8044 can also be used as an intelligent
tocol in hardware not only offloads the CPU, but it HOLC/SOLC front end for a microporcessor, capable
also improves the throughput on the network. The of extensively off-loading link control functions for
230876-8
15-64
AR-307
the microporcessor. In some applications the 8044 can computer. Sophisticated secondary stations could also
even be used for communications preprocessing, in take advantage of this design.
addition to data link control. For this type of design
the 8044 would communicate to the Host CPU Since the 8044 has ROM on chip, all the communica-
through a FIFO, or dual port RAM. A block diagram tions software is non-volatile. The 8044 primary
of this design is given in Figure 8. A tightly coupled station could down-line-load software to 8044 secon-
interface between the 8044 and the Host CPU would dary stations. Once down-line-loading is implemented,
be established. The Host CPU would give the 8044 software updates to the primary and secondary
high level commands and data which the 8044 would stations could be done very inexpensively. The only
convert to HOLC/SOLC. This . particular type of things which would remain fIXed in ROM are the
design would be most appropriate for a primary HOLC/SOLC communications software and the soft-
Station which is normally a micro, mini, or mainframe ware interface to the HOST.
SYSTEM
HOST MEMORY
SYSTEM DATA BUS
INTERFACE
HARDWARE
8044 DATA BUS
8044
EXPANSION
MEMORY
HDLC/SDLC DATA LINK
Figure 8. 8044 front end processor
230876-9
15-65
inter ICETM·5100/044In·Circuit Emulator
for the RUPITM·44 Family
• Precise, Full-Speed, Real-Time
Emulation of the RUPITM-44 Family of • Symbolic Debugging Enables Access to
Memory Locations and Program
Peripherals Variables
• 64 KB of Mappable High-Speed
Emulation Memory
• Four Address Breakpoints Plus In-
Range, Out-of-Range, and Page Breaks
• 254 24-bit Frames of Trace Memory (16
Bits Trace Program Execution • Equipped with the Integrated Command
Directory (ICDTM) That Provides
Addresses and 8 Bits Trace Eternal - On-Line Help
Events) - Syntax Guidance and Checking
- Command Recall
• Serial Link to Intel Series III/IV or IBM*
PC AT or PC XT (and PC DOS
• On-Line Disassembler and Single-Line
Compatibles) Assembler to Help with Code Patching
• ASM-51 and PL/M-51 Language
Support
• Provides an Ideal Environment for
Debugging BITBUSTM Applications
• Built-in CRT-Oriented Text Editor Code
The ICETM-5100/044 in-~ircuit emulator is a high-level. interactive debugger that is used to develop and test
the hardware and software of a target system based on the RUPITM-44 family of peripherals. The ICE-
5100/044 emulator can be serially linked to an Intellec® Series III/IV or an IBM PC AT or PC XT. The emulator
can communicate with the host system at standard baud rates up to 19.2K. The design of the emulator
supports all of the RUPI-44 components at speeds up to and including 12 MHz.
·IBM is a registered trademark of International Business Machines Corporation. Intel Corporation assumes no responsibility
for the use of any circuitry other than circuitry embodied in an Intel product. No other patent licenses are implied. Information
contained herein supersedes previously published specifications on these devices from Intel.
280325-1
November 1988
15-66 Order Number: 280325-001
ICETM·5100/044
PRODUCT OVERVIEW tion of the microcontroller to debug the system as a
completed unit.
The ICE-51001044 emulator provides full emulation
support for the RUPI-44 family of peripherals, includ- The final product verfication test can be performed
ing 8044-based BITBUSTM board products. The using the ROM or EPROM version of the microcon-
RUPI-44 family consists of the 8044, the 8744, and troller. Thus, the ICE-51001044 emulator provides
the 8344. ' the ability to debug a prototype or production system
at any stage in its development without introducing
The ICE-5100/044 emulator enables hardware and extraneous hardware or software test tools.
software development to proceed simultaneously.
With the ICE-5100/044, prototype hardware can be
added to the system as it is designed and software, PHYSICAL DESCRIPTION
can be developed prior to the completion of the
hardware prototype. Software and hardware integra- The ICE-5100/044 emulator consists of the follow-
tion can occur while the product is being developed. ' ing components (see Figure 1):
• Power supply
The ICE-5100/044 emulator assists four stages of
• AC and DC power cables
development: .
• Controller pod
• Software debugging
• Serial Cable (host-specific)
• Hardware debugging
• User probe assembly (consisting of the proces-
o System integration
sor module and the user cable)
• System test • Crystal power accessory (CPA)
• 40-pin target adaptor
Software Debugging It Clips assembly
The ICE-5100/044 emulator can be operated with- • Software (includes the ICE-5100/044 emulator
software, diagnostic software, and a tutorial)
out being connected to the target system and before
any of the user's hardware is available (provided ex-
ternal data RAM is not needed). In this stand-alone The controller pod contains 64 KB of emulation
mode, the ICE-5100/044 emulator can be used to memory, 254- by 24-bit frames of trace memory, and
facilitate program development. the control processor. In addition, the controller pod
houses. a BNC connector that can be: used to con-
nect up to 10 multi-ICE compatible emulators for
synchronous starting and stopping of emulation.
Hardware Debugging
The ICE-51001044 emulator's AC/DC parametric The serial cable connects the host system to the
characteristics match the microcontroller's. The em- controller pod. The serial cable supports a subset of
ulator's full-speed operation makes it a valuable tool the RS-232C signals.
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces. The user probe assembly consists of a user cable
and a processor module. The processor module
houses the emulation processor and the interface
System Integration logic. The target adaptor connects to the processor
module and provides an electrical and mechanical
Integration of software and hardware can begin , interface to the target microcontroller socket.
when the emulator is plugged into the microcontrol-
ler socket of the prototype system hardware. Hard- The crystal power accessory (CPA) is a small, de-
ware can be added, modified, and tested immediate- tachable board that connects to the controller pod
ly. As each section of the user's hardware is com- and enables the ICE-5100/044 emulator to run in
pleted, it can be added to the prototype. Thus, the stand-alone mode. The target adaptor plugs into the
hardware and software can be system tested in real- socket on the CPA; the CPA then supplies clock and
time operation as each section becomes available. power to the user probe.
The clips assembly enables the user to trace exter-
System Test nal events. Eight bits of data are gathered on the
rising edge of PSEN during opcode fetches. The
When the prototype is complete, it is tested with the clips information can be displayed using the CLIPS
final version of the system software. The ICE- option with the PRINT command.
5100/044 emulator is then used for real-time emula-
15-67
ICETM·5100/044
280325-2
Figure 1. The ICETM·51001044 Emulator Hardware _
The ICE-5100-044 emulator software supports mne- troller of the target system. ElTlulation is a transpar-
monics, object file formats, and symbolic references ent process that happens in real-time. ,The executi_on
generated by Intel's ASM-51 and PL/M-51 program- of the user software is facilitated with the ICE-
ming languages~ Along with the ICE-5100104.4 emu- S100/044 command language.
lator -software -is a customer confidence test disk - - --
with diagnostic routines that check the operation of
the hardware. Memory Mapping
The on-line tutorial is written in the ICE-5100 com- There is a 64 KB of memory that can be mapped to
mand language. Thus, the user is able to interact the CODE memory space in 4. KB blocks on 4 KB
with and use the ICE-51001044 emulator while exe- boundaries. By _mapping -'memory to _the ICE-
cuting the tutorial. 5100/044 emulator, software development.can pro-
ceed b~fore the user hardware is available.
A comprehensive set of documentation is provided
with the ICE-51 001044 emulator.
Memory Examination and Modification
ICETM·5100/044 EMULATOR The memory space for the 8044 microcontroller and
FEATURES its target hardware is fully accessible through the
emulator. The ICE-5100/044 emulator refers to four
The ICE-51 00/044 emulator has been created to as- physically _distinct memory spaces, as follows: -
sist a product designer in developing, debugging and • CODE....,..references program memory
testing designs incorporating the RUPI-44 family of
• IDATA-"--references internal data memory
peripherals. -The following sections detail some of
the ICE-51 001044 emulator features. • RDATA-references special function' register
, memory -
• XDATA-references external data memory
Emulation
ICE-5100/044 emulator commands that access
Emulation is the controlled execution of the user's memory use one of the special prefixes (e.g., CODE)
software in the target hardware or in an artificial to specify the memory space.
hardware environment that duplicates the microcon-
15-68
inter ICETM-5100'044
The microcontroller's special function registers and Breakpoint Specifications
register bits can be accessed mnemonically (e.g.,
OPt.:, TCON, CY, P1.2) with, the ICE-51 00/044 emu- Breakpoints are used to halt a user program in order
lator software. to examine the effect of the program's execution on
the target system. The ICE-51 00/044 emulator sup-
Data can be displayed or modified in one of three ports three different types of break specifications:
bases: hexadecimal, decimal, or binary. Data can
also be displayed or modified in one of two formats: • Specific address break-specifying a single ad-
dress point at which emulation is to be stopped.
ASCII or unsigned integer. Program code can be dis-
assembled and displayed as ASM-51 assembler • Range break-an arbitrary range of addresses
mnemonics. Code can be modified with standard can be specified to halt emulation. Program exe-
ASM-51 statements using the built-in single-line as- cution within or, optionally, outside the range
sembler. halts emulation.
• Page break-up to 256 page breaks can be spec~
Symbolic references can be used to specify memory , ified. A page break is defined as a range of ad-
locations. A symbolic reference is a procedure dresses that is 256-bytes long and begins on a
name, line number, program variable, or label in the 256-byte address boundary.
user program that corresponds to a location.
Break registers are user-defined debug definitions
Some typical symbolic functions include: used to create and store breakpoint definitions.
• Changing or inspecting the value of a program Break registers can contain multiple breakpoint defi-
variable by using its symbolic name to access the nitions and can optionally call debug procedures
memory location. when emulation halts.
• Defining break and trace events using symbolic
references.
• Referencing variables as primitive data types.
Trace Specifications
The primitive data types are ADDRESS, BIT, Tracing can be triggered using speCifications similar
BOOLEAN, BYTE, CHAR (character), and to those used for breaking. . Normally, the
WORD. ICE-5100/044 emulator traces program activity
while the user program is executing. With a trace
The ICE-51 00/044 emulator maintains a virtual sym-
specification, tracing can be triggered to. occur only
bol table (VST) for program symbols. A maximum of
when specific conditions are met during execution.
61 KB of host memory space is available for the Up to 254 24-bit frames of trace information are col-
VST. If the VST is larger than 61 KB, the eXCeSS is
lected in a buffer during emulation. Sixteen of the 24
stored on available host system disk space and is
bits trace instruction execution addresses, and 8 bits
paged in and out as needed. The size of the VST is
capture external events (CLIPS).
limited only by the disk capacity of the host system.
'1~ ,. Print newest four instructions in the buffer
hlt>PRINT NEWEST 4
*'
FRAME ADDR CODE INSTRUCTIONS
(28) 300A C02A PUSH 2AH
(30 300C 2532 ADD A, 32H
(32) 300E F52A MOV 2AH, A
(34) 3010 B53210 CJNE A,32H, $+10H
hlt>
h1 t > PRINT CLIPS OLDEST 2
FRAME ADDR. CODE
'*
Buffer display showing clips
INSTRUCTIONS CLIPS (76543210)
*'
(00) 007AH 0508 INC INDX PTR 10101111
(01) 007CH 80E6 SJMP (#28) 00100010
Figure 2. Selected Trace Buffer Displays
- -
280325-3'
15-69
intJ ICETM·5100/044
The trace buffer display is similar to an ASM-51 pro- Procedures
gram listing as shown in Figure 2. The PRINT com-
mand enables the user to selectively display the Debugging procedures (PROCs) are a user-defined
contents of the trace buffer. The user has the option group of ICE-51 00/044 commands that are execut-
of displaying the clips information as well as dissas- ed as one command. PROCs enable the user to de-
sembled instructions. fine several commands in a named block structure.
The commands are executed by entering thename
of the PROC. The PROC bodies are a simple DO ...
END construct.
ARM FOREVER TIL USING TRACE <execute>
~>Gon,"
<expr>
hl t > GO FROM 13H
J
<operator> ARM FOREVER TIL USING TRACE
hl t > GO FROM 13H USING
13H USING brl
TRACE <execute>
hl t > GO FROM 13H USING brl TRACE
<expr> OUTSIDE PAGE FROM TIL <tr~reg name> <execute>
hlt>GO FROM 13H USING brl TRACE trace1t
<execute>
280325-4
Figure 3. The Integrated Command Directory for the GO Command
15-70
inter ICETM·5100/044
PROCs can simulate missing hardware. or software, tor's memory along with the user's code to enable
set breakpoints, collect debug information, and exe- rapid debug of 8044 BITBUS applications code.
cute high-level software patches. PROCs can be
copied to text files on disk, then recalled for use in DESIGN CONSIDERATIONS
later test sessions. PROCs can also serve as pro-
gram diagnostics, implementing ICE-51 00/044 emu- The height of the processor module and the target
lator commands or user-defined definitions for spe- adaptor need to be considered for target systems.
cial purposes. Allow at least 1% inches (3.8 cm) of space to fit the
prqcessor module and target adaptor. Figure 5
On·Line Syntax Menu shows the dimensions of the processor module.
A special syntax menu, called the Integrated Com- Execution of user programs that contain interrupt
mand directory (ICD), similar to the one used for the routines causes incorrect data to be stored in the
121CETM system and the VLSiCE-96 emulator, aids in trace buffer, When an interrupt occurs, the next in-
creating syntactically correct command lines. Figure struction to be executed is placed into the trace buff-
3 shows an example of the ICD and how it changes er before it is actually executed. Following comple-
to reflect the options available for the GO command. tion of the interrupt routine, the instruction is execut-
ed and again placed into the trace buffer.
Help
ELECTRICAL CONSIDERATIONS
The HELP command provides ICE-51 00/044 emula-
tion command assistance via the host system termi- The emulation processor's user-pin timings and
nal. On-line HELP is available for the ICE-5100/044 loadings are identical to the 8044 component, ex-
emulator commands shown in Figure 4. cept as follows.
• Up to 25 pF of additional pin capacitance is con-
BITBUSTM Applications Support tributed by th~ processor module .and target
adaptor assemblies.
The ICE-5100/044 emulator provides an ideal envi-
o Pin 31, EA, has approximately 32 pF of additional
ronment for developing applications code for BIT-
BUS board products such as the RCB-44/10, the capacitance loading due to sensing circuitry.
RCB-44/20, the PCX-344, and the iSBXTM-344 • Pins 18 and 19, XTAL1 and XTAL2 respectively,
board. have approximately 15-16 pF of additional capac-
itance when configured for crystal operation.
The BITBUS firmware, available separately as BIT-
WARE, can be loaded into the ICE-51 00/044 emula-
It>HELP
HELP is available for:
ADDRESS APPEND ASM BASE BIT BOOLEAN BRKREG
BYTE CHAR CI CNTL_C COMMENTS CONSTRUCTS COUNT
CURHOME CURX CURY DCI DEBUG DEFINE DIR
DISPLAY DO DYNASCOPE EDIT ERROR EVAL EXIT
EXPRESSION GO HELP IF INCLUDE .INVOCATION ISTEP
KEYS LABEL LINES LIST LITERALLY LOAD LSTEP
MAP MENU MODIFY MODULE MSPACE MTYPE NAMESCOPE
OPERATOR PAGING PARTITION PRINT PROC PSEUDO_VAR PUT
REFERENCE REGS REMOVE REPEAT RESET RETURN SAVE
STRING SYMBOLIC SYNCSTART TEMP CHECK TRCREG TYPES VARIABLE
VERIFY VERSION WAIT WORD WRITE
hlt>
l l \ - - - - - - - - - -________~~-· --------n 280325-5
Figure 4. HELP Menu
15-71
intJ ICETM·5100/044
PROCESSOR MODULE~ PIN 1
TOP VIEW
j
~ ~I~&J T
I·
H
CABLE BODY
39"
. (99 em) I
!
~~Z
!iis t
. z
i
4"
(10,2 em)
~
'i
---l
.
3':J/,."
rem)
SIDE VIEW
..
PROCESSOR MODULE
~-9;r··
TARGET
ADAPTOR
~
280325-6
Figure 5. Processor Module Dimensions
HOST REQUIREMENTS PHYSICAL CHARACTERISTICS
• IBM PC AT or PC XT (or PC DOS compatible)
with 512 KB of available RAM and a hard disk Controller Pod
running under the DOS 3.0 ( or later) operating
system. Width: 8-%" (21 cm)
• Intellec Series III/IV microcomputer development Height: 1-%" ( 3.8 cm)
system running the ISIS or iNDX operating sys-
Depth: 13-%" (34.3 cm)
tem respectively, with at least 512 KB of applica-
tion memory resident. Weight: 41bs ( 1.85 kg)
• Disk drives-dual floppy or one hard disk and one
floppy drive required.
User Cable
ICETM·5100/044 EMULATOR The user cable is 3 feet (approximately 1 m)
SOFTWARE PACKAGE
• ICE-51 00/044 emulator software Processor Module
• ICE-51 00/044 confidence tests
(With the target adaptor attached)
• ,ICE-51 00 tutorial software
Width: 3-1 0/16" (9.7 cm)
EMULATOR PERFORMANCE Height: 4" (10.2 cm)
Depth: 1-%" (3.8 cm)
Memory
Mappable 64 KB Mappable to user or ICE-
full-speed 5100/044 emulator mem- Power Supply
emulation code ory in 4 KB blocks on 4 KB
memory .~-,;' boundaries. Width: 7-%" (18.1 cm)
Height: 4" (10.06 cm)
Trace memory 254 x 24 bit frames
Depth: 11" (27.97 em)
Virtual Symbol A maximum of 61 KB of
Table host memory space is Weight 151bs ( 6.1 kg)
available for the virtual
symbol table (VST). The
rest of the VST resides on Serial Cable
disk and is paged in and The serial cable is 12 feet (3.6 m).
out as needed.
15-72
intJ ICETM·5100/044
ELECTRICAL CHARACTERISTICS Software Only
Order Code Description
Power Supply SA044D This kit contains the host, probe, di-
agnostic, and tutorial software on
100-120V or 200-240V (selectable) 5%" disks for use on an IBM PC AT
50-60 Hz or PC XT (requires DOS 3.0 or later).
2 amps (AC max) @ 120V [Requires software license.]
1 amp (AC max) @ 240V SA044S This kit contains the host, probe, di-
agnostic, and tutorial software on 8"
disks (both single-density and dou-
ENVIRONMENTAL ble-density) for use on a Series III,
CHARACTERISTICS and on 5-%" disks for use on a Se-
ries IV. [Requires software license.]
Operating temperature + 10°C to + 40°C (50°F to
104°F)
Other Usefullntel® MCS®-51 Debug and
Operating humidity Maximum of 85% relative Development Support Products
humidity, non-condensing
Order Code Description
D86ASM51 8051 Software Development Pack·
ORDERING INFORMATION age (DOS version)-Consists of the
ASM-51 macro assembler which
gives symbolic access to 8051 hard-
Emulator Hardware and Software ware features; the RL51 linker and
Order Code Description relocator program that links modules
generated by ASM-51; CONV51
1044KITAD This kit contains the ICE-51001044 which enables software written for
user probe assembly, power supply the MCS-48 family to be up-graded to
and cables, serial cables, target run on the 8051, and the LlB51 Li-
adaptor, CPA, ICE-5100 controller brarian which programmers can use
pod, software, and documentation for to create and maintain libraries of
use with an IBM PC AT or PC XT. The software object modules. Use with
kit also -includes the 8051 Software the DOS operating system (version
Development Package and the 3.0 or later).
AEDIT text editor for use on DOS
systems. [Requires software license.] D86PLM51 PL/M·51 Software Package (DOS
version)-Consists of the PL/M-51
1044KITD This kit is the same as the 1044KITAD compiler which provides high-level
excluding the 8051 Software Devel- programming language support; the
opment Package and the AEDIT text LlB51 utility that creates· and
editor. [Requires software license.] maintains libraries of software object
1044KITAS This kit contains the ICE-51001044 modules, and the RL51 linker and
user probe assembly, power supply relocator program that links modules
and cables, serial cables, target generated by ASM-51 and PL/M-51
adaptor, CPA, ICE-5100 controller and locates the linked object mod-
pod, software, and documentation-for ules to absolute memory locations.
use with Intel hosts (Series IIIIIV). Use with the DOS operating system
The kit also includes the 8051 Soft- (version 3.0 or later).
ware Development Package and the 186ASM51 8051 Software Development Pack·
AEDIT text editor for use on the Se- age (ISIS version)-Same as the
ries IIIIIV. [Requires software li- D86ASM51 package except this one
cense.] ,
is for use with the Series III.
1044KITS This kit is the same as the 1044KITAS 186PLM51 PL/M·51 Sofware Package-Same
excluding the 8051 Software Devel- as the D86PLM51 package except
opment Package and the AEDIT text this one is for use with the Series III
editor. [Requires software license.] and Series IV.
D86EDINL AEDIT text editor for use with the
DOS operating system.
15-73
MCS®-80 /85 Data Sheets 16
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intJ 8080A/8080A-1/8080A-2·
8-BIT N-CHANNEL MICROPROCESSOR
• TTL Drive Capability·
• Decimal, Binary, and Double Precision
• 2JJ,s (-1:1.3JJ,s, -2:1.5JJ,s) Instruction
Cycle
•
Arithmetic
Ability to Provide Priority Vectored
• Powerful Problem Solving Instruction
Set
•
Interrupts
512 Directly Addressed I/O Ports
• 6 General Purpose Registers and an
Accumulator • Available in EXPRESS
- Standard Temperature Range
• 16·Bit Program Counter. for Directly
Addressing up to 64K Bytes of Memory • Available in 40·Lead Cerdip and Plastic
Packages
• 16·Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
(See Packaging Spec. Order #231369)
Switching of the Program Environment
The Intel@ 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose
registers may be addressed individually or in· pairs. providing Qoth single and double precision operators.
Arithmetip and logical instructions set or reset4 testable flags. A fifth flag provides decimal arithmetic opera-
tion. .
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the
8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line
bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the
interface to memory and I/O are provided directly by the 8080A. Ultimate control of t~e address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
address and data busses into a high impedance state. This permits OR-tying these busses with other control-
ling devices for (DMA) direct memory access or multi-processor operati.on.
. NOTE:
The 8080A is functionally and electrically compatible with the Intel 8080.
November 1986
16-1 Order Number: 231453-001
8080AI8080A-1/8080A-2
IIBITI
INTEAt:aAL DATA ius
..~ ,It
,.,'"
S
:::a:
REG.
0 .,
REG.
,., ,., REGISTER
~
H L
REG. REG. ARRAV
"::! STACK POINTER ""
1111
PROGRAM COUNTER
1111
TIMING
AND
CONTROL
ACK
231453-1
Figure 1. Block Diagram
A,. A11
GND A,.
D. An
'D. Au
O. A,.
D, At
D3 A. '
D. A,
D,O 32 At
D.O 10 8OIIOA 31 As
-5V II 30 OAo
RESET 12 29 -'3
HOLD 13 28 +1ZV
INT 14 27 A.
~. IS 26 A,
18 Au
.,
17 24 WAIT
Wii 18 23 READY
SYNC 19 22
+5V 20 21 HLDA
231453-2
Figure 2. Pin Configuration
16-2
SOSOA/SOSOA-1/S0S0A-2
Table 1. Pin Description
Symbol Type Name and Function
A15-AO 0 ADDRESS BUS: The address bus provides the address to memory (up to 64K 8·bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
DrDo I/O DATA BUS: The data bus provides bi·directional communication between the CPU,
memory, and 110 devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 8080A outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNC 0 SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
DBIN 0 DATA BUS IN: The DBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the 8080A data
bus from memory or 110.
READY I READY: The READY signal indicates to the 8080A that valid memory or input data is
available on the 8080A data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the 8080A does not receive a
READY input, the 8080A will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.
WAIT 0 WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WR 0 WRITE: The WR signal is used for memory WRITE or 110 output control. The data on
the data bus is stable while the WR signal is active low (WR = 0).
HOLD I HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD stato
allows an external device to gain control of the 8080A address and data bus as soon as
the 8080A has completed its use of these busses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (Dr Do)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
HLDA 0 HOLD ACKNOWLEDGE: The HLDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
signal begins a t : · .
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLDA signal appears after the rising edge of cfJ2.
INTE 0 INTERRUPT ENABLE: Indicates the content of t.he internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is·reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.
INT I INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request. .
RESET1 I RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The,INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
Vss GROUND: Reference.
VDO POWER:. + 12 ±5% V.
Vee POWER: +5 ±5% V.
VBB POWER: -5 ±5% V.
cfJ1, cfJ2 CLOCK PHASES: 2 externally supplied clock phases. (non TTL compatible)
NOTE:
1. The RESET signal must be active for a minimum of 3 clock cycles.
16-3
8080A/8080A-1/8080A-2
, ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses abo.ve those listed under "Abso-
lute Maximum Ratings" may cause permanent dam~
Temperature Under Bias ............ O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature ,.......... - 65·C to + 150·C functional operation of the device at these or any
other conditions above those indicated in the opera-
All Input or Output Voltages
tional sections of this specification is not implied. Ex-
with Respect to Vss ........... - 0.3V to + 20V
posure to absolute maximum rating conditions for
Vcc, VDD and Vss extended periods may affect device reliability.
with Respect to Vss ...• '..••..• - 0.3V to + 20V
Power Dissipation .....•.................... 1.5W
D.C. CHARACTERISTICS
TA = O·C to 70·C, VDD = + 12V ±5%, Vcc = +5V ±5%, Vss = -5V ±5%, Vss = OV; unless otherwise
noted
Symbol Parameter Min Typ Max Unit Test Condition
VllC Clock Input Low Voltage Vss - 1 Vss + 0.8 V
VIHC Clock Input High Voltage 9.0 VDD +1 V
Vil Input Low Voltage Vss - 1 Vss + 0.8 V
VIH Input High Voltage 3.3 Vce +1 V
Val Output Low Voltage 0.45 V
} IOl = 1.9 rnA on All Outputs,
VOH Output High Voltage ' 3.7 V IOH = -150/LA.
IDD(AV) Avg. Power Supply Current (VDD) 40 70 rnA
ICC (AV) Avg. Power Supply Current (Vce> 60 80 rnA ) Ope-"
Tcy =0.48/Ls
IsS (AV) Avg. Power Supply Current (Vss) 0.01 1 rnA
III Input Leakage ±10 /LA Vss :s: VIN :s: Vcc
ICl Clock Leakage ±10 /LA Vss :s: VClOCK :s: VDD
IDl Data Bus Leakag'e'in Input Mode -100 /LA Vss:S: VIN :s: Vss + 0.8V
--'2.0 rnA Vss + 0.8V :s: VIN :s: VCC
IFl Address and Data Bus Leakage +10 VADDR/DATA = VCC
During HOLD -100 /LA
VADDR/DATA = Vss + 0.45V
CAPACITANCE 1,5 r-----r-----,---......,
TA = 25°C, Vcc = VDD = Vss = OV,Vss = -5V
Symbol Parameter Typ Max Unit Test Condition ~
a:
a:
Cq, Clock 17 25 pF fc= 1 MHz ~ 1.01---=""'".,.....=--+----j
Capacitance
Input
i
CIN 6 10 pF Unmeasured Pins
Capacitance O.50~-----:.=25---:'.50:---~.,5
COUT Output 10 20 pF Returned to Vss AMBIENT TEMPERATURE lOCI
Capacitance 231453-3
Typical Supply Current vs
Temperature. Normalized
Dol Supply/DoTA = -O.45%rC
16-4
8080A/8080A-1/8080A-2
A.C. CHARACTERISTICS (8080A), TA = 0·Ct070·C, voo = +12V ±5%, vee = +5V ±5%,
VBB= -5V ± 5%, VSS = OV; unless otherwise noted
Symbol Parameter
-1 -1 -2 -2 Unit Test Condition
Min Max Min Max Min Max
tey(3) Clock Period 0.48 2.0 0.32 2.0 0.38 2.0 /Ls
tr, tf Clock Rise and Fall Time 0 50 0 25 0 50 ns
t</>1 I </>1 Pulse Width 60 50 60 ns
td>2 I d>2 Pulse Width 220 145 175 ns
t01 Delay <1>1 to <1>2 0 0 0 ns
t02 Delay <1>1 to <1>2 70 60 70 ns
t03 Delay <1>1 to <1>2 Leading Edges 80 60 70 ns
tOA Address Output Delay From <1>2 200 150 175 ns
CL = 100 pF
too Data Output Delay From <1>2 200 180 200 ns
toe Signal Output Delay From <1>1 or <1>2
120 110 120 ns CL = 50 pF
(SYNC, WR, WAIT, HLDA)
tOF DBIN Delay From <1>2 25 140 25 130 25 140 ns
tOI(1) Delay for Input Bus to Enter Input Mode tOF tOF tOF ns
tOS1 Data Setup Time During <1>1 and DBIN 30 10 20 ns
tOS2 Data Setup Time to <1>2 During DBIN 150 120 130 ns
tOH(1) Data Hold Time From <1>2 and DBIN (1) (1) (1) ns
tiE INTE Output Delay From <1>2 200 200 200 ns CL = 50 pF
tRS READY Setup Time During <1>2 120 90 90 ns
tHS HOLD Setup Time During <1>2 140 120 120 ns
tiS INT Setup Time During <1>2 120 100 100 ns
tH Hold Time From <1>2 (READY, INT, HOLD) 0 0 0 ns
tFO Delay to Float During Hold
120 120 120 ns
(Address and Data Bus)
tAW Address Stable Prior to WR (5) (5) (5) ns
tow Output Data Stable Prior to WR (6) (6) (6) ns
two Output Data Stable From WR (7) (7) (7) ns
tWA Address Stable From WR (7) (7) (7) ns
tHF HLDA to Float Delay (8) (8) (8) ns
tWF WR to Float Delay (9) (9) (9) ns
tAH Address Hold Time After DBIN During HLDA -20 -20 -20 ns
A.C. TESTING LOAD CIRCUIT
DEVICE
'1CL~100PF
UNDER
TEST
-= 231453-4
CL = 100 pF
CL Includes Jig Capacitance
16-5
~
., - ~t~'
~
tey .
f\ it'- ~ I~
<
m
."
oJ3
l
.2 -I ~
io---
s::
en
-.t03 _ "-f
~I t02 - -
---I
A'S-AO
I--toA--:r - - - -1 -- -- t-,.....--
tAW
------ --- -4
-too-I -- tOi 1- ~
toHI""'- I--t oo-
~-- L _____
--·t:-~
---:::.. :,1= ~ ---- - ---
g~TA IN ATA OUT
° ,° oJ
-
7 0 -f
to
~ ~
-lOW
T ~
SYNC _ 1052 - I»
Q
DBIN
-- to~l-- - tDel-
11 l.
I»
i:.....
I--toF~1 ---'OF-!
I»
Q
..... I»
[. Q
en
m
WR
----------- ~
,L tH -
toe 1---1
J-:-- ....
co
~~~--:I
READY -X@
------------ f.-- Q
~
- t R5
WAIT tH- ..- 71 ~
HOLD
t oc- -
- - ...X@tH --0
J--
-X
N
~r;;.; Q-
HLDA
- .............. rf
INT
X~ '-4
tlSJ:-:
'H_
~
...
~
INTE
231453-5
NOTE:
Timing measurements are made at the following reference voltages: CLOCK "1" = a.ov, "0" = 1.0V; INPUTS "1" = a.av, "0" = o.av; OUTPUTS "1" = 2.0V,
"0" = o.av
8080A/8080A-1/8080A-2
WAVEFORMS (Continued) Typlcalll Output Delay vs Il Capacitance
~, ,J\ f\ !
>
:5
~
w
~2 ~
I-J Q
-
--- ---~-'FD I--
~
.~
o
A,s·Ao I-~--
I-
Y
tWA
-- 1--. '1
+100
.°7·°0 . - I- I-_.Y -- --.- -- ....
-t-1'wD -- ~ CAPACITANCE (pI)
(CACTUAL - CSPEC )
231453-7
SYNC
--:'1 .. tAH 3. The following are relevant when interfacing the
8080A to devices having VIH = 3.3V:
DBIN I ~ a) Maximum output rise time from 0.8V to 3.3V =
100 ns @ CL = SPEC.
WAf- W
I-- toe
-- ~'wF- b) Output delay when measured to 3.0V = SPEC
+60 ns @ CL = SPEC.
READY c) If CL = SPEC, add 0.6 ns/pF if CL > CSPEC,
subtract 0.3 ns/pF (from modified delay) if CL <
I - tHf- CSPEC·
WAIT 4. tAW = 2tcv - t03 - trcf>2 - 140 ns (-1:110
ns, - 2:130 ns).
I- S. tow = tcv - .t03 '- tr<j>2 - 170 ns (-1:1S0 ns,
HOLD
HLDA
- -
to'
_X-
- 2:170 ns).
.6. If not HLDA, two = tWA = t03 + tr<j>2 + 10 ns.
If HLDA, two = tWA = tWF·
~
7. tHF = t03 + trcf>2 -SO ns.
INT 8. tWF = toa + tr<f>2 - 10 ns.
9. Data in must be stable for this period during
DBIN T 3. Both tOSl and tOS2 must be satisfied.
INTE
I
~:~- 10. Ready signal must be stable for this period dur-
ing T 2 or TW. (Must be. externally synchronized.)
11. Hold signal must be stable for this period during
231453-6 T 2 or TW when entering hold mode, and during T 3,
T4, T 5 and TWH when in hold mode. (External syn-
chronization is not required.)
NOTES:
(Parenthesis gives -1, - 2 specifications, respec- 12. Interrupt signal must be stable during this peri-
tively.) od of the last clock cycle of any instruction in order
1. Data input should be enabled withDBIN status. to be recognized on the following instruction. (Ex-
ternal synchronization is not required.)
No bus conflict can then occur and data hold time
13. This timing diagram shows timing relationships
is assured.
only; it does not represent any specific machine cy-
tOH = SO ns or tOF, whichever is less.
cle.
2. lev = t03 + tr<1>2 + t<f>2 + tf<j>2 + t02 + tr<j>l ~
480 ns (-1 :320 ns, - 2:380 ns).
16-7
inter 8080A/8080A-1/8080A-2
INSTRUCTION, SET ' 8080A. The ability to increment and decrement
memory,the six general registers and the accumula-
The accumulator group instructions include arithme- tor is provided as well as extended increment and
tic and logical operators with direct, indirect, and im- decrement instructions to operate on. the register
mediate addressing modes. pairs and stack pointer. Further capability is provid-
ed by the ability to rotate the accumulator left or right
Move, load, and store instruction groups provide the through or around the, carry bit.
ability to move either 8 or 16 bits of data between
memory, the six working registers and the accumula- Input and output may be accomplished using memo-
tor using direct, indirect, and immediate addressing ry' addresses as I/O -ports or the directly addressed
modes. I/O provided for in the 8080A instruction set. , '
The ability to branch to different portions of the pro- The following special instruction gro!-,p completes
gram is provided with jump, jump conditional, and the 8080A instruction set: the NOP instruction"
computed jumps. Also the ability to call to and return HALT to stop processor execution and the OAA in-
from subroutines is provided both conditionally and structions provide decimal arithmetic capability. STC
unconditionally. The RESTART (or single byte call allows the carry flag to be directly set, and the CMC,
instruction) is useful for interrupt vector operation. instruction allows it to be complemented. CMA com-
plements the contents of the, accumulator and
Double preCision operators such as stack manipula- XCHG exchanges the contents of two 16-bit register
tion and double add instructions extend both the pairs directly.
arithmetic and Interrupt 'handling capability of the
Data and Instruction Formats
Oata·in the8080A is stored in the form Df8-bit binary integers. All data transfers to they system data bus will
be in the same format. ' .
rl0-7-'-06-0-5-0
-'-4-
0-3-0-2-0 1- 0-'0I
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in
:~~cessive words in program memory.. The instruction formats then depend on the particular operation execut-
One Byte Instructions . ' TYPICAL INSTRUCTIONS
107 D6 05 04 03 D2 ~1 Do I OP CODE Register to register, memory reference,
arithmetic or logical, rotate, return, push,
pop, enable or disable Interrupt
instructions
Two Byte Instructions
107 06 05 D4 03 02 01 Dol OPCODE
Immediate mode or I/O instructions
107 D6 05 04 03 02 0 1' Dol OPERAND
Three Byte Instructions
Jump, call or direct load and store
107 06 D5 04 03 02 01 Dol OPCOOE instructions ' ' ,
107 06 D5 D4 03 02 D1 Dol LOW ADDRESS OR OPERAND 1
10 7 06 D5 04 D3 02 01 Dol HIGH ADDRESS OR OPERAND 2
For the 8080A a logiC "1" is defined as a high level and a logiC "0" is defined as a low level.
16-8
inter 8080A/8080A-1/8080A-2
Table 2. Instruction Set Summary
Clock Clock
Instruction Code (1) Operations Instruction Code (1) Operations
~nemonlc' Cycles ~nemonlc' Cycle!
D7D6DsD4D3D2D1Do Description D7 D6 Ds D4 D3 D2 D1 Do Description
(2) (2)
MOVE, LOAD, AND STORE JM 1 1 1 1 1 0 1 a Jump on minus 10
MOVr1,r2 a 1 D D D S S S Move register to 5 JPE 1 1 1 a 1 a 1 a Jump on parity 10
register even
MOVM,r a 1 1 1 a S S S Move register to 7 JPO 1 1 1 a 0 a 1 a Jump on parity odd 10
memory PCHL 1 1 1 a 1 a 0 1 H & L to program 5
MOVr,M a 1 D D D 1 1 a Move memory to counter
7.
register CALL.
MVlr a a D D D 1 1 a Move immediate 7
CALL 1 1 0'0 1 1 a 1 Call unconditional 17
register
MVIM a a 1 1 a 1 1 a Move immediate 10 CC 1 1 0 1 1 1 a a Call on 9arry 11/17
memory CNC 1 1 0 1 0 1 a o Call on no carrY 11/17
LXIB a a a a a a a 1 Load immediate 10 CZ 1 1 a a 1 1 a o Call on zero 11/17
register Pair B & C CNZ 1 1 a a a 1 a o Call on no zero 11/17
LXID a a a 1 0 0 a 1 Load immediate 10 CP 1 1 1 1 0 1 0 o Call on positive 11/17
register Pair D & E CM 1 1 1 1 1 1 0 a Call on minus 11/17
LXIH a a 1 a a a a 1 Load immediate 10 CPE 1 1 1 a 1 1 a a Call on parity even 11/17
register Pair H & L 'CPO 1 1 1 a a 1 a o Call on parity odd 11/17
STAXB a a a a a a 1 a Store A indirect 7
STAXD a a a 1 a a 1 a Store A indirect 7 RETURN
LDAXB a a a a 1 a 1 a Load A indirect 7 RET 1 1 a a 1 a 0 1 Return 10
LDAXD a a a 1 1 a 1 a Load A indirect 7 RC 1 1 0 1 1 a a o Return on carry 5111
STA a a 1 1 a a 1 a Store A direct 13 RNC 1 1 a 1 0 a 0 o Return on no carry 5/11
LDA 0 0 1 1 1 a 1 b Load A direct 13 RZ 1 1 a a 1 a a a Return on zero 5/11
SHLD a a 1 a a a 1 a Store H & L direct· 16 RNZ 1 1 a a a a a a Return on no zero 5/11
LHLD a a 1 a 1 a 1 a Load H & L direct 16 RP 1 1 1 1 a a a a Return on positive 5/11
XCHG 1 1 1 a 1 a 1 1 Exchange D & E, 4 RM 1 1 1 1 1 a a a Return on minus 5/11
H & L Registers RPE 1 1 1 0 0 a a a Return on parity 5/11
STACKOPS even
RPO 1 1 1 a a 0 0 a Return on parity 5/11
PUSHB 1 1 a a a 1 a 1 Push register Pair 11 odd
B &Constack
PUSHD 1 1 a 1 a 1 a 1 Push register Pair 11 RESTART
D& E on stack RST 1 1 A A A 1 1 1 Restart 11
PUSHH 1 1 1 a a 1 a 1 Push register Pair 11
H& Lon stack INCREMENT AND DECREMENT
PUSH 1 1 1 1 0 1 a 1 Push A and Flags 11 INRr a a D D D 1 a a Increment register 5
PSW on stack
DCRr a a D DD 1 a 1 Decrement register 5
POPB 1 1 a a a a a 1 Pop register Pair B 10
INRM a 0 1 1 0 1 a o Increment memory 10
& C 011 stack
DCRM 0 0 1 1 a 1 0 1 Decrement memory 10
POPD 1 1 a 1 a a a 1 Pop register Pair D 10
& E 011 stack INXB 0 0 0 0 0 0 1 1 Increment B & C 5
registers
POPH 1 1 1 0 a a a 1 Pop register Pair H 10
INXD 0 0 0 1 0 0 1 1 Increment D & E 5
& L 011 stack
registers
POPPSW 1 1 1 1 a a a 1 Pop A and Flags 10
011 stack INXH a 0 1 a 0 0 1 1 Increment H & L 5
registers
XTHL 1 1 1 a a a 1 1 Exchange top of 18
stack, H & L DCXB a 0 a a 1 0 1 1 Decrement B & C 5
SPHL 1 1 1 1 1 a 0 1 H & Ltostack 5 DCXD 0 0 0 1 1 a 1 1 Decrement D & E 5
pointer DCXH a 0 1 a 1 0 1 1 Decrement H & L 5
LXISP 0 0 1 1 0 0 a 1 Load immediate 10 ADD
stack pointer
INXSP 0 0 1 1 a 0 1 1 Increment stack 5 ADDr 1 0 0 a a S S S Add register to A 4
pointer ADCr 1 0 a a 1 S S S Add register to A 4
DCXSP 0 0 1 1 1 a 1 1 Decrement stack 5 with carry
pOinter ADDM 1 a a a a 1 1 a Add memory to A 7
JUMP ADCM 1 0 0 a 1 1 1 o Add memory to A 7
with carry
JMP 1 1 a 0 0 a
1 1 Jump 10 ADI 1 1 0 a a 1 1 a Add immediate to A 7
unconditional ACI 1 1 0 a 1 1 1 o Add immediate to A 7
JC 1 1 a 1 1 a 1 o
Jump on carry 10 with carry
JNC 1 1 0 1 a a 1 o Jump on no carry 10 DADB 0 a 0 a 1 a a 1 AddB&CtoH&L 10
JZ 1 1 '0 0 1 0 1 o Jump on zero 10 DADD a a a 1 1 a a 1 AddD&EtoH&L 10
JNZ 1 1 a 0 a a 1 a Jump on no zero 10 DADH a 0 1 a 1 a a 1 AddH&LtoH&L 10
JP 1 1 1 1 a a 1 o
Jump on positive 10 DADSP a 0 1 1 1 0 0 1 Add stack pointer 10
toH&L
16-9
8080A/8080A-1/8080A-2
Table 2 Instruction Set Summary (Continued)
Clock Clock
Instruction Code (1) Operations Instruction Code (1) Operations
Mnemonic· Cyclel ~nemonlc· Cycle!
o,.DsDsD4D3D2Dl D Description D7DsDsD4D3D2D1D Description
(2) (2)
SUBTRACT ROTATE
SUBr 1 0 0 1 0 S S S Subtract register 4 RLC 0 0 0 0 0 1 1 1 Rotate A left 4
from A RRC 0 0 0 0 1 1 1 1 Rotate A right 4
SBBr l' 0 0 1 1 S S S Subtract register 4 RAL 0 0 0 1 0 1 1 1 Rotate A left 4
from A with borrow through carry
SUBM 1 0 0 1 0 1 1 o Subtract memory 7 RAR 0 0 0 1 1 1 1 1 Rotate A right 4
from A through carry
SBBM 1 0 0 1 1 1 1 o Subtract memory 7
SPECIALS
from A with borrow
SUI 1 1 0 1 0 1 1 o Subtract 7 CMA 0 0 1 0 1 1 1 1 Complement A 4
immediate from A STC 0 0 1 1 0 1 1 1 Set carry 4
SBI 1 1 0 1 1 1 1 o Subtract 7 CMC 0 0 1 1 1 1 1 1 Complement carry ~
immediate from A
with borrow OM 0 0 1 0 0 1 1 1 Decimal adjust A 4
INPUTIOUTPUT
LOGICAL
IN 1 1 0 1 1 0 1 1 Input 10
ANAr 1 0 1 0 0 S S S And register 4
with A OUT 1 1 0 1 0 0 1 1 Output 10
XRAr 1 0 1 0 1 S S S Exclusive or 4 CONTROL
register with A
ORAr 1 0 1 1 0 S S S Or register with A 4 EI 1 1 1 1 1 0 1 1 Enable Interrupts 4
CMPr 1 0 1 1 1 S S S Compare register 4 01 1 1 1 1 0 0 1 1 Disable Interrupt 4
with A NOP 0 0 0 0 0 0 0 o No-operation 4
ANAM 1 0 1 0 0 1 1 o And memory 7 HLT 0 1 1 1 0 1 1 o Halt 7
with A
XRAM 1 0 1 0 1 1 1 o Exclusive Or 7
memory with A
ORAM 1 0 ·1 1 0 1 1 o Or memory with A 7
CMPM 1 0 1 1 1 1 1 o Compare memory 7
with A
ANI 1 1 1 0 0 1 1 .0 And immediate 7
with A
XRI 1 1 1 0 1 1 1 o Exclusive Or 7
immediate with A
ORI 1 1 1 1 0 1 1 o Or immediate 7
with A
CPI 1 1 1 1 1 1 1 o Compare 7
immediate with A
NOTES:
1. DDD or SSS: B = 000, C = 001, D = 010, E = 011, H = 100, L = 101, Memory = 110, A = 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
'AII mnemonics copyright @ Intel Corporation 1977
16-10
8085AH/8085AH-2/8085AH-1
8-BIT HMOS MICROPROCESSORS
• Single + SV
Voltage Margins
Pow~r Supply with 10%
• On-Chip System Controller; Advanced
Cycle Status Information Available for
Large. System Control.
•. Available
3 MHz, S MHz and 6 MHz Selections
• Non-Maskable) Plus an SOSOA-
Four Vectored Interrupt Inputs (One Is
• SOSSA
20% Lower Power Consumption than
for 3 MHz and S MHz Compatible Interrupt
• p.s (80SSAH-2); 0.67 p.s (80SSAH-1)
1.3 p.s Instruction Cycle (SOSSAH); O.S • Decimal, Binary and Double Precision
Serial In/Serial Out Port
• Arithmetic
• On-Chip
100% Software Compatible with S080A
• Direct Addressing Capability to 64K
• Crystal, LCClock Generator (with External.
or RC Network) Bytes of Memory
• Available
Packages
in 40-Lead Cerdip and Plastic
(See Packaging Spec., Order # 231369)
The Intel 8085AH is a complete 8-bit parallel Central Processing Unit (CPU) implemented in N-channel,
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the
8080A microprocessor, and it is designed to improve the present 8080A's performance. by higher system
speed. Its high level of system integration allows a minimum system of three IC's [8085AH (CPU),8156H
(RAMIIO) and 8755A (EPROM/IO)] while maintaining total system expandability. The 8085AH-2 and
8085AH-1 are faster versions of the 80B5AH.
The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the 8080A, thereby offering a higher level of system integration. .
The 8085AH uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit
data bus. The on-chip address latches of 8155H/8156H/8755A memory products allow a direct interface with
the 8085AH.
liifA
Xl Vee
X2 HOLD
RESET OUT HLDA
eLK lOUT!
SIO RESET IN
TRAP REAOV
RST 7.5 101M
RST 6.5 S1
}-.
I ,.. C III
RST 5.5 iii5
'1(0 REG INTR iVA
D
REG.
II, I.
flEO
'"
iNfA ALE
Kill l ,"
REG. MG. ARRAY ADO So
STACI(POINTEA fill AOl Al5
PROGRAM COUNTER 1111 AD2 Al4
INCAEM1NTEA/DECREMlNTEA ADJ All
ADDR($SLATCIl "I! AD4 Al2
AD5 All
AD6 AlO
AD7 Ag
x,
x, Vss AS
231718-2
AII-At ADJ-ADo
AODAlSIIDAT A aus
ADDItEII8US
Figure 2. 8085AH Pin
231.718-1
Configuration
Figure 1. 8085AH CPU Functional Block Diagram
September 1987
16-11 Order Number: 231718-001
intJ 8085AH/8085AH-2/8085AH-1
Table 1_ Pin Description
Symbol Type Name and Function
Aa-A15 0 ADDRESS BUS: The most significant 8 bits of memory address or the 8 bits of the
1/0 address, 3~stated during Hold and Halt modes and during RESET.
ADo-7 1/0 MULTIPLEXED ADDRESSIDATA BUS: Lower 8 bits of the memory address (or
1/0 address) appear on the bus during the first clock cycle (T state) of a machine
cycle. It then becomes the data bus during the second and third clock cycles.
ALE 0 ADDRESS LATCH ENABLE: It occurs during the first clock state of a machine
cycle and enables the address to get latched into the on-chip latch of peripherals.
The falling edge of ALE is set to guarantee setup and hold times for the address
information. The falling edge of ALE can also be used to strobe the status
information. ALE is never 3-stated.
So, S1 and 101M 0 MACHINE CYCLE STATUS:
101M 51 50 Status
0 0 1 Memory write
0 1 0 Memory read
1 0 1 1/0 write
1 1 0 1/0 read
0 1 1 Opcode fetch
1 ·1 1 Interrupt Acknowledge
• 0 0 Halt
• X X Hold
• X X Reset
• = 3-state (high impedance)
X = unspecified
51 can be used as an advanced R/W status. 101M, SO and S1 become valid at the
beginning of a machine cycle and remain stable throughout the cycle. The falling
edge of ALE may be used to latch the state of these lines. .
RD 0 READ CONTROL: A low level on RD indicates the selected memory or 1/0 device
is to be read and that the Data Bus is available for the data transfer, 3-stated during
Hold and Halt modes and during RESET.
WR 0 WROTE CONTROL: A low level on WR indicates the data on the Data Bus is to be
written into the selected memory or 1/0 location. Data is set up at the trailing edge
of WR. 3-stated during Hold and Halt modes and during RESET.
READY I READY: If READY is high during a read or write CyCh3, it indicates that the memory
or peripheral is ready to send or receive data. If READY is low, the CPU will wait an
integral number of clock cycles for READY to go high before completing the read
or write cycle. READY must conform to specified setup and hold times;
HOLD I HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the bus
as soon as the completion of the current bus transfer. Internal processing can
continue. The processor can regain the bus only after the HOLD is removed. When
the HOLD is acknowledged~ the Address, Data RD, WR, and 101M lines are
3-stated.
HLDA 0 HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request
and that it will relinquish the bus in the next clock cycle. HILDA goes low after the
Hold request is removed. The CPU takes the bus one half clock cycle after HLDA
goes low.
INTR I INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of an instruction and during Hold and Halt
states. If it is actiVe, the Program Counter (PC) will be inhibited from incrementing
and an INTA will be issued. During this cycle a RESTART or CALL instruction can
be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.
16-12
intJ SOS5AH/SOS5AH-2/S0S5AH-1
Table 1. Pin Description (Continued)
Symbol Type Name and Function
INTA 0 INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as)
RD during the Instruction cycle after an INTR is accepted. It can be used to
activate an 8259A Interrupt chip or some other interrupt port.
RST5.5 I RESTART INTERRUPTS: These three inputs have the same timing as INTR
RST6.5 except they cause an internal RESTART to be automatically inserted.
RST7.5 The priority of these interrupt is ordered as shown in Table 2. These interrupts have
a higher priority than INTR. In addition, they may be individually masked out using
the SIM instruction.
TRAP I TRAP: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the
same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt
Enable. It has the highest priority of any interrupt. (See Table 2.)
RESET IN I RESET IN: Sets the Program Counter to zero and resets the Interrupt Enable and
HlDA flip-flops. The data and address buses and the control lines are 3-stated
during RESET and because of the asynchronous nature of RESET, the processor's
internal registers and flags may be altered by RESET with unpredictable results.
RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for
power-on RESET delay (see Figure 3). Upon power-up, RESET IN must remain low
for at least 10 ms after minimum Vee has been reached. For proper reset
operation after the power-up duration, flESET IN should be ~ept Iowa minimum of
three clock periods. The CPU is held in the reset condition as long as RESET IN is
applied.
RESET OUT 0 RESET OUT: Reset Out indicates CPU is being reset. Can be used as a system
reset. The signal is synchronized to the processor clock and lasts an integral
number of clock periods.
X1,X2 I X1 and X2: Are connected to a crystal, lC, or RC network to drive the internal
clock generator. X1 can also be an external clock input from a logic gate. The input
frequency is divided by 2 to give the processor's internal operating frequency.
ClK 0 CLOCK: Clock output for use as a system clock. The period of ClK is twice the X1,
X2 input period.
SID I SERIAL INPUT DATA LINE: The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD 0 SERIAL OUTPUT DATA LINE: The output SOD is set or reset as specified by the
SIM instruction.
Vee POWER:· + 5 volt supply.
Vss GROUND: Reference.
.
Table 2. Interrupt Priority, Restart Address and Sensitivity
Address Branched to(1)
Name Priority Type Trigger
When Interrupt Occurs
TRAP 1 24H Rising Edge AND High level until Sampled
RST7.5 2 3CH Rising Edge (latched)
RST6.5 3 34H High level until Sampled
RST5.5 4 2CH High level until Sampled
INTR 5 (Note 2) High level until Sampled
NOTES:
1. The processor pushes the pe on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the CPU when. the interrupt is acknowledged.
16-13
inter 8085AH/8085AH-2/8085AH-1
(SID) and Serial Output Data (SOD) lines for simple
RESET IN serial interface.
' c,
:
R, In addition to these features, the 8085AH has three
I~
Vee 0 maskable, vector interrupt pins, one nonmaskable
I
Typical Power-On Reset RC Values'
RI = 75 KO
f 231718-3
TRAP interrupt, and a bus vectored interrupt, INTR.
INTERRUPT AND SERIAL I/O
The 8085AH has 5 interrupt inputs: INTR, RST 5.5,
CI = 1 "F
RST 6.5, RST 7.5, and TRAP. INTR is identical in
'Values May Have to Vary Due to Applied Power Supply Ramp function to the 8080A INT. Each of the three RE-
UpTime. START inputs, 5.5, 6.5, and 7.5, has a programma-
ble mask. TRAP is also a RESTART interrupt but it is
Figure 3. Power-On Reset Circuit
nonmaskable.
The three maskable interrupt cause the internal exe-
FUNCTIONAL DESCRIPTION cution of RESTART (saving the program counter in
The 8085AH is a complete 8-bit parallel central the stack 'and branching to the RESTART address) if
the interrupts are enabled and if the interrupt mask
processor. It is designed with N-channel, depletion
load, silicon gate technology (HMOS), and requires is not set. The nonmaskable TRAP causes the inter-
a singie + 5V supply: Its basic clock speed is 3 MHz nal execution of a RESTART vector independent of
(8085AH), 5 MHz (8085AH~2), or 6 MHz (8085-AH- t), the state of the interrupt enable or masks. (See Ta-
ble 2.)
thus improving on the present 8080A's performance
with higher system speed. Also it is designed to fit , There are two different types of inputs in the restart
into a minimum system of three IC's:, The CPU interrupts. RST 5.5 and RST 6.5 are high level-sensi-
(8085AH), a RAM/10(8156H), and an EPROM/IO tive like INTR (and INT on the 8080) and are recog-
chip (8755A). '
nized with the same tiining ,as INTR. RST 7.5 is rising
edge-sensitive.
The 8085AH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register For RST 7.5, only a pulse is required to set an inter-
pairs. Six others can be used' interchangeably as nal flip-flop which generates the internal interrupt re-
8-bit registers or as 16-bit register, pairs. The quest (a normally high level signal with a low going
8085AH register, set is as follows: pulse is recommended for,highest system noise im-
Mnemonic Register Contents munity). The RST 7.5 request flip-flop remains set
ACC or A, Accumulator 8 Bits until the request is serviced. Then it is reset auto-
PC Program Counter 16-Bit Address matically. This flip~flop may also be reset by using
BC, DE, HL General-Purpose 8-Bits x 6 or theSIM instrUction or by issuing a RESET IN to the
Registers; data 16'Bitsx3 8085AH. The RST 7.5 internal flip-flop will be set by
pointer (HL) a pulse on the RST 7.5 pin even when the RST 7.5
Stack Pointer '16-Bit Address interrupt is masked out. '
SP
Flags or F Flag Register 5 Flags (8-Bit Space) The status of the ,three, RST interrupt' masks can
only be affected by the SIM instruction and
The 8085AH uses a multiplexed Data Bus. The ad- RESET IN. (See SIM, Chapter 5 of the 8080/8085
dress is split between the higher 8-bit Address Bus User's Manual.)
and the lower 8-bit Address/Data Bus. During the
first T state (clock cycle) of a machine cycle the low The interrupts are arranged' in a fixed priority that
order address is sent out on the AddresS/Data bus. determines which interrupt is to be recognized if
These lower 8 bits may be latched exterrially by the more than one is pending as follows: TRAP-high-
Address Latch Enable Signal (ALE). During the rest est priority, RST 7.5, RST 6.5, RST 5;5, INTR-Iow-
of the machine cycle the data bus is used for memo- est priority. This priority scheme does not take into
ry or I/O data. account the priority of a routine that was started by a
higher priority interrupt. RST 5.5 can interrupt an
The 8085AH provides RD, WR, So, Sl, and 10/M RST 7.5 routine if the interrupts are re-enabled be-
Signals for' bus control. An Interrupt Acknowledge fore the end of the RST 7.5 routine.
signal (INTA) is also provided. HOLD and all Inter-
rupts are synchronized with the processor's internal The TRAP interrupt is useful for catastrophic 'events
clock. The 8085AH also provides Serial Input Data such as power failure or bus, error. The TRAP input is
recognized just as any other interrupt but has the
16-14
intJ 8085AH/8085AH-2/8085AH-1
highest priority. It is not affected by any flag or mask. hence, the 8085AH is operated with a 6 MHz crystal
The TRAP input is both edge and level sensitive. (for 3 MHz clock), the 8085AH-2 operated with a 10
The TRAP input must go high and remain high until it MHz crystal (for 5 MHz clock), and the 8085AH-1
is acknowledged. It will not be recognized again until can be operated with a 12 MHz crystal (for 6 MHz
it goes low, then high again. This avoids any false clock). If a crystal is used, it must have the following
triggering due to noise or logic glitches. Figure 4 il- characteristics:
lustrates the TRAP interrupt request circuitry within
the 8085AH. Note that the servicing of any interrupt Parallel resonance at twice the'clock frequency de-
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables sired
all future interrupts (except TRAPs) until an EI in- CL (load capacitance) s 30 pF
struction is executed. Cs (Shunt capacitance)s 7 pF
Rs (equivalent shunt resistance) s 75!l
Drive level: 10 mW
Frequency tolerance: ± 0.005% (suggested)
INSIDE THE
EXTERNAL 8085AH
TRAP
INTERRUPT
Note the use of the 20 pF capacitor between X2 and
REOUEST ground. This capacitor is required with crystal fre-
quencies belpw 4 MHz to assure oscillator startup at
the correct frequency. A parallel-resonant LC citcuit
RESET I':;; SCHMITT may be used as the frequency-determining network
TRIGGER
for the 8085AH, providing that its frequency toler-
ance of approximately ± 10% is acceptable. The
+5V 0 elK components are chosen from the formula:
D
FIF
To minimize variations in frequency, it is recom-
INTERNAL TRAP F.F.
TRAP mended that you choose a value for Cext that is at
ACKNOWLEDGE
least twice that o,f Cjnt, or 30 pF. The use of an LC
231718-4 circuit is not recommended for frequencies higher
than approximately 5 MHz.
Figure 4. TRAP and RESET In Circuil
An 'RC circuit may be used as the frequency-deter-
The TRAP interrupt is special in that it disables inter-
mining network for the 8085AH if maintaining a pre-
rupts, but preserves the previous interrupt enable
cise clock frequency is of no importance. Variations
status. Performing the first RIM instruction following
in the on-chip timing generation can cause a wide
a TRAP interrupt allows you to determine whether
variation in frequency when using the RC mode. Its
interrupts were enabled or disabled prior to the
advantage is its low component cost. The driving
TRAP. All subsequent RIM instructions provide cur-
frequency generated by the circuit shown is approxi-
rent interrupt enable status. Performing a RIM in-
mately 3 MHz. It is not recommended that frequen-
struction following INTR, or RST 5.5-7.5 will provide
cies greatly higher or lower than this be attempted.
current Interrupt Enable status, revealing that inter-
rupts are disabled. See the description ofthe RIM
Figure 5 shows the recommended clock driver cir-
instruction in the 8080/8085 Family User's Manual.
cuits. Note in d and e that pullup resistors are re-
quired to assure that the high level voltage of the
The serial I/O system is also controlled by the RIM
input is at least 4V and maximum low level voltage
and SIM instruction. SID is read by RIM,' and SIM
of 0.8V.
sets the SOD data.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to Xl and leave X2
DRIVING THE X1 AND X2 INPUTS open-circuited (Figure 5d). If the driving frequency is
You may drive the clock inputs of the 8085AH, from 6 MHz to 12 MHz, stability of the clock genera-
8085AH-2, or 8085AH-1 with a crystal, an LC tuned tor will be improved by driving both Xl and X2 with a
circuit, an RC network, or an external clock source. push-pull source (Figure 5e). To prevent self-oscilla-
The crystal frequency must be at least 1 MHz, and tion of the 8085AH, be sure that X2 is not coupled
must be twice the desired internal clock frequency; back to Xl through the driving circuit.
16-15
inter 8085AH/8085AH·2/8085AH·1
+IY
Xt eOllIAtI
,----,
I
I
*I
I CINT
-15pF
'--:........~_~2 X2_ _ _ J
'20 pF capacttors required for '--_ _ _ _ _ __
crystal frequency ,;; 4 MHz only. 231718-5
a. Quartz Crystal Clock Driver.
'X2 left floating
808SAH
r x, 231718-8
,..--...---1 1.:::"" - - . . ,
'1 " d. 1-6 MHz Input Frequency
I C'NT Clock Driver Circuit
t LEXT - CEXT .....I
...L. -15pF
+IY
;! x. I
'----+-....,--11... -""- - _....J
.. 231718-6
b. LCTuned Circul~ Clock DrIver
x, 47011
'-----lx.
1
-8K .
20
231718-9
pF ' - - - - (
e.1-12 MHz Input Frequency
External Clock Driver Circuit
231718-7
c. RC Circuit Clock Driver
Figure 5. Clock Driver Circuits
GENERATING AN8085AH WAIT As in the,8080, the READY line is used to extend the
STATE . read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU
If your system requirements are such that' slow to relinquish the bus when it is thOrough with it by
memories or peripheral devices are being used, the floating the Address and Data Buses.
circuit shown in Figure 6 may. be used to insert one
WAIT state in each 8085AH machine cycle.
SYSTEM INTERFACE
Th~ D flip-flops should be chosen so that
• ClK is rising edge-triggered The 8085AH family includes memory components,
• CLEAR is low-level active. which are directly compatible to the 8085AH CPU.
For example, a system consisting of the three chips,
8085AH, 8156H, and 8755A. will have the following
features:
~
CLEAR 808SAH • 2K Bytes EPROM
ClK CLlUIUTPIIT"" - ClK TO
808SAH • 256 Bytes RAM
"0" '"0'" READY
F/F F/F - INPUT • 1 Timer/Counter
+5V- 0
Q
0 ~~
• 4 8-bit 110 Ports,
231718-10 .1 6-bitll0 Port
'ALE and ClK (OUT) should be buffered if ClK input of latch
exceeds 8085AH IOl or IOH. • 4 Interrupt Levels
Figure 6. Generation of a • Serial In/Serial Out Ports
Wait State for 8085AH CPU
16-16
8085AH/8085AH-2/8085AH-1
This minimum system, using the standard 1/0 tech- shows the system configuration of Memory Mapped
nique is as shown in Figure 7. 1/0 using 8085AH. .
In addition to the standard 1/0, the memory mapped The 8085AH CPU can also interface with the stan-
1/0 offers an efficient 1/0 addressing technique. dard memory that does not have the multiplexed ad-
With this technique, an area of memory address dressldata bus. It will require a simple 8-bit latch as
space is assigned for 1/0 address, thereby, using shown in Figure 9.
the memory address for 110 manipulation. Figure 8
r1D~x,
Vss vee
rl I
-- TRAP
RST1.5
x, RESET IN
HOLD
HlDA
I-
I--
---
RST6.5 SOD I-- ,
8085AH
RST5.5 SID I-
5,1--
- INTR
TNTA
ADDR
ADDRI
DATA ALE AD Wli
RESET
101M
OUT S.
RDY ClK
I--
18) (81 Vi' vr
I~r- ~ POR!~
WR
_ PORT ~
181
RD 8156H B
ALE PORT~
A J.. DATAl C 161
ADDR
~
101M
RESET
IN
TIMER
OUT -
r--
iow
AD
~
ALE
PORT
Itr- CE A
~.;:: '"
V
A8-10
8755A
.A J..
DATAl
ADDR
~.
1011\; PORT
B
RESET
I- * RDY Vee
~ ClK lOR -.J
.t tJ 1.
Vss Vee Voo PROG
Vee
Vee
Vee
231718-11
• NOTE:
Optional Cqnnection
Figure 7. 8085AH Minimum System (Standard 1/0 Technique)
16-17
AS-1S - ,
r-
"-
l
, v
~O-7
ALE 0 0
l!
(D
...IDc.
8085AH RD
WR
101M
-
-
-
-
- Vee
vce
!»
co
CI
co
CLK
RESET OUT f
- II co
01 - READY
- 0
co
3C i - en
S" 1 vec )I-
3" I. .. 1
I.
::z::
.....
c co
3 :TIMER AD A8- AD 101
1 0
...... (I) RESET + WR AD ALE CE ",-,70-7 101M
~A10VO.7 CE M ALE AD iOW CLK RS1RDY co
m '<
IN en
~
to
,!,
ID
3
.
)I-
::z::
PI)
.....
3:
ID
co
0
3 Tb~~R_ CO
en
0 )I-
~ 8158H ::z::
3C
III
[RAM + I/O + COUNTERlTIMERj 8755A [EPROM + I/O] .....•
~
~
ID
Co
:::::
.9
231718-12
'NOTE:
Optional Connection.
inter 8085AH/8085AH-2/8085AH-1
-- TRAP
X, X2 RESET IN
HOLD
-
-_.
-
RST7 HlDA
--- ---
RST6 SOD
RST5 8085AH SID
INTR S,
RESET
INTA OUT So
ADDRI
ADDR DATA ALE AD WR 101M RDYClK
' ~~
'Qr V' .1\.
101M (CS)
WR
RD
DATA
~
" STANDARD
MEMORY
\ ADDR (CS)
, V
/
(16)
--- ClK
RESET
101M (CS) 1/0 POR TS,
lS
B
WR
RD
...
V
r--..
DATA
" STANDARD
1/0
...
I ADDR
V
DUI II AA
Y:V
YAY;
Vee
Vee
.. YV Vee
231718-13
Figure 9. 8085 System (Using Standard Memories)
16-19
inter 8085AH/8085AH-2/8085AH-1
BASIC SYSTEM TIMING the three control signals (RD, WR, and INTA). (See
Table 3.) The status lines can be used as advanced
The 8085AH has a multiplexed Data Bus. ALE is controls (for device selection, for example), since
used as a strobe to sample the lower 8-bits of ad- they become active at the T 1 state, at the outset of
dress on the Data Bus. Figure 10 shows an instruc- each machine cycle. Control lines RD and WR be-
tion fetch, memory read and 1/0 write cycle (as come active later, at the time when the transfer of
would occur during processing of the OUT instruc- data is to take place, so are used as command lines.
tion). Note that during the 1/0 write and read cycle
that the 1/0 port address is copied on both the up- A machine cycle normally consists of three T states,
per and lower half of the address. . with the exception of OPCODE FETCH, which nor-
mally has either four or six T states (unless WAIT or
There are seven possible types of machine cycles. HOLD states are forced by the receipt of READY or
Which of these seven takes place is defined by the HOLD inputs). Any T state must be one of ten possi-
status of the three status lines (101M, S1, So) and ble states, shown in Table 4 ..
Table 3. 8085AH Machine Cycle Chart
Status Con,trol
Machine Cycle
101M S1 SO RD W~~ INTA
OPCODE FETCH (OF) 0 1 1 0 1 1
MEMORY READ (MR) 0 1 0 0 1 1
MEMORY WRITE (MW) 0 0 1 1 0 1
1/0 READ (lOR) 1 1 0 0 1 1
1/0 WRITE (lOW) 1 0 1 1 0 1
ACKNOWLEDGE
OFINTR (INA) 1 1 1 1 1 0
BUS IDLE (BI): DAD 0 1 0 1 1 1
ACK.OF
RST,TRAP 1 1 1 1 1 1
HALT TS 0 0 TS TS 1
Table 4. 8085AH Machine State Chart
Machine Status & Buses Control
State S1,SO 101M Aa-A 15 ADo-AD7 RD,WR INTA ALE
T1 X X X X 1 1 1·
T2 X X X X X X 0
TWAIT X X X X X X 0
Ts X X X X X X 0
T4 1 ot X TS 1 1 0
Ts 1 ot X TS 1' 1 0
Ts 1 ot X TS 1 1 0
TRESET X TS TS TS TS 1 0
THALT 0 TS TS TS TS 1 0
THOLD X TS TS TS TS 1 0
o = LogIc "0" TS = High Impedance
1 = Logic "1" X = Unspecified
• ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
tlOiM = 1 during T4-Ts of INA machine cycle.
16-20
intJ 8085AH/8085AH-2/8085AH-1
M, M2 M3
CLK T,
As -A'5 PCH (HIGH ORDER ADDRESS! (PC + 1IH
AO O_7
ALE
iID
WR
101M
STATUS S,s. (FETCH! 10 (READ! 01 WRITE 11
231718-14
Figure 10. 8085AH Basic System Timing
16-21
8085AH/8085AH~2/8085AH·1
ABSOLUTE MAXIMUM RATINGS· • Notice: Stresses above those listed under ':4bso-
Ambient Temperature under Bias .....,. O·C to 70·C lute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
Storage Temperature .......... - 65·C to + 150·C funCtional operation of the device at these or any
Voltage on Any Pin other conditions above those indicated in the opera-
with Re!!pect to Ground .........• - 0.5V to + 7V tional sections of this specification is not implied. Ex-
Power Dissipation ........•................. 1.5W posure to absolute maximum rating conditions for
extended periods may IfIffect device reliability.
D.C. CHARACTERISTICS
8085AH, 8085AH-2: TA = O·C to 70·C, Vee = 5V t 10%, Vss = OV; unless otherwise specified" '
80S5AH-1: TA = O·C to 70·C, Vee = 5V ±5%, Vss = OV; unless otherwise specified"
Symbol Parameter Min Max Units Test Condlti,ons
VIL Input Low Voltage -0.5 +O.S V
VIH Input High Voltage 2.0 Vee +0.5 V
VOL Output Low Voltage 0.45 V IOL = 2mA
VOH Output High Voltage 2.4 V IOH = -400 p,A
Icc Power Supply Current 135 rnA 8085AH, SOS5AH-2
200 rnA 8085AH-1
IlL Input Leakage ±10 . p,A o ~ VIN ~ Vee
ILO Output Leakage ±10 p,A 0.45V ~ VOUT ,~ Vee
VILR Input Low Level, RESET, -0.5 +O.S V
VIHR Input High Level, RESET 2.4 Vee + 0.5 V
VHY Hysteresis, RESET 0.15 'V
A.C. CHARACTERISTICS
SOS5AH, 8085AH-2: TA = o·c to 70·C, Vee = 5V ±10%, vss = ov·
S085AH-1: TA = O·C to 70·C, vee = 5V ±5%, vss = OV
8085AH (2) 8085AH.2 (2) 8085AH~1 (2)
Symbol Parameter Units
Min Max Min Max Min Max
tCYC CLK Cycle Period 320 2000 200 2000 167 2000 ns
t1 CLK Low Time (Standard CLK Loading) SO 40 20 ns
t2 CLK High Time (Standard CLK Loading), 120 70 50 ns
tr, tf CLK Rise and Fall Time 30 30 30 ns
tXKR X1 Rising to CLK Rising 20 120 20 100 20 100 ns
tXKF X1 Rising to CLK Falling 20 150 20 110 20 110 ns
tAC A8-15 Valid to Leading Edge of Control (1) 270 115 70 ns
tACL AO-7 Valid to Leading Edge of Control 240 115 60 ns
tAD AO-15 Valid to Valid Data In 575 350 225 ns
tAFR Address Float after Leading Edge of 0 0 0 ns
READ (lNTA)
tAL A8-15 Valid before Trailing Edge'of ALE (1) 115 50 25 ns
°NOTE:
For Extended Temperature EXPRESS use M8085AH Electricals Parameters.
16-22
SOS5AH/SOS5AH·2/S0S5AH·1
A.C. CHARACTERISTICS (Continued)
8085AH (2) . 8085AH-2 (2) 8085AH-1 (2)
Symbol Parameter Units
Min Max Min Max Min Max
tAll AO-7 Valid before Trailing Edge of ALE 90 50 25 ns
tARY READY Valid from Address Valid 220 100 40 ns
tCA Address (AS-15) Valid after Control 120 60 30 ns
tcc Width of Control low (RD. WR.INTA) 400 230 150 ns
Edge of ALE
tCl Trailing Edge of Control to leading Edge 50 25 0 ns
of ALE
tow Data Valid to Trialing Edge of WRITE 420 230 140 ns
tHABE HlDA to Bus Enable 210 150 150 ns
tHABF Bus Float after HlDA 210 150 150 ns
tHACK HlDA Valid to Trailing Edge of ClK 110 40 0 ns
tHOH HOLD Hold Time 0 0 0 ns
tHOS HOLD Setup Time to Trailing Edge of ClK 170 120 120 ns
tlNH INTR Hold Time 0 0 0 ns
tiNS INTR. RST. and TRAP Setup Time to 160 150 150 ns
Falling Edge of ClK
tLA . Address Hold Time after ALE 100 50 20 ns
tlC Trailing Edge of ALE to leading Edge 130 60 25 ns
of Control
tlCK ALE low During ClK High 100 50 15 ns
tLDR ALE to Valid Data during Read 460 270 175 ns
tLDW ALE to Valid Data during Write 200 140 110 ns
tll ALE Width 140 80 50 ns
tlRY ALE to READY Stable 110 30 10 ns
tRAE Trailing Edge of READ to Re-Enabling 150 90 50 ns
of Address
tRO READ (or INTA) to Valid Data .300 150 75 ns
tRY Control Trailing Edge to leading Edge 400 220 160 ns
of Next Control
tROH Data Hold Time after READ INTA 0 0 0 ns
tRYH READY Hold Time 0 0 5 ns
tRYS READY Setup Time to leading Edge 110 100 100 ns
ofClK
two Data Valid after Trailing Edge of WRITE 100 60 30 ns
tWOl lEADING Edge of WRITE to Data Valid 40 20 30 ns
NOTES:
1. Aa-A15 address Specs apply 101M. SO. and 51 except Aa-A15 are undefined during T4-T6 of OF cycle whereas 101M.
SO. and 51 are stable.
2. Test Conditions: tCYC = 320 ns (SOS5AH)/200 ns (SOS5AH-2);/167 ns (SOS5AH-1); CL = 150 pF.
*
3. For all output timing where C 150 pF use the following correction factors:
25 pF s;; CL < 150 pF: -0.10 ns/pF
150 pF < CL S;; 300 pF: +0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other values of tCYC use Table 5.
16-23
inter 8085AH/8085AH-2/8085AH-1
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
OEVICE
<u)C
IJCL~150PF.
UNDER
TEST
~~...
0.45
~
0.8
> TEST POINTS .
.
.
0.8.
231718-16
231718-15
CL = 100 pF
A.C. Testing: Inputs are driven at 2.4V for a .Logic "I" and 0.45V CL .Includes Jig Capacitance
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".
Table 5. Bus Timing Specification as a Teye Dependent
Symbol 8085AH 8085AH-2 8085AH-1
tAL (1/2)T - 45 (1/2)T - 50 (1/2)T -.58 Minimum
tLA (1/2)T - 60 (1/2)T - 50 (1/2)T - 63 Minimum
tLL (1/2)T - 20 (1/2)T - 20 (1/2)T - 33 Minimum
tLCK (1/2)1- 60 (1/2)T - 50 (112)T - 68 Minimum
tLC (1/2)T - 30 (1/2)T - 40 (1/2)T - 58 Minimum
tAD (5/2 + N)T - 225 (5/2 + N)T - 150 (5/2 + N)T - 192 Maximum
tRO (3/2 + N)T - 180 (3/2 + N)T - 150 (3/2 + N)T - 175 Maximum
tRAE (1/2)T - 10 . (1/2)T - 10 (1/2)T - 33 Minimum'
tCA (1/2)T"""740 (1/2)T - 40 (1/2)T - 53 Minimum
tow (3/2 + N)T - 60 (3/2 + N)T - 70 (3/2 + N)T - 110 Minimum.
two (1/2)T - 60 (1/2)T - 40 (1/2)T - 53 Minimum
tcc (3/2 + N)T - 80 (3/2 + N)T - 70 (3/2 + N)T - 10.0 Minimum
tCL (1/2)T -110 (1/2)T - 75 (1/2)T - 83 Minimum
tARY (3/2)T - 260 (3/2)T - 200 (3/2)T - 210 Maximum
tHACK (1/2)T - 50 (1/2)1- 60 (1/2)T - 83 I Minimum
tHABF (1/2)T + 50 (1/2)T + 50 (1/2)T + 67 Maximum
tHABE (1/2)T + 50 (1/2)T + 50 (1/2)T + 67 Maximum
tAc (2/2)T- 50 (2/2)T - 85 (2/2)T - 97 Minimum
tl (1/2)T - 80 (1/2)T - 60 (1/2)T - 63 Minimum
t2 (1/2)T -'- 40 (1/2)1 - 30 (1/2)T - 33 Minimum
tRY (3/2)T -80 (3/2)T - 80 (3/2)T - 90 Minimum
tLDR (4/2 + N)T - 180 (4/2)T - 130 (4/2)T - 159 Maximum
NOTE:
N is equal to the total WAIT states. T = tCYC'
16-24
8085AH/8085AH-2/8085AH-1
WAVEFORMS
CLOCK
X, INPUT
t
r
_]. _ __
t
~
elK
OUTPUT
1 _ 11 _1
I-------'CVC - - - - - - + 1
_lXKF-
231718-17
READ
T, I T, I T, T,
elK \'-_..Jlr--}"---~, _ l _ ''-----II ''-_..J1
lCK _ ICA _
• )! ADDRESS
l
AO
_ tRDH __ ~1_tRAE
.....
-, - -
J
_Iq._
ADDRESS 1;/ $ff~ DATA IN
"I
-
i
-
f---tLA-
ALE
J
t AFR .......
tLOA
I _
I-'CL-
1
_IAL_ RO
_--'cc I
RDilNTA
_llC_ ~
~tAC_
231718-18
WRITE
T, I T, I T, I T,
elK \\...._..JI \'-----JI \\....____--,r---.,'----J
r-tlCK-I"
)! ADDRESS
X
r-- tLDW
-
i'CA-1
1 ADDRESS } DATA OUT
X
14 - tLl _ I . . - tLA----I -tow -two--I
ALE
'J -t _
- -'WOL
.
Al
-tee
WR
~tAC-
-'lC :j~ ....... t el -.-
231718-19
16-25
SOSSAH/SOSSAH-2/S0SSAH-1
WAVEFORMS (Continued)
HOLD
elK :\
T,
, I
T,
I
T HOLD
\
T HOLD
I - , T,
HOLD t "\ '~
'HD'· IJ=HDH tt HACK '"
HLOA t t HABF -
\
I. tHABE-H
BUS (ADDRESS. CONTROLS) >--:I
:1
231718-20
READ OPERATION WITH WAIT CYCLE (TYPICAL)-SAME READY TIMING APPLIES TO WRITE
I T, T2 TWAIT T, T,
elK
/ \ ~ /
- - tlCK
·1 _ICA_
As-A,. ). ADDRESS
)
- 'AD
//II/) -
tRDH .. ~rRA'-
....
ADo-AD, ADDRESS
elL DATA IN
~
-)
ALE
r- r- tLL--'" -tLA-
tAFR_
- 'LOA
-'Cl-Y
. 'Al ~
1- 'Ro . ,I
tee
--'L~-rt
IJ
RD/iNTA
'i.
<'---'LRY
/:==
. tAC_
'ARY •~ ]---
I 'RY' 'RYH _I .
- .... ---....
lAYS tRYH
READY . '\ I lIlllllllA J
231718-21
NOTE:
1. Ready must remain stable during setup and hold times.
/
16-26
8085AH/8085AH·2/8085AH·1
WAVEFORMS (Continued)
INTERRUPT AND HOLD
11----·-- BUS FLOATING' -----1
MI-------------l-----,~----------------~
HOLD
HLOA
231718-22
'NOTE:
101M is also floating during this ·time.
16-27
8085AH/8085AH-2/8085AH-1
Table 6. Instruction Set Summary
Mnemonic Instruction Code Operations Instruction Code Operations
D7 D6 D5 D4 D3 D2 D1 Do Description Mnemonic
. D765
D D D4 D3 D2 D'1 D0 Description
MOVE, LOAD AND STORE STACK OPS (Continu.ed)
MOVr1 r2 0 1 D D D S S S Move register POPPSW 1 1 1 1 0 0 0 1 Pop A and Flags
to register off stack
MOVM.r 0 1 1 1 0 S S S Move register XTHL 1 1 1 0 0 0 1 1 Exchange top of
to memory stack, H & L
MOVr.M 0 1 D D D 1 1 0 Move memory SPHL 1 1 1 '1 1 0 0 1 H & Ltostack
to register pointer
MVlr 0 0 D D D 1 1 0 Move immediate LXISP 0 0 1 1 0 0 0 1 Load immediate
register stack pointer
MVIM 0 0 1 1 0 1 1 0 Move immediate INXSP 0 0 1 1 0 0 1 1 Increment stack
inemory pOinter
LXIB 0 0 0 0 0 0 0 1 Load immediate DCXSP 0 0 1 1 1 0 1 1 Decrement stack
. register Pair B & C pOinter
LXID 0 0 0 1 0 0 0 1 Load immediate JUMP
register Pair D & E JMP 1 1 0 0 0 0 1 1 Jump unconditional
LXIH 0 0 1 0 0 0 0 1 Load immediate JC 1 1 0 1 1 0 1 0 Jump on carry
register Pair H & L
JNC 1 1 0 1 0 0 1 0 Jump on no carry
STAXB 0 0 0 0 0 0 1 0 Store A indirect
JZ 1 1 0 0 1 0 1 0 Jump on zero
STAXD 0.0 0 1 0 0 1 0 Store A indirect
JNZ 1 1 0 0 0 0 1 0 Jump on no zero
LDAXB 0 0 1 0 1 0 1 0 Load A indirect
JP 1 1 1 1 0 0 1 0 Jump on positive
LDAXD 0 0 0 1 1 0 1 0 Load A indirect
JM 1 1 1 1 1 0 1 o Jump on minus
STA 0 0 1 1 0 0 1 0 Store A direct
JPE 1 1 1 0 1 0 1 0 Jump on parity even
LDA 0 0 1 1 1 0 1 0 Load A direct
JPO 1 1 1 0 0 0 1 0 Jump on parity odd
SHLD 0 0 1 0-0 0 1 0 Store H & L direct
PCHL 1 1 1 0 1 0 0 1 H & L to program
LHLD 0 0 1 0 1 0 1 0 Load H & L direct counter
XCHG 1 1 1 0 1 0 1 1 Exchange D & E, CALL
H & L Registers
CALL 1 1 0 0 1 1 0 1 Call unconditional
STACKOPS
CC 1 1 0 1 1 1 0 0 Call on carry
PUSHB 1 1 0 0 0 1 0 1 Push register Pair
B & Con stack CNC 1 1 0 1 0 1 0 0 Call on no carry
PUSHD 1 1 0 1 0 1 0 1 Push register Pair CZ 1 1 0 0 1 1 0 o Call on zero
D & E on stack CNZ 1 1 0 0 0 1 0 0 Call on no zero
PUSHH 1 1 1 0 0 1 0 1 Push register Pair CP 1 1 1 1 0 1 0 0 Call on positive
H & Lon stack CM 1· 1 1 1 1 1 0 0 Call on minus
PUSH 1 1 1 1 0 1 0 1 Push A and Flags CPE 1 1 1 0 1 1 0 0 Call on parity even
PSW on stack
CPO 1 1 1 0 0 1 0 0 Call on parity odd
POPB 1 1 0 0 0 0 0 1 Pop register Pair
B & C off stack RETURN
POPD 1 1 0 1 0 0 0 1 Pop register Pair RET 1 1 0 0 1 0 0 1 Return
D & E off stack RC 1 1 0 1 1 0 0 0 Return on carry
POPH 1 1 1 0 0 0 0 1 Pop register Pair RNC 1 1 0 1 0 0 0 0 Return on no carry
H & L off stack RZ 1 1 0 0 1 0 0 0 Return on zero
16-28
inter 8085AH/8085AH·2/8085AH·1
Table 6. Instruction Set Summary (Continued)
Mnemonic Instruction Code Operations Mnemonic Instruction Code Operations
D7 D6 Ds D4 D3 D2 Dl Do Description D7 D6 Ds D4 D3 D2 Dl Do . Description
RETURN (Continued) IADD (Continued)
RNZ 1 1 0 0 0 0 0 0 Return on no zero DADO 0 0 0 1 1 0 0 1 AddD&EtoH&L
RP 1 1 1 1 0 0 0 0 Return on positive DADH 0 0 1 0 1 0 0 1 AddH&LtoH&L
RM 1 1 1 1 1 0 0 0 Return on minus DAD8P 0 0 1 1 1 0 0 1 Add stack pOinter
RPE 1 1 1 0 1 0 0 0 Return on toH&L
parity even IsUBTRACT
RPO 1 1 1 0 0 0 0 0 Return on 8UBr 1 0 0 1 0 8 8 8 Subtract register
parity odd from A
RESTART 8BB r 1 0 0 1 1 8 8 8 Subtract register
R8T 1 1 A A A 1 1 1 Restart from A with borrow
INPUTIOUTPUT 8UBM 1 0 0 1 0 1 1 o 8ubtract memory
from A
IN 1 1 0 1 1 0 1 1 Input
8BBM 1 0 0 1 1 1 1 o Subtract memory
OUT 1 1 0 1 0 0 1 1 Output from A with borrow
INCREMENT AND DECREMENT 8UI 1 1 0 1 0 1 1 o Subtract immediate
INRr 0 0 D D D 1 0 0 Increment register from A
DCRr 0 0 D D D 1 0 1 Decrement register SBI 1 1 0 1 1 1 1 o Subtract immediate
INRM 0 0 1 1 0 1 0 0 Increment memory from A with borrow
DCRM 0 0 1 1 0 1 0 1 Decrement memory LOGICAL
INXB 0 0 0 0 0 0 1 1 Increment B & C ANAr 1 0 1 0 0 8 8 8 And register with A
registers XRAr 1 0 1 0 1 S 8 8 Exclusive OR
INXD 0 0 0 1 0 0 1 1 Increment D & E register with A
registers ORAr 1 0 1 1 0 8 8 8 OR register
INXH 0 0 1 0 0 0 1 1 Increment H & L with A
registers CMPr 1 0 1 1 1 8 8 8 Compare register
DCXB 0 0 0 0 1 0 1 1 Decrement B & C with A
DCXD 0 0 0 1 1 0 1 1 Decrement 0 & E ANAM 1 0 1 0 0 1 1 o And memory with A
DCXH 0 0 1 0 1 0 1 1 Decrement H & L XRAM 1 0 1 0 1 1 1 o Exclusive OR memol)l
with A
ADD
DRAM 1 0 1 1 0 1 1 o OR memory with A
ADDr 1 0 0 0 0 8 8 8 Add register to A
CMPM 1 0 1 1 1 1 1 o Compare
ADCr 1 0 0 0 1 8 8 8 Add register to A memory with A
with carry
ANI 1 1 1 0 0 1 1 o And immediate
ADDM 1 0 C 0 0 1 1 o Add memory to A with A
ADCM 1 0 0 0 1 1 1 o Add memory to A XRI 1 1 1 0 1 1 1 o Exclusive OR
with carry immediate with A
ADI 1 1 0 0 0 1 1 0 Add immediate to A ORI 1 1 1 1 0 1 1 o OR immediate
ACI 1 1 0 0 1 1 1 0 Add immediate to A with A
with carry CPI 1 1 1 1 1 1 1 o Compare
DADB 0 0 0 0 1 0 0 1 Add B & C to H & L immediate with A
16-29
inter 8085AH/8085AH-2/8085AH-1
Table 6. Instruction Set Summary (Continued)
Mnemonic Instruction Code . Operations Mnemonic Instruction Code Operations
D7 D6 Ds D4 D3 D2· D1 Do Description ~ D6 Ds D4 D3 D2 D1 Do Description
ROTATE CONTROL
RLC 0 0 0 0 0 1 1 1 Rotate A left EI 1 1 1 1 1 0 1 1 Enable Interrupts
RRC 0 0 0 0 1 1 1 1 Rotate A right DI 1 ,1 1 1, 0 0 1 1 Disable Interrupt
RAL 0 0 O. 1 0 1 1 1 Rotate A left NOP 0 0 0 0 0 0 0 0 No-operation
through carry HLT 0 1 1 1 0 1 1 0 Halt
RAR 0 0 0 1 1 1 1 Rotate A right
" through carry
NEW 8085AH INSTRUCTIONS
RIM 0 0 1 0 0 0 0 0 Read Interrupt
SPECIALS Mask
CMA 0 0 1 0 1 1 1 1 Complement A SIM 0 0 1 1 0 0, 0 0 Set Interrupt Mask
STC 0 0 1 1 0 1 1 1 Set carry
CMC 0 0 1 1 1 1 1 1 Complement carry
DAA 0 0 1 0 0 1 1 1 Decimal adjust A
NOTES:
1. DDS or SSS: B 000, 'C 001, D 010, E011, H 100, L101, Memory 110, A 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
"All mnemonics copyrighted @lIntel Corporation 1976.
16-30
8155H/8156H/8155H-2/8156H-2
2048-BIT STATIC HMOS RAM
WITH I/O PORTS AND TIMER
• Single + 5V Power Supply with 10%
• 1 Programmable 6-Bit 1/0 Port
•
Voltage Margins
30% Lower Power Consumption than
• Programmable 14-Blt Binary Counter1
Timer
the 8155 and 8156
• 256 Word x 8 Bits • Compatible with 8085AH and 8088 CPU
• • Multiplexed Address and Data Bus
•
Completely Static Operation
Internal Address Latch
• Available in EXPRESS
- Standard Temperature Range
• 2 Programmable 8-Bit 1/0 Ports - Extended Temperature Range
The Intel® 8155H and 8156H are RAM and I/O chips implemented in N-Channel, depletion load, silicon gate
technology (HMOS), to be used in the 8085AH and 8088 microprocessor systems. The RAM portion is
designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit
use with no wait states in 8085AH CPU. The 8155H-2 and 8156H-2 have maximum access times of 330 ns for
use with the 8085H-2 and the 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be
status pins, thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal
count pulse for the CPU system depending on timer mode.
PC, Vee
PC. PC.
101M
TIMER IN PC I
G
PAa - 7
RESET PC.
ADo 7 256 X 8 PC, PB,
STATIC TIMER OUT PBs
RAM 101M PBs
* PB.
ALE
RO
G PBo-7 AD
WR
ALE
AD.
PB,
PB.
PB,
PB.
WR AD, PA,
RESET TIMER
G PCa - s AD.
AD,
AD.
AD,
PAs
PAs
PA.
PA,
TIMER CLK vce 1+5V) AD. PA.
AD, PA,
TIMER OUT vss IOV)
vss PA•.
231719-1
'8155H/8155H·2 = ~,8156H/8156H-2 = CE 231719-2
Figure 1. Block Diagram Figure 2. Pin Configuration
December 1986
16-31 Order Number: 231719-001
inter . 8155H/8156H/8155H·2/8156H·2
Table 1. Pin Description
Symbol Type Name and FUl1ction
RESET I RESET: Pulse provided by the 8085AH to initialize the system (connect to
8085AH RESET OUT). Input high on this line resets the chip and initializes the
three I/O ports to input mode. The width of RESET pulse should typically be
two 8085AH clock cycle times.
ADo-7 I/O ADDRESS/DATA: 3-state Address/Data lines that interface with the CPU
lower 8-bitAddress/Data Bus. The 8·bit address is latched into the address
latch inside the 8155H/56H on the falling edge of ALE. The address c~ be
either for the memory section or the I/O section depending on the 10/Minput.
The 8·bit data..!!..either written into the chip or read from the chip, depending
on the WR or RD input signal.
CEorCE .I CHIP ENABLE: On the 8155H, this pin is CE and is ACTIVE LOW. On the
8156H, this pin is CE and is ACTIVE HIGH.
RD I READ CONTROL: Input low on this line with the Chip Enable activ~ enables
and ADo-7 buffers. If 10/M pin is low, the RAM content will be read out to the
AD bus. Otherwise the content of the selected I/O port or command/s.tatus .
registers will be read to the AD bus.
WR I WRITE CONTROL: Input low on this line with the Chip Enable active causes
the data on the Address/Data bus to bewritt~n to the RAM or I/O ports and
command/status register, depending on 10/M.
ALE I ADDRESS LATCH ENABLE: This control signal latches both the address on
the ADo-7 lines and the state of the. Chip Enable and 10/M into the chip at the
falling edge of ALE.
10/M I I/O MEMORY: Selects memory if low and I/O and command/status registers
if high.
PAO-7 (8) I/O PORT A: These 8 pins are general purpose I/O pins. The in/out direction is
selected by programming the command register.
PBO-7 (8) I/O PORT B: These 8 pins are general purpose I/O pins. The in/out direction is
selected by programming the command register.
PCo-s (6) 110 PORT C: These 6 pins can function as either input port, output port, or as
control signals for PA and PB. Programming is done through the command
register. When PCo-s are .used as control signals, they will provide the
following:
PCo-A INTR (Port A Interrupt)
PC,-ABF (port A Buffer Full)
PCr-A STB (Port A Strobe)
PCs-B INTR (Port B Interrupt)
PC4-B BF (Port B Buffer Full)
PCs':""B STB (Port B Strobe)
TIMER IN I TIMER INPUT: Input to the timer-counter.
TIMER OUT d . TIMER OUTPUT: This output can be either a square wa~e or a pulse,
d~pending on the timer mode.
Vee VOLTAGE: + 5V supply.
Vss GROUND: Ground reference.
16·32
8155H/8156H/8155H-2/8156H-2
FUNCTIONAL DESCRIPTION
I
The 8155H/8156H contains the following: I
I
e2K Bit Static RAM organized as 256 x8 I
I
e Two 8-bit I/O ports (PA & PB) and one 6-bit I/O I
port (PC) I
I
e 14-bit timer-counter I
TIMER
MODE I
The 101M (IO/Memory Select) pin selects either the L ____ _ _________ JI
five registers (Command, Status, PAO-7, PBO-7,
PCO-5) or the memory (RAM) portion. .
231719-3
The 8-bit address on the Address/Data lines, Chip
Enable input CE or CE, and 101M are all latched on- Figure 3. 8155H/8156H Internal Registers
chip at the falling edge of ALE.
CE(8155H)
\ V '\
OR
CE(8156H)
/ 1\ /
101M
\ V \
A°0-7
X ADQRESS
I\. I X DATA VALID
ALE
iiiiORWR
NOTE: 231719-4
For detailed timing information, see Figure 12 and A.C. Characteristics.
Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle
16-33
intJ 8155H/8156H/8155H-2/8156H-2
PROGRAMMING OF THE COMMAND READING THE STATUS REGISTER
REGISTER
The status register consists of seven latches, one
The command register consists of eight latches. for each bit; six (0-5) for the status of the ports and
Four bits (0-3) define the mode of the ports, two bits one (6) for the status of the timer.
(4-5) enable or disable the interrupt from port C
when it acts as control' port, and the last two bits The status of the timer and the liD section can be
(6-7) are for the ,timer. polled by reading the Status Register (Address
XXXXXOOO). Status word format is shown in Figure
The command register contents can be altered at 6. Note that you may never write to the status regis-
any time by using the liD address XXXXXOOO during ter since the command register shares the same liD
a WRITE operation with the Chip Enable active and address and the command register is selected when
101M = 1. The meaning of each bit of the command a write to that address is issued.
byte is defined in Figure 5. The contents of the com-
mand register may never be read.
r=
5 4 3 2 0
ITM. TM,I IEBI lEAl Pc.1 PC, PB I PA I
'--r---'
DF.FINESPAo-, }
0;; INPUT
. DEFINES P90-1 1 '" OUTPUT
, { 00- ALT 1
" • ALT 2
DEFINES PCo.. 01 • ALT 3
10 .. ALl'"
ENABLE PORT A }
INTERRUPT 1 '" ENABLE
'-----'-_ _ _ _ _ _ ~:::RL~U~RT B 0 • DISABLE
00· NOP - DO NOT AFFECT COUNTER
OPERATION
01 '" STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING JF THE TIMER IS
RUNNING
10" STOP AFTER Te - STOP IMMEDIATELY
L-..TIMER COMMAND AFTER PRESENT TC IS REACHEO (NOP
IF TIMER HAS NOT STARTED'
l' E START - LOAD MODE AND CNT LENGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNINGl. IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT Te
IS REACHED,
231719-5
Figure 5. Command Register Bit Assignment
AD, AD, ADs AD4 AD3 AD2 AD1 ADo
IXITIMFRI1N:el ~ IIN:RIIN;EI ':F liN;'
I I I T':'" PORT A INTERRUPT REQUEST
~ ~,.W"' .."'~_
(lNPUT/OUTPUTI
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
PORT B BUFFER FULL/EMPTY
UNPUTIOUTPUTI
PORT B INTERRUPT ENABLED
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED. AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESETI.
231719-6
Figure 6. Status Register Bit Assignment
16-34
inter 8155H/8156H/8155H-2/8156H-2
INPUTIOUTPUT SECTION ond is an output signal. indicating whether the
buffer is full or empty, and the third is an input pin
The 1/0 section of the 8155H/8156H consists of to accept a strobe for the strobed input mode.
five registers: (see Figure 7.) (See Table 2.)
• CommandlStatus Register (C/S)-Both regis-
When the 'C' port is programmed to either ALT3 or
ters are assigned the address XXXXXOOO. The
ALT4, the control signals for PA and PB are initial-
CIS address serves the dual purpose.
When the CIS registers are selected during ized as follows:
WRITE operation, a command is written into the
Control Input Mode Output Mode
command register. The contents of this register
are not accessible through the pins. BF Low Low
When the CIS (XXXXXOOO) is selected during a INTR Low High
READ operation, the status information of the 1/0 STB Input Control Input Control
ports and the timer becomes available on the
ADo_ilines.
1/0 Addresst
• PA Register-This register can be programmed Selection
to be either input or output ports depending on A7 A6 A5 A4 A3 A2 A1 AO
the status of the· contents of the CIS Register. X X X X X 0 0 0 Interval CommandlStatus
Also depending on the command, this port can Register
operate in either the basic mode or the strobed X X X X X 0 0 1 General Purpose 1/0 Port A
mode (see timing diagram). The 1/0 pins as- X X X X X 0 1 0 General Purpose 1/0 Port B
Signed in relation to this register are PAO-7. The X X X X X 0 1 1 Port C-General Purpose
address of this register is XXXXX001. 110 or Control
• PB Register-This register functions the same X X X X X 1 0 0 Low-Order 8 bits of Timer
as PA Register. The I/O pins assigned are Count
PBO-7. The address of this register is XXXXX010. X X X X X 1 0 1 High 6 bits of Timer Count
and 2 bits of Timer Mode
• PC Register-This register has the address
X: Don't Care.
XXXXX011 and contains only 6 bits. The 6 bits t: 1/0 Address must be qualified by CE = 1 (8156H) or CE
can be programmed to be either input ports, out- = 0 (8155H) and 101M = 1 in order to select the appropri-
put ports or as control signals for PA and PB by ate register.
properly programming the AD2 and AD3 bits of Figure 7. 1/0 Port a.nd Timer Addressing Scheme
the CIS register.
When PCO-5 is used as a control port, 3 bits are Figure 8 shows how 1/0 PORTS A and B are struc-
assigned for Port A and 3 for Port B. The first bit tured within the 8155H and 8156H:
is an interrupt that the 8155H sends out. The sec-
8155H/8156H One Bit of Port A or Port B
NOTES:
(1) Output Mode
(2) Simple Input
1 Multiplexer
. Control
231719-7
(4) = 1 for Output Mode
(3) Strobed Input = 0 for Input Mode
READ Port = (101M = 1) • (RD = 0) • (CE Active) • (Port Address Selected)
WRITE Port = (101M = 1) • (WR = 0) • (CE Active) • (Port Address Selected)
Figure 8. 8155H/8156H Port Functions
16-35
inter
."
8155H/8156H/8155H-2/8156H-2
Table 2 Port Control Assignment
Pin ALT1. ALT2 ALT3 ALT4
PCO Input Port Output Port . A INTR (Port A Interrupt) .A INTR (Port A Interrupt)
PC1 Input Port Output Port A SF (Port A Buffer Full) A BF (Port A Buffer FiJlI)
PC2 Input Port Output Port A 13TB (Port A Strobe) A STB (Port A Strobe)
PC3 Input Port· Output Port Output Port B INTR (Port B Interrupt)
PC4 Input Port Output Port Output Port B BF (Port B Buffer Full)
PC5 Input Port . Output Port Output Port B STB (Port B Strobe)
Note in the diagram that when the 1/0 ports are pro- TIMER SECTION
grammed to be output ports, the contents of the out-
put ports can still be read by a READ operation The time is a 14-bit down-counter that counts the
when appropriately addressed. TIMER IN pulses and provides either a square wave
or pulse when terminal count (TC) is reached.
The outputs of the 8155H/8156H are "glitch-free"
meaning that you can write a "1" to a bit position The timer has the. 1/0 address XXXXX100 for the
that was previously "1" and the level at the output low order byte of the register and the I/O address
pin will not change. XXXXX101 for the high order byte of the register.
(See Figure 7.)
Note also that the output latch is cleared when the
port enters the input mode. The output latch cannot To program the timer, the COUNT LENGTH REG is
be loaded by writing to the port if the port is in. the loaded first, one byte at a time, by selecting the tim-
input mode. The result is that each time a port mode . er addresses. Bits 0-13 of.the high order count reg-
is changed from input to output, the output pin will ister will specify the length of the next count and bits
go low. When the 8155H/56H is RESET, the output 14-15 of the high order register will specify the timer
latches are all cleared and all 3 ports enter the input output mode (see Figure 10). The value loaded into
mode. . the count length register can· have any value from
2H through 3FFFH in Bits 0-13. .
When in the ALT 1 or ALT 2 modes, the. bits of
PORT C are structured like the diagram above in the
simple input or output mode, respectively. 765432·10
I~I~I~I~I~I~I~I~I
Reading from an input port with nothing connected ~' r
TIMER MODE MSB OF CNT LENGTH
to the pins will provide unpredictable results.
7 6 5 4 3 2 ,1 O'
Figure 9 shows how the 8155H/8156H 1/0 ports I~I~I~I~I~I~I~I~I
, ,
might be configured in a typical MCS®-85 system.
LSB OF CNT LENGTH
231719-9
I
TO 8085AH RST INPUT
Figure 10. Timer Format
--1
PORTA OUTPUT PORT A
A tNTR ISIGNALS DATA RECEIVED)
A SF (SIGNALS DATA READY) There are four modes to choose from: M2 and M1
}-~
A 5Ta (ACKNOWL. DATA RECEIVED) define the timer mode, as shown in Figure 11.
PORTC B STa (LOADS PORT B LATCH) PERIPHERAL
INTERFACE
B BF (SIGNALS BUFFER IS FULLI
B tNTR (SIGNALS BUFfER
READY FOR READING)
PORTB INPUT MODE START TERMINAL (TERMINAL)
TO INPuJ PORT (OPTIONALI BITS COUNT COUNT COUNT
TO 8085AH RST INPUT M2 M, ~ _____ i ____ .
o 1. SINGLE
231719-8 0
saUAAEWAVE
Figure 9. Exa,mple: 2. CONTINUOUS
saUAREWAVE
Command Register = 00111001
3. ~~~~iEON ---"~--------.--'
TERMINAL COUNT
4. CONTINUOUS
PULSES' -----,ur----~
231719-10
Figure 11. Timer Modes
16-36
inter 8155H/8156H/8155H-2/8156H-2
Bits 6-7 (TM2 and TM1) of command register con- The counter in the 8155H is not initialized to any
tents are used to start and stop the counter. There particular mode or count when hardware RESET oc-
are four commands to choose from: curs, but RESET does stop the counting. Therefore,
TM2 TM1 counting cannot begin following RESET until a
o 0 Nap-Do not affect counter operation. START command is issued via the CIS register.
o 1 STOP-Nap if timer has not started; stop
counting if the timer is running. Please note that the timer circuit on the 6155HI
o STOP AFTER TC-Stop immediately after 8156H chip is designed to be a square-wave timer,
present TC is reached (Nap if timer has not an event counter. To achieve this, it counts
not started) down by twos twice in completing one cycle. Thus,
START-Load mode and CNT.length and its registers do not contain values directly represent-
start immediately after loading (if timer is ing the number of TIMER IN pulses received. You
not presently running). If timer is running, cannot load an initial value of 1 into the count regis-
start the new mode and CNT length im- ter and cause the timer to operate, as its terminal
mediately after present TC is reached. count value is 10 (binary) or 2 (decimal). (For the
detection of single pulses, it is suggested that one of
Note that while the counter is counting, you may the hardware interrupt pins on the 8085AH be used.)
load a new count and mode into the count length After the timer has started counting down, the val-
registers. Before the new count and mode will be ues residing in the count registers can be used to
used by the counter, you must issue a START com- calculate the actual number of TIMER IN pulses re-
mand to the counter. This applies even though you quired to complete the timer cycle if desired. To ob-
may only want to change the count and use the pre- tain the remaining count, perform the following oper- ,
vious mode. ations in order:
1. Stop the count
In case of an odd-numbered count, the first half-cy- 2. Read in the 16-bit value from the count length
cle of the squarewave output, which is high, is one registers
count longer than the second (low) half-cycle, as
shown in Figure 12. 3. Reset the upper two mode bits
4. Reset the carry and rotate right one position all 16
bits through carry
5. If carry is set, add % of the full original count (%
full count-1 if full count is odd).
NOTE:
If you started with an odd count and you read the
count length register before the third count pulse
occurs, you will not be able to discern whether one
5
or two counts has occurred. Regardless of this, the
231719-11 8155H/56H always counts out the right number of
pulses in generating the TIMER OUT waveforms.
NOTE:
5 and 4 refer to the number of clocks in that time peri-
od. .
Figure 12. Asymmetrical Square-Wave Output
Resulting from Count of 9
16-37
8155H/8156H/8155H-2/8156H-2
8085AH MINIMUM SYSTEM • 2K Bytes EPROM
CONFIGURATION • 38110 Pins
Figure 13a shows a minimum system using three • 1 Interval Timer
chips, containing: • 4 Interrupt Levels
• 256 Bytes RAM
J\
A8-15
Y1 _J\
ADO·1 )
, r-
~
ALE
asAN jjjj
WA t--
101M t--
ClK
r---
RESET OUT
t--
READY
t--
t--
Vee
RESET
TIMER.
IN WARD ALE CE:-; .7 101M ,
,
7:~~ 7: 0
_101
0-7 CE M
ALE jjjj~Oii ClK RS ROY
J:
'-!. LATCHES J
T:'~~R_
G -~~
CONTROL
256 x 8
RAM
8755A (EPROM + 1/0)
,,- ~ I
~~cp~
B88 88 231719-12
Figure 13a. 8085AH Minimum System Configuration (Memory Mapped I/O)
16-38
inter 8155H/8156H/8155H-2/8156H-2
8088 FIVE CHIP SYSTEM • 38 1/0 Pins
,. 1 Interval Timer
Figure 13b shows a five chip system containing: • 2 Interrupt Levels
• 1.2SK Bytes RAM
• 2K Bytes EPROM
~ Vss Vee
j j
H- ~ POR!fOV
>--_WR ~
AD PORT (8)
11111101 8
...
ALE
DATAl
ADDR
PORT
C W (6)
IN_
" 101M TIMER
OUT f--
RESET
As-A19 AD DR lOW
RD
A p-,
~
ADDRIOATA ALE
. - - CLKADo-AD7
T~
PORT
" CE A
L-
... A8 _10
8088 /,-- V 1755A-I
~ READY ... DATAl
--I
MN/MX f--Vee ADDR
Vee
rD1 ALE f- ~ 101M PORT
~4
RST@ AD f- I-- I- RESET 8
X, X,
CLK 'NA f- READY Vee
READY I-- 101M i-- ~-l
liES .-- i--
8284
f-
III LROG
?'"
RESET Vss Vee Voo
Vee
RDY'
WR
6
GND
GND
MANUAL,
RESET
.... RD
(V,,) G) CE,
118502
ALE
If- <:S,
I~
i-- CE,
f- A•• Ag
"'"-
ADO_7
"
I J
V" Vee
,
231719-13
Figure 13b. 8088 Five Chip System Configuration
16-39
8155HI8156H/8155H-2/8156H-2
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent dam-
Temperature Under Bias ............ O·C to + 70·C' age to the device. This is a stress rating only and
Storage Temperature .......... - 65·C to + 150·C functional operation of the device at, these or any
other conditions above those indicated in the opera-
Voltage on Any Pin
with Respect to Ground .......... -O.5V to + 7V ' tional sections of this specification is not impliecl.' Ex-
posure' to absolute maximum rating conditions for
Power Dissipation .......................... 1.5W extended periods may affect device reliability.
D.C., CHARACTERISTICS TA = 0·Ct070·C, Vcc = 5V ±10%
Symbol Parameter Min Max Units Test Conditions
,
Vil Input LowVoltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vcc+ 0.5 V
Val Output Low Voltage 0.45 V IOl = 2mA
VOH Output High Voltage 2.4 V IOH = -400 p-A
III Input Leakage, ±10 p-A OV ~ VIN ~ Vcc
ILO Output Leakage Current ±10 p-A 0.45V ~ VOUT ~ Vcc
Icc Vcc Supply Current 125 mA
III (CE) Chip Enable Leakage
8155i-f -, +100 p-A OV ~ VIN ~ Vcc
8156H -100 p-A '
A.C. CHARACTERISTICS TA = O·C to 70·C, Vcc = 5V ± 10%
'8155H/8156H 8155H-2/8156H-2
Symbol Parameter Units
Min Max Min Max
tAL Address to Latch Setup Time 50 30 ns
tLA Address Hold Time after Latch 80 30 ns
tlC Latch to ,READ/WRITE Control 100 40 ns
tRO Valid Data Out Delay from READ Control 170 140 ns
tLO Latch to Data Out Valid 350 270 n,s
tAD Address Stable to Data Out Valid 400 330 ns
tll Latch Enable Width 100 70 ns
tROF Data Bus Float after READ 0 100 0 80 ns
tCl READ/WRITE Control to Latch Enable 20 10 ns
tCll WRITE Control to Latch Enable for CIS Register 125 125 ns
tcc READ/WRITE Control Width 250 200 ns
tow Data In to WRITE Setup Time 150 100 ns
two Data In Hold Time after WRITE 25 25 ns
tRV Recovery Time between Controls 300 200 ns
twp WRITE to Port Output 400 300 ns
16-40
8155H/8156H/8155H-2/8156H-2
A.C. CHARACTERISTICS TA = O·C to 70·C, Vee = 5V ± 10% (Continued)
8155H/8156H 8155H-2/8156H-2
Symbol Parameter Units
Min Max Min Max
tPR Port Input Setup Time 70 50 ns
tRP Port Input Hold Time 50 10 ns
tSBF Strobe to Buffer Full 400 300 ns
tss Strobe Width 200 150 ns
tRBE READ to Buffer Empty 400 300 ns
tSI Strobe to INTR On 400 300 ns
tRDI READ to INTR Off 400 300 ns
tpss Port Setup Time to Strobe 50 0 ns
tpHS Port Hold Time After Strobe 120 100 ns
tSBE Strobe to Buffer Empty 400 300 ns
tWBF WRITE to Buffer Full 400 300 ns
tWI WRITE to INTR Off 400 300 ns
tTL TIMER-IN to TIMER-OUT Low 400 300 ns
tTH TIMER-IN to TIMER-OUT High 400 300 ns
tRDE Data Bus Enable from READ.Control 10 10 ns
t1 TIMER-IN Low Time 80 40 ns
t2 TIMER-IN High Time 120 70 ns
twr WRITE to TIMER-IN 360 200 ns
(for writes which start counting)
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
231719-14
DEVICE
UNDER
TEST
i cl = 150pF
A.C. testing: inputs are driven at 2.4V for a logic "I" and O.45V for
a logic "0". Timing measurements are made at 2.0V for a logic 231719-15
"I" and O.BV for a logic "0".
CL = 150 pF
CL Includes Jig Capacitance
16-41
inter 8155H/8156H/8155H-2/8156H-2
WAVEFORMS
READ
CEC1155HI / '\
CECI15IHI /- \. /
-
101M \ V \
lAO
7
>- ADDRESS
>-
DATA VALID
~
- tAl - - t LA -
Al E
/ i\ ~
_t AOf _
- t LL- - I--t ROF -
_ILC-~
_tRD_
1/
"-
_ I CC · -
- -tel-
_ t Rv -
ILO
231719-16
WRITE
151H) \ / \
aR
CE(I158H)
/ '"'\ 7
lolM'
\ I '\
AO O_7
X ADDRESS
K )~ DATA VALID
~
I- I AL- f---t LA - _ t ow - _ t el -
ALE
J ~ V
l - t LL - _ t LC -==1 I- two---':""
Wi!
tCLL---l 1- tee ------
\I
IWT
_ t Rv -
~-
I--
TIMER IN j
"
231719-17
16-42
inter 8155H/8156H/8155H-2/8156H-2
WAVEFORMS '(Continued)
STROBED INPUT
OF
INTR
INPUT DATA
FROM PORT
------------------~~-----+----~~-------------------------------------------------------------
231719-18
STROBED OUTPUT
OF
INTR
'w,
OUTPUT DATA
TO PORT
--------------------------------------------~~------------------------------------------------------
231719-19
BASIC INPUT BASIC OUTPUT
RD
}
'.P J -I WR
'NPUT ==x 'P. \...
k DATA BUS·
OATABUS· - -- -
-------
- - =x OUTPUT
231719-20 231719-21
'Data Bus Timing is shown in Figure 7,
16-43
~
:e
ii!
m
::D
0
c:
»
<
m
."
(
~ 0
"tI
c: :::u
~ 3:
0
en
0
c:
'0
0
z ~
~ :::l
c
_I C
I~
<D
I
LOAD COUNTER FROM CLR
2 I 5 3
RELOAD COUNTER FROM CLR
I 2 I -\ 5
.s
""::D0 ....co
s::: en
TIMER IN en
en ::r:
......
~
0 ....
CO
en
en
TIMER OUT
\ INOTE 1) II
::r:
......
IPULSEI ___ J
~
\~
....enCO
en
::r:
~
......
TlMEROOT
I
ISQUARE WAVE)
\
\
INOTE 11
I ....
CO
en
~...,-------..1 en
::r:
~
231719-22
NOTE:
1. The timer output is periodic if in an automatic reload mode (Ml Mode bit = 1).
intJ 8185/8185·2
1024 x 8·BIT STATIC RAM FOR MCS®·85
• Multiplexed Address and Data Bus • Low Standby Power Dissipation
• Directly Compatible with B085AH and • Single + 5V Supply
8088 Microprocessors • High Density 1B-Pln Package
• Low Operating Power Dissipation·
The Intel 8185 is an 8192·bit static random access memory (RAM) organized as 1024 words by 8·bits using N·
channel Silicon·Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface
directly to the 8085AH and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185·2 is a high·speed selected version of the 8185 that is compatible with the 5 MHz 8085AH·2 and the
5 MHz 8088.
ADD Vee
, cs
CE,
. AD,
A~
RD
WR
CE2
RD RJW AD3 ALE
LOGIC
WR
ALE AD4 CS
l ADs
AD6
CE,
CE2
~ AD7 A9
DATA tK.'
BUS RAM
BUFFER MEMORY Vss As
V ARRAY
231450-2
.X.YDECODE
Figure 2. Pin Configuration
~'="~~
Pin Names
ADo-AD7 AddresslData Lines
As.Ag Aa. A9 Address Lines
ALE CS Chip Select
231450-1 CEl Chip Enable (101M)
Figure 1. Block Diagram CE2 Chip Enable
ALE ,Address Latch Enable
WR Write Enable
May 1987
16·45 Order Number: 231450-002
8185/8185-2
FUNCTIONAL DESCRIPTION
The 8185 has been designed to provide for direct
r1Dh
Vss Vee
interface to the multiplexed bus structure and bus III
timing of the 8085A microprocessor.
--- TRAP
RST7,5
X, X, RESET IN
HOLD
HLDA
I-
r-
At the beginning of an 8185 memory access cycle,
the 8-bit address on ADo_i, As and Ag, and the
status of GEl and GE2 are all latched internally in
--- RSTB,5
RST5.5
INTR
TN'fA ADDR/
SOS5A
RESET
OUT
SOD
SID
s,r-
"of-
r-
I-
the 8185 by the falling edge of ALE. If the latched ADDR DATA ALE ml WR IO/~ RovelK
status of both GEl and GE2 are active, the 8185
powers itself up, but no action occurs until the GS
(8' C8, Vi' Vr
line goes low and the appropriate RD or WR control 11-- CE
.
PORT~
A
signal input is activated. .
WR PORT ~
8
RDS156B ('
The GS input is not latched by the 8185 in order to
ALE PORT~
allow the maximum amount of time for address de- DATAl C (61
coding in selecting the 8185 chip. Maximum power ADDR'
IN
consumption savings will occur, however, only when
GEl and GE2 are activated selectively to power 1-- -
101M TIMER
RESET OUT
:::
down the 8185 when it is not in use. A possible con-
nection wduld be to wire the 8085A's IOlM line to lOW .
the 8185's GEl input, thereby keeping the 8185 AD
powered down during liD and interrupt cycles.
Table 1. Truth Table for H-
ALE
CE
PORT
A ¢!!>
Power Down and Function Enable ~~ AoIO
S755A
CE1 CE2 CS (CS*)(2) 8185 Status DATAl
ADDR
1 X X 0 Power Down and
Function Disable(l) 1-r- f-
101M
RESET
ROY
PoRT
' B W
X 0 X 0 Power Down and I- CLK
Function Disable(l)
0 1 1 0 powered Up and
~1 v!c vtD tRaG
Function Disable(l) WR
AD
0 1 0 1 Powered Up and
CE'·S1·S5
Enabled ALE
NOTES: ~- CS.CE2
X = Don't Care. . .' ~- ,. Aa.Ag
1: Function Disable 'implies Data Bus· in high impedance ADo.7
state and not writing.
x
2: CS· = (CEl = 0) X (CE2 == 1) (CS = 0).
CS· = 1 signifies all chip enables and chip select ac-
tive.
vt L Vee
Vee
Table 2. Truth Table for
Control and Data Bus Pin Status 231450-3
ADo,-'; During Data Figure 3. 8185 In an MCS®-85 System
(CS*) RD WR 8185 Function
Portion of Cycle
4 Chips:
0 X X Hi-Impedance . No FU'lction 2K Bytes EPROM
1.25K Bytes RAM
1 0 1 Data from Memory Read 38110 Lines
1 1 0 Data to Memory Write 1 CounterITlmer
2 Serial 110 Lines
1 1 1 Hi-Impedance Reading, but not 5 Interrupt Inputs
Driving Data Bus
NOTE:
X = Don't Care.
16-46
8185/8185-2
iAPX 88 FIVE CHIP SYSTEM:
• 1.2SK Bytes RAM
• 2K Bytes EPROM
• 38 I/O Pins
• 1 Internal Timer
• 2 Interrupt Levels
/). V•• Vee
I I
I ~I- ~ POR!~
WR
RD POR~ k A
(81 >
.1_
ALE PORTkA>
~ DATAl C (61
ADDR
"f ~ IN_
101M TIMER
RESET
OUT f.-
Aa AI, ADDR iOW
v Ali
~
/1
~
ADDR/DATA ALE
.---- CLKAOo- ADr
'J
J~ ee
PORT
A
.-
8088
READY
:= "-
V
Aa_1o
,1755A02
DATAl
MNIMX I--vee ADDR
y
rD1 ALE ~ ~
~
r
Vee 101M PORT
r- RST ® RD l- I - I-- RESET B
X, x,
WR I-
l4
ClK
READY
Vee
READY I-- 101M ~ iDA -.J
RES ~
I284A
RESET
r---
I-
III
Vss Vee VDD
LROG
RDY1 Vee
I~ GND
MANUAL ....
W1i
Ali
GND RESET
(Vss) CD ee, .1115-2
ALE
\1- es.
Irl- CE,
II-I- AI,A,
V ADo·,
Iv•• t Vee
, 7
231450-4
Figure 4. IAPX 88 Five Chip System Configuration
16-47
8185/8185-2
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under ':4bso-
lute Maximum Ratings" may cause permanent dam-
Temperature Under Bias ............ O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .......... -65·C to + 150·C functional operation of the device at these. or any
Voltage on Any Pin other conditions above those indicated in the opera-
with Respect to Ground .......... - 0.5V to + 7V tional sections of this specification is not implied. Ex-
Power Dissipation .......................... 1.5W posure to absolute maximum rating conditions for
extended periods may affect device reliability..'
D.C. CHARACTERISTICS TA = 0·Ct070·C, Vcc = 5V ±10%
Symbol Parameter Min Max Units Test Conditions
Vil Input Low, Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vcc+ 0.5 V
VOL Output Low Voltage' 0.45 V IOl = 2mA
VOH Output High Voltage 2.4 IOH = -400 p.A
III Input Leakage ±10 p.A OV ~ VIN ~ Vcc
ILO ., " Output Leakage Current ±10 p.A 0.45V ~ VOUT ~ Vcc
Icc Vcc Supply Current
100 mA
Powered Up
Powered Down 35 mA
A.C. CHARACTERISTICS TA= 0·Ct070·C, Vcc = 5V ±10%
8185 8185·2
Symbol Parameter
Min Max Min Max Units
tAL Address to Latch Set Up Time 50 30 ns
tLA Address Hold Time After Latch 80 30 ns
tlC Latch to READ/WRITE Control 100 40 ns
tAO Valid Data Out Delay from READ Control 170 140 ns
tLD ALE to Data Out Valid 300 200 ns
tll Latch Enable Width 100 70 ns
tAOF Data Bus Float After READ 0 100 0 80 ns
tel READ/WRITE Control to Latch Enable 20 10 ns
tcc READ/WRITE Control Width 250 200 ns
tow Data In to WRITE Set Up Time 150 150 ns
two Data In Hold Time After WRITE 20 20 ns
tsc Chip Select Set Up to Control Line 10 10 ns
tcs Chip Select Hold Time A~er Control 10 10 ns
tAlCE Chip Enable SetUp to ALE Falling 30 10 ns
tLACE Chip Enable Hold Time After ALE 50 30 ns
16-48
inter 8185/8185-2
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
"=X >
0.45
2.0
0.8
TEST POINTS < )C
. 2.0
0.8
DEVICE
UNDER
TEST
i Cl = IS0pF
231450-5
221450-6
A.C. Testing: Inputs Are Driven at 2,.4V for a Logic "I" and
0.45V for a Logic "0." Timing Measurements Are Made at CL=150pF
.2.OV for a Logic "I" and O.SV for a Logic "0."
CL Includes Jig Capacitance
WAVEFORM
ALE
(CE1-01-
(CE2'"'l'
WR.RD
ADO-AD1 IREAD CYCLE)
(As.Asl
--.cc----I
ADO-AD7 (WRITE CYCLE I
cs.
(SELECTEDl {DESELECTEDl
231450-7
16-49
intJ 8224
CLOCK GENERATOR AND DRIVER
FOR 8080A C.PU
. Single Chip Clock Generator/Driver for
8080A CPU • Crystal Controlled for Stable
System Operation
• Power-Up Reset for CPU
• Available
Reduces System Package Count
• Ready Synchronizing Flip-Flop
• - Standardin EXPRESS
Temperature Range
• Advanced Status Strobe
• Available in 16-Lead Cerdip Package
• Oscillator Output for External System
Timing (See Packaging Spec, Order #231369)
The Intel 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, seiected
by the designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.
RESET Vee
RESIN XTAL1
RDYIN XTAL2
§> XTAL1
,....,.----I>---osc IE> READY TANK
1!9 XTAL2
I!D TANK
I--i~---~, [E>
SYNC
.. ~, (TTLI .,
osc
STSTB ~,
I--i~---., §>
GND VDD
I-----¢,ITTLI(D
231464-2
ID SYNC ----t----ll-..,
RESiN Reset Input
IV mrN --I,>-t-l RESET Reset Output XTAL 1 } Connections
XTAL2 for Crystal
l -........--RESET II> RDYIN Ready Input
READY Ready Output TANK Us9d with Overtone XTAL
IV RDYIN --,...---+-1 t----READY[9
OSC Oscillator Output .
SYNC Sync Input
STSTB StatusSTB <l>2(lTL) <1>2 CLK (TTL Level)
231464-1 (Active Low) Vee +5V
Figure 1. Block Diagram ~ } 801i0 Voo +12V
<1>2 Clocks GND OV
Figure 2. Pin Configuration
December 1986
16-50 Order Number: 231464-001
inter 8224
ABSOLUTE MAXIMUM RATINGS* • Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent dam-
Temperature Under Bias ............ O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature .......... -65·C to + 150·C functional operation of the device at these or any
other conditions above those indicated in the opera-
Supply Voltage, Vee ............... -0.5V to + 7V
tional sections of this specification is not implied. Ex-
Supply Voltage, VOD ............ -0.5V to + 13.5V posure to absolute maximum rating conditions for
Input Voltage ..................... -1.5V to + 7V extended periods may affect.device reliability.
Output Current .......................... 100 mA
D.C. CHARACTERISTICS
TA = O·Cto +70·C, Vee = +5.0V ±5%, Voo = +12V ±5%
Limits
Symbol Parameter Units Test Conditions
Min Typ Max
IF Input Current Loading -0.25 mA VF = 0.45V
IR Input Leakage Current 10 ,."A VR = 5.25V
Ve Input Forward Clamp Voltage 1.0 V Ie = -5mA
VIL Input "Low" Voltage 0.8 V Vee = 5.0V
VIH Input "High" Voltage 2.6 V Reset Input ..
2.0 V All Other Inputs
VIWVIL RESIN Input Hysteresis 0.25 V Vee = 5.0V
VOL Output "Low" Voltage 0.45 V (4)1, 4>2), Ready, Reset, STSTB
IOL = 2.5mA
0.45 V All Other Outputs
IOL = 15 mA
VOH Output "High" Voltage
4>1, 4>2 9.4 V IOH = -100,."A
READY,RESET 3.6 V IOH = -100,."A
All Other Outputs 2.4 V IOH = -1 mA
lee Power Supply Current 115 mA
100 Power Supply Current 12 mA
NOTE:
1. For crystal frequencies of 18 MHz connect 510n resistors between the Xl input and ground as well as the X2 input and
ground to prevent oscillation at harmonic frequencies.
Crystal Requirements
Power Dissipation (Min): 4 mW
Tolerance: 0.Q05% at 0·C-70·C
Resonance: Series (Fundamental)' "NOTE:
Load Capacitance: 20 pF-35 pF With tank circuit use 3rd overtone mode.
Equivalent Resistance: 750-200
16-51
inter 8224
A.C. CHARACTERISTICS
Limits Test
Symbol Parameter Units
Min Typ Max Conditions
t.,,1 <1>1 Plllse Width 2tcy
--20ns
9
t.,,2 <1>2 Pulse Width 5tcy
--35ns
9
t01 <1>1 to <1>2 Delay 0
t02 <1>2 to <1>1 Delay 2tcy ns CL= 20pFt050pF
.--.14ns
9
t03 <1>1 to <1>2 Delay 2tcy 2tcy
9 + 20ns
9
tR <1>1 and <1>2 Rise Time 20
tF <1>1 and <1>2 Fall Time 20
to.,,2 <1>2 to <1>2 (TIL) Delay :-5 +15 ns <l>2TIL,CL = 30
R1 :: 3000.
R2 = soon
toss <1>2 to STSTB Delay Stcy _ 30 ns 6tcy
ns
9 9
tpw STSTB Pulse Width tcy STSTB, CL = 15 pF
- -15ns
9 R1 = 2K
RDYIN Setup Time to 4tcy R2 =4K
tORS 50ns-- ns
Status Strobe 9
RDYIN Hold Time 4tcy
tORH afterSTSTB 9
RDYIN or RESIN to 4tcy Ready & Reset
tOR --25ns
<1>2 Delay 9 CL = 10pF
ns
R1 = 2K
R2 = 4K
tCLK CLKPeriod tcy ns
9
Maximum Oscillating 27 MHz
fmax
Frequency,
Cin Input Capacitance 8 pF VCC = +5.0V
VOO = +12V
VSIAS = 2.5V
'f = 1 MHz
NOTE:
These formulas are based on the internal workings of the part and intended for customer convenience. Actual testing of the
part is done at Icy = 488.28 ns.
1S-52
8224
A.C. CHARACTERISTICS (Continued)
For tey = 488.28 ns; TA = O·C to 70·C, Vee = +5V ±5%, VOO = +12V ±5%
LImits
Symbol Parameter Units Test Conditions
Min Typ Max
t</>1
t4>2
<P1 Pulse Width
<P2 Pulse Width
89
236
ns
ns
- tey = 488.28 ns
t01 Delay <P1 to <P2 0 ns
t02 Delay <P2 to <P1 95 ns <P1 & <P2 Loaded to
Delay <P1 to <P2 Leading Edges 109 129 ns CL = 20 pF to 50 pF
t03
tr Output Rise Time 20 ns
tf
toss
Output Fall Time
<P2 to STSTB Delay 296
20
326
ns
ns
-
to</>2 <P2 to <P2 (TTL) Delay -5 +15 ns
tpw Status Strobe Pulse Width 40 ns Ready & Reset Loaded
to 2 mAl 10 pF
tORS RDYIN Setup Time to STSTB -167 ns
All measurements
tORH RDYIN Hold Time after STSTB 217 ns referenced to 1.5V
tOR READY or RESET 192 ns unless specified
to <P2 Delay otherwise.
fMAX Oscillator Frequency 18.432 MHz
A.C. TESTING, INPUT,
OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
-r-Vcc
R,
DEVICE
UNDER
TEST
~ R2
C'i
~
231464-3
-=- -:;:-
A.C. Tesling: Inputs are driven at 2.4V for a logic "1" and 0.45V 231464-4
for a logic "0". Timing measurements are made at 2.0V for a
logiC "1" and O.SV for a logic "0" (unless otherwise noted). CL Includes Jig Capacitance
16-53
8224
WAVEFORMS
~----~------~------b------------------~
.,
., ----~~------~~------~ ~------
¢ZITTLI
SYNC
IFROM 8OBOAI
i-----tORH'-----t
~Ir~--------------,I,--------- -------------------
ROVIN OR R~~IN
- ;. . - - - - - - - - - - -'1'-----------+-----------------------
READY OUT
-------------------'r--~----+_----~~~------------
RESHOUT
231464-5
VOLTAGE MEASUREMENT POINTS: <1>1, <1>2 Logic "0" = 1.0V, Logic "1" = B.OV. All other signals measured at 1.5V.
CLOCK HIGH AND LOW TIME (USING X1, X2)
Xl eLK
18MHz 0"'T
X2
Rl R2
":-
- 231464-6
16-54
intJ 8228
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
• Single Chip System Control for
MCS®·80 Systems • User Selected Single Level Interrupt
Vector (RST 7)
• Built·ln Bidirectional Bus Driver for
Data Bus Isolation • Available in EXPRESS
- Standard Temperature Range
• Allows the Use of Multiple Byte
Instructions (e.g. CALL) for Interrupt • Available in 28·Lead Cerdip and Plastic
Packages
Acknowledge (See Packaging Spec, Order #231369)
• Reduces System Package Count
The Intel® 8228 is a single chip system controller and bus driver for MCS®-80. It generates all signals required
to directly interface MCS-80 family RAM, ROM, and I/O components.
A bidirectional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080
data bus from memory and lID. This allows for the optimization of control signals, enabling the systems
designer to use slower memory and lID. The isolation of the bus driver also provides for enhanced system
noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small
system requirements. The 8228 also generates the correct control signals to allow the use of multiple byte
instructions (e.g., CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large,
interrupt driven systems to have an unlimited number of interrupt levels. .
The 8228 is deSigned to support a wide variety of system bus structures and also reduce system package
count for cost effective, reliable design of MCS-80 systems.
NOTE:
The specifications for the 3228 are identical with those for the 8228.
CPU
DATA
BUS 1 0.-
0,_
°2-
°3-
0,_
0 .. -
0,-
0,-
_aBo}
- O B1
- ° 82
::: g:!
-as,
-DB,
- O B7 _
SYSTEM DATA BUS
.
.
III ~
~LATCH
STATUS
GATING
ARRAY
S'rSfii _ _ _ _ _ _ _ _ _-'
231465-2
m ---------------l
____________________
OlIN ~
07·00 DalaBus (80BO Side) INTA Interrupt Acknowiedge
HLDA -------------iL~~-- IlIITA 087·080 Data Bus (System Side) HlDA HLDA ('rom B080)
1100 /10 Reed WI! WR (from aOBO)
231465-1
,"OW 110 Write
= Bus Enable Input
Figure 1. Block Diagram tfEfJR
~
Memory Read
MemoryWri1e
=
Vee
Status Strobe (Irom 8224)
+5V
DelN CaiN (Irom 8080) GND o Volta
Figure 2. Pin Configuration
September 1987
16-55 Order Number: 231465-002
inter 8228
ABSOLUTE MAXIMUM RATINqS*· *Notice: Stresses above those listed under ':Abso-
lute Maximum Ratings" may cause permanent dam-
Temperature Under Bias ............ O'C to+ 70'C age to the device. This is a stress rating only and
Storage Temperature .......... - 65'C to + 150'C functional operation of the device at these or any
other conditions. above those indicated in the opera-
Supply Voltage, Vee ............... ":'05V to + 7V tional sections of this specification is not implied Ex-
Input Voltage ...................... -1.5 to + 7V posure to absolute maximum rating conditions for
Output Current ...... :' .......... , ....... ,.100 mA ex/ended periods may affect device reliability.
D.C. CHARACTERISTICS TA = O'Cto +70'C, Vee = 5V ±5%·
limits
Symbol Parameter Unit Test Conditions
Min Typ(1) Max
Ve Input Clamp Voltage, 0.75 ~1.0 V Vee = 4.75V; Ie = -5 mA
All Input
IF Input Load Current STSTB .500 p.A Vee = 5.25V
02&06 750 p.A VF = 0.45V
00,01,04, 250 p.A
05&07
All Other Inputs 250 p.A
IR Input Leakage Current STSTB 100· p.A Vee = 5.25V
VR = 5.25V
OBo-OB7 20 p.A
All Other Inputs "100 p.A
VTH Input Threshold O.S 2.0 V Vee =5V
Voltage. All Inputs
lee Power Supply Current 140 190 mA Vee = 5.25V
VOL Output Low Voltage 00- 0 7 0.45 V Vee = 4.75V; 10L = 2 rnA
All Other Outputs 0..45 V 10L =·10mA
"
VOH Output High Voltage 00-0 7 3.6 3.8 V Vee = 4,.75V; 10H = -10p.A
All Other Outputs 2.4 V 10H = -1 mA
los Short Circuit Current, All Outputs 15 90 mA Vee = 5V
10 (off) Off State Output Current 100 p.A Vee = 5.25V; Vo = 5.25V
All Control Outputs -100 p.A Vo = 0.45V
liNT INTA Current 5 mA (See INTATestCircuit)
NOTE:
1. Typi9al values are for TA'= 25°e and nominal supply voltages.
16-56
8228
CAPACITANCE VSIAS = 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz
1. This parameter is periodically sampled and not 100% tested. .
Limits
Symbol Parameter Unit
Min Typ(1) Max
CIN Input Capacitance 8 12 pF
COUT Output Capacitance 7 15 pF
Control Signals
1/0 1/0 Capacitance 8 15 pF
(Dor DB)
A.C. CHARACTERISTICS TA = O°Cto + 70°C, Vee = 5V ±5%
Limits
Symbol Parameter Unit Conditions
Min Max
tpw Width of Status Strobe 22 ns
tss Setup Time, Status Inputs 00-07 8 ns
tSH Hold Time, Status Inputs 00-07 5 ns
toe Delay from STSTB to any Control Signal 20 60 ns CL = 100pF
tRR Delay from DBIN to Control Outputs 30 ns CL = 100pF
tRE Delay from DBIN to EnablelDisable 8080 Bus 45 ns CL = 25 pF
tRO Delay from System Bus to 8080 Bus during Read 30 ns CL = 25 pF
tWR Delay from WR to Control Outputs 5 45 ns CL = 100 pF
tWE Delay to Enable System Bus DBo-DB7 after STSTB 30 ns CL = 100 pF
two Delay from 8080 Bus 00-07 to System Bus 5 40 ns CL = 100 pF
DBo-DB7 during Write
tE Delay from System Bus Enable to System Bus DBo-DB7 30 ns CL - 100 pF
tHO HLDA to Read Status Outputs 25 ns
tos Setup Time, System Bus Inputs to HLDA 10 ns
tOH Hold Time, System Bus Inputs to HLDA 20 ns CL = 100 pF
AC TESTING LOAD CIRCUIT INTA Test Circuit (for RST 7)
.12Y
~Vcc
lKO:l:l0'lo
R,
~
i
DEVICE
UNDER
TEST
Cl
f
~
R,
8228
-=- -=
231465-3
For Do-~; Rl = 4 KO. R2 = 000, CL = 25 pF.
23
For all other outputs: Rl. = 5000, R2 = 1 KO, CL = 100 pF.
INTA 0--------'
231465-4
16-57
8228
WAVEFORMS
.,
·2----
"ST"'A"'TU"'S"'S"'T";R"'OB""E
-"'pw-
~
_DATA BUS X X
I~I-= -Is.ri
OBIN \.
INTA, lOR, iiiiiii
\
-l'RRj=-
IDC_ I~
INTA, lOR, MEMR
OURINGHLDA
HLDA
\
- ~
I_IHO
.I_lOS- _IO~ _____________
-------- --
SYSTEM BUS DURING READ
-------- I- ---~I~ ~~-------------
_ BUS DURING READ .-------- ~ - '~E -:P 1>- - - - - - - - - - - - - - -
\. J
lOW OR MEMW
'WR~ _1- -11-twR
'\ J
1010 BUS DURING WRITE --------- -
---------- -
SYSTEM BUS DURING WRITE
------~ -~ ,:1- t"IWOl
SYSTEM BUS ENABLE j d
SYSTEM BUS OUTPUTS - - - - - - - - - - - - - - ~I~ ~I:-=" --_-________ _
231465-5
VOLTAGE MEASUREMENT POINTS: Do-D7 (when outputs) LogiC "0" = O.BV, Logic "1" = 3.0V. All other signals mea-
sured at 1.5V.
·16-58
intJ 8755A
16,384-BIT EPROM WITH 110
• 2048 Words x 8 Bits
• 2 General. Purpose 8-Bit I/O Ports
• Single + 5V Power Supply (VcC> • Each I/O Port Line Individually
Programmable as Input or Output.
• Directly Compatible with 8085AH
•
• U.V. Erasable and Electrically
Reprogrammable
•
Multiplexed Address and Data Bus·
40-Pin DIP
• Internal Address Latch
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The Intel·8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the
8085AH microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with. no wait states in an 8085AH CPU. .
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and.each I/O port line
is individually programmable as input or output.
PROG ANOCE I vee
ClK~-----, PB 7
. . eE2
ClK PB6
RESET PBs
voo PB4
ADo-7
READY PB J
101M PB 2
G
As- IO lOR PB I
AD PBo
CE2
2K x 8 PA 7
EPROM lOW
101M
ALE PA 6
ALE
ADo PA5
RD
iOW
RESET
G ADI
AD2
AD J
PA 4
PA J
PA 2
lOR A0 4 PAl
AD5 PAo
PROGICE I t t. vee t+5vl AD6 A IO
v o o - - -.... ~Vsstovl AD7 Ag
231735-1 vss As
Figure 1. Block Diagram 231735-2
Figure 2. Pin Configuration
November 1986
16·59 Order Number: 231735·002
8755A
Table 1. Pin Description
Symbol Type Name and Function
ALE I AD!!RESS LATCH ENABLE: When Address latch Enable goes high, ADO-ZL
101M, AS-10, ~ and CE1 enter the address latches. The signals, (AD, 101M,
ADs-10, CE2, CE1) are latched in at the trailing edge of ALE.
ADo_7 I BIDIRECTIONAL ADDRESS/DATA BUS: The lower 8 bits of the PROM or I/O
address are applied to the bus lines when ALE is high.
Du.!!!:!.9 an 1/0 cycle, Port A or B is selected based on the latched value of ADo.
IF RD or lOR is low when the latched Chip Enables are active, the output
buffers present data on the bus.
ADS-10 I ADDRESS BUS: These are the high order bits of the PROM address. They do
not affect I/O operations.
PROG/CE1 .I CHIP ENABLE INPUTS: CE1 is active low and CE2 is active high. The 8755A
CE2 can be accessed only when both Chip Enables are active at the time the ALE
signal latches them up. If either Chip Enable input is not active, the ADo-7' and
READY ouputs will be in a high impedance state. CE1 is also used as a
programming pin. (See section on programming.)
101M I I/O MEMORY: If the latched 101M is high when RD is low, the output data
comes from an I/O port. If it is low the output data comes from the PROM.
RD I READ: If the latched Chip Enables are active when RD goes low, the ADo-7
output buffers are enabled and output either the selected PROM location or
I/O port. When both RD and lOR are high, the ADo_7 output buffers are 3-
stated.
lOW I I/O WRITE: If the latched Chip Enables are active, a Iowan lOW causes the
output port pointed to b~he latched value of ADo to be written with the data on
ADo-7. The state of 101M is ignored.
ClK I CLOCK: The ClK is used to force the READY into its high impedance state
after it has been forced low by CE1 low, CE2 high, and ALE high.
READY 0 READY is a 3-state output controlled by CE1, CE2, ALE and ClK. READY is
forced low when the Chip Enables are active during the time ALE is high, and
remains low until the rising edge of the next ClK. (See Figure 6c;)
PAO.7 I/O PORT A: These are general purpose I/O pins. Their inputloutput direction is
determined by the contents of Data Direction Register (DDR). Port A is
selected for write operations when the Chip Enables are active and lOW is low
and a 0 was previously latched from ~ AD1.
Read Operation is s~ected ~either lOR low and active Chip Enables and ADo
and AD1 low, or 101M high, RD low, active Chip Enables, and ADo and AD1
low.
PBO-7 I/O PORT B: The general purpose I/O port is identical to Port A except that it is
selected by a 1 latched from ADo and a 0 from AD1.
RESET I RESET: In normal operation, an input high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR register).
lOR I I/O READ: When the Chip Enables are active, a Iowan lOR will output the
selected I/O port onto the AD bus. lOR low performs the same function as the
combination of 101M high and RD low. When lOR is not used in a system, lOR
should be tied to Vee ("1 ").
Vee POWER: + 5V supply.
Vss GROUND: Reference.
Voo POWER SUPPLY:Voo is a programming voltage, and must be tied to Vee
when the 8755A is being read.
For programming, a high voltage is supplied with Voo =. 25V, typical. (See
section on programming.)
16-60
inter 8755A
FUNCTIONAL DESCRIPTION A port can be read out when the latched Chip En-
ables are active and either RD goes low with 101M
high, or lOR goes low. Both input and output mode
PROM Section bits of a selected port will appear on lines ADo-7.
The 8755A contains an 8-bit address latch which To clarify the function of the 1/0 Ports and Data Di-
allows it to interface directly to MCS@-48 and rection Registers, the following diagram shows the
MCS@-85 processors without additional hardware. configuration of one bit of PORT A and DDR A. The
same logic applies to PORT Band DDR B.
The PROM section of the chip is addressed by the
11-bit address and the Chip Enables. The address,
CEl and CE2 are latched into the address latches on 8755A ONE BIT OF PORT A AND DDR A
the falling edge of ALE. If the latched Chip Enables
are active and 101M is low when RD goes low, the
contents of the. PROM location addressed by the
latched address are put out on the ADo-7 lines (pro-
vided that Voo is tied to Vecl.
I/O Section ...
~
The 1/0 section of tne chip is addressed by the ffi
! RESET
latched value of ADo-1. Two 8-bit Data Direction
Registers (DDR) in 8755A determine the input/out-
put status of each pin in the corresponding ports. A Do
"0" in a particular bit position of a DDR signifies that ~
the corresponding 110 port bit is in the input mode. A AEADPA
"1" in a particular bit position signifies that the corre- 231735-3
WRITE PA = (lOW = 0) • (CHIP ENABLES ACTIVE) • (PORT A
sponding 1/0 port bit is in the output mode. In this ADDRESS SELECTED)
manner the 1/0 ports of the 8755A are bit-by-bit pro- WRITE DDR A = (lOW = 0) • (CHIP ENABLES ACTIVE) • (DDR
grammable as inputs or outputs. The table summa- A ADDRESS SELECTED)
READ PA = ((101M = 1) • (RD = 0) + (lOR = 0)1 • (CHIP
rizes port and DDR designation. DDR'scannot be ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)
read.
NOTE:
Write PA is not qualified by IOlM.
ADl ADo Selection
0 0 PortA
Note that hardware RESET or writing a zero to the
0 1 PortB
DDR latch will cause the output latch's output buffer
1 0 Port A Data Direction Registe((DDR A) to be disabled, preventing the data in the Output
1 1 Port B Data Direction Register (DDR B) Latch from being passed through to the pin. This is
equivalent to putting the port in the input mode. Note
When lOW goes low and the Chip Enables are ac- also that the data can be written to the Output Latch
tive, the data on the ADo-7 is written into 1/0 port even though the Output Buffer has been disabled.
selected by the latched value of ADo_1. During this This enables a port to be initialized with. a value prior
operation all 1/0 bits of the selected port are affect- to enabling the output.
ed, regardless of their 1/0 mode and the state of 10/
M. The actual output level does not change until The diagram also shows that the contents of PORT
lOW returns high. (Glitch free output.) A and PORT B car be read even when the ports are
configured as outputs.
16-61
inter 8755A
ERASURE CHARACTERISTICS SYSTEM APPLICATIONS
The erasure characteristics cif the 8755A.are such
that erasure begins to occur when exposed to light System Interface with 8085AH
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and A system using the 8755A can use either one of the
certain types of fluorescent lamps have wavelengths two I/O Interface techniques:
in the 3000-4000A range. Data show that constant • Standard I/O
exposure to room level fluorescent. lighting could • Memory Mapped I/O
erase the typical 8755A in approximately 3 years
while it would take approximately 1 week to cause If a standard I/O technique is·used, the system can
erasure when exp·osed to direct sunlight. If the use the feature of both CE2 and CE1. By using a
8755A is to be exposed to these types of lighting combination of unused address lines All :"15 and the
conditions for extended periods of time, opaque la- Chip Enable inputs, the 8085AH system can use up
bels are available from Intel which should be placed to 5 8755A's without requiring a CE decoder. See
over the 8755A window to prevert unintentional era-. Figure 4. ' ,
sure.
If a memory mapped I/O approach is used the
The recommended erasure procedure for the 8755A, 8755A will be selected by the combination of both
is exposure to shortwave ultraviolet light which has a the Chip Enables and 101M using ADs-15 address
wavelength of 2537 Angstroms (A). The integrated lines. See Figure 3. .
dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2. The erasure
time with this dosage is approximately 15 to 20 min- ~
utes using an ultraviolet lamp with a 12000 /J-W/cm 2 A
power rating. The 8755A should be placed within
one inch from the lamp tubes during erasure. Some ~
A":'15
~
"-
lamps have a filter on their tubes and this filter '.
.~
8085AH
should be removed before erasure.
~LE "
AD t-
t--
WIi
PROGRAMMING eLK (~2)
t-
READY t-
Initially, and after each erasure, all bits. of the t-
1011.1
t- f
EPROM portions of the 8755A are in the "1" state.
Information is introduced by selectively program- J~ 7 , 7 I
ming "0" into the desired bit locations. A pro- AlD._I AI-II RD' eLK 101M
grammed "O"canonly be changed to a "1" by UV iiITI ALE mil READY CE
erasure. 8155A
The 8755A can be programmed on the Intel Univer- 231735-4
sal Programmer (iUP), and iUPF8744A programming
module. Figure 3. 8755A in 8085AHSystem
(Memory-Mapped 1/0)
The program mode itself consists of programming a
single address at a time, giving a single 50 msec
pulse for every address. Generally, it is desirable to
have a verify cycle after a program cycle for the
same address as shown in the attached timing dia"
gram. In the verify cycle (I.e., normal memory
read cycle) 'Voo' should be at + 5V.
16-62
l
....,
...
. An ..... A" A .. A,.
"-
)
::!! AIDD-7
fa
...
C .-- - r'- r- -
CD "
~ .... AN
ALE
I-- - I-- I- -
AD
CO I- - l- e- -
...... Wii
(/I
(/I
I-- - I-- I- -
~
CLKI.21
I- - l- e- -
3' READY
- - I-- 1-- -
CO
«:I
101M
- - I-- I- -
.... CO
(/I co
~
0)
c.J
~
::E:
en
""
en
en
J>
1
CD
3
,
-...
Cil
I II
:;,
a.
III
";, 7' 7
I,-AIDO-'
10'
......
.755A
.0 elK
12K BYTES)
10""
AU iii READY fE,
II
";,
iiii AIDO-' A
.." AUiIliiDIelKREADY
.755A
12K BYTESI
10111tE,
";"
'11iiDii
7
AID..,
1755A
12K BYTES)
i'
AO-" AU:'0iiielKREADY10"tE,'11iiiiii
7
AID.,
7
8755A
12K BYTESI
l'
AO-" ALEiIlimweLKREADY.. IIICI,'11iiiii AID..,
" 7
A." AU.0illilelKREADY,alii,
8155A
12K BYTESI
CE,
I
a.
:::: 231735-6
.9 NOTE:
Use CEl for the first 8755A in the system, and CE2 for the other 8755.A's. Permits up to5-8755A's in a system without CE decoder.
8755A
ABSOLUTE MAXIMUM RATINGS* • Notice.' Stresses above those listed under "Abso-
lute Maximum Ratings" may cause permanent dam-
Temperature Under Bias ........ ,', , , O·C to + 70·C age to the device. This is a stress rating only and
Storage Temperature " " " " " - 65·C to + 150·C functional operaiion of the device at these or any
other conditions above those indicated in the opera-
Voltage on any Pin
tional sections of this specification is not implied Ex-
with Respect to Ground, , , , , , , , , , - O,5V to + 7V . ,
posure to absolute maximum rating conditions for
Power Dissipation, , , , , , , , , , , , , , , , , , , , , , , , , , 1,5W . extended periods may affect device reliability.
D.C. CHARACTERISTICS.
TA = o·c to 70·C, Vee = voo =5V ±5%
Symbol Parameter Min Max Unit ' Test Conditions
VIL Input Low Voltage -0,5 0,8 V Vee = 5,OV
VIH Input High Voltage 2,0 Vee + 0,5 V Vee = 5,OV
VOL Output Low Voltage 0.45 V IOL = 2mA
VOH Output High Voltage 2.4 V IOH = - 400 /LA
IlL Input Leakage 10 /LA Vss ::;: VIN ::;: Vee
ILO Output Leakage Current ±10 /LA O,45V::;: Vour::;: Vee
lee Vee Supply Current 180 rnA
100 Voo Supply Current, 30 rnA Voo = Vee
CIN Capacitance of Input Buffer 10 ...
pF fc = 1 /LHz
CliO Capacitance of 1/0 Buffer 15 pF fe = 1/LHz
D.C. CHARACTERISTICS-PROGRAMMING
T A = o·C to 70·C, Vee = 5V ± 5%, Vss = OV, Voo = 25V ± 1V
Symbol Parameter Min Typ Max Unit
Voo Programining Voltage (during Write to EPROM) , 24 25 26 V
100 Prog Supply Current 15 30 rnA
16-64
8755A
A.C. CHARACTERISTICS
TA = O·C to 70·C. vcc = 5V ±5%
8755A
Symbol Parameter Unit
Min Max
tCYC Clock Cycle Time 320 ns
T1 CLK Pulse Width 80 ns
T2 CLK Pulse Width 120 ns
tf. tr CLK Rise and Fall Time 30 ns
tAL Address to Latch Set Up Time 50 ns
tLA Address Hold Time after Latch 80 ·ns
tlC Latch to READ/WRITE Control 100 ns
tRD Valid Data Out Delay from READ Control' 170 ns
tAD Address Stable to Data Out Valid" 450 ns
tll Latch Enable Width 100 ns
tRDF Data Bus Float after READ 0 100 ns
tCl READ/WRITE Control to Latch Enahle 20 ns
tcc READ/WRITE Control Width 250 ns
tDW Data in Write Set Up Time 150 ns
tWD Data in Hold Time after WRITE 30 ns
twp WRITE to Port Output 400 ns
tpR Port Input Set Up Time 50 ns
tRP Port Input Hold Time to Control 50 ns
tRYH READY HOLD Time to Control 0 160 ns
tARY ADDRESS (CE) to READY 160 ns
tRV Recovery Time between Controls 300 ns
ti=lDE READ Control to Data Bus Enable 10 ns
NOTES:
CLOAD = 150 pF.
'Or TAD - (TAL + T Lcl, whichever is greater.
"Defines ALE to Data Out Valid in conjunction with TAL.
A.C. CHARACTERISTICS-PROGRAMMING
TA = O·C to 70·C, Vcc = 5V ±5%. Vss = OV. VDO = 25V ±1V
Symbol Parameter Min Typ Max Unit
tps Data Setup Time 10 ns
tpD Data Hold Time 0 ns
ts Prog Pulse Setup Time 2 fLs
tH Prog Pulse Hold Time 2 fLs
tpR Prog Pulse Rise Time 0.01 2 p.s
tPF Prog Pulse Fall Time 0.01 2 p.s
tpRG Prog Pulse Width 45 50 ·ms
16·65
8755A
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
"=X )C
DEVICE
.. >
0.45
2.0
0.'
.
TEST POINTS ~
2.0
0.'
UNDER
TEST
ICL.1SOP F
231735-7
A.C. Testing: Inpuls are driven a12.4V for a Logic "1" and 0.45V 231735-8
CL=150pF
for a Logic "0". Timing Measurements are made al 2.0V for a
CL Includes Jig Capacitance
Logic "1" and 0.8V for a Logic "0".
WAVEFORMS
CLOCK SPECIFICATION FOR 8755A
231735-9
PROM READ, I/O READ AND WRITE
Aa·10 ADDRESS
101M
ADO·1
'------,....,}-
ALE
CE,
--t----·ow
231735-10
Please note that eEl must remain low for the entire cycle.
16-66
intJ 8755A
WAVEFORMS (Continued)
1/0 PORT
~OR )~ __________ -J~
"''' ---,J ~ '.. ~-f-rIR_P_______
INPUT ~ X. .______
DATA· - - - - - - - )(
BUS
------- ~------------------ 231735-11
A. Input Mode
\ {
PORT
OUTPUT
--- - ----------'::~XO"""'
------------
GLITCH FREE
V
DATA" -
BUS
-
____ _
- - -
..A_________ X".____
..J
231735-12
B. Output' Mode .
WAIT STATE (READY = 0)
231735-13
16-67
8755A
WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION
I. .~----- PAOGRAM CYCLE - - - - - -...rl........- - - V E R I F V CYCLE" ------1_ PROGRAM CYCLE
ALE
DATA TO BE
A/DO·7
PROGRAMMED
IpO
A8·10
CEa
Ips
+25
VOO
+5------------------------(
231735-14
·Verify cycle is a regular Memory Read Cycle (with Voo = +5V for 8755A),
16-68
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Bacher Electronics GmbH Vertrlebs-AG
=~~b='~k
Rotenmuehlgasse 26 12
1120Wlen " 82 20092 Clnlsello BalSamo
Ri:(~~S 84 60 Milano
10
~~!:~:ee68
~~~~~0012
ITT MultikOmponent GmbH Bytech Comway Ltd.
BELGIUM
Bahnhofstrasse 44 NETHERLANDS Unll2 The Western Centre
lnelca Belgium S.A.
Av. des Croix de Guane 94
7,., Mm"lI""
m~~~~9879
Western Road
~=e:~~r1man
B
1120 Bruxelles Ba lRW
~~~~180180 2621 AP Delft 2211
DENMARK
Jermyn GmbH
1m Oachsstueck
8250 UmbU,%.,
9 ~~~~~~O 99 06
Jermyn
Vestry Estate
m~~~~~-o
NORWAY
80 Otford Road
Nordisk Elektronik AIS Sevenoaks
Metrologle GmbH P,O. Box 122 kent TNt. SEU
Smedsvingen ..
~j~:,::~:~~~9 1384 Hvalstad ~:(~~~J24S 0144
FINlAND
Tel: (089118 04 20
TLX: 5213189 ~~~ttrtO Rapid Silicon
RaPJd House
OYAntronlcAB Proelectron Vertflebs GmbH PORTUGAL DenmarlcSt.
Max Planck Sirasse 1-3
=~~~~
Melkonkatu 24A
00210 Helsmkl21 6072 Oreleich Ollram
~M)2~~:022 m~~V9~ 30 43 43 Av. M. Bombard., 133-1 0
1000 Usboa
Tel: (II 54 5313
m!m3f 2268
FIIANC! IRELAND TLX: 14182 Rapid,Systems
Rapid House
~:Oag=~" Park
SPAIN Denmark St.
.
A10 Electronica S.A. ~~:"~~~R
g:~~~I~ Plaza Cludad de Viana no. 6
mf~Ja~0244
~~:(y,~6288 28040 Madrid
~~~~2~~ 40 00 YUGOSLAVIA
ISRAt!L
ITT-SESA H.R. MICroelectronics Corp.
Eastronles Ltd. i~1oMr!fa,:~:ngel no. 21·3 2005 de II Cruz Blvd., Ste. 223 •
11 Rozenis Street Santa Clara, CA 95050
P.O. Box 39300
~~~~7~~ 09 51 U.S.A.
Te! Aviv 81392
~~~~~SI51
~~!~4~f0286
SWEDEN
'TALV Nordlsk ElektrOnlk A,9.
~~~g:,~~1
11127 SoIna
Tel, (6) 734 97 70
d.. _ TLX: 10547
Clrle-Vemet ~ BP 2 SWITZERLAND
0_
.~~:1535
INTERNATIONAL SALES OFFICES
AUSTRALIA JAPAN JAPAN (Conl'd) KOREA
Inlel Australia Pty. Ltd: Intel Technology Asia ltd.
Wi~~~~~:i.~·~isu9i Bldg.
S&ri!rum Bulldin'l
~:~~it~w, ~:~6 1-2-1 Asahl-machi ~~~y~:~SJ~~~~~o~~~eUngpo-ku
~:,~t:~~~.37~awa 243 Seoul 150
~~t~ti~~-2744 FAX: 0462-29-3781
Tel: (2) 784-8186
TLX: 29312INTELKO
FAX: (2) 923-263~ FAX: (2) 784-8096
~!~~~f~~~~9~~ld9.
Inlel Japan K.K.·
BRAZIL Ayokuchl-Eki Bldg. SINGAPORE
1-8989 Fuchu-cho 2-4-1 Terauchi
Intel Semlcondutores do Brasil LTD"
f~Fri4;~:l~1183 Tor:onaka-shi, Osaka 560
~nJ~I~6~s':~~~;~f~ Ltd.
~~x~~J-:~~g:l
Av. Paulista. 1159-CJS 404/405
01311 -Sao Paulo - S,P. FAX: 0423-60-0315 Goldhlrr Squara
~~~f2ro.78\~30
Tal: 55-11-287-5899
TLX: 1153146 Intel Japan K,K.· Intel Japan K.K.
FAX: 55·11-212·7631 Aower-HIII Shin-mach! Bldg. Shinmaru Bldg. TLX: 39921 INTEL
1-23-9Shinmachi 1-5-1 Marunouchl FAX: 250-9256
CHINA ~:~a~~~~~~kYO 154 ¥~l:Ygg.~f:3~~~YO 100 TAIWAN
FAX: 03-427-7620 FAX: 03-201-6850
Intel Japan K.K:
~':~iw:r. K.K.
:~B·.ro~~c~:ya 1-16-30 ~eieki Minami
~:&f:l~2:~8~fltama 360 ~~~~5~a-ku, Nagoya-shl
FAX: 0485-24-7518 Tel: 052-561-5181
HOHGKONG FAX: 052-561-5317
Intel Semiconductor Ltd.· ~~e~~~G~~~i~:saShl_koSU91 Bldg.
1701-3 Connaught Centre 915 Shinmaruko, Nakahara-ku
n u htRoad
1
T 555 ~~=~t:;!7~:ragawa 211
TWX: ISLHK HX FAX: 044--733-7010
FAX: 589
INTERNATIONAL
DISTRIBUTORS/REPRESENTATIVES
ARGENnNA CHINA IConl'd) JAPAN ICont'd) NEW ZEALAND
DAFSYSS.R.L. Schmidt & Co. Ltd. Dia Semlcon Systems, Inc. Northrup Instruments & Systems Ltd.
Chacabuco, 90-4 PISO Wacore 64, 1·37-8 Sa~enjaya
~~g.~~~NRe':~arket
18/F Great Eagle Centre
t069-Buenos Aires 23 Harbour Road
~:a~a8~~~~kyo 1 Auckland 1
·~r~~~5~~~
Tel: 54-1-334-1871
54-1-34-7726 FAX: 03-487-8088 Tel: 64-9-501-219, 501-801
TLX: 25472 . TWX: 74766 SCHMC HX TLX: 21570 THERMAL
FAX: 852-5-891-8754 'Okaya Koki
2-4-18 Sakae
INDIA
~:I~~~~:2~~:I:;Shi 460
Micronic Devices FAX: 052-204-2901
~~"Jcr.t.&~Road Ryoyo EJecl:ro Corp.
Basavanagudl Konwa Bldg.
'::~~I:r2~~'
AUSTRAUA 1-12-22 Tsukiji SINGAPORE
Total Electronics TLX:. 0845-8332 MD BG IN re'1~~'54~Jf,'04 Francotone Electronics Pte Ltd.
P.M.B.250 FAX: 03-546-5044 17 Harvey Road #1)4..01
~~1~:~81~89-1618
9 Harker Street Micronic Devices
Burwood, Victoria 3125 403, Gagan Deep KOREA
Tal: 81-3-288-4044 12, Rajeildra Place TWX: 56541 FRELS
TLX: AA 31261 New Delhi 110008 FAX: 2895327
Tel: 91-58-97-71
Total EJectronles TLX: 03163235 MONO IN SOUTH AFRICA
P.O. Box 139
Artamon, N.S,W. 2064 Mlcronic DeviCes ~~~~~c':~ding Elements, Ply. Ltd.
Tel: 61-02-438-1855 No. 516 5th Roor
TLX: 26297 Swastlk Chambers Pine Square, 18th Street
BRAZIL g~~b~h='irl,Road Hazelwood, Pretoria 0001
Tel: 27-12-469921
Tet, 91.~2-39-63 Samsung Semiconductor & TLX: 3-227786 SA
8ebra Microelectronlca TLX: 9531 171447 MDEV IN Telecommunications Co., Ltd.
R. Geraido Ftaustno Gomes, 78 150, 2-KA, Tafpyung-ro, Chung-ku TAIWAN
SAndat JAPAN Seoul 100
04575 - Sao Paulo - S.P. Tel: 82-2-751-3987 Mltac Corporation
Tel: 55-11-534-9522
TLX: 1154591 or 1154593BR
Asahi Electronics Co. Ltd.
KMM Bldg. 2-14-1 Asano
TLX: 27970 KORSST
FAX: 82-2-753-0967
~~P;~5R.~~'l? Shen East Rd.
FAX: 55-11-534-9637 Kokurakftl.-ku Tel: 886-2-501-8231
~~~~~~;~~~~2
MEXICO· FAX: 886-2-501-4265
CHILE
FAX: "093-551-7861, Dicopei S.A. VENEZUELA
DIN Instruments Tochtli 368 Frace. Ind. San Antonio
C. Itoh Techno-Science Co., Ltd. P. Benavides S.A.
~~~:=~eXico,
Suecia2323
CesUIa 6055, Correa 22 C. Itch B~, 2-5-1 Klta-Aoyama D.F. Avllanes a Rio
~~~.22"8139
ResldenCia Kamarata
¥~~~~7-4~ 107 Tel: 52-5-561-3211
TLX: 1773790 DICOME Locales 4 AL 7
TL.X: 440422 RUDY CZ FAX: 03-497-4969 La Candelaria, Caracas
Tel: 58-2-571-0396
ell.. TL.X: 28450
FAX: 58-2-572-3321
Novel Precision Machin~ Co., ltd.
~:!~ ~.O~'~:!fw~n:iree~g.
N.T., Kowloon
~:'i~"'3-222
TWX: 39114 JINMI HX
FAX: 8524261..&02
"Field Application location
inter DOMESTIC SERVICE OFFICES.
ALABAMA CONNECTICUT MICHIGAN PINNSYLVANIA
Intel Corp. Intel Corp.
1071 Orchard Lake Road 201 Penn Center Boul....ard
Suite tOO Suite 301 W
West Bloomfield 48033
Tol: (3'3) 851-11905 ~~h3w.f:.o
ARIZONA
=
FLORIDA MJSSOURI TEXAS
InteICcrp.
11225 N. 28th Dr., #0214 IntslCorp. Intel Corp.
Phoenix 85029 ~~ CJty Expressway 313 E. Anderlon Lane
Tel: (602) 869"980 Suite 314
~:"(3~~~'5
AusUn78762
~J~Jf~~C,
InlelC
6OOE.
~: ~~atmonte DrIve
SlerraVllt1 HEW JERSEY
Tel: (602)4
SUite 105
ARKANSAS
~($~rsr8=32714
~.~g:!206 GEORGIA
Ulm 72170
Tel: (501) 2414264
~,~ ~rrnte Parkway ~:ita~~iZalll
InltICorp.
CAUFORNIA Sulle200 Rarllan Centsr =~~n:t\4 Suite 225
Norcross 30092 Edison 08817 rei: (9'5) 75'.0'88
Tel: (404) 44H171 Tel: (20') 225-3000
YrRGINIA
fLUNQrs NORTH CAROLINA
Intel Corp.
m:8's~~~eadowvlew Road 1603 Sanla Rosa Rd .• #109
Richmond 23288
Tel: (804) 282-5668
=~perial Highway
Suite 206
Greensboro 27407
SUite 218 Tel: (9'9) 294-'54' WASHINGTON
~~:=a INOIANA Inlel Corp.
Intel Corp. Intel Corp. ~~~ ~~~d., Suite 102
~:o~:a~r5~'
8777 Purdue Rd., #'25 Tel: (B'9) 781-11022
Tel: (918) 351-8143 ~":.(a~W~~::\ OHIO
=~IhStreet
KANSAS WISCONSIN
te~~~'1Oth Street
SlIIte110 InlelCorp.
Santa Ana 92705 330 S. EXecutive Dr.
~J~~~~4~
Suite 170 SUI\e'02
Overland Park 66210 Brookfield 53005
Tel: (913) 345-2727 Tel: (414) 714-8087
Intel Corp.
'~':aS&'!r~or~pcpressway KENTUCKY Intel Corp.
8500 Poe CANADA
~:rr,:r:~
Tel: (408) 970-1740
~,=';a'P'
OREGON Rexdale
Canada
MARYLAND Tel: (41
COLORADO
Intel Corp.
5th Floor - :;:~orlein Blvd. .
7833 Walker Drive PoInte Qalre, Quebec
canada H9R 3K3
:mg1~/iiCherry Greenbeft 20nO
Tal: (301) 441-1020 Tel: (5'4) 894-9'30
Sulte91S
Denver 80222 IIASSACHUSErrB Intel Corp.
2850 0u88l'lsvtew DrIve. #250
~~~~~~';= Ottawa. Ontario,
==corp.Center
3 carlllle Road
canada K2B 8H8
Tel: (8'3) 929-9?'4
Westford 01886
Tel: (817) 692·1060
CUSTOMER TRAINING CENTERS
CALifORNIA ILliNOIS MASSACHUSEns MARYLAND
2700 San Tomas Expressway 7833 Walker Dr•• 4th Floor
~:Um~~~~~:300
3 Carlisle Road
Santa Clara 95051 Westford 01886 Greenbelt2f1770
Tel: (408) 970-1700 Tel: (3'2) 3'1'0-5700 Tel:(617)692-1~ Tel: (30') 220-3380
SYSTEMS ENGINEERING OFFICES
CAUFORNIA ILUNQIS MASSACHUSETTS NEW YORK
2700 San Tomas Expressway 3 Carlisi. Road 300 Motor Parkway
~:imM~~ln~~#300
~:r\fi'~;31~30
Sanla Ctara 95051 ' Westford 01886
Tel: (408) _8086 Tel: (3'2) 3¥0-B03' Tel: (617) 692-3222
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