PAMANTASAN NG CABUYAO

COLLEGE OF COMPUTING AND ENGINEERING

COURSE CODE: CPP 110

COURSE DESCRIPTION: INTRODUCTION TO HDL

COURSE INTENDED On the completion of the course, student is expected to be able to do the
LEARNING OUTCOMES: following:

1. The ability to code and simulate any digital function in HDL.

2. Understand library modeling, behavioral code and the differences
between them.
3. Understand the differences between simulator algorithms as well
as Logic verification using HDL software tool
4. Learn good coding techniques per current industrial practices

LEARNING MATERIAL FOR 7

WEEK NUMBER:

I. TITLE: Blocking and Condition Statements

II. OBJECTIVES: By the end of this module you should be able to:

1. Understand the purpose of Blocking and Non-Blocking

assignments
2. Able to understand the purpose of condition statements in Verilog
3. Solve problems using condition statements in the synthetic
approach

III. INTRODUCTION:
The purpose of this module is to understand the reasons behind the
guidelines, one needs to have a full understanding of the functionality and
scheduling of Verilog blocking and nonblocking assignments.

IV. CONTENTS:

Lesson Coverage:

- Blocking and Condition Statements

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INTRODUCTION

Two well-known Verilog coding guidelines for modeling logic are:

Guideline: Use blocking assignments in always blocks that are written to generate combinational logic.
Guideline: Use nonblocking assignments in always blocks that are written to generate sequential logic.

A Verilog race condition occurs when two or more statements that are scheduled to execute in the same simulation
time-step, would give different results when the order of statement execution is changed, as permitted by the
IEEE Verilog Standard. To avoid race conditions, it is important to understand the scheduling of Verilog blocking
and nonblocking assignments.

Blocking assignments

The blocking assignment operator is an equal sign ("="). A blocking assignment gets its name because a blocking
assignment must evaluate the RHS arguments and complete the assignment without interruption from any other
Verilog statement. The assignment is said to "block" other assignments until the current assignment has
completed. The one exception is a blocking assignment with timing delays on the RHS of the blocking operator,
which is considered to be a poor coding style.

Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression)
of the blocking assignment without interruption from any other Verilog statement.

A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the
current assignment has been completed.

A problem with blocking assignments occurs when the RHS variable of one assignment in one procedural block
is also the LHS variable of another assignment in another procedural block and both equations are scheduled to
execute in the same simulation time step, such as on the same clock edge. If blocking assignments are not properly
ordered, a race condition can occur. When blocking assignments are scheduled to execute in the same time step,
the order execution is unknown.

To illustrate this point, look at the Verilog code in Example 1.

module fbosc1 (y1, y2, clk, rst);

output y1, y2;
input clk, rst;
reg y1, y2;

always @(posedge clk or posedge rst)

if (rst) y1 = 0; // reset
else y1 = y2;

always @(posedge clk or posedge rst)

if (rst) y2 = 1; // preset
else y2 = y1;
endmodule

According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. If the first always
block executes first after a reset, both y1 and y2 will take on the value of 1. If the second always block executes
first after a reset, both y1 and y2 will take on the value 0. This clearly represents a Verilog race condition.

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Nonblocking assignments

The nonblocking assignment operator is the same as the less-than-or-equal-to operator ("<="). A nonblocking
assignment gets its name because the assignment evaluates the RHS expression of a nonblocking statement at the
beginning of a time step and schedules the LHS update to take place at the end of the time step. Between
evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated
and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS
updates scheduled.

The nonblocking assignment does not block other Verilog statements from being evaluated.

Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

Nonblocking assignments are only made to register data types and are therefore only permitted inside of
procedural blocks, such as initial blocks and always blocks. Nonblocking assignments are not permitted in
continuous assignments.

To illustrate this point, look at the Verilog code in Example 2.

module fbosc2 (y1, y2, clk, rst);

output y1, y2;
input clk, rst;
reg y1, y2;

always @(posedge clk or posedge rst)

if (rst) y1 <= 0; // reset
else y1 <= y2;

always @(posedge clk or posedge rst)

if (rst) y2 <= 1; // preset
else y2 <= y1;
endmodule

Again, according to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. No matter
which always block starts first after a reset, both nonblocking RHS expressions will be evaluated at the beginning
of the time step and then both nonblocking LHS variables will be updated at the end of the same time step. From
a users perspective, the execution of these two nonblocking statements happen in parallel.

Verilog coding guidelines

Before giving further explanation and examples of both blocking and nonblocking assignments, it would be useful
to outline eight guidelines that help to accurately simulate hardware, modeled using Verilog. Adherence to these
guidelines will also remove 90-100% of the Verilog race conditions encountered by most Verilog designers.

Guideline #1: When modeling sequential logic, use nonblocking assignments.

Guideline #2: When modeling latches, use nonblocking assignments.

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Guideline #3: When modeling combinational logic with an always block, use blocking assignments.

Guideline #4: When modeling both sequential and combinational logic within the same always block, use
nonblocking assignments.

Guideline #5: Do not mix blocking and nonblocking assignments in the same always block.

Guideline #6: Do not make assignments to the same variable from more than one always block.

Guideline #7: Use $strobe to display values that have been assigned using nonblocking assignments.

Guideline #8: Do not make assignments using #0 delays.

Designers new to Verilog are encouraged to memorize and use these guidelines until their underlying functionality
is fully understood.

Self-triggering always blocks

In general, a Verilog always block cannot trigger itself. Consider the oscillator example in Example 3. This
oscillator uses blocking assignments. Blocking assignments evaluate their RHS expression and update their LHS
value without interruption.

The blocking assignment must complete before the @(clk) edge-trigger event can be scheduled. By the time the
trigger event has been scheduled, the blocking clk assignment has completed; therefore, there is no trigger
event from within the always block to trigger the @(clk) trigger.

module osc1 (clk);

output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;
endmodule

In contrast, the oscillator in Example 4 uses nonblocking assignments. After the first @(clk) trigger, the RHS
expression of the nonblocking assignment is evaluated and the LHS value scheduled into the nonblocking assign
updates event queue.

Before the nonblocking assign updates event queue is "activated," the @(clk) trigger statement is encountered
and the always block again becomes sensitive to changes on the clk signal. When the nonblocking LHS value is
updated later in the same time step, the @(clk) is again triggered. The osc2 example is selftriggering (which is
not necessarily a recommended coding style).

module osc2 (clk);

output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk <= ~clk;
endmodule

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Condition Statements

Condition statements are important since you have learned programming, it evaluates and gives primary solutions
as written by the developer.

The Conditional Statement if-else

The if - else statement controls the execution of other statements. In programming language like c, if - else controls
the flow of program. When more than one statement needs to be executed for an if condition, then we need to use
begin and end.

Syntax : if

if (condition)
statements;

Syntax : if-else

if (condition)
statements;
else
statements;

Syntax : nested if-else-if

if (condition)
statements;
else if (condition)
statements;
................
................
else
statements;

if-else Statements

if statements allows the tool to decide a statement is to be executed or not, depending on the conditions specified.
General syntax is as follows:

if( condition )
statement;

If the condition or conditional expression is true, then statement will be executed, otherwise not.

Consider the example

if( hold == 0 )
counter = counter + 1;

If reset is not zero, counter will be incremented.

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else statement can be used with if optionally. If condition specified in if statement is false, statement after else
will be executed. See this example, if reset is nonzero counter will become zero, othewise it will be incremented.

if( reset )
counter = 0;
else
counter = counter + 1;

If there are more than one statements within an if block, we can combine them using begin -- end. We can also
nest if-else statements as in these examples.

if( reset )
begin
counter <= 0;
over_flow <= 0;
end
else if ( counter == 15 )
begin
counter <= 0;
over_flow <= 1;
end
else
begin
counter <= counter + 1;
over_flow <= 0;
end

if-else statements should be used inside initial or always blocks. Generally if-else statements generates
multiplexers while synthesizing.

Variable declaration

It is a fundamental rule of the Verilog HDL that any object that is assigned a value in an always statement must
be declared as a variable. Hence,

reg f; // must be declared before it is used in a statement

The term variable was introduced in the verilog-2001 standard. Previously, the term used was register. This was
confusing, because a Verilog variable (register) does not necessarily imply that a hardware register would be
synthesized, hence the change of terminology.

If statement

The if statement in Verilog is a sequential statement that conditionally executes other sequential statements,
depending upon the value of some condition. An if statement may optionally contain an else part, executed if the
condition is false.

Although the else part is optional, for the time being, we will code up if statements with a corresponding else
rather than simple if statements. In order to have more than one sequential statement executed in an if statement,
multiple statements are bracketed together using the begin..end keywords,

reg f, g; // a new reg variable, g

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always @(sel or a or b)
begin
if (sel == 1)
begin
f = a;
g = ~a;
end
else
begin
f = b;
g = a & b;
end
end

If statements can be nested if you have more complex behavior to describe:

reg f, g;
always @(sel or sel_2 or a or b)
if (sel == 1)
begin
f = a;
if (sel_2 == 1)
g = ~a;
else
g = ~b;
end
else
begin
f = b;
if (sel_2 == 1)
g = a & b;
else
g = a | b;
end

Notice that the code is beginning to look a little bit confusing! In the code above, begin..end blocks have only
been used where they must be used, that is, where we have multiple statements. It is probably a good idea to use
begin..end blocks throughout your Verilog code - you end up typing in a bit more Verilog but it's easier to read.
Also, if you have to add more functionality to an always block later on (more sequential statement), at least the
begin..end block is already in place. So,

reg f, g, h; // yes, an extra reg variable, h

always @(sel or sel_2 or a or b)
begin
if (sel == 1)
begin
f = a;
if (sel_2 == 1)
begin
h = ~b;
g = ~a;
end
else
begin
g = a | b;

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h = a & b;
end
end
else
begin
if (sel_2 == 1)
begin
g = a & b;
h = ~(a & b);
end
else
begin
h = ~(a | b);
g = a | b;
end
f = b; // here's f!
end
end
Note that the order of assignments to f, g and h has been played around with

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V. REFERENCES: Roth, C.H. Jr. And John, L. K. (2018). Digital Systems Design Using VHDL (3rd
ed.). Texas, USA: Cengage Unlimited

Brown, S. and Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL

Design. (3rd ed.). New York, NY: McGraw-Hill

Online Readings and Guide

Hardware Description Language | VLSI Tutorial | Mepits

VHDL || Electronics Tutorial (electronics-tutorial.net)

Index of /ece232/pdf (umass.edu)

VI. ASSESSMENT TASK:

See Attached file given by the instructor

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