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5 5 4110 a 1 2
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( n )
 from the numbered blocks in main memorv to the block frames in the cache. Draw all
lines showing the mappings as clearly as
i) Showthe direct mapping and the addresspossible.
bits that identify the tag field, the block
number, and the word number.
ii) Show the fully associative mapping and the address bits that identify the tag field
and the word number.
ii) Show the two-way set-associative mapping and the address bits that identity the tag
field, the set number, and the word number.
b With a neat diagram discuss the specifications of a typical Backplane bus. 8 Marks
OR
Q6
a Consider the five-stage pipelined processor specified by the following reservation 12 Marks
Table 6(a); (2X 6=12)
i) List the set of forbidden latencies and the collision vector.
ii)Draw a state transition diagram showing all possible initial sequences (cycles)
without causing a collision in the pipeline.
i) List all the simple cycles and greedy cycles from the state diagram
iv) What is the minimum average latency (MAL) and constant cycle of this pipeline?
v) What will be the maximum throughput of this pipeline?
vi) What willbe the throughput if the minimum constant cycle is used?
b An instruction pipeline consists of 4 stages - Fetch (F), Decode field (D). Execute (E) 8 Marks
and Result Write (W). The 5 instructions in a certain instruction sequence need these
stages for the different number of clock cycles as shown by the Table 6(b) below;
Draw the pipeline details and find the number of clock cycles needed to perform the 5
instructions.
No. of clock cycies needed for

2 3 Instruction F D
4 6

1 1

2 1
X
S3 X 3 1 3 2
1

S4 4

S X 5 2

Table 6(a) Table 6(b)

Unit -IV
Q7
12 Marks
a Consider adual-processor (Pi and P2) system using write-back private caches and a
shared memory, all connected io coTMOn contention bus. Each cache has four block (6X2=12)
frames label below as 0, 1,2, 3.
Prcces sor 2
Erocessr 1

Cache

Bus

Man Memory

The shared memory is divided into eight cache blocks as 0. 1,., 7. To maintain cache
coherence the system uses a three-state (R0, RW, and invalid) snoopy protocol based
on the write-invalidate policy. Assume the same clock drives the processors and the
memory bus. Within each cycle, any processor can submit a request to access the bus.
In case of simultaneous bus requests from both processors, the request from Pl is
granted and P2 must wait one or more cycles to access the bus. In all cases, the bus
allows only one transaction per cycle. Once a bus access is granted, the transaction
must be completed before the next request is granted. When there is no bus contention.
memory-access events from each processor may require one to two cycles to complete.
as specified below separately;
Page 3 of 4
 Read-hit in cache requires one cycle and no bus request at all.
Read-miss in cache requires two cycles without contention: one for block
and one for CPUread from cache
Write-hit requires one cycle for CPU write and bus invalidation
fetch
Write-miss requires two cycles: one for block fetch and bus
one for CPUwrite. simullaneously.
invalidation. and
Replacement of adirty block requires one cycle to update memory via
the bus.
Consider the following two asynchronous sequences of
bold-italicized face memory-access events, whera
numbers are for write and the remaining are for read.
Processor #1:0,0,0,1,1,4,3,3,5,5,5
Processor #2:2.2,0,0,7,5,5,5.7.7,0
Trace the executicon of these two
successive blocks. Both caches are sequences
initially
on the two processors by
flushed
executing the
(empty).
Organization in both caches. Indicate the state (R0 or RW) of Assume a direct-mannin.
and mark cache misses and bus each valid cache block
Cvcle. ASsume that the very firstutilization (busy or idle) in the block trace for each
place in cyclel
simultaneously. memory-access events from both processors take
respectively. Calculate the hit ratio of cache I and cache 2
With diagrams, discuss the
interconnects for efficient andHierarchical Bus and Crossbar
shared memory. fast
communication among theswitches used in system 81
multiple processors and
Q8 OR
With neat diagram,
networks along withdiscuss
message
the different message
routing schemes in
b
Discuss snoopy protocol for
the formats. multicomputer 12
caches. maintaining the cache coherence for different types of (3N
8M
Q9 Unit -y
Discuss the Principles of
h development.
Discuss the roles of
synchronization witk respect to parallel program 10
Reorder buffer (RC i
necessary diagrams an example. tsiruction level parallelism with 10
Q10 OR
Discuss the working of
Tomasulo's algorithm with necessary
What is the possible diagrams and example. 10

contribution from compiler in enhancing the

parallelism? Explain ILoop Unrolling with an example. instruction level 10
Q. No. la lb lc 3a 3b
CO -

2
5b
7b
2 9a
Q. No. 2a 3
2b 2c 4a 4b 4c
4 4
CO
-

1 6a 6b
-

2 2 2 Sa 8b 10a 10b 10c

3
4 4 5

Page 4 of 4
 USN S D
SDM COLLEGE OF ENGINEERING &
TECHNOLOGY, DHARWAD
B.E
(Computer Science and Engineering)
Course Code: 18UCSC700 Semester End Examination, January 2023
Course Title: Artificial Semester: VII
Puration :3 hours Intelligence and Machine Learning
Rote: Answer any one full Max. Marks: 100
question from each unit.
Unit - I
Q1

Explain briefly the components and features of

8Mar b Write A* Algorithm and find the Artificial Intelligence. 10 Marks

for given graph. shortest path from initial node to final (goal) node 10 Marks
10

A 5

12 Ma
he9 B
h-4
h-2

3X4=|
Marl
1
1
S
h-7 G

0Mar
D E
0 Mar he3

Hint: 'h' in the node indicated

Sis the start node heuristic value.
G is the goal node.
Mat Label on link indicates cost.
2 OR
Mar
Write the algorithm and explain in detail
means end analysis in Al with an 10 Marks
example.
Write Depth First Search (DFS)
graph below and show its output. Algorithm and Apply the technique for the given 10 Marks

A
Oc
-

D
 Unit - II

representation. We ha
Q3 types Knowledge disease
different Predicate Logic (FCOPL) to prove that
List and explain First Order Availa
resolution method usingknowledge base and also draw the resolution tree. 98 %
Apply forthe given
1V 97% o
goal is achieved V In othe
Knowledge Base: food.
all kinds of
i) Gitalikes chapati are food. Find the joint
ii)Mango and and is stillalive. alive is food.
for the below
eats
iii)Gita almond still
anyoneand is
iv)Anything caten by
Scenar
almond.
Goal: Gita likes Game oft
OR West W
Othe
for each.
04 and give an example
Differentiate followingdeclarative TOT
a knowledge
i. Procedural and
Prepositional and predicate logic Case 1: P(
i1. reasoning
Forward and backward its issues. Case 2: P(
i.
Knowledge Representation and Mappings and state
b Explain the
Unit - III
What is lin
given novel
Q5 Classifier for the given scenario on the High, Wind = Strong). method for
Apply Naive Bayes = cool, Humidity =
instance(outlook = sunny, Temperature Tennis or Not.
to play
Determine this instance suitable PlayTennis 2
Humidity Wind
Otlaok Tempruture
Day
Weak No
Hot High No
Sunny Strong
Hot High Weak Yes
Sunny Hot High Yes
Overcast High Weak What is lo
Mild Weak Yes
Rain
Rain
Cool Normal
Strong
No polynom
Ran
Cool Normal
Normal Strong
Yes
Overcant Col Weak No
D7 High
Sunny Mild
Normal Weak Yes D8
Sunny
Cool Wcak Yes What is re
Mild Normal
Raln Yes
Mild Nomal Srong Yes
below.
Sunny High Suong
vercast Mild Yes
DI2 Normal Weak
Overcast Hot No
D!3
Milkd High Srong
D4 Rain

wrt Al. X2 t2
b Briefly explain the following with an example
Probability
Inference
i11. Hypothesis b Write th
Prior Probability Construc

V. Novel Instances in Bayes theorem i. diame

ii. color
OR

Q6 scenario to diagnose that the patient

Define Bayes theorem and apply for given difficulties in applying Bayesta
practical
having cancer or not ? Also state the
method.
which resulted positive with
Scenario: A new patient has undergone cancer test
following assumptions as given below.
 i. We have prior knowledge that over entire population 0.008 have cancer
disease.
ii. Available data has twvo possible outcomes as positive and negative.
iii. 98% of test results are correct positive.
iv. 97% of test results are correct negative.
V. In other cases test results are in opposite.

h Find the joint probability for the given scenario and check for the independent or not
for the below gives cases.

Scenario: Male Female TOTAL

Game of thrones 80 120 200 10 Marks
West Word 100 25 125
Other 50 125 175
TOTAL 230 270 500

Case 1: P(West Word | Female) and P(West Word)

Case 2: P(West word o Female) and P(West Word) X P(Female)
Unit - IV

Q7
a What is linear regression? Find the mean square error (R) using Linear regression
method for the given data.
1 3 10 MarkS

3 2
4 4
5
logistic and
b What is logistic regression? Write the difference between linear, 10 Marks
polynomial regression methods.
OR
Q8 of space as
a What is regression tree? Construct regression tree for the given region
below.

RS
R2 R3
10 Marks
t4
R4
X2t2 RI

Xltl
given data set and
b Write the algorithm of decision tree. Apply the algorithm for the
construct decision tree based on the following criterias: 10 Marks
i. diameter and color attributes.
ii. color and diameter attributes
 Color Diam Label

Green 3 Mango
Yellow 3 Lemon
Red Grape
Yellow Mango
Red 1 Grape

Unit- V
09
a
With aneat diagram explainthe different early models of Neural networks.
What is Support Vector Machine? Explain types of SVM with example.
With a neat diagram explain the architecture of Artificial Neural Networks.
Recurrent Neural Network and Convolution Neural Network.

OR

Q10
a Write Hierarchical Clustering Algorithm and plot the dendogram using Min
cluster similarity (single link) with the following example shown in below Table. inter
Sample Y
No
P1 0.40 0.53
P2 0.22 0.38
P3 0.35 0.32
P4 0.26 0.19
P5 0.08 0.41
P6 0.45 0.30

Divide the given sample data given in table into two

algorithm using Euclidean Distance. Consider C1 and C2 areclusters using K-Means
the initial two clusters
respectively from the given Table.
Cluster No. Height (H)
C1
Weight (W)
185 72
C2 170 S6
C3 168 60
C4 179 68
CS 182 72
Table: Dataset

Q. No. la lb 3a 3 5b 7a 7b 9 9c
CO 1 3 3 4 4 4 4
Q. No. 2a 2b 4a 4 ba 6b 8a 8b 10a 10b
CO 2 2 3 3 4 5
 USN S D

SDM COLLEGE OF ENGINEERING & TECHNOLOGY, DHARWAD

B.E (Computer Science and Engineering)

Semester End Examination, February 2022
Course Code: 18UCSC700 Semester: VIi
Course Title: Artificial Intelligence and Machine Learning
Duration :3hours Max. Marks: 100

Note: Answer any one full question from each unit.

Unit - I
Q1
Explain Hillclimbing Heuristic search algorithm with an example and state its draw 8-2=10
Marks
backs.
b Write AO* algorithm and find and drawthe revised cost graph for the following. 8+2=10
Marks

Man(14,21]= 14

4ND
1

13
12

1 OR
1
AND

sD 5

OR
Q2
Explain in detailany one solution with production rules for the below given water jug 10 Marks
Problem scenario.
Problem Scenario: You are given two jugs, a 4-gallon one and a 3-gallon one.
Neither has any measuring mark on it. There isa pump that can be used to fill the jugs
with water. How can you get exactly 2 gallons of water into the 4-gallon jug.
Write Breadth First Search (BFS) algorithm and Apply BFS for the given graph below 10 Marks
and show its output.

Page Iof 4
 Unit - II

Q3
Apply resolution method using propositional logic to prove that the goal is
resolution tree.
achieved for the
draw the
given knowledge base and also
Knowledge Base:
or the sky is cloudy.
The humidity is highthen it will rain.
If the sky is cloudy,
high, then it is hot.
If the humidity is
It is not hot.
Goal: It will rain.
computahl,
prove that Marcus is not alive now using
Consider the following predicates to
1)

functions.
MarcuS Was a man.
1.
ii. Marcus was a Pompeian.
Marcus was born in 40
A.D.
iii.
0V. Allmen are mortal. erupted in 79 AD.
volcano
V AllPompeians died when the
Vi. No mortal lives longer than 150 years.
Vil I is now 2004.
Vili. Alive means not dead.
dead at all later times.
0x. if somebody dies, then he is
OR

Q4 example for each.

Differentiate following and give anknowledge M

procedural and declarative

ii Prepositional and predicate logic
backward reasoning
ii. Forward and Representation and Mappings and state its issues. M3
Explain the Knowledge
Unit - II

Instance. 10
Q5 for the given scenario on the given novel
a Apply Navie Bayes Classifier
= Holiday)
Yes, Free Delivery = Yes, Day= Holiday)
Instances are :
P(Yes Buy | Discount =
P(AJB)= Yes, Free Delivery = Yes, Day
P(AJB)= P(No Buy | Discount =

Ais Buy and No Buy Delivery = Yes and Day =

Holiday
B is Discount = Yes, Free
DataSet Scenario:
BUY
Frequency Table YES NO
WEEKDAY 2
7 1
DAY WEEKEND
HOLIDAY 3

YES 19 1
DISCOUNT
NO 5

YES 21
FREE
DELIVERY 3 4
NO

Page 2 of4
 b Briefly explain the following with an
Probability example. 5x2 =10
ii Inference Marks
iii. Hypothesis
iv
Prior Probability
V.
Novel Instances in Bayes theorem

OR
Q6
a What is Dempster Shafer Theory and Applv measure of belief
for the following set. 08 Marks
{Allergy, Flue, Cold, Pneumonia)
b Find the joint probability for the given scenario and check for the
independent or not 6+6=12
for the below gives cases. Marks
Scenario : Male Female TOTAL
Game of thrones 80 120 200
West Word 100 25 125
Other 50 125 175
TOTAL 230 270 500

Case 1: P(West Word | Female) and P(West Word)

Case 2: P(West word Female) and P(West Word) X P(Female)

Unit - IV
Q7
Explain Linear and Polynomial regression with example. 10 Marks
b Write a python code for the following 5x2=10
Marks
1. to display the labels in x andy axis for the graph.
to import data set
to display confusion matrix
to display Size of data set.
V to Display first five data rows.

OR
Q8 08 Marks
List and explain the major criteria's to split the data set using decision tree.
10+2=12
b Construct decision tree for the given scenario and indicate with proper label Marks
for the nodes and links.
for two
SceDario: XYZ company is considering whether it should tender
for the
contracts (MSI and MS2) on offer from a government department
supply of certain components. The company has three options:
tender for MS1 only; or
tender for MS2 only; or
tender for both MSI and MS2.
been determined. In addition,
For each contract, possible tender prices have of getting the
subjective assessments have been made of the probability
below. Note here that the
contract with a particular tender price as shown
for example, submit two
company can only submit one tender and cannot,
Page 3 of4
 prices) fr the same contract.
tenders (at different
Probability
Possible
Option of getting
tender Contract
prices (£)

130,000 0.20
MS1 only 0.85
115, 000

70, 000 0.15

MS2 only 0.80
65, 000
0.95
60, 000

190,000 0.05
MS1 and MS2
140, 000 0.65

Unit - V

Q9 back propagation algorithm. for tha

With a neat diagram explain
Clustering Algorithm and find Min inter cluster similarity
Write an Agglomerative
Euclidean distance.
given data using
X Y

0.40 0.53
PI
P2 0.22 0.38

P3 0.35 0.32

P4 0.26 0.19

P5 0.08 0.41
P6 0.45 0.30

OR
three
Q10 algorithm and apply for the given data to find the
Write K Means clustering second iteration.
cluster centers after the
locations) into
following eight points (with (x, y)representing
Given Data :Cluster the C3:
three clustersC1, C2
and A8(4, 9)
A3(8, 4), A4(5, 8), AS(7, 5), A6(6, 4), A7(1,2),
Al(2, 10), A2(2, 5),
A7(1. 2).
Al(2, 10), A4(5, 8) and (x2, v2) is defined as
Initial cluster centers are: two points a= (xl, y!) and b=
distance function between
The
|y2- yl|
P(a, b) = 2- xI| + explain SVM Classifier
With a neat diagram
b

7a 7 9a 9b
la 3a 3b 5a Sb
). No. 4
3 4
CO
6b 8a 8b J0a 10b
Q. No. 2a 2b 4a 4b
4
CO 2 2 3

Page 4 of4
 USN 2

SDM COLLEGE OF ENGINEERING & TECHNOLOGY, DHARWAD

B.E (Computer Science and Engineering)

Semester End Examination, February 2022
Course Code: 18UCS701 Semester: VII

Course Title: Advanced Computer Architecture

Duration :3 hours Max. Marks: 100

Note: Answer any one full question from each unit.

Unit - I

Draw and explain the architectural differences of Flynn's classification of computing architecture. Marks
Consider the execution of an object code with 2x 10° instructions on a 400MHz processor. The program
consists of "Four" major types of instructions. The instruction mix and the number of cycle (CPI) needed
for each instruction type is given below based on the results of a program trace experiment.
Instruction mix
Instruction Type CPI

Arithmetic Logic 60%

Load/ Store with cache hit 18%

Marks
Branch 4 12%

10%
Memory reference (with cache 8
miss)
Calculate the average CPI when the program is executed on auniprocessor
Calculate the corresponding MIPS rate based on CPl obtained.
reference to various 6
Explain the program partitioning, grain sizes and communication overhead with Marks
levels of parallelism in program execution.
OR

Define and explain the following terms related to parallelism and dependence relations:
Flow dependence Marks
ii. Antidependence
ii. Resource dependence
Analyze the data dependencies among the following statements in a given program:
Sl: Load R1, 1024
S2: Load R2. M(10)
S3: Add RI, R2
S4: Store M(1024), RI 7
S5: Store M((R2)), 1024 Marks

where Ri means the contents of register Ri and Memory(10) contains 64 initially.

i. Draw a dependence graph to show all dependences.
ii. Are there any resource dependences if only one copy of each functional unit is available in the
CPU?
The following Fortran Program is to be executed on a uniprocessor and parallel version is to be executed
7
on a shared memory multiprocessor. Marks
L1: Do 10|= 1, 1024
L2: SUM(I)-0
 L3 Do 20 J=1,J
L4: 20 SUM(J) =SUM(I) + L
L5: 10 Continue
Suppose statements 2 and 4 each take two machine cycle times, including all CPU
and memory-a
activities. Ignore the overhead caused by the software loop control and all other system
resource conflicts.
What is the total execution time of the program on a uniprocessor?
i Divide the outer loop iterations among 32 processors with prescheduling as foll
Overhead
Processor l executes the first 32 iterations (I=lto 32), processor 2 executes
(|=33 to 64). and so on. What are the execution time and speedup factors the next 32 ite
Unit - II compared with
Q3
Briefly explain the following concepts:
Degree of parallelism
Average parallelism
iii. Asymptotic speedup
b A workstation uses 1.5 GHz. Processor with a claimed 1000MIPS rating to execute a given
ne
Assume one cycle memory access delay.
What is the effective CPI?
Suppose if the clock is upgraded to 3.0 GHz., what is the execution time to execute 2
instructions.
With relevant block diagrams, compare and contrast RISCand CISC architectures
OR
Q4
a Define and explain the following related to modern processor technology:
i. Processor design space
Instruction issue latency
iii Instruction issue rate
Unified Versus split caches
V Hardwired Versus micro coded control
Explain the structures and operational requirements of the instructional pipelines used in CISC, seal
RISC, superscalar RISCand VLIW processors. Comment on the cycles per instructions expected fro
these processor architectures.
Unit - III
Q5
Consider the following reservation table:
2 3 45 6
S X X

S2 X

S3 X X X

What are the forbidden latencies and initial collision vector?

Draw a state diagranm for scheduling the pipeline.
Determine the MAL associated with the shortest greedy cycle
b
What are the different hazards you come across in instruction pipeline? How do you overcome ne
OR
Q6
a
Explain the different mechanisms to improve the efficiency of instruction pipelining.
b Explainthe following dynamic instruction scheduling algorithms:
Tumasulo's algorithm
ii. CDC scoreboarding
 With a neat diagram give step by step procedure for pipelined multiplication of two 8-bit binary numbers. 8
Marks
Unit - IV

6
What are multistage networks? Explain how routing takes place in Omega Network. Marks

Draw a l6-input Omega network using 4 X 4 switches a building blocks. 8

Marks
What is acache coherence problem? Explain Snoopy cache protocol to overcome cache coherence
problem. 6
Marks

OR

With a neat diagram explain the directory base cache coherence scheme. 10
Marks
Explain the following terms as applied to communication patterns in a message passing network:
Unicast Versus multicast
ii Broadcast Versus conference 10
iii Channel bandwidth Marks
iv. Communication latency
V.
Network Partitioning
Unit - V

Explain the various issues the parallel programming languages must address. Marks

Explain reorder buffering and register renaming as connected to instruction level parallelism Marks
OR
10
Explain the following terms associated with fast and efficient synchronization schemes on shared memory
multiprocessor:
i. Busy-wait versus. sleep-wait protocols for sole access of a critical section. 6
i. Fairness policies for reviving one of the suspended processes waiting in a queue. Marks
ii. Lock mechanisms for pre-synchronization to achieve sole access tocritical section.
Explain why mutual exclusion, non-preemption, wait for, and circular wait are necessary conditions but 6
not sufficient conditions for system deadlock to occur. Marks
8
Discuss various design issues in instruction level parallelism. Marks

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 USN 2 S D3
SDM COLLEGE OF ENGINEERING & TECHNOLOGY, DHARWAD

B.E (Computer Science & Engineering)

Semester End Examination, February 2022
Course Code: 15UCSE706 Semester: VII
Course Title: Software Testing Duration: 3 hours
Max. Marks: 100

Note: Answer any one full question from each unit.

Unit - I
Q1
10 Marks
Explain the process of Refactoring, Verification and Validation.
b Explain Testing and Debugging cycle with appropriate diagram and describe its 10 Marks
relevance in software testing.
OR
Q2
10 Marks
a With an example explain the relationship between the program under test and oracle. 10 Marks
Explain how the role of Developer and Tester are two distinct complementary roles.

Unit - II
Q3
Write a pseudocode that takes two integers x &y and outputs GCD (xy). List the 10 Marks
blocks and lines in pseudocode by forming Control Flow Graph. Also construct
feasible and complete paths by providing inputs.
b Explain with an example how the test selection could be done in Boundary Value 10 Marks
Analysis.
OR
04
Consider the task for a GUI based computer purchase system selling for computers,
printers, monitors and memory.The GUI consists of 4windows for displaying
selections from CPU, PR, Mand RAM andone window for free giveaway. Monitors
M20 and M23 can be purchased with any CPUor as a standalone item. M30can only
be purchased with CPU3. PR Iis available free with the purchase of CPU 2 and CPU
3. Monilors and Printers, except for M30, can also be purchased separately without
purchasing any CPU. Purchase of CPU Igets RAM 256 upgrade and purchase of CPU
2 or CPU3gets RAM S12 upgrade. The RAM IG upgrade and a free PR 2 is available
when CPU 3is purchased with monitor M30. Sample configuration is given below.
Items Purchased "Free Window" Price" 10 MarkS

CPU 3

CPU 2, M23, PR2

M 23

CPU3, M 30, PRI

i. List the causes and effects, and also draw the Cause- Effect Graph explaining
the relation between them.
ii. Express the relation in terms of Boolean expression.
b With an example explain the steps in generation of tests using Category Partition 10 Marks
Method.
 Unit - III

Q5 Explain the process of generating tests and test configurations using combinatorial

design. latin square of the order of 5.

Define latin square. Construct OR

Q6 to calculate x^y, form Data

Define the Definition-Use pair. Consider a program
Dependence Graph and Control Dependence Graph. expression.
Write an iterative worklist algorithm for computing available

Unit - IV
Q7
a
Define Test Adequacy and Criterion. With an example explain a test construction -
enhancement cycle.
Explain the Interprocedural analysis with respect to,
a) Context sensitivity.
b) Context insensitivity. 10
c) Flow sensitivity
OR
Q8
Define DU pair and DU path. With an example explain the Data Flow Testing
for, criteria
a) All DU pairs
b) AllDU paths 10
c) All definitions.
Explain with an example the Data Flow coverage with
and Pointers. complex structure using Arrays
10 1

Q9 Unit - V
Write a program to find and area and circumference of circle using
control flow graph. Write 3 test cases function and form
Condition testing and Path testing. and compute Statement testing, Branch testing, 10 M
List and explain thc issues in
testing Object-oriented software.
Q10 OR 10 M

Explain the
b
How the testimpact of
executionObject-Oriented
can be performeddesign and coding on analysis and 10M
with respect to capture testing.
and reply. 10M

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