CDMA BASED WIRELESS TRANSCEIVER SYSTEM

MATLAB SIMULATION AND FPGA IMPLEMENTATION

Zohaib Mahtab, Suhaib Jalis Ahmed, Syed Sameem Hussain, Sarwar Hasan
Dept. of Computer & Information Systems Engg., N.E.D University of Engg. & Tech. Karachi
{zohaib.online,suhaibj, sameem.hussain, server_hasan}@gmail.com

Abstract provides superior multiple-access capabilities, in addition

to a number of other desirable attributes for wireless
Code Division Multiple Access (CDMA) has become cellular service. These attributes include optimum
the technology of choice for the current and future subscriber station power management, universal
generation of wireless systems. We have implemented the frequency reuse, soft handoff, and enablement of the use
CDMA IS-95 based Wireless Transceiver System using of optimum receiver structures for time-varying
Matlab Simulink v 7.0. The entire system is implemented multipath fading channels [1]. We assume that the reader
using the Xilinx System Generator Block v6.3. has some familiarity with CDMA principles and the IS-
95-A standard, in particular.
Even though the CDMA IS-95 system is already Simulink, which runs in MATLAB, is an interactive
implemented in Simulink and is provided as a demo, tool for modeling, simulating, and analyzing dynamical
there is no way of converting it into real Hardware. systems. The Xilinx System Generator [8], a high-
Using Xilinx System Generator we have made our performance design tool, runs as part of Simulink. The
implementation capable of being translated into any of System Generator elements bundled as the Xilinx
the HDL codes. This can be then mapped onto Blockset appear in the Simulink library browser. It
appropriate FPGA easily. We have used the hardware provides some basic block for system design. The
co-simulation feature of the Xilinx System generator to Bottom-Up approach for the system development is used,
create a library of the basic building blocks of the IS-95 wherein we have divided the sub-modules of the system
system. This library can be used for implementing to into the basic leaf blocks, so that they can be mapped
create the various channels that are the part of the with the provided library blocks.
CDMA system.
This paper is organized as follows. In section 2
Keywords: CDMA, CRC, Convolutional, Interleaver, PN System Architecture is explained. Section 3 deals with
Sequence, Walsh codes, Viterbi decoder. the implementation of the whole architecture. Synthesis
and the results are discussed in Section 4. Finally the
paper is concluded in section 5.
1. INTRODUCTION
Code Division Multiple Access (CDMA) has become
the technology of choice for the current and future 2. SYSTEM ARCHITECTURE
generation of wireless systems. IS-95 based CDMA
systems developed by TIA have been widely deployed in In this section the complete system architecture has
the U.S. and around the world [1]. The IS-95-A design been discussed.

CCECE 2004- CCGEI 2004, Niagara Falls, May/mai 2004

0-7803-8253-6/04/$17.00 ©2004 IEEE

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
 [17 423] [657, 475] PCBs Wi I Pilot PN

1.2288 Mcps
800 bps BB Filter
1.2288 Mcps
8.6 Kbps 9.6 Kbps 19.2 Kbps 19.2 Kbps
CRC Conv.Encoder Block To QPSK
Generator R = 1/2 Interleaver Modulator

BB Filter

Long Code Decimate 800 bps 1.2288 Mcps

Generator 64

f (ESN) 1.2288 Mcps 19.2 Ksps Decimate Q Pilot PN

24

19.2 Kbps Despreader

8.6 Kbps 9.6 Kbps 1.2288 Mcps
Frame Quality Viterbi Derpeater Deinterleaver Descrambler Demodulator
Detector Decoder

[17 423] [657, 475] Long Code Decimate

Generator 64
Wi

Figure 1: Forward Link Traffic Channel Transmitter and Receiver.

The base-band sequence is a stream of 0s that are spread

2.1 Channel Description by Walsh function 0, which is also a sequence of all 0s.
The standard IS-95 protocol has two different link 2.1.2 Sync Channel: The information that is contained in
structures for the Forward Channel and the Reverse the sync channel message notifies the mobile of
Channel. Our developed system is based on the IS-95 important information about system synchronization and
Forward Channel architecture. parameters. First the base-band information is error
protected and interleaved. It is then spread by Walsh
The forward link consists of four types of logical function 32 and further spread by the PN sequence that is
channels [1], [2], [3], [11]: pilot, synchronizing, paging, identified with the serving sector. The base-band
and traffic channels. There is one pilot channel, one sync information is at a rate of 1.2 Kbps.
channel, up to seven paging channels, and several traffic
channels. Each of these forward-link channels is first 2.13 Paging Channel: The paging channel also carries
spread orthogonally by its Walsh function, and then it is baseband information at higher rates. It can transmit at
spread by a quadrature pair of short PN sequences. At either 4.8 or 9.6 Kbps. Although there can be up to seven
one time IS-95 supports up to 63 channels, and each one paging channels per sector, each mobile only monitors
has a unique Walsh code sequences. All channels are one paging channel. The baseband information is first
added together to form the composite SS signal to be error protected, and then if the data rate is at 4.8 Kbps,
transmitted on the forward link. the bits are repeated once. Otherwise, they are not
repeated. Following interleaving, the data is first
2.1.1 Pilot Channel: The pilot channel is transmitted scrambled by a decimated long PN sequence, and then it
continuously by the base station sector. The pilot channel is spread by a specific Walsh function and by the short
provides the mobile with timing and phase reference. The PN sequence assigned to the serving sector. Long PN
mobile’s measurement of the signal-to-noise ratio (i.e., code undergoes a decimation ratio of 64:1 (i.e., from
Ec /I0) of the pilot channel also gives an indication of 1.2288 Mcps to 19.2 Ksps). The long-code generator
which is the strongest serving sector of that mobile. The itself is masked with a mask specific to each unique
pilot channel is identified by the Walsh function 0 (w0). paging channel number (i.e., 1 through 7). The paging
The channel itself contains no base-band information. channel is divided into 80-ms slots. A group of 2,048
slots is called a maximum slot cycle. An 80-ms slot is

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
divided into four paging channel frames, and each paging rate of 1.2288 Mcps. The data stream is further spread by
channel frame is further divided into two paging channel the assigned short PN sequence of the transmitting
half-frames. The first bit of each half-frame is called the sector. The short PN sequence provides a second layer of
synchronized capsule indicator (SCI) bit. isolation that distinguishes among the different
transmitting sectors. This way, all 64 available Walsh
2.1.4 Traffic Channel: The forward traffic channel is functions can be reused in every sector.
used to transmit user data and voice; signaling messages
are also sent over the traffic channel. 3. SYSTEM IMPLEMENTATION
Figure 1 shows the forward traffic channel for Rate
Set 1. For this rate set, the vocoder is capable of varying 3.1 Design Consideration
its output data rate in response to speech activities. Four
different data rates are supported: 9.6, 4.8, 2.4, and 1.2 The design considerations which are followed during
Kbps. For example, during quiet periods of speech, the the design will be mentioned here.
vocoder may elect to code the speech at the lowest rate of
1.2 Kbps. The baseband data from the vocoder is First, as per IS-95 system architecture, our design
convolutionally encoded for error protection. For Rate starts after the very first block i.e. vocoder. It means that
Set 1, a rate 1/2 convolutional encoder is used. The the input to our system will be the raw data stream at the
encoding effectively doubles the data rate. After defined rate sets.
convolutional encoding, the data undergoes symbol
repetition, which repeats the symbols when lower rate Secondly, the IS-95 as an international standard for
data are produced by the vocoder. After symbol mobile communication has some strict real time
repetition, the data is interleaved to combat fading then constraints. Even though, we have followed the protocol
the interleaved data is scrambled by a decimated long PN with timing limitations, very strictly, the leaf blocks
sequence. The long PN sequence is generated by a long which are used to develop the system do have some
PN code generator. The generator outputs a long PN latency. Our system modules deal with the data stream in
sequence at 1.2288 Mcps. Because the data rate at the frames, and a frame of information data as defined by the
interleaver output is 19.2 Ksps, the PN sequence is IS-95 standard has a span of 20ms. The modules that are
decimated by a ratio of 64:1 to also achieve a rate of 19.2 developed, although accepts data in a 20ms time frame,
Kcps; the decimated long PN sequence at 19.2 Kcps is but their processing require some time, because of the
then multiplied with the 19.2-Ksps data stream. Note that latencies. Therefore as the system starts, it will take some
the long-code generator produces the long PN sequence time to output the first frame, but then after there will be
using a mask that is specific to the mobile. In reality, the no delay in the subsequent frames.
mask is a function of the mobile’s electronic serial
number (ESN).
3.2 Cyclic Redundancy Check Generator
The PCBs at 800 bps are then multiplexed with the
scrambled data stream at 19.2 Ksps. A PCB can be IS-95 CDMA use Cyclic Redundancy Check to
punctured into any one of the first 16 bit positions of a indicate the quality of each transmitted frame [1].
PCG (which contains 24 bits). The exact location of the According to the standard, when the vocoder is operating
PCB in the PCG is determined in a pseudorandom at full rate, each 20ms frame consists of 172 bits, thereby
fashion. More specifically, given that the input of the giving the data rate of 8.6kbps. This data is input to the
decimator is the long PN sequence, the PCB bit position CRC encoder to generate the 12 frame quality bits and 8
is determined by the decimal value of the four most encoder tail bits. The 8 encoder tail bits consist of 0s and
significant bits of the decimator output. It is important to are merely responsible for flushing the bits out from the
recognize that the exact location of the PCB in the PCG convolutional encoder which comes after the CRC
is not fixed, but is determined in a pseudorandom encoder. The generator polynomial used to generate the
manner. frame quality bits for a full-rate frame is:
g (x) = x 12 + x 11 + x 10 + x 9 + x 8 + x 4 + x + 1
At this point, the multiplexed data stream (still at
19.2 Ksps) is orthogonally spread by the assigned Walsh Input: Input data Frame @ 8.6 kbps according to Rate
function. Each forward traffic channel is identified by its set 1, i.e. 172 bits in 20-ms. Output: CRC encoded data
assigned Walsh function. The spreading Walsh function @ 9.6 kbps according to Rate set 1, i.e. 192 bits in 20-ms
is at a rate of 1.2288 Mcps; each symbol is spread by a which consists of 172 data bits, 12 frame quality bits and
factor of 64, and the result is a spread data stream at a 8 encoder tails.

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
 The basic blocks which are used for the 3.3 Convolutional Encoder
implementation are Shifter, LFSR and the Select Logic.
The input 172 bits are first passed through the shifter The Convolutional Encoder provides us powerful
block which first converts the serial input into the error-correcting & encoding capability [1]. At the
decimal equivalent of the 172 bits. This is done because receiver, the Viterbi Decoder is used to reverse this
the shifter block of the system generator only accepts encoder’s effect. Along with the Viterbi Decoder, the
parallel input. This decimal value is then shifted by 20 convolutional encoder is a means of correcting a multiple
places and is then again converted into the serial form. number of errors. It is an FEC technique that is
The shifted serial bits are then passed through the LFSR particularly suited to a channel in which the transmitted
block. The LFSR consists of a series of registers and signal is corrupted mainly by additive white Gaussian
XOR gates, in which the tapping is done according to the noise (AWGN). AWGN can be thought of as noise
generator polynomial specified above. The remainder whose voltage distribution over time has characteristics
from the LFSR will be generated after 184 clock cycles that can be described using a Gaussian, or normal,
and this remainder will be then appended with the data statistical distribution, i.e. a bell curve [4].
starting from the 172nd clock cycle. Therefore delays of
12 units have to be inserted in the data bits path. The Encoded bits are functions of information bits and the
check bits (remainder) will be generated in parallel exact number of memory elements. The information sequence
at 184th clock cycle but will be appended in the serial is shifted into a shift register k bits at a time. Bits are
fashion. To make the check bits serial from MSBs to tapped off at different stages of the shift register and
LSBs, the select logic and the MUX is used. The Select summed in a modulo-2 adder (XOR gate).
Logic Block is used in order to enable the MUXes at the
right time. There are 12 Muxes in all and one of the The convolutional encoder is defined by two
inputs to each of the MUXes is the one of the outputs parameters:
from the LFSR. 1. Constraint Length K = No. of shift registers + 1.
This basically represents the number of
The remainder is then ORed with the delayed data locations from where bits can be tapped of.
stream, the MSB or the remainder is put at 172nd placed 2. Rate = k/n. If there are n modulo-2 adders, it
and so on, the remainder ends at 184th place. Then the 8 means that for every k-bit shift, there will be an
tail bits follow, thus making the length of whole CRC output of n bits.
encoded frame equal to 192. Since there is a maximum of
4 input OR is available in the library, and the latency of For the forward-link, IS-95 sets the constraint length
the OR gate is zero, multiple gates are used in order to as K=9. i.e. an 8-bit shift register is used. The 8 encoder
perform the desired operation. tail bits mentioned in the previous section were added to
clear the contents of the shift register before the next
LFSR frame enters. IS-95 has defined the rate to be 1/2., which
means that there are two separate modulo-2 adders. So
184 bits for every one bit that enters the convolutional encoder,
12 bits two bits are received at the output. The generator
polynomials representing the modulo-2 adders are
G0 = x8 + x7 + x5 + x3 + x2 + x + 1

G1 = x8 + x5 + x4 + x3 + x2 + 1
It should be noted that there should be only one
12
output port from which the result of both modulo-2
Remainder adders is to be passed. Therefore, the output of both
bits modulo-2 adders has to be time-multiplexed. The input
rate of the convolutional encoder is 9.6 ksps (kilo
192 bits Frame symbols per second); this rate will obviously double to

Figure 2: CRC Encoder

3.2 Convolutional Encoder

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
19.2 ksps. repeater:
G T Input
XOR I Out
1 1
M
E
0
In
M
XOR U
G 2s 4s
X
Convolutional Encoder Figure 4: Input to Interleaver
Now, according to the principle of symbol repetition,
Figure 3: Convolutional Encoder we increase the symbol rate by 4. This is done by
repeating each received symbol 3 times at 2 sps
While implementing the convolutional encoder, the
data was made to pass through an 8-bit shift register. The Output
modulo-2 adders were implemented simply by using
cascaded 2-input XOR gates. Inputs for the modulo-2 1 1 1 1 1 1 1 1
adders (i.e. XOR) were tapped from the 8-bit shift
register as specified in the generator polynomials. Finally 0 0 0 0
the output of the modulo-2 adders were time multiplexed
onto a single output port.
1 2 4s
3.4 Symbol Repeater
Figure 5: Interleaved Output
Symbol repetition has the following benefits:
So effectively, there does not seem to be any
• Reduces probability of error
difference between the input signal and the output signal.
• Decreases power per repeated symbol when the
This seems to mean that no additional circuitry in the
data rate is low
symbol repeater. We just have a clock which samples
• Maintains an output data rate of 19.2ksps
input at 19.2 ksps, regardless of the input rate .The block
regardless of input rate, in case of Rate Set I.
interleaver needs input at 19.2 ksps, and therefore it must
have a clock that samples at 19.2 ksps. This means that
The probability of error is reduced because of having
the clock of the interleaver serves as the symbol repeater,
the same symbol repeated redundantly.
we won’t need a separate module for the symbol
repeater.
We must maintain an output data rate of 19.2 ksps
(kilo symbols per second) because that is the fixed input
data rate of the next component, i.e. the block 3.5 Block Interleaver
interleaver. For this purpose, the following scheme is
used. At full rate of 19.2 ksps, there is no need to repeat. Signals traveling through a mobile communication
At half rate i.e. 9.6 ksps, we will need to repeat the channel are susceptible to fading. The error-correcting
symbol once, so that every symbol is sent twice, meaning codes are designed to combat errors resulting from fades
that the rate at the output is 19.2 ksps. Similarly at 4.8 and, at the same time, keep the signal power at a
ksps, we repeat the symbol thrice. While at 2.4 ksps, we reasonable level. Most error-correcting codes perform
repeat it 7 times well in correcting random errors. However, during
periods of deep fades, long streams of successive or burst
Consider a scaled-down example in which we take 2 errors may render the error-correcting function useless.
sps as full rate. Suppose data arrives at ¼ rate i.e. 0.5 sps,
at the input. We send 1 0 1 to the input of the symbol Interleaving is a technique for randomizing the bits in
a message stream so that burst errors introduced by the
channel can be converted to random errors [1]. Random
errors are then corrected by the FEC techniques
mentioned in the previous sections.

The interleaver consists of a 2D block or matrix of

shift registers. The transmitter reads encoder output

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
symbols into the matrix by rows until it is full. Then the 3.6 Data Scrambling
contents of the matrix are shifted out by columns. While
one matrix is filling the other is being emptied. After the data is interleaved, it is XORed with Long
PN Sequence. [5] The long PN code is generated in a 42
The interleaver of IS-95 consists of two 24 row by 16 stage linear shift register generator with the output of the
column blocks. While one block is shifting horizontally 42nd stage input into the first stage and modulo-2 added
to receive input of the current frame, the other is shifting with the outputs of stages 1, 2, 3, 5, 6, 7, 10, 16, 17, 18,
vertically to give output of the previous frame. 19, 21, 22, 25, 26, 27, 31, 33, and 35 as depicted in the
figure below. The output of the long code generator is
taken after the output of each flip-flop in the generator
has been added with a corresponding bit in a 42-bit mask
which is unique to each user, access, and paging channel.

Figure 6: Horizontal Shift (used to take input)

Figure 8: Long Code LFSR

The output of the flip-flop is in parallel; therefore it is
then passed from the Parallel to Serial block at the rate of
1.2288 Mcps. The output of the interleave is at the rate of
0.02 / 384 Kbps, therefore in order to make the Long
Figure 7: Vertical Shift (used to take output)
code compatible so that bit wised XORed can be
performed; it is down sampled by 64. This XORed data
The functionality of the block interleaver was
is then passed from the power control block.
implemented first by creating the matrix of shift
registers. Every shift register in this block has two
possible input sources. The first source is the horizontal 3.7 Power Control
predecessor and the other is the vertical predecessor.
Hence a multiplexer was required for each of the 384 Power control is essential to the smooth operation of
shift registers. However the first register requires no a CDMA system. Because all users share the same RF
multiplexing as it always receives the input bit. When the band through the use of PN codes, each user looks like
select pin of these MUXes was ‘0’, it results in a random noise to other users. The power of each
horizontal shift indicating the input mode. When this pin individual user, therefore, must be carefully controlled so
is ‘1’, it results in a vertical shift indicating the output that no one user is unnecessarily interfering with others
mode. who are sharing the same band [1]. The base station
sends the power-control commands to the mobile using
The block interleaver uses two instances of this the forward link. These power-control commands are in
matrix. At any time, one of the matrices takes input (i.e. the form of power control bits (PCBs). The amount of
shifts horizontally) while the other gives output (shifts mobile power increase and power decrease per each PCB
vertically). Hence selection logic is required to select a is nominally +1 dB and -1 dB.
matrix for input or output. This selection logic simply
consists of a counter that counts to 384. As soon as the After the data is interleaved the PCBs at 800 bps are
count reaches 384, the roles of the matrices are switched. multiplexed onto the baseband stream at 19.2 Kbps. The
The matrix that was taking input is now giving output PCBs are integrated into the traffic channel by robbing
and the second matrix is doing vice-versa. selected bits from the baseband stream. This way, a
separate “channel” at 800 bps (for power-control
To understand the manner in which the effect of the purposes) exists beneath the traffic channel. The stream
interleaver is nullified, please refer to the Block of PCBs at 800 bps is therefore called the power-control
Deinterleaver section. subchannel (PCS). These PCBs are continuously
transmitted to the mobile by the base station. Note that
since the rate of PCB transmission is 800 bps, a PCB is
sent once every (1/800) second, or 1.25ms. Both
forward-link and reverse-link traffic channel frames are
20 ms in duration. Since one PCB is sent once every 1.25

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
ms, each traffic channel frame can be divided into (20
ms/1.25 ms) or 16 segments. These segments are called In the implementation, all the 63 possible 64-bit
power-control groups (PCGs). Since each power-control Walsh codes are placed in separate ROMs. A particular
group is 1.25 ms in duration and the baseband is at a rate channel will use only one Walsh code. The message m (t)
of 19.2 Kbps, then each power-control group contains is up-sampled by a factor of 64. In other words, every bit
(19.2 ´ 103)(1.25 ´ 10-3) = 24 bits. is repeated 64 times. Each repeated bit is XNORed with a
bit in the Walsh code w (t). The XNOR gate serves as a
The decimated output of the LFSR is again down multiplier that is unique for every channel. Its output is
sampled by 6 to make the rate 800bps. The position of called the product of m (t) and w (t). Effectively each
the PCB in each PCG is determined in the pseudorandom message bit mi(t) is multiplied with each Walsh code bit
fashion. The 4 most significant bits of the two times wi(t). This product can be represented as mi(t)wi(t) and it
decimated long code is converted into decimal and then it has two possible values: 0 and 1.
is used to control the MUX whose inputs are the first 16
bits of the PCG. Therefore the power bit can have any The output of the XNOR gate is then passed through
place from 0 to 15 in each PCG. In this way the whole a unipolar-to-bipolar converter that basically converts 0
power is distributed in the frame. to -1, while 1 is left as it is. So now the signal has two
possible values: -1 and 1. The output of the unipolar-to-
bipolar converter of every channel is now added, the
result can be represented as Σ mi(t)wi(t). This output
varies from -63 to +63; i.e. the output has 7 bits coming
in parallel. These parallel bits are made to pass serially
through the single-bit output. The final output appears
completely different from the input.

Effectively, the input rate of 19.2 ksps has been

increased firstly before the multiplier by a factor of 64.
Then it is further increased by a factor of 7 at the output.
In all, the output rate of the Walsh Spreader comes out to
Figure 9: Power Spreading be 19.2ksps * 64 * 7= 8.6016 Msps.

To understand the manner in which the data is

3.8 Walsh Spreading retrieved, please refer to the Walsh Despreader.

In order to avoid mutual interference on the forward

link, Walsh codes are used to separate individual users 3.9 Short PN Spreading
while they simultaneously occupy the same RF band.
Walsh codes as used in IS-95 are a set of 64 binary In a CDMA system the PN code sequence is mainly used
orthogonal sequences [1], [11]. These sequences are for code spreading, code scrambling, and code division
orthogonal to each other, and they are generated by using [12], [9]. Code spreading spreads the channel power
the Hadamard matrix. Recursion is used to generate across the whole channel, the scrambling gives additional
higher order matrices from lower order ones; that is, data security and the code division expands the channel
capacity. Code division by PN code offset is used in the
IS-95 system. The channels use the same PN sequence
but skewed in time with reference to a common
reference. The PN code is characterized by a Polynomial,
Where ĤN contains the same but inverted elements of HN. where the degree of the polynomial is equal to the
The seed matrix is: number of stages in the generating register. In the
Cellular and PCS systems as per IS- 95, the quadrature
modulation in forward and reverse link is performed by
using two distinct PN sequences generated by 15 stage
shift registers and lengthened by one chip to 215 = 32,768
The IS-95 forward link uses a set of 64 orthogonal chips. At a rate of 1.2288 Mcps, the sequence repeats
Walsh sequences, thus the physical limitation on the every 26.66 ms or 75 times every 2 seconds [12]. The
number of channels on the forward link is 63 because in characteristic polynomial for in-phase (I) and quadrature-
an IS-95 system, w0 is not used to transmit any baseband phase (Q) sequence are:
information.

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
 G0 = x15 + x13 + x9 + x8 + x7 + x5 + 1 place the descrambler output can be highly affected
because it performs the same XOR function as was
G1 = x15 + x12 + x11 + x10 + x6 + x5 + x4 + x3 performed on the receiver side to decrypt the data bits.
The implementation for the I and Q PN sequence is done
by the shift registers and the XOR gates as defined by the 3.12 Block Deinterleaver
polynomial.
At the receiving end, the block deinterleaver nullifies
the effect of the block interleaver. T deinterleaver
3.10 Walsh Despreading reconstructs the message using the same matrix (block),
except in this case the deinterleaver loads the received
The Walsh Despreader is a component on the message into columns first, and then reads the message
receiver side, whose purpose is to nullify the effect of out from the rows.
Walsh spreading. The Walsh spreader was used to merge
the data of all 63 channels. But the Walsh Despreader The block deinterleaver uses two instances of this
will extract the data of any one of the channels. Hence, it matrix. At any time, one of the matrices takes input (i.e.
only uses one Walsh code unique to that particular shifts vertically) while the other gives output (shifts
channel. horizontally). Hence selection logic is required to select a
matrix for input or output. This selection logic simply
The implementation of the Walsh despreader is as consists of a counter that counts to 384. As soon as the
follows. The output of the multiplier in the Walsh count reaches 384, the roles of the matrices are switched.
spreader has a value varying from -63 to +63; i.e. the The matrix that was taking input is now giving output
output has 7 bits coming in parallel. But the 7 bits are and the second matrix is doing vice-versa.
sent serially through the final output. The first task of the
Walsh Despreader is to collect 7 serially entering bits and The output of the deinterleaver will contain
convert them to parallel. Once again we have values information with random errors, i.e. the probability of
ranging from -63 to +63, which represent Σ mi(t)wi(t). two contiguous erroneous bits is very much less. This is
so because the interleaver caused consecutive bits to
The bits of the Walsh code (stored in memory) are become far apart from each other, so burst errors in the
first passed one by one through a unipolar-to-bipolar channel do not affect the consecutive bits. The absence of
converter. So each bit has been converted to -1 or +1. no continuous erroneous bits makes it easier for the
These values are multiplied by the incoming values of Viterbi Decoder to correct the scattered random errors
Σ mi(t)wi(t). The products are sent into an adder that takes
64 such products as input. The output of this sum is
represented as Mi(t). A “decision threshold” looks at the 3.13 Symbol Derepeater
integrated function Mi(t ).The decision rules used are
m(t) = 0 if M(t) < 0 At the receiver, the symbol derepeater works like a
m(t) = 1 if M(t) > 0 voter. It simply counts how many of the repeated
symbols are 1 and how many are 0. If the number of 1s is
The output data rate is 19.2 Ksps. greater, the output is a 1. If the number of 0s is greater,
the output is a 0.
3.11 Descrambler Naturally, the voter’s parameters depend on the data
rate. At full rate, there will be no voting. This is so
This is a hierarchical block performing power
because full rate does not require repetition in the first
bit extraction and descrambling. It extracts the power bit place. At ½ rate, the voter will check for majority in 2
for each PCG using the long code and combines the symbols. At ¼ rate, the voter will check for majority out
signals from all fingers. The extracted power bit is
of 4 symbols. At 1/8 rate, the voter will check for
updated once every power group, that is, 16 times every majority out of 8 symbols.
20 ms frame. There are two symbols carrying the power
control bit in Rate. After power bit extraction the block
The implementation was carried out by developing
sets to zero the symbol corresponding to the power separate circuitry for each rate. The basic functionality
control bit. The block subsequently descrambles the was the same. Consider the circuit for ¼ rate. This circuit
combined signal using the decimated long code consisted of an adder that sums 4 incoming bits. If this
sequence. Synchronization between the sender and the value is greater than 2, the output is 1. If the value is less
receiver is the most important thing while decoding.
than or equal to 2, the output is 0. The immediate
Even if the synchronization is missed with only one bit

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.
question that arises is that if the sum is 2, it indicates simple application which consists of the microphone at
equality, so why was the output set to 0. The answer is the transmitter and the speaker at the receiver was used to
that it does not create much of a difference. The Viterbi test the dumped system.
decoder is able to correct multiple errors.
5. CONCLUSION
3.14 Viterbi Decoder
Xilinx System generator is a powerful tool for
This block decodes a convolutionally encoded accurately translating the simulated design into HDL,
information sequence optimally [6], [4]. In the IS-95 hence making it suitable for creating FPGA
system, the constraint length of the viterbi decoder is 9. implementation. System architecture based on the
The Viterbi algorithm searches through the trellis, which forward Traffic channel of the IS-95 system has been
defines all possible allowed sequences determined by the discussed, and briefly their implementation using the
encoder, for the most probable sequence. This is done by library blocks of the Xilinx System Generator has been
updating likelihood metric for each possible choice of the presented. Finally a simple application demonstrating the
decoded sequence and selecting the paths corresponding FPGA implementation has been presented.
to the best metric choices. Finally, it outputs the decoded
data along with the metric for the final detected path. The
decoder performs a traceback along the survivor paths in References
the trellis to generate the output bits. Since the traceback [1] Samuel C. Yang, NCDMA RF SYSTEM
is started in the zero state, so the last 8 bits of the ENGINEERIN . London: Artech House
sequence being decoded must be 0, which indicates the
flush bits that were inserted in the CRC encoding [2] CDMA DESIGN LIBRARY . Agilent Technologies,
process. We do not have implemented the viterbi decoder 2003.
from the basic blocks, but have used the one that is
already provided in the library. [3] ACOLADE IS-95-A / CDMA LIBRARY OVERVIEW.
ICUCOM Corporation, 1996.

3.15 Frame Quality Indicator. [4] Chip Fleming, “A Tutorial on Convolutional Coding
with Viterbi Decoding” Spectrum Applications.
The effect of the CRC Generator is cancelled out by
the Frame Quality Indicator. Actually, this component [5] www.cdmaonline.com
can be considered as “the last resort”. It checks to see if
the data is correct. If the data is correct, it is allowed to [6] Richard B. Wells, APPLIED CODING AND
move forward. However, if it is not, it stops it from INFORMATION THEORY FOR ENGINEERS.
moving forward to the output.
[7] CDMA DESIGN LIBRARY . Agilent Technologies,
Consider full rate transmission. The Frame Quality 2003.
Indicator extracts the 184 bits out of the 192 bit frame.
The remaining 8 bits are supposed to be 0.These 184 bits [8] XILINX SYSTEM GENERATOR v 2.1 BASIC
are made to pass through an LFSR similar to the LFSR of TUTORIAL. U.S.A.
the CRC Generator. If the output of the LFSR is 0, it
indicates correct data. [9] CODE DIVISION MULTIPLE ACCESS – A
TUTORIAL . Amol Shah, 1999
4. SYNTHESIS AND RESULTS
[10] RECONFIGURABLE MODULE TO SUPPORT
After having developed the various submodules of MULTIPLE CDMA STANDARDS. Nara Doriswamy,
the mentioned architecture, those submodules were Metuchen, N.J.
integrated. The final simulation was run on Simulink.
Next, the hardware co-simulation feature of the System [11] TECHNICAL INTRODUCTION TO CDMA
generator was used to create a library of the separate v3.23, Scott Baxter, 2003.
submodules. The blocks in this library were basically the
HDL versions of the submodules. These library blocks [12] RECONFIGURABLE MODULES TO SUPPORT
were used to recreate the design, and the bit file was then MULTIPLE CDMA STANDARDS.,
generated. Finally the bit file was dumped into the Nara Doriswamy, Metuchen, N.J.
Viterx2 xcv3000 FPGA with a speed grade of -4. A

Authorized licensed use limited to: S R R Engineering College. Downloaded on March 04,2010 at 01:07:27 EST from IEEE Xplore. Restrictions apply.