Week 7: Assignment 7
Q1: Find the BW of the given amplifier circuit. The device’s parameters are gm= 4mA/V, rds = 40KΩ,
Cgs = 5 pF, Cgd = 2 pF, RD = 20KΩ, RSIG = 100Ω. (Consider fH >> fL)
a. 10 MHz
b. 14 MHz
c. 18 MHz
d. 26.3 MHz
Ans: (b) 14 MHz
Q2: For the amplifier circuit shown in figure below, calculate its midband gain (AM). Given RSIG =
100Ω, RG = 100Ω, RD = 20KΩ, rds = 40KΩ and gm = 4mA/V
a. − 25.6
b. − 23.9
c. − 26.67
d. − 31.5
Ans: (c) − 26.67
Q3: An n channel JFET has IDSS =10 mA and VP = −3V. Find its max transconductance
a. 0.4 mS
b. 6.67 mS
c. 7.84 mS
d. 3 mS
Ans: (b) 6.67 mS
Q4: For an n-channel JFET, IDSS = 10mA, VP = −5V and VGS = −3.5V. Find ID
a. 0.8 mA
b. 1 mA
c. 1.2 mA
d. 0.9 mA
Ans: (d) 0.9 mA
Q5: Working of a JFET can be explained as modulation of the channel conductance by an electric
field ____
a. Parallel to the channel.
b. Perpendicular to the channel.
c. Parallel and Perpendicular to the channel.
d. Equal to zero
Ans: (c) Perpendicular to the channel
Q6: In a BJT based differential amplifier, the allowable range of V CM is determined at the upper end
by Q1 and Q2 leaving the ____ mode and entering _____ mode.
a. Cut-off; Active
b. Active; Saturation
c. Saturation; Active
d. Active; Cut-off
Ans: (b) Active; Saturation
Q7: fH and fL are the frequencies at which the gain drops by ___ below its value at midband.
a. 20 dB
b. 3 dB
c. 6 dB
d. 10 dB
Ans: (b) 3 dB
Q8: In a JFET, IDSS is a function of transistor’s width.
a. True
b. False
c. IDSS independent of transistor’s width
Ans: (a) True
Q9: For a perfect matched differential pair, the common mode gain should be ____ and CMRR should
be _____.
a. Zero; Zero
b. Zero; Infinite
c. Infinite; Zero
d. Infinite; Infinite
Ans: (b) Zero; Infinite
Q10: The input stage of every op-amp is a _______.
a. Differential amplifier
b. Common source amplifier
c. Common gate amplifier
d. Common drain amplifier
Ans: (a) Differential amplifier
Week 7: Assignment 7: Brief Explanation
Q1. Explanation:
Cin = Cgs + Cgd (1+gmRL)
RL = RD || rds = 20 KΩ || 40 KΩ = 13.33 KΩ
Cin = Cgs + Cgd (1+gmRL) = 5 × 10-12 + 2 ×10-12 (1 + 4×10-3 × 13.33 × 103) = 113.64 pf
fH = 1/(2π × Cin × Rsig) = 1/(2 × π × 113.64 × 10-12 × 100) = 14 MHz
BW = fH – fL; as fH >> fL; BW = fH = 14 MHz
Q2. Explanation:
Gain, AM = −(RG/(RG+RSIG)) × gm × (rds || RD)
= −(100 / (100+100)) × 4 × 10-3 × ( (40 × 103) || (20 × 103) ) = −26.67
Q3. Explanation:
𝜕𝐼𝐷 2𝐼𝐷𝑆𝑆 𝑉𝐺𝑆
𝑔𝑚 = = (1 − )
𝜕𝑉𝐺𝑆 |𝑉𝑃 | 𝑉𝑃
Maximum value of gm occurs when VGS = 0
2IDSS 2 × 10
𝑔𝑚max = = = 6.67 mS
|VP | 3
Q4. Explanation:
ID = IDSS (1-VGS/VP)2 = 10(1-3.5/5)2 = 0.9 mA
Q5. Explanation:
Working of a JFET can be explained as modulation of the channel conductance by an electric field
perpendicular to the channel.
Q6. Explanation:
In a BJT based differential amplifier, the allowable range of VCM is determined at the upper end by
Q1 and Q2 leaving the active mode and entering saturation mode.
Q7. Explanation:
fH and fL are the frequencies at which the gain drops by 3dB below its value at midband.
Q8. Explanation:
The current carrying capabilities of a JFET can be increased by increasing the value of I DSS, which is a
function of transistor’s width.
Q9. Explanation:
For a perfect matched differential pair, the common mode gain should be zero and CMRR should be
infinite.
Q10. Explanation:
The input stage of every op-amp is a differential amplifier.
