A Survey and Analysis on SoC Platform Security in

ARM, Intel and RISC-V Architecture

Geraldine Shirley Nicholas, Yutian Gui, Fareena Saqib
Dept. of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, North Carolina
[email protected], [email protected], [email protected]

Abstract— Modern heterogeneous computing including IoT building trust between the system and the firmware before the
devices and Networks deliver optimized and enhanced execution of the application by providing authentication and
performance along with high speed but rely on an increased validation. Device Enrollment, Attestation, and key exchanges
number of components to achieve the desired results. The design compose a chain of trust in Secure Boot.
productivity for hardware accelerators with machine learning
Trusted Execution Environment (TEE) is an isolated
platforms for various application has significant progress on
system-on-chip architectures. Most of these technologies provide execution environment providing security features where the
the desired performance, however, there is always a tradeoff software and the data is protected through isolation [1]. The
between security and performance. The major role in developing ARM TrustZone based TEE technology provides a
frameworks for hardware security attacks depends on the IP and methodology to isolate security-critical components in a system
system architecture. RISC-V provides a platform for custom [2]. Intel Software Guard Extensions (SGX) enclave is
implementation of security extensions when compared to other supported in modern processors to protect the privilege levels
traditional architectures. This paper provides a brief survey of by certain authorized functions [3]. Some other architectures
different hardware/software security attacks and summarizes a for security-critical applications are AMD Platform Secure
comparison of security features in RISC-V and other traditional
Processor, AMD Memory Encryption Technologies, and Intel
architectures along with security extensions that can be achieved
by RISC-V. Management Engine (ME), Open Portable TEE, and different
Platform Security Architectures (PSA). Though these
Keywords—RISC-V, ARM TrustZone, Intel SGX, Trusted traditional architectures provide a secure environment to a
Execution Environment (TEE) certain level, they fail to ensure isolation due to the separation
of different stacks of libraries.
I. INTRODUCTION RISC-V, an open-source architecture provides the platform
Electronic systems in emerging technology are susceptible to implement different levels of security in a system unlike the
to several security threats. Any active device connected to a SoC with 3PIP proprietary architecture and integration of
network is vulnerable to Firmware and Hardware attacks. securing the system. RISC-V Multizone Security by Hex Five
Firmware attacks involve different components and techniques provides a hardware-enforced software defined separation with
that are not present on traditional software-based attacks. Some multiple TEEs [4]. With the benefits of RISC-V being open-
of the firmware-level threats today are network attacks, Denial source, especially in the security context, different modules can
of Service, Trojan insertion etc. These attacks play a major role be implemented to secure the system from any kind of attacks
in the system components, wherein an adversary takes control [5].
over the whole system by exploiting vulnerabilities in the This paper focusses on the major threats in an SoC Design
system. In terms of hardware attacks, the SoC designs must be and Architectural Platform and points out the different features
protected from any unauthorized access. Some of the threat and vulnerabilities present in the ARM TrustZone and Intel
sources are IC supply chain, side-channel attacks, reverse SGX platforms. Finally, it provides a solution for security
engineering, cloning etc. enhancement using RISC-V architecture.
For an SoC platform with different levels of abstraction, the
security vulnerabilities of that system must be determined to II. THREAT MODEL
develop a secured platform. Key factors of SoC Platform Most of the implementations aim at securing only the firmware
Security are 1) Root of Trust, 2) Secure Boot, and 3) Trusted and data in critical applications. However, an adversary can
Execution Environment (TEE) to run the system. In the find a link through other backdoor channels to penetrate the
connected world, root of trust is a set of modules with different system. This can be done through a micro-architectural event of
security features that are trusted by the system, to monitor the the hardware, privileged software, or physical hardware
functionality and provide secure authentication with protection probing. Considering some of the reference models for security
to each component in the system along with securing the data and challenges in the SoC Design and Architectural Platform,
and resources by executing secure algorithms and functions. A four major types of scenarios are reviewed.
programmable hardware-based root of trust design offers the i. Insertion of Malware/Unwanted Application gaining
most efficient secured system. Secure Boot on the other hand is access: In a connected network, the adversary can
a mechanism that can be used for the integrity of the firmware, insert a hidden functionality that can track the data and

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 critical information or one that gets triggered to deliver implementation of the TEE standard. The intellectual property
disruptive outcomes. This can be achieved using cores are partitioned into secure and non-secure world. Figure 2
system software privilege levels. In addition, shows the ARM TrustZone implementation consisting of the
malicious modification to the circuit can be done by core along with different units. The TrustZone Memory Adapter
bypassing the security fence of the system. (TZMA) and TrustZone Address Space Controller (TZASC) are
used to provide partitions between the memory and peripheral
ii. Side-channel attacks: It is one of the most used units for both the worlds. A detailed description of the ARM
security exploitation methods, to obtain information TrustZone and building a secure system using TrustZone
Technology is provided in [7]. Hardware Isolation is achieved
on crypto engines running in the system through
by the ARM TrustZone, where separation in the model secures
communication channels. In this method, the
the critical data but in modern design, the system tends to
adversary can reverse engineer the functions to gain enlarge with large stacks of libraries, and optimized functions.
access to the system and network by monitoring the Hence, it fails in the design point of modern security systems.
power consumption or the electromagnetic fields
associated with the hardware.
iii. Supply Chain Attacks: Globalized IC supply chain can
result in malicious design modification or IP theft
through reverse engineering [6]. In the software
supply chain attacks, an unsecured network or
infrastructure is targeted, where malicious code can
compromise the build tools.
iv. Network Attacks: Denial of Service in a distributed
network result in bridging through the system and
gaining access over it. Figure 1 illustrates the different
security challenges in a connected network.

Fig. 2. ARM TrustZone Implementation

This model is vulnerable to cache-based side-channel attacks.

Extraction of keys from any crypto engines running in the secure
world is possible by compromising the non-secure world OS or
by tracking the power or EMF signals during key exchanges
between the two worlds [8]. Malicious modification of the
secure IP, denial of service by prohibiting access to any secure
IP, resource denial, port attack, etc. are some of the hardware
attacks performed on the ARM TrustZone in Zynq-7010 SoC
platform [9]. Configuring the NS bit along the AXI bus in two
different worlds is simple and effective but it becomes difficult
Fig. 1. Security Challenges in a Connected Network to manage the structure in a multi-core environment. Also,
additional security enforcements are to be incorporated for
Most of the traditional architectures have limited capability to optional memory controller present outside the Cortex-M
implement security features necessary to secure devices from TrustZone Architecture.
the above-mentioned attacks. The main reason for this is the B. Intel SGX
lack of flexibility as the developers of proprietary architectures
do not offer security enhancements due to the associated Intel SGX offers enclave memory access semantics and
performance tradeoffs. RISC-V, on the other hand, provides protection of ad dress mappings of the application [10]. The
enclaves are a region of memory, protected from any access or
this flexibility to customize the design of a system with
modifications. Encrypted and decrypted on the fly, these
reconfigurability and system security.
enclaves are hardware isolated trusted environments. Figure 3
III. SECURITY MODELS, FEATURES AND VULNERABILITIES shows the basic operation done in the SGX Model. An untrusted
application invokes a trusted function inside the enclave which
A. ARM TrustZone cannot be accessed by any application. Integrity violation from
TEEs secure the data from unauthorized access by isolating software attacks, confidentiality of the code with isolation can
the secured and non-secured applications. ARM TrustZone is an be achieved by this model. The Processor Reserved Memory

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 (PRM) holds the enclave page cache and is protected from any are achieved by different RISC-V security implementations
non-enclave memory accesses. The downside of this model is, module.
the enclave gains full access to the entire address space of the
untrusted application, which makes it vulnerable to enclave One among them is Sanctum: Minimal Hardware
malwares. Extensions for strong Software Isolation, implemented with
Rocket RISC-V core, is a strong provable isolation module that
protects against different software attacks related to memory
access patterns [13]. The microarchitectural state, caches, data
structures managed by the OS along with memory and
interrupts are protected. Privileged enclave and signing enclave
can invoke a secure inter-enclave service for attestation. Figure
4 shows the basic software stack in the Sanctum Model with
different modes of operation.

Fig. 3. SGX Model

Fig. 4. Software stack in the Sanctum Model
Since the enclave uses the same cache architecture, it is also
vulnerable to cache-based side-channel attacks. Fine-grained RISC-V MultiZone Security by HEX-Five provides a
software-based side-channel attacks were targeted on co-located trusted environment to shield critical functionality from
SGX enclaves to extract the RSA private keys [11]. Though untrusted components with the freedom to multi-source open
most of the modern Intel processors feature Hyper-threading, source software’s and third-party libraries [14]. The main
SGX does not prevent it, causing malicious software to execute feature in this model consists of equal memory-mapped
system threads. resources per zone with multi-tasking functionalities. Similar to
By gaining the enclaves memory access patterns, any critical the previous model, the MultiZone takes the advantages of
data can be extracted. Intel-specific architectural and RISC-V privilege levels and offers a platform to compile and
microarchitectural details with SGX’s security features are link each zone separately with its own protected features.
summarized in [12]. It is also impossible to reason about SGX’s Keystone based TEEs on unmodified RISC-V hardware is
security features as they are not publicly available. Therefore, to another framework for building customizable TEEs [15]. This
develop a trust model by customizing the TEEs involves the provides a new programmable layer and isolation primitives
provider’s architectural modification which requires proprietary below the untrusted code with decoupled resource
rights. Bridging the support for more than one hardware- management. Each layer is independent with secure abstraction
enforced isolated domain is not possible with the traditional awareness to make it compatible with all the existing privilege
architectures. levels.
To restrict such vulnerabilities, a hardware/software-based In addition, a hardware approach using hardware
co-design resilience model must be implemented to provide accelerators compatible with RISC-V architecture for memory
maximal protection to the system from any kind of attacks. protection is designed for the Keystone Framework [16]. This
design proves that RISC-V architecture is structured in a way
C. RISC-V Implementations that is compatible and user friendly with numerous open-source
An open-source framework for building a customizable frameworks. Designing a security extension for a model with
multi-domain Trusted Execution Environment is achieved by RISC-V architecture helps in implementing multi-layered
RISC-V for various applications. RISC-V has different security protection against different attacks. The limitations in
privilege modes to operate and can be configured easily to Keystone was enhanced by this model by adding security
manage the TEE. The physical memory protection provided by features to the existing model which is impossible in traditional
this architecture is used for authenticating the execution of architectures.
trusted nodes. Integration of hardware cryptographic Existing RISC-V TEEs which provide different levels of
accelerators, key management, and security extensions are protection but are vulnerable to side-channel attacks can be
made simple using available open-source frameworks. Multi- improvised to a resilient model with the open-source features
threaded enclaves with memory-mapped resource protection available and by implementing different countermeasures in the
existing framework. Table 1 provides RISC-V compatible

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 TABLE I

Threat Models RISC-V compatible countermeasure models

Cache-Timing Attacks Transparent Hardware-Protection Layers with memory access leakage protection

Side-Channel Attacks Core hardened resilient models with hardware Accelerators and virtual TEEs

Denial of Service Attacks Information flow tracking models tracking the flow of the data to protect memory
corruption and mitigate DoS attacks by attestation models [18]

Malware Insertion Multilayer camouflaged secure boot for SoCs along with data tracking models [17]
Supply Chain Attacks Logic Obfuscation with SAT attack resilient model for the SoC platform

countermeasures by taking into consideration the possible (VLSI-SoC), Abu Dhabi, 2017, pp. 1-6, doi: 10.1109/VLSI-
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