2021 Ivannikov Memorial Workshop (IVMEM)

Survey of Open-source Flows for

Digital Hardware Design
Mikhail Chupilko Alexander Kamkin Sergey Smolov
Ivannikov Institute for System Ivannikov Institute for System Ivannikov Institute for System
Programming of the RAS Programming of the RAS Programming of the RAS
Plekhanov Russian University of Plekhanov Russian University of Plekhanov Russian University of
Economics Economics Economics
2021 Ivannikov Memorial Workshop (IVMEM) | 978-1-6654-2327-4/21/$31.00 ©2021 IEEE | DOI: 10.1109/IVMEM53963.2021.00008

Moscow, Russia Lomonosov Moscow State University Moscow, Russia

[email protected] Moscow Institute for Physics and [email protected]
Technology
Higher School of Economics
Moscow, Russia
[email protected]

Abstract — This paper considers open-source tools for the netlist. Reverse construction of the netlist from the layout is
logical-synthesis and place-and-route hardware design stages. used here [1]. LVS makes sense only for ASICs.
Several flows (CADs), including qFlow, OpenLANE, Coriolis,
VTR, and SymbiFlow, have been described. For experimental Proprietary tools support all the steps of the hardware
evaluation of these flows, two RISC-V implementations have design process and are used for development of almost all
been used: schoolRISCV and PicoRV32. The results show that electronics nowadays. However, there are some open-source
open-source flows are capable to produce physical layouts for toolkits that are capable either to cover some of the mentioned
realistic examples. At the same time, commercial CADs allow stages or to support the entire process. The latter is referred to
generating more effective designs in terms of clock frequency. as open-source computer-aided design systems (CADs).
Keywords — computer-aided design, open source, digital The rest of the paper is organized as follows. Section II
hardware, microprocessor, FPGA, ASIC, RISC-V, qFlow, reviews existing open-source CADs, both for ASICs and
OpenLANE, Coriolis, VTR, SymbiFlow FPGAs. Section III outlines RISC-V implementations
(schoolRISCV and PicoRV32) chosen for experimenting with
I. INTRODUCTION the CADs. Section IV is devoted to the evaluation of the
The typical process for digital hardware design includes CADs. Section V concludes the paper.
the following stages: (1) logic synthesis from an RTL model
II. OPEN-SOURCE CADS
to the technology-mapped netlist; (2) place and route; (3)
static timing analysis (STA); (4) physical layout generation. The main task of CADs being considered here is to
elaborate an RTL model and to get either the GDS II layout or
The input for the first stage is an RTL model written in the FPGA bitstream. This paper observes five open-source
Verilog or VHDL. The logic synthesizer elaborates the model, CADs: three of them are for ASICs (qFlow, OpenLANE, and
optimizes it, and, using a certain technology cell library, Alliance/Coriolis), and two of them are for FPGAs (VTR and
transforms into the gate-level netlist. On the second stage, the SymbiFlow).
gates (cells) from the netlist are mapped to the resources of an
FPGA or floorplanned on a future ASIC; the nets between the A. qFlow
cells are routed (first, globally, and then in detail). The third qFlow 1.4.96 [3] is a GPL-licensed [4] CAD aimed at
stage is aimed at checking whether the placed-and-routed generating GDS II layouts for RTL models written in Verilog.
circuit satisfies the given clock frequency constraints. If the This CAD was initially developed in 2013 by R. Timothy
constraints are met, the physical layout is generated. Edwards. The last version was issued on 10.06.2021. qFlow
The layout for FPGAs is represented as a bitstream that uses some external tools (e.g., Magic, graywolf, and Yosys)
defines the functionality of the logic elements (lookup tables, and consists of utilities that launch those tools and convert
LUTs) and the connections between them. As for ASICs, the hardware representations. Each of the external tools is
layout (represented in terms of planar geometric shapes in distributed under its own license (not necessarily GPL).
GDS II [2]) should proceed through design rule checking Let us consider the tools used by qFlow at each stage of
(DRC) [1]. DRC shows whether the layout is technologically the design process (see Fig. 1) and tools for LEC/LVS.
correct and can be used by a semiconductor foundry for ASIC
fabrication. 1. Logic synthesis: Yosys [5] or Odin II [7] (both use
ABC [6] for logic optimization). The result is a netlist
While obtaining different representations of a hardware in BLIF [8] format.
design, there arises a problem of checking their equivalence.
There are two approaches. 2. Place and route: graywolf [9] for the initial
placement and global routing; qrouter [10] for the
1. Logic equivalence checking (LEC) is used to verify detailed routing. To connect them, graywolf’s
correspondence between two logical models (e.g., between an resulting files are translated into Design Exchange
RTL model and the corresponding netlist) [1]. Format (DEF) [11] — an open format for layout
2. Layout vs schematic (LVS) is used to verify whether description proposed by Cadence — by an auxiliary
the (optimized) physical layout is equivalent to the original script. qrouter is a simple restricted detail router that
does not scale to complex state-of-the-art designs.

978-1-6654-2327-4/21/$31.00 ©2021 IEEE 11

DOI 10.1109/IVMEM53963.2021.00008
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 Fig. 1. The qFlow 1.1 structure

3. STA: OpenSTA [12] or vesta [13].

4. Layout generation/DRC: Magic [14] (facilitates
SPICE [15] to model electrical characteristics of the
chip under design). Fig. 2. The OpenLANE structure

5. LEC/LVS: Yosys for LEC; Netgen [16] for LVS. In general, OpenLANE looks more preferable for
industrial application than qFlow due to the relatively new cell
Summing up, qFlow implements the entire process from library (130 nm) and the modern tools for the place-and-route
Verilog to GDS II. It is distributed with IIT/OSU 2.7 180- stage. It should also be noticed that both CADs depend on
500 nm and FreePDK45 45 nm technology cell libraries [17] Yosys and ABC for logic synthesis.
and provides a user-friendly GUI to set up about 10 synthesis
parameters. It should be noticed that qFlow is an extendable C. Alliance/Coriolis
framework and can be adapted to support new tools and cell Alliance/Coriolis 2.0.1 [26] is a GPL/LGPL/Apache 2.0-
libraries. To demonstrate the qFlow abilities, its author has licensed CAD for ASIC design. It was developed at the Pierre
published the layout generation results for the Raven RISC-V and Mari Curie University in 1990-2000 years. The latest
microprocessor [18]. version was issued on 11.03.2014. Originally, Coriolis
B. OpenLANE supported the VHDL-to-GDS II flow. By migrating from the
Alliance logic synthesizer to Yosys, the CAD started
OpenLANE 03.00.48 [19] is an Apache-2.0-licensed [20] supporting the Verilog-based flow. Coriolis is also applicable
CAD that handles RTL models written in Verilog. The tool to analog- and mixed-signal hardware designs.
uses SkyWater PDK 130 nm technology cell library [21]
sponsored by Google. OpenLANE architecture is close to Let us consider how Alliance/Coriolis implements the
qFlow, and one of its authors is R. Timothy Edwards. hardware design process [27].
Development started quite recently, in 2020, and there is no
stable version available. The last version is 03.00.48 dated 1. Logic synthesis: Alliance (for VHDL) or Yosys (for
09.09.2021. As qFlow, OpenLANE utilizes different external, Verilog; uses the nsxlib cell library [28] and ABC).
which may be distributed under their own licenses. The result is stored in LGPL-licensed [29] Hurricane
database [30] in VST format.
Here is the list of the tools used by the CAD (see Fig. 2).
2. Place and route: Etesian [31] for placement;
1. Logic synthesis: Yosys. Katana [32] for global and detailed routing (uses
BSD-licensed FLUTE tool [33]). The result is kept in
2. Place and route: OpenROAD [22] (includes several AP format [34].
tools for the placement and global routing) and
TritonRoute [23] (for the detailed routing). 3. STA: commercial HiTas [35] (works with VST files
extracted from the AP model by the cougar tool).
3. STA: OpenSTA.
4. Layout generation/DRC: s2r [36] for layout
4. Layout generation/DRC: Magic or KLayout [24]. generation (processes the AP model and produces the
GDS II file); DRuC [37] for DRC.
5. LEC/LVS: Yosys for LEC; Netgen for LVS.
5. LEC/LVS: cougar for converting the AP model to the
OpenLANE and qFlow apply similar sets of external
VST format; lvx for LVS; Yosys or GHDL for LEC.
tools. The major differences are that the former uses
OpenROAD (instead of graywolf), TritonRoute (instead of It should be noticed that Coriolis supports the OpenAccess
qrouter), and SkyWater PDK (instead of IIT/OSU 2.7 and conception [38] proposed by Cadence; namely, it can import
FreePDK45). OpenLANE has been used for production of 40 place-and-route information from LEF (Library Exchange
chips under the Open MPW Shuttle Program sponsored by Format) and DEF (Design Exchange Format) [11] files.
Google [25]. Those designs include Caravel_RISCV_OSU There are some examples of applying Alliance/Coriolis to
and Softshell SoCs with RISC-V cores. industrial-scale projects, including the StaCS microprocessor
(875 000 transistors) and 1 GHz IEEE Gigabit HSL Router
(400 000 transistors). At the same time, the CAD developers
warn that Coriolis is not suitable for technologies below
130 nm.

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 Summing up, Alliance/Coriolis had been a unique open- proprietary tools as Vivado [49], ISE [50], and
source CAD for many years until the development of qFlow Quartus [51]).
in early 2010s was started. The CAD is rather self-sufficient;
the only external tool is Yosys. Besides OpenFPGA, the SymbiFlow community is
developing a variety of ISC-licensed bitstream generators.
D. VTR and SymbiFlow There are Project IceStorm [52] (for Lattice iCE40), Project
VTR (Verilog-to-Routing) 8.0.0 [39] is an MIT- Trellis [53] (for Lattice ECP5), Project Oxide [54] (for Lattice
licensed [40] CAD [42] for FPGAs that uses FASM (FPGA Nexus), Project Apicula [55] (for Gowin LittleBee), and
Assembly) format [41] to represent the resulting design. VTR Project X-Ray [56] (for Xilinx’s 7 Series).
developers recommend using their CAD as a part of the Summing up, although VTR and SymbiFlow allows
SymbiFlow CAD (see below). The core of VTR is the VPR generating bitstreams for some modern FPGAs, these CADs,
(Versatile Place and Route) tool [43] having been developed are hardly applicable to complex hardware designs. In [57],
since mid-1990s. VTR itself has been developed since 2010s where SymbiFlow is compared with commercial CADs, there
with the most recent version dated 24.03.2020. is a recommendation to improve SymbiFlow’s place-and-
Let us consider how VTR generates FPGA bitstreams (see route algorithms. The authors showed that SymbiFlow and
green-colored part of Fig. 3). Quartus demonstrate comparable results in terms of FPGA
resource usage when using Intel Stratix IV (500 000 LUTs).
However, for Xilinx Artix-7 (50 000 LUTs), a design
generated by SymbiFlow requires twice as much resources
than one being generated by Vivado.
III. RISC-V MICROPROCESSOR EXAMPLES
RISC-V [58] is an open instruction set architecture that
allows designing microprocessors of various complexity. To
evaluate open-source CADs, we have selected two RISC-V
implementations written in Verilog. The first one is
schoolRISCV [59], a tiny (about 1 600 lines of code) MIT-
licensed core that supports some RISC-V instructions (ADD,
OR, SRL, SLTU, SUB, ADDI, LUI, BEQ, and BNE),
without pipeline but with an instruction memory and a
registry file. The second one is PicoRV32 [60], a size-
optimized (about 5 400 lines of code) core that implements
the RV32IMC instruction subset.
Fig. 3. The VTR structure IV. EVALUATION
1. Logic synthesis: Odin II or Yosys (both use ABC). A. Experiments
2. Place and route: VPR. The result is a FASM model We have applied qFlow, OpenLANE, Coriolis, and
(with known FPGA resources, power consumption, VTR/SymbiFlow to synthesize the GDS II layout for the
and timing characteristics). schoolRISCV core. All experiments have been done on a
machine with Intel Core i7-8700 3.2 GHz CPU, 32 Gb RAM
3. LEC: Yosys. and Ubuntu 20.04 OS. The only exception is Coriolis: it does
not work on Ubuntu 20.04; a virtual machine with Ubuntu
18.04 and 8 GB RAM has been used.
The results are represented in Table I, which covers
qFlow, OpenLANE, and Coriolis. It should be noticed that
VTR failed to handle schoolRISCV due to limitations of the
Verilog subset supported by Odin II. Also, we did not manage
to obtain a bitstream in a reasonable time by using
SymbiFlow.
Let us return to qFlow, OpenLANE, and Coriolis. For
Fig. 4. Tools used in SymbiFlow each of the CADs the following technology cell libraries have
been selected: OSU350 (350 nm) for qFlow; SKY130 (its
SymbiFlow [44] is an ISC-licensed [45] CAD having been fd_sc_hd subversion, 130 nm) for OpenLANE; symbolic
developed since 2018. cmos45 and real nsxlib (130 nm) for Coriolis. Each CAD uses
Here is how SymbiFlow generates bitstreams (see Fig. 4). Yosys 0.9 for logical synthesis, which, in turn, utilizes ABC
for technology mapping.
1. Logic synthesis: Odin II or Yosys (for Verilog); Table I shows the number of logical cells after ABC
Verific [46] for VHDL. execution. It has been found out that OpenLANE applies
2. Place and route: VTR or nextpnr [47] (both produce Yosys’s flattening option to simplify the RTL model before
a FASM model to be transformed into the bitstream logical synthesis, whereas qFlow and Coriolis apply the same
by the OpenFPGA open-source tool [48] or by such flattening option after the logical synthesis stage. To make
the results comparable, we have modified qFlow and

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 Coriolis’s scripts to call Yosys in a way OpenLANE does it. TABLE II. RESULTS OF LOGIC SYNTHESIS BEFORE TECHMAP
It results in a significant reduction of time (from 30-60 to 1-
Cell type Coriolis OpenLANE qFlow
2 minutes for the entire process) and the number of cells
$_ANDNOT_ 227 150 213
(from 5 000-10 000 to 500-1 000).
$_AND_ 44 28 28
TABLE I. EXPERIMENTS WITH OPEN-SOURCE CADS $_DFFE_PN0P_ 33 1 1

Parameters and results $_DFFE_PP_ 64 64 64

CADs
qFlow OpenLANE Coriolis $_DFF_PN0_ 30 30 30
Technology, nm 350 130 130 $_DFF_P_ 20 10 10
Cells (after ABC’s Techmap) 567 746 470 $_MUX_ 108 221 93
Area, um 2
119 000 24 500 73 000 $_NAND_ 87 41 73
Frequency, MHz 312 171 434 $_NOR_ 77 77 77
$_NOT_ 6 4 5
To gather the data presented in Table I, information from $_ORNOT_ 52 20 52
different sources has been used. For qFlow, it is known from $_OR_ 128 120 120
the DEF file that the die area is 40 960 x 29 000 units with $_XNOR_ 38 38 38
parameter “units distance micros” being equal to 100. The $_XOR_ 144 113 113
case of OpenLANE is similar: 151 275 x 161 995 units with
Total 1058 917 917
parameter “units distance micros” being equal to 1 000. This
is significantly less than in qFlow, which can be explained by
TABLE III. LOGIC SYNTHESIS RESULTS (QFLOW)
using the different technology (130 nm). For Coriolis, the die
area, according to the AP file, is 270 000 x 270 000 nm. The Parameter/Cell name Value
clock frequency is derived from the longest path information Total number of logical cells 567
provided by the STA checkers: OpenSTA (for qFlow and AND2X2 13 DFFSR 31 NOR3X1 2
OpenLANE) and XiTas (for Coriolis). The data arrival times AOI21X1 12 INVX1 52 OAI21X1 26
for qFlow, OpenLANE, and Coriolis are 3.2 ns, 5.84 ns, and
AOI22X1 1 NAND2X1 66 OAI22X1 21
2.3 ns respectively.
The numbers of logical cells before the technology BUFX2 95 NAND3X1 109 OR2X2 3
mapping are shown in Table II; the post-mapping statistics is DFFPOSX1 74 NOR2X1 61 XNOR2X1 1
represented in detail in Tables III, IV, and V. It should be
noticed that after the logical-synthesis stage the design may TABLE IV. LOGIC SYNTHESIS RESULTS (OPENLANE)
require additional elements, e.g. filler cells (say, 1 976 Parameter/Cell name Value
different “decap” and “fill” cells in case of OpenLANE; Total number of logical cells 746
2 722 cells in total after the place-and-route stage).
a21bo_2 1 and3_2 6 mux4_1 32 o22a_2 28
The layout produced by qFlow is shown on Fig. 5. It is
a21boi_2 2 and3b_2 1 nand2_2 2 o22ai_2 2
very simple and has a regular structure. Fig. 6 represents the
result of OpenLANE. (Setup files were taken from the a21_oi_2 16 and4b_2 2 nor2_2 10 o2bb2a_2 7
PicoRV32 [59] example included into the CAD distribution.) a22o_2 28 buf_1 65 nor2b_2 1 o2bb2ai_2 3
The layout produced by Coriolis is shown on Fig. 7. (Setup a22bb2o_2 1 buf_2 1 nor3_2 3 o31a_2 5
files were taken from the VexRiscv/cmos45 [61] example a2bb2oi_2 7 conb_1 97 o2111a_2 1 o32a_2 2
from alliance-check-toolkit [62].) Note that DRuC returned a2bb2oi_2 7 dfrtp_2 31 o21a_2 21 or2_2 23
four DRC errors for the resulting GDS file. On the contrary, a31o_2 8 dfxtp_2 74 o21ai_2 15 or3_2 14
qFlow and OpenLANE successfully passed the checking.
a31oi_2 2 inv_2 69 o21ba_2 1 or3b_2 7
B. Analysis a32o_2 2 mux2_1 125 o21bai_2 7 or4_2 5
For schoolRISCV, OpenLANE has shown the smallest and2_2 2 mux2_2 1 o221a_2 8 or4b_2 1
area (24 500 um2) and the worst estimated clock frequency
(171 MHz). The first result is quite predictable because TABLE V. LOGIC SYNTHESIS RESULTS (CORIOLIS)
OpenLANE utilizes the most advanced technology (130 nm)
among the competitors. The second result requires further Parameter/Cell name Value
investigation: it can be caused either by ineffective routing Total number of logical cells 470
algorithms or by pessimistic STA estimates. a2_x2 14 mx3_x2 1 no2_x1 40 oa2a22_x2 6
The results achieved by the open-source CADs have also a3_x2 1 na2_x1 9 no3_x1 6 oa2a2a23_x2 31
been compared with the ones [63] produced by a proprietary a4_x2 4 na3_x1 11 no4_x1 5 oa2ao222_x2 1
framework VSDFLOW [64]. For these experiments, the an12_x1 7 na4_x1 9 noa22_x1 4 on12_x1 3
PicoRV32 core has been used; the results are represented in ao22_x2 2 nao22_x1 8 nxr2_x1 25 sff1_x4 84
Table VI. buf_x2 62 nao2o22_x1 1 o2_x2 4 sff1r_x4 63
inv_x1 15 nmx2_x1 9 o4_x2 1 xr2_x1 13
mx2_x2 1 nmx3_x1 1 oa22_x2 29

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 TABLE VI. PICORV32 SYNTHESIS

Characteristics
CAD Technology, Frequency,
Cells
nm MHz
VSDFLOW 180 13 826 378

OpenLANE 130 14 840 24

As it can be seen from the table, the results are similar in

terms of the supported technology and the number of cells.
The most significant distinction is in the operating frequency.
VSDFLOW demonstrates 15 times higher frequency than
OpenLANE.

Fig. 5. The layout of schoolRISCV produced by qFlow V. CONCLUSION

In this paper, we have considered open-source CADs for
digital hardware design (qFlow, OpenLANE, Coriolis, VTR,
and SymbiFlow) and compared them by using tiny RISC-V
cores as examples (schoolRISCV and PicoRV32). The results
of the experiments have shown that OpenLANE produces
layouts with the smallest area and the lowest frequency. The
comparison with a commercial CAD (VSDFLOW) has
demonstrated that the latter allows generating more effective
designs in terms of clock frequency.
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