Adder Subtractor DLD
Adder Subtractor DLD
Adder Subtractor DLD
Combinational Circuits :
These circuits are developed using AND, OR, NOT, NAND, and NOR logic gates.
A combinational circuit consists of input variables and output variables. Since these
circuits are not dependent upon previous input to generate any output, so are
combinational logic circuits.
A combinational circuit can have an n number of inputs and m number of outputs.
In combinational circuits, the output at any time is a direct function of the applied
external inputs.
. Sequential circuits:
A sequential circuit is specified by a time sequence of inputs, outputs, and internal
states.
The output of a sequential circuit depends not only on the combination of present
inputs but also on the previous outputs.
Unlike combinational circuits, sequential circuits include memory elements with
combinational circuits. Some examples are counters and shift registers.
Inputs Outputs
A B C (Carry) S (Sum)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Draw K-maps using the above truth table and determine the simplified Boolean
expressions-
Limitation of Half Adder-
Inputs
Outputs
A B Cin Cout (Carry) S (Sum)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
N-bit Parallel Adders
Parallel adder is a binary adder circuit implemented to add two binary number
having N-bits (for example, to add 4-bit binary numbers, we use 4- bit
parallel adder, and so on).
As its name implies, the parallel adder is a digital combinational circuit that
adds two binary numbers in parallel form and generates the arithmetic sum
of those binary numbers in parallel form.
As we already mentioned above that a full adder can perform addition of only
two one-bit binary numbers consisting of two input bits and one input carry
bit, i.e. addition of three bits.
But in actual practice, we have to add such binary numbers whose length is
more than one bit. To add such binary numbers, we use parallel binary adder
which is capable of adding the two binary numbers of any bit length such as
4-bit, 5-bit, etc.
From the block diagram of the N-bit parallel adder, it can be seen that the
carry output from each full-adder is connected to the carry input terminal of
the next higher level full-adder in the chain.
The number of full-adder to realize a parallel adder is
determined from the number of bits in the two binary
numbers to be added.
Let-
Calculation of S0–
S0 = A0 ⊕ B0 ⊕ Cin
S0 = 1 ⊕ 0 ⊕ 0
S0 = 1
Calculation of C0–
S1 = A1 ⊕ B1 ⊕ C0
S1 = 0 ⊕ 1 ⊕ 0
S1 = 1
Calculation of C1–
Calculation of C2–
Calculation of S3–
S3 = A3 ⊕ B3 ⊕ C2
S3 = 0 ⊕ 1 ⊕ 0
S3 = 1
Calculation of C3–
hus finally,
Output Sum = S3S2S1S0 = 1111
Output Carry = C3 = 0
Ripple Carry Adder does not allow to use all the full
adders simultaneously.
Each full adder has to necessarily wait until the carry bit
becomes available from its adjacent full adder.
This increases the propagation time.
Type-01 Problem:
You will be given the carry propagation delay and sum propagation
delay of each full adder.
You will be asked to calculate the worst case delay of the ripple
carry adder.
Required time
= Total number of full adders till full adder producing C x X
Carry propagation delay of full adder
Required time
= Time taken for its carry in to become available + Sum propagation
delay of full adder
Type-02 Problem:
You will be given the propagation delay of some basic logic gates.
You will be told how the full adder has been implemented.
Then, you will be asked to calculate the worst case delay of Ripple
Carry Adder.
Solution-
We calculate the carry propagation delay of full adder using its carry generator
logic circuit.
It has 2 levels in the given implementation.
At first level, three AND gates operate.
All the three AND gates operate in parallel.
So, we consider the propagation delay due to only one AND gate.
At second level, OR gate operates.
We calculate the sum propagation delay of full adder using its sum
generator logic circuit.
It has only 1 level at which XOR gate operates in the given
implementation.
Now,
Sum propagation delay of full adder
= Time taken by it to generate the output sum bit
= Propagation delay of XOR gate
Problem-01:
A 16-bit ripple carry adder is realized using 16 identical full adders. The
carry propagation delay of each full adder is 12 ns and the sum
propagation delay of each full adder is 15 ns. The worst case delay of
this 16 bit adder will be ______?
A) 195 ns
B) 220 ns
C) 250 ns
D) 300 ns
SOLUTION
Time after which output carry bit becomes available from the last full
adder
= Total number of full adders X Carry propagation delay of full adder
= 16 x 12 ns
= 192 ns
Time after which output sum bit becomes available from the last full
adder
= Time taken for its carry in to become available + Sum propagation
delay of full adder
= { Total number of full adders before last full adder X Carry propagation
delay of full adder } + Sum propagation delay of full adder
= { 15 x 12 ns } + 15 ns
= 195 ns
Q. Following figure shows the implementation of full adders in a
16-bit ripple carry adder realized using 16 identical full adders. The
propagation delay of the XOR, AND and OR gates are 20 ns, 15
ns and 10 ns respectively. The worst case delay of this 16 bit
adder will be ______?
Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of full adder
= Total number of full adders X { Propagation delay of AND gate + Propagation delay of
OR gate }
= 16 x { 15 ns + 10 ns }
= 16 x 25 ns
= 400 ns
Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of full adder
= { Total number of full adders before last full adder X Carry propagation delay of full
adder } + Propagation delay of XOR gate
= { 15 x (15 ns + 10 ns) } + 20 ns
= 395 ns
Carry Look Ahead Adder-
Carry Look Ahead Adder is an improved version of the ripple carry adder.
It generates the carry-in of each full adder simultaneously without causing any
delay.
The time complexity of carry look ahead adder = Θ (logn).
C1 = C0P0 + G0
C2 = C0P0P1 + G0P1 + G1
The following formula is used to calculate number of gates required for evaluating all
carry bits-
For a n-bit carry look ahead adder to evaluate all the carry bits, it requires-
Number of AND gates = n(n+1) / 2
Number of OR gates = n