Adder Subtractor DLD

Download as docx, pdf, or txt
Download as docx, pdf, or txt
You are on page 1of 26

Combinational and Sequential Circuits

Combinational Circuits :
These circuits are developed using AND, OR, NOT, NAND, and NOR logic gates.
A combinational circuit consists of input variables and output variables. Since these
circuits are not dependent upon previous input to generate any output, so are
combinational logic circuits.
A combinational circuit can have an n number of inputs and m number of outputs.
In combinational circuits, the output at any time is a direct function of the applied
external inputs.

. Sequential circuits:
A sequential circuit is specified by a time sequence of inputs, outputs, and internal
states.
The output of a sequential circuit depends not only on the combination of present
inputs but also on the previous outputs.
Unlike combinational circuits, sequential circuits include memory elements with
combinational circuits. Some examples are counters and shift registers.

 The memory elements are circuits capable of storing binary information.


 The binary information stored in these memory elements at any given time
defines the state of the sequential circuit at that time.
 The external output of a sequential circuit depends both on the present
input and the previous output state.
 The next state of the memory elements also depends on the external input
and the present state of the external output.
 Some sequential circuits may not contain combinational circuits, but only
memory elements.
 Generally, there are two types of storage elements used: Latches, and Flip-
Flops.
 Storage elements that operate with signal levels (rather than signal transitions)
are referred to as latches; those controlled by a clock transition are flip-flops.
Half Adder-
 It is used for the purpose of adding two single bit numbers.
 It contains 2 inputs and 2 outputs (sum and carry).

Inputs Outputs

A B C (Carry) S (Sum)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0
Draw K-maps using the above truth table and determine the simplified Boolean
expressions-
Limitation of Half Adder-

 Half adders have no scope of adding the carry bit resulting


from the addition of previous bits.
 This is a major drawback of half adders.

 This is because real time scenarios involve adding the


multiple number of bits which can not be accomplished
using half adders.

To overcome this drawback, Full Adder comes into play.


Full Adder-

 Full Adder is a combinational logic circuit.


 It is used for the purpose of adding two single bit numbers
with a carry.
 Thus, full adder has the ability to perform the addition of
three bits.
 Full adder contains 3 inputs and 2 outputs (sum and carry)
as shown-

Inputs
Outputs
A B Cin Cout (Carry) S (Sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1
N-bit Parallel Adders

Parallel adder is a binary adder circuit implemented to add two binary number
having N-bits (for example, to add 4-bit binary numbers, we use 4- bit
parallel adder, and so on).
As its name implies, the parallel adder is a digital combinational circuit that
adds two binary numbers in parallel form and generates the arithmetic sum
of those binary numbers in parallel form.

As we already mentioned above that a full adder can perform addition of only
two one-bit binary numbers consisting of two input bits and one input carry
bit, i.e. addition of three bits.

But in actual practice, we have to add such binary numbers whose length is
more than one bit. To add such binary numbers, we use parallel binary adder
which is capable of adding the two binary numbers of any bit length such as
4-bit, 5-bit, etc.

We can implement an N-bit parallel adder with the help of full-adders


connected in a chain fashion. The block diagram representation of an N-bit
parallel adder using full adders is shown in Figure-2.

From the block diagram of the N-bit parallel adder, it can be seen that the
carry output from each full-adder is connected to the carry input terminal of
the next higher level full-adder in the chain.
The number of full-adder to realize a parallel adder is
determined from the number of bits in the two binary
numbers to be added.

Therefore, an N-bit parallel adder requires N full-adders


to perform the addition in parallel form. For example, a
2-bit parallel adder requires 2 full adders, 4-bit parallel
adder consists of 4 full adders, and so on.

Advantages of Parallel Adder

Some important advantages of parallel adder are listed below


 The parallel adder adds bits simultaneously.


 It makes addition of binary numbers fast.
 Parallel adder is more economical.
Ripple Carry Adder-

 Ripple Carry Adder is a combinational logic circuit.


 It is used for the purpose of adding two n-bit binary numbers.
 It requires n full adders in its circuit for adding two n-bit binary numbers.
 It is also known as n-bit parallel adder.

 RippleCarry Adder works in different stages.


 Each full adder takes the carry-in as input and produces carry-out
and sum bit as output.
 The carry-out produced by a full adder serves as carry-in for its
adjacent most significant full adder.
 When carry-in becomes available to the full adder, it activates the
full adder.
 After full adder becomes activated, it comes into operation.

Working Of 4-bit Ripple Carry Adder-

Let-

 The two 4-bit numbers are 0101 (A3A2A1A0) and 1010


(B3B2B1B0).
 These numbers are to be added using a 4-bit ripple carry
adder.

Calculation of S0–

S0 = A0 ⊕ B0 ⊕ Cin
S0 = 1 ⊕ 0 ⊕ 0
S0 = 1

Calculation of C0–

C0 = A0B0 + B0Cin + CinA0


C0 = 1.0 +0.0 +0.1 = 0
Calculation of S1–

S1 = A1 ⊕ B1 ⊕ C0
S1 = 0 ⊕ 1 ⊕ 0
S1 = 1

Calculation of C1–

C1 = A1B1 + B1C0 +C0A1


C1 = 0.1 +1.0 + 0.0
C1 = 0 + 0 + 0
C1 = 0
Calculation of S2–
S2 = 1 ⊕ 0 ⊕ 0
S2 = 1

Calculation of C2–

C2 = A2B2 + B2C1 + C1A2


C2 = 1.0 + 0.0 + 0.1
C2 = 0 + 0 + 0
C2 = 0

Calculation of S3–

S3 = A3 ⊕ B3 ⊕ C2
S3 = 0 ⊕ 1 ⊕ 0
S3 = 1

Calculation of C3–

C3 = A3B3 + B3C2 + C2A3


C3 = 0.1 + 1.0 +0.0
C3 = 0 + 0 + 0
C3 = 0

hus finally,
 Output Sum = S3S2S1S0 = 1111
 Output Carry = C3 = 0

Disadvantages of Ripple Carry Adder-

 Ripple Carry Adder does not allow to use all the full
adders simultaneously.
 Each full adder has to necessarily wait until the carry bit
becomes available from its adjacent full adder.
 This increases the propagation time.

 Due to this reason, ripple carry adder becomes extremely


slow.
 This is considered to be the biggest disadvantage of using
ripple carry adder.

Type-01 Problem:

 You will be given the carry propagation delay and sum propagation
delay of each full adder.
 You will be asked to calculate the worst case delay of the ripple
carry adder.

It is important to know the following terms-


 Carry propagation delay of a full adder is the time taken by it to
produce the output carry bit.
 Sum propagation delay of a full adder is the time taken by it to
produce the output sum bit.
 Worst case delay of a ripple carry adder is the time after which the
output sum bit and carry bit becomes available from the last full
adder.

In Ripple Carry Adder,


A full adder becomes active only when its carry in is made
available by its adjacent less significant full adder.
 When carry in becomes available to the full adder, it starts its
operation.
 It produces the corresponding output sum bit and carry bit.

Time After Which Carry Bit Cx Becomes Available-

Required time
= Total number of full adders till full adder producing C x X
Carry propagation delay of full adder

Time After Which Sum Bit Sx Becomes Available-

Required time
= Time taken for its carry in to become available + Sum propagation
delay of full adder

Type-02 Problem:

 You will be given the propagation delay of some basic logic gates.
 You will be told how the full adder has been implemented.
 Then, you will be asked to calculate the worst case delay of Ripple
Carry Adder.

Solution-

 The computation has to be done in the same manner as in Type-


01 problem.
 It’s just that in Type-02 problem, one step is increased.
 We have to first calculate the carry propagation delay and sum
propagation delay in terms of logic gates.
 Then, our problem will reduce to Type-01 problem.
Calculating Carry Propagation Delay-

 We calculate the carry propagation delay of full adder using its carry generator
logic circuit.
 It has 2 levels in the given implementation.
 At first level, three AND gates operate.
 All the three AND gates operate in parallel.
 So, we consider the propagation delay due to only one AND gate.
 At second level, OR gate operates.

Carry propagation delay of full adder


= Time taken by it to generate the output carry bit
= Propagation delay of AND gate + Propagation
delay of OR gate

Calculating Sum Propagation Delay-

 We calculate the sum propagation delay of full adder using its sum
generator logic circuit.
 It has only 1 level at which XOR gate operates in the given
implementation.

Now,
Sum propagation delay of full adder
= Time taken by it to generate the output sum bit
= Propagation delay of XOR gate
Problem-01:

A 16-bit ripple carry adder is realized using 16 identical full adders. The
carry propagation delay of each full adder is 12 ns and the sum
propagation delay of each full adder is 15 ns. The worst case delay of
this 16 bit adder will be ______?
A) 195 ns
B) 220 ns
C) 250 ns
D) 300 ns

SOLUTION

Time after which output carry bit becomes available from the last full
adder
= Total number of full adders X Carry propagation delay of full adder
= 16 x 12 ns
= 192 ns

Time after which output sum bit becomes available from the last full
adder
= Time taken for its carry in to become available + Sum propagation
delay of full adder
= { Total number of full adders before last full adder X Carry propagation
delay of full adder } + Sum propagation delay of full adder
= { 15 x 12 ns } + 15 ns
= 195 ns
Q. Following figure shows the implementation of full adders in a
16-bit ripple carry adder realized using 16 identical full adders. The
propagation delay of the XOR, AND and OR gates are 20 ns, 15
ns and 10 ns respectively. The worst case delay of this 16 bit
adder will be ______?

We consider the last full adder for worst case delay.

Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of full adder
= Total number of full adders X { Propagation delay of AND gate + Propagation delay of
OR gate }
= 16 x { 15 ns + 10 ns }
= 16 x 25 ns
= 400 ns

Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of full adder
= { Total number of full adders before last full adder X Carry propagation delay of full
adder } + Propagation delay of XOR gate
= { 15 x (15 ns + 10 ns) } + 20 ns
= 395 ns
Carry Look Ahead Adder-

 Carry Look Ahead Adder is an improved version of the ripple carry adder.
 It generates the carry-in of each full adder simultaneously without causing any
delay.
 The time complexity of carry look ahead adder = Θ (logn).

the working of carry look ahead adder is based on the principle-


The carry-in of any stage full adder is independent of the carry bits
generated during intermediate stages.

C1 = C0 (A0 ⊕ B0) + A0B0


C2 = C1 (A1 ⊕ B1) + A1B1

For simplicity, Let-


 Gi = AiBi where G is called carry generator
 Pi = Ai ⊕ Bi where P is called carry propagator

 C1 = C0P0 + G0
 C2 = C0P0P1 + G0P1 + G1

 C3 = C0P0P1P2 + G0P1P2 + G1P2 + G2

 C4 =C0P0P1P2P3 + G0P1P2P3 + G1P2P3 + G2P3 + G3


Implementation Of Carry Generator Circuits-

The above carry generator circuits are usually implemented as-


 Two level combinational circuits.
 Using AND and OR gates where gates are assumed to have any number of
inputs.
Implementation Of C2–

 The carry generator circuit for C2 is implemented as shown below.


 It requires 2 AND gates and 1 OR gate.
General Formula-

The following formula is used to calculate number of gates required for evaluating all
carry bits-

For a n-bit carry look ahead adder to evaluate all the carry bits, it requires-
 Number of AND gates = n(n+1) / 2
 Number of OR gates = n

Advantages of Carry Look Ahead Adder-

The advantages of carry look ahead adder are-


 It generates the carry-in for each full adder simultaneously.
 It reduces the propagation delay.

Disadvantages of Carry Look Ahead Adder-

The disadvantages of carry look ahead adder are-


 It involves complex hardware.
 It is costlier since it involves complex hardware.
 It gets more complicated as the number of bits increases.

You might also like