Digital

Fundamentals
Tenth Edition

Floyd

Chapter 8
Synchronous
Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education,©Upper
2008 Pearson Education
Saddle River, NJ 07458. All Rights Reserved
 A 2-bit synchronous binary counter.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-
flops are assumed to be equal).

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counters
In a synchronous counter all flip-flops are clocked
together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J J1 J
has the same count 0 2

sequence as the 3-bit C C C

asynchronous counter K0 K1 K2

shown previously. CLK

The next slide shows how to analyze this counter by writing the logic
equations for each input. Notice the inputs to each flip-flop…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Analysis of Synchronous Counters
A tabular technique for analysis is illustrated for the counter on the
previous slide. Start by setting up the outputs as shown, then write the
logic equation for each input. This has been done for the counter.
1. Put the counter in an 2. Use the new inputs to 3. Set up the next
arbitrary state; then determine determine the next state: Q2 and group of inputs from
the inputs for this state. Q1 will latch and Q0 will toggle. the current output.

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K 2 = Q0 Q1 J1 = Q0 K 1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0

4. Q2 will latch again but both Q1 and Q0 will toggle.

Continue like this, to complete the table.
The next slide shows the completed table…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Analysis of Synchronous Counters
Outputs Logic for inputs
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K 1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1

1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1
0 0 0
At this points all states have been accounted
for and the counter is ready to recycle…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
A 4-bit Synchronous Binary Counter
Q1Q0
G1 Q2Q1Q0
G2
FF0 FF1 FF2 FF3

HIGH J0 Q0 J1 Q1 J2 Q2 J3 Q3

CLK C C C C

K0 Q0 K1 Q1 K2 Q2 K3 Q3

The 4-bit binary counter

has one more AND gate Q0
than the 3-bit counter just
described. The shaded Q1
areas show where the
AND gate outputs are Q2

HIGH causing the next

Q3
FF to toggle.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decade Counter
With some additional logic, a binary counter can be
converted to a BCD synchronous decade counter. After
reaching the count 1001, the counter recycles to 0000.
This gate detects 1001, and causes FF3 to toggle on the next
clock pulse. FF0 toggles on every clock pulse. Thus, the count
starts over at 0000.
Q3
HIGH Q0
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decade Counter
Waveforms for the decade counter:
CLK 1 2 3 4 5 6 7 8 9 10

Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

These same waveforms can be obtained with an asynchronous

counter in IC form – the 74LS90. It is available in a dual version –
the 74LS390, which can be cascaded. It is slower than synchronous
counters (max count frequency is 35 MHz), but is simpler.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
A 4-bit Synchronous Binary Counter
The 74LS163 is a 4-bit IC synchronous counter with additional
features over a basic counter. It has (synchronous) parallel load, a
(synchronous) CLR input, two chip enables, and a ripple count
output that signals when the count has reached the terminal count.
Data inputs
D0 D1 D2 D3

(3) (4) (5) (6)

CLR (1) CTR DIV 16

(9)
LOAD
(10) (15)
ENT TC = 15 RCO
(7)
ENP
(2)
CLK C

(14) (13) (12) (11)

Q0 Q1 Q2 Q3
Example waveforms
Data outputs
are on the next slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
CLR
LOAD
D0
D1
Data
inputs D2

D3

CLK
ENP
ENT

Q0
Q1
Data
outputs Q2
Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
Clear Preset

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
A 4-bit Synchronous Binary Counter
The 74LS160 is a 4-bit IC synchronous BCD counter with additional
features over a basic counter. It has (synchronous) parallel load, a
(asynchronous) CLR input, two chip enables, and a ripple count output
that signals when the count has reached the terminal count.

LOAD
ENT
ENP
CLK

Q0
Example waveforms
are on the next slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Up/Down Synchronous Counters
An up/down counter is capable of progressing in either
direction depending on a control input.
UP
Q0.UP
HIGH
FF0 FF1 FF2
Q2
J J1 J2
0 Q0 Q1
UP/DOWN C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0.DOWN
CLK

Example waveforms from Multisim are on the next slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Up/Down Synchronous Counters

Q0

Q1

Q2

UP/DOWN Count up Count down

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Up/Down Counters

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Up/Down Synchronous Counters D0 D1 D2 D3 Data inputs

(15) (1) (10) (9)

The 74HC190 is a high speed 74HC190
(4) (12)
CTEN MAX/MIN
CMOS synchronous up/down D/U
(5)
(11) CTR DIV 10
decade counter with parallel load LOAD (14) (13)
CLK C RCO
capability. It also has a active
(3) (2) (6) (7)
LOW ripple clock output (RCO)
and a MAX/MIN output when the Q0 Q1 Q2 Q3 Data outputs

terminal count is reached.

D0 D1 D2 D3 Data inputs

(15) (1) (10) (9)

The 74HC191 has the same (4)
74HC191
CTEN (12)
inputs and outputs but is a D/U
(5)
MAX/MIN
CTR DIV 16
synchronous up/down binary (11)
LOAD (14) (13)
CLK C RCO
counter.
(3) (2) (6) (7)

Q0 Q1 Q2 Q3 Data outputs

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 74HC190

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 General clocked sequential circuit

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counter Design
Most requirements for synchronous counters can be met
with available ICs. In cases where a special sequence is
needed, you can apply a step-by-step design process.
The steps in design are described in detail in the text and lab manual.
Start with the desired sequence and draw a state diagram and next-
state table. The gray code sequence from the text is illustrated:
State diagram: Next state table:
000 Present State Next State
100 001 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
111 010 1 1 0 1 1 1
1 1 1 1 0 1
110 1 0 1 1 0 0
1 0 0 0 0 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counter Design
The J-K transition table lists all combinations of present
output (QN) and next output (QN+1) on the left. The inputs
that produce that transition are listed on the right.
Each time a flip-flop is clocked, the Output Flip-Flop
J and K inputs required for that Transitions Inputs
QN Q N+1 J K
transition are mapped onto a K-map.
Q0
0 0 0 X
Q2Q1 0 1 0 1 1 X
An example of 1 0 X 1
00 1 X Q2Q1 1 1 X 0
the J0 map is:
01 0 X

11 1 X Q2Q1 The logic for each input is read

10 0 X and the circuit is constructed.
J0 map The next slide shows the circuit
for the gray code counter…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counter Design

FF0 FF1 FF2

Q2
J J1 J
0 Q0 Q1 2

C C C
Q0 Q1 Q2
K0 K1 K2

CLK

The circuit can be checked with Multisim before constructing it.

The next slide shows the Multisim result…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary

Q0
Q1
Q2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 State diagram for a 3-bit Gray code counter.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Examples of the mapping procedure for the counter sequence.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Karnaugh maps for present-state J and K inputs.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Three-bit Gray code counter. Open file F09-31 to verify operation.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Cascaded counters
Cascading is a method of achieving higher-modulus counters. For
synchronous IC counters, the next counter is enabled only when
the terminal count of the previous stage is reached.
HIGH
ƒin
Counter 1 Counter 2
16 fout ƒin
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin

a) What is the modulus of the cascaded DIV 16 counters?

b) If fin =100 kHz, what is fout?
a) Each counter divides the frequency by 16. Thus the
modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Cascaded Counters

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Counter Decoding
Decoding is the detection of a binary number and can be
done with an AND gate.
HIGH

Q2
J0 Q0 J1 Q1 J2 Q2

C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

What number is decoded by

this gate?
Decoded 4
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Partial Decoding
The decade counter shown previously incorporates
partial decoding (looking at only the MSB and the
LSB) to detect 1001. This was possible because this is
the first occurrence of this combination in the sequence.
Detects 1001 by looking only at two bits

HIGH
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Resetting the Count with a Decoder
The divide-by-60 counter in the text also uses partial
decoding to clear the tens count when a 6 was detected.

CLR CTR DIV 10 CLR CLR CTR DIV 6

RCO
HIGH CTEN TC = 9 CTEN

C C
CLK To next
Decode 6 counter

TC = 59
To ENABLE
Decode 59 of next CTR
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

units tens

The divide characteristic illustrated here is a good way to obtain a

lower frequency using a counter. For example, the 60 Hz power line
can be converted to 1 Hz.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Counter Decoding

Show how to decode state 5 with an active LOW output.

HIGH

Q0 Q2
J0 Q0 J1 Q1 J2 Q2

C C C

Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

Notice that a NAND gate

was used to give the active
Decoded 5
LOW output.
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Logic Symbols
Dependency notation allows the logical operation of a
device to be determined from its logic symbol.
Common
CTR DIV 16 control
(1) block
CLR (9)
5CT = 0
D0 D1 D2 D3 LOAD M1
(15)
M2 RCO
(3) (4) (5) (6) (10)
ENT G3
(7)
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) CTR DIV 16 (15)
ENT RCO (3) (14)
(7) D0 Q0
ENP 1, 5 D [1]
(2) (4) (13)
CLK C D1 [2] Q1
(5) (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 [8] Q3
Q0 Q1 Q2 Q3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Selected Key Terms

Asynchronous Not occurring at the same time.

Modulus The number of unique states through which a
counter will sequence.
Synchronous Occurring at the same time.
Terminal count The final state in a counter’s sequence.
State machine A logic system exhibiting a sequence of states or
values.
Cascade To connect “end-to-end” as when several counters
are connected from the terminal count output of
one to the enable input of the next counter.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved