CSC159 Okt 2021 Question Set 1
CSC159 Okt 2021 Question Set 1
FINAL TEST
INSTRUCTIONS TO CANDIDATES
1. This question paper consists of three (3) parts : PART A (15 Questions)
PART B (15 Questions)
PART C (7 Questions)
2. Answer ALL questions in the Answer Booklet. Start each answer on a new page.
3. Do not bring any material into the examination room unless permission is given by the
invigilator.
ANSWER SCHEME
𝑅 = 𝐴 ∙ 𝐵̅ + 𝐵 ∙ 𝐶
A. X = OR gate, Y = AND gate
B. X = OR gate, Y = OR gate
C. X = AND gate, Y = OR gate
D. X = AND gate, Y = AND gate
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
A. 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅
(𝐴 ⊕ 𝐵)
B. ̅̅̅̅̅̅̅̅̅
𝑌 = (𝐴 ∙ 𝐵)
C. 𝑌 = 𝐴̅ + 𝐵
D. 𝑌 = 𝐴̅ ∙ 𝐵
A. 𝑅 = (𝐴 ∙ 𝐵̅) + ̅̅̅̅̅̅̅̅̅
(𝐴 ⊕ 𝐶
B. 𝑅 ̅ ̅̅̅̅̅̅̅̅̅̅̅
= 𝐴 ∙ 𝐵 + (𝐴 ⊕ 𝐶)
C. 𝑅 = 𝐴 ∙ 𝐵̅ ⊕ ̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐶)
D. 𝑅 = 𝐴 ∙ 𝐵 ⊕ (𝐴 + 𝐶̅ )
̅
4. What is the condition of three NOR gate input A, B and C that will cause the output X
in the truth table to be TRUE?
A. A=1, B=1, C=1
B. A=1, B=0, C=0
C. A=0, B=0, C=1
D. A=0, B=0, C=0
5. The sum of two hexadecimal numbers 43Ah and 5BCh in binary is _____.
9. Which of the following registers hold the actual instruction currently being executed
by the computer?
A. memory data register
B. Instruction register
C. program counter register
D. memory address register
10. Why magnetic core memory is rarely used in the modern computer environment?
A. Requires refreshment
B. Uses magnetic material
C. Erasable content
D. Slow
12. Several different methods in improving read and write operation in the memory are:
i. Multitasking
ii. Wide Path Memory Access
iii. Cache memory
iv. Pipelining
A. i and ii
B. ii and iii
C. ii, iii and iv
D. i and iv
14. “It is a capability provided by some computer bus architectures that allows data to be
sent directly from an attached device to the memory without CPU involvement”.
This statement refers to _____.
A. Bus interface
B. Channel subsystem
C. Direct Memory Access
D. Polling
15. What are the strengths of FireWire interface compared to SCSI interface?
i. Wider cable
ii. Low cost
iii. Easy to implement
iv. High speed.
A. i, iii and iv
B. ii, iii and iv
C. i and iii
D. All of the above
1. The difference between the XOR gate and the OR gate is, they (True) (False)
differ only in one input situation. When both input signals are 1,
the OR gate produces a 1 and the XOR produces a 0.
2. A three-input gate has eight possibilities (000, 001, 010, 011, (True) (False)
100, 101, 110, and 011) for input states.
3. The decimal positive value of the 2’s complement number (True) (False)
11110111 is 10.
5. The higher the memory hierarchy will result in slower transfer (True) (False)
rates.
6. DRAM memory does not require refreshing its memory (True) (False)
periodically.
10. The I/O interface and memory must be placed separately to (True) (False)
allow Direct Memory Access method works.
11. Handshaking is a process to hold and release parts of data at (True) (False)
particular times.
13. The stack is usually build following the Little Endian method. (True) (False)
14. One example of interrupt used as external event notifier is (True) (False)
when the power is cut off.
15. I/O module can be considered as the middleman between CPU (True) (False)
interface and device interface.
QUESTION 1
𝑍 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅
(𝑅 ⊕ 𝑆) + (𝑆 ∙ 𝑃̅)
(5 marks)
(5 marks)
QUESTION 2
(5 marks)
QUESTION 3
a) Convert the following numbers to the respective numbering system. Show your work.
101.625
(3 marks)
i) 23548 + 6658
(2 marks)
QUESTION 4
a) Convert 151/32 using 32-bit IEEE single precision format in hexadecimal form.
(5 marks)
b) Convert 3DE20000 IEEE single precision floating number to its decimal value.
(5 marks)
QUESTION 5
a) Define the function of Memory Address Register and Memory Data Register
(2 marks)
QUESTION 6
(6 marks)
QUESTION 7
X X X AX BX CX DX PC
0 0 0 1 0 1 0 1
a) Build the content of stack (with the related addresses) after the interruption by following
the sequence of CX, BX, AX, PC and DX. Assume that the stack content starting at the
location FFE9h.
(3 marks)
b) Continue building the stack when the following instructions are encountered.
POP BX
PUSH CX
POP AX
(2 marks)
c) What is the value of the Stack Pointer Register after POP BX and PUSH
CX?
(1 mark)
(1 mark)