ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JULY 2020, VOLUME: 06, ISSUE: 02

DOI: 10.21917/ijme.2020.0164

COMPARATIVE ANALYSIS OF VARIOUS APPROXIMATE FULL ADDERS UNDER

RTL CODES
Chinna V. Gowdar1, M.C. Parameshwara2 and Savita Sonoli3
1,3
Department of Electronics and Communication Engineering, Rao Bahadur Y Mahabaleshwarappa Engineering College, India
2
Department of Electronics and Communication Engineering, Vemana Institute of Technology, India

Abstract • Architecture level

Approximate or inexact computing is a well-established paradigm for • Gate level
designing error-tolerant applications such as image and digital signal
processing. It is an interesting area of research, especially in the • Transistor level
computer arithmetic designs. One key feature of this technique is that At the algorithmic level, the energy efficiency is achieved by
it reduces accuracy but still provides meaningful results with low power significant driven computation (SDC). In SDC, the computations
and reduced circuit complexity. This paper presents a comparative are classified as significant and non-significant. The significant
analysis of state-of-the-art approximate 1-bit full adders (AFA) for computations are performed using exact circuits and non-
inexact computation. The performance of these AFAs are compared in significant computations are performed using AC [4]-[6]. At
terms of the design metrics (DMs) such as power, delay, and area. For
a fair comparison, all AFAs under consideration have been described
architectural level, the reduction of logic complexity is achieved
in Verilog register-transfer-level (RTL) codes and synthesized using using the voltage over scaling (VOS) and algorithmic noise
Cadence’s RTL compiler. The synthesis is carried out using Cadence’s tolerance (ANT) [7]-[9]. The VOS is used to achieve low power
180 nm standard cell library. by scaling down the supply voltage below its lower bound. This
results in intermittent or time induced errors, whenever the critical
delay path is excited. This degrades the signal-to-noise (SNR)
Keywords:
performance of a system under consideration. To mitigate this
Approximate Adder, Low Power, Approximate Computing, Full Adder, problem an error control technique ANT is used. Thus, the VOS
Inexact Adder
and ANT together are used to achieve low power with required
accuracy. The reduction in logic complexity at gate level were
1. INTRODUCTION investigated in [10]-[14]. And other works discussed extensively
on reduction of logic complexity, at transistor level [15]-[20]. In
The quest to minimize the gap between CMOS technology both gate/circuit level, the logic complexity is reduced by
scaling and application computational workloads has made the eliminating some of the logic gates/transistors in the critical path
designers to look into different techniques [1], [2] one such and thus achieving the energy efficiency. In this paper, the state-
standard technique is an ‘approximate computation’ (AC). It of-the-art approximate-FAs (AFAs) have been compared in terms
exploits the error resilience of a system by trading-off the of DMs [21] such as power, delay, and area.
accuracy and performance. The common applications of an AC
Rest of this paper is organized as follows. Section 2 presents
are in multimedia, wireless communications, data mining,
related work on approximate FAs. Section 3 presents the
recognition, neuromorphic systems etc. Processing multimedia
approximate FAs. Section 4 presents the synthesis environment.
applications such as image, audio, and video are error resilient.
The section 5 presents the results and discussion. Finally, section
Since the human beings have limited perceptional capabilities,
6 concludes this work.
hence generating numerically approximate results is more
sufficient rather than accurate. This relaxation on numerical
exactness allows us to perform inexact or approximate 2. RELATED WORK
computations. The handheld multimedia devices uses the ‘Digital
Signal Processing’ (DSP) system as core to process the image and In the current state-of-the-art literature many 1-bit AFAs have
video [3]. been proposed and discussed at both gate level and transistor
level. The brief summary of these adders is as follows:
A ‘1-bit full adder’ (FA) being primitive unit of DSP block,
plays an important role to determine the overall accuracy and In [11] an AFA that approximates both Sum and Cout is
performance of a DSP system. Thus, the state-of-the-art literature presented. The gate level diagram of this AFA is shown in the
extensively focused on investigation of energy efficient DSP by Fig.1(a). It has smaller number of logic gates and shortest critical
approximating the FA to trade-off the accuracy and performance. path as compared to the conventional exact FA. Three different
gate level approximate FA were proposed in [14]. The gate level
The various works proposed in the current technical literature
representation of these 1-bit AFAs are shown in Fig.1(b)-Fig.1(d),
have discussed and presented the design of energy efficient
all these AFAs are derived by approximating both the Sum and
arithmetic blocks using AC. The energy efficiency can be
Cout. All these adders are designed using smaller number of
achieved through AC by the reduction of logic complexity at
transistors, simulated and analyzed in 45 nm technology node.
different levels of design abstraction such as:
The authors claimed that these AFAs consume less power and
• Algorithmic level have low delay.

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Table.1. Truth Table of Approximate Full Adders

Adder Outputs
Inputs EFA AFA1 AFA2 AFA3 AFA4 AFA5 AFA6 AFA7
A B Cin Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout
0 0 0 0 0 1× 0✓ 0✓ 0✓ 0✓ 0✓ 1× 0✓ 1× 0✓ 1× 0✓ 0✓ 0✓
0 0 1 1 0 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓
0 1 0 1 0 1✓ 0✓ 1✓ 0✓ 0× 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓
0 1 1 0 1 1× 0× 1× 1✓ 1× 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 0✓ 1✓
1 0 0 1 0 0× 1× 0× 0✓ 0× 0✓ 1✓ 0✓ 0× 0✓ 1✓ 0✓ 1✓ 0✓
1 0 1 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓
1 1 0 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 1✓
1 1 1 1 1 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 0× 1✓ 1✓ 1✓
Reference [12]

Adder Outputs
Inputs EFA AFA8 AFA9 AFA10 AFA11 AFA12 AFA13 AFA14
A B Cin Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout
0 0 0 0 0 0✓ 0✓ 1× 0✓ 1× 0✓ 0✓ 0✓ 0✓ 0✓ 0✓ 0✓ 0✓ 0✓
0 0 1 1 0 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 0× 0✓ 1✓ 1× 1✓ 0✓
0 1 0 1 0 0× 1× 1✓ 0✓ 0× 1× 0× 0✓ 0× 0✓ 1✓ 0✓ 1✓ 0✓
0 1 1 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 0× 0✓ 0× 0✓ 1✓ 1× 1✓
1 0 0 1 0 0× 0✓ 1✓ 0✓ 1✓ 0✓ 0× 1× 1✓ 1× 1✓ 0✓ 1✓ 0✓
1 0 1 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 1× 1✓
1 1 0 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 1✓ 0✓ 0× 0✓ 1✓
1 1 1 1 1 1✓ 1✓ 0× 1✓ 0× 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓
Reference [13,18] [14]

Adder Outputs
Inputs EFA AFA15 AFA16 AFA17 AFA18 AFA19 AFA20 AFA21
A B Cin Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout
0 0 0 0 0 1× 0✓ 1× 0✓ 1× 0✓ 1× 0✓ 0✓ 0✓ 1× 0✓ 0✓ 0✓
0 0 1 1 0 0× 1× 1✓ 0✓ 0× 1× 1✓ 0✓ 1✓ 0✓ 0× 1× 0× 1×
0 1 0 1 0 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓
0 1 1 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 0× 0✓ 1✓ 0✓ 1✓
1 0 0 1 0 1✓ 0✓ 0× 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓
1 0 1 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 0× 0✓ 1✓ 0✓ 1✓
1 1 0 0 1 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 1× 1✓ 1× 0×
1 1 1 1 1 0× 1✓ 0× 1✓ 1✓ 0× 0× 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓
Reference [10] [11] [15] [16]

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Adder Outputs
Inputs EFA AFA22 AFA23 AFA24 AFA25 AFA26 AFA27 AFA28
A B Cin Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout Sum Cout
0 0 0 0 0 0✓ 0✓ 0✓ 0✓ 1× 0✓ 0✓ 0✓ 0✓ 0✓ 0✓ 0✓ 1× 0✓
0 0 1 1 0 0× 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 1✓ 0✓ 0× 0✓ 1✓ 0✓
0 1 0 1 0 1✓ 0✓ 0× 1× 0× 0✓ 0× 0✓ 1✓ 0✓ 0× 0✓ 1✓ 0✓
0 1 1 0 1 1× 0× 1× 0× 0✓ 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 0✓ 1✓
1 0 0 1 0 0× 1× 0× 1× 0× 0✓ 0× 0✓ 1✓ 0✓ 0× 0✓ 1✓ 0✓
1 0 1 0 1 0✓ 1✓ 1× 0× 0✓ 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 0✓ 1✓
1 1 0 0 1 1× 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 1× 1✓ 0✓ 1✓ 0✓ 1✓
1 1 1 1 1 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 1✓ 0× 1✓
Reference [13] [18] [19] [20] [17] [20]

In this work the authors claimed that the carry based approximate
adders are found to be more efficient than conventional
approximate adders. The other works [15] [16] also discussed on
gate level approximate adders and discussed their merits in terms
of power and delay. The transistor level approximate adders have
been extensively studied in the works [13] [14] [18] [20]. A 5
different approximate adders have been derived by approximating
(a) the CMOS mirror adder [13] [18]. The approximation is carried
out by removing some of the transistors in the critical path. This
resulted in reduced delay and low power.

3. APPROXIMATE FULL ADDERS

The state-of-the-art AFAs are derived based on approximation
(b) of the Sum and Carry outputs of exact FA. The block diagram and
truth table of exact FA is shown in Fig.2(a) and Fig.2(b),
respectively.

(c)

(a)
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
(d) 0 1 0 1 0
0 1 1 0 1
Fig.1. Gate level approximate full adders reported in [11] [14]
1 0 0 1 0
In [12], a total 7 gate level AFAs have been proposed and used 1 0 1 0 1
in the design and analysis of approximate multipliers. All the 1 1 0 0 1
proposed approximate multipliers have been simulated and
1 1 1 1 1
synthesized using Cadence’s RTL compiler using TSMC 180 nm
standard cell library. Among the 7 proposed AFAs, the authors (b)
found that the Sum and Cout approximated adders are more power Fig.2. FA (a) Block diagram (b) Truth Table
efficient. A carry based approximate FAs were reported in [10].

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The Sum and Cout of exact FA are expressed as follows 3.3 APPROXIMATED Sum AND COUT ADDERS
Sum = A⊕B⊕Cin (1) (TYPE3)
Cout = A.B+B·Cin+A·Cin (2) The Type3 AFAs are derived by approximating both Sum as
The state-of-the-art AFAs are derived either by approximating well as Cout outputs. From the Table.1 it is found that the
the Sum or Cout or both outputs of the exact full adder (EFA). approximate adders namely AFA1 [12], AFA8, AFA10-AFA12
Depending on the output that is being approximated, in this work [13, 18], AFA15, AFA17 [10], AFA19 [17], AFA20 [15], AFA21
we classify the AFAs into 3 different types. [16], AFA22 [13], and AFA23 [18] fall under Type3.
3.1 APPROXIMATED SUM ADDERS (TYPE1) The K-map simplified Sum expression for Type3 AFAs are
tabulated in Table.3.
These AFAs are derived by approximating the Sum alone and
retaining the exact Cout as in Eq.(2). These type approximate Table.3. K-Map Simplified approximated Sum and Cout
adders are herein referred to as ‘Type1’. From the Table.1 it is
found that the approximate adders AFA2-AFA7 [12], AFA9 [13] AFA Sum Cout
[18], AFA14 [14], AFA16, AFA18 [10], AFA24, AFA25 [19], AFA1 A  B  Cin A
and AFA27-AFA29 [17] [20], all these adders fall under Type1
category. The K-map simplified Sum expressions for Type1 AFA8 A  B  Cin  A  B  Cin B+A·Cin
AFAs are listed in Table.2.
AFA10 A  B  B  Cin B+A·Cin

Table.2. K-Map Simplified approximated Sum 

AFA11 A  B  Cin  A

AFA Sum AFA12 A A

AFA2 A   B  Cin   B  Cin AFA15 A  Cin  B  Cin Cin + A·B

AFA3  A  B  C
in AFA17 A  Cin  B  Cin  A  B  Cin A  Cin  B  Cin  A  B  Cin

AFA4 A  B  A  Cin  B  Cin  A  B  Cin AFA19 Cin  A  B  A  B A·B

AFA5 A  B  Cin AFA20 Cin  A  B Cin  A  B

AFA6 A  B  A  Cin  B  Cin AFA21 B  Cin  A  Cin  A  B Cin

AFA7 B  Cin  A  Cin  A  B  A  B  Cin AFA22 B A

AFA23 Cin B  Cin  A  Cin  A  B
AFA9 A  B  A  Cin  B  Cin
AFA14 Cin  A  B  A  B 4. SYNTHESIS ENVIRONMENT
AFA16 A  B  A  Cin
The synthesis environment used to extract the DMs is shown
AFA18 A  B  A  Cin  B  Cin in Fig.3. The Verilog RTL code and TSMC 180 nm standard cell
library are used an inputs to the synthesis tool. With these inputs
AFA24 A  B  A  B
the Cadence’s RTL compiler (RC) generates gate level netlist to
AFA25 A  B  Cin  A  B  Cin extract the required DMs. For a fair comparison, all the AFAs
under consideration have been described using Verilog RTL
AFA26 A  B  Cin codes and synthesized using supply voltage, Vdd = 1.8 V.
AFA27 A  B  C
AFA28 A  B  A  Cin  B  Cin

3.2 APPROXIMATED COUT ADDERS (TYPE 2)

Fig.3. Synthesis environment used to extract the DMs
The Type 2 AFAs are derived by approximating the Cout
alone and retaining the exact Sum as in Eq.(1). From the Table.1 RTL is an acronym for ‘register transfer level’. Any
it is found that the only approximate adder that fall under this synthesizable HDL code is called RTL code. An example of RTL
category is AFA13 [14]. The K-map simplified Sum expression code that describes an AFA1 is illustrated below. In this example
for Type 2 AFA is listed in Eq.(3). the continuous assignment statements are used to describe RTL
Cout = Cin (3) code.

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module AFA1(A, B, Cin, Sum, Cout); AFA16 0.217 3691.747 3691.964 334 49.90
input A, B, Cin; AFA18 0.119 2647.841 2647.961 271 36.59
output Sum, Cout; AFA24 0.278 3153.634 3153.912 279 49.90
assign Sum = ~A|(B and Cin); AFA25 0.289 3544.190 3544.479 280 59.87
assign Cout = A; AFA26 0.341 3094.364 3094.705 331 49.90
endmodule AFA27 0.179 2871.688 2871.866 169 46.57
AFA28 0.119 2647.841 2647.961 271 36.59
5. RESULTS AND DISCUSSION
Table.5. Design Metrics of Type 2 AFAs
This section presents the performance of state-of-the-art
AFAs. The DMs that have been extracted for Type1, Type 2 and Power (nW) Delay Area
Type3 AFAs (using the synthesis environment shown in Fig.3) AFA 2
Leakage Dynamic Total (ps) (µm )
are tabulated in the Table.4 - Table.6 respectively. The maximum
and minimum values in each column are highlighted using bold AFA13 0.314 3869.030 3869.344 371 49.90
font.
From the Table.4, among the Type1 AFAs, the following Table.6. Design Metrics of Type3 AFAs
inferences can be drawn: Power (nW) Delay Area
• The AFA6, AFA9, AFA18, and AFA28 are found to be AFA 2
Leakage Dynamic Total (ps) (µm )
power and area efficient. These adders are having same
power (2647.961nW) and area (36.59µm2). This can be AFA1 0.082 1077.481 1077.562 100 16.63
attributed to their underlying architecture. AFA8 0.195 3752.307 3752.502 249 56.55
• The AFA3, AFA5, and AFA27 are found to be having low AFA10 0.034 1510.208 1510.242 191 19.95
delay this is due to shortest critical path. The delay of these AFA11 0.046 1692.486 1692.532 135 26.61
adders are equal and found to be 169ps.
AFA15 0.034 1680.161 1680.195 191 19.95
• The AFA2 is having a leakage power of 0.101nW, which is
the lowest among other Type-1 AFAs. AFA17 0.119 3090.067 3090.186 292 39.92
Considering the Table.5, among Type 2 AFAs, it is noticed AFA19 0.137 2891.337 2891.474 254 46.57
that: AFA20 0.139 2223.611 2223.749 148 33.26
• AFA13 is the only adder that falls under this category, it has AFA21 0.099 1966.927 1967.026 159 33.26
leakage power = 0.314nW, total power = 3869.344nW, AFA23 0.099 1966.927 1967.026 159 33.26
delay = 371ps, and area = 49.90µm2.
Considering Table.6, among the Type3 AFAs, the following 6. CONCLUSION
observations can be made:
• The AFA10 has the low leakage power (0.034nW). This paper discussed and compared a total 28 AFAs that were
• The AFA1 is found to be power (1077.562nW), delay reported in the state-of-the-art technical literature. The
(100ps) and area (16.63µm2) efficient as compared to other comparison of these adders have been performed in terms of
AFAs. design metrics (DMs) such as total power, delay, and area. Based
Note: Among AFA12 and AFA22 are not considered for on the type approximation used, we have classified the AFAs into
comparison as their area and delay are found to be same and equal three different categories namely Type-1, Type-2, and Type-3.
to 0. Therefore it is not fair to compare these adders against other Among these, the AFA1 is found to be power and area efficient
AFAs. with low delay. It has a total power = 1077.562nW, delay = 100ps,
and area=16.63µm2. The AFA10 has the lowest leakage power as
Table.4. Design Metrics of Type1 AFAs compared to any other AFA under consideration. It has the
leakage power of 0.034nW. This comparison work assists the
Power (nW) Delay Area designers to trade-off the various AFAs in terms of power, area,
AFA 2 and delay DMs. This study also helps in choosing a right AFA for
Leakage Dynamic Total (ps) (µm )
particular application. There is a wide scope for further research
AFA2 0.101 3525.857 3525.957 214 53.22 on these AFAs at image/video/audio application level.
AFA3 0.153 3536.112 3536.265 169 56.55
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