Combinational ATPG

Ganesh C. Patil

Tuesday, November 7, 2023

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Test Generation
 Test generation is the bread-and-butter in
VLSI Testing
 Efficient and powerful ATPG can alleviate high costs
of DFT
 Goal: generation of a small set of effective vectors at a
low computational cost
 ATPG is a very challenging task
 Exponential complexity
 Circuit sizes continue to increase (Moore’s Law)
– Aggravate the complexity problem further
 Higher clock frequencies
– Need to test for both structural and delay defects
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Functional vs. Structural ATPG
Functional ATPG – generate complete set
of tests for circuit input-output
combinations

129 inputs, 65 outputs:

2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns

Using 1 GHz ATE, would take

2.15 x 1022 years

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Structural ATPG-Carry Circuit
#PI=3,
#gates=4,
# fanout branches =6
#PO=1
#FO=3
# Gi =9
# Ni =0

Number of fault sites = #PI + #gates + # (fanout branches)

Number of fault sites =3+4+6=13
Number of single stuck-at-faults =2×13=26
Number of Collapsed faults = 2× (PO+FO) + Gi-Ni
= 2× (1+3) + 9-0 =17

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Structural ATPG-Sum Circuit
#PI=3,
#gates=2,
# fanout branches =0
#PO=1
#FO=0
# Gi =4
# Ni =0

Number of fault sites = #PI + #gates + # (fanout branches)

Number of fault sites =3+2+0=5
Number of single stuck-at-faults =2×5=10

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Functional vs. Structural
 Structural test:
 No redundant adder hardware, 64 bit slices

 Each with 27 faults (using fault equivalence)

 At most 64 x 27 = 1728 faults (tests)

 Takes 0.000001728 s on 1 GHz ATE

 Designer gives small set of functional tests

– augment with structural tests to boost
coverage to 98+ %

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Exhaustive Test Generation
 Exhaustive Testing
 Apply 2n patterns to an n-input combinational circuit
under test (CUT)
 Guarantees all detectable faults in the combinational
circuits are detected
 Test time maybe be prohibitively long if the number of
inputs is large
 Feasible only for small circuits
 Pseudo-exhaustive Testing
 Partition circuit into respective cones
 Apply exhaustive testing only to each cone
 Still guarantees to detect every detectable fault
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Conceptual View of ATPG
 Generate an input vector that can distinguish
the defect-free circuit from the hypothetically
defective one

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Simple illustration of ATPG

 Consider the fault d/1 in the defective circuit

 Need to distinguish the output of the defective circuit
from the defect-free circuit
 Need: set d=0 in the defect-free circuit
 Need: propagate effect of fault to output
 Vector: abc=001 (output = 0/1)

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Definition of Automatic Test-
Pattern Generator
 Inject fault into circuit modeled in
computer
 Use various ways to activate and
propagate fault effect through hardware
to circuit output
 Output flips from expected to faulty
signal

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Shannon’s Expansion Theorem
 F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) +
X2F (X1, 0, …, Xn)
e.g.

F (x,y,z) = y. F (x, y=1, z) + y. F (x, y=0, z)

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Boolean Difference Method

 Let the target fault be y/0, then the function

for the faulty circuit is f’ = f(y=0)
 Goal of test generation: find a vector that
makes f XOR f’ = 1

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Boolean Difference Method
 f XOR f’ = 1 iff f and f’ result in opposing logic
values
 Thus, any vector that can set f XOR f’ = 1 is
able to produce opposing values at the outputs
of the fault-free and faulty circuits respectively
 Definition:

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Boolean Satisfiability
 Given a circuit with output f and fault α/v.
 The set of vectors that can detect this fault
includes all vectors that satisfy,
df
(  v) 1
d
df
 For α/0  1
d
df
 For α/1  1
d

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Boolean Difference Method Example-1
 To excite the fault
y/0, y=1
df
 .And y  1
dy
y.[ f ( y  1)  f ( y  0)]  1

 For y= 1, f (y=1) = x
 For y= 0, f (y=0) = z

 Therefore,

 xyz= 110 or 011 can

detect the fault
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Boolean Difference Method Example-2
 Target fault is w/0

 For w= 1, f (w=1) = 1
 For w= 0, f (w=0) = xy

Hence, xyz=001, 101 can detect w/0

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Boolean Difference Method Example-3
 Target fault is z/0

 For z= 1, f (z=1) = xy
 For z= 0, f (z=0) = xy

This fault is
untestable by
Boolean Difference
Method

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Deterministic ATPG
 In general, we don’t need an entire set of
vectors that can detect the target fault
 Instead, we just want to compute one vector
quickly
 Rather than using Boolean Difference that
can obtain all vectors
 Simply use a BDD
 Deterministic ATPG has two main goals
 Excite the target fault
 Propagate the corresponding fault effect to an output

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Roth’s Higher-Order Algebra
 Represent two machines, which are
simulated simultaneously by a computer
program:
 Good circuit machine (1st value)

 Bad circuit machine (2nd value)

 Needed for complete Combinational ATPG:

 Path sensitization, Roth Algebra

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Roth’s 5-Valued Algebra

Good Failing
Symbol Meaning Machine Machine
D 1/0 1 0
D 0/1 0 1 Roth’s
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X

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Roth’s 5-value Algebra
 Instead of using two circuits (fault-free and the faulty)
 We will solve the ATPG problem on one single circuit
 To do so, every signal value must be able to
capture fault-free and faulty values simultaneously
 5-Value Algebra: 0, 1, X, D, D-bar
 Conventional: Logic 0, Logic 1, Don’t care

 D: 1/0

 D-bar: 0/1

v/vf => v is the fault free value

vf is the faulty value

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AND Operator on 5-Value Algebra
 1 AND D => 1 AND 1 => 1
1 AND 0 => 0
=> 1/0 => D

AND 0 1 D D_bar X
0 0 0 0 0 0
1 0 1 D D_bar X
D 0 D D 0 X
D_bar 0 D_bar 0 D_bar X

X 0 X X X X

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OR Operator on 5-Value Algebra
 D OR D_bar => 1 OR 0 => 1
0 OR 1 => 1
=> 1

OR 0 1 1 D D_bar X
0 0 1 1 D D_bar X
1 1 1 1 1 1 1
D D 1 1 D 1 X
D_bar D_bar 1 1 D_bar X

X X 1 X X X

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NOT Operator on 5-Value Algebra
NOT
0 1
1 0
D D_bar
D_bar D

X X

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Path Sensitization Method
 Fault Sensitization or Fault activation or Fault
Excitation
 In this step fault is activated by forcing the
opposite value from the fault value
 Fault Propagation
 In this step the fault effect is propagated through
one or more paths towards the PO
 Line Justification
 In this step the internal signal assignments made
to sensitize the fault or propagate its effect are
justified by setting the PIs
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Path Sensitization Method Example-1

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Step-1 Fault Sensitization

 To Sensitize the fault B SA0 we set B=1.

 This leads to signal assignment f=D and g= D.

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Step-2 Fault Propagation

 For fault Propagation there are three Scenarios

 Scenario 1: Propagation along path f-h-k-l
 Scenario 2: Simultaneous Propagation along
path f-h-k-l and g-i-j-k-l
 Scenario 3: Propagation along path g-i-j-k-l
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Step-3 Line Justification

D
1
D

 Every AND gate along the path, the off path

inputs should be set to logic 1
 Every OR gate along the path, the off path
inputs should be set to logic 0
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Step-3 Line Justification
Scenario 1: Propagation along path f-h-k-l
1 D
D D D
D 0

1
 To satisfy j=0 we have to assign i= 1
 But at input of AND gate one input g= D
 Therefore if C=1, i=D and if C=0, i=0
 i.e i=1 is not justified.
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Step-3 Line Justification
Scenario 1: Propagation along path f-h-k-l
1 D
D 1
1 1
D 1

1
 Therefore, now try backtracking and assign j= 1
 But if j=1, k=1 and If E= 1, L= 1 Also If E= 0, L=0
 i.e. the back tracking blocks the propagation of the fault
 Hence, the Propagation along path f-h-k-l is not justified.
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Step-3 Line Justification
Scenario 2: Simultaneous Propagation along path f-h-k-l and
1 D g-i-j-k-l
D 1
1
D D
D
1
1
 Now A=1, E=1, C=1
 Therefore, i=D, h=D, j=D_bar, k=1, and L=1
 In this scenario D disappears at the PO
 Hence, the Simultaneous Propagation along path f-h-k-l
and g-i-j-k-l is not justified.
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Step-3 Line Justification
Scenario 3: Propagation along path g-i-j-k-l
0
D 0 D
D
D D
D
1
1
 Now we set C=1 and E=1. Hence, i=D and j= D_bar
 Now to propagate D_bar we required to set h=0
 Therefore to set h=0 we required to set A=0.
 Now k=D_bar. Hence L= D_bar which propagates the fault
with line justification
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Test Vector Generation
0

D 0 D
1 D
D D
D
1
1
 Thus, among all the scenarios Propagation along path
g-i-j-k-l satisfies the criterion of fault propagation
 The test set for the detection of fault
BSA0 is ABCE = {0111}
 The above test set produces L=0 for good machine and
L=1 for the faulty machine
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Example-2
 Target fault is b/0

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Example-2
 Target fault is b/0

For Detection of b/0 fault test vector is

w1 w2 w3 w4 = {0011)
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Example-2
 Target fault is g/1

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Example-2
 Target fault is g/1

For Detection of g/1 fault test vector is

w1 w2 w3 w4 = {0000)
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Backtracking
 The ATPG searches one branch at a time
Whenever a conflict (e.g., all D’s
disappeared) arises, must backtrack on
previous decisions

Current decision a=0, c=1, d=0 causes a conflict

If d=1 also causes a conflict, backtrack to c=0

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Decision Tree branch and-bound search
 The ATPG systematically and implicitly searches
the entire search space

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Shannon’s Expansion

f=xf(x) + x’f’(x) a
a=0 a=1
f= ac + bc
fa = f (a=1) = c+ bc
fa’ = f (a=0) = bc
fa’ = bc
f= a fa + a’ fa’ fa = c+ bc
f= a (c+bc) + a’ (bc)

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Binary Decision Diagram (BDD)
 Binary Decision Diagram are the trees whose
non terminal nodes are labeled with binary
variables X,Y, Z….and whose terminal nodes
are labeled with 0 or 1
 Each non terminal node has two edges one
dashed line and one solid line
 Dashed line represents 0 and solid line
represents 1

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Simple BDD

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Thank you !!!

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