LTC4286
LTC4286
LTC4286
LTC4286
High Power Positive Hot-Swap Controller with Power Monitor via PMBus
Rev. A
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Data Sheet LTC4286
TABLE OF CONTENTS
REVISION HISTORY
10/2023—Rev. 0 to Rev. A
Changed Master to Host and Slave to Target (Throughout)............................................................................ 1
Changes to Figure 1 Caption........................................................................................................................... 1
Changes to Table 3.......................................................................................................................................... 8
Change to Applications Information Section.................................................................................................. 15
Deleted Figure 20; Renumbered Sequentially............................................................................................... 15
Changes to Turn-On Sequence Section........................................................................................................ 15
Changes to Turn-Off Sequence Section........................................................................................................ 15
Change to Data Converters Section.............................................................................................................. 17
Changes to Table 10...................................................................................................................................... 21
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Data Sheet LTC4286
ELECTRICAL CHARACTERISTICS
Specifications apply over the full operating temperature range, unless otherwise noted. All currents into pins are positive and all voltages are
referenced to GND, unless otherwise specified.
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Data Sheet LTC4286
ELECTRICAL CHARACTERISTICS
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Data Sheet LTC4286
ELECTRICAL CHARACTERISTICS
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Data Sheet LTC4286
ELECTRICAL CHARACTERISTICS
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Data Sheet LTC4286
ABSOLUTE MAXIMUM RATINGS
All currents into pins are positive and all voltages are referenced to Table 2. Absolute Maximum Ratings (Continued)
GND, unless otherwise specified. Parameter Rating
Table 2. Absolute Maximum Ratings Output Currents
Parameter Rating INTVCC, DVCC −5 mA
Temperature
Supply Voltages
Operating Range −40°C to +125°C
VDD −0.3 V to +100 V
Storage Range −65°C to +150°C
INTVCC, DVCC −0.3 V to +5.5 V
Input Voltages 1 An internal clamp limits the GATE pin to a minimum of 10 V above SOURCE.
SDAI, SCL −0.3 V to +6 V Driving this pin to voltages beyond the clamp may damage the device.
CFIG4 −0.3 V to +1 V
Stresses at or above those listed under Absolute Maximum Ratings
OV, UV, FB, EN −0.3 V to +100 V
may cause permanent damage to the product. This is a stress
VDSFB −0.3 V to VDD + 0.3 V rating only; functional operation of the product at these or any other
TMR, ADR0, ADR1, CFIG3 −0.3 V to INTVCC + 0.3 V conditions above those indicated in the operational section of this
ADC+, SENSE+ VDD − +4.5 V to VDD + 0.3 V specification is not implied. Operation beyond the maximum operat-
ADC−, SENSE− VDD − +4.5 V to VDD + 0.3 V ing conditions for extended periods may affect product reliability.
CFIG1, CFIG2 VDD − +4.5 V to VDD + 0.3 V
SOURCE −0.3 V to +100 V
ESD CAUTION
GATE − SOURCE1 −0.3 V to +10 V ESD (electrostatic discharge) sensitive device. Charged devi-
Output Voltages ces and circuit boards can discharge without detection. Although
ISET, CFIG5, CFIG6 −0.3 V to DVCC + 0.3 V this product features patented or proprietary protection circuitry,
GPIO1, GPIO2, GPIO6 −0.3 V to 100 V damage may occur on devices subjected to high energy ESD.
GPIO3, GPIO5, GPIO7 −0.3 V to INTVCC + 0.3 V Therefore, proper ESD precautions should be taken to avoid
GATE −0.3 V to +100 V performance degradation or loss of functionality.
SDAO, GPIO4, GPIO8 −0.3 V to +6 V
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Data Sheet LTC4286
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
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Data Sheet LTC4286
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
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Data Sheet LTC4286
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
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Data Sheet LTC4286
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. IDD vs. VDD Figure 6. DVCC vs. Load at VDD = 8.5 V, 12 V, and 48 V
Figure 5. INTVCC vs. Load at VDD = 8.5 V, 12 V, and 48 V Figure 8. MOSFET Power vs. VDS
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Data Sheet LTC4286
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Current-Limit Threshold vs. Temperature Figure 12. IGATE (Up) vs. Temperature
Figure 10. VGATE − VSOURCE vs. Temperature at VDD = 8.5 V, 12 V, and 48 V Figure 13. ISOURCE vs. VSOURCE
Figure 11. VGATE − VSOURCE vs. IGATE (Leak) at VDD = 8.5 V, 12 V, and 48 V Figure 14. VOL GPIO1, GPIO2, GPIO6 vs. IGPO
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Data Sheet LTC4286
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. VOL GPIO3, GPIO5, GPIO7 vs. IGPO Figure 18. ADC DNL vs. Code (64x Average)
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Data Sheet LTC4286
THEORY OF OPERATION
The LTC4286 is designed to turn a board’s supply voltage on and LTC4286 turns off GATE and the IOUT_OC_FAULT bit is set, which
off in a controlled manner, allowing the board to be safely inserted causes the FAULT# pin to pull low. Then the TMR pin ramps down
or removed from a live backplane. During normal operation, the using a 5 μA current source until the voltage drops below 0.2 V. If
charge pump and gate driver turn on an external N-channel MOS- overcurrent auto-retry is enabled by tying the GPIO2 (configured as
FET gate to pass power to the load. The gate driver uses a charge FAULT#) pin to the UV pin, the LTC4286 turns on again at the end
pump that derives its power from the VDD pin. Also, included in the of the 9.28 s cool-down timer.
gate driver is an internal 14 V GATE to SOURCE clamp to protect
the oxide of the external MOSFET. The output voltage is monitored using the SOURCE pin and the
power good (PG) comparator to determine if the power is available
In normal operation, the LTC4286 turns on the external N-channel for the load. The power good condition is signaled by the GPIO1
MOSFET after a startup debounce delay, passing power to the (configured as Power-Good#) pin using an open-drain pull-down
load. A precise current limit value can be set from 6 mV to 20 mV transistor.
in 2 mV steps using ISET voltage or bits in the MFR_CONFIG1 reg-
ister. During startup, the voltage between SENSE+ and SENSE− The LTC4286 includes three ADCs and all operate at 12-bit resolu-
is controlled to be no higher than the current limit threshold with tion. One data converter continuously monitors the ADC+ to ADC−
foldback (α). The startup current may be set to even lower values voltage, sampling every 1 µs and producing a 12-bit result of the
with an external gate RC network. average sense voltage every 283 µs. The second data converter is
synchronized to the first and measures the SOURCE voltage during
An overcurrent fault at the output may result in excessive MOSFET the same time period. Every time the first two ADCs finish taking a
power dissipation during active current limiting (ACL). To limit measurement, the sense voltage is multiplied by the measurement
this power, the ACL amplifier regulates the voltage between the of the SOURCE pin to provide a power measurement. The third
SENSE+ and SENSE− pins by reducing the gate-to-source voltage data converter measures temperature on an external or internal
in an active control loop when the sense voltage exceeds the diode with 1°C resolution. The minimum and maximum SOURCE,
current-limit value. When the MOSFET drain to source voltage ADC+ to ADC−, POWER, and TEMP measurements are stored,
is high, power dissipation is further reduced by folding back the and optional alerts may be generated if a measurement is above or
current limit to 30% of nominal. In the event of a catastrophic output below user configurable 12-bit thresholds.
short, fast current limit comparators immediately pull the GATE pin
down with 1 A when the sensed current is three times the nominal A PMBus interface is provided to read the A/D registers. It also
current-limit. allows the host to poll the device and determine if faults have
occurred. If any GPIO pin is configured as an ALERT# interrupt, the
To prevent MOSFET overheating, the current-limit timeout is set by host is enabled to respond to faults in real time. The PMBus device
a capacitor on the TMR pin. The TMR pin is configured to drive target address is decoded using the ADR0 and ADR1 pins. These
a single capacitor and ramp up with 20 µA when active current inputs have three states each that decode into a total of nine device
limiting is engaged. If the TMR pin reaches its 2.56 V threshold, the addresses.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
A typical LTC4286 application is in a high availability system in a power-good output releases high to indicate that power is good
which a positive voltage supply is distributed to power individual and the load can be activated. The CFIG6 pin is used to select if
boards. PMBus telemetry includes voltages, currents, and status the LTC4286 starts up automatically after power up or waits for a
information including faults to be read by the host. The LTC4286 PMBus host controller to command it to turn on. If the CFIG6 pin
stores minimum and maximum ADC measurements, calculates is grounded, it turns on, if it is set to 1.6 V by a resistive divider, it
power, and can be configured to generate alerts based on meas- remains off and wait for further instructions. See Table 4.
urement results, avoiding the need for the system to poll the device Table 4. Using the CFIG6 Pin to Configure the Default On/Off State
on a regular basis. A basic LTC4286 application circuit is shown in
CFIG6 at Power-Up ON Bit
Figure 1. The following sections cover turn-on, turn-off, and various
faults that the LTC4286 detects and acts upon. <1 V On
>1 V, <2.56 V Off
OVERVIEW
The output is controlled by using a N-channel MOSFET, M1, placed At the minimum input supply voltage of 8.5 V, the minimum GATE-
in the power path. The resistor RS1 provides the current measure- to-SOURCE driver voltage is 10 V. The GATE-to-SOURCE voltage
ment. The resistive dividers R1, R2, and R3 define undervoltage is clamped below 14 V to protect the gates of 20 V N-channel
and overvoltage levels. The UV and OV thresholds can be set using MOSFETs. A curve of GATE-to-SOURCE drive (ΔVGATE) vs. VDD is
a three resistor dividers. Choose a divider current of at least 200 shown in the Typical Performance Characteristics section.
μA. R1 < 2.56 V/200 μA = 12.8 kΩ, then calculate: TURN-OFF SEQUENCE
VOV OFF UVTH RISING
R2 = × R1 × − R1 (1) A normal turn-off sequence is initiated by card withdrawal when
VUV ON OVTH FALLING
the backplane connector short pin connected to EN opens, causing
VUV ON × R1 + R2 the EN pin to change state. Additionally, several fault conditions
R3 = UVTH RISING − R1 − R2 (2) turn off the GATE pin. These include an input overvoltage, input un-
dervoltage, overcurrent, or FET-BAD fault. The MOSFET is turned
The resistor RG1 prevents high frequency self-oscillations in the off with 1 mA of current pulling the GATE pin to ground combined
MOSFET. R7 and R8 set the power-good threshold, and R6 scales with 11 mA from GATE-to-SOURCE, for a total of 12 mA. With the
current-limit foldback to the intended operating voltage. The resis- MOSFET turned off, the SOURCE and FB voltages drop as the
tive divider, R9 and R10, sets the value of the current limit. For load capacitance discharges. When the FB voltage crosses below
more details, see Table 5. its threshold, a GPIO pin configures as a power-good output pulls
TURN-ON SEQUENCE low to indicate that the output power is no longer good. If the
VDD pin falls to less than 5.5 V or INTVCC drops to less than the
Several conditions must be present before the external MOSFETs undervoltage lockout falling threshold of 3.89 V, a fast shut down of
turn on. First, the external supply, VDD, must exceed its 6.0 V the MOSFET is initiated. The GATE pin is then pulled down with 1
undervoltage lockout level. Next, the internally generated supplies, A of current to the SOURCE pin.
INTVCC and DVCC, must cross their 4 V and 2.2 V undervoltage
thresholds, respectively. This generates an internal power-on reset Overcurrent Fault Condition
signal. After a power-on reset, the UV and OV pins verify that
input power is within the acceptable range and the EN pin must be The current limit is set by the value of the ILIM bits in the
made active to indicate that the board is seated, or the LTC4286 is MFR_CONFIG1 register and the value of the current-sense resistor,
commanded to turn on. The state of the UV and EN comparators RS1. In the event of an overcurrent, the power-dissipation in the
must be stable for at least 90.6 ms to qualify for turn on. When MOSFET is limited by the foldback profile shown in Figure 7 and
these conditions are satisfied, turn on is initiated. The MOSFET Figure 8. Calculate the value of the external resistor, R6:
is then turned on by charging up the GATE pin with a 53 μA R6 = 10 kΩ × VIN − 12 V (4)
current source. When the GATE pin voltage reaches the MOSFET
threshold voltage, the MOSFET begins to turn on and the SOURCE Examples include the following:
voltage then follows the GATE voltage as it increases. The capac-
itor CGATE limits the dv/dt on the GATE voltage, controlling the ► VIN = 12 V, RVDSFB = 0 Ω
inrush current. The inrush current is: ► VIN = 48 V, RVDSFB = 365 kΩ
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Data Sheet LTC4286
APPLICATIONS INFORMATION
limits. The worst-case operating condition can be completely charg- Setting the Current Limit
ing a large bypass capacitor at the output during start up or riding
through a large input step. The capacitor on the TIMER pin must be The current limit is set with a resistive divider on the ISET pin. The
calculated to ensure that the MOSFET stays within the SOA during ISET pin provides a 2 mV resolution. These options are shown in
normal and fault conditions. Table 5. ISET is only read at power-up or reboots. Changing ISET
while operating does not change the current limit. Writing to ILIM
Note that the timer is independent of the current limit. If the current while operating changes the current-limit.
limit is changed, it may be necessary to change the value of the
TIMER pin capacitor.
Table 5. Configuring Current Limit with the ISET Pin
ISET Thresholds Compared with
∆VSNS(TH) (mV) ILIM VISET (V) Lower (V) Upper (V) RTOP (kΩ) RBOTTOM (kΩ) RBOTTOM/(RTOP + RBOTTOM)
6 0001 0 0.357 Open Short 0.000
8 0011 0.714 0.357 1.071 88.7 14.7 0.143
10 0101 1.429 1.071 1.786 73.2 29.4 0.286
12 0111 2.143 1.786 2.5 59.0 44.2 0.429
14 1001 2.857 2.5 3.214 44.2 59.0 0.571
16 1011 3.571 3.214 3.929 29.4 73.2 0.714
18 1101 4.286 3.929 4.643 14.7 88.7 0.857
20 1111 5 4.643 Short Open 1.000
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Data Sheet LTC4286
APPLICATIONS INFORMATION
DATA CONVERTERS The two data converters are synchronized, and after each current
measurement conversion, the measured current is multiplied by the
The LTC4286 incorporates a pair of 12-bit Σ-Δ ADCs, and a third measured VDD or VSOURCE, as selected by the VPWR_SELECT bit
data converter, which monitors temperature with a 1°C/LSB. One in the MFR_CONFIG1 register, to yield input or output power. The
converter continuously samples the current-sense voltage, while measurements are compared to the min/max warning thresholds
the other monitors the input voltage, output voltage, and the VDD- and set the corresponding ADC warning bits in the MFR_SYS-
SOURCE voltage. The Σ-Δ architecture inherently averages signal TEM_STATUS2 register and generate an alert if configured to do so
noise during the measurement period. The second data converter in the MFR_STAT2_ALERT_MASK register.
can be configured to measure VIN at the VDD pin, VOUT at the
SOURCE pin, and/or the voltage across the MOSFET by selecting The following formulas are used to convert the values in the ADC
related bits in the MFR_ADC_CONFIG register. The data converter result registers into physical units. The data is in twos complement
full scale is 32 mV for the current-sense voltage, a choice of 102.4 format, left justified, so for 12-bit data the MSB is always 0, and the
V or 25.6 V for VDD and VSOURCE, 2.56 V for GPIO and 320 mV for 3 LSBs are also 0s.
the VDD-SOURCE measurement. To calculate the input and output voltage, use the following equa-
tion:
CODE WORD × VFS OUT
V= (5)
215 − 1
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 7. LTC4286 ADC Measurement Pattern in Continuous Mode, Assuming No AUX Channels Selected
Conversions over Time
ADC1 ADC1 ADC1 ADC1 ADC1
(ADC+ – ADC−) (ADC+ – ADC−) (ADC+ – ADC−) (ADC+ – ADC−) (ADC+ – ADC−)
ADC2 ADC2 ADC2 ADC2 ADC2
VOUT VIN VOUT VIN VOUT VIN VOUT VIN VOUT VIN
PMBus specifies M, B, and R constants for use in calculating ADC results. See Table 8 for the LTC4286 M, B, and R parameters.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
1 R = read only, R/W = read or write, R/W1C = read or write 1s to clear, and R/W1S = read or write 1s to set.
2 N/A = not applicable.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
ADC-RELATED COMMANDS AND ALIASES and LTC4286 specific. This leads to multiple command names for
the same internal register in many cases. Results are the same
PMBus defines command codes for several ADC values and warn- whether a PMBus standard command or its MFR alias is accessed.
ing limits. The LTC4286 uses these command codes, which are
defined. Many additional ADC-related commands are not defined The five READ_ PMBus standard commands respond with either
as PMBus standard. averaged or non-averaged ADC data. This depends on the setting
of DISP_AVG in MFR_AVG_SEL. In the MFR area, non-averaged
The MFR command area above 0xFE00 is arranged orthogonally ADC results are available at any time at separate commands.
to allow addressing ADC-related values, both PMBus standard
Table 11. PMBus ADC-Related Commands and MFR Aliases
PMBus Command Code MFR Alias Code
VOUT_OV_WARN_LIMIT 0x42 MFR_VOUT_OV_LIMIT 0xFE1D
VOUT_UV_WARN_LIMIT 0x43 MFR_VOUT_UV_LIMIT 0xFE1C
IOUT_OC_WARN_LIMIT 0x4A MFR_IOUT_OC_LIMIT 0xFE05
OT_WARN_LIMIT 0x51 MFR_TEMP_OT_LIMIT 0xFE4D
UT_WARN_LIMIT 0x52 MFR_TEMP_UT_LIMIT 0xFE4C
VIN_OV_WARN_LIMIT 0x57 MFR_VIN_OV_LIMIT 0xFE15
VIN_UV_WARN_LIMIT 0x58 MFR_VIN_UV_LIMIT 0xFE14
PIN_OP_WARN_LIMIT 0x6B MFR_PIN_OP_LIMIT 0xFE0D
READ_VIN 0x88 MFR_VIN 0xFE10
READ_VOUT 0x8B MFR_VOUT 0xFE18
READ_IOUT 0x8C MFR_IOUT 0xFE00
READ_TEMPERATURE_1 0x8D MFR_TEMP 0xFE48
READ_PIN 0x97 MFR_PIN 0xFE08
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
LATCHED STATUS AND MASK COMMANDS Once set, each status bit remains set until one of the following
occurs:
Overview ► A chip reset or reboot.
Latched status is kept in the following command locations: ► A CLEAR_FAULTS command clears them all.
► STATUS_BYTE ► The ON bit in the OPERATION command is cleared then set
again.
► STATUS_WORD ► At an active edge of EN, all status bits are cleared if RE-
SET_FAULT_ENABLE is set in MFR_CONFIG2.
► STATUS_VOUT
► A 1 bit is written to the corresponding location in the status
► STATUS_IOUT command to clear it.
► STATUS_INPUT The LTC4286 also provides a method for software to set latched
status bits. To support this, a parallel list of commands is defined.
► STATUS_TEMPERATURE Writing a 1 bit to these commands set the corresponding status
► STATUS_CML bits.
► STATUS_OTHER Each of the latched status bits is able to generate an SMBus alert
condition by pulling down on a selected open-drain output (for more
► STATUS_MFR_SPECIFIC details, see Table 19).
► MFR_SYSTEM_STATUS1 Status bits are combined with corresponding mask bits before
activating the alert. If the mask bit is 1, the status bit does not
► MFR_SYSTEM_STATUS2
contribute to the alert. The LTC4286 power-on default is for all
The status bits have three categories: status bits to be masked off, preventing alert indication. Software
can write the mask commands to unmask selected status bits.
► Faults: conditions that cause GATE to turn off.
► Warnings: conditions, which can lead to a fault. Table 19 shows how the commands for latched status are related.
► Events: errors and other information, not related to faults.
Table 19. Latched Status Commands
Main (R/W1C) Code Mirror (R/W1S) Code Mask (R/W)1 Code1
STATUS_BYTE 0x78 MFR_STATUS_BYTE 0xFEC0 MFR_BYTE_ALERT_MASK 0xFED0
STATUS_WORD 0x79 MFR_STATUS_BYTE 0xFEC0 MFR_BYTE_ALERT_MASK 0xFED0
MFR_STATUS_WORD_HIGH 0xFEC1
STATUS_VOUT 0x7A MFR_STATUS_VOUT 0xFEC2 MFR_VOUT_ALERT_MASK 0xFED2
STATUS_IOUT 0x7B MFR_STATUS_IOUT 0xFEC3 MFR_IOUT_ALERT_MASK 0xFED3
STATUS_INPUT 0x7C MFR_STATUS_INPUT 0xFEC4 MFR_INPUT_ALERT_MASK 0xFED4
STATUS_TEMPERATURE 0x7D MFR_STATUS_TEMP 0xFEC5 MFR_TEMP_ALERT_MASK 0xFED5
STATUS_CML 0x7E MFR_STATUS_CML 0xFEC6 MFR_CML_ALERT_MASK 0xFED6
STATUS_OTHER 0x7F MFR_STATUS_OTHER 0xFEC7 N/A N/A
STATUS_MFR_SPECIFIC 0x80 MFR_SPECIFIC_STATUS 0xFEC8 MFR_SPECIFIC_ALERT_MASK 0xFED8
MFR_SYSTEM_STATUS1 0xE0 MFR_SYS_STAT1_SET 0xFECA MFR_STAT1_ALERT_MASK 0xFEDA
MFR_SYSTEM_STATUS2 0xE1 MFR_SYS_STAT2_SET 0xFECC MFR_STAT2_ALERT_MASK 0xFEDC
Table 20. STATUS_BYTE (0x78) W1C, MFR_STATUS_BYTE (0xFEC0) W1S, MFR_BYTE_ALERT_MASK (0xFED0) R/W
Default 0x78,
Bit Name 0xFEC0 Default 0xFED0 Operation
7 BUSY 0 1 Bit set if the device was busy and cannot respond to a PMBus access.
6 OFF 0 RO/0 Hot-swap gate is off, 1 = gate is disabled, 0 = gate is enabled.
5 Reserved 0 RO/0 Always returns 0.
4 IOUT_OC_FAULT 0 RO/0 Copy of IOUT_OC_FAULT bit in STATUS_IOUT.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 20. STATUS_BYTE (0x78) W1C, MFR_STATUS_BYTE (0xFEC0) W1S, MFR_BYTE_ALERT_MASK (0xFED0) R/W (Continued)
Default 0x78,
Bit Name 0xFEC0 Default 0xFED0 Operation
3 VIN_UV_FAULT 0 RO/0 Copy of VIN_UV_FAULT in STATUS_VIN.
2 TEMPERATURE 0 RO/0 Temperature fault or warning, 1 = there are one or more active status bits in
the STATUS_TEMPERATURE (7D), 0 = There are no active status bits.
1 CML 0 RO/0 CML fault or warning, 1 = there are one or more active status bits in the
STATUS_CML (7E), 0 = There are no active status bits.
0 NONE_OF_THE_ABOVE 0 RO/0 None of the above, 1 = one or more status bits not listed in bits [7:1] are set.
Table 21. STATUS_WORD (0x79) R/W1C, MFR_STATUS_BYTE/MFR_STATUS_WORD_HIGH (0xFEC0/0xFEC1) R/W1S, MFR_BYTE_ALERT_MASK (0xFED0) R/W
Default 0x79, Default 0xFED0
Bit Name 0xFEC0 (Byte Register) Operation
15 VOUT 0 N/A VOUT (SOURCE pin) fault or warning, 1 = there are one or more active status
bits in the STATUS_VOUT (0X7A), 0 = There are no active status bits.
14 IOUT 0 N/A IOUT current fault or warning, 1 = there are one or more active status bits in
the STATUS_IOUT (0X7B), 0 = There are no active status bits.
13 INPUT 0 N/A VIN (VDD pin) status warning, 1 = there are one or more active status bits in
the STATUS_INPUT (0x7C), 0 = There are no active status bits.
12 MFRSPECIFIC 0 N/A Manufacture specific fault or warning, 1 = there are one or more active
faults, bits [7:3] in the STATUS_MFR_SPECIFIC (0x80), 0 = There are no
active fault bits.
11 PG_STATUS# 0 N/A Bit is high if FB input pin is below 2.56 V, indicating the MOSFET output
voltage is not high enough for PG_LATCH status.
10 Reserved 0 N/A Always returns 0.
9 OTHER 0 N/A Status is present in STATUS_OTHER byte.
8 UNKNOWN 0 N/A Bit is high to indicate one or more bits in MFR_SYSTEM_STATUS1 are set.
7 BUSY 0 1 Bit set if the device was busy and could not respond to a PMBus access.
6 OFF 0 RO/0 Hot-swap gate is off, 1 = gate is disabled, 0 = gate is enabled.
5 Reserved 0 RO/0 Always returns 0.
4 IOUT_OC_FAULT 0 RO/0 Copy of IOUT_OC_FAULT bit in STATUS_IOUT.
3 VIN_UV_FAULT 0 RO/0 Copy of VIN_UV_FAULT in STATUS_VIN.
2 TEMPERATURE 0 RO/0 Temperature fault or warning, 1 = there are one or more active status bits in
the STATUS_TEMPERATURE (7Dh), 0 = There are no active status bits.
1 CML 0 RO/0 CML fault or warning, 1 = there are one or more active status bits in the
STATUS_CML (7Eh), 0 = There are no active status bits.
0 NONE_OF_THE_ABOVE 0 RO/0 None of the above, 1 = one or more status bits not listed in bits [7:1] are set.
Table 22. STATUS_VOUT (0x7A) R/W1C, MFR_STATUS_VOUT (0xFEC2) R/W1S, MFR_VOUT_ALERT_MASK (0xFED2) R/W
Default 0x7A,
Bit Name 0xFEC2 Default 0xFED2 Operation
7 Reserved 0 RO/0 Always returns 0.
6 VOUT_OV_WARNING 0 1 VOUT overvoltage warning, 1 = detected overvoltage by the VOLTAGE ADC
measuring the SOURCE pin, 0 = no OV detected.
5 VOUT_UV_WARNING 0 1 VOUT undervoltage warning, 1 = detected undervoltage by the VOLTAGE
ADC measuring the SOURCE pin, 0 = no UV detected.
[4:0] Reserved 00000 RO/00000 Always returns 00000.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 23. STATUS_IOUT (0x7B) R/W1C, MFR_STATUS_IOUT (0xFEC3) R/W1S, MFR_IOUT_ALERT_MASK (0xFED3) R/W
Default 0x7B,
Bit Name 0xFEC3 Default 0xFED3 Operation
7 IOUT_OC_FAULT 0 1 IOUT overcurrent fault (latched), 1 = detected overcurrent past the TMR pin
time limit, 0 = no OC fault detected.
6 Reserved 0 RO/0 Always returns 0.
5 IOUT_OC_WARNING 0 1 IOUT overcurrent warning, 1 = detected overcurrent warning by the
CURRENT ADC (VSENSE+ − VSENSE–), 0 = no OC detected.
[4:0] Reserved 00000 RO/00000 Always returns 00000.
Table 24. STATUS_INPUT (0x7C) R/W1C, MFR_STATUS_INPUT (0xFEC4) R/W1S, MFR_INPUT_ALERT_MASK (0xFED4) R/W
Default 0x7C,
Bit Name 0xFEC4 Default 0xFED4 Operation
7 VIN_OV_FAULT 0 1 VIN overvoltage fault (latched), 1 = detected overvoltage on the OV pin, 0 =
no OV detected.
6 VIN_OV_WARNING 0 1 VIN overvoltage warning, 1 = detected overvoltage by the VOLTAGE ADC
measuring the VDD pin, 0 = no OV detected.
5 VIN_UV_WARNING 0 1 VIN undervoltage warning, 1 = detected overvoltage by the VOLTAGE ADC
measuring the VDD pin, 0 = no UV detected.
4 VIN_UV_FAULT 0 1 VIN undervoltage fault (latched), 1 = detected undervoltage on the UV pin, 0
= no UV detected.
[3:1] Reserved 000 RO/000 Always returns 000.
0 PIN_OP_WARNING 0 1 Calculated input power, PIN, overpower warning, 1 = detected overpower, 0
= no OP detected.
Table 25. STATUS_TEMPERATURE (0x7D) R/W1C, MFR_STATUS_TEMP (0xFEC5) R/W1S, MFR_TEMP_ALERT_MASK (0xFED5) R/W
Default 0x7D, -
Bit Name xFED5 Default 0xFED5 Operation
7 OT_FAULT 0 1 Overtemperature fault (latched), 1 = detected overtemperature fault by the
TEMP ADC, 0 = no OT detected.
6 OT_WARNING 0 1 Overtemperature warning, 1 = detected overtemperature warning by the
TEMP ADC, 0 = no OT detected.
5 UT_WARNING 0 1 Undertemperature warning, 1 = detected undertemperature warning by the
TEMP ADC, 0 = no UT detected.
[4:0] Reserved 00000 RO/00000 Always returns 00000.
Table 26. STATUS_CML (0x7E) R/W1C, MFR_STATUS_CML (0xFEC6) R/W1S, MFR_CML_ALERT_MASK (0xFED6), R/W
Default 0x7E,
Bit Name 0xFEC6 Default 0xFED6 Operation
7 BAD_CMD 0 1 Invalid or unsupported command received.
6 BAD_DATA 0 1 Invalid or unsupported data received.
5 PEC_FAILED 0 1 Packet error check failed, or PEC byte missing where is it required.
4 Reserved 0 0 Always returns 0.
[3:2] Reserved 00 RO/00 Always returns 00.
1 MISC_FAULT 0 1 Miscellaneous communications fault has occurred.
0 Reserved 0 1 Reserved
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 28. STATUS_MFR_SPECIFIC (0x80) R/W1C, MFR_SPECIFIC_STATUS (0xFEC8) R/W1S, MFR_SPECIFIC_ALERT_MASK (0xFED8) R/W
Bit Name Default 0x80, 0xFEC8 Default 0xFED8 Operation
7 EN_CHANGED 0 1 Indicates that the EN pin changed state; 1 = EN changed
state, 0 = EN unchanged.
6 TSD_FAULT 0 1 Latched to a 1 if a thermal shutdown condition is
detected, 0 = no thermal shutdown.
5 VDD_UVLO 0 1 Latched to a 1 if the VDD input goes below the VDD_UVLO
limit, 0 = no UVLO condition on VDD.
4 PIN_OP2_FAULT 0 1 Indicates that the PIN has exceeded the limit for
immediate fault.
3 PIN_OP1_FAULT 0 1 Indicates that the timer has expired for the timed PIN fault
limit.
2 FET_BAD_FAULT 0 1 Latched to a 1 if FET Bad Fault occurred, 0 = No FET
Bad fault.
1 Reserved 0 1 Reserved for future use.
0 Reserved 0 1 Reserved for future use.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 35. MFR_SYSTEM_STATUS1 (0xE0) R/W1C, MFR_SYS_STAT1_SET (0xFECA) R/W1S, MFR_STAT_ALERT_MASK (0xFEDA) R/W
Default 0xE0,
Bit Name 0xFECA Default 0xFEDA Operation
15 ALERT 0 RO/0 Bit set to 1 when an Alert is generated. This can be cleared via SMBus write
or alert response protocol. The bit can be configured to appear as active low
or high on any GPIO pin.
14 L_ALERT 0 RO/0 Alternate version of ALERT or latched ALERT. This bit is set by the same
conditions that set ALERT. But it can only be cleared by an SMBus write.
This bit can be configured to appear on any GPIO pin as L_ALERT# or
L_ALERT.
13 Reserved 0 1 Reserved
12 Reserved 0 1 Reserved
11 POWER_LOSS 0 1 Bit is 1 following a power-on reset, or 0 after a reboot-generated reset.
10 RESET_DONE 0 1 Latched status bit is set after each chip reset (either power-on or reboot).
[9:8] Reserved 00 RO/00 Always returns 00.
7 AVERAGE_DONE 0 1 Set at the completion of an average.
6 ADC_CONV 0 1 Latched to 1 when a full ADC conversion (current and voltage) completes.
5 Reserved 0 1 Reserved
4 Reserved 0 1 Reserved
3 Reserved 0 1 Reserved
2 Reserved 0 1 Reserved
1 Reserved 0 1 Reserved
0 MFR_NONE_OF_ABOVE 0 RO/0 Bit is set if bits in MFR_SYSTEM_STATUS2 are set.
Table 36. MFR_SYSTEM_STATUS2 (9xE1) R/W1C, MFR_SYS_STAT2_SET (0xFECC) R/W1S, MFR_STAT2_ALERT_MASK (0xFEDC) R/W
Default 0xE1,
Bit Name 0xFECC Default 0xFEDC Operation
15 POWER_FAILED_WARNING 0 1 This latched bit is set if POWER_FAILED_STATUS goes active. This
happens if the FB input pin goes below 2.56 V while the PG_LATCH status
bit is set. That indicates a loss of output voltage after it was initially good.
14 FET_SHORT_WARNING 0 1 Latched to a 1 if measured (VSENSE+ − VSENSE−) exceeds 2 mV while FET
is off (FET Short was detected); 1 = FET Short Fault occurred, 0 = No FET
Short fault.
[13:12] Reserved 00 RO/00 Always returns 00.
11 Reserved 0 1 Reserved for future use. Only write 0.
10 Reserved 0 1 Reserved for future use. Only write 0.
9 Reserved 0 1 Reserved for future use. Only write 0.
8 Reserved 0 1 Reserved for future use. Only write 0.
7 Reserved 0 1 Reserved for future use. Only write 0.
6 Reserved 0 1 Reserved for future use. Only write 0.
5 Reserved 0 1 Reserved for future use. Only write 0.
4 Reserved 0 1 Reserved for future use. Only write 0.
3 VDS_UV_WARNING 0 1 Latched to 1 when the VDS input is below MFR_VDS_MIN_WARN_LIMIT.
2 VDS_OV_WARNING 0 1 Latched to 1 when the VDS input is above MFR_VDS_MAX_WARN_LIMIT.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
Table 36. MFR_SYSTEM_STATUS2 (9xE1) R/W1C, MFR_SYS_STAT2_SET (0xFECC) R/W1S, MFR_STAT2_ALERT_MASK (0xFEDC) R/W (Continued)
Default 0xE1,
Bit Name 0xFECC Default 0xFEDC Operation
1 IOUT_UC_WARNING 0 1 Indicates that the IOUT current is below warning limit in
MFR_IOUT_UC_WARN_LIMIT.
0 PIN_UP_WARNING 0 1 Indicates that the PIN power is below warning limit in
MFR_PIN_UP_WARN_LIMIT.
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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Data Sheet LTC4286
APPLICATIONS INFORMATION
1 This table is common to all eight GPIO pins with n to be replaced by the GPIO number (1 to 8).
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Data Sheet LTC4286
APPLICATIONS INFORMATION
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Data Sheet LTC4286
TYPICAL APPLICATION
RELATED PARTS
Table 50. Related Part Numbers
Part Number Description Comments
LTC4260 Positive high voltage hot-Swap controller with 8-bit ADC monitoring current and voltages, supplies from 8.5 V to 80 V, single MOSFET driver.
I2C compatible monitoring
LTC4238 High voltage high current hot-swap controller Operates from 6.5 V to 80 V, compatible with LTC4286 with COMM/GPIO5 pins, dual MOSFET
drivers.
ADM1272 High voltage positive hot-swap controller and Operates from 16 V to 80 V, single MOSFET driver.
digital power monitor with PMBus
LTC4282 High current hot-swap controller with I2C Operates from 2.9 V to 33 V, 12-bit ADC monitoring current, voltage, and power, dual MOSFET
compatible monitoring drivers.
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Data Sheet LTC4286
OUTLINE DIMENSIONS
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Data Sheet LTC4286
OUTLINE DIMENSIONS
EVALUATION BOARDS
Model1 Description
EVAL-LTC4286-A1Z Evaluation Board
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2023 Analog Devices, Inc. All rights reserved. Trademarks and Rev. A | 43 of 43
registered trademarks are the property of their respective owners.
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