CoAsia SEMI

FIFO verification

2023.10.15
CoAsia SEMI VN DC
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1. Overview of Design Verification
2. FIFO verification
3. How to use Vivado
1. Overview of Design Verification
 RTL Verification flow

What is the goal of verification?

The goal of hardware design is to create a device that performs a particular task, such as a DVD
player, network router, or radar signal processor, based on a design specification.

As a verification engineer,
Not only do you have to understand the design and its intent, but also, you have
to consider all the corner test cases that the designer might not have thought about.

Directed test coverage

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 RTL Verification flow

Design
- Each functional must have at Requirement
- Check testbench the testbench andand waveform
least 1 coverage.
waveform
to
-- Test confirm to
that
environmentconfirm
stimulus thatisdiagram
block the
Functional
Analyzeisthe related to input
design requirement ports
stimulus
correct
-are Description correct
for all component in
Functional Analysis
Design Testplan
and used
design to specification
generate stimulus and Specification Creation
-the Check the DUT behavior to
environment
should
-confirm List allhave a coverage,
functional thechecker
ofworking design Checker/coverage plan
-isDescription that DUT is
for all checker and in
not required.
properly
coverage Design
Test environment Test environment
- Functional related to output
-Note:
Implementation Implementation
Tracing
Dead code
DUT analyze
problem if possible
if possible specification
ports
- Each functional should must
or internal signals have a
Note:
have
tag and a coverage
reference and a checker.
to the related
Testbench
-document problem:
Driver should have dataflow Simulation
-diagram Update test environment, rerun
-the Note:
Function which covered
test to confirm that theby
-other
Coverage
functioncan should
be implement
be ignored FALSE FALSE
testbench
Require: problem is fixed and Passed
using
and must covergroup
be noted. or SVA
DUT
The functional
is working
-- Review isproperly.
covered. TRUE
Checker can be implement using
testbench
Required: code or SVA Coverage
DUT problem: Analysis

-- ReportReviewan issue to designer to

- Review
Done
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2. FIFO verification
 2. FIFO verification
Step 1: Read Design requirement and create Testplan
• Functional analysis: list all function of FIFO (fifo read, fifo write, fifo full, fifo empty…)
• Create checker for the function: ensure that this function work correctly.
• Make sequence for the function that will be implemented by test code.

3. Make sequence flow

1.Functional analysis
2.Checker for each func

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 2. FIFO verification
Step 2: Test environment specification
 Driver: drive the input signal to DUT
Ex: write transaction, read transaction.
 Monitor: capture transaction
Driver to DUT <input monitor>
Output <output monitor>
 Scoreboard: compare data between input and
output.
Ex: drive a transaction with wdata=0xff
 expectation: when read data rdata=0xff.
If wdata != rdata, Scoreboard will inform the error.

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 2. FIFO verification
 Idea for driver
• We declare ‘task’ that supply DUT input for read or write
transaction.
Whenever need to send transaction to DUT. We just call the task
fifo_read, fifo_write or something task like that

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 2. FIFO verification
 Idea for monitor
• We declare ‘task’ that always look at input and output interface. Whenever DUT receive a transaction through input,
or send a transaction through output. Monitor must capture them.

 Idea for scoreboard

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 2. FIFO verification

Some System Verilog syntax is useful for verification FIFO

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3. How to use Vivado
 3. How to use Vivado

 Open Vivado
Execute these command

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 3. How to use Vivado

 Create project

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 3. How to use Vivado

 Create project

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 3. How to use Vivado

 Create project

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 3. How to use Vivado

 Create project

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 3. How to use Vivado

 Select RTL files, or create them after

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 3. How to use Vivado

 Next to end and finish

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 3. How to use Vivado

 Working space

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 3. How to use Vivado

 Setting for simulation

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 3. How to use Vivado

 Add file testbench to project

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 3. How to use Vivado
 Set tb.sv file as top

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 3. How to use Vivado
Result of simulation

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 Thank you

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