Name: Manan Kalavadia

Roll No.: 200553

Lab Report – 4

Experiment 1:
Objective: Measure Transfer characteristics of NMOS
Design:

Simulation:
 • Slope = 0.0316.
• Intercept = -0.0443
• 𝛽 N = 1.99 m A/V2
• VTN = 1.4 V

Experimental Results:
VGS (V) ID(A) VGS(V) ID(A) VGS(V) ID(A) VGS(V) ID(A)
2.04E-01 0.00E+00 1.20E+00 0.00E+00 2.05E+00 8.00E-05 3.15E+00 9.12E-04
3.00E-01 0.00E+00 1.30E+00 0.00E+00 2.20E+00 1.42E-04 3.25E+00 1.00E-03
4.00E-01 0.00E+00 1.40E+00 0.00E+00 2.30E+00 2.00E-04 3.36E+00 1.10E-03
5.00E-01 0.00E+00 1.54E+00 1.60E-06 2.45E+00 2.80E-04 3.50E+00 1.30E-03
6.00E-01 0.00E+00 1.65E+00 7.25E-06 2.52E+00 3.95E-04 3.65E+00 1.47E-03
7.00E-01 0.00E+00 1.70E+00 1.30E-05 2.61E+00 4.65E-04 4.00E+00 1.80E-03
8.00E-01 0.00E+00 1.80E+00 2.80E-05 2.75E+00 5.45E-04 4.20E+00 2.15E-03
9.00E-01 0.00E+00 1.85E+00 3.39E-05 2.88E+00 6.60E-04 4.52E+00 2.65E-03
1.00E+00 0.00E+00 1.91E+00 4.60E-05 2.99E+00 7.50E-04 4.75E+00 3.20E-03
1.10E+00 0.00E+00 2.00E+00 6.80E-05 3.06E+00 8.26E-04 5.00E+00 3.60E-03
 4.00E-03
3.50E-03
3.00E-03
2.50E-03
2.00E-03
Id (A)

1.50E-03
1.00E-03
5.00E-04
0.00E+00
0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00
-5.00E-04
V GS (V)

0.07

0.06

0.05

0.04
SQRT( Id )

0.03

0.02

0.01

0
0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00
-0.01
V GS (V)

• Slope = 0.013589
• Intercept = -0.01345
• 𝛽 N = 369 u A/V2
• VTN = 0.99 V

Conclusions: The current in the NMOS follows a parabolic equation/law with respect to
VGS, after a certain value of VGS called threshold voltage VTn. Hence the graph obtained is a
parabolic graph.

Experiment 2:
Objective: Measure output characteristics of NMOS.
Design:
Simulations:

• VG = 3 V
• VDS(Sat) = 1.5 V
• VG - VTN = 3 – 1.5 = 1.5 V (close to VDS(Sat))
Experimental Results:

VDS(V) ID(A) VDS(V) ID(A) VDS(V) ID(A)

0 0 0.54 8.55E-04 1.45 9.37E-04
0.05 1.75E-04 0.62 8.63E-04 1.53 9.38E-04
0.1 3.50E-04 0.75 9.08E-04 1.65 9.39E-04
0.15 4.80E-04 0.82 9.16E-04 1.75 9.40E-04
0.2 6.25E-04 0.91 9.24E-04 1.82 9.40E-04
0.3 7.00E-04 1.02 9.26E-04 2 9.42E-04
0.35 7.57E-04 1.12 9.31E-04 2.15 9.43E-04
0.41 7.85E-04 1.23 9.34E-04 2.25 9.49E-04
0.46 8.20E-04 1.37 9.35E-04

0.001

0.0009

0.0008

0.0007

0.0006
Id (A)

0.0005

0.0004

0.0003

0.0002

0.0001

0
0 0.5 1 V DS (V) 1.5 2 2.5

• VG = 1.95V
• VDS(Sat) = 0.91 V
• VG - VTN = 1.95 – 0.99= 0.95 V (close to VDS(Sat))

Conclusions: For smaller value of VDS, the current obeys parabolic graph with VDS, but the
current in the NMOS gets saturated after a certain value of VDS, called VDS(Sat). After VDS(Sat),
the current almost remains same for every value of VDS (>VDS(Sat)).
Therefore we obtained the above graph in the experiment.

Experiment 3
Objective: Measure transfer characteristics of PMOS
Design:
Simulations:
 • Slope = 0.007
• Intercept = -0.0118
• 𝛽 P = 98 u A/V2
• VTP = 1.685 V

Experimental Results:
VSG(V) ID(A) VSG(V) ID(A) VSG(V) ID(A)
5.00E+00 4.50E-03 3.38E+00 1.95E-03 1.89E+00 3.00E-04
4.88E+00 4.50E-03 3.20E+00 1.64E-03 1.79E+00 2.04E-04
4.52E+00 3.67E-03 3.02E+00 1.42E-03 1.70E+00 1.22E-04
4.42E+00 3.53E-03 3.00E+00 1.35E-03 1.53E+00 7.70E-05
4.36E+00 3.37E-03 2.85E+00 1.19E-03 1.32E+00 5.00E-05
4.30E+00 3.21E-03 2.65E+00 1.00E-03 1.00E+00 1.00E-05
4.11E+00 2.88E-03 2.59E+00 9.00E-04 9.00E-01 0.00E+00
4.05E+00 2.70E-03 2.53E+00 7.85E-04 6.00E-01 0.00E+00
3.84E+00 2.49E-03 2.31E+00 6.57E-04 3.00E-01 0.00E+00
3.61E+00 2.15E-03 2.21E+00 5.62E-04 0.00E+00 0.00E+00
 5.00E-03

4.00E-03

3.00E-03
Id (A)
2.00E-03

1.00E-03

0.00E+00
0 1 2 3 4 5 6
-1.00E-03
V SG(V)

0.08

0.07

0.06

0.05
SQRT(Id)

0.04

0.03

0.02

0.01

0
0 1 2 3 4 5 6
-0.01
V SG(V)

• Slope = 0.01547
• Intercept = -0.01004
• 𝛽 P = 478 u A/V2
• VTP = -0.649 V

Conclusions: The current in the PMOS follows a parabolic equation/law with respect to
VSG, after a certain value of VSG called threshold voltage |VTp| . Hence the graph obtained is
a parabolic graph.

Experiment 4
Objective: Measure voltage transfer characteristics of CMOS Inverter
Design:

Simulations:

• VM = 2.2 V

Experimental Results:
Vin(V) Vout(V) Vin(V) Vout(V) Vin(V) Vout(V) Vin(V) Vout(V)
0.00E+00 5 1.29E+00 4.87 2.50E+00 4.4 3.50E+00 1.10E-05
1.51E-01 4.94 1.37E+00 4.87 2.60E+00 2.64 3.56E+00 3.00E-06
3.02E-01 4.89 1.58E+00 4.85 2.68E+00 1.00E-03 3.68E+00 0.00E+00
3.71E-01 4.88 1.69E+00 4.85 2.76E+00 2.96E-04 4.00E+00 0.00E+00
4.06E-01 4.87 1.83E+00 4.83 2.84E+00 2.17E-04 4.20E+00 0.00E+00
6.80E-01 4.87 1.96E+00 4.82 2.91E+00 1.61E-04 4.40E+00 0.00E+00
8.04E-01 4.87 2.03E+00 4.79 3.00E+00 1.09E-04 4.60E+00 0.00E+00
8.95E-01 4.87 2.20E+00 4.65 3.17E+00 7.00E-05 4.80E+00 0.00E+00
1.08E+00 4.87 2.27E+00 4.64 3.20E+00 3.90E-05 5.00E+00 0.00E+00
1.14E+00 4.87 2.40E+00 4.55 3.38E+00 2.40E-05
 6

Vout (v) 4

0
0 1 2 3 4 5 6
-1
Vin (V)

• VM = 2.583 V

Conclusions: When Vin is smaller than VTn, NMOS is cut-off and PMOS is ON, hence the
VOUT = VDD. Then the NMOS gets ON and outputs starts to decrease but still remains close to
VDD. After Inverter Threshold voltage VM, the VOUT decreases steeply and becomes closer to
0V. After Vin greater then VDD - |VTp|, the PMOS gets off and NMOS is ON, so VOUT becomes
0V.