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Lab 7 - COA

The document contains VHDL code for designing basic digital logic circuits including a D flip-flop, 4-bit shift register, and 6-bit counter. The D flip-flop code describes a behavioral model with an if statement that assigns the output based on the clock and reset signals. The shift register code uses four D flip-flops in a structural model to shift input bits through each stage. The 6-bit counter code implements a modulo-6 counter using three D flip-flops, combinational logic, and a reset signal.

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ABHYANSH SHRIVASTAVA
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32 views3 pages

Lab 7 - COA

The document contains VHDL code for designing basic digital logic circuits including a D flip-flop, 4-bit shift register, and 6-bit counter. The D flip-flop code describes a behavioral model with an if statement that assigns the output based on the clock and reset signals. The shift register code uses four D flip-flops in a structural model to shift input bits through each stage. The 6-bit counter code implements a modulo-6 counter using three D flip-flops, combinational logic, and a reset signal.

Uploaded by

ABHYANSH SHRIVASTAVA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 7

VHDL module for D flip flop:


entity DFF is begin
port ( if (clk'event and clk = '1') then
d, reset, clk : in std_logic; if (reset = '1') then
q : out std_logic q <= '0';
); else
end DFF; q <= d;
end if;
architecture Behavioral of DFF is end if;
begin end process;
process (d, reset, clk) end Behavioral;

VHDL module for Shift register:


entity SISO_Shift_Register is );
port ( end component;
serial_in : in std_logic;
reset : in std_logic; signal q0, q1, q2 : std_logic;
shift_in : in std_logic; begin
shift_out : out std_logic -- Instantiate D flip-flops
); FF0: DFF port map (shift_in, reset, clk, q0);
end SISO_Shift_Register; FF1: DFF port map (q0, reset, clk, q1);
architecture Structural of SISO_Shift_Register FF2: DFF port map (q1, reset, clk, q2);
is FF3: DFF port map (q2, reset, clk,
component DFF is shift_out));
port (
d, reset, clk : in std_logic; end Structural;
q : out std_logic

TEST BENCH
LIBRARY ieee; L7_E1_201b085_4_bit_s
USE ieee.std_logic_1164.ALL; hift_TB IS END
ENTITY L7_E1_201b085_4_bit_s
Abhyansh Shrivastava
201B013 B1
hift_TB; Data_op => Data_op
);
ARCHITECTURE
clk_process
behavior OF
:process
L7_E1_201b085_4_bit_s
begin
hift_TB IS clk <= '0';
COMPONENT wait for
L7_E1_201b085_4_bit_s clk_period/2;
hift_register clk <= '1';
PORT( wait for clk_period/2;
Serial_ip : IN end
std_logic; reset process;
: IN std_logic; stim_proc:
clk : IN process
std_logic; begin
Data_op : OUT reset <= '0';
std_logic Serial_ip <='0';
); wait for 100 ns;
END COMPONENT; Serial_ip <='1';
signal Serial_ip : wait for 100 ns;
std_logic := '0'; Serial_ip <='1';
signal reset : wait for 100 ns;
std_logic := '0'; Serial_ip <='1';
signal clk : wait for 100 ns;
std_logic := '0'; Serial_ip <='0';
signal Data_op : wait for 100 ns;
std_logic; Serial_ip <='0';
wait for 100 ns;
constant clk_period :
Serial_ip <='1';
time := 10 ns; BEGIN
reset <= '1';
uut: wait for
L7_E1_201b085_4_bit_shift_re
100 ns;
gister PORT MAP ( Serial_ip =>
wait;
Serial_ip,
end
reset => process;
reset, clk END;
=> clk,

Abhyansh Shrivastava
201B013 B1
MOD6 COUNTER VHDL CODE
library IEEE; clk : in STD_LOGIC; reset : in STD_LOGIC;
use IEEE.STD_LOGIC_1164.ALL; Q : out STD_LOGIC;
entity L7_E2_201b085_mod6_counter is Port ntQ : out STD_LOGIC); end component;
( D : in STD_LOGIC; begin
clk : in STD_LOGIC; qA,qB : out D1: L7_E2_201b085_D_flip_flop
STD_LOGIC; port map(w0,clk,RST,q0,w0);
qC : out STD_LOGIC); qA <= q0;
end L7_E2_201b085_mod6_counter; D2: L7_E2_201b085_D_flip_flop
architecture Behavioral of port map(w1,w0,RST,q1,w1);
L7_E2_201b085_mod6_counter is signal qB <= q1;
w0,w1,w2 : STD_LOGIC; D3: L7_E2_201b085_D_flip_flop
signal q0,q1,q2 : STD_LOGIC; signal RST : port map(w2,w1,RST,q2,w2);
STD_LOGIC; qC <= q2;
component L7_E2_201b085_D_flip_flop Port RST <= q1 AND q2;
( D : in STD_LOGIC; end Behavioral;

Abhyansh Shrivastava
201B013 B1

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