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The document is a semester end examination question paper for an Advanced Digital Design course. It contains 10 questions divided across 5 units. The questions assess various concepts of digital design including Verilog modeling of logic gates and modules, digital logic design using multiplexers, writing Verilog code for counters, functions and tasks, logic synthesis process and design methodologies. Students have to answer one full question from each unit dealing with concepts like modeling delays, encoding, initializing arrays, modulo counters and edge detection algorithms.

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22 views2 pages

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The document is a semester end examination question paper for an Advanced Digital Design course. It contains 10 questions divided across 5 units. The questions assess various concepts of digital design including Verilog modeling of logic gates and modules, digital logic design using multiplexers, writing Verilog code for counters, functions and tasks, logic synthesis process and design methodologies. Students have to answer one full question from each unit dealing with concepts like modeling delays, encoding, initializing arrays, modulo counters and edge detection algorithms.

Uploaded by

1ms21ec132
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE552

USN 1 M S
(Autonomous Institute, Affiliated to VTU)
(Approved by AICTE, New Delhi & Govt. of Karnataka)
Accredited by NBA & NAAC with ‘A+’ Grade

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SEMESTER END EXAMINATIONS – JANUARY 2023
B.E. – Electronics and Communication
Program : Semester : V
Engineering
Course Name : Advanced Digital Design Max. Marks : 100
Course Code : ECE552 Duration : 3 Hrs

Instructions to the Candidates:


 Answer one full question from each unit.

UNIT - I
1. a) Write verilog description for the gate level representation of module Y CO1 (08)
with delay as shown below.

b) Write Verilog code for a 4-Bit Ripple Carry Full Adder in gate level CO1 (06)
modeling. The full adder is made up of two half adders.
c) Illustrate VLSI design flow with a flow chart. CO1 (06)

2. a) Differentiate ASIC flow with SoC flow with flow charts. Also explain any CO1 (08)
2 blocks in detail.
b) Compare bitwise, logical and reduction operators with suitable examples. CO1 (06)
c) Explain the different types of gate delays in Verilog from input to output CO1 (06)
with examples.

UNIT - II
3. a) Write a Verilog model for an encoder for use in a domestic burglar alarm CO2 (10)
that has sensors for each of eight zones. Each sensor signal output is 1
when an intrusion is detected in that zone and 0 otherwise. The encoder
has three bits of output, encoding the zone has follows: Zone 1:000,
Zone2: 001, Zone 3: 010, Zone 4: 011, Zone 5:100, Zone 6:101,
Zone 7: 110, Zone8: 111.
b) Design a Verilog code to initialize all even locations of an array element CO2 (10)
with 0 and all odd locations with 1. Assume size of the array element
as 32.

4. a) Design and develop a circuit and Verilog module for modulo 10 counters. CO2 (10)
b) Realize the following: CO2 (10)
(i) 13:1 mux using 2:1 and 4:1 mux
(ii) Full adder using 4:1 mux
Use necessary diagram, truth table and expressions.

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ECE552
UNIT - III
5. a) Write Verilog code to convert an unsigned 4-bit binary number into CO3 (10)
decimal number using task statement.
b) Write Verilog code for a function to calculate the factorial of a 4 bit CO3 (10)

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number. The output is a 32 bit value. Invoke the function by using
stimulus.

6. a) Distinguish between Function and task. CO3 (06)


b) Define a task to design an 8 function ALU that takes two 4-bit numbers CO3 (14)
a and b and computes a 5 bit result out based on a 3 bit select signal.
Apply the stimulus for the same. The five functions are:
i. Output zero
ii. Equality
iii. Add
iv. Subtract
v. Multiply.

UNIT- IV
7. a) Describe the synthesis design flow from RTL description to an optimized CO4 (10)
gate-level description with the help of flow diagram.
b) What is the inference of logic synthesis tool for the following: CO4 (10)
(i)
always (posedge clock)
if (reset)
target <= 0;
else if (clock_en)
target <= input;
(ii)
always @(posedge clock)
if (reset) target <= 0;
else if (shift_en)
target <= {data_in, target[3:1]};

8. a) What is a logic synthesis process? Illustrate the basic CAD synthesis CO4 (10)
process with block diagram.
b) What are the advantages of automated logic synthesis tool over manual CO4 (10)
design process?

UNIT - V
9. a) Design a synchronous counter to count the sequence 0-2-3-6-5-1 using CO5 (10)
JK flip flop. Also write the state table, state diagram and logic diagram
and Verilog description for the counter using JK flipflop.
b) Design the Sobel Edge Detection algorithm using Pseudo code. CO5 (10)

10. a) Design a BCD adder using 4bit binary adder. Develop a Verilog RTL for CO5 (10)
the same.
b) Explain the following design methodologies. CO5 (10)
i) Architecture exploration
ii) Functional verification
iii) Physical area optimization.

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