IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.

12, DECEMBER 2003 2209

A 5-GHz Direct-Conversion CMOS Transceiver

Utilizing Automatic Frequency Control for the
IEEE 802.11a Wireless LAN Standard
Arya R. Behzad, Senior Member, IEEE, Zhong Ming Shi, Senior Member, IEEE, Seema Butala Anand, Li Lin,
Keith A. Carter, Member, IEEE, Michael S. Kappes, Member, IEEE, Tsung-Hsien (Eric) Lin, Member, IEEE,
Thinh Nguyen, Member, IEEE, Dan Yuan, Stephen Wu, Y. C. Wong, Victor Fong, and
Ahmadreza Rofougaran, Member, IEEE

Abstract—A fully integrated CMOS direct-conversion 5-GHz are several reported 5-GHz CMOS papers on RF transceivers
transceiver with automatic frequency control is implemented in [2]–[7] and frequency synthesizers [8], [9]. A fully integrated
a 0.18- m digital CMOS process and housed in an LPCC-48 CMOS direct-conversion 5-GHz transceiver with automatic
package. This chip, along with a companion baseband chip,
provides a complete 802.11a solution frequency control (AFC) is implemented in a 0.18- m digital
The transceiver consumes 150 mW in receive mode and 380 mW CMOS process and housed in an LPCC-48 package [10].
+
in transmit mode while transmitting 15-dBm output power. This chip along with a companion baseband chip provides a
The receiver achieves a sensitivity of better than 93.7 dBm and complete 802.11a solution. As compared with the previously
73.9 dBm for 6 Mb/s and 54 Mb/s, respectively (even using reported work [2]–[7], this paper presents the highest level of
hard-decision decoding). The transceiver achieves a 4-dB receive
+
noise figure and a 23-dBm transmitter saturated output power. integration, the lowest achieved power consumption in both
transmit (380 mW at 15-dBm Tx power) and receive (150 mW)
The transmitter also achieves a transmit error vactor magnitude
of 33 dB. The IC occupies a total die area of 11.7 mm2 and is modes, the lowest achieved noise figure (4 dB) and sensitivity
packaged in a 48-pin LPCC package. The chip passes better than ( 93.7 dBm for 6 Mb/s), the highest reported transmit power
2.5-kV ESD performance. Various integrated self-contained or (23-dBm saturated power), and the smallest reported die size
system-level calibration capabilities allow for high performance
and high yield. (11.7 mm square).
The 802.11a standard utilizes different modulation types
Index Terms—Amplifier linearization, automatic frequency con- ranging from BPSK to QAM64 to achieve variable data rates
trol, class-AB amplifier, direct conversion, IEEE 802.11a, orthog-
onal frequency division multiplexing (OFDM), power amplifier, (Fig. 1). Within a modulation type, the data rate can be slightly
RF transceiver, receiver, synthesizer, transconductance lineariza- modified by using a different coding rate. Multiple access for
tion, transmitter, wireless LAN (WLAN). the standard is provided by frequency-division multiplexing
and carrier-sense multiple access collision avoidance schemes.
The Rx–Tx and Tx–Rx turnaround times can be inferred
I. INTRODUCTION
from the minimum interframe spacing (16 s) requirement

I N THE PAST several years, the demand for wireless LAN

(WLAN) technology has grown significantly. Along with
this growth in demand has come an increased interest in more
of the standard and is typically required to be less than a few
microseconds (depending on the PHY and the MAC decoding
delays). The OFDM modulated signal is made of 48 data and
than the maximum 11 Mb/s offered by the 802.11b standard. four pilot subcarriers, with the subcarriers spaced 312.5 kHz
The IEEE 802.11a WLAN protocol provides data rates up to apart. Signal bandwidth is 16.25 MHz per channel with a
54 Mb/s using a 20-MHz channel bandwidth in the 5-GHz 20-MHz channel spacing. A 20-MHz channel spacing is used
unlicensed national information infrastructure (UNII) band to reduce the interchannel interference.
[1]. The data is modulated with BPSK, QPSK, 16QAM, or In the U.S., three bands are specified for the 802.11a standard
64QAM, and further mapped into 52 subcarriers of an orthog- (Fig. 2). Each band constitutes four channels. The maximum
onal frequency division multiplexing (OFDM) signal. There allowed transmit power is 16, 23, and 29 dBm, respectively, for
channels residing in the lowest, mid, and highest bands.
At the lowest data rate of 6 Mb/s, the standard requires a
Manuscript received April 21, 2003; revised July 16, 2003. minimum sensitivity of 82 dBm and at the highest data rate
A. R. Behzad, M. S. Kappes, and Y. C. Wong are with Broadcom Corporation,
San Diego, CA 92128 USA (e-mail: [email protected]). of 54 Mb/s, it requires a minimum sensitivity of 65 dBm.
Z. M. Shi was with Broadcom Corporation, San Diego, CA 92128 USA. The reduction in sensitivity for the higher data rates is due to
S. B. Anand, K. A. Carter, T.-H. Lin, S. Wu, and A. Rofougaran are with the need for higher signal-to-noise ratios (SNRs) for the higher
Broadcom Corporation, Irvine, CA 92618 USA.
L. Lin is with Berkana Wireless, Inc., Campbell, CA 95008 USA. order modulation types.
T. Nguyen is with Texas Instruments Incorporated, Sunnyvale, CA 94089 Error vector magnitude (EVM) is the parameter used to in-
USA. dicate the quality of digitally modulated signals. EVM takes
D. Yuan is with Qualcomm Inc., San Diego, CA 92121 USA.
V. Fong is with Broadcom Corporation, San Jose, CA 95134 USA. into account signal impairments such as phase and amplitude
Digital Object Identifier 10.1109/JSSC.2003.819085 mismatches, in-band frequency rolloffs, phase noise, thermal
0018-9200/03$17.00 © 2003 IEEE
2210 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

Fig. 1. IEEE 802.11a data rate versus modulation.

II. ARCHITECTURE AND CIRCUIT IMPLEMENTATION

The goal of this work is to achieve the lowest cost, highest
performance, and lowest power consumption radio for the
802.11a standard. It is therefore decided to use a direct con-
version architecture without requiring any external filters. To
allow for low cost and in addition to allow for future integration
with digital signal processing (DSP), a CMOS process is
chosen. Furthermore, an integrated power amplifier (PA) is
Fig. 2. IEEE 802.11a channel allocation and power levels in the U.S.
added to the transmitter to reduce the bill-of-materials cost.
Finally, extensive use of autocalibration schemes enhances
noise, nonlinearity, and any other source of induced noise. The performance and increases yield.
802.11a standard requires the transmitter to have an EVM better However, these choices result in a host of challenges that need
than 25 dB for a QAM64 modulated signal. This level of to be dealt with in the architectural implementation and/or in
EVM ensures that a “good receiver” would be able to achieve a the circuit design of the blocks. For example, the choice of a
low packet-error rate (PER) when receiving such a signal. The direct conversion architecture with an integrated PA requires the
standard specifies the interference performance when a max- designer to deal with the following issues.
imum PER can be achieved with a signal level 3-dB above the • DC offsets which result from self-mixing of the receive
minimum sensitivity level while the interferences are at certain mixer as well as dc offsets which result from baseband
power levels and at certain offset frequencies. For example, the block mismatches and the high gain of the baseband stages
receiver should have a sensitivity at least 3-dB above the require- will result in clipping of the subsequent stages if not prop-
ments when the adjacent channel interference is at a power level erly rejected.
of 66 dBm and the alternative adjacent channel interference is • Flicker noise on the receive path can impair the SNR of
at 50 dBm. the lowest index OFDM subcarriers.
The standard requires a crystal frequency tolerance of • The receive baseband path can have potential oscillation
20 ppm. This translates into a maximum frequency offset of problems due to the fact that most of the receive path gain
107 kHz at the carrier frequency of 5.35 GHz. In the worse is implemented at a single frequency (baseband).
case when the transmitter and the receiver are both off by • The transmit path can have potential oscillation problems
this amount, a maximum frequency offset of 214 kHz will since large amounts of gain are required at the 5-GHz RF
be observed. This fairly loose requirement of the standard on frequency.
frequency tolerance of the crystal is the fundamental reason • Local oscillator (LO) pulling issues by the on-chip PA can
for the need of a mixed-mode (analog and digital) frequency cause system problems.
correction mechanism in receivers that employ a zero-IF fre- • LO feedthrough issues on the transmitter have to be dealt
quency as their final IF stage (with a direct conversion receiver with.
being one such receiver). • The on-chip power amplifier is required to have a very
The transceiver presented in this paper along with its base- high linearity in order to be able to accommodate the large
band counterpart satisfies the requirements of the 802.11a stan- peak-to-average ratios present in the OFDM signal.
dard as outlined in the previous paragraphs. Section II describes Among the autocalibration schemes that are incorporated in this
the architecture of choice for this work as well as details of the radio, the AFC is the most challenging to implement and will be
receiver, transmitter, and phase-locked loop (PLL) sections of discussed in detail in Section IV.
the radio. Section III describes the details of the mixed-mode The simplified radio architecture is shown in Fig. 3. The
AFC blocks. Measurement results are presented in Section IV. transceiver consists of a receiver (RX), a transmitter (TX),
BEHZAD et al.: 5-GHz DIRECT-CONVERSION CMOS TRANSCEIVER UTILIZING AFC FOR THE IEEE 802.11a WLAN STANDARD 2211

entire signal path is differential but is shown as single-ended

after the LNA for the sake of simplicity. The receiver front-end
includes on-chip matching for the 5-GHz input. A high-gain
low-noise high-linearity and gain-controllable front-end allows
for optimal system tradeoffs between sensitivity and linearity.
The RX gain is carefully distributed before and after the mixers
to minimize the noise contribution to the overall system
noise figure (NF). Three stages of HPVGAs are incorporated
throughout the baseband signal path and provide both high gain
and dc offset rejection. These HPVGAs are programmable in
3-dB gain steps from 0 to 21 dB (0–18 dB for the last HPVGA).
Since the preamble duration is 16 s, the dc offset cancellation
has to be very fast, and at the same time, it must not attenuate
the lowest subcarriers of the signal. Therefore, the HPVGAs
Fig. 3. Simplified transceiver architecture. are designed to accommodate dynamic dc offsets which result
from gain changes. A fifth-order Chebyshev LPF is integrated
between the first and second HPVGAs that acts to reject any
continuous-wave (CW) or modulated interferers. The LPF is
automatically calibrated within 2% tolerance to ensure pre-
cise channel selection. Dual receive signal strength indicators
(RSSIs) are integrated before and after the LPF. These RSSIs
allow for the system to determine whether a received signal
strength is dominated by an out-of-band interference signal or
by an in-band desired signal. For example, if the second RSSI
Fig. 4. Receiver block diagram. output voltage is smaller than the first, this will be an indication
that the large incoming signal is due to an out-of-band interfer-
ence. Based on this determination, optimal front-end gain can
a frequency synthesizer, a high-speed custom JTAG digital be set for the proper tradeoff between sensitivity and linearity.
control block, and calibration blocks for bias currents ( ) The receiver NF and gain (as measured with a noise head)
and RC time constants. A fully differential signal path is used as a function of the baseband frequency is shown in Fig. 5(a).
throughout the transceiver to reduce LO feedthrough, LO Note that the axis is in logarithmic scale. An average NF of
leakage, and common-mode noise. The calibration block better than 4 dB in the receive path is achieved. It is also im-
uses an external 1% resistor to generate a code for various portant to note that the NF at the frequency of the lowest fre-
bandgap circuits, resulting in biasing independent of on-chip quency subcarriers is maintained to better than 5.5 dB, allowing
resistance variations. The RC time constant calibration circuit for these subcarriers to maintain high SNR. The overall receiver
uses an RC-based oscillator with a reference provided by the transfer function with both high-pass and low-pass characteris-
crystal oscillator to generate a 5-bit time-constant code for tics are apparent in the gain plot of Fig. 5(a). The receiver sen-
the on-chip filters. RC calibration is performed at startup only sitivity is shown in Fig. 5(b) along with the 802.11a require-
since the variation of the resistors and capacitors utilized here ment as a reference. For the lowest data rate of 6 Mb/s, a typical
with temperature is small. An integrated temperature sensor sensitivity of 93.7 dBm and a standard deviation of 0.3 dB is
allows the DSP to make optimal system-level adjustments as achieved. At the highest data rate of 54 MB/s, a typical sen-
a function of temperature. The JTAG block controls all of the sitivity of 73.9 dBm and a standard deviation of 0.4 dB is
radio functions, including receive and transmit gain controls. achieved. All sensitivity measurements are obtained with the
The transceiver as shown, along with a companion baseband actual baseband companion chip to this RF transceiver. These
PHY/MAC chip, two external baluns, an optional bandpass sensitivity results are obtained using hard-decision decoding.
filter (BPF) and a TR/Diversity switch, constitute a full 802.11a Results obtained using soft-decision decoding would be even
system. We will now discuss each building block in more detail. better.

A. Receiver B. Transmitter
The receiver is shown in detail in Fig. 4. The RF signal is am- The transmitter block diagram is shown in Fig. 6. Like the re-
plified first by an on-chip tuned low-noise amplifier (LNA) and ceiver, the transmitter is based on a direct conversion architec-
then downconverted to baseband by two quadrature mixers. The ture and is fully integrated on chip. It incorporates third-order
output of the mixers is fed into the first high-pass variable gain Butterworth LPFs which receive the signals from the baseband
amplifier (HPVGA). The output of the first HPVGA is fed into and digital-to-analog converters (DACs). The outputs of
a fifth-order Chebyshev low-pass filter (LPF) for channel se- the LPFs are then applied to baseband VGAs. The signals are
lection. The output of the LPF is then fed to second and third directly upconverted to the RF frequency and combined before
HPVGAs. The outputs of the last HPVGA are passed on to an RF VGA. The signal is then amplified by a power amplifier
analog-to-digital converters (ADCs) on the baseband chip. The driver (PAD) and then applied to a high-linearity high-power
2212 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

(a) (b)
Fig. 5. (a) Measured receiver gain and NF versus frequency. (b) Sensitivity versus data rate.

Fig. 6. Transmitter block diagram.

integrated class-AB power amplifier. On-chip matching is pro-

vided for the PA. The transmitter incorporates baseband and RF
gain control for optimum tradeoff between linearity, noise, LO
feedthrough, balance, and power consumption. A gain con-
trol of 33 dB is provided at baseband, 3 dB at the mixer, and Fig. 7. Measured average output power versus data rate.
35 dB at the RF amplifiers. Some gain control is needed to com-
pensate for power variations resulting from changes in process, an efficiency of 32.9%. As the data rate is further reduced, the
temperature, and power supply. The gain control is also used to maximum transmit power can no longer be increased and is still
allow for transmit power control for the future versions of the limited by the spectral mask requirements. It is interesting to
802.11a standard. An integrated power detector allows for the note that if the spectral mask requirements were to be ignored,
DSP to set a constant output level in the presence of process, at the lowest data rates, a maximum transmit power equal to
temperature, or supply variations. A scheme for the cancella- the saturated output power of the transmitter 23 dBm could
tion of the LO feedthrough is also integrated in the transmitter. be achieved while still satisfying the EVM requirements of
This scheme utilizes DACs at the mixer transconductance stage the standard. It is also important to note that what is shown
to cancel out the LO feedthrough at RF. The transmitter shown on the axis is the average transmit power, and that during
in Fig. 6 achieves a 1-dB compression point of 19 dBm and a statistical peak excursions of the OFDM signal, output power
saturated output power of 23 dBm. levels significantly higher than the average level (at times equal
The measured transmit output power versus the data rate to the saturated power) are observed.
is shown in Fig. 7. At the highest data rates associated with Fig. 8(a) displays the measured transmitter output spectrum
QAM64 modulation, the maximum transmit power is limited to while transmitting a 12.8-dBm 54-Mb/s QAM64 modulated
12.8 dBm by the required EVM and the high peak-to-average signal. In this case, the maximum transmit power is limited by
ratio of the OFDM signal. Under these conditions, the inte- EVM requirements. In applications in which a higher 54-Mb/s
grated PA consumes 63 mA from 3.3 V and has an efficiency transmit power is required, an external PA can be used and the
of 9.2%. As the data rate is reduced and the modulation is internal gain of this chip can be backed off to account for the
switched to QAM16, the maximum transmit output power is gain of the external PA and the desired output power. Fig. 8(b),
limited equally by both the EVM requirements and the spectral on the other hand, displays a 18.7-dBm 36-Mb/s QAM16
mask requirements of the standard. For example, at 36 Mb/s, signal. In this case, the maximum transmit power is equally
a maximum transmit power of 18.7 dBm is achieved. In this limited by the EVM requirements as well as the spectral mask
case, the integrated PA consumes 77 mA from 3.3 V and has requirements.
BEHZAD et al.: 5-GHz DIRECT-CONVERSION CMOS TRANSCEIVER UTILIZING AFC FOR THE IEEE 802.11a WLAN STANDARD 2213

(a) (b)
Fig. 8. Measured output power spectrum. (a) EVM limited. 12.8 dBm, 54 Mb/s, QAM64. (b) EVM and spectral mask limited. 18.7 dBm, 36 Mb/s, QAM16.

Fig. 11. Simplified PLL architecture with AFC.

phase noise, thermal noise, nonlinearity, phase and amplitude

imbalance, and group delay are maintained to very tight toler-
ances. Note that the two darker constellation points on the real
Fig. 9. Measured constellation diagram at TX output (EVM = 033 dB, axis are from the pilot tones which are always transmitted with
+
QAM64, 54 Mb/s, 6 dBm). BPSK modulation. The histogram for 20 transmitted frames at
50 packets per frame for the same conditions as Fig. 9 is shown
in Fig. 10.

C. PLL
An external 20-MHz crystal is used with an on-chip oscil-
lator as a reference for the integer- PLL with programmable
loop bandwidth (Fig. 11). Various PLL-related issues typically
impair the operation of a direct conversion transceiver. These
impairments include pulling effects by the on-chip PA, large
in-band LO leakage, and large dc offsets as a result of LO
self-mixing. In order to reduce these impairments, a “fractional
VCO” is used in which the desired RF frequency is 1.5 times
higher than the VCO frequency [11]. Furthermore, in order
to reduce negative effects due to the crystal tolerance, a
mixed-mode AFC design is used.
Fig. 10. Measured EVM histogram at TX output for 50 frames of 20 packets The measured phase noise of the system is shown in Fig. 12.
+
each (QAM64, 54 Mb/s, 6 dBm). An in-band phase noise of 100 dBc/Hz at an offset frequency
of 30 kHz and with a carrier frequency of 5.24 GHz is achieved.
The measured constellation diagram of a QAM64 54-Mb/s The reference spurs are maintained to very low levels. The target
6-dBm transmitted signal with an EVM of 33 dB is shown specification over the bandwidth of one subcarrier is indicated
in Fig. 9. Recall that the 802.11a standard requires an EVM of by the solid line in Fig. 12. The integrated phase modulation
25 dB, and therefore, 8 dB of margin is present here. The fact within the bandwidth of one subcarrier is a very important factor
that the constellation points fall within a small radius around in the performance of an OFDM system and in this case is main-
the center of the crossing points of the constellation circles is tained to less than 0.45 . Also specified in the plot are the target
an indication of the high quality of the transmitted signal. This spot specifications at 8 and 50 MHz which determine the in-
is an indication that all transmit signal impairments, including terchannel interference performance of the system. Also shown
2214 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

Fig. 14. Mixed-mode AFC block diagram.

Fig. 12. Measured phase noise.

Tx) can be present in the received spectrum relative to the loca-

tion of the baseband filter poles. This could result in the lowest
frequency subcarrier as well as the highest subcarriers being
heavily attenuated by the receive filters (Fig. 13, middle graph).
This can have a severe impact on the EVM and PER of the re-
ceived signal. The situation can be even worse in the presence of
a multipath channel. Under a multipath environment, many of
the subcarriers are heavily attenuated by the channel, and as a
result the receiver has to rely on the unattenuated subcarriers
more heavily. When these subcarriers are subject to receiver
filter attenuation, overall system performance can degrade quite
severely (Fig. 13, lower graph).
Fig. 13. Subcarrier location with frequency offset. Most receivers require an automatic frequency correction in
order to correct for frequency offsets. However, the correction
is typically done entirely in the digital domain and would, there-
is the capability of the PLL to adjust the loop bandwidth using
fore, not be able to avoid the filtering problem described above.
JTAG programming. The loop bandwidth has greater than an
In the implementation described here, the system corrects for the
octave of tuning range (not shown in Fig. 12).
frequency offsets of the receiver and transmitter in the analog
domain, and therefore, eliminates the filtering of the desired
III. MIXED-MODE AFC AND LO GENERATION OFDM subcarriers. The estimation of the frequency offset and
A direct conversion receiver has to be able to reject dc offsets the generation of the correction baseband frequency, however,
which would result from self-mixing of the receive mixer or re- are done in the digital domain. Therefore, this operation takes
ceiver baseband mismatches. In order to accomplish this, some place in both the analog and the digital domains (hence, the term
form of a high-pass filter (HPF) would have to be used. In this mixed-mode AFC).
particular case, we have three HPFs distributed in the receive The block diagram of the mixed-mode AFC system is shown
path. The poles of these HPFs cannot be too low as they would in Fig. 14. During the receive cycle, the received in-phase and
result in long transient settling during gain changes or Tx-to-Rx quadrature-phase signals are applied to the baseband ADCs. A
switching. On the other hand, the poles cannot be placed too frequency estimation of the effective frequency offset is
high as they will attenuate the lowest OFDM subcarriers and, made (this estimation includes frequency offsets from the trans-
therefore, the system performance. In the ideal case and during mitting source as well as that from the receiver itself). As a
steady-state operation, the poles in the receiver described in result, correction frequency signals and are
this paper are placed at about 120 kHz during the payload re- generated in the digital domain and passed on to high-precision
ception (but are set wider during the preamble for fast settling low-offset DACs. These signals are then passed on to the radio
behavior). Fig. 13 shows an OFDM modulated signal with its chip where they are filtered. The AFC and signals are then
52 subcarriers and their payloads. The lowest subcarriers are at applied to the first set of mixers in the LO generation block.
312 kHz and the highest subcarriers are at 8.125 MHz. In Assuming a VCO frequency of 3.5 GHz, the first mixer would
the ideal case, as shown in the upper graph of Fig. 13, none of have an image-rejected output frequency of GHz .
the subcarriers are attenuated by the filter in the receive chain. This signal is then mixed with the VCO frequency in the second
However, since the standard requires only a 20 ppm crystal, a set of LO generation mixers resulting in the output frequency of
total of 214 kHz of frequency offset (107-kHz Rx plus 107-kHz GHz . In the transmit mode, is set to 0, and an
BEHZAD et al.: 5-GHz DIRECT-CONVERSION CMOS TRANSCEIVER UTILIZING AFC FOR THE IEEE 802.11a WLAN STANDARD 2215

Fig. 15. Block diagram of LO generation mixer.

output LO of 5.25 GHz is generated. The LO generation signal,

therefore, is constantly switching back and forth between the Tx
and the Rx frequencies, as shown in Fig. 14. Also note that in
order to reject the image of the AFC tone, the entire AFC signal
path is implemented in the complex form ( and ). In sum-
mary, the relations for the Rx and Tx LO outputs are

In practice, the correction frequency is no larger than

240 kHz.
It is important to note that in a 802.11a system, the AFC cor-
rection must occur on a per-packet basis. Therefore, it needs Fig. 16. Simplified schematic of LO generation mixer. (Only I -side shown
here.)
to occur during the preamble processing and, therefore, is re-
quired be quite fast. This fact along with potential spur prob-
lems rule out a fractional synthesizer as an alternative solution. Ideally, at the output of the first set of mixers, a single tone
Furthermore, unlike a cellular system in which the transmitter (a at would be present. However, in reality, due
base station) has excellent frequency accuracy, an 802.11a ac- to the nonideal image rejection of the mixers, an image tone
cess point is subject to the same frequency tolerance (20 ppm) as would also be present at . Additionally, due to
a client. Therefore, the receiver has to correct for the frequency the dc offsets at baseband, an LO feedthrough term exactly at
offsets of its own receiver and the transmitter. Since the trans- would be present. Finally, due to the nonlinearity of the
mitter can change from packet to packet, a static frequency cor- transconductance stage, third- and possibly second-order har-
rection similar to one commonly used in cell phones (using a monics of the AFC signal will be present at
VCXO) is not a feasible solution for a 802.11a system. In the and . All these spurs will be upconverted to the
system proposed here, no PLL settling is involved and the AFC final 5-GHz frequency by the second set of mixers (Mix5 and
correction is directly implemented in the LOGEN after the VCO Mix6). The challenge in the design of the LO generation mixer
and, therefore, requires very short time to settle to its final value. is to generate output signals large enough for the receive and
The simplified block diagram of the LO generation mixers transmit path mixers over temperature and process variations,
is shown in Fig. 15. The filtered AFC signals are applied to while maintaining these spurs to less than 40 dB below the de-
the transconductance stages (Gm1–Gm4) of the mixers. The re- sired signal. The simplified schematic of the in-phase side of the
sulting signals are gain controlled through current-mode gain- LO generation “stacked” mixers is shown in Fig. 16. A similar
control blocks VGA1–VGA4. The gain control is placed after block generates the desired quadrature-phase output.
the transconductance stage so that the dc offsets of the transcon- An AFC self-calibration mode is integrated in the system by
ductance stage scale with gain control. The resulting signals are which the LO feedthrough of the AFC block as well as the image
upconverted with an LO of and then further upconverted term in the AFC block can be automatically cancelled at startup.
with an LO of resulting in the desired output As previously discussed, the transconductance stages of the
frequency. The entire LOGEN is implemented in complex ( LO generation mixers (Gm1-Gm4 of Fig. 15) need to be oper-
and ) domain. ated in a linear region in order to avoid the generation of spu-
2216 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

Fig. 17. (a) Multisection class-AB offset G of AFC mixer. (b) Simulation results.

rious tones at the output of the mixers. Additionally, as shown linearized range of the transconductance curve. Due to
in Figs. 15 and 16, it is evident that minimal amount of head- the complex shape of the overall transconductance curve,
room should be utilized by the stage in order to be able to simple extrapolation concepts such as intercept points no
perform under the minimum supply voltage condition of 1.7 V. longer apply.
A pseudodifferential grounded differential amplifier [Gm_main • All the differential pairs described in this linearization
stage of Fig. 17(a)] has minimal headroom requirements. How- technique operate in class-AB mode with grounded
ever, as shown in the plot of transconductance versus incoming sources. The operation in this mode is quite different than
voltage of Fig. 17(b), such a stage exhibits large variation in linearization techniques operating in class-A mode with a
transconductance as a function of the incoming voltage. In this constant tail current source.
particular example, a variation of 700 S is observed over an • Unlike many other linearization techniques such as emitter
input signal voltage range of 400 to 400 mV, with a peak degeneration, this technique can achieve fairly large and
transconductance of 2.2 mS. By utilizing additional grounded linear transconductance levels simultaneously.
pseudodifferential amplifier stages Gm1–Gm4, each operating • For a given input voltage swing and a particular number of
with the same incoming ac signal, but shifted operating points stages with certain device sizes, an optimal offset voltage
implemented through dc IR drops as shown in Fig. 17(a), addi- can be found which results in a very large improvement
tional transconductances Gm1–Gm4 of Fig. 17(b) can be gener- over an uncompensated stage. However, if properly
ated. When all of these transconductances are added at the drains designed, the scheme is tolerant of reasonable size device
of the differential pair transistors, a much more linear transcon- mismatches and resultant offsets, and can result in several
ductance curve (Gm_overall) of Fig. 17(b) would be generated. decibels in linearity improvement even in the presence of
Over the same input voltage range, the enhanced design shows 3-sigma device mismatches.
an overall variation of 38 S with a peak transconductance of • As described here, the technique is applied to a low-fre-
6.97 mS. An overall transconductance variation of about 30% quency application. However, the general technique is
has been reduced to 0.5%. In this particular case, this reduction quite applicable to very high-frequency analog and RF
in transconductance variation results in more than 20-dB im- circuits.
provement in third harmonic distortion (HD3) performance. The • In this particular case, any improvement of 20 dB in lin-
improvement in HD3 performance for this linearization scheme earity is achieved for the nominal process corner and with
can be solved mathematically, however, the deviation is fairly no device mismatches. However, Monte Carlo simulations
algebraically involved and will not be presented here. Several show that under worst case process and 3-sigma device
important points are highlighted below. mismatch models, an improvement of better than 12 dB in
• The technique can be easily applied to two to stages. HD3 can be achieved as compared with the nonlinearized
In this particular example, a five-stage design has been case.
shown. Tradeoffs can be made between maximum The performance of the receiver in the presence of frequency
peak-to-valley deviation of the transconductance, the offsets and multipath distortion is examined in Fig. 18. Due to
in-band ripple of the transconductance curve, and the the effect of a severe multipath channel of 200-ns rms delay,
BEHZAD et al.: 5-GHz DIRECT-CONVERSION CMOS TRANSCEIVER UTILIZING AFC FOR THE IEEE 802.11a WLAN STANDARD 2217

Fig. 18. AFC performance with (a) AFC disabled and (b) AFC enabled.

2-dBc multipath signal strength, and 180 of relative phase,

the received spectrum displays deep nulls. Also, the multipath
channel results in an increase in the EVM of the OFDM subcar-
riers that fall at the frequency of the nulls. However, the more
severe effect on the error vector spectrum is due to the large
200-kHz frequency offset that is present on the received base-
band signal (relative to the location of the receive HPF poles)
which causes severe attenuation of the lowest frequency sub-
carriers. This results in a very large increase in the EVM of the
lowest frequency subcarrier. On average, the EVM has increased
from less than 5% to over 24% for this subcarrier, and the peak
EVM has increased to over 60% for this subcarrier. This results
in the outlier points in the constellation diagram of Fig. 18(a).
The average EVM in this case is 24 dB, which is not sufficient Fig. 19. Die microphotograph of RF transceiver.
for good PER performance.
Now with the AFC enabled, as shown in Fig. 18(b), the im-
tipath channel (such as the example described here). The AFC
pairments due to the multipath channel are still present, but the
system preserves high-data-rate operation that would otherwise
effects of the frequency offset have been significantly reduced,
be unattainable at any receive power level.
as apparent in the error vector spectrum plot of Fig. 18(a). In
this case, most of the constellation diagram outlier points have
IV. MEASUREMENT RESULTS
been eliminated, and a receive EVM of 28 dB is achieved
(even in the presence of a very severe multipath channel). This The RF transceiver has been integrated in a 0.18- m digital
EVM is more than sufficient for reliable 54-Mb/s performance. CMOS process, with a single poly and five metal layers. It oc-
It is also important to note that while in the presence of rel- cupies a total area of 11.7 mm including the pad ring. The chip
atively mild multipath channels, the AFC would improve the is housed in a LPCC-48 pin package with an exposed paddle
high-data-rate sensitivity level, but in the case of a severe mul- to provide good grounding. The die photo of the transceiver is
2218 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

TABLE I [2] M. Zargari et al., “A 5 GHz CMOS transceiver for IEEE 802.11a wire-
SUMMARY OF TRANSCEIVER PERFORMANCE less LAN system,” IEEE J. Solid-State Circuits, vol. 37, pp. 1688–1694,
Dec. 2002.
[3] D. Su et al., “A 5 GHz CMOS transceiver for IEEE 802.11a wireless
LAN,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002,
pp. 92–93.
[4] T. P. Liu et al., “5-GHz CMOS radio transceiver front-end chipset,”
IEEE J. Solid-State Circuits, vol. 35, pp. 1927–1933, Dec. 2000.
[5] H. Samavati et al., “A 5-GHz CMOS wireless LAN receiver front end,”
IEEE J. Solid-State Circuits, vol. 35, pp. 765–772, May 2000.
[6] I. Bouras et al., “A digitally calibrated 5.15–5.825 GHz transceiver for
802.11a wireless LANs in 0.18 m CMOS,” in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, 2003, pp. 352–353.
[7] P. Zhang et al., “A direct conversion CMOS transceiver for IEEE
802.11a WLANs,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Papers, 2003, pp. 354–355.
[8] H. R. Rategh et al., “A CMOS frequency synthesizer with an injection-
locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J.
Solid-State Circuits, vol. 35, pp. 780–787, May 2000.
[9] C. Lam et al., “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-m
CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788–794,
May 2000.
[10] A. Behzad et al., “A direct-conversion CMOS transceiver with automatic
frequency control for IEEE 802.11a wireless LAN,” in IEEE Int. Solid-
State Circuits Conf. Dig. Tech. Papers, 2003, pp. 356–357.
[11] H. Darabi et al., “A 2.4 GHz CMOS transceiver for Bluetooth,” in IEEE
Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 200–201.

shown in Fig. 19. The chip consumes 150 mW of power in re-

ceive mode and 380 mW of power in transmit mode while trans- Arya R. Behzad (S’90–M’95–SM’03) was born
mitting a 15-dBm OFDM signal. The entire chip operates with a in Michigan in 1969. He transferred from Sharif
University of Technology, Tehran, Iran, to Arizona
1.8-V supply except for the power amplifier which operates with State University (ASU), Tempe, in 1988. He
a 3.3-V supply. The chip passes 2.5-kV electrostatic discharge received the B.S.E.E. degree from ASU (summa cum
(ESD) testing using the human-body model. The performance of laude) as the Outstanding Graduate of the College
of Engineering in 1991. He received the M.S.E.E.
the transceiver is summarized in Table I. All system-level mea- degree from the University of California at Berkeley
surements are referred to the chip inputs and outputs. in 1994 after completing his thesis on the Infopad
project.
He was a Special Project Engineer with United
V. CONCLUSION Technology Corporation from 1991 to 1992. He worked at MicroUnity Systems
Engineering from 1994 to 1996 as a Senior Analog and System Engineer
The highest performance, highest integration, smallest size, implementing RF and analog front-ends for set-top boxes and cable modems.
From 1996 to 1998, he was with Maxim Integrated Products implementing
and lowest power consumption 802.11a transceiver reported to high-precision analog components, infrared receivers, and cellular phone ICs.
date has been presented. This chip along with the companion Since 1998, he has been with Broadcom Corporation, San Diego, CA, working
single-chip PHY/MAC constitutes a full 802.11a system. The on integrated tuners, gigabit Ethernet, and wireless LAN systems and ICs. He
is currently a Senior Manager of Engineering working on radios for current and
transceiver achieves a 4-dB receive NF and 23-dBm trans- future generation wireless products. He has over 20 patents issued and pending,
mitter saturated output power. It achieves low cost through the as well as several publications, in the areas of precision analog circuits, cellular
use of a direct conversion architecture in digital CMOS. Various transceivers, integrated tuners, gigabit ethernet, and wireless LANs.
Mr. Behzad is a member of the IEEE International Solid-State Circuits Con-
integrated self-contained or system-level calibration capabilities ference Wireless Technical Committee. He is a past president of Eta Kappa Nu,
allow for high performance and high yield. AZ B chapter.

ACKNOWLEDGMENT
The authors acknowledge the contribution of the following Zhong Ming Shi (M’91–SM’03) received the B.S.
degree from Fudan University, Shanghai, China, in
Broadcom Divisions: System Engineering (Sunnyvale, CA), 1982, the M.S. degree from East China Normal Uni-
CAD Support (Irvine, CA), RF Engineering (El Segundo, versity, Shanghai, in 1985, and the Ph.D. degree from
CA), and Operations and Test Engineering (Irvine, CA). In the Swiss Federal Institute of Technology, Lausanne,
Switzerland, in 1992.
particular, the contributions of the following individuals are He was a Postdoctoral Fellow at the Swiss Federal
greatly appreciated: B. Yeung, S. Tian, T. Gloerstad, D. Yang, Institute of Technology in 1993 and the University of
J. Castaneda, J. Trachewsky, C. Hansen, T. Moorti, R. Gaikwad, Waterloo, ON, Canada, in 1994. From 1995 to 2000,
he was with Nokia, Prominent Communication, and
T. Kwan, A. Woo, L. Burns, T. V. Nguyen, M. Chok, P. Wong, LSI Logic as a Team Leader, Director, and Principal
A. Ito, B. Bacher, J. To, and A. Niknejad (U.C. Berkeley). Manager to develop RF/mixed-signal ICs for cellular and Bluetooth applica-
tions. From 2000 to 2003, he was with Broadcom Corporation, San Diego, CA,
as a Principal Scientist engaged in RF architecture and system and IC design for
REFERENCES IEEE 802.11 wireless LAN applications. He holds several U.S. and European
patents in the area of RF architecture and system and IC designs. He is currently
[1] IEEE Standard 802.11a-1999: Wireless LAN MAC and PHY Specifica- an independent consultant.
tion—High Speed Physical Layer in the 5 GHz Band, 2000. Dr. Shi received the Nokia Hall of Fame Award in 1997.
BEHZAD et al.: 5-GHz DIRECT-CONVERSION CMOS TRANSCEIVER UTILIZING AFC FOR THE IEEE 802.11a WLAN STANDARD 2219

Seema Butala Anand was born in Modasa, India, in Tsung-Hsien (Eric) Lin (M’95) received the B.S.
1970. She received the B.S. degree in electrical engi- degree in electronics engineering from National
neering from the University of California at Los An- Chiao-Tung University, Hsinchu, Taiwan, R.O.C.,
geles (UCLA) in 1992, the M.S. degree in electrical in 1991, and the M.S. and Ph.D. degrees from the
engineering and computer science from the Univer- University of California at Los Angeles in 1997 and
sity of California at Berkeley in 1994, and the Ph.D. 2001, respectively.
degree in electrical engineering from UCLA in 2001. He has been with Broadcom Corporation, Irvine,
From 1994 to 1997, she was a Member of Tech- CA, since March 2000, where he is currently a
nical Staff with the High Speed Electronic Depart- Senior Staff Scientist. His research interests include
ment, Hewlett Packard Laboratories, Palo Alto, CA, analog and RF IC design for wireless applications
where she designed CMOS ananlog, RF, and mixed- and CMOS mixed-signal circuits.
signal ICs for wireless communications. From 1997 to 2000, she was a Research
Assistant for the Integrated Circuits and Systems Laboratories, UCLA. Since
July 2000, she has been with Broadcom Corporation, Irvine, CA, where she is a
Senior Staff Scientist engaged in the design and development of CMOS trans- Thinh Nguyen (M’99) was born in Manila, Philippines. He received the
ceivers for wireless LAN applications. Her research interests include trhe design B.S.E.E. degree from San Jose State University, San Jose, CA, in 1984, and the
of RF, analog, mixed-signal, and broad-band data communications ciruits. M.S.E.E. degree from Santa Clara University, Santa Clara, CA, in 1998.
He has worked for Raytheon Company, Micro Linear Inc., Sierra Research
Inc., Plato Labs Inc., and Broadcom Inc., and has designed many analog blocks
supporting networking, and WLAN communication chips such as low-noise
opamps, VGAs, 100 Base-T analog adaptive equalizer, and G -C filters. He is
currently with Texas Instruments Incorporated, Sunnyvale, CA.

Li Lin received the B.S. degree in electrical engi-

neering from Portland State University, Portland, Dan Yuan received the B.S. degree in electrical en-
OR, in 1994 and the M.S. and Ph.D. degrees in elec- gineering from Beijing Polytechnic University, Bei-
trical engineering from the University of California jing, China, in 1989 and the M.S. degree in electrical
at Berkeley in 1996 and 2000, respectively. and computer engineering from the University of Ari-
In 2000, she joined Broadcom Corporation, San zona, Tucson, in 1994.
Jose, CA, where she was involved in the develop- She joined Broadcom Corporation in 2000,
ment of wireless LAN applications. Since 2003, she working on Bluetooth and 802.11a products. She is
has been with Berkana Wireless Inc., Campbell, CA, now with Qualcomm Incorporated, San Diego, CA.
where she is working on RF integrated circuit design
for wireless communication.
Dr. Lin is a member of Etu Kappa Nu and Tau Beta Pi. She was a corecipient
of the 2001 IEEE International Solid-State Circuits Conference Lewis Winner
Outstanding Paper Award.
Stephen Wu was born in 1973. He received the B.S.
and M.S. degrees in electrical engineering from the
University of California at Los Angeles in 1997.
He was a Master’s Fellow with Hughes Aircraft,
Torrance, CA, from 1995 to 1997. Since 1999, he
has been with Innovent Systems, now Broadcom Cor-
Keith A. Carter (M’87) received the M.S. degree in poration, Irvine, CA. His interests include RF and
electrical engineering from Santa Clara University, analog integrated circuit design for wireless commu-
Santa Clara, CA, in 1996. nications.
From 1991 to 2000, he developed wireless
integrated circuits primarily for Hewlett-Packard
emphasizing CDMA applications. Currently, he is
with Broadcom Corporation, Irvine, CA, developing
next-generation wireless LAN and Bluetooth Y. C. Wong received the B.S. degree from Shanghai
products. Univeristy, Shanghai, China, in 1984 and the M.S. de-
gree from the California Institute of Technology (Cal-
tech), Pasadena, in 1988.
From 1989 to 1995, he was a Principal Engineer
with Siemens Medical System, Inc. From 1995 to
1998, he was a Lead Engineer with the Advance
Product Division, Cellular Infrastructure Group,
Motorola, Inc., where he designed SoC chip sets for
Michael S. Kappes (M’93) received the B.S.E.E. and cellular infrastructure. From 1998 to 1999, he was
M.S.E.E. degrees from the University of California at a Senior Staff Engineer with the Network Access
San Diego, La Jolla, in 1990 and 1992, respectively. Division, Conexant Systems, Inc. In 1999, he joined Broadcom Corporation,
From 1993 to 1997, he was with Brooktree San Diego, CA, where he is leading Bluetooth SoC single-chip development.
Corporation, San Diego, CA, in the communications
business unit, working on analog circuits for
telecommunications. In 1997, Brooktree was ac-
quired by Rockwell Semiconductor Systems, where Victor Fong received the B.E.Sc. degree in electrical
he continued working as an Analog IC Designer until engineering from the University of Western Ontario,
1998, when the semiconductor division was spun London, ON, Canada, in 1991.
off as Conexant Systems. He was with Conexant He started his career in integrated circuits with
Systems as a Group Leader developing analog interface technology for xDSL. Sintek Semiconductors, Hong Kong. In 1996, he
In 2000, he joined Microlink Corporation, focusing on Bluetooth transceiver joined Maxim Integrated Products, Sunnyvale, CA.
development. Microlink was later acquired by Broadcom Corporation. Since He is currently with Broadcom Corporation, San
June 2000, he has been with Broadcom, San Diego, CA, working on the Jose, CA, as a Senior Staff VLSI Layout Engineer
development of wireless LAN transceivers. engaged in physical design of analog/RF circuits
Mr. Kappes was named Engineer of the Year at Conexant Systems in 1999. and CAD development.
2220 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

Ahmadreza Rofougaran (M’97) was born in

February 1964 in Iran. He received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from the
University of California at Los Angeles (UCLA)
in 1986, 1988, and 1998, respectively. His Ph.D.
research was on the integration of a full CMOS RF
frequency-hopped spread-spectrum transceiver.
He was with Gigabit Logic, Inc., Newbury Park,
CA, from 1988 to 1992. He has been a Consultant
with various companies for the last few years in
the area of wireless communications. In 1998, he
cofounded Innovent System Corporations, and is currently a Senior Director of
Engineering with Broadcom Corporation, Irvine, CA, working on RF CMOS
and wireless products. He has more than 20 publications in journals and
conferences.
Dr. Rofougaran was a corecipient of the 1995 ESSCIRC Best Paper
Award, the 1996 IEEE International Solid-State Circuits Conference (ISSCC)
Outstanding Student Paper Award, the 1997 ISSCC Outstanding Technology
Directions Paper Award, and the 1998 DAC Best Paper Award.