INSTRUCTION SET OF 8051 (A SUMMARY)

8051 instructions are classified based on:

1. Instruction types (functions)

2. Machine cycles required for execution
3. Size of instructions
4. Addressing Mode

ADDRESSING MODES:
1) Immediate addressing mode (IAM)
2) Register direct addressing mode (RDAM)
3) Direct addressing mode (DAM)
4) Indirect addressing mode (InDAM)

Eg. IAM: MOV R0, #data8

MOV DPTR, #data16

RDAM: MOV A, R2
ADDC A, R3

DAM: MOV R0, addr8 (eg. MOV R0, 3FH)

MOV addr8, #05H
MOV P1, #0A5H
MOV add8_1, add8_2 (MOV 0A8H, 56H)
MOV 3AH, #3AH

Indirect AM: MOV @Rp, #n

Rp = pointer reg
@Rp, add
Memory pointer registers
@Rp, A
i) R0/R1: R0 & R1 are also called
MOV add, @Rp
MOV A, @Rp data pointer to hold the address
of one of the data locations in
INSTRUCTIONS TYPES: internal RAM from address 00H
to 07FH
ii) DPTR: Data pointer
1) Data transfer instructions
2) Logical instruction
3) Arithmetic instruction
4) Branching Instruction
5) Boolean Instruction

DATA TRANSFER INSTRUCTIONS:

MOV →Data movement from/to internal RAM/SFR

MOVX → Data movement from/to external RAM
MOVC →Data movement from external/internal ROM
PUSH & POP
XCH
MOVX → Copy Data from/to external memory

This instruction Always Uses Indirect Addressing mode

➔ R0 & R1 will hold the external RAM addresses from 00H-FFH
➔ DPTR can address maximum external RAM space of 0000H to FFFFH
Valid instruction formats
MOVX A, @Rp
MOVX A, @DPTR Rp→R0/R1
MOVX @ Rp, A
MOVX @DPTR, A
LUT in
ROM
MOVC: Code memory read only data moves (eg. LUT) [DPTR]
Valid instruction formats A=2
MOVC A, @A+DPTR [ A+DPTR] →A
A @(A+DPTR)
MOVC A, @A+PC
(i) PC  PC+1 MOVC A, @A+DPTR
(ii) A  @(A+PC) To read the elements of LUT in
external ROM

PUSH and POP:

➔ Stores or retrieves data from stack memory implemented in Internal RAM
➔ PUSH Operation: (i) SP = SP+1, (ii) Then Push (Write) data in Top of stack location
➔ POP Operation: (i) Read Data from Top of stack location (ii) then SP=SP-1
➔ Valid instruction formats
Push add8 ((i) SP=SP+1 (ii) [SP] [add8])
Pop add8 ((i) [SP]→ [add8] (ii) SP=SP-1)

Data Exchanges:
➔ All addressing modes except immediate addressing mode can be used
➔ Valid instruction formats
➔ XCH A, Rr
A, address8
A, @Rp Where, RpR0/R1
➔ XCHD A, @Rp (Exchange lower nibbles of A & M.L. data with addr pointed by Rp)
(Upper nibbles are not affected)

LOGICAL INSTRUCTIONS:

Boolean operator 8051 Mnemonic

AND ANL (And logical)
OR ORL
XOR XRL
NOT CPL (complement)

These instructions do not affect flags

Valid instruction formats
ANL A, #n
, add
, Rr
, @Rp
ANL add, A (ANL 02H, A)
ANL add, #n (ANL 07H, #12H)

ORL: Similar formats for this instruction as in ANL

XRL: Similar formats for this instruction as in ANL

CLR A (Only works on Reg. A)

CPL A (Only works on Reg. A)

Note:
The normal source of data from a port is the port pins. The destination for Port writing is port latch.
But Read Modify Write instructions will always read from port latch and will write to port latch.

Eg. ANL P0, #0FH ANL A, P0

Read port latch Reads port Pins
Modify
Update port latches

Rotate instructions:
RL A, RLC A
RR A, RRC A
SWAP A  exchange low & high nibbles in the byte present in accumulator

Bit level logical operations:

➔ Internal RAM bit address
→Byte address → 20-2FH
→Bit address → 00H-7FH
➔ SFR Bit addresses
➔ A, B, IE, IP, P0, P1, P2, P3, PSW, TCON, SCON (Bit addressable SFRs)
Eg. CLR b b= Address of bit
CLR ACC.5
SETB ACC.5
CPL b

Bit level Boolean operations:

ANL c, b c = carry flag
ANL c, /b b= Address of bit
ORL c, b
ORL c, /b Note: Only the bit addressable
CPL c, CPL b RAM/SFRs must be used in Bit
MOV c, b operations
MOV b, c
SETB c, SETB b
CLR b

Eg:
SETB 00h
CLR 05h
MOV c, 00h or MOV 7Fh, c
ANL c, /00h
ORL c, 00h
CPL 7Fh, CLR c
ORL c, /7Fh

Rotate and SWAP instruction:

Rotate
RL A left Accumulator one place without & with
carryArespectively: RL A, RLC A
RLC

RR A, RRC A

SWAP A (interchanges lower & higher nibbles of A)

High Low SWAP A

nibble nibble

ARITHMATIC INSTRUCTIONS:
Operations supported:
➔ Addition with/without carry
➔ Increment
➔ Subtraction with borrow
➔ Decrement
➔ Decimal adjust
➔ Multiplication
➔ Division (8 bit)
Affects C, OV, AC and P flags only
ADD / ADDC A, source
INC Source (No flags are changed)
SUBB A, source
DEC source
DA A (decimal adjust of Acc.)→ Defined only for ADD/ADDC
MUL AB (A×B= Bhigh Byte Alower Byte) [Affects only C(=0) and OV flag when prod>FFH]
DIV AB (A ÷ B => A (integer Quotient), B (integer remainder)) [Affects only C(=0) and OV flag
when B=0 before division operation]

Increment/decrement (No flags are changed):

INC A, INC Rr, INC addr, INC @Rp, INC DPTR
DEC A, DEC Rr, DEC addr, DEC @Rp, DEC DPTR
➔ INC P0: This is a Read Modify Write type instruction hence Affects only port latches

Addition / Subtraction:
ADD/ADDC A, #n SUBB A, #n
A, Rr , Rr
A, add , add
A, @Rp ,@Rp

Unsigned / Signed add

CF Affects: CF & OF (OV=1 for overflow)
Otherwise for
-ve result => CF=1
Res. In 2’s comp.

BRANCHING INSTRUCTIONS:

Branching: Altering the program execution flow from the sequential pattern of execution. Here, PC is
altered with new address of the program codes from where the program needs to be executed after
branch instructions are encountered.
There are two types of branch instruction:-
(i) A Jump (Branch without return): That permanent changes the contents of PC.
(ii) A Call (Branch with return): That temporarily changes the PC to execute a different part of the
program.

These codes are also called decision codes that alter the flow of programs depending on the results of
the action codes and affect the contents of PC.

Types of decision instruction:

➔ Jump on bit conditions
➔ Compare bytes & Jump if not equal
➔ Decrement byte & Jump if not zero
➔ Jump Unconditionally
➔ Call a subroutine
➔ Return from a subroutine

Range of branching for Jump & Call:

Range of branching = (New value of PC – Initial value of PC)

Classifications based on range of branch instructions:

➔ Relative Range:
• Branching address format specified with instruction: 8 bit signed offset
format (PC=PC+signed offset)
 • Branching range: +127d to -128d locations from the instruction after
the Jump Instruction
• Memory efficient and relocatable but lower/limited branching range
(only 256 memory locations)
➔ Absolute Range: (Short Absolute Range)
• Branching address format specified with instruction: 11 bit absolute
range. The Upper 5 bits of branching destinations are taken from the
current value of PC. i.e the programmer only specifies lower 11 bits of
branching address. The Upper 5 bits (Page address) of branching
destinations are taken from the current value of PC. The bits are
concatenated to form a 16 bit physical branching address
• Branching range: Within the same 2KB page where the instruction
following the branching instruction is present.
• Relocatable branching address and higher branching range (2KB range)
➔ A long range (Long absolute range): Any address from 0000H to FFFFH anywhere in
program mem.
• Branching address format specified with instruction: 16 bits absolute
address
• Branching address format is Not relocatable and not a memory efficient
way to specify branching address. Instruction size increases but highest
branching range (64 KB locations)
• Accordingly following types of unconditional branching instructions are specified:
o SJMP sadd: The instruction is of 2 bytes. Range of branch is 128 locations backward and
127 locations forward (Total 256 bytes)
o AJMP abs_addr: The instruction is of two bytes. The lower 11 bits contains the absolute
address within the current page. Range of branching is restricted within the 2KB page.
o LJMP ladd: This instruction is three bytes long. Range of branch is 64KB

Unconditional Branching instructions without return

o JMP @ A+DPTR
o AJMP aadr → Jump to absolute range address (absolute aad)
o LJMP laddr → Jump to absolute address range (long)
o SJMP raddr → Jump to relative address range (Short)

Conditional branching Instructions without return:

1. Bit Jump types: Branching instructions those test a bit for carrying out branching operation

JC radd (Jump if CF=1), radd means relative address of 8 bits

JNC radd (Jump if CF=0)
JB b, radd (Jump if the addressed bit is 1), b is the bit address
JNB b, radd (Jump if the addressed bit is 0)
JBC b, radd (Jump if the addressed bit is 1 and Clear the bit)
JBC P1.0, radd (This is a read modify write type operation)

Steps of execution for instruction JNB PX.X, radd

Read PX.X latch
Test if the bit is non - zero
If the bit is non-zero Then Branch according to specified relative address

2. Byte Jumps types: branching instructions those test a byte for carrying out branching
operation

CJNE → Compare & Jump if not equal (Used for branching based on comparison result)
CJNE A, add8, radd
A, #n, radd
Rn, #n, radd
@Rp, #n, radd
Sequence of operation:
1. Compare operand 1 and operand 2 and update the required flags
2. If the result of comparison is non-zero then branch to new ROM address given by
PC=PC+radd else don’t branch

DJNZ → Decrement & Jump if not zero (used for implementing loops)
DJNZ Rn, radd
RnRn-1
Jump to relative address; radd, if after decrementing Rn, result ≠ 0 (NFAC except if
the destination is PSW)
Sequence of operation:
1. Decrement the register specified
2. Check the register value after decrement operation
3. If the new value of the register is non-zero then branch to new ROM address given
by PC=PC+radd else don’t branch

DJNZ PX, radd; then PX PX-1, branch if PX ≠ 0 (read latch, decrement and update port latch)

JZ → Jump if Acc. Is zero (Note: There is no zero flag in 8051: Byte testing type instruction)
JZ radd → Jump to relative addr if A=0
JNZ radd → jump if A ≠0 (A is not after & NFAC)

Branching Instructions with return

CALLS & SUBROUTINES

Call is used to execute a smaller stand-alone program, which is termed as a “subroutine”.
The call instruction can be invoked by specifying CALL instruction in the program OR by generating
the interrupts.

Types of CALL Instructions:

ACALL abs_addr:
Function: Calls/Executes the subroutine located on the same page as the address of the
opcode immediately following the ACALL instruction.
Working:
▪ Push the two bytes of physical address of the instruction (in program memory)
immediately after the ACALL instruction on the stack.
 ▪ Then branch to the location of subroutine given by new branching address to
be copied to PC calculated as below:
PCnew = (upper 5 bits of PCold) concatenated with (lower 11 bits of the
absolute address specified with instruction).

LCALL ladd:
Function: Calls/Executes the subroutine located anywhere in program memory space.
Working:
• Push the two bytes of physical address of the instruction (in program memory)
immediately after the LCALL instruction on the stack Branch to the location
of subroutine.
• The new branching address to be copied into PC is calculated as below:
PCnew = 16 bits of the long address specified with instruction.

Types of Return Instructions:

RET: Pop two bytes from top of stack into program counter. Internally POP PC operation is
executed.
RETI → Pops 2 byte from the stack into the program counters & restores the IE bits.
-RETI restores the interrupt logic
- RETI is called by ISSR

Steps of Execution of CALL & RET Instruction:

(i) CALL may be specified in the program software or may be invoked by interrupts
generated by the hardware circuitry.
(ii) The Return address of the next instruction after CALL instruction or interrupt is found in
PC.
(iii) The 16-bit Return address is pushed in stack twice for each of the 8-bits, with lower byte
pushed first.
(iv) The SP is incremented for each push on the stack. So SP  SP+2
(v) The Sub-program address is placed in PC
(vi) The Sub-program is executed
(vii) The RET opcode is encountered at the end of the SP
(viii) Two POP operations restore the return address to the PC from the stack area in internal
RAM
(ix) The SP is decremented for each address byte POP.
SP  SP -2
RET → pop 2 byte of return address from stack into PC

Interrupts & Return:

i. The interrupt is a hardware generated CALL.
ii. Invoked when signal status at the interrupt pin changes.
iii. Internal or external hardware events initiates the interrupts (like serial data
reception/transmission complete, timer overflow)
iv. When an interrupt call takes place, the hardware of interrupt circuit disables the flags
controlling the interrupt behaviour till the ISSR (Interrupt service subroutine) is executed &
RETI is encountered.

RETI → Pops 2 byte from the stack into the program counters & resets the IE bits.
 -Always used at the end of an ISR (Interrupt Service Routine) for returning the program
control to the code before which the branching took place
- Pops two bytes of return address from the stack into program counter
-Resets the interrupt enable flipflops, thus RETI restores the interrupt logic in this manner

Interrupt generated hardware ISR call

Certain pins on 8051 can cause a hardware call by the system when the electrical signals on them
goto low state (active low signal) or when the signals on them changes from high to low state
(Negative edge signal)
Internal operations of the timers and serial port can also cause an interrupt call to take place
The subroutines called by an interrupt are specified at fixed hardware address as given below:

Interrupt Name Type Interrupt Flag Interrupt Vector

enable address
flag bit
External interrupt 0 External, IE0 EX0 0003H
Hardware
(Pin ̅̅̅̅̅̅̅
𝐼𝑁𝑇0)
External Interrupt 1 External, IE1 EX1 0013H
Hardware
(Pin ̅̅̅̅̅̅̅
𝐼𝑁𝑇1)
Timer 0 Over flow Internal, TF0 ET0 000BH
Hardware
Timer 1 Over flow Internal, TF1 ET1 001BH
Hardware
Serial Interrupt Internal, TI and RI ES 0023H
Hardware

A Table indicating different instructions of 8051, their sizes and machine cycles required for
Fetch and execution of those instructions

Mneumonic Description Size (Byte) Machine

Cycles
required
MOV A, Rr Rr → A 1 1
MOV A, add (add) → A 2 1
MOV A, @Rp (Rp) → A 1 1
MOV A, #n n→A 2 1
MOV Rr, add (add) → Rr 2 2 (F+E)
MOV add1, add2 (add2) → (aad1) 3 2
MOV add, #n n → (add) 3 2
MOV @Rp, add (add) → (Rp) 2 2
MOV DPTR, #nn nn → DPTR 3 2
MOVC A, @A+DPTR (A+DPTR) → A 1 2
MOVC A, @A+PC (A+DPTR) → A 1 2
MOVX A, @ DPTR (DPTR)^ → A 1 2
MOVX A, @ Rp (Rp)^ → A 1 2
POP add (SP) → (add) 2 2
PUSH add (add) → (SP) 2 2
XCH A, @Rp A → (Rp) 1 1
XCH A, add A → (add) 2 1
XCHD A, @Rp ALSN → (Rp)LSN 1 1
MUL AB A x B → B, A 1 4
DIV AB A/B → A, B 1 4

Some patterns:
1. In general, 1 byte instruction requires 1 machine cycle for Fetch and execution, 2 byte instruction
requires 1 machine cycle for Fetch and execution, and 3 byte instruction requires 2 machine cycle
for Fetch and execution
2. Using direct addresses in source or destination operation causes 2 machine cycles (But if one of
the operand is A, then only 1 machine cycle is required)
3. MOVC and MOVX instructions require 2 machine cycles to execute
4. MUL and DIV are 1-byte instructions but require 4 machine cycles to execute