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This document provides an overview of embedded systems concepts covered in a course on embedded system design. It discusses typical subsystems in embedded systems like processors, memory, sensors and actuators. It also covers embedded firmware design approaches and challenges in optimizing design metrics like performance, power, cost for the desired functionality.

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0% found this document useful (0 votes)
19 views

Mod1 1

This document provides an overview of embedded systems concepts covered in a course on embedded system design. It discusses typical subsystems in embedded systems like processors, memory, sensors and actuators. It also covers embedded firmware design approaches and challenges in optimizing design metrics like performance, power, cost for the desired functionality.

Uploaded by

Hitarth Parikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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K J SOMAIYA COLLEGE OF ENGINEERING, MUMBAI-77

(CONSTITUENT COLLEGE OF SOMAIYA VIDYAVIHAR UNIVERSITY)

Deepa Jain
Course: Embedded System Design

Department of Electronics Engineering

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Concept Covered

 Introduction to embedded systems

 Applications of embedded systems

 Typical subsystems in an embedded system

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Introduction
• We have been brought up in the age of computing.
• Computers are everywhere (some we see, some we do not see).

• Types of computers we are familiar with:


• Desktops and Laptops
• Servers
• Mobile phones

• But there’s another type of computing system that is often hidden.


• Far more common and pervasive...
• Hidden in the environment. Embedded Systems

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What are Embedded Systems?
• Computers are embedded within other systems:
• What is “other systems”? – Hard to define.
• Any computing system other than desktop / laptop server.
• Typical examples:
• Washing machine, refrigerator, camera, vehicles, airplane,
missile, printer.
• Processors are often very simple and inexpensive
(depending on application of course).
• Billions of embedded system units produced yearly,
versus millions of desktop units.

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Embedded System Vs General Computing System
Parameter General Purpose Embedded system

Application Variety of Applications Specific set of application

OS General Purpose OS May or May not

Application can change Alterable Preprogrammed and can not change


by user

Key Performance Performance Performance, Power requirement, memory usage

Response Not time critical For some system, Time Critical


Requirement

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Classification of Embedded System

• Based on Generation
• Complexity and Performance requirement
• Based on Deterministic behavior
• Based on Triggering

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Hard Real time system
• Flight Control Systems
• Missile Guidance Systems
• Weapons Defense System
• Medical System
• Inkjet printer system
• Railway signaling system
• Air traffic control systems
• Nuclear reactor control systems
• Anti-missile system
• Chemical plant control
• Autopilot System In Plane
• Pacemakers

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Soft Real time System
• Personal computer
• Audio and video systems
• Set top boxes
• DVD Players
• Weather Monitoring Systems
• Electronic games
• Multimedia system
• Web browsing
• Online transaction systems
• Telephone switches
• Virtual reality
• Mobile communication

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Common Features of Embedded Systems
• They are special-purpose or single-functioned.
• Executes a single program, possibly with inputs from the environment.
• Imagine a microwave oven, a washing machine, an AC machine, etc.
• Tight constraints on cost, energy, form factor, etc.
• Low cost, low power, small size, relatively fast.
• They must react to events in real-time.
• Responds to inputs from the system’s environment.
• Must compute certain results in real-time without delay.
• The delay that can be tolerated depends on the application.

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Core of the Embedded System

 GENERAL PURPOSE & DOMAIN SPECIFIC PROCESSORS


 Microprocessors
 Microcontrollers
 Digital Signal Processors

 2. APPLICATION SPECIFIC INTEGRATED CIRCUITS(ASIC)


 3. PROGRAMMABLE LOGIC DEVICES(PLD)
 4. COMMERCIAL-OFF-THE-SHELF COMPONENTS(COTS)

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MICROPROCESSORS and MICROCONTROLLERS :

Microprocessor
• Has CPU
• Capable of performing arithmetic & logical operations
• Dependent unit ie requires memory, timer unit ,interrupt controller etc.

Microcontroller
• Highly integrated chip Contains its own CPU,
• scratchpad RAM,
• on chip ROM/Flash memory
• Has dedicated ports
• Independent working
• Cheap
• cost effective and readily available.

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DIGITAL SIGNAL PROCESSING:

• Are powerful 8/16/32 bit microprocessors For audio, video and


communication applications
• 2 to 3 times faster from microprocessors
• It Consists of :
o Program memory (ROM),
o Data Memory (RAM),
o Computational Engine,
o I/O unit
• DSP employs large amount of real time calculations:

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CISC Vs RISC
CISC RISC

Complex Instruction Set Computing Reduced Instruction Set Computing

Large No of Instructions Small no. of Instruction

Variable length of Instruction set Fixed length of Instruction format

Large no of Addressing mode Few no of instruction set

Cost is high Low Cost

More Powerfull Less Powerfull

Several Cycle instruction Single Cycle Instruction

Manipulation directly in memory Only in Registers

Microprogrammed Control Unit Hardwired Control Unit

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Core of the Embedded System

 GENERAL PURPOSE & DOMAIN SPECIFIC PROCESSORS


 Microprocessors
 Microcontrollers
 Digital Signal Processors

 2. APPLICATION SPECIFIC INTEGRATED CIRCUITS(ASIC)


 3. PROGRAMMABLE LOGIC DEVICES(PLD)
 4. COMMERCIAL-OFF-THE-SHELF COMPONENTS(COTS)

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Memory

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Program Storage Memory

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RAM

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SRAM

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DRAM

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SRAM Vs DRAM

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Sensors and Actuators

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Sensors

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Actuators

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Silicon Technolab Digital Analog Arduino Starter

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I/O Subsystem

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LED

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7-Segment Display

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Optocoupler

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Stepper

• Rotating shaft in terms of steps.


• Pulses has to be apply to the motor.
• Application:
Dot Matrix printer: Having 2 stepper motor
 1st Motor used to moved the paper to nextline position
 2nd motor, move the print line to next char position.

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Stepper Motor

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Watch Dog Timers
• A watchdog timer is a piece of hardware that can be used to automatically detect software
anomalies and reset the processor if any occur.

• A watchdog timer is based on a counter that counts down from some initial value to zero.

• The embedded software selects the counter’s initial value and periodically restarts it.

• If the counter ever reaches zero before the software restarts it, the software is presumed to be
malfunctioning and the processor’s reset signal is asserted.

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Embedded Firmware

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Design and Implementation of Embedded Firmware

• 1.The SuperLoop based Approach


• 2. The Embedded operating System based Approach

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Assembly to Hex File Conversion

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High level language to Hex File

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Inline Assembly

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Concept Covered

 Design challenges for embedded systems

 Understanding design tradeoffs

 Non-recurring cost and unit cost metrics

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Design Challenges

• Primary design goal:


• An implementation that realizes the desired functionality.

• The main design challenge is …


• To simultaneously optimize several design metrics.
• Often mutually conflicting.

• What is a design metric?


• Some feature of an implementation that can be measured and evaluated.

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Common Design Metrics

• Non Recurring Engineering (NRE) Cost: One-time initial cost of designing a system.
• Unit Cost: The cost of manufacturing each copy of the system, without counting
the NRE cost.
• Size: The actual physical space occupied by the system.
• Performance: This is measured in terms of the time taken or throughput.
• Power: The amount of (battery) power consumed by the system.
• Flexibility: The ability to change the functionality of the system.

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• Maintainability: How easy or difficult it is to modify the design of the system?
• Time-to-prototype: How much time is required to build a working version of the
system (i.e. a prototype)?
• Time-to-market: How much time is required to develop a system such that it can
be released to the market commercially?
• Safety: Are there any adverse effects on the operating environment?
• Can be many more …

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Design Tradeoff

• Many of the design metrics can be mutually conflicting.


• Improving one may degrade the other (e.g. power, performance, size and NRE cost, etc.).
Power

Performance Size

NRE cost

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• Often requires expertise in both hardware and software to take a proper
decision.
• Expertise in hardware may indicate the types of co-processor or I/O interfaces to use for
specific applications (e.g. analog ports, digital ports, PWM ports, etc.).
• Expertise in software is required to identify parts of the implementation that need to be
implemented in software and run on the microcontroller.
• Hardware / Software Co-design becomes important.

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Time-to-market Design Metric
• This is a very crucial design metric.
• Must be strictly followed to make a
product commercially viable.
• Requires exhaustive market study and
analysis.
• Starting from the point a product
design starts, we can define a
Market Window within which it is
expected to have the highest sales.
• Any delay can result in drastic reductions in
sales.

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Loss due to Delayed Market Entry
Peak revenue

• Consider a simplified revenue model: Peak revenue from


delayed entry
• Product life is 2W On-time

Revenues ($)
Market rise
• Maximum sale occurs at time W Market fall

• Market rise and market fall defines a triangle in


Delayed
the revenue graph.
• Area of the triangle determines the total revenue.
• For delayed entry, can estimate the loss. D W 2W

• Difference in areas of the expected and actual On-time Delayed Time


entry entry
triangles.

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Peak revenue

• Area of a triangle = ½ * base * height


Peak revenue from
delayed entry • Area (on-time) = ½ * 2W * W
Revenues ($)

On-time
• Area (delayed) = ½ * (2W – D) * (W – D)
Market rise
Market fall
• Percentage revenue loss = D(3W –D)/2W2 * 100
Delayed
• Examples:
• 2W = 52 weeks, D = 4 weeks  LOSS = 22%
D W 2W
• 2W = 52 weeks, D = 10 weeks  LOSS = 50%
On-time Delayed Time
entry entry

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NRE and Unit Cost Metrics

• If CNRE denotes the NRE cost and Cunit the unit cost of a product, then the total
cost for manufacturing N units is given by:
Total Cost = CNRE + N * Cunit
• Therefore, per-unit cost is given by: CNRE / N + Cunit
• Example:
• CNRE= Rs. 5,00,000 and Cunit = Rs. 5,000
• Total cost for manufacturing 100 units = 5,00,000 + 5000 * 100 = 10,00,000
• Per unit cost = 5,00,000 / 100 + 5000 = 10,000

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1
Per-unit cost = (CNRE / N) + Cunit
• We can compare technologies by cost:
• Choice A: CNRE = Rs. 20,000, Cunit = Rs. 8,000
• Choice B: CNRE = Rs. 4,00,000, Cunit = Rs. 3,000
• Choice C: CNRE = Rs. 10,00,000, Cunit = Rs. 8,000
• Of course, time-to-market cost must also be considered.

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Performance Design Metric

• Most widely used, but can also be most misleading.


• Must be careful in the evaluation.
• Some of the measures:
• Clock frequency, MIPS --- not very good for comparison
• Latency (response time)
• Throughput
• Measure of speedup among design alternatives.

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3
Basic Operation of a Computing System
• The central processing unit (CPU) carries
out all computations.
• Fetches instructions from the program
memory and executes it; may require access
to data in data memory.
• The input/output block provides interface
with the outside world.
• Allows users to interact with the computing
system, and also observe the output results.

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• About the instruction set architecture (ISA) of the CPU.
a) Complex Instruction Set Computer (CISC)
• Typically used in desktops, laptops and servers (courtesy Intel).
b) Reduced Instruction Set Computer (RISC)
• Typically used in microcontrollers, that are used to build embedded systems.

• Two different types of memory:


a) Random Access Memory (RAM)
• Volatile; used for data memory in microcontrollers.
b) Read Only Memory (ROM)
• Non-volatile; used for program memory in microcontrollers.

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Classification of CPU
Architecture
• Broadly two types of architectures:
a) Von Neumann Architecture
• Both instructions and data are stored in the same memory.
• This model is followed in conventional computing systems.
b) Harvard Architecture
• Instructions and data are stored in separate memories.
• Typically followed in microcontrollers, used for building embedded systems.
• Instructions are stored in a ROM (permanent), while temporary data are stored
in RAM.

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Von Neumann Architecture Harvard Architecture

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What is a Microprocessor?

• It is basically the entire CPU fabricated on a single chip.


• Consists of a set of registers to store temporary data.
• Consists of an arithmetic logic unit (ALU), where all arithmetic and logical computations are
carried out.
• Consists of some mechanism to interface external devices (memory and I/O) through buses
(address, data and control).
• Consists of a control unit that synchronizes the operation.

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Schematic Diagram
of Microprocessor

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What is a Microcomputer?
• It is a computer system built using a microprocessor.
• Since a microprocessor does not contain memory and I/O, we have to interface these
to build a microcomputer.
• Too complex and expensive for very small and low-cost embedded systems.

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Microcontrollers: The Heart of Embedded Systems

• It is basically a computer on a single chip.


• Very inexpensive, small, low power.
• Convenient for use in embedded system design.
• It operates on data that are fed through its
serial or parallel input ports, controlled by
the software stored in on-chip memory.
• Often has analog input pins, timers and other
utility circuitry built-in.

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0
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1
Microcontroller Packaging and Appearance

From left to right:


PIC 12F508, PIC 16F84A, PIC 16C72, Motorola 68HC05B16, PIC 16F877, Motorola 68000

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How Microcontrollers are different from PCs?

• When a PC executes a program, the program is first loaded from disk/SSD into an
allocated section of memory.
• Usually the program is loaded part by part to conserve memory space.
• There is a complicated operating system that handles all low-level operations (includes low-
level driver codes for interfacing with various devices).
• In a microcontroller there is no disk to read from.
• On-chip ROM stores the program that is to be executed.
• Size of the ROM limits the maximum size of the application.
• There is no operating system, and the program is ROM is the only program that
is running (must include low-level routines).

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Where are Microcontrollers Used?

• Typically in applications where processing power is not critical.


• Modern-day household can have 10 to 50 such devices embedded in various devices and
equipments.
• One-third of the applications are in the office automation segment.
• Another one-third are in consumer electronics goods.
• Rest one-third are used in automotive and communication applications.

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Evolution of Microcontrollers
• Microcontroller evolved from a microprocessor-based board-level design to a single
chip in the mid-1970's.
• As the process of miniaturization continued, all of the components needed for a controller were
built into a single chip.
• In the mid-1980’s, microcontrollers got embedded into a larger ASIC (Application
Specific Integrated Circuit).
• Microcontrollers are fabricated as a module inside a larger chip.

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Advantages of using microcontrollers
• Fast and effective
• The architecture correlates closely with the problem being solved (control systems).
• Low cost / Low power
• High level of system integration within one component.
• Only a handful of components needed to create a working system.
• Compatibility
• Opcodes and binaries are the SAME for all 80x51 / ARM / PIC variants.

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History of ARM Series of Microcontrollers

• Architectural ideas developed in 1983 by Acorn Computers.


• To replace the 8-bit 6502 microprocessor in BBC computers.
• The first commercial RISC implementation.

• The company founded in 1990.


• Advanced RISC Machine (ARM).
• Initially owned by Acorn, Apple and VLSI.

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Why do we talk about ARM?
• One of the most widely used processor cores.
• Some application examples:
• ARM7: iPod
• ARM9: BenQ, Sony Ericsson
• ARM11: Apple iPhone, Nokia N93, N100
• 90% of 32-bit embedded RISC processors till 2010.
• Mainly used in battery-operated devices:
• Due to low power consumption and reasonably good
performance.

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About ARM Processors

• A simple RISC-based architecture with powerful design.


• A whole family of ARM processors exist.
• Share similar design principles and a common instruction set.
• Design philosophy:
• Small processor for lower power consumption (for embedded system applications).
• High code density for limited memory and physical size restrictions.
• Can interface with slow and low-cost memory systems.
• Reduced die size for processor to accommodate more peripherals.

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Popular ARM Architectures
• ARM7
• 3 pipeline stages (fetch/decode/execute)
• High code density / low power consumption
• Most widely used for low-end systems
• ARM9
• Compatible with ARM7
• 5 stages (fetch/decode/execute/memory/write)
• Separate instruction and data cache
• ARM10
• 6-stages (fetch/issue/decode/execute/memory/write)

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ARM Family
Comparison
ARM 7 (1995) ARM9 (1997) ARM10 (1999) ARM11 (2003)
Pipeline depth 3-stage 5-stage 6-stage 8-stage
Typical clock frequency (MHz) 80 150 260 335
Power (mW/MHz) 0.06 0.19 0.50 0.40
Throughput (MIPS/MHz) 0.97 1.1 1.3 1.2
Architecture Non Neumann Harvard Harvard Harvard
Multiplier 8 x 32 8 x 32 16 x 32 16 x 32

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ARM is based on RISC
Architecture
• RISC supports simple but powerful instructions that execute in a single cycle at
high clock frequency.
• Major design features:
• Instructions: reduced set / single cycle / fixed length
• Pipeline: decode in one stage / no need for microcode
• Registers: large number of general-purpose registers (GPRs)
• Load/Store Architecture: data processing instructions work on registers only;
load/store instructions to transfer data from/to memory.
• Now-a-days CISC machines also implement RISC concepts.

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ARM Features

• ARM architecture is different from pure RISC:


• Variable cycle execution for certain instructions (multiple-register load/store for higher code
density).
• In-line barrel shifter results in more complex instructions (improves performance and code
density).
• Thumb 16-bit instruction set (results in improvement in code density by about 30%).
• Conditional execution (reduces branch and improves performance).
• Enhanced instructions (some DSP instructions are present).

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VonNeumann
Von Neumann Harvard
ARM9s
ARM7s and newers
and olders Inst. Data

AHB
bus
Memory-mapped I/O: I D
• No specific instructions for I/O Cache Cache
MEMORY
• Use Load/Store instr. for I/O & I/O
• Peripheral’s registers at some
Bus Interface
memory addresses
AHB
bus

MEMORY
& I/O

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0
A[31:0]

ARM7 Address Register Address


Incrementer

bus
PC
Typical PC

Architecture REGISTER
BANK

ALU
INSTRUCCTION

bus

Control
DECODER

Lines
Multiplier

bus

bus
A

B
SHIFT

A.L.U.
Instruction Reg.

Thumb to
ARM
Write Data Reg. Read Data Reg.
translator

D[31:0]

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1
What is Pipelining?
• A mechanism for overlapped execution of several input sets by partitioning some
computation into a set of k sub-computations (or stages).
• Very nominal increase in the cost of implementation.
• Very significant speedup (ideally, k).

• Where are pipelining used in a computer system?


• Instruction execution: Several instructions executed in some sequence.
• Arithmetic computation: Same operation carried out on several data sets.
• Memory access: Several memory accesses to consecutive locations are made.

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A Real-life Example W+D+R

• Suppose you have built a machine M that can wash (W),T dry (D), and
iron (R) clothes, one cloth at a time.
For N clothes, time T1 = N.T
• Total time required is T.
• As an alternative, we split the machine into three smaller machines MW,
MD and MR, which can perform the specific task only.
W D R
• Time required by each of the smaller machines is T/3 (say).
T/3 T/3 T/3
For N clothes, time T3 = (2 + N).T/3

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How does the pipeline work?
Cloth-1 Cloth-2 Cloth-3 Cloth-4 Cloth-5 W Finishing times:
• Cloth-1 – 3.T/3
• Cloth-2 – 4.T/3
Cloth-1 Cloth-2 Cloth-3 Cloth-4 D • Cloth-3 – 5.T/3
• …
• Cloth-N – (2 + N).T/3
Cloth-1 Cloth-2 Cloth-3 R

T/3 T/3 T/3 T/3 T/3


Time

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Extending the Concept to Processor Pipeline
• The same concept can be extended to hardware pipelines.
• Suppose we want to attain k times speedup for some computation.
• Alternative 1: Replicate the hardware k times  cost also goes up k times.
• Alternative 2: Split the computation into k stages  very nominal cost increase.
• Need for buffering:
• In the washing example, we need a tray between machines (W & D, and D & R) to keep the cloth
temporarily before it is accepted by the next machine.
• Similarly in hardware pipeline, we need a latch between successive stages to hold the
intermediate results temporarily.

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Model of a Synchronous k-stage Pipeline
STAGE 1 STAGE 2 STAGE k

L S1 L S2 L … L Sk

Clock

• The latches are made with master-slave flip-flops, and serve the purpose of isolating
inputs from outputs.
• The pipeline stages are typically combinational circuits.
• When Clock is applied, all latches transfer data to the next stage simultaneously.

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Speedup and Efficiency
Some notations:
τ :: clock period of the pipeline
ti :: time delay of the circuitry in stage Si
dL :: delay of a latch
Maximum stage delay τm = max {ti}
Thus, τ = τm + dL
Pipeline frequency f = 1/τ
• If one result is expected to come out of the pipeline every clock cycle, f will represent
the maximum throughput of the pipeline.

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• The total time to process N data sets is given by
Tk = [(k – 1) + N].τ (k – 1) τ time required to fill the pipeline
1 result every τ time after that  total N.τ

• For an equivalent non-pipelined processor (i.e. one stage), the total time is
T1 = N.k.τ (ignoring the latch overheads)

• Speedup of the k-stage pipeline over equivalent non-pipelined processor:


T1 N.k.τ N.k
Sk = = =
Tk k.τ + (N – 1).τ k + (N – 1)

As N  ∞, Sk  k

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• Pipeline efficiency:
• How close is the performance to its ideal value?
Sk N
Ek = =
k k + (N – 1)

• Pipeline throughput:
• Number of operations completed per unit time.
N N
Hk = =
Tk [k + (N – 1)].τ

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0
14

12

10

8 k=4
Speedup

k=8
6
k = 12
4

0
1 2 4 8 16 32 64 128 256

Number of tasks N

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1
ARM Pipelining Examples
ARM7TDMI Pipeline

FETCH DECODE EXECUTE


Reg. Reg.
Read Shift ALU Write

1 Clock cycle

ARM9TDMI Pipeline

FETCH DECODE EXECUTE MEMORY WRITE


Reg. Reg.
Shift ALU access
Read Write

1 Clock cycle

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2
Pipelining in
Simple instructions (like ADD, SUB)
ARM7 can complete at a rate of one
1 FETCH DECODE EXECUTE instruction per cycle.

2 FETCH DECODE EXECUTE

3 FETCH DECODE EXECUTE

instruction
time

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3
With more complex instructions … stall cycles possible
1 ADD FETCH DECODE EXECUTE

2 STR FETCH DECODE Cal. ADDR Data Xfer.

3 ADD FETCH stall DECODE EXECUTE

4 ADD FETCH stall DECODE EXECUTE

5 ADD FETCH DECODE EXECUTE


instruction time
time

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4
ARM7 3-state Pipeline

ARM9 5-state Pipeline

ARM10 6-state Pipeline

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5
• In execution, the program counter (PC) is always 8 bytes ahead.

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6
THANK YOU

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