INTECO

Krakow, POLAND, [email protected]

www.inteco.com.pl

RT-DAC/USB2
I/O Board
Board version 1.03

User’s Manual

Kraków 2010
Revision History

Version Date Resp. Description

1.0 2010-09-30 KK First release
1.1 2010-10-25 KK Text improvements
 InTeCo

Table of contents

1. GENERAL INFORMATION................................................................................................................. 4
1.1 SPECIFICATION ................................................................................................................................... 4
1.2 BOARD ARCHITECTURE ...................................................................................................................... 6
2. BOARD INSTALLATION ..................................................................................................................... 7

3. DRIVER INSTALLATION.................................................................................................................... 8

4. CONNECTOR PIN ASSIGNMENT.................................................................................................... 10

5. USB ACCESS FUNCTIONS ................................................................................................................ 14

5.1 GENERAL DESCRIPTION OF SOFTWARE INTERFACES ......................................................................... 14
5.1.1 C interface ............................................................................................................................... 14
5.1.2 .NET interface.......................................................................................................................... 15
5.1.3 MATLAB/Simulink interface.................................................................................................... 16
5.2 USB FUNCTIONS .............................................................................................................................. 18
5.2.1 C interface ............................................................................................................................... 18
5.2.2 .NET interface.......................................................................................................................... 21
5.3 VERSION MANAGEMENT ................................................................................................................... 23
5.3.1 Logic version ........................................................................................................................... 23
5.3.2 Application name..................................................................................................................... 23
5.3.3 Synthesis date .......................................................................................................................... 23
5.3.4 Number of channels ................................................................................................................. 24
5.3.5 Example ................................................................................................................................... 24
5.4 OPERATING MODE OF THE SHARED OUTPUT SIGNALS ....................................................................... 26
5.5 DIGITAL I/O ..................................................................................................................................... 27
5.5.1 Direction.................................................................................................................................. 27
5.5.2 Input......................................................................................................................................... 28
5.5.3 Output...................................................................................................................................... 28
5.5.4 Example ................................................................................................................................... 29
5.6 COUNTER/TIMER .............................................................................................................................. 31
5.6.1 Mode........................................................................................................................................ 31
5.6.2 Reset ........................................................................................................................................ 32
5.6.3 Counter .................................................................................................................................... 32
5.6.4 Example ................................................................................................................................... 33
5.7 PWM ............................................................................................................................................... 35
5.7.1 Mode........................................................................................................................................ 36
5.7.2 Prescaler.................................................................................................................................. 36
5.7.3 Width ....................................................................................................................................... 36
5.7.4 Example ................................................................................................................................... 37
5.8 ENCODER ......................................................................................................................................... 39
5.8.1 Reset ........................................................................................................................................ 40
5.8.2 IdxActive .................................................................................................................................. 40
5.8.3 IdxInvert .................................................................................................................................. 41
5.8.4 Counter .................................................................................................................................... 41
5.8.5 Example ................................................................................................................................... 41
5.9 FREQUENCY METER .......................................................................................................................... 43
5.9.1 EnableBlock............................................................................................................................. 44
5.9.2 SwHwGateStartFlag ................................................................................................................ 44
5.9.3 SwStart..................................................................................................................................... 45
5.9.4 StartInv .................................................................................................................................... 45
5.9.5 SwGate..................................................................................................................................... 45
5.9.6 GateInv .................................................................................................................................... 45
5.9.7 InputInv.................................................................................................................................... 46

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5.9.8 GateMode ................................................................................................................................ 46

5.9.9 InfiniteFlag .............................................................................................................................. 46
5.9.10 Mode........................................................................................................................................ 47
5.9.11 Timer ....................................................................................................................................... 47
5.9.12 Ready ....................................................................................................................................... 47
5.9.13 Counter .................................................................................................................................... 48
5.9.14 Result ....................................................................................................................................... 48
5.9.15 Example ................................................................................................................................... 48
5.10 CHRONOMETER ................................................................................................................................ 51
5.10.1 EnableBlock............................................................................................................................. 52
5.10.2 TriggerMode............................................................................................................................ 53
5.10.3 EnableGate .............................................................................................................................. 53
5.10.4 InvertStartStop......................................................................................................................... 53
5.10.5 InvertStop ................................................................................................................................ 53
5.10.6 InvertGate................................................................................................................................ 54
5.10.7 ArmMeasurement..................................................................................................................... 54
5.10.8 NextMeasurement .................................................................................................................... 54
5.10.9 Armed ...................................................................................................................................... 55
5.10.10 Pending................................................................................................................................ 55
5.10.11 Ready ................................................................................................................................... 55
5.10.12 ClkDivider ........................................................................................................................... 55
5.10.13 Counter ................................................................................................................................ 56
5.10.14 Result ................................................................................................................................... 56
5.10.15 Example ............................................................................................................................... 57
5.11 A/D CONVERSION ............................................................................................................................. 59
5.11.1 Gain ......................................................................................................................................... 59
5.11.2 Result ....................................................................................................................................... 59
5.11.3 Example ................................................................................................................................... 60
5.12 D/A CONVERSION ............................................................................................................................. 62
5.12.1 D/A control .............................................................................................................................. 62
5.12.2 Example ................................................................................................................................... 63
6. TEST APPLICATIONS........................................................................................................................ 64
6.1 DIGITAL IO TEST .............................................................................................................................. 64
6.2 TIMER/COUNTER TEST...................................................................................................................... 65
6.3 PWM TEST ....................................................................................................................................... 66
6.4 ENCODER TEST ................................................................................................................................. 67
6.5 FREQUENCY METER TEST ................................................................................................................. 67
6.6 CHRONOMETER TEST ........................................................................................................................ 69
6.7 A/D CONVERSION TEST .................................................................................................................... 71
6.8 D/A CONVERSION TEST .................................................................................................................... 72

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NOTES

MATLAB, Simulink, RTW and RTWT are registered trademarks of The MathWorks, Inc.
Windows 95/98/NT/2000/XP are registered trademarks of Microsoft Corporation

Copyright INTECO 2010. All rights reserved.

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1. GENERAL INFORMATION

The RT-DAC/USB2 is a multifunction analog and digital I/O board dedicated to real-time data acquisition
and control in the Windows 95/98/NT/2000/XP environments. The board contains a Xilinx FPGA chip. All
boards are built as the OMNI version. It means the boards can be reconfigured to introduce a new
functionality of all inputs and outputs without any hardware modification.
The default configuration of the FPGA chip accepts signals from incremental encoders and generates PWM
outputs, typical for mechatronic control applications and is equipped with the general purpose digital
input/outputs (GPIO), A/D and D/A converters, timers, counters, frequency meters and chronometers.
The RT-DAC/USB2 board is distributed in two versions:
• analog and digital (RT-DAC/USB2) and
• digital only (RT-DAC/USB2-D).
This manual contains description for the both versions. In the case, if any facility of the board relates to one
version only, this fact is clearly marked.

1.1 Specification

Analog section (not available in the RT-DAC/USB2-D version)

Analog Inputs
Channels: 16 single-ended, multiplexed
Resolution: 12 bit
Input ranges: ±10V, programmable gain (x1, x2, x4, x8, x16)
Conversion time: 5.4 µs
Trigger: all the A/D channels are scanned automatically when USB host
requires data
Reference voltage: on-board

Analog Outputs
Channels: 4
Resolution: 12 bit / 14 bit
Output range: ± 10V, ± 5V
Settling time: 10 µs (to 0.01%)
Reference voltage: on-board

Digital section (version 1.03)

Digital Input/ Output

Channels: 26 bi-directional, direction setting; 8 channels shared with
PWM outputs; some inputs shared with counter, timer,
chronometer and frequency meter inputs
Direction: bi-directional, individually software programmable
Input voltage: VIH = 2.0V÷3.6V, VIL = - 0.5V÷0.8V
Output voltage: VOH = 2.4V (min), VOL = 0.4V (max)
Output current: 2mA per channel
Standard: LVTTL

Digital Timer/Counter
32 bit timer / counter : 2 channels, counts internal clock signal or external
impulses . External pulse duration: min 50ns

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PWM Outputs
Channels: 4
Resolution: 8/12 bits (software selected)
Base frequency: programmable, initial 16-bits divider

Incremental encoders
Channels: 4
Output: 32 bit counter
Index Software configured. 2 modes: with and without index,
selectable active level of the index signal

USB features
USB 2.0 hi-speed specification compliant.

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1.2 Board architecture

The block diagram of the RT-DAC/USB2 board is shown in Fig. 1.1. The block diagram of the digital
version is presented in Fig. 1.2.

Clock reference digital I/O

signal
PWM

encoders
XILINX
USB /FPGA
FPGA timer/counter
bridge
frequency meter

chronometer

Configuration A/D converter Programmable gain

USB Interface 16 channels
EEPROM

D/A converters D/A buffers

USB Bus
Fig. 1.1. General block diagram of the RT-DAC/USB2 board

Clock reference digital I/O

signal
PWM

encoders
XILINX
USB /FPGA
FPGA timer/counter
bridge
frequency meter

chronometer

Configuration
USB Interface EEPROM

USB Bus

Fig. 1.2. General block diagram of the RT-DAC/USB2-D board

The board is equipped with the 12-bit successive approximation A/D converters that give the 5 mV resolution
within the input range ±10V. A finer resolution can be achieved by the gain definition using digitally
programmable analog amplifier. The A/D conversion time of the RT-DAC/USB2 board is equal to 5.4 µs.
The board contains four 12-bits D/A converters connected to four analog output channels (optionally 14-bit
D/A converters are available). The output voltage of the channels is ± 10V. Each analog output channel can
sink up to 10 mA.

Reprogramming the XILINX FPGA chip at the boards can change functions of the board. The information
and specification how to reprogram XILINX FPGA is not included in this guide. Please, relate to
RTDAC/USB2 FPGA Programming Guide distributed by INTECO separately.

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2. BOARD INSTALLATION

The RT-DAC/USB2 setup contains:

• RT-DAC/USB2 board,
• Two 40-pin ribbon cables (only one cable when the digital version is distributed ),
• USB cable,
• CD containing a software and e-manuals,
• terminal wiring board (optional),
• 9V-12V DC / 4W stabilised power supply (optional). The plug dimensions are given in Fig. 2.2.

The layout of the RT-DAC/USB2 board is presented in Fig. 2.1

RT-DAC/USB2
USB socket

Power socket
CN2 and CN1 metal part
LEDs: 40-pins connectors
Power (CN1 not visible)
Programming enable φ 5.5 mm
Ready
min 13 mm
On/Off

Fig. 2.2. The plug of the DC power

Fig. 2.1. The layout of the RT-DAC/USB2 board
supply

The CN1 connector is not visible at the Fig. 2.1 because it is placed below the CN2 connector. The digital
version of the board is equipped with the CN1 connector only. The CN2 connector contains pins connected to
A/D inputs and D/A outputs only.
The Power signalling LED is emitting light when the On/Off switch is on, Ready LED indicates that the
communication between the RT-DAC/USB2 board and computer is running and Programming Enable LED
is emitting light when the board is ready to be programmed.

To install the board:

• install driver for the board (see below or CD:\DRIVER\readme*.txt),
• install RT-DAC/USB2 testing applications
• optionally install the RT-CON package,
• connect the board to the computer using the included USB cable,
• connect the national version of the DC 9V-12V stabilised power supply (not included). 9V DC
voltage is recommended.
• test the board (see section 6).

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3. DRIVER INSTALLATION

The driver for RT-DAC/USB2 board has to be installed. The user with administrator privileges must
install the drivers for Windows 2000 and Windows XP.

Windows 2000/XP installation

1. Start Microsoft Windows 2000/XP

2. Connect the RT-DAC/USB2 device and turn power ON
3. System detects a new USB device
4. Select the file CD:\driver\w2k_xp\cyusb.inf and then press OK

If the driver is not installed and the RT-DAC/USB2 device is connected to the PC it appears as
unknown device at the list of the devices in the Device Manager (see Fig. 3.1).

Fig. 3.1. Device list with an unknown device Fig. 3.2. Update driver option

Press the right mouse button at the Unknown device item and select the Update Driver Software item
(see Fig. 3.2). Select the Browse my computer for driver software option (DO NOT select the Search
automatically for updated driver software) and select the driver location as given in Fig. 3.3and Fig. 3.4.

Fig. 3.3. Browse the computer option Fig. 3.4. Select the driver

Windows displays the security warning caused by the uncertified driver. Please force the driver to be
installed (see Fig. 3.5). Finally the confirmation of the successful driver installation is given as presented in
Fig. 3.6.

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Fig. 3.5. Windows security warning

Fig. 3.6. Confirmation of the successful installation

The 64-bit versions of Windows require that all drivers are digitally certified, which the driver for
the RT_DAC/USB2 is not. A user needs to reboot the Windows PC and press F8 to show the boot
option list. The loading/installing unsigned drivers option has to be selected to allow installation of
the driver.

When the RT-DAC/USB2 is properly installed it is visible in the Device Manager at the list of devices
in the Universal Serial Bus controllers category as the InTeCo RT-DAC/USB2 entry (see Fig. 3.7).

Fig. 3.7. RT-DAC/USB2 device at the list of installed devices

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4. CONNECTOR PIN ASSIGNMENT

The digital version the RT-DAC/USB2D board is equipped with one 40-pin I/O connector CN1. The pin
assignment of the connector is shown in Table 1 and Fig. 4.1.

Table 1. RT-DAC/USB2 I/O CN1 pin assignment

CN1 Pin Power Digital Frequency

Counter PWM Encoder Chronometer
No supply I/O meter
1 DIO0 ENC0A Fr0G Ch0G
2 GND
3 DIO1 ENC0B Fr0St Ch0St
4 GND
5 DIO2 PWM0 ENC0I Fr0I Ch0StSt
6 GND
7 DIO3 ENC1A Fr1G Ch1G
8 GND
9 DIO4 ENC1B Fr1St Ch1St
10 GND
11 DIO5 PWM1 ENC1I Fr1I Ch1StSt
12 GND
13 DIO6 ENC2A Fr2G Ch2G
14 GND
15 DIO7 ENC2B Fr2St Ch2St
16 GND
17 DIO8 PWM2 ENC2I Fr2I Ch2StSt
18 GND
19 DIO9 ENC3A Fr3G Ch3G
20 GND
21 DIO10 ENC3B Fr3St Ch3St
22 DIO11 PWM3 ENC3I Fr3I Ch3StSt
23 DIO12 ENC4A Fr4G Ch4G
24 DIO13 ENC4B Fr4St Ch4St
25 DIO14 PWM4 ENC4I Fr4I Ch4StSt
26 DIO15 ENC5A Fr5G Ch5G
27 DIO16 ENC5B Fr5St Ch5St
28 DIO17 PWM5 ENC5I Fr5I Ch5StSt
29 DIO18 ENC6A Fr6G Ch6G
30 DIO19 ENC6B Fr6St Ch6St
31 DIO20 PWM6 ENC6I Fr6I Ch6StSt
32 DIO21 ENC7A Fr7G Ch7G
33 DIO22 ENC7B Fr7St Ch7St
34 DIO23 PWM7 ENC7I Fr7I Ch7StSt
35 DIO24 CNT 0
36 DIO25 CNT 1
37 GND
38 GND
39 +5.0 V
40 +3.3 V

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Digital I/O
Counter
PWM
Encoder
Frequency meter
Chronometer
Power

DIO0 ENC0A Fr0G Ch0G 1 2 GND

DIO1 ENC0B Fr0St Ch0St 3 4 GND
DIO2 PWM0 ENC0I Fr0I Ch0StSt 5 6 GND
DIO3 ENC1A Fr1G Ch1G 7 8 GND
DIO4 ENC1B Fr1St Ch1St 9 10 GND
DIO5 PWM1 ENC1I Fr1I Ch1StSt 11 12 GND
DIO6 ENC2A Fr2G Ch2G 13 14 GND
DIO7 ENC2B Fr2St Ch2St 15 16 GND
DIO8 PWM2 ENC2I Fr2I Ch2StSt 17 18 GND
DIO9 ENC3A Fr3G Ch3G 19 20 GND
DIO10 ENC3B Fr3St Ch3St 21 22 Ch3StSt Fr3I ENC3I PWM3 DIO11
DIO12 ENC4A Fr4G Ch4G 23 24 Ch4St Fr4St ENC4B DIO13
DIO14 PWM4 ENC4I Fr4I Ch4StSt 25 26 Ch5G Fr5G ENC5A DIO15
DIO16 ENC5B Fr5St Ch5St 27 28 Ch5StSt Fr5I ENC5I PWM5 DIO17
DIO18 ENC6A Fr6G Ch6G 29 30 Ch6St Fr6St ENC6B DIO19
DIO20 PWM6 ENC6I Fr6I Ch6StSt 31 32 Ch7G Fr7G ENC7A DIO21
DIO22 ENC7B Fr7St Ch7St 33 34 Ch7StSt Fr7I ENC7I PWM7 DIO23
DIO24 CNT0 35 36 CNT1 DIO25
GND 37 38 GND
+5V 39 40 +3.3V

Fig. 4.1. RT-DAC/USB2 I/O CN1 connector

The analog and digital version of the RT-DAC/USB2 board is equipped additionally with the CN2 40-pin
connector. The pin assignment of the connector is shown in Fig. 4.2.

Analog output
Analog input
Ground

A/I 0 1 2 GND
A/I 1 3 4 GND
A/I 2 5 6 GND
A/I 3 7 8 GND
A/I 4 9 10 GND
A/I 5 11 12 GND
A/I 6 13 14 GND
A/I 7 15 16 GND
A/I 8 17 18 GND
A/I 9 19 20 GND
A/I 10 21 22 GND
A/I 11 23 24 GND
A/I 12 25 26 GND
A/I 13 27 28 GND
A/I 14 29 30 GND
A/I 15 31 32 GND
A/O 0 33 34 GND
A/O 1 35 36 GND
A/O 2 37 38 GND
A/O 3 39 40 GND

Fig. 4.2. RT-DAC/USB2 I/O CN2 connector

The RT-DAC/USB2 board is equipped with 16 multiplexed analog inputs located at the CN2 connector.
They are named from A/I 0 down to A/I 15. The output of the analog multiplexer is connected to the input of
the digital programmable analog amplifier. The board is also equipped with four 12-bit D/A converters.
These outputs are named from A/O 0 down to A/O 3.
Only 26 pins at the CN1 connector are used as general-purpose digital I/O signals (DIO0 to DIO25). The
remaining pins are the ground and power (GND, +5V, +3.3V). The general purpose digital I/O signals can be
individually configured to be either the input or output.
As the number of general-purpose digital I/O signals is limited, all of them are shared with the signals of the
specialized blocks. The specialized blocks are implemented as the modules in the on-board FPGA structure.

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It means that the functions of the specialized block are hardware-implemented. The specialized blocks
are:

• PWM generators – there are eight PWM blocks. The outputs are marked: PWM0, PWM1, PWM2,
PWM3, PWM4, PWM5, PWM6 and PWM7,
• incremental encoders – the device contains eight incremental encoder channels. Each channel
requires three input signals – wave A (named from ENC0_A down to ENC7_A), wave B (from
ENC0_B to ENC7_B) and index (from ENC0_I to ENC7_I),
• counters – there are two counters available. The input signals are marked CNT0 and CNT1
respectively,
• frequency meters – RT-DAC/USB2 contains eight such blocks. The signals are named from
Fr0_G, Fr0_St and Fr0_I to Fr7_G, Fr7_St and Fr7_I,
• eight chronometer blocks – the signals are named from Ch0_G, Ch0_St and Ch0_StSt down to
Ch7_G, Ch7_St and Ch7_StSt.

There are two kinds of specialized blocks:

• the first kind of the specialized blocks contains digital output signals (PWM blocks). In this case
the appropriate pins of the CN1 connector can operate as the general purpose digital I/O signals or
as the output of the specialized block. The operating mode is determined by a mode configuration
register (CN1 Pin Mode Register). If they operate as general purpose digital I/Os their directions
and states are determined by the software. If they operate as the outputs of the specialized blocks
the state of the output is controlled by the PWM block. The states of the output signals can be read
by the software (the software can check the PWM output),
• the second kind of the specialized blocks contains only the digital input signals (the incremental
encoders, counters, frequency meters and chronometers). In this case it is not necessary to select
the operating mode of the block signals. If the appropriate general purpose I/O signals are
configured to be the inputs then their states can be read by the software and simultaneously the
signals excite the specialized block (see Fig. 4.3). If the shared general purpose I/O signals are
configured to be outputs their states can be set by the software and simultaneously the signals
excite the specialized block (see Fig. 4.4). This operating mode can be applied for testing of the
specialized blocks – for example the encoder can be excited and read in a software manner. This
testing strategy is not significant during common device applications. It may be very useful when
one wants to design and test his own FPGA blocks (see “USB Device XILINX Programming
Guide”)

FPGA
FPGA Pin

ENC0_A / DIO0 Read encoder

Encoder
Block

Read digital input

Fig. 4.3. The shared FPGA pin configured as the input

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FPGA
FPGA Pin

ENC0_A / DIO0 Read encoder

Encoder
Block

Set digital output

Fig. 4.4. The shared FPGA pin configured as the output

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