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EoC 1 Combinational Logic Part1

This document discusses combinational logic circuits, specifically adders. It begins by defining combinational circuits and providing examples. It then discusses half adders, which add two bits, and full adders, which add three bits. Circuit diagrams and HDL implementations are provided for half adders and full adders. The document explains how full adders can be combined to add multiple bit binary numbers. Exercises are provided to implement half and full adders using NAND gates on a Hack platform.

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32 views13 pages

EoC 1 Combinational Logic Part1

This document discusses combinational logic circuits, specifically adders. It begins by defining combinational circuits and providing examples. It then discusses half adders, which add two bits, and full adders, which add three bits. Circuit diagrams and HDL implementations are provided for half adders and full adders. The document explains how full adders can be combined to add multiple bit binary numbers. Exercises are provided to implement half and full adders using NAND gates on a Hack platform.

Uploaded by

sarangoudsai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Elements of Computing Systems-1

Combinational Logic (Part 1)

Dr. Jyothish Lal G, Assistant Professor (Sr. Gr)


Department of AI / Center for Computational Engineering and Networking (CEN)
Amrita School of AI, Coimbatore
Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken
Combinational Circuit
• Output depends only on the inputs that have been applied, and have no
bearing on the past history of the inputs

• Common examples:
– Adder, Subtractor
– Multiplexer,
– Demultiplexer
– Encoder

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 2


Adders
• Half Adder : designed to add two bits
• Full Adder : designed to add three bits
• Adder : designed to add two n-bit numbers

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 3


Half Adder

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 4


HDL implementation

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 5


Addition of multi-bit binary numbers

At every stage, we require to add 3 bits


•1 bit of number A We need a Full Adder
•1 bit of number B
•1 carry bit coming from previous stage

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 6


Full Adder
• Has 3 inputs and 2 outputs
– Inputs: inputs A and B, and carry input Cin
– Output: the sum S , and carry output Cout

• To add multi-bit numbers, we use a cascade of full


adders

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 7


Full Adder

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 8


Gate level implementation
a b c

sum

carry

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 9


HDL implementation

Test it in
hardware
simulator :
DEMO

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 10


Full adder using Half adder
A Sum → 3 Input XOR
S
B using two 2 input XOR
Cin
Cout
Carry

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 11


Hack exercises
• Half adder
• Full adder using two half adders and an OR
gate
• Realize half adder and full adder using NAND
gates; implement and test in Hack platform

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 12


Thank You

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 13

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