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    Pw1 Cmos Daniel f1070

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    iskandardaniel0063
    This document contains details of a practical work assignment on layout design and simulation of NMOS and PMOS transistors, including: 1) Sections for student and lecturer details, group number, marks, and submission/return dates. 2) Requirements to complete the layout and simulation of an NMOS transistor without DRC errors, and produce its cross section, characteristics curve, and timing diagram. 3) The same requirements for a PMOS transistor. 4) Discussion questions addressing technology features, micron and lambda units, design rules, differences in NMOS and PMOS layout sizes and characteristics, and their logic level passing abilities.

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    Pw1 Cmos Daniel f1070

    Uploaded by

    iskandardaniel0063
    8 views9 pages
    This document contains details of a practical work assignment on layout design and simulation of NMOS and PMOS transistors, including: 1) Sections for student and lecturer details, group number, marks, and submission/return dates. 2) Requirements to complete the layout and simulation of an NMOS transistor without DRC errors, and produce its cross section, characteristics curve, and timing diagram. 3) The same requirements for a PMOS transistor. 4) Discussion questions addressing technology features, micron and lambda units, design rules, differences in NMOS and PMOS layout sizes and characteristics, and their logic level passing abilities.

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    This document contains details of a practical work assignment on layout design and simulation of NMOS and PMOS transistors, including: 1) Sections for student and lecturer details, group number, marks, and submission/return dates. 2) Requirements to complete the layout and simulation of an NMOS transistor without DRC errors, and produce its cross section, characteristics curve, and timing diagram. 3) The same requirements for a PMOS transistor. 4) Discussion questions addressing technology features, micron and lambda units, design rules, differences in NMOS and PMOS layout sizes and characteristics, and their logic level passing abilities.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    8 views9 pages

    Pw1 Cmos Daniel f1070

    Uploaded by

    iskandardaniel0063
    This document contains details of a practical work assignment on layout design and simulation of NMOS and PMOS transistors, including: 1) Sections for student and lecturer details, group number, marks, and submission/return dates. 2) Requirements to complete the layout and simulation of an NMOS transistor without DRC errors, and produce its cross section, characteristics curve, and timing diagram. 3) The same requirements for a PMOS transistor. 4) Discussion questions addressing technology features, micron and lambda units, design rules, differences in NMOS and PMOS layout sizes and characteristics, and their logic level passing abilities.

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    ELECTRICAL ENGINEERING DEPARTMENT

    ACADEMIC SESSION: ____________


    DEC50143 – CMOS IC DESIGN AND FABRICATION

    PRACTICAL Layout Design and Simulation of NMOS and PMOS


    WORK 1: Transistors

    PRACTICAL
    WORK DATE:
    LECTURER’S WAN ZAIMI BIN WAN YUSOF
    NAME:

    GROUP NO.:

    TOTAL
    MARKS
    STUDENT ID & NAME : (100%)

    (1) DANIEL ISKANDAR BIN MOHD SHUKRI


    (13DTK21F1070)

    (2)
    (3)

    DATE SUBMIT : DATE RETURN :

    RESULT

    1.NMOS a)Transistor layout without DRC error

    b. Transistor cross section


    c.Id/Vd Characteristics Curve
    d)Input/Output timing Diagram

    2.PMOS
    a)Transistor layout without DRC error

    b.Transistor cross section


    c.Id/Vd characteristics
    D Input/Output timing diagram

    DISCUSSION

    1.Explain the terminology ‘technology feature’. (2 marks)


    The term "technology feature" refers to a specific and distinctive characteristic or capability
    of a technological product or system. In the context of technology, a feature is a unique
    attribute or function that provides a certain benefit or advantage to the user. Technology
    features can vary widely depending on the type of technology in question, such as software,
    hardware, or a combination of both. These features are designed to meet specific user
    needs, enhance usability, or differentiate a product from others in the market.

    2.Describe the difference between micron and lambda unit in layout design
    process. (2 marks)

    In the context of layout design in the semiconductor industry, "micron" and "lambda" are
    units of measurement used to describe the dimensions of features on an integrated circuit.
    Here's a brief description of each:

    - Lambda is a unit of measurement that is used to express feature sizes in terms of the
    wavelength of light used in photolithography, a key process in semiconductor
    manufacturing.

    3.Explain the functions of design rules. (2 marks)


    Design rules are a set of constraints imposed on the geometry of the
    layout to ensure maximum yield for the components of the PIC in high-
    volume manufacturing. Just as in electronic-integrated circuits, the rules
    are created for a particular technology based on the fabrication process to
    reproduce the intended design.

    4.PMOS transistor is usually larger than NMOS transistor in layout. Give an


    explanation. (2 marks)

    The channel of a PMOS FET will be slightly wider than the channel of an
    NMOS FET for channels that are similarly doped due to differences in
    carrier mobility between P and N type semiconductors, resulting in equal
    channel resistance for both. The PMOS FET needs a larger chip area to
    create a wider channel.

    5.State TWO (2) differences between NMOS transistor layout and PMOS
    transistor layout. (2 marks)
    In a NMOS, carriers are electrons, while in a PMOS, carriers are holes. When a high voltage
    is applied to the gate, NMOS will conduct, while PMOS will not.

    6.NMOS and PMOS transistors are good at passing which logic level?
    Explain your answer. (2 marks)
    PMOS pass transistor passes Strong '1' but weak '0' . An NMOS pass-transistor can pull
    down to the positive supply rail, but it can only be pull-down to a threshold voltage above
    the negative rail.

    CONCLUSION

    In conclusion, in practical work 1 I was able to install microwind and use it in


    cemos. I can also describe circuits like mos transistors. I can also use this skill
    in the future.

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