8-bit AVR Microcontroller

ATmega32A

DATASHEET SUMMARY

Introduction
®
The Atmel ATmega32A is a low-power CMOS 8-bit microcontroller based
®
on the AVR enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the ATmega32A achieves throughputs close to
1MIPS per MHz. This empowers system designer to optimize the device for
power consumption versus processing speed.

Features
• High-performance, Low-power Atmel AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 32Kbytes of In-System Self-programmable Flash program
memory
– 1024Bytes EEPROM
– 2Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
This is a summary document. A – Extensive On-chip Debug Support
complete document is available – Programming of Flash, EEPROM, Fuses and Lock Bits through
on our Web site at the JTAG Interface
www.atmel.com • Atmel QTouch® library support

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
 – Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels in TQFP Package Only
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V
• Speed Grades
– 0 - 16MHz
• Power Consumption at 1MHz, 3V, 25°C
– Active: 0.6mA
– Idle Mode: 0.2mA
– Power-down Mode: < 1μA

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Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description.................................................................................................................4

2. Configuration Summary............................................................................................. 5

3. Ordering Information..................................................................................................6

4. Block Diagram........................................................................................................... 7

5. Pin Configurations..................................................................................................... 8
5.1. VCC............................................................................................................................................... 9
5.2. GND..............................................................................................................................................9
5.3. PortA (PA7:PA0)........................................................................................................................... 9
5.4. Port B (PB7:PB0)........................................................................................................................10
5.5. Port C (PC7:PC0).......................................................................................................................10
5.6. Port D (PD7:PD0).......................................................................................................................10
5.7. RESET........................................................................................................................................10
5.8. XTAL1.........................................................................................................................................10
5.9. XTAL2......................................................................................................................................... 11
5.10. AVCC........................................................................................................................................... 11
5.11. AREF.......................................................................................................................................... 11

6. Resources................................................................................................................12

7. Data Retention.........................................................................................................13

8. About Code Examples............................................................................................. 14

9. Capacitive Touch Sensing....................................................................................... 15

10. Packaging Information.............................................................................................16

10.1. 44-pin TQFP...............................................................................................................................16
10.2. 40-pin PDIP................................................................................................................................ 17
10.3. 44-pin VQFN...............................................................................................................................18

11. Errata....................................................................................................................... 19
11.1. ATmega32A, rev. J to rev. K....................................................................................................... 19
11.2. ATmega32A, rev. G to rev. I........................................................................................................20
1. Description
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega32A provides the following features: 32Kbytes of In-System Programmable Flash Program
memory with Read-While-Write capabilities, 1024bytes EEPROM, 2048bytes SRAM, 32 general purpose
I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging
support and programming, three flexible Timer/Counters with compare modes, Internal and External
Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit
ADC with optional differential input stage with programmable gain (TQFP package only), a programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving
modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter,
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the next
External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize
switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega32A is a powerful microcontroller that
provides a highly-flexible and cost-effective solution to many embedded control applications.
The Atmel AVR ATmega32A is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and
evaluation kits.

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2. Configuration Summary
Features ATmega32A
Pin count 44
Flash (KB) 32
SRAM (KB) 2
EEPROM (KB) 1
General Purpose I/O pins 32
SPI 1
TWI (I2C) 1
USART 1
ADC 10-bit, up to 76.9ksps (15ksps at max resolution)
ADC channels 8
AC propagation delay Typ 400ns
8-bit Timer/Counters 2
16-bit Timer/Counters 1
PWM channels 4
RC Oscillator +/-3%
VREF Bandgap
Operating voltage 2.7 - 5.5V
Max operating frequency 16MHz
Temperature range -55°C to +125°C
JTAG Yes

Atmel ATmega32A [DATASHEET] 5

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3. Ordering Information
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
ATmega32A-AU 44A
ATmega32A-AUR(3) 44A
ATmega32A-PU 40P6 Industrial (-40oC to 85oC)
ATmega32A-MU 44M1

16 2.7 - 5.5V ATmega32A-MUR(3) 44M1

ATmega32A-AN 44A
ATmega32A-ANR(3) 44A
Extended (-40oC to 105oC)(4)
ATmega32A-MN 44M1
ATmega32A-MNR(3) 44M1

Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
4. See characterization specifications at 105°C

Package Type
44A 44-lead, 10 × 10 × 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP)
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1 44-pad, 7 × 7 × 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

Atmel ATmega32A [DATASHEET] 6

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4. Block Diagram
Figure 4-1. Block Diagram

SRAM

TCK
TMS
CPU
TDI
JTAG OCD
FLASH
TDO

PARPROG NVM
MOSI programming EEPROM
EEPROMIF
MISO SPIPROG
SCK

Clock generation
XTAL1 D
8MHz 8MHz Power A
Crystal Osc Calib RC
management T
12MHz A PA[7:0]
XTAL2
External External and clock I/O PB[7:0]
B
RC Osc clock control U PORTS PC[7:0]
TOSC1 PD[7:0]
32.768kHz 1MHz int S
XOSC osc
TOSC2

ExtInt INT[2:0]

VCC
Power Watchdog
Supervision Timer
RESET ADC ADC[7:0]
POR/BOD & AREF

GND RESET
Internal AIN0
Reference AC AIN1
ADCMUX

MISO
MOSI
SCK
SPI TC 0 T0
(8-bit sync) OC0
SS

OC1A/B/C
SDA
TWI TC 1 T1
SCL (16-bit)
ICP1

RxD0
TxD0 USART 0 TC 2 OC2
(8-bit async)
XCK0

Atmel ATmega32A [DATASHEET] 7

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5. Pin Configurations
Figure 5-1. Pinout TQFP ATmega32A
Power

PB3 (AIN1/OC0)
PB2 (AIN0/ INT2)

PB0 (XCK/T0)
Ground

PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
Programming/debug

PB4 (SS)

PB1 (T1)
Digital

GND
VCC
Analog

Crystal/Osc 44
43
42
41
40
39
38
37
36
35
34
(MOSI) PB5 1 33 PA4 (ADC4)
(MISO) PB6 2 32 PA5 (ADC5)
(SCK) PB7 3 31 PA6 (ADC6)
RESET 4 30 PA7 (ADC7)
VCC 5 29 AREF
GND 6 28 GND
XTAL2 7 27 AVCC
XTAL1 8 26 PC7 (TOSC2)
(RXD) PD0 9 25 PC6 (TOSC1)
(TXD) PD1 10 24 PC5 (TDI)
(INT0) PD2 11 23 PC4 (TDO)
12
13
14
15
16
17
18
19
20
21
22
(INT1) PD3
(OC1B) PD4
(OC1A) PD5

GND
(ICP1) PD6
(OC2) PD7
VCC

(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3

Atmel ATmega32A [DATASHEET] 8

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
 Figure 5-2. Pinout PDIP ATmega32A

AIN0/ INT2

5.1. VCC
Digital supply voltage.

5.2. GND
Ground.

5.3. PortA (PA7:PA0)

Port A serves as the analog inputs to the A/D Converter.

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 Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can
provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive
characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and
are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A
pins are tristated when a reset condition becomes active, even if the clock is not running.

5.4. Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega32A as listed in Alternate
Functions of Port B.

5.5. Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG
interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated
even if a reset occurs.
The TD0 pin is tristated unless TAP states that shift out data are entered.
Port C also serves the functions of the JTAG interface and other special features of the ATmega32A as
listed in Alternate Functions of Port C.

5.6. Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega32A as listed in Alternate
Functions of Port D.

5.7. RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in System and Reset Characteristics. Shorter
pulses are not guaranteed to generate a reset.

5.8. XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Atmel ATmega32A [DATASHEET] 10

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5.9. XTAL2
Output from the inverting Oscillator amplifier.

5.10. AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

5.11. AREF
AREF is the analog reference pin for the A/D Converter.

Atmel ATmega32A [DATASHEET] 11

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
6. Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.

Atmel ATmega32A [DATASHEET] 12

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
7. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.

Atmel ATmega32A [DATASHEET] 13

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
8. About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

Atmel ATmega32A [DATASHEET] 14

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
9. Capacitive Touch Sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most
®
Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.

Atmel ATmega32A [DATASHEET] 15

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10. Packaging Information

10.1. 44-pin TQFP

P IN 1 IDENTIFIER

P IN 1
e B
E1 E

D1
D

C 0°~7°

A1 A2 A
L
COMMON DIMENS IONS
(Unit of Me a s ure = mm)

S YMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2

Note s : E 11.75 12.00 12.25

1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. E1 9.90 10.00 10.10 Note 2
2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble
B 0.30 0.37 0.45
protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum
pla s tic body s ize dime ns ions including mold mis ma tch. C 0.09 (0.17) 0.20
3. Le a d copla na rity is 0.10mm ma ximum. L 0.45 0.60 0.75
e 0.80 TYP

06/02/2014

44A, 44-le a d, 10 x 10mm body s ize , 1.0mm body thickne s s ,

44A C
0.8 mm le a d pitch, thin profile pla s tic qua d fla t pa cka ge (TQFP )

Atmel ATmega32A [DATASHEET] 16

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
10.2. 40-pin PDIP

D
PIN
1

E1

SEATING PLANE

A1
L
B
B1
e

E
COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE
eB A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
Notes: L 3.048 – 3.556
1. This package conforms to JEDEC reference MS-011, Variation AC. C 0.203 – 0.381
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). eB 15.494 – 17.526
e 2.540 TYP

13/02/2014

40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual

Inline Package (PDIP) 40P6 C

Atmel ATmega32A [DATASHEET] 17

Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
10.3. 44-pin VQFN

Marked Pin# 1 I D

SE ATING PLANE

A1
TOP VIEW
A3
A
K
L
Pin #1 Co rne r SIDE VIEW
D2

1 Option A Pin #1 COMMON DIMENSIONS

Triangl e
2 (Unit of Measure = mm)
3
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
E2
Option B
Pin #1 A1 – 0.02 0.05
Cham fe r
(C 0.30) A3 0.20 REF
b 0.18 0.23 0.30
D 6.90 7.00 7.10
K Option C Pin #1
D2 5.00 5.20 5.40
e Notch
b (0.20 R) E 6.90 7.00 7.10

BOTTOM VIEW E2 5.00 5.20 5.40

e 0.50 BSC
L 0.59 0.64 0.69
Note : JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 .
K 0.20 0.26 0.41

9/26/08
TITLE GPC DRAWING NO. REV.
Package Drawing Contact: 44M1, 44-pad, 7 x 7 x 1.0mm body, lead
[email protected] pitch 0.50mm, 5.20mm exposed pad, thermally ZWS 44M1 H
enhanced plastic very thin quad flat no
lead package (VQFN)

Atmel ATmega32A [DATASHEET] 18

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11. Errata

11.1. ATmega32A, rev. J to rev. K

• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take
longer than
expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable the Analog Comparator before
the first
conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous
Timer/Counter register (TCNTx) is 0x00.

Problem Fix/Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00
before writing
to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register
(TCNTx), or
asynchronous Output Compare Register (OCRx).
3. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by
all-ones
during Update-DR.

Problem Fix / Workaround

• If ATmega32A is the only device in the scan chain, the problem is not visible.
• Select the Device ID Register of the ATmega32A by issuing the IDCODE instruction or by
entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device
ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS
instruction to the ATmega32A while reading the Device ID Registers of preceding devices of
the boundary scan chain.
• If the Device IDs of all devices in the boundary scan chain must be captured simultaneously,
the ATmega32A must be the fist device in the chain.
4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.

Atmel ATmega32A [DATASHEET] 19

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 Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register
triggers an
unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

11.2. ATmega32A, rev. G to rev. I

• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take
longer than
expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable the Analog Comparator before
the first
conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous
Timer/Counter register (TCNTx) is 0x00.

Problem Fix/Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00
before writing
to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register
(TCNTx), or
asynchronous Output Compare Register (OCRx).
3. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by
all-ones
during Update-DR.

Problem Fix / Workaround

– If ATmega32A is the only device in the scan chain, the problem is not visible.
– Select the Device ID Register of the ATmega32A by issuing the IDCODE instruction or by
entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device
ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS
instruction to the ATmega32A while reading the Device ID Registers of preceding devices of
the boundary scan chain.

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Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016
 – If the Device IDs of all devices in the boundary scan chain must be captured simultaneously,
the ATmega32A must be the fist device in the chain.
4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register
triggers an
unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

Atmel ATmega32A [DATASHEET] 21

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Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com

© 2016 Atmel Corporation. / Rev.: Atmel-8155I-ATmega32A_Datasheet_Summary-08/2016

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SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any
applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without
an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the
operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments
unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically
designated by Atmel as automotive-grade.
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