Chapter 1.

Hardware Configuration

1. Feature
(a) MTS-Z80A, a training kit using a 8-bit CPU Z80 of Zilog, has a built-in various peripherals
and do not use optional circuits.
(b) This tool can show data by using PC after down loading or inputting Data with the Keypad
(c) It supports step functions rind disassembling. The program inputted in machine codes by
the keypad can be run line-by-line or step-by-step.
(d) This hardware can be conducted by the Demo program stored in the Monitor Program.
(e) When you make a program, you can use input function from a keyboard of your. PC and
displaying to PC Program stored in the Monitor Program.
(f) This Kit is easy-to-use on account of built-in Power Supply. It also has free-voltage system.

2. Memory Map
(a) You can easily, understand the Memory Map of this Kit by referencing detailed sheets and
Demo program.
(b) The address 0000H - FFFFH is allocated to ROM, 8000H - FFFFH to RAM.
(c) You can refer to the table bellow which has detailed address map.
(d) USER Memory has the same address as ROM area which is for ROM writing.

Then if the ROM is 2764 or 27128, insert ROM into USER MEMORY and move the short bat
down ROM and turn on the kit. Then ROM of USER MEMORY with be driven, but if ROM is
27256, delete MONITOR ROM and immediately insert ROM and turn on the switch.

A15 A14-A0 Address Description

ROM 0 X 4000H-7FFFH Monitor Program
RAM 1 X 8000H-FFFFH User Program
EXT ROM 0 X 0000H-3FFFH User Memory(ROM)
* X is '1' or '0'

3. I/O Map
(a) I/O port address From A3 to A7 is connected to the recorder 74LS154 IC, and From A0 to
A2 is directly connected to reserved ICs. However the unconnected pin in A0 - A2 can (a)
I/O port address From A3 to A7 is be '1' or'0'. The default value is '0'.
(b) In the case of additioning I/O to System Bus, A7 should be set to '1'

1
 Connected to Connected to
Physical
74LS154 corresponding IC Remark
Address
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 X 0 0 00H A Port
0 0 0 0 0 X 0 1 01H B Port
EXT
0 0 0 0 0 X 1 0 02H C Port
0 0 0 0 0 X 1 1 03H CW
0 0 0 0 1 X X 0 08H I.R
LCD
0 0 0 0 1 X X 1 09H D.R
KEY 0 0 0 1 0 X X X 10H Key Input
KEY CLR 0 0 0 1 1 X X X 18H Key Buffer Clear
0 0 1 0 0 X 0 0 20H A Port
0 0 1 0 0 X 0 1 21H B Port
ROM WR
0 0 1 0 0 X 1 0 22H C Port
0 0 1 0 0 X 1 1 23H CW
0 0 1 0 1 X 0 0 28H A Port
0 0 1 0 1 X 0 1 29H B Port
DOT
0 0 1 0 1 X 1 0 2AH C Port
0 0 1 0 1 X 1 1 2BH CW
DAC 0 0 1 1 0 X X X 30H DAC0808
0 0 1 1 1 0 0 0 38H Channel 0
0 0 1 1 1 0 0 1 39H Channel 1
0 0 1 1 1 0 1 0 3AH Channel 2
0 0 1 1 1 0 1 1 3BH Channel 3
ADC
0 0 1 1 1 1 0 0 3CH Channel 4
0 0 1 1 1 1 0 1 3DH Channel 5
0 0 1 1 1 1 1 0 3EH Channel 6
0 0 1 1 1 1 1 1 3FH Channel 7
0 1 0 0 0 X X 0 40H Command
8251
0 1 0 0 0 x x 1 41H Data
0 1 0 0 1 X 0 0 48H Count 0
0 1 0 0 1 X 0 1 49H Count 1
CTC
0 1 0 0 1 X 1 0 4AH Count 2
0 1 0 0 1 X 1 1 4BH Command
LED 0 1 0 1 0 X X X 50H 8 Bit LED
SWITCH 0 1 0 1 1 X X X 58H 8 Bit Switch
FND 0 1 1 0 0 X X X 60H FND
STEP 0 1 1 0 1 X X X 68H Stepping Motor
SPK 0 1 1 1 0 X X X 70H Speaker
ROM CONT 0 1 1 1 1 X X X 78H ROM WR Control

2
Chapter 2. HOW TO USE TRAINING KIT

1. Selection of Keypad/Serial
For using MTS-Z80A, you should decide whether you use Keypad directly
or PC connected through RS-232C Serial.

2. Function of Keypad

FUNCTION KEYS HEXADECIMAL KEYS

C D E F
STEP
SZH PNC SZH' PNC

8 9 A B
INS
IX IY SP I

4 5 6 7
ADDR GO
AF' BC' DE' HL'

0 1 2 3
RESET INC
AF BC DE HL

: RESET Key halts a currently running program or makes registers

RESET
initial condition

INC : increment the current address by 1

DEC : decrement the current address by 1

: Assign an address. You should put 4-digit address.

ADDR
Then it will turn into Data Mode.

: execute a User defied program. The address must be at

GO
from 5000H to FEFFH.

3
 : Validate and modify registers of MTS-Z80A for a single step.
REG
A non-used register is unimportant.

: Run a single step in the Assembly Mode.

STEP
Displaying current status not in the Assembly Mode.

: Transfer Non Maskable interrupt signal to CPU.

NMI
For the first time. it acts like RESET key, but you can modify.

: Insert data on the currently displayed address.

INS
Namely, data shifts backwards by 1 count.

3. Method by Keypad
(a) Basic Use
When you turn on the kit, One message below will display

MTS-Z80A
K&H MFG.

As above mentioned, after the Kit is turned on or a Key is pushed with holding the
RESET Key, the current mode will turn into the Serial mode. Then you cannot use the
Keypad.
A few seconds after not pushing the key, the mode will turn into the Keypad Mode and
the LCD will display as follows. After reset the address will be set to the address '8000H'
which is the starting address of RAM.

Addr. Data
8000 FF

4
(b) Data Confirmation
Without inserting data you cannot know what data of the address is in it.

Addr. Data : A few seconds after reset the data of the address
RESET
8000 FF_ '8000H' will display.

Addr. Data : The address increases by 1 the data of the address will
INC
8001 FF_ display.

Addr. Data : The address increases by 1 the data of the address will
INC
8002 FF_ display.

Addr. Data : The address decreases by 1 the data of the address

DEC
8001 FF_ will display.

(c) Input and Charlie of data

Input of data or modification to the address is the same way.
Let's the data of the address'8000H'change to'12H'.

Addr. Data
RESET
8000 FF_

: LSB digit shifts to MSB.

1 Addr. Data
A new data will be stored in LSB by pushing the button
BC 8000 F1_
which you want.

: LSB digit shifts to MSB.

2 Addr. Data
A new data will be stored in LSB by pushing the
DE 8000 12_
Button which you want.

5
(d) Validating and Modifying Registers
This section is only validating and modifying registers for a single step.
Unused register has no meaning. You don't still need to know the name and function
of a register. Let's change data of AF register to'1234H'.

Addr. Data
RESET
8000 12_

PC:8000 SP:FF00
REG
F:FF:SZHVNC

: Validating register by pushing INC,DEC buttons.

AF:FFFF BC:FFFF
INC Then register can be modified by the
DE:FFFF HL:FFFF
Hexadecimal key.

0 REGISTER MODIFY : You should change all the bits(16 bits) of the
AF AF:FFFF_ register.

1 REGISTER MODIFY
BC AF:FFF1_

2 REGISTER MODIFY
DE AF:FF12_

3 REGISTER MODIFY
HL AF:F123_

4 REGISTER MODIFY
AF’ AF:1234_

PC:8000 12 : After modifying the register, it will turns into the

LD (DE),A single step mode.

* Actually validation and modification of registers is for a single step.

6
(e) Modifying and Running an Address
You should input 4-digits of 16-bit to modify an address.
First, let's run the example given in the Monitor ROM.
The starting address of the program for flikering LED.

Addr. Data
RESET : After reset, the address will be '8000H'
8000 FF_

Addr. Data : The cursor shifts the address part by pressing the
ADDR
8000_ FF ADDR key

: Displayed data is the data of the real address

5 Addr. Data
‘0005H’. Its data may not be the same data written on
BC’ 0005_ FF
this manual.

0 Addr. Data
AF 0050_ C3

1 Addr. Data
BC 0501_ 20

0 Addr. Data
AF 5010_ 21

8 BIT LED TEST!

GO
K&H MFG.
* Immediately LED lower-left starts flickering.

7
(f) INS, DEL Function
INS and DEL are the functions INSERT and DELETE respectively,
which functions can help correcting typing errors. For example, when the address is not
correct by pushing the INC key twice or more, you can delete the data by pushing the
DEL key. Moreover,
when you want to insert data of an specific address you can do it by pushing the INS
key.
Let's start from 8000H and test INC, DEL functions.

Addr. Data
RESET : After reset, the address will be '8000H'
8000 FF_

0 Addr. Data
AF 8000 F0_

0 Addr. Data
AF 8000 00_

Addr. Data
INC
8001 FF_

1 Addr. Data
BC 8001 F1_

1 Addr. Data
BC 8001 11_

Addr. Data
INC
8002 FF_

Addr. Data : By pushing the INC key once again, you omit the data
INC
8003 FF_ of 8002H.

2 Addr. Data
DE 8003 F2_

2 Addr. Data
DE 8003 22_

8
 Addr. Data
INC
8004 FF_

4 Addr. Data
AF’ 8004 F4_

4 Addr. Data
AF’ 8004 44_

Addr. Data
INC’
8005 FF_

4 Addr. Data
AF’ 8004 44_

5 Addr. Data
BC’ 8005 F5_

5 Addr. Data
BC’ 8005 55_

Addr. Data
RESET : After reset, the address will be '8000H'
8000 00_

Addr. Data
INC
8001 11_

Addr. Data
INC
8002 FF_

Addr. Data
DEL : Delete the data of the address 8002H
8002 22_

Addr. Data
INC
8003 44_

Addr. Data : Insert the data to the address 8003H

INS
8003 00_ (the inserted data will be 00H)

9
 3 Addr. Data
HL 8003 03_

3 Addr. Data
HL 8003 33_

Addr. Data
INC
8004 44_

Addr. Data
INC
8005 55_

Addr. Data
RESET : Check one again if it is well- corrected.
8000 00_

Addr. Data
INC
8001 11_

Addr. Data
INC
8002 22_

Addr. Data
INC
8003 33_

Addr. Data
INC
8004 44_

Addr. Data
INC
8005 55_

10
Chapter 3. CPU Architecture

1. Z80 CPU
(a) Description of function of Each Pin

11
 Functions for each pin as followings.
Name of a Pin Action Description
A15 - A0 Addressing Addressing memory or I/O
Receiving or transmitting data
D7 - D0 Input and output of Data
to/from Memory or I/O
/MREQ Connecting CPU to Memory is selected when 'L' sign
(MEMORY REQUEST) data bus of Memory appears
/IORQ Connecting CPU to I/O is selected when 'L' sign
(I/O REQUEST) data bus of I/O appears
/RD CPU decodes the Data Memory or I/O is selected
(READ) from Memory, or I/O by MREQ or IORQ signal
/WR CPU outputs data from Memory or I/O is selected
(WRITE) Memory or I/O by MREQ or IORQ signal
For 'L' sign,
CPU will make the Bus high
Impedance when the currently
/BUSRQ Request the Bus Open currently running machine cycle
(BUS REQUEST) For use finish.
Namely, it is in disconnection.
Then the access to control is
Given to the External.
When CPU accepts BUSRQ signal
/BUSAK
Check if the Bus is and makes it high impedance.
(BUS
Open Then CPU outputs 'L' sign to
ACKNOWLEDGE)
Notify that the Bus is open.
By 'L' sign,
/INT(INTERRUPT) Request interrupt
CPU is requested to interrupt.
When the signal High goes to
Low, CPU is requested for NMI.
/NMI(NON MASKABLE
Request NMI Using EI or DI, INT interrupt signal
INTERRUPT)
can prevent interrupt, but NMI is a
uninterruptable signal.
Reflash signal for the
/RFSH Reflash
Dynamic RAM
In order to synchronize the speed
/WAIT Wait of slower Memory and I/O, CPU
signal is delayed.
/HALT Halt Notify that CPU is Halt
The speed of CPU depends on
this signal. the lowest value of 'H'
CLK Clock level is 0.6V.
Therefore, 330 Ohm is pulled-up
To apply.
When 3 clocks are applied 'L'
sign, CPU will be reset and
/RESET Reset
PC(program counter)
Goes to '0000H'.

12
(b) Clock Generating Circuit
Clock is generated at 2.4575MHz using crystal. It is provided
CPU with 330 Ohm pull-up resistance.
It is also used for Serial communications by division.

(c) Reset Circuit

Z80 CPU should be reset when L signs are applied more than
3 clocks, so it needs enough delay for the different reset
request timing of peripheral circuits.
For example, 8251 IC needs more than 6 clocks of pulse.

(d) NMI Generating Circuit

When the NMI Key of the Keypad is pushed, one NMI signal is applied to CPU by a single
pulse generating circuit. After Z80 CPU receives the NMI signal, the current program
counter is pushed to the STACK and jumps to 0066H. The address 0066H should
have a NMI routine. MTS-Z80A is designed. Is jump to FF00H. Therefore, the user
inputs an instruction which jumps to NMI routine, then NMI routine will execute the
routine.

13
(e) Registers Configuration of Z80-CPU

Registers configuration of Z80-CPU is shown in the following table.

Main Register Alternate Register Set

A F A' F'
B C B' C'
D E D' E'
H L H' L'

I(Interrupt Vector) R(Memory Reflash)

IX((Index Register)
IY(Index Register)
SP(Stack Pointer)
PC(Program Counter)

(f) Procedure of Running instructions

1) Instruction Fetch
i) output the data in PC(program counter) register through the address bus.
ii) store the instruction on Memory in IR(Instruction Register) of CPU through Bus.
iii) increment PC by 1

2) Instruction Execution
According to the data of IR, a Program will be executed, then the control signals
corresponding to each instruction are outputed. In that way, arithmetic operation and
transmission instructions are executed.

2. Instruction Set of Z80 CPU

(a) instruction Format
LD A,B : An op-code, LD means a transmission instruction, A is the first
operand(destination) and B is the second operand(source), The instructions are
executed in the way that the 2nd operand op-codes 1st operand. The instructions
are always executed in the right-to-left direction.

(b) The Length of a instruction

The length of instructions of Z80 CPU consists of from 1 byte to 4 bytes. the number
of instructions is 158. It has many. instructions compared to 8080A CPU which has
78 instructions. There are lots of convenient instructions in Z80 CPU, so it is very
easy to program. The following table shows the length.

14
1 byte command OP code Ex) CPL
OP code1 OP code2 CPDR, INDR
2 byte command
OP code1 Operand CP 98H
OP code1 OP code2 Displayment AND (IX+d)
3 byte command
OP code1 Operand Operand LD HL,1234H
OP code1 OP code2 Operand Operand LD IX,(nn)
4 byte command
OP code Operand Displayment Operand BIT 1,(IX+d)

15
Chapter 4. Data Transmission Instruction

1. 8-bit Data Transmitting

(a) Immediate Addressing
LD r,n : The method is the addressing of storing the data of the second operand, ‘r’
means any of the registers B, C, D, E, H, L, (HL), A. ‘n’ is a 1-byte data.
eq) Let's make the instruction which stores 98H at A register.
LD A,98H

(b) Register Addressing

LD r1,r2 : ‘r2’ refers to a source and ‘r1’ refers to a destination.
The data of the source register will be copied to the destination register
(the data of source will not be clear)
eq) Let's make the instruction which transmits the data of C register to A register.
LD A,C

(c) Direct Addressing

LD r,(nn) or LD (nn), r : ‘nn’ refers to the memory address of 16bit. Data can be
assigned from 0000H to FFFFH of Memory area of Z80.() means the data that
the address in the bracket designates.
eq) Let's make the instruction which transmits the data of A register to the address
8100H.
LD (8100H), A

(d) Indirect Addressing

LD r,(ss) or LD (ss),r : This command is for the addressing which uses pair
registers(BC, DE, or HL) or 16-bit registers.
eq) Let's make the instruction which transmits the data of B register to the address
that DE designates.
LD (DE),B

2. 16-bit Data Transmitting

(a) Extended Immediate Addressing
LD ss,nn : This addressing is the extended method of immediate addressing.
‘nn’ is 16-bit data.
eq) Let's make the instruction which store 1234H in BC
LD BC,1234H

16
(b) Extend Addressing
LD ss,(nn) : This addressing is the method that moves between pair register(or
16-bit register) and 2 bytes data to a destination.
eq) Let's make the instruction which stare 1234H in BC
LD BC,(1234H)

※ Then, the data of ‘1234H’ are transmitted to C register and the data' of 1234H+1
(1235H) are transmitted to B register.

(c) Index Addressing

LD r,(IX+d) : This addressing is the method that uses index register(IX,IY)
eql) Let's make the instruction which stores the data of 8050+10H in A register using
IX register.
LD IX,8050H
LD A,(IX+10H)

eq2) Let's change the mnemonics as above mentioned.

LD IX,8050H : DD 21 5080
LD A,(IX+10H) : DD 7E 10
※ In LD IX, 8050H the LSB and MSB exchanges.

Flag OP code the No.

Machine
Mnemonic Action of Status
S Z H P/V N C 76543210 HEX Cycle
Byte
11011101 DD
00100001 21
LD IX,mm IX←n1n2 * * * * * * 4 4 14
<- n2 ->
<- n1 ->

11011101 DD
LD r,(IX+d) r←(IX+d) * * * * * * 01rrr110 3 5 19
<- d ->

the value of rrr (used for r1 and r2)

Register Rrr reference
B 000
C 001
D 010
E 011
H 100
L 101
A 111

17
3. Other Methods of Addressing(except transmission instructions)
(a) Modified Page Zero addressing
RST n : In this addressing, a specific RST n designates the address n.
eq) if there in RST 10H, it will jump to 0010H

(b) Relative Addressing

JR n : Jumps to the address of the relative value (-128 ~ +127)
from the program counter after executing this instruction.

(c) Bit Addressing

SET b,r : Designates the bit of a register as an address.

(d) Implied addressing

CPL : The instructions itself designates to a specific register.

4. Test I
In order to store the follow value, let's make the program by using a 8-bit data
Transmission instruction and execute from the training kit.
A=00H, B=12H, C=34H, D=34H

Test 1-1. Make a program as follows.

LD A,00H
LD B,12H
LD C,34H
LD D,C
RST 08H ; Halt the program and Return to the Monitor Program.

Test 1-2. Modify the mnemonic into machine codes.

Machine Code Mnemonic Description
3E 00 LD A,00H ; transmits 00H to A
06 12 LD B,12H ; transmits 12H to B
0E 34 LD C,34H ; transmits 34H to C
51 LD D,C ; transmits (or copy) the data of C to D
CF RST 08H ; return to the Monitor

18
 Test 1-3. Assign the address. Allocate addresses from 8000H because the user
programing area is from 8000H to FEEEH. Then insert the starting address of
each line.
Address Machine Code Mnemonic Description
8000 3E 00 LD A,00H ; transmits 00H to A
8002 06 12 LD B,12H ; transmits 12H to B
8004 0E 34 LD C,34H ; transmits 34H to C
8006 51 LD D,C ; transmits (or copy) the data of C to D
8007 CF RST 08H ; return to the Monitor

Test 1-4. Let's insert the program into the training kit.

RESE Addr. Data

T 8000 FF_

3 E Addr. Data
HL SZ·H’ 8000 3E_

0 0 Addr. Data
INC
AF AF 8001 00_

0 6 Addr. Data
INC
AF DE’ 8002 06_

1 2 Addr. Data
INC
BC DE 8003 12_

0 E Addr. Data
INC
AF SZ·H’ 8004 0E_

3 4 Addr. Data
INC
HL AF’ 8005 34_

5 1 Addr. Data
INC
BC’ BC 8006 51_

C F Addr. Data
INC
SZ·H ·PNC’ 8007 CF_

19
Test 1-5. Let's insert the program into the training kit

8 0 0 0 Addr. Data
ADDR
IX AF AF AF 8000 3E_
※ You can use RESET key instead of ADDR 8000H

PC:8000 3E 00
STEP : Nothing executes yet
LD A,00H

: The result of LD A,00H PC:8002 06 12

STEP
the displayed data is the next operation LD B,12H

: showing the current program counter PC:8002 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC
※ When RESET Key is pushed, the Monitor program set the stack pointer to FF00H.
Unused registers are no meaning.

AF:00FF BC:FFFF
INC : checking the next register
DE:FFFF HL:FFFF

: After checking the register and

PC:8002 06 12
STEP pushing the STEP key, it shows the
LD B,12H
current status without further operation

PC:8004 0E 34
STEP : LD B,12H has been executed
LD C,34H

: showing the current program counter PC:8004 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC

AF:00FF BC:12FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:8004 0E 34
STEP : display the current status
LD C,34H

PC:8006 51
STEP : LD C,34H has been executed
LD D,C

20
 : showing the current program counter PC:8006 SP:FF00
REG
stack pointer and flag register F:FF:SZHVNC

AF:00FF BC:1234
INC : checking the next register
DE:FFFF HL:FFFF

PC:8006 51
STEP : display the current status
LD D,C

PC:8007 CF
STEP : LD D,C has been executed
RST 08H

: showing the current program counter PC:8007 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC

AF:00FF BC:1234
INC : checking the next register
DE:34FF HL:FFFF

5. Test 2
In order to store the follow value, let's make the program by using a 16-bit data
transmission
instruction and execute from the training kit.
BC=1234H, DE=5678H, HL=5678

Test 2-1. Make a program as follows.

LD BC,1234H
LD DE,5678H
LD HD
LD L,E
RST 08H : Halt the program and Return to the Monitor Program

Test 2-2. Modify the mnemonic into machine codes.

Address Machine Code Mnemonic Description
8000 01 34 12 LD BC,1234H :transmits 1234H to BC
8002 11 78 56 LD DE,5678H :transmits 5678H to DE
8004 62 LD H,D :transmits D to H
8006 6B LD L,E :transmits(or copy) E to L
8007 CF RST 08H :return to the Monitor

21
※ MSBs and LSBs of 16-bit register or its data should be exchanged.

Test 2-3. Let's insert the program into the training kit.

RESE Addr. Data

T 8000 FF_

0 1 Addr. Data
AF BC 8001 01_

3 4 Addr. Data
INC
HL AF’ 8001 34_

1 2 Addr. Data
INC
BC DE 8002 12_

1 1 Addr. Data
INC
BC BC 8003 11_

7 8 Addr. Data
INC
HL’ IX 8004 78_

5 6 Addr. Data
INC
BC’ DE’ 8005 56_

6 2 Addr. Data
INC
DE’ DE 8006 62_

6 B Addr. Data
INC
DE’ I 8007 6B_

C F Addr. Data
INC
SZ·H ·PNC’ 8008 CF_

22
Test 2-4. Let's see the state of the registers while executing the program using the single
step function.

RESE Addr. Data

T 8000 01_

PC:8000 01 34 12
STEP : Nothing executes yet
LD BC,1234H

: The result of LD BC,1234H PC:8003 11 78 56

STEP
the displayed data is the next operation LD DE,5678H

: showing the current program counter PC:8003 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC

AF:FFFF BC:1234
INC : checking the next register
DE:FFFF HL:FFFF

: After checking the register and

PC:8003 11 78 56
STEP pushing the STEP key, it is shows the
LD DE,5678H
current status without further operation

PC:8006 62
STEP : LD DE,5678H has been executed
LD H,D

: showing the current program counter PC:8006 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC

AF:FFFF BC:1234
INC : checking the next register
DE:5678 HL:FFFF

PC:8006 62
STEP : display the current status
LD H,D

PC:8007 6B
STEP : LD H,D has been executed
LD L,E

: showing the current program counter PC:8006 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC
23
 AF:FFFF BC:1234
INC : checking the next register
DE:5678 HL:56FF

PC:8007 6B
STEP : display the current status
LD L,E

PC:8008 CF
STEP : LD L,E has been executed
RST 08H

: showing the current program counter PC:8008 SP:FF00

REG
stack pointer and flag register F:FF:SZHVNC

AF:FFFF BC:1234
INC : checking the next register
DE:5678 HL:5678

6. Test 3
Let's analysis the following program and predict the value of BC register. Then insert the
program into the training kit and execute in order to compare the result to the predicted
value. 'INC HL' and 'INC A' are the instructions which increment the designated address
by 1.

Test 3-1. Let's analysis the following program. Setting a stack pointer is important, but let's
skip this procedure in this example. a stack pointer should be the address plus 1, so in
MTS-Z80A it is correct to set the stack pointer to FF00H. (the last address is FFFFH, but
Monitor program uses the address area from FF00H Ultimately the last user address
should be FEFFH. Then Adding 1 becomes FF00H)

Address Machine code Mnemonic

8000 31 00 90 LD SP,9000H
8003 21 20 80 LD HL,8020H
8006 3E 98 LD A,98H
8008 77 LD (HL),A
8009 23 INC HL
800A 3C INC A
800B 77 LD (HL),A
800C ED 4B 20 80 LD BC,(8020H)
8010 CF RST 08H

24
Test 3-2. Let's insert the program to the training kit and execute the program step-by-step
using the single step function. While at that, see the change of registers and data.(Input
method of the program is the same as mentioned in the previous sections)

RESE Addr. Data

T 8000 31_

PC:8000 31 00 90
STEP : Nothing executes yet
LD SP,9000H

PC:8003 21 20 80
STEP : LD SP,9000H has been executed
LD HL,8020H

: showing the current program counter PC:8003 SP:9000

REG
stack pointer and flag register F:FF:SZHVNC

PC:8003 21 20 80
STEP : display the current status
LD HL,8020H

PC:8006 3E 98
STEP : LD HL,8020H has been executed
LD A,98H

: showing the current program counter PC:8006 SP:9000

REG
stack pointer and flag register F:FF:SZHVNC

AF:FFFF BC:FFFF
INC : checking the next register
DE:FFFF HL:8020

PC:8006 3E 98
STEP : display the current status
LD A,98H

PC:8008 77
STEP : LD A,98H has been executed
LD (HL),A

: showing the current program counter PC:8008 SP:9000

REG
stack pointer and flag register F:FF:SZHVNC

25
 AF:98FF BC:FFFF
INC : checking the next register
DE:FFFF HL:8020

PC:8008 77
STEP : display the current status
LD (HL),A

PC:8009 23
STEP : LD (HL),A has been executed
INC HL

8 0 2 0 Addr. Data
ADDR
IX AF DE AF 8020 98_
※ In the case of checking the data of Memory while executing single step, you should set
again the last address of checking the data before. Then execute single step.

8 0 0 9 Addr. Data
ADDR
IX AF AF IY 8009 23_

PC:8009 23
STEP : display the current status
INC HL

PC:800A 3C
STEP : INC HL has been executed
INC A

: showing the current program counter PC:800A SP:9000

REG
stack pointer and flag register F:FF:SZHVNC

AF:98FF BC:FFFF
INC : checking the next register
DE:FFFF HL:8021

PC:800A 3C
STEP : display the current status
INC A

PC:800B 77
STEP : INC A has been executed
LD (HL),A

: showing the current program counter PC:800A SP:9000

REG
stack pointer and flag register F:89:S.…C

26
 AF:9989 BC:FFFF
INC : checking the next register
DE:FFFF HL:8021

PC:800B 77
STEP : display the current status
LD (HL),A

PC:800C ED 4B 20 80
STEP : LD (HL),A has been executed
LD BC,(8020H)

8 0 2 1 Addr. Data
ADDR
IX AF DE BC 8021 99_

8 0 0 C Addr. Data
ADDR
IX AF AF SZ·H 800C ED_

PC:800C ED 4B 20 80
STEP : display the current status
LD BC.(8020H)

PC:8010 CF
STEP : LD BC,(8020H) has been executed
RST 08H

: showing the current program counter PC:8010 SP:9000

REG
stack pointer and flag register F:89:S.…C

AF:9989 BC:9998
INC : checking the next register
DE:FFFF HL:8021
※ After executing the single step, you checked that BC register
has 9998H. Is that the same as the predicted value?

27
Chapter 5. Logic and Arithmetic Instructions

1. Flag Register
You should understand registers very well in order to efficiently use the arithmetic
instructions. The following details flag registers.

BIT
7 6 5 4 3 2 1 0
NO.
Sign S Z H P/V N C

Carry Flag

Negative Flag

Parity/ Overflow Flag

Auxiliary Carry Flag

Zero Flag

Sign Flag

※ has no mean

(a) C(Carry) Flag

C = 1, if the add operation produced a carry from the MSB of the operand or result.
If the subtract operation produced borrow, the flag will be also set. By Shift and Rotate
instructions, it is set or reset.
You can modify the carry flag according to the following instructions.
SCF : Set carry
CCF : Complement carry

(b) N(Subtract) Flag

N = 1 if the previous operation was a subtract. This flag is used in conjunction with the
decimal adjust instruction (DAA) to properly correct the result into packed BCD format
following addition or subtraction using operands with packed BCD format.

28
(c) P/V(Parity/overflow) Flag
This flag has the following functions.
① Parity Flag : Logical operations affect this flag with the parity of the result while
arithmetic operations affect this flag with the overflow of the result. If P/V holds parity,
P/V =1 if the result of the operation is even. P/V = 0 if the result is odd. If the P/V holds
overflow, P/V = 1 if the result of the operation produced an overflow.
② Overflow Flag : If the P/V holds overflow, P/V = 1 if the result of the operation produced
an overflow(the limit is -128～1127, for 16-bit operation -32768 ～ +32767)

③ Block Transfer instruction : checks if the register(B or BC) for using block transfer or
search instruction is 0 or not.

④ Checking the status of Interrupt Enable Flag : By using "LD A,I" or "LD A,R", You can
check the status of the flag because the content of the interrupt enable flip-flop(IFF2) is
copied into the P/V flag.

(d) H(Half Carry) Flag

H = 1 if the add or subtract operation produced a carry into or borrow from bit 4 of the
accumulator.

(e) Z(Zero) Flag

Z = 1 if the result of the operation is zero.
① arithmetic and logical operation instruction : if the result is zero, 2 =1, otherwise Z = 0
② compare instruction : if the compared data is the same, Z = 1, otherwise Z=0
③ bit-test instruction : if the particular bit is zero, Z = 1, otherwise Z = 0
④ block input/output instruction : For INI, IND, OUTI, OUTD instructions, if B register is
zero, Z = 1, otherwise Z = 0
⑤ Other function : at IN r,(C) instructions, if an input data is zero, Z = 1, otherwise Z = 0

(f) S(Sign) Flag

S = 1, if the MSB of the result is one
① two's complement : 1n 2's complement operation, if S = 1,
it is written positive. if S = 0, it is written negative.
bit 7 of the result or operand is a sign bit, so bit 7 is copied to the S flag.

② input instruction : at IN r,(C) if the MSB of the result is one, S = 1.

29
2. 8-bit Arithmetic instructions

(a) Increment and Decrement instruction (INC, DEC)

store the data in registers or the memory by incrementing and decrementing, Carry
Flag doesn't change.

(b) Add and Subtract instruction (ADD, SUB)

An operational unit of the addition and subtraction is A(Accumulator) register and the
result of the operation is stored into A register.

(c) Multi-byte Add and Subtract instruction (ADC, SBC)

In the operation of more than 2 bytes, ADC and SBC instruction are used. Unlike ADD
or SUB, ADC and SBC perform 16-bit add or subtract with carry which is produced
after the operation.

(d) Decimal Adjust Subtract instruction (DAA)

The decimal adjust instruction (DAA) to properly correct the result into packed BCD
format following addition or subtraction using operands with packed BCD format.

※ BCD(binary Coded Decimal) : presents decimal numbers (from 0 to 9) as 4-bit data.

The maximum number of re-presentable 4-bit data is 16, but the last 6 BCDs are not
used. BCD needs 4-bit to express 2 BCDs with one byte, which is called Packed BCD.

binary hexa BCD binary hexa BCD

0000 0 0 1000 8 8
0001 1 1 1001 9 9
0010 2 2 1010 A
0011 3 3 1011 B
0100 4 4 1100 C
not used
0101 5 5 1101 D
0110 6 6 1110 E
0111 7 7 1111 F

(e) Comparison instruction (CP)

Fetch the data of the operand of memory or register from A register and store the result
of the operation in the flag register. The content of the operand will not be changed,
which is used as conditional jump or call instructions.

30
3. 16-bit Arithmetic instructions
(a) Increment, Decrement instruction (INC, DEC)
store the data in registers or the memory by incrementing and decrementing. Importantly, in
16-bit INC, DEC Carry Flag doesn't change, so you should consider it.

(b) Add instruction (ADD)

In the 16-bit add operation, the operational units are HL, IX, IY registers.
Only carry flag affects the result of the operation.
There is no 16-bit subtract instruction.

(c) Multi-byte Add and Subtract instruction (ADC, SBC)

In the operation of more than 2 bytes, ADC and SBC instruction are used.
Unlike ADD or SUB, ADC and SBC perform 16-bit add or subtract with carry which is produced
after the operation.
Only HL register is used as the accumulator which can store the result of the operation.

4. Logical Operation Instructions

(a) Logical Operation Instructions (AND, OR, XOR, CPL, NEG)
The logical operation is executed only in the 8-bit operation.
The result of the operation with A register is stored in A register. After AND, OR, XOR
operation, Carry flag becomes zero.
Therefore these instructions are used to reset Carry flag in the multi-byte operation.
eq) XOR A : Clear A register and Carry flag
AND A : Keep A register and Clear Carry flag. Check if C is 0 or not.
OR A : the same way as AND A

CPL instruction changes A register into 1's complement

(bit inversion), and the flag register doesn't change.
NEG instruction changes A register into 2's complement and it is
used as arithmetic instruction. Action of NEG instruction
A ← 0-A. Namely, store the result of-subtracting the value of A register from 0 in A
register.

(b) Bit Operation instruction (BIT, SET, RES)

These instructions perform bit-test(BIT), set(SET) or reset(RES) of particular bit of the
memory or registers. BIT instruction affect Zero flag. SET and RES don't affect the flag
register.

31
(c) Rotate, Shift instruction (RL, RLC, RLA, RLCA etc)
① RL, RR instruction : In RL instruction, the register or the data of the Memory shifts 1 bit
left and the MSB goes into the Carry Flag. Then the Carry flag which is generated
preceding the instruction moves into the LSB. In RR instruction, the register or the data
of the Memory shifts 1 bit right and the LSB goes into the Carry Flag. Then the Carry
flag which is generated preceding the instruction moves into the LSB.

Cy MSB LSB
RL

MSB LSB Cy
RR

② RLC, RRC instruction : In RLC instruction, the register or the data of the Memory shifts
1 bit left and the MSB goes into the LSB with the Carry Flag. In RRC instruction, the
register or the data of the Memory shift 1 bit right and the LSB goes into the MSB with
the Carry Flag.

Cy MSB LSB
RLC

MSB LSB Cy
RRC

③ RLA, RRA : RLA and RRA respectively is the same as RL r and RR r instruction when
r register is A register, but the length is shorter, the execution speed is faster. The
change of the flag register is a little bit different.

④ RLCA, RRCA : RLCA and RRCA respectively is the same as RLC r and RRC r
instruction when r register is A register but the length is shorter, the execution speed is

⑤ faster. The change of the flag register is a little bit different.

32
⑥ SLA, SRA, SRL : These instructions are hard to understand, so very careful attention
is required to make a program. In SLA instruction the register or the data of the
Memory shifts 1 bit left and the MSB goes into the Carry Flag. 0 goes into the MSB. In
SRA instruction, the register or the data of the Memory shifts 1 bit right and the MSB
before shift is copied into the MSB after shift. LSB goes into the Carry Flag.

Cy MSB LSB
SLA

MSB LSB Cy
SRA

MSB LSB Cy
SRL

⑦ RLD, RRD : In RLD instruction, the data that A and HL register circles 4-bit left. 4 bit of
the MSB of A register doesn't change. RRD instruction, like RLD circles right.

RLD

RRD

33
 5. Test 1
Analyses the following program and record the change of the flag register and A register.
Let's input the program into the training kit and execute it.(a).

Test 1-1. Analysis the following program and make the table of the of the prediction
value.

8000 310090 LD SP,9000H

8003 A7 AND A
8004 0609 LD B,09H
8006 3EFF LD A,0FFH
8008 3C INC A
8009 88 ADC A,B
800A AF XOR A
800B 80 ADD A,B
800C C688 ADD A,88H
800E 37 SCF
800F 0E33 SBC 33H
8011 D625 SUB 25H
8013 CF RST 08H

Prediction Result
Register Flag Register Flag
Address Mnemonic
A S Z H V N C A S Z H V N C
8000 LD SP,9000H 00 1 1 1 1 1 1 00 1 1 1 1 1 1
8003 AND A
8004 LD B,09H
8006 LD A,0FFH
8008 INC A
8009 ADC A,B
800A XOR A
800B ADD A,B
800C ADD A,88H
800E SCF
800F SBC 33H
8011 SUB 25H

34
Test 1-2. Input the program into the training kit. Then execute the program step-by-step
by using single step function an observe the change of the registers.

RESE Addr. Data

T 8000 31_

PC:8000 SP:FF00
REG : check the register
F:FF:SZHVNC

0 REGISTER MODIFY!
: modify the AF resister
AF AF : FFFF_

0 0 F F REGISTER MODIFY!
AF AF ·PNC’ ·PNC’ AF : 00FF_

After modifying the resister, it is the step PC:8000 31 00 90

Mode LD SP,9000H

PC:8000 SP:FF00
REG : check the register
F:FF:SZHVNC

1 REGISTER MODIFY!
: modify the BC resister
BC BC : FFFF_

0 0 F F REGISTER MODIFY!
AF AF ·PNC’ ·PNC’ BC : 00FF_

After modifying the resister, it is the step PC:8000 31 00 90

Mode LD SP,9000H

PC:8003 A7
STEP : LD SP,9000H has been executed
AND A

PC:8004 06 09
STEP : AND A has been executed
LD B,09H

: showing the current program counter PC:8004 SP:9000

REG
stack pointer and flag register F:54:.ZHV..

35
 AF:0054 BC:00FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:8004 06 09
STEP : display the current status
LD B,09H

PC:8006 3E FF
STEP : LD B,09H has been executed
LD A,FFH

: showing the current program counter PC:8006 SP:9000

REG
stack pointer and flag register F:54:.ZHV..

AF:0054 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:8006 3E FF
STEP : display the current status
LD A,FFH

PC:8008 3C
STEP : LD A,FFH has been executed
INC A

: showing the current program counter PC:8008 SP:9000

REG
stack pointer and flag register F:54:.ZHV..

AF:FF54 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:8008 3C
STEP : display the current status
INC A

PC:8009 88
STEP : INC A has been executed
ADC A,B

: showing the current program counter PC:8009 SP:9000

REG
stack pointer and flag register F:50:.ZH...

36
 AF:0050 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:8009 88
STEP : display the current status
ADC A,B

PC:800A AF
STEP : ADC A,B has been executed
XOR A

: showing the current program counter PC:800A SP:9000

REG
stack pointer and flag register F:08:…...

AF:0908 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:800A AF
STEP : display the current status
XOR A

PC:800B 80
STEP : XOR A has been executed
ADD A,B

: showing the current program counter PC:800B SP:9000

REG
stack pointer and flag register F:44:.Z.V..

AF:0044 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:800B 80
STEP : display the current status
ADD A,B

PC:800C C6 88
STEP : ADD A,B has been executed
ADD A,88H

: showing the current program counter PC:800C SP:9000

REG
stack pointer and flag register F:08:.…..

AF:0908 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

37
 PC:800C C6 88
STEP : display the current status
ADD A,88H

PC:800E 37
STEP : ADD A,88H has been executed
SCF

: showing the current program counter PC:800E SP:9000

REG
stack pointer and flag register F:90:S.H...

AF:9190 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:800E 37
STEP : display the current status
SCF

PC:800F DE 33
STEP : SCF has been executed
SBC A,33H

: showing the current program counter PC:800F SP:9000

REG
stack pointer and flag register F:81:S....C

AF:9181 BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

PC:800F DE 33
STEP : display the current status
SBC A,33H

PC:8011 D6 25
STEP : SBC A,33H has been executed
SUB 25H

: showing the current program counter PC:8011 SP:9000

REG
stack pointer and flag register F:1E:..HVN.

AF:5D1E BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

38
 PC:8011 D6 25
STEP : display the current status
SUB 25H

PC:8013 CF
STEP : SUB 25H has been executed
RST 08H

: showing the current program counter PC:8013 SP:9000

REG
stack pointer and flag register F:2A:….N.

AF:382A BC:09FF
INC : checking the next register
DE:FFFF HL:FFFF

39
Chapter 6. Jump Instructions

1. Program Counter
Z80-CPU has the Program counter register. This register has the address of the next
instruction. After system reset, it returns to 0000H. Whenever CPU fetches the
instruction from the memory address to which PC points, PC is incremented. When jump
or call instructions are executed or the interrupt signal is received, the new address is
loaded to PC.

2. Unconditional Jump Instruction

Unconditional jump instruction jumps to the designated address independent of flag
registers.

(a) Absolute Jump (JP)

Absolute jump instruction loads 2 byte after the op-code to the PC. Namely, it jumps to
the address. The format is JP nn.

(b) Relative Jump (JR)

As above mentioned, JP instruction designates the real 2 byte address for jump. Unlike
JP, relative jump instruction format is JR e. e is the displayment byte which is expressed
as 2's complement of 1 byte ranging from -128 to +127. The absolute jump instruction
jumps to all the range, but the relative jump instruction has the disadvantage of jumping
only to the area ranging from -128 to +127. Instead, by the relative jump a program
can easily move to the other address of memory.

(c) Other Instructions of Absolute Jump

JP (HL), JP (IX), JP (IY) : load the data of register HL, IX, or IY to PC and Jumps to the
address.

3. Conditional Jump Instruction

(a) Absolute Conditional Jump Instruction
Conditional jump instructions check the flags. If the condition is in accord, jumps to the
absolute address. otherwise the next instruction is continued. The instruction format is
JP cc, nn, cc consists as follows.
Cc(Condition Code) Related flag
NZ(Non Zero) Zero Flag
Z(Zero)
NC(Non Carry) Carry Flag
C(Carry)
PO(Parity Odd) Parity Flag
PE(Parity Even)
P(Plus) Sign Flag
M(Minus)
40
(b) Relative Conditional Jump Instruction
The instruction checks the designated flag. If the condition is in accord, it jumps to the
relative address, otherwise the next instruction is continued. The instruction format is as
follows. JR NZ,e ; JR Z,e ; JR NC,e ; JR C,e (e is the displayment byte)

(c) Other Instruction of Relative Conditional Jump

In Z80 instruction set, DJNZ n is the useful instruction of combining the arithmetic
operation instruction and relative jump function. Register B is used for this instruction.
The instruction subtracts 1 from B register. Then if the result is not zero, jumps to the
relative address
“DJNZ e” is the same as
DEC B
JR NZ,e

4. Test 1
Test 1-1. Analyses the following program to know what the program does.

8000 310090 LD SP9000H

8003 AF XOR A
8004 47 LD B,A
8005 210081 LD HL,8100H
8008 77 INC (HL),A
8009 23 INC HL
800A 3C INC A
800B 10FB DJNZ J1
800D CF RST 08H

Test 1-2. Insert the program into the Kit and execute the program by pushing GO key.
Then see what the result is. Inserting 'RST 08H' at the last address of the program
and Pushing Go key has the same result as setting the breakpoint at the address
which has RST 08H. Namely all the registers are already stored right after RST 08H
executes, so you can check by pushing the REG key. If the RESET key is pushed,
the stack pointer changes to FF00H without changing other registers. By using Go
function execute the program at once, but for training, single step function is used.
When you execute the program step-by-step, you can see the mnemonic DJNZ
8008H at 800BH. The exact notation is DJNZ FBH, but it was changed to help the
user disassemble the program from the Monitor program using single step function.

41
RESE Addr. Data
T 8000 31_

Addr. Data
GO
800D CF_

8 1 0 0 Addr. Data
ADDR
IX BC AF AF 8100 00_

Addr. Data
INC
8101 01_

Addr. Data
INC
8102 02_

Addr. Data
INC
8103 03_

- - - - - - - - - - - - - - - omitted - - - - - - - - - - - - - - - - - - - - - - - - - - -

Addr. Data
INC
81FD FD_

Addr. Data
INC
81FE FE_

Addr. Data
INC
81FF FF_

42
5. Test 2
Test 2-1. Analyses the following program to know what the program does.
Then compare that with Test 1

8000 310090 LD SP,9000H

8003 AF XOR A
8004 47 LD B,100D ;D of 100D means decimal
8006 210081 LD HL,8100H
8009 77 J1: INC (HL),A
800A 23 INC HL
800B C601 ADD A,1 ;After INC instruction, the decimal
;conversion is impossible.
; Instead, use ADD instruction.
800D 27 DAA
800E 10F9 DJNZ J1
8010 CF RST 08H

43
 Test 1-2. Insert the program into the Kit and execute the program by pushing GO key.
Then see what the result is.

RESE Addr. Data

T 8000 31_

Addr. Data
GO
8010 CF_

8 1 0 0 Addr. Data
ADDR
IX BC AF AF 8100 00_

Addr. Data
INC
8101 01_

Addr. Data
INC
8102 02_

Addr. Data
INC
8103 03_

- - - - - - - - - - - - - - - omitted - - - - - - - - - - - - - - - - - - - - - - - - - - -

Addr. Data
INC
8161 97_

Addr. Data
INC
8162 98_

Addr. Data
INC
8163 99_

44
Chapter 7. Stack and Subroutine

1. Stack Pointer
(a) Stack
Stack is the place that the data of registers is stored in the temporary memory or the
return address of subroutine call is stored. In the stack, the data that are first stored in
are first poked out.

(b) PUSH, POP

PUSH instruction performs storing the value of a register in the stack. The instruction
uses pair registers AF, BC, DE, HL and 16-bit registers IX, IY. After PUSH executes, the
stack pointer decrement by 2. Unlike PUSH, POP receives the value of the register
stored from the stack. After POP executes, the SP increments by 2.

(c) Stack Pointer

Stack Pointer points to the address plus 1 which is to be pushed.
There is no data stored in the Memory pointed as the stack pointer. Therefore the stack
pointer is generally chosen the last address plus 1. For example if the last address of the
user memory(RAM) is 3FFFH, the stack pointer is 4000H.

2. Subroutine
Subroutine is the block of instructions which the programmer names after.
The subroutine jumps to the routine by the call instruction, and by the return instruction(RET)
returns to the main Program. When jumping to the routine the call instruction points to, CPU
stores the return address in the stack and jumps.

(a) Unconditional Call and Return(CALL, RET)

unconditional CALL instruction can be expressed as 'PUSH PC' and 'JP address'.
Then PC points to the next address of the CALL instruction( CALL instruction is 3byte,
so when CALL instruction is at 8000H, the next address is 8003H). RET instruction,
reversely of CALL, can be expressed as 'POP PC'
LD HL,8100H
PUSH HL
RET

If the programmer do the same program above, CPU jumps to the address's 8100H with
the execution of RET.

45
(b) Conditional Call1 and Return(CALL, RET)
When the condition is in accord, the conditional CALL instruction calls the subroutine,
otherwise the next instruction is continued. RET also returns if the condition is not in
accord, otherwise the next instruction is continued. The conditions for conditional CALL
and RET as follows.
cc(Condition code) related flag
NZ(Non Zero)
Zero Flag
Z(Zero)
NC(Non Carry)
Carry Flag
C(Carry)
PO(Parity Odd)
Parity Flag
PE(Parity Even)
P(Plus)
Sign Flag
M(Minus)

3. Test 1
Test 1-1. Analyse the following program to know what the program does. Then predict
the values of A, BC, DE, HL in the end of the program.

8000 310090 LD SP,9000H

8003 AF XOR A
8004 0E96 LD C,06H
8006 210081 LD HL,8100H
8009 E5 PUSH HL
800A 0605 J1: LD B,05H
800C CD1A80 J2: CALL COUNT
800B C601 ADD A,1
800F 10FB DJNZ J2
8011 CD1A80 CALL COUNT
8014 0D DEC C
8015 C29A80 JP NZ,Jl
8018 D1 POP DE
8019 CF RST 08H

810A 77 COUNT: LD (HL),A

801B 23 INC HL
801C 3C INC A
801D C9 RET

46
 Test 1-2. Insert the program into the Kit and execute the program by pushing GO key.
Then see what the result is.

RESE Addr. Data

T 8000 31_

Addr. Data
GO
8019 CF_

: showing the current program counter PC:8019 SP:9000

REG
stack pointer and flag register F:42:.Z..N.

AF:2442 BC:0000
INC : checking the next register
DE:8100 HL:8124

8 1 0 0 Addr. Data
ADDR
IX BC AF AF 8100 00_

Addr. Data
INC
8101 01_

Addr. Data
INC
8102 02_

Addr. Data
INC
8103 03_

- - - - - - - - - - - - - - - omitted - - - - - - - - - - - - - - - - - - - - - - - - - - -

Addr. Data
INC
8122 22_

Addr. Data
INC
8123 23_

Addr. Data
INC
8124 FF_

47
Chapter 8. Other Instructions

1. HALT instruction
When the HALT instruction executes, CPU repeats NOP instruction in order to keep the
Dynamic RAM reflash until CPU accepts the interrupt or the reset signal of the Hardware.

2. NOP instruction(No Operation)

NOP instruction do nothing and just waste the machine cycle. However it is useful for
synchronizing the Hardware or giving delay to the program.

3. RST instruction(Restart)
This instruction consists of 1 byte op-code and executes CALL instruction. From the
following table, 3 bit combination corresponding to ttt can make 8 addresses( the
combination: 00H, 08H, 10H, 18H, 20H, 28H, 30H, 38H)

Eq.) RST 08H performs the same action as CALL 0008H, but unlike CALL instruction,
it is a 1 byte instruction

Flag OP code the No.

Machine
Mnemonic Action of Status
S Z H P/V N C 76543210 HEX Cycle
bytes
Restart to
RST n * * * * * * 11ttt111 1 3 11
Loacation n

4.Input/output Instruction(IN,OUT)
MTS-Z80A consists of lots of external device such as LCD, PPI, CTC, which is called I/O
device. These I/O device writes and reads the data to/from the external.

IN A,(n) : write the data from the externals to A register. n is the 8-bit address of I/O
device.
IN r,(C) : write t C register points to.
OUT (n),A : output the 8-bit data of the pointed I/O register to A register r(any of B, C, D,
E, H, L,4) from the I/O device theater.
OUT C,r : output the data to a r register to the I/O device that C register points to.

48
5. Block Input/Output Instruction(INI, IDHR, IND etc)
① INI : receive the data from the I/O device that C register points to, store the data at
the address HL register points to. HL register increments and B register decrements.
Then Z = 1 if B register is zero, otherwise Z = 0.
② IND : the same as INI, but HL register decrements.
③ INIR : repeat INI instruction until B register is zero.
① INDR : repeat IND instruction until B register is zero.
⑥ OUTI : output the data of the address pointed by HL register to the I/O device that C
register points to. HL register increments and B register decrements. Then Z = 1 if B
register is zero, otherwise Z = 0.
⑥ OUTD : the same as OUTI, but HL register decrements.
⑦ OTIR : repeat OUTI instruction until B register is zero.
⑧ OTDR : repeat OUTD instruction until B register is zero.

6. Block Transfer Instruction (LDI, LDIR, LDD, LDDR)

The block transfer instructions have powerful function which transfer lots of data at one
time. In the Keypad, INS, DEL, MOVE functions use these instructions.

① LDI : transfer the data of the Memory pointed by HL register to the Memory at the address
HL register points to. HL and DE register increment, and BC register decrements. Then Z =
1 if B register is zero, otherwise Z = 0.
② LDIR : repeat LDI instruction until BC register is zero.
③ LDD : the same as LDI, but HL and DE register decrement.
④ LDDR : repeat LDD instruction until BC register is zero.

7. Block Search Instruction(CPI, CPIR, CPD, CPDR)

① CPI : compare the data of the Memory pointed by HL register with the data of the Memory
at the address HL register points to. Then Z = 1 if A = (HL), otherwise Z = 0. HL register
increments, and BC register decrements. P/V = 0 if BC register is zero, otherwise P/V = 1.
② CPD : the same as CPI, but HL register decrements.
③ CPIR : repeat CPI instruction until A = (HL) or BC =0.
④ CPDR : repeat CPD instruction until A = (HL) or BC =0.

49
Chapter 9. Interrupt

1. Z80 Interrupt
Z80-CPU has non-maskable interrupts(NMI) and maskable interrupts(INT Non-
maskable interrupt is prior to all the other interrupts and it is used for protecting the
system from power cut or black-out.

2. Non Maskable Interrupt

NMI literally means non-maskable interrupts and always accepts an interrupt signal.
Despite of interrupting by INT, NMI can occur. When Z80-CPU acknowledges NMI, it
stores PC in the stack and jumps to 0066H. At the end NMI routine RETN executes and
return to the routine before the Call instruction. If NMI occurs INT is forbidden.
MTS-Z80A reads the address from the Memory at FF01H, FF02H and jumps to that
address. For the start, the Monitor Programs is supposed to jump to the starting
address, namely it acts as RESET key is pursed.

3. Maskable Interrupt
Z80-CPU has 3 types of maskable interrupts(INT). These maskable interrupts allows the
programer to use El(Enable Interrupt) and Dl(disable Interrupt) instructions in order to
acknowledge or forbid. The control to acknowledge or forbid is done by two interrupt
enable flip-flops IFF1 and IFF2. If Z80-CPU is reset or DI instruction executes, the two
flip-flops are reset. If EI instruction execute, the two flip-flops are set. Once the two
flip-flops are reset. the interrupts is acknowledged. Nevertheless, the reason that there
are two filly-flops is the presence of NMI. If CPU receives NMI, IFF1 is reset. IFF2
doesn't change and indicates IFF1 before NMI requests. NMI is forbidden because IFF1
is reset. When NMI routine has finished, RETN instruction needs to execute. Then by this
instruction the status of IFF2 is copied into IFF1. Namely it returns to the routine just
before NMI interrupt occurs. After that it restores the PC in the stack and returns to the
previous routine. When the maskable interrupt routine halts, RETI instruction executes.

4. Mode 0 Interrupt
Z80-CPU is set to Interrupt Mode 0 when it is reset or IM0 instruction executes. Mode 0
interrupt is the mode that pheriparals transmits instructions through Bus. There is 1 byte
RST(Restart) and 3 byte CALL instruction of the types of instruction. RST is used most.

5. Mode 1 Interrupt
When IM1 instruction executes, the Mode is set to the interrupt Mode 1. If the interrupt
apply, CPU stores PC into the stack and jumps to 0038H. MTS-Z80A reads the address
from the Memory at FF04H and FF05H. For the start, the Monitor Programs is supposed
to jump to the starting address, namely it acts as RESET key is phased.
50
6. Mode 2 Interrupt
When IM2 instruction executes, the Mode is set to the interrupt Mode 2. The Mode 2
interrupt is called the vector interrupt. I register of Z80 registers is only used for Mode 2
interrupt. When the interrupt occurs, I register becomes the MSB of the vector. This
mode is only designed for Z80 family IC(8420, 8430 etc).

51
Chapter 10. Assembler

1. Z80 Assembler
Until now you has practised by hand assembling on the keypad. From now on, let's
practise using Editor program on the personal computer. At first, write the source
program and assemble it and compile it to HEX format. Then by using the serial monitor,
load the program into the training kit.

(a) Assembler Directive

Assembler directives are the instructions that provide information that the assembler
can convert the written program into the machine codes.

① ORG(Origin) : sets the starting address of the program or data

② END : it is written at the end of the source program. After End, nothing is converted into a
machine code.
③ EQU(Equate) : assign the value of the equation to the label when the equation of operand
and label is needed. Namely, it cause the symbol table to register the equation of the label.
Detailed description will be later.
④ DB(Define Byte) : is used to store the data to the Memory by the unit of 1 byte.
④ DW(Define Word): is used to store the data to the Memory by the unit of 2 bytes.
Remember that when the data is stored, the MSB and LSB is exchanged.
⑥ DS(Define Storage) : is used to obtain the memory by the unit of byte.

(b) Assembler Format

Using the assembler needs to follow the standard format. A assembly programs, called
a source program follows the format below.

Label Operation Operand ; Comment

Each part needs more than one space. After semicolons, the comments doesn't affect
the Program and only is used for comments. You can writhed everything you want in the
comment part.
① Label Part : Labels can be omitted. When you use a label, you have to write the first column
of the line, the length is limited to 8 characters. Generally when Label is used to indicate the
location of data or the address for Jump routines. It is also called symbolic address.
※ Reserved word(instruction or indicator) can be used as label.
※ Depending on assemblers colon is required.
※ There shouldn't be the space between a label and a colon.
② Operation Part : it is for instructions and assembler directives
③ Operand Part : the name of a register, integer, label
⑤ Comment Part : It is used for the explanation about the program. It can be omitted. When
the comment part is used, a semicolon is written before a comment.

52
2. Writing the Source Program
(a) Write the source program by using the editor program.
To edit the source code, simply edit it under any text editor, such as Notepad or Microsoft
Word. BE SURE that the file is saved with the extension of [ASM]. Creates a new file. Here
file name is EXAM.ASM.

Let's start editing.

ORG 8000H ;set the starting address of the program

LD SP,9000H ;set the stack pointer

XOR A ;clear A register
LD C,06H ;set circular count (C register = 6)
LD HL,8100H ;set the starting address of the data
PUSH HL ;store the value of HL register in the stack
J1: LD B,05H ;set circular count (C register = 5)
J2: CALL COUNT ;call the subroutine
DJNZ J2 ;B register decrement by 1. If B is not zero, jumps to J2
CALL COUNT ;call the subroutine
DEC C ;C register decrement by 1
JP NZ,J1 ;if not zero, jump to J1
POP DE ;transmit the value in the stack to DE register
RST 08H ;the user program halts

COUNT: LD (HL),A ;transmit the data of A register to the address

;of the memory that HL register points to
INC HL ;the address increments by 1
INC A ;A register increments by 1
RET ;return to be main routine
END ;the end of the program

After finishing input of the program, to save the file. Like that, after input in the source file, you
can assemble the program by using the Z80 Assembler.

The following step is to convert the assemble code [EXAM.ASM] to machine code
[EXAM.HEX].It is supported in Windows XP/7 32bits OS. Refer to Appendix 1 if your OS is
Windows 7 64 bits.

53
Step 1: Create a new folder on C:\ , and rename it “MTS80A”.

Step 2: Put your assembly code [*.asm] and assembler (X80.exe and LINK80.exe)
in this folder.

Step 3: Double click [X80.EXE] and type the source program(EXAM) in Input Filename.

Step 4: Press [Enter] twice. The object file [EXAM.OBJ] will be shown in the same folder.

54
Step 5: Double click [LINK80.EXE] and type the .obj file(EXAM.obj) and then click Enter 5
times to finish the link process.

Step 6: The hexadecimal file [EXAM.HEX] will be shown in the same folder. To download the
program into Z80 chip.

55
Chapter 11. How to Use the Serial Monitor

>From now on, execute the program by transmitting the data to MTS-Z80A through RS -232c
communication.

1. Communication Program
Use the “Hyper Terminal” communication program. It is supported in Windows XP OS.
Refer to Appendix 2 if your OS is Windows 7.

2. Serial Monitor Program

(a) Introduction
This program is the Software Education & Development Tool which make the executable
file by transmitting *.HEX file to MTS-Z80A. Namely it makes MTS-Z80A control the program
on the Emulator of PC. It also support the useful subroutines for input/output, so it Is very easy
to write a program.

(b) How to Drive the Program

From FF00H to FFFFH of the Memory of MTS-Z80A is in use by the Serial Monitor
Program. You should make a program in the range of 8000H～ FEFFH By using a given
RS-232C cable, connect PC to MTS-Z80A. At first, run the communication program.

If it is connected to COM 2 of PC, change to COM2 and save the settings. Then check if the
short bar Is plugged on the upper tilde of BUAD RATE which is on the MTS-Z80A board.
After preparing, push RESET key on the MTS-Z80A and push Hexa Key. Then it shows as
follows.
Serial Monitor
K&H MFG.

And On the PC monitor it shows as below

Z80 Training Kit Version 4.1

K&H MFG. CO., LTD.
MTS-Z80A >
(c) Description of Instruction
On the prompt of MTS-Z80A, if type 'H', Help will show to refer.

MTS-Z80A > H↵
###### HELP ######
1. Load from PC
L : Load program from PC through serial cable.

56
2. Memory Dump
D[start] , [end] : Dump the contents of memory to the display
Ex) D8000
3. Trace, Step execution of program

T or T[Count]
S or S[Count] : Trace the execution of the specified number
of instruction.
Ex) T05 or S10

4. Program Execution
G : runs the program.
Start Address is Reg.PC

<< Press and key to Continue (1/3)>> ↵

5. Program Execution
G[Break Point] : runs the program.
and terminates at Break Point.
You must be careful to choose Break Point.
Start Address is Reg.PC
Ex) G8080

6. Move
M start, end, destination : Move a block of data from a source
location in memory to a destination location.
Ex) M8000, 800F, 9000

7 Fill
F Start, End, Data : Fill a block in memory with the data.
Ex) F9000, 90FF, 98

8. Edit
E[Start] : Examine or modify the contents of memory
You can use <SPACE>, <.> for skipping.
Ex) E8080

<< Press and key to Continue (2/3)>> ↵

57
9. Register Check or Modify

R or R[Reg. Name] : Examine or modify the contents of

an internal register.
Ex) R or RBC

10. Disassemble
U or U[Count] : Disassemble the contents of memory
Defaults = 20 Lines

11. Rom writer

W : ROM Write or Read

I2. Clear
CLS : Clear the Monitor of PC.
* If you want to know more, contact Your Manual.

* K&H MFG. CO., LTD.

MTS-Z80A >

① LOAD
The instruction that transmits *.HEX file generated by assembling from PC to the training
kit.

MTS-Z80A > L↵
Then Press ? in order to allow the PC to transmit the data. Then send file' menu will
appear. On that menu select 'send' and input the file name. You can see the procedure of
transmitting to PC by the sign *. When you downloads the file, the data of the Memory after the
data loading fills with FFH. Then the Program Counter turns to 8000H.
**
PC SZ-H-VNC A BC DE HL IX IY SP I
8000:310090 11111111 FF FFFF FFFF FFFF FFFF FFFF FFFF FF
LD SP,9000H 11111111 FF FFFF FFFF FFFF

MTS-Z80A >
The data on PC has been transmitted to the MTS-Z80A training kit

58
② Go and GOTO
The transmitted Program can be executed by the GO, GOTO, STEP, TRACE. GO
instruction executes first the Program at the Program counter, GOTO instruction starts the
program at the current address and stops the execution at the address the user defines. Then
the address the user defines is called break points.

MTS-Z80A > G↵
Program Counter = 8000H

MTS-Z80A >
If execute GO instruction, the current address appears on the Monitor and executes the
program. Let's execute GO instruction The important thing is, the break points should be at the
starting address. Because the program counter has changed, change PC to 8000H and
execute GOTO instruction.
then stop the program at 8011H

MTS-Z80A > RPC↵

PC:8021 -> 8000
PC SZ-H-VNC A BC DE HL IX IY SP I
8000:310090 00000000 03 0206 FFFF 8130 FFFF FFFF 8FFF FF
LD SP,9000H 11111111 FF FFFF FFFF FFFF

MTS-Z80A > G8011↵

Program Counter = 8000H

PC SZ-H-VNC A BC DE HL IX IY SP I
8011:CD1A80 00000000 05 0006 FFFF 8105 FFFF FFFF 8FFF FF
CALL 801AH 11111111 FF FFFF FFFF FFFF

MTS-Z80A >
stop the Program, and display the value of each register at the time it stops.

③ STEP and TRACE

There is Bug(Run time error) when the program is made firstly. While executing the
program step-by-step, Checking the values of the Memory and registers, then observing the
change of the entire Program are the very easy way to debug the program. For debugging,
MTS-Z80A provides S and T instruction. You can input not only S,T instruction without any
operand, but also the number of execution such as S02, T05. When STEP, TRACE, DUMP
are input one time, they become defaults. After that, just pressing ENTER causes the program
to continue. STEP and TRACE has the similar function. Despite TRACE is a subroutine, it runs

59
one step. Unlike TRACE, STEP runs all the steps and the next step of the CALL instruction. It
helps trace the time delayed subroutine such as TIMER.

MTS-Z80A > T↵ : After that, TRACE function executes by only pressing ENTER
PC SZ-H-VNC A BC DE HL IX IY SP I
8003:4F 11111111 FF FFFF FFFF FFFF FFFF FFFF 9000 FF
XOR A 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
8006:0E06 01000100 00 FFFF FFFF FFFF FFFF FFFF 9000 FF
LD C,06H 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
8006:210081 01000100 00 FF06 FFFF FFFF FFFF FFFF 9000 FF
LD HL,8100H 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
8009:E5 01000100 00 FF06 FFFF 8100 FFFF FFFF 9000 FF
PUSH HL 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
800A:0605 01000100 00 FF06 FFFF 8100 FFFF FFFF 8FFE FF
LD B,05H 11111111 FF FFFF FFFF FFFF
MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
800C:CD1A80 01000100 00 0506 FFFF 8100 FFFF FFFF 8FFE FF
CALL 801AH 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
801A:77 01000100 00 0506 FFFF 8100 FFFF FFFF 8FFC FF
LD (HL), A 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
801B:23 01000100 00 0506 FFFF 8100 FFFF FFFF 8FFC FF
INC HL 11111111 FF FFFF FFFF FFFF
60
MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
801C:3C 01000100 00 0506 FFFF 8101 FFFF FFFF 8FFC FF
INC A 11111111 FF FFFF FFFF FFFF

MTS-Z80A > ↵
PC SZ-H-VNC A BC DE HL IX IY SP I
801D:C9 00000000 01 0506 FFFF 8101 FFFF FFFF 8FFC FF
INC A 11111111 FF FFFF FFFF FFFF

MTS-Z80A > : For DJNZ 800CH, DJNZ FBH is originally the right expression.
However in order easily to trace it is disassembled.
PC SZ-H-VNC A BC DE HL IX IY SP I
800F:10FB 00000000 01 0506 FFFF 8101 FFFF FFFF 8FFE FF
DJNZ 800CH 11111111 FF FFFF FFFF FFFF

MTS-Z80A > S↵ : After that, STEP function executes by only pressing ENTER
: In TRACE instruction, the fact that CALL instruction also executes
one step
: Let's execute STEP function and see the difference.
PC SZ-H-VNC A BC DE HL IX IY SP I
800C:CDIA80 00000000 01 0406 FFFF 8101 FFFF FFFF 8FFE FF
CALL 801AH 11111111 FF FFFF FFFF FFFF

MTS-Z80A > (
PC SZ-H-VNC A BC DE HL IX IY SP I
800F:10FB 00000000 02 0406 FFFF 8102 FFFF FFFF 8FFE FF
INC A 11111111 FF FFFF FFFF FFFF

MTS-Z80A > (
PC SZ-H-VNC A BC DE HL IX IY SP I
800C:CDIA80 00000000 02 0306 FFFF 8102 FFFF FFFF 8FFE FF
CALL 801AH 11111111 FF FFFF FFFF FFFF

MTS-Z80A > (
PC SZ-H-VNC A BC DE HL IX IY SP I
800F:10FB 00000000 03 0306 FFFF 8103 FFFF FFFF 8FFE FF
DJNZ 800CH 11111111 FF FFFF FFFF FFFF

61
MTS-Z80A > (
PC SZ-H-VNC A BC DE HL IX IY SP I
800C: CDIA80 00000000 03 0206 FFFF 8103 FFFF FFFF 8FFE FF
CALL 801AH 11111111 FF FFFF FFFF FFFF

MTS-Z80A >

④ Check and Modify Register

This function is checking and modifying the current register. Nothing 8 bit register
itself can not modify, but pair registers(AF, BG, DE, HL, AF', BC' DE',HL') and 16-bit
register(IX, IY, SP, PC) are modified at the same time. For input of instructions you can
check the status of the register. If you inputs the name of the register like 'RBC', it can
be easily modified.

Then for the name of the register, you just need the first character except IX, IY, I.

MTS-Z80A > R(
PC SZ-H-VNC A BC DE HL IX IY SP I
8000: 310090 11111111 FF FFFF FFFF FFFF FFFF FFFF FF00
FF
LD SP,9000H 11111111 FF FFFF FFFF FFFF

MTS-Z80A > RBC(

BC:FFFF -> 1234(
PC SZ-H-VNC A BC DE HL IX IY SP I
8000: 310090 11111111 FF 1234 FFFF FFFF FFFF FFFF FF00
FF
LD SP,9000H 11111111 FF FFFF FFFF FFFF

⑤ FILL, MOVE and DUMP

DUMP outputs the data of the Memory(ROM, RAM) to the Monitor of PC. The
instruction format is 'D Start Address, End Address', but Start Address and End
Address can be omitted. If both Start address and End address is omitted, after
RESET or downloading, it dumps from 8000H. Dump instruction is also inputted once.
After that, press ENTER and execute the instruction line by incrementing the address.

62
MTS-Z80A> D(
8000:31 00 90 AF 0E 06 21 00 - 81 E5 06 05 CD 1A 80 10 1.....!.........
8010: FB CD IA 80 0D C2 0A 80 – D1 CF 77 23 3C C9 FF FF ..........W#<...
8020: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8030: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8040: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8050: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8060: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8070: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................

8080: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8090: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80A0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80B0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80C0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80D0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80E0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80F0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................

MTS-Z80A> D8000, 800F(

8000: 31 00 90 AF 0E 06 21 00 - 81 E5 06 05 CD 1A 80 10 1.....!.........

MTS-Z80A> (
8010: FB CD 1A 80 0D C2 0A 80 - Dl CF 77 23 3C C9 FF FF ..........W#<...
8020: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8030: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8040: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8050: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8060: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8070: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8080: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8090: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF................
80A0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80B0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80C0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80D0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80E0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
80E0: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8100: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................

63
MOVE outputs the data of the Memory(ROM, RAM) to the other, area(RAM). The instruction
format is 'M Start Address, End Address, Restart Address', but any address of them can be
omitted. Let's copy the data of 8000H-801FH to the address from 8030H to 804F and dump
from 8000H to 805FH to check

MTS-Z80A> M8000,801F,8030↵
MTS-Z80A> D8000,805F↵
8000: 31 00 90 AF 0E 06 21 00 - 81 E5 06 05 CD IA 80 10 1.....!.........
8010: FB CD 14 80 0D C2 0A 80 – D1 CF 77 23 3C C9 FF FF ......... W#<...
8020: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................
8030: 31 00 90 AF 0E 06 21 00 - 81 E5 06 05 CD 1A 80 10 1.....!.........
8040: FB CD 1A 80 0D C2 0A 80 – D1 CF 77 23 3C C9 FF FF ......... W#<...
8050: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF................

MTS-Z80A>

FILL function fills the Memory(ROM or RAM) with the data you want. The instruction format 'F
Start Address, End Address, Data' Let's fill 8000H - 801FH with 44H and dump it to check.

MTS-Z80A> F8000,801F,44↵
MTS-Z80A> D8000,802F↵
8000: 44 44 44 44 44 44 44 44 - 44 44 44 44 44 44 44 44 DDDDDDDDDDDDDDDD
8010: 44 44 44 44 44 44 44 44 - 44 44 44 44 44 44 44 44 DDDDDDDDDDDDDDDD
8020: FF FF FF FF FF FF FF FF - FF FF FF FF FF FF FF FF ................

MTS-Z80A>
⑥ EDIT
EDIT is used for modifying the data of the Memory(RAM). To modifying the data, Insert'.'. To
go to one address backward, insert When just press ENTER, the address increments without
and change of data. The instruction format is 'E Start Address'. If the address is omitted the
default is 8000H.

MTS-Z80A> E↵
8000: 44 -> 11↵
8001: 44 -> 22↵
8002: 44 -> 33↵
8003: 44 -> 55↵
8004: 44 -> ＼↵ : the address increments
8003: 55 -> 44↵
8004: 44 -> 55↵
8005: 44 -> .↵ : finish modifying the data
64
 MTS-Z80A>

⑦ Disassembler
Disassembler shows the mnemonics of the machine codes that transmitted to PC or inputted
from the keypad. We are used to using STEP and TRACE, so you knows convenience. The
other way, MTS-Z80A has the function that converts the machine codes of the Memory(ROM,
RAM) on the PC into the mnemonics. If the instruction format 'U line' or the number of lines are
omitted, it shows the mnemonics of 20 lines.

MTS- Z80A> U↵
8000: 310090 LD SP,9000H
8003: AF XOR A
8004: 0E06 LD C,06H
8006: 210081 LD HL,8100H
8009: E5 PUSH HL
800A: 0605 LD B,05H
800C: CD1A80 CALL 801AH
800F: 10FB DJNZ 800CH
8011: CD1A80 CALL 801AH
8014: 0D DEC C
8015: C20A80 JP NZ,800AH
8018: Dl POP DE
8019: CF RST 08H
801A: 77 LD (HL), A
801B: 23 INC HL
801C: 3C INC A
801D: C9 RET
801E: FF RST 38H
801F: FF RST 38H
8020: FF RST 38H

65
Chapter 12. Externally Conneted Circuits

1. LED Output I according to the switch input (74LS244, 74LS373)

(a) Source file name : 80SWITCH.ASM
(b) Hexa file name : 80SWITCH.HEX
(c) Address : 5000H
(d) Action : 8 bit LEDs is flickering according to the switch input.

① 74LS244
A TTL IC, 74LS244 When the control signal 1G and 2G is 'High', output Y is high
impedance(electrically there is no connection, namely no high and not low). When 1G and 2G
are 'Low', the output Y is the same as A. When it's connected to the external, it is used for the
input ports lot as well as the selector of micro-processors. For the pin configuration the IC,
refer to the sheets.
② 74LS373
74LS373 has the latch function, so for the external connection it is used a lot for the
output ports as well as the address latch of micro-processors. When the output control(OC) of
74LS373 is 'H', the output becomes the high impedance. This output is prior to Enable(G).
When the Enable becomes 'H', the data will be lost. When the Enable is 'L', the data are hold.

0050 LED EQU 50H ; the I/O address of 8-bit LED

0058 SWITCH EQU 58H ; the I/O address of 8-bit switch
0048 LCDCLR EQU 0048H ; refer to the system call
0060 STRINGL EQU 0060H ; refer to the system call
0058 LINE2 EQU 0058H ; refer to the system call

8000 ORG 8000H ; set the starting address of the program

8000 CD4800 START: CALL LCDCLR ; clear LCD

8003 CD6000 CALL STRINGL ; output the strings on the LCD
8006 38424954 DB '8BIT SWITCH TEST $'
8018 CD5800 CALL LINE2 ; move down the cursor on the LCD
801B CD6000 CALL STRINGL ; output the strings on the LCD
801E 20202020 DB ' K&H MFG. $'
; The real program is the next 3 lines.
; When you want to execute single step,
; change the program counter to 802DH
802D DB58 MAIN: IN A,(SWITCH) ; read the status of the switch
802F D350 OUT (LED),A ; output on the LCD
8031 C32D80 JP MAIN ; jump to MAIN

0000 END
66
2. LED Output Ⅱ according to the switch input (74LS244, 74LS373)
(a) Source file name : 80SW1.ASM
(b) Hexa file name : 80SW1.HEX
(c) Address : 5150H
(d) Action : If more than one of 8-bit switches are pressed, all the 8-bit
LEDs flicker, otherwise all the 8-blt LEDs are lights -out.

0050 LED EQU 50H

0058 SWITCH EQU 58H

8000 ORG 8000H

8000 DB58 MAIN: IN A,(SWITCH) ;read the status of the switch

8002 2F CPL ;inverse the data(if the switch is
;pushed,'Low' signal is inputted.
;Therefore inverse the data for
;convenience
8003 FE00 CP 0 ;Is it '0'? (is there any switch
;pushed? )
8005 2803 JR Z,J1 ;Jump to J1 if there's no switch
;pushed.
8007 4F XOR A ;set all the lighting patterns
8008 1802 JR J2 ;jump to J2

800A 3EFF J1: LD A,0FFH ;reset all the lighting patterns

802D D350 J2: OUT (LED),A ;output the data
800E 18F0 JR MAIN ;jump to MAIN

0000 END

67
3. LED Flickering 1 (74LS373)
(a) Source file name : 80LIGHT1.ASM
(b) Hexa file name : 80LIGHT1.HEX
(c) Address : 5160H
(d) Action : 8-bit LEDs flicker( the Left 4 bits and Right 4bits flicker
alternatively)

0050 LED EQU 50H

8000 ORG 8000H

8000 3E0F LD A,0FH ;set the initial 1ighting pattern

8002 D350 MAIN: OUT (LED),A ;output the data
8004 CD0B80 CALL TIMER ;delay the time
8007 2F CPL ;inverse the data
8008 C30280 JP MAIN ;jump to MAIN

800B 16D0 TIMER: LD D,0D0H ;set time constant

800D 1EFF J1: LD E,0FFH ;set time constant
800F 1D J2: DEC E ;subtract 1 from E
8010 20FD JR NZ,J2 ;jump to J2 if not zero
8012 15 DEC D ;subtract 1 from D
8013 20F8 JR NA,J1 ;Jump to J1 if not zero

0000 END

4. LED Flickering 2 (74LS373)

(a) Source file name : 80LIGHT2.ASM
(b) Hexa file name : 80LIGHT2.HEX
(c) Address : 5170H
(d) Action : 8-bit LEDs flicker(output with increment of the data)

0050 LED EQU 50H

8000 ORG 8000H

8000 AF XOR A ;clear A register

8001 F5 MAIN: PUSH AF ;store AF register in
8002 2F CPL ;inverse the data
8003 D350 OUT (LED),A ;output the data
8005 F1 POP AF ;retrieve AF register from the stack
68
8006 CD0D80 CALL TIMER ;delay the time
8009 3C INC A ;increase the data by 1
800A C30180 JP MAIN ;jump to MAIN

800D 16D0 TMER: LD D,0D0H ;delay the time

800F 1EFF J1: LD E,0FFH
8011 1D J2: DEC E
8012 20FD JR NZ,J2
8014 15 DEC D
8015 20F8 JR NZ,J1
8017 C9 RET

0000 END

5, LED Flickering 3 (74LS373)

(a) Source file name : 80LIGHTS3.ASM
(b) Hexa file name : 80LIGHTS3.HEX
(c) Address : 51A0H
(d) Action : two 8-bit LEDs move left or right

0050 LED EQU 50H

8000 ORG 8000H

8000 3100FF LD SP,0FF00H

8003 3EFC START: LD A,0FCH ;set the lighting pattern (only the
;left 2 lights are on)
8004 D350 J1: OUT (LED),A ;output the data
8007 07 RLCA
8008 CB7F BIT 7,A ;if the MSB is zero
800A CA1380 JP Z,J2 ;jump to J2
800D CD2180 CALL TIMER
8010 C30580 JP J1
8013 D350 J2: OUT (LED),A
8015 0F RRCA
8016 CB47 BIT 0,A ;if the LSB is zero
8018 CA0580 JP Z,J1 ;jump to J1
8013 CD2180 CALL TIMER
801E C31380 JP J2
69
8021 1640 TIMER: LD D,40H
8023 1EFF TIME1: LD E,0FFH
8025 1D TIME2: DEC E
8026 C22580 JP NZ,TIME2
8029 15 DEC D
802A C22380 JP NZ,TIME1
802D C9 RET

0000 END

6. LED Flickering 4 (74LS373)

(a) Source file name : 80LIGHT4.ASM
(b) Hexa file name : 80LIGHT4.HEX
(c) Address : 5010H
(d) Action : 8-bit LEDs flicker (repeat the three actions as above
mentioned)

0050 LED EQU 50H

0048 LCDCLR EQU 0048H ;refer to the system call
0060 STRINGL EQU 0060H ;refer to the system call
0058 LINE2 EQU 0058H ;refer to the system call

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 38204249 DB '8 BIT LED TEST!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 20202020 DB ' K&H MFG.$'

802B 0606 MAIN: LD B,6 ;set the numbers of output

802D 3E0F LD A,0FH ;set the data of the initial lighting
802F CD5980 J1: CALL OUTPUT ;delay the output and time
8032 2F CPL ;inverse the data
8033 10FA DJNZ J1 ;subtract 1 from B register and jump to J1
;if not zero
8035 CD6180 CALL CLEAR
8038 0608 LD B,8H ;set the numbers of output
803A 3E01 LD A,1H ;set the data of the initial lighting
70
803C CD5980 J2: CALL OUTPUT ;delay the output and time
803F CB07 RLC A ;shift left
8041 10F9 DJNZ J2 ;subtract 1 from B register, jump to J2 if
;not zero
8043 CD6180 CALL CLEAR

8046 0608 LD B,8H ;set the numbers of output

8048 3E01 LD A,1H ;set the data of the initial lighting
804A CD5980 J3: CALL OUTPUT ;delay the output and time
804D CB07 RLC A ;shift left
804F C601 ADD A,1 ;add 1(to make the LSB on)
8051 10F7 DJNZ J3 ;subtract 1 from B register, jump to J3 if
;not zero
8053 CD6180 CALL CLEAR
8056 C32B80 JP MAIN ;jump to MAIN
8059 2F 0UTPUT: CPL ;inverse the signal ( the LED is lit in the
;state 'LOW')
805A D350 OUT (LED),A ;output the data
805C CD6680 CALL TIMER ;delay the time

805F 2F CPL ;inverse the signal

8060 C9 RET ;return to the Main routine
8061 AF CLEAR: XOR A ;the same as 'LD A,0'
8062 CD5980 CALL OUTPUT ;delay the output and time
8065 C9 RET ;return to the Main routine

8066 F5 TIMER: PUSH AF ;store AF register in the stack

8067 21FFCF LD HL,0CFFH ;set time constant
806A 2B T1: DEC HL ;subtract 1 from HL register
806B 7C LD A,H ;copy H into A
806C B5 OR L ;OR operation of A and L
806D C26A80 JP NZ,T1 ;jump to T1 if not zero (if the 16-bit
;register decrement, the zero flag will not
;change)
8070 F1 POP AF ;retrieve AF register from the stack
8071 C9 RET ;return to the Main routine

0000 END

71
7. FND Control (74LS373)
a) Source file name : 80FND.ASM
b) Hexa file name : 80FND,HEX
c) Address : 5020H
d) Action : outputs hexadecimal in sequence on the FND

0060 FND EQU 60H

0048 LCDCLR EQU 0048H
0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 20202046 DB ' FND TEST!$'
8014 CD5800 CALL LINE2
8017 CD6000 CALL STRINGL
801A 20202020 DB ' K&H MFG.$'

8029 0610 MAIN: LD B,16 ;set the number of the output

802B 214680 LD HL,TABLE ;set the starting address of the
;data to HL register
802E 7E J1: LD A,(HL) ;transmit the data of the address
;pointed by HL to A
802F D360 OUT (FND),A ;output the data
8031 CD3A80 CALL TIMER ;delay the time
8034 23 INC HL ;increment the address by 1
8035 10F7 DJNZ J1 ;jump to J1 if all the output did not
;output
8037 C32980 JP MAIN

803A E5 TIMER: PUSH HL

803B 21FFDF LD HL,0DFFFH
803E 2B T1: DEC HL
803F 7C LD A,H
8040 B5 OR L
8041 C23E80 JP NZ,T1
8044 E1 POP HL
8045 C9 RET

72
 ;each segments are lit in the LOW state.
8046 ; Dgfedcba
8046 C0 TABLE: DB 11000000B ;0
8047 F9 DB 11111001B ;1
8048 A4 DB 10100100B ;2
8049 B0 DB 10110000B ;3
804A 99 DB 10011001B ;4
804B 92 DB 10010010B ;5
804C 82 DB 10000010B ;6
804D D8 DB 11011000B ;7
804E 80 DB 10000000B ;8
804F 90 DB 10010000B ;9
8050 88 DB 10001000B ;A
8051 83 DB 10000011B ;B
8052 C6 DB 11000110b ;C
8053 A1 DB 10100001B ;D
8054 86 DB 10000110B ;E
8055 8E DB 10001110B ;F

0000 END

8. FND output according to the switch input (74LS244,74LS373)

(a) Source file name : 80SWFND.ASM
(b) Hexa file name : 80SWFND.HEX
(c) Address : 5030H
(d) Action : according to the switch input, outputs any of from 0 to 7 on
the FND

0058 SWITCH EQU 58H

0060 FND EQU 60H
0048 LCDCLR EQU 0048H
0060 STRINGL EQU 0060H
0058 LlNE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR
8003 CD6000 CALL STRINGL
8006 20202046 DB ' FND TEST !$'
8014 CD5800 CALL LINE2
8017 CD6000 CALL STRINGL
801A 496E7075 DB 'Input =8 bit S/W$'
73
802B DB58 MAIN: IN A,(SWITCH) ;read the switch
802D FEFF CP A,0FFH ;is there any key pushed?
802F CA2B80 JP Z,MAIN ;jump to MAIN if not
8032 2F CPL ;inverse the signal
8033 1600 LD D,0 ;clear D to do operation for the
;location of data
8035 0600 LD B,0 ;clear D to do operation checks
;the selected bit
8037 CB47 J1: BIT 0,A ;is that switch pushed?
8039 C24180 JP NZ,CHK_NO ;jump to CHK_NO if pushed
803C 0F RRCA ;shift the data
803D 04 INC B
8041 214C80 CHK_NO: LD HL,TABLE ;set the starting address HL
;register
8044 58 LD E,B ;transmit the count value to E
8045 19 ADD HL,DE ;get the data address adding the
;table address to A the count
;value
8046 7E LD A,(HL) ;transmit the data of the address
;pointed by HL to A
8047 D360 OUT (FND),A ;output the data on the FND
8049 C32B80 JP MAIN

804C ; Dgfedcba
804C C0 TABLE: DB 11000000B ;0
804D F9 DB 11111001B ;1
804E A4 DB 10100100B ;2
804F B0 DB 10110000B ;3
8050 99 DB 10011001B ;4
8051 92 DB 10010010B ;5
8052 82 DB 10000010B ;6
8053 D8 DB 11011000B ;7

0000 END

74
Chapter 13. 8255

1. DOT MATRIX LED 1 (8255)

(a) Source file name : 80DOT1.ASM

(b) Hexa file name : 80DOT1.HEX
(c) Address : 5050H
(d) Action : Display HL in three colors on the DOT MATRIX LED

① What is 8255?
Most microprocessors use particular components to easily perform connection to the
external. The Intel 8255(PPI. Programmable Peripheral Interface) is a general purpose I/O
component designed for use with various type of microprocessors. 8255 has 24 I/O pins which
are classified A, B and C ports in sets of 8 bits. A and B ports can be individually programmed
in sets of 8 bit to be input and output. C port consists of the 4 bits MSB and 4-bits LSB and is
used in sets of 4 to be input output. Its main feature is that of a general purpose programmable
device with three ports with 8-bit input/output.

1) 40 pins, DIP type, 5V applied voltage

2) Completely TTL Compatible
3) 24 Programmable 1/O Pins
4) latch/buffer for using as the output port
5) The 8255 can be programmed in 2 groups of 12 or used in 3 major modes of
operation
ⓐ mode 0 : Basic Input/output.
ⓑ mode 1 : Strobed Input/Output
ⓒ mode 2 : Bi-Directional Bus

② 8255's control word

In order to set the control word of 8255 set A1 and A0 pins to'1'. For mode selection, set
the 7th bit of the control word to'1'. For example, to use A port as the input and B, C ports as
the output, write '90H'.

75
D7 D6 D5 D4 D3 D2 D1 D0

GROUP B
Port C 0 Output
(Lower) 1 Input
0 Output
PORT B
1 Input
Mode 0 Mode 0
Selection 1 Mode 1

GROUB A
Port C 0 Output
(Upper) 1 Input
0 Output
Port A
1 Input
00 Mode 0
Mode
01 Mode 1
Selection
1x Mode 2

Mode set flag

1 = Active

D7 D3 D2 D1 D0
O Reset
Bit Set/Reset
1 Set

Port C Bit selection

Bit 0 1 2 3 4 5 6 7

D1 0 1 0 1 0 1 0 1

D2 0 0 1 1 0 0 1 1

D3 0 0 0 0 1 1 1 1

Bit Set/Reset Flag

0 = Active

76
③ How to light a DOT MATRIX LED
The LEDs as display are required to have more than 256Dots(16 × 16 Dot per a
character to express Korean or Chinese. If only onto character controlled by the static method,
it Is virtually impossible to configure control the hardware.
Dot Matrix LED is the LED component which is connected to the joining point of a row and
column line. In general, a Dot Matrix LED is lit in the Dynamic lighting method. The dynamic
method is a little bit complicated but it is the very convenient way to control lots of LEDs.

④ Font Configuration of a Dot Matrix LED

1) In the following table, LED on-state is'1'and LED off-state is'0'. Then calculate them Into
hexadecimal. For the output of the data to A port, it is displayed in green color. For B port, it is
displayed in red color. Moreover, when the same data are transmitted to both A and B ports, it
is displayed in orange color.

No. DATA FONT

01 CCH ● ● ● ●
02 CCH ● ● ● ●
03 CCH ● ● ● ●
04 FCH ● ● ● ● ● ●
05 FCH ● ● ● ● ● ●
06 CCH ● ● ● ●
07 CFH ● ● ● ● ● ●
08 CFH ● ● ● ● ● ●

77
 2) Practising FONT Construction on the character generator
Using the following table, construct characters and pictures. Then use that programming
practice.

<Table 1> <Table 2>

No. DATA FONT No. DATA FONT
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08

<Table 3> <Table 4>

No. DATA FONT No. DATA FONT
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08

78
⑤ Program
0028 APORTD EQU 28H
0029 BPORTD EQU APORTD+ 1
002A CPORTD EQU BPORTD+1
002B CNTD EQU CPORTD+1

0048 LCDCLR EQU 0048H

0058 LINE2 EQU 0058H
0060 STRINGL EQU 0060H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 436F6C6F DB 'Color Dot Matrix$ '
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 20202020 DB ' K&H MFG. $'

802D 3E80 LD A,80H ;define the control word of the

;8255(the output of the previous
;port
802F D32B OUT (CNTD),A ;output to the 8255
8031 0662 J1: LD B,98 ;set the numbers of the output
8033 0E28 J2: LD C, APORTD ;set the output port(GREEN)
8035 CD5D80 CALL DISP ;display the character
8038 10F9 DJNZ J2 ;jump to J2 if 98 outputs has not
;been done
803A CD8380 CALL DELAY ;delay the time (all the LEDs are
;off)
803D 0DE29 J3: LD C,BPORTD ;set the output port(RED)
803F 0662 LD B,98 ;set the number of output

8041 CD5D80 J4: CALL DISP ;display the character

8044 10FB DJNZ J4 ;Jump to J2 if 98 outputs has not
;been done
8046 CD8380 CALL DELAY ;delay the time (all the LEDs are
;off)
;display the mixed orange color by flickering green and red color
;alternative1y

79
8049 062D J5: LD B,45 ;set the number of the output
804B 0E28 J6: LD D,APORTD ;set the output port(GREEN)
804D CD5D80 CALL DISP ;display the character
8050 0E29 LD C,BPORTD ;set the output port(RED)
8052 CD5D80 CALL DISP ;display the character
8055 10F4 DJNZ J6 ;jump to J6 if 45 outputs has not
;been done
8057 CD8380 CALL DELAY ;delay the time (all the LEDs are
;off)
805A C33180 JP J1 ;jump to J1

; display routine for the first time

805D C5 DISP: PUSH BC
805E 1601 LD D,1 ;set the initial scan line
8060 0608 LD B,8 ;set the number of the output
8062 DD218F80 LD IX,LET ;set the starting address of the
;data
8066 74 LOOP: LD A,D ;transmit the scan line data
8067 D32A OUT (CPORTD),A ;select the line to light
8069 DD7E00 LD A,(IX) ;transmit the lighting data to A
806C ED79 OUT (C),A ;output the port C points to
806E DD23 INC IX ;increment the indexed address of
;the data by 1
8070 CD7C80 CALL TIMER ;delay the time(while LEDs on)
8073 CB02 RLC D ;change the scan data to the next
;line
8075 AF XOR A ;set the light data (all of them off)
8076 ED79 OUT (C),A ;output the port C points to
8078 10EC DJNZ LOOP ;jump to LOOP if all of 8 lines are
;not displayed
807A C1 POP BC
807B C9 RET

807C C5 TIMER: PUSH BC

807D 0600 LD B,00
807F 10FE DJNZ $
8081 C1 POP BC
8082 C9 RET

8083 C5 DELAY: PUSH BC

8084 0100A0 LD BC,0A000H
80
8087 0B DEC BC
8088 78 LD A,B
8089 B1 OR C
808A C28780 JP NZ,DEL1
808D C1 POP BC
808E C9 RET

808F CCCCCCFC DB 0CCH, 0CCH, 0CCH, 0FCH

8093 FCCCCFCF DB 0FCH, 0CCH, 0CFH, 0CFH

0000 END

2. DOT MATRIX LED 2 (8255)

(a) Source file name : 80DOT2.ASM
(b) Hexa file name : 80DOT2.HEX
(c) Address : 5060H
(d) Action : Display the moving of a simple figure on the Dot Matrix LED

0028 APORTD EQU 28H

0029 BPORTD EQU APORTD+1
002A CPORTD EQU BPORTD+1
002B CNTD EQU CPORTD+1

0048 LDCCLR EQU 0048H

0058 LINE2 EQU 0058H
0060 STRINGL EQU 0060H

8200 LET1 EQU 8200H ;GREEN color displaying area

8208 LET2 EQU LET1+8
8210 LET3 EQU LET2+8 ;RED displaying area

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR
8003 CD6000 CALL STRINGL
8006 436F6C6F DB 'Color Dot Matrix$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 20202020 DB ' K&H MFG. $'

81
802D 3E80 LD A,80H
802F D32B OUT (CNTD) ,A

8031 21FFFF MAlN: LD HL,0FFFFH ;clear the data area for display
8034 FD210082 LD IY,LET1 ;clear the area for GREEN
8038 CDB480 CALL CLEAR
803B FD2l1082 LD IY,LET3 ;clear the area for RED
803F CDB480 CALL CLEAR
8042 DD210B81 LD IY,DATA2 ;set the starting address of the
;data
8046 FD210882 LD IY,LET2 ;the data area for GREEN
804A CDBF80 CALL MOVE ;data transfer routine
804D DD210381 LD IX,DATA1 ;set the starting address
8051 FD211082 LD IY,LET3 ;transmit the data for RED
8055 CDBF80 CALL MOVE ;data transfer routine

8058 0E08 LD C,8 ;the number of shift

805A 061E J3: LD B,30 ;the number of display
805C CDCE80 J4: CALL DISP ;display routine
805F 10FB DJNZ J4 ;jump to J4 if 30 outputs has not
;been done
8061 CD4180 CALL SHIFT ;shift routine
8064 0D DEC C ;shift has been done?
8065 C25A80 JP NZ,J3 ;jump to J3 if not
8068 0E02 LD C,2 ;the number of repeat
806A 21FFFF J5: LD HL,0FFFFH ;turn on Both RED and GREEN
806D 0640 LD B,40H
806F CDCE80 J6: CALL DISP
8072 10FB DJNZ J6

8074 21FF00 LD HL,00FFH ;turn on only RED light

8077 0640 LD B,40H
8079 CDCE80 J7: CALL DISP
807C 10FB DJNZ J7

807E 2100FF LD HL,0FF00H ;turn on only GREEN light

8081 0640 LD B,40H
8083 CDCE80 J8: CALL DISP
8086 10FB DJNZ J8
8088 0D DEC C ;decrease the number of repeat
;by 1
82
8089 C26A80 JP NZ,J5 ;jump to J5 if not zero

808C 0E08 LD C,8 ;the number of shift

808E 2EFF LD L,0FFH ;turn on all the lights (H is FFH)
8090 061E J9: LD B,30
8092 CDCE80 J10: CALL DISP
8095 10FB DJNZ J10
8097 CDA180 CALL SHIFT
809A 0D DEC C
809B C29080 JP NZ,J9
809E C33180 JP MAIN

80Al FD210082 SHIFT: LD IY,LET1 ;the start ins address

80A5 0608 LD B,8 ;the number of shift
807A FDCB0816
REP_SHIFT: RL (IY+8) ;because the real data for display
;is 'IY+7', shift left the buffer
;memory data. Then the MSB is
;transmitted to the carry flag
80AB FDCB0016 RL (IY) ;shift the data left, the previous
;carry flag goes into the LSB

; display area buffer area

C ← RL (IY) ← C ← RL (IY+8) ← C
; ↑ ↑ ↑
;no meaning notice the moving the this carry flag no meaning

80AF FD23 INC IY ;increment the data pointing

;address
80B1 10F4 DJNZ REP_SHIFT ;jump to REP_SHIFT if it's not
;repeated 8 times
80B3 C9 RET ;data clear routine
80B4 AF CLEAR: XOR A
80B5 0608 LD B,8
80B7 FD7700 JC1: LD (IY),A
80BA FD23 INC IY
80BC 10F9 DJNZ JC1
80BE C9 RET ;data transfer routine
80BF 0608 MOVE: LD B,8
80C1 DD7E00 JM1: LD A,(IX)
80C4 FD7700 LD (IX),A
83
80C7 DD23 INC IX
80C9 FD23 INC IY
80CB 10F4 DJNZ JM1
80CD C9 RET ;display routine
80CE C5 DISP: PUSH BC
80CF 1601 LD D,1 ;SCAN LINE
80D1 0608 LD B,8 ;the number of the output lines
80D3 DD210082 LD IX,LET1 ;GREEN
80D7 FD211082 LD IY,LET3 ;RED

80DB 7A LOOP: LD A,D

80DC D32A OUT (CPORTD),A
80DE DD7E00 LD A,(IX)
80E1 A4 AND H ;decide if it outputs or not (no
;GREEN light if 'L' is 00H)
80E2 D328 OUT (APORTD),A
80E4 FD7E00 LD A,(IY)
80E7 A5 AND L ;decide if it outputs or not (no
;RED light if 'L' is 00H)
80E8 D329 OUT (BPORTD),A
80EA DD23 INC IX
80EC FD23 INC IY
80EE CDFC80 CALL TIMER
80F1 CB02 RLC D
80F3 AF XOR A ;display clear
80F4 D328 OUT (APORTD),A
80F6 D329 OUT (BPORTD),A
80FB 10E1 DJNZ LOOP
80FA C1 POP BC
80FB C9 RET

80FC C5 TIMER: PUSH BC

80FD 0600 LD B,00H
80FF 10FE DJNZ $
8101 C1 POP BC
8102 C9 RET

8103 183C66DB DATA1: DB 18H, 3CH, 66H, 0DBH

8107 DB663C18 DB 0DBH, 66H, 3CH, 18H

84
810B 007E7E7E DATA2: DB 00H, 7EH, 7EH, 7EH
810F 7E7E7E00 DB 7EH, 7EH, 7EH, 00H

0000 END

85
Chapter 14. 8253

1. SOUND - TEST 1
(a) Source file name : 80CTC.ASM
(b) Hexa file name : 80CTC.HEX
(c) Address : 5120H
(d) Action : Play the sound generated by the division of the clock at
2.4576MHz which is input to COUNT0 of the IC 8253

① Characteristics of the 8253

The timer plays a very important role in controlling the real-time hardware. For example,
without a timer it is very difficult to repeat the constant time in period. Some characteristics of
the 8253 is summarized as follows.
1) 3 independent programmable counters
2) binary or decimal counting

② Functions of Input/Output pin

1) CLK0 ～ CLK2 : Input
They are the clock source input pin of each counter which counts the clock inputted
by this pin.
2) GATE0 ～ GATE2 Input
Although they are different according to a mode, they are used for the start and stop
of counters
3) OUT0 ～ OUT2 Output
Although they are different according to a mode, they output 'H' at that time general
counter register is a zero count

③ Mode controlling register

The 8253 has various mode it cannot be reset, so that it should be initialized before using.
The mode of each channel can be set by writing the mode control word for each channel. The
8253 has a special mode control command that can latch the current count value to the
register, so it read the right value without stop. Remember that a timer and counter down
counters.

④ Counter/Timer Mode
1) Mode 0 Count Complete interrupt
ⓐ Start counting after loading the count value
ⓑ If the counter becomes zero. the OUT pin becomes 'H'. Then if is an interrupt, the
interrupt is requested.
ⓒ Maintain the OUT pin until selecting a Mode and setting the count value.
86
2) Mode 1 : Programmable One Shot
ⓐ Use a GATE pin as trigger function
ⓑ If the GATE pin(Trigger) becomes 'H', the counter starts action
ⓒ OUT pin becomes 'L'. If the counter is zero, it becomes 'H'
ⓓ This mode is so retriggerble that if a trigger signal is inputted to Gate pin, the count
value is reloaded.

3) Mode 2 Rate Generator

ⓐ Act as an N-nary counter
ⓑ According to the value of a counter, if N clocks is inputted, 'L' pulse is outputed to
the OUT pin within 1 clock period.
ⓒ To load a new count value while counting, start loading after current counting
completes.
ⓓ A GATE pin has reset function. If a Gate pin is 'L', a OUT pin become 'H'. Then in
the rising edge of the GATE pin the count reload to start counting.
ⓔ A OUT pin Stays 'H' until loading a count value after definition of a Mode.

4) Mode 3 : Square Wave Rate Generator

ⓐ the same as Mode 2
ⓑ Generate in 1/2 of the count value square wave
ⓒ If the set value is odd, there will be the square wave with one clock bigger of 'H'
ⓓ Although the count value is zero, it keep acting forever by the automatic loading.
ⓔ Like Mode 2, a Gate pin has the reset function

5) Mode 4 : Software Triggered Strobe

ⓐ After Mode selection, a OUT pin is 'H'.
ⓑ After loading the count value, it starts counting.
ⓒ If the count value is zero, a OUT pin is 'L' during the time of 1 Clock.
ⓓ Like Mode 2, a Gate pin has the reset function

6) Mode 5 : Hardware Triggered Strobe

ⓐ After Mode selection, a OUT pin is 'H'
ⓑ A Gate pin starts counting in the rising edge.
ⓒ If the count value is zero, a OUT pin is 'L' during the time of 1 clock.
ⓓ Like Mode 1, This mode is so retriggerble that if a trigger signal is inputted to the
Gate pin, the count value is reloaded.

87
 D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD
Binary BCD Counter
1 BCD
0 Binary

Mode Selection
Mode
M2 M1 M0 Mode
No.
Interrupt enable if the
0 0 0 0
counter is ‘0’
0 0 1 Programmable One Shot 1
0 1 0 Rate Generator 2
Square Wave Rate
0 1 1 3
Generator
1 0 0 Software Triggered Strobe 4
1 0 1 Hardware Triggered Strobe 5

Counter Control
RL1 RL0 Function
0 0 Counter Latch
0 1 Read/Load only LSB
1 0 Read/Load only MSB
1 1 Read/Load LSB/MSB

Counter Selection
RL1 RL0 Counter
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Counter 3
◆ Mode Byte of the 8253

◆ To generate the sound, output the frequency that the sound has Divide frequency
(24576000Hz) applied to CTC(8253) by the reference frequency.

◆ For example, the division rate of degree is 9394 because 2457600÷261.6 = 9394.495413.
The decimal 9394 is converted into the hexadecimal 24B2H.
88
 The musical scale Do Re Mi Fa Sol Ra Si
Reference
261.6 293.7 329.6 349.2 392.0 440.0 493.2
Frequency(Hz)
period(ms) 3.82 3.40 3.03 2.86 2.55 2.27 2.03
Division ratio(decimal) 9394 8386 7456 7038 6269 5585 4983
Division
20B0 20B0 1D20 1B7E 1B7E 187D 1377
Ratio(hexadecimal)

⑤ Program
0048 COUNT0 EQU 48H
0049 COUNT1 EQU 49H
004A COUNT2 EQU 4AH
004B CSR EQU 4BH
0000 DO EQU 0
0002 RE EQU 2
0004 MI EQU 4
0006 FA EQU 6
0008 SOL EQU 8
000A RA EQU 0AH
000C SY EQU 0CH
000E DO1 EQU 0EH
0010 NO EQU 10H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 534F554E DB 'SOUND GENEHATOR!$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 20444950 DB ' DIP1 = NO 2 ON$'

802D 3E36 I8253: LD A,00110110B ;initialize COUNT0 of the 8253

802F D34B OUT (CSR),A
;stop generation the sound by outputting very small division ratio. (generate
;the sound beyond the audible frequency)

89
8031 3E0A LD A,10 ;the LSB of the division ratio
8033 D348 OUT (COUNT0).A ;output to the 8253
8035 AF XOR A ;the MSB of the division ratio
8036 D348 OUT (COUNT0),A ;output to the 8253
8038 CD7D80 CALL TIMER ;delay the time
;the first byte of the song data is
stored in order of musical scale,
tempo.
803B FD219B80 PLAY: LD IY,DATA2 ;the starting address of the song
;data
803F 1600 MAIN: LD D,0 ;clear D to operate
8041 DD218980 LD IX,DATA1 ;division ratio table
8045 FD7E00 LD A,(IY) ;transmit the scale data to A
8048 FEFF CP A,0FFH ;is that the end of the song?
804A CA3B80 JP Z,PLAY ;jump to PLAY if it is.

804D 5F LD E,A ;transmit the scale data to E

804E DDl9 ADD IX,DE ;get the address of division ratio
;correspond to the sound by
;adding the division ratio table to
;the scale data.
8050 DD7E00 LD A,(IX) ;the LSB of the division ratio
8053 D348 OUT (COUNT0),A ;output to 8253
8055 DD23 INC IX ;increment the address of the
;division ratio
8057 DD7E00 LD A,(IX) ;the LSB of the division ratio
805A D348 OUT (COUNT0),A ;output to 8253
805C FD23 INC IY ;increment the data pointing
;address pointing of the song
805E FD7E00 LD A,(IY) ;transmit the tempo data to 4

8061 CD7D80 J1: CALL TIMER ;delay the time of standard tempo
8064 3D DEC A ;decrement the tempo data
8065 C26180 JP NZ,J1 ;Jump to J1 if not zero
8068 3E0A LD A,10 ;stop generating the sound
806A D348 OUT (COUNT0),A
806C AF XOR A ;delay for very short time( to stop
the continuous sound)
806F 210001 LD HL,100H
8072 2B J2: DEC HL
8073 7C LD A,H
90
8074 B5 OR L
8075 C27280 JP NZ,J2
8078 FD23 INC IY
807A C33F80 JP MAIN

807D F5 TIMER: PUSH AF ;timer for the standard temp

807E 210030 LD HL,3000H
8081 2B T1: DEC HL
8082 7C LD A,L
8083 B5 OR L
8084 C28180 JP NZ,T1
8087 F1 POP AF
8088 C9 RET

8089 DATA1: ; DO, RE, Ml, FA

8089 B224B020 DW 24B2H, 20B0H, 1D20H, 1B7EH
8091 ; SOL, RA, SY, DO1, NO
8091 DW 187DH, 15DIH, 1377H, 1259H, 10H

809B 04020A02 DATA2: DB MI,2,RA,2,SOL,2,FA,2

80A2 04020602 DB MI,2,F,4,2,MI,2,NO,2
80AB 04020602 DB MI,2,FA,2,SOL,2,DOI ,2

2. SOUND - TEST 2 (SWITCH INPUT)

(a) Source file name : 80CTCl.ASM
(b) Hexa file name : 80CTCl.HEX
(c) Address : 5130H
(d) Action : Generate the sound by dividing the clock of 2.4576MHz
which is inputted to the COUNT0 of the 8253 corresponding
to 8-bit switch reading. Whenever the switch Is pushed once,
the sound continues. To stop the sound, push the NMI key.
0048 COUNT0 EQU 48H
0049 COUNT1 EQU 49H
004A COUNT2 EQU 4AH
004B CSR EQU 4BH
0058 SWITCH EQU 58H

FF00 NMI_BUF EQU 0FF00H

0048 LCDCLR EQU 0048H

91
0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 534F554E DB 'SOUND GENERATOR!$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 20444950 DB ' DIP1 = NO.2 ON$'
802D 3E36 I8253: LD A,00110110B ;initialize COUNT0 of the 8253
802F D34B OUT (CSR),A
8031 DD218780 LD IX, NOSOUND ;the starting address of NMI
;routine
8035 DD2201FF LD (NMI_BUF+1),IX ;if the address is stored in the NMl
;buffer, when the NMI occurs it
;jumps to the address
8039 0E00 LD C,0
803B 1600 LD D,0

803D DB58 MAIN: IN A,(SWITCH) ;input the status of 8-bit switch

803F B9 CP C ;is that the same as the previous
;key?
8040 DA3D80 JP Z,MAIN ;jump to MAIN if it is
8043 FEFF CP 0FFH ;is there any key pushed?
8045 4F LD C,A ;store the data in C if it is
8046 CA3D80 JP Z,MAIN ;otherwise, jump to MAIN find the
;bit number of the pushed key
8049 2F CPL
804A 0600 LD B,0
804C CB47 J1: BIT 0,A
804E C25680 JP NZ,CHK_NO
8051 0F RRCA
8052 04 INC B
8053 C34C80 JP J1

8056 DD2l9480 CHK_NO: LD IX,TABLE

805A 3E0A LD A,10 ;stop generating the sound
805C D348 OUT (COUNT0),A
805E AF XOR A
92
805F D348 OUT (COUNT0),A
8061 110005 LD DE,500H ;timer for stoping the continuos
;and repeat sound.
8064 1B J2: DEC DE
8065 7A LD A,D
8066 B3 OR E
8067 C26480 JP NZ,J2

806A 78 LD A,B
806B 87 ADD A,A ;double the data because the
;each division ratio consists of 2
;bytes
806C 5F LD E,A
806D DDl9 ADD IX,DE
806F DDTE00 LD A,(IX)
8072 D348 OUT (COUNT0),A
8074 DD23 ADD IX,DE
8076 DD7E00 LD A,(IX)
8079 D348 OUT (COUNT0),A ;timer for removing chattering
807B 110030 LD DE,3000H ;don't recognize although the
;switch is pushed faster than the
;timer, namely in the minimum
;time of generating the sound
807E 1B J3: DEC DE
807F 7A LD A,D
8080 B3 OR E
8081 C27E80 JP NZ,J3
8084 C33D80 JP MAIN

8087 3E0A NOSOUND: LD A,10

8089 D348 OUT (COUNT0),A
808B AF XOR A
808C D348 OUT (COUNT0),A

808E 213D80 LD HL,MAIN

8091 E3 EX (SP),HL ;exchange HL value and the
;address of the RETN instruction
;which is stored in the stack.
;Namely, it returns to MAIN
;without going to the location
;which NMI occurs
93
8092 ED45 RETN ;return to MAIN from the NMI
;routine

8094 59127713 TABLE: DW 1259H, 1377H, 15D1H, 187DH

809C 7E1B201D DW 1B7EH, 1D20H, 20B0H, 24B2H

0000 END

3. SOUND - TEST 3 (Keyboard Input of PC)

(a) Source file name : 80CTC2.ASM
(b) Hexa file name : 80CTC2.HEX
(c) Address : There's no address in the ROM, because this is for a PC
(d) Action : Generate the sound by dividing the clock of 2.4576MHz
which is inputted to the COUNT0 of the 8253 corresponding
to the Keyboard input on PC. On the Keyboard, if from 'z' to ','
are pushed, the sound in 1 octave is generated. push the
other keys to stop the sound.

0048 COUNT0 EQU 48H

0049 COUNTI EQU 49H
004A COUNT2 EQU 4AH
004B CSR EQU 4BH
0058 SWITCH EQU 58H

0048 LCDLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
0028 INRS EQU 0028H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 534F554E DB 'SOUND GENERATOR!$'

94
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 20444950 DB ' DIP1 = NO.2 ON$'

802D 3E36 I8253: LD A,00110110B

802F D34B OUT (CSR),A

8031 CD2800 PLAY: CALL INRS ;get 1 character as input on the

;keyboard
8034 CDC180 CALL NOSOUND ;stop generating the sound for the
;seconds
8037 FE5A PLAY1: CP 'Z' ;if the upper case 'Z'
8039 CA8580 JP Z,DO
803C FE7A CP 'z' ;or if the lower case 'z'
803E CA8580 JP Z,DO ;jump to DO

8041 FE58 CP 'X'

8043 CA8B80 JP Z,RE
8046 FE78 CP 'x'
8048 CA8B80 JP Z,RE

804B FE43 CP 'C'

804D CA9180 JP Z,MI
8050 FE63 CP 'c'
8052 CA9l80 JP Z,MI

8055 FE56 CP 'V'

8057 CA9780 JP Z,FA
805A FE76 CP 'v'
805C CA9780 JP Z,FA

805F FE42 CP 'B'

8061 CA9D80 JP Z,SOL
8064 FE62 CP 'b'
8066 CA9D80 JP Z,SOL

8069 FE4E CP 'N'

806B CAA380 JP Z,RA
806E FE6E CP 'n'
8070 CAA380 JP Z,RA

95
8073 FE4D CP 'M'
8075 CAA980 JP Z,SI
8078 FE6D CP 'm'
807A CAA980 JP Z,SI

807D FE2C CP ','

807F CAAF80 JP Z,SI
8082 C3B580 JP PAUSE ;stop she sound if there is no
;corresponding sound
8085 11B224 DO: LD DE,24B2H
8088 C3B880 JP SET8253
808B 11B020 RE: LD DE,20B0H
808E C3B880 JP SET8253
8091 l1201D MI: LD DE,1D20H
8094 C3B880 JP SET8253
8097 117E1B FA: LD DE,1B7EH
809A C3B880 JP SET8253
809D 117D18 SOL: LD DE,187DH
80A0 C3B880 JP SET8253
80A3 11D115 RA: LD DE,15D1H
80A6 C3B880 JP SET8253
80A9 117713 Sl: LD DE,1377H
30AC C3B880 JP SET8253
80AF l15912 DO1: LD DE,1259H
80B2 C3B880 JP SET8253

80B5 111000 PAUSE: LD DE,10H

80B8 7B SET8253: LD A,E
80B9 D348 OUT (COUNT0),A
80BB 7A LD A,D
80BC D348 OUT (COUNT0),A
80BE C33180 JP PLAY

80C1 F5 NOSOUND: PUSH AF

80C2 D5 PUSH DE
80C0 3E0A LD A,10
80C5 D348 OUT (COUNT0),A
80C7 AF XOR A
80C8 D348 OUT (COUNT0),A
80CA 110005 LD DE,500H

96
80CD 1B J1: DEC DE
80CE 7A LD A,D
80CF B3 OR E
80D0 C2CD80 JP NZ,J1
80D3 D1 POP DE
80D4 F1 POP AF
80D5 C9 RET

0000 END

97
Chapter 15. DAC0808

1. Generating Pulse Wave 1 (DAC0808)

(a) Source file name : 80DA1.ASM
(b) Hexa file name : 80DA1.HEX
(c) Address : 5070H
(d) Action : Output '00H' and 'FFH' periodically by using D/A Converters
and output the pulse wave. Let's observe the wave of TP1 on
the oscilloscope. TP2 is for grounding.

① What is DAC0808?
DAC 0808 is 8-bit one channel current output D/A converter. The current signal form DAC
0808 should be converted into the voltage signal by using an OP amp. An OP amp, called ‘a
operational amplifier’ was used for the basic components of analog computers. An OP amp is
the DC amplifier with high gain and its characteristics of the input/output is applied to the
simple operational circuit like addition/subtraction or an oscillator The output current of
DAC0808 is the multiple of the digital input value and the reference current. The relation
between the current lout and the reference current 1ref is as follows.

This current signal is converted into the voltage signal through an OP amp. The output
voltage is from 0 to 10V. The minimum conversion voltage 10/256V because the input value is
in 256 level(from 0 to 255). This signal can be checked from TP1. From the program for
generating pulse wade, you can observe the shape of the wave by connecting TP1 to an
oscilloscope. TP2 is for grounding.

② Program
0030 DAC EQU 30H
0038 AD0 EQU 38H
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

98
8000 CD4800 START: CALL LCDCLR
8003 CD6000 CALL STRINGL
8006 20442F41 DB ' D/A Converter!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 2050756C DB ' Pulse Wave !!$'

802B AF MAIN: XOR A ;modify A to 0

802C D330 REPT: OUT (DAC),A ;output to D/A
802E CD3580 CALL DELAY ;pulse width depends on the
timer
8031 2F CPL ;inverse the signal
8032 C32C80 JP REPT ;jump to REPT

8035 06FF DELAY: LD B,0FFH

8037 10FE DJNZ $
8039 C9 RET

0000 END

2. Generating Pulse Wave 2 (DAC0808)

(a)Source file name : 80DA2.ASM
(b)Hexa file name : 80DA2.HEX
(C)Address : 5080H
(d)Action : Output ramp wave by increasing the data through D/A
CONVERTERS. Let's observe the wave of TP1 on the
oscilloscope. TP2 is for grounding.

0030 DAC EQU 30H

0038 AD0 EQU 38H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 20442F41 DB ' D/A Converter!$'

99
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 20205261 DB ' Ramp Wave !!$'
802B AF MAIN: XOR A
802C D330 REPT: OUT (DAC),A
802E 3C INC A
802F C32C80 JP REPT

0000 END

3. Generating Pulse Wave 3 (DAC0808)

(a) Source file name : 80DA3.ASM
(b) Hexa file name : 80DA3.HEX
(c) Address : 5090H
(d) Action : Output triangle wave by increasing the data through D/A
CONVERTERS and decreasing the data after it comes to the
maximum value. Let's observe the wave of TP1 on the
oscilloscope TP2 is for grounding.

0030 DAC EQU 30H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 20442F41 DB ' D/A Converter!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 54726961 DB 'Triangle Wave !!$'

802D AF MAIN: XOR A

802E D330 REPT: OUT (DAC),A
8030 3C INC A
8031 FEFF CP 0FFH
8033 C22E80 JP NZ,REPT
8036 D330 REPT1: OUT (DAC),A
8038 3D DEC A
8039 A7 AND A ;check if A is zero or not

100
803A C23680 JP NZ,REPT1
803D C32E80 JP REPT

0000 END
4. Generating Pulse Wave 4 (DAC0808)
(a) Source file name : 80DA4.ASM
(b) Hexa file name : 80DA4.HEX
(c) Address : 50A0H
(d) Action : Output sine wave in the constant period by making sine wave
data normalize by 10 " through D/A CONVERTERS. Let's
observe the wave of TP1 on the oscilloscope. TP2 is for
grounding.

0030 DAC EQU 30H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 20442F41 DB ' D/A Converter!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 20205369 DB ' Sine Wave !!$'

802B 0624 MAIN: LD B,36 ;the number of the output data

802D 213980 LD HL,SINE ;set he starting data address
8030 7E REPT: LD A,(HL)
8031 D330 OUT (DAC),A
8033 23 INC HL
8034 10FA DJNZ REPT
8036 C32B80 JP MAIN

8039 ; 0, 10, 20, 30, 40, 50, 60, 70

8039 8096ABC0 SINE DB 128,150,171,192,219,225,238,247
8041 ; 80, 90, 100, 110,120,130,140,150
8041 FDFFFDF7 DB 253,255,253,247,238,225,210,192
8049 ; 160,170,180,190,200,210,220,230
8049 AB96806A DB 171,150,128,106,85,65,46,31
8051 ; 240,250,260,270,280,290,300,310
8051 12090301 DB 18, 9, 3, 1, 3, 9, 18, 31
101
8059 ; 320,330,340,350,360
8059 2E41556A DB 46, 65, 85, 106,128

0000 END
5. Control the Speed of a DC Motor (ADC0890, DAC0808)
(a) Source file name : 80ADDA.ASM
(b) Hexa file name : 80ADDA.HEX
(C) Address : 50E0H
(d) Action : read the volume signal through A/D converter and output the
data through D/A converter to control the speed of a DC
motor. Observe the speed by changing the volume after
execute the program.

① What is the ADC0809?

The A/D converter is the IC device that convert the analog signal to the digital signal.
According to the method of conversion, there are integral, successive comparison and parallel
comparison converters. The integral type can obtain high disintegration and high degree, but
the conversion speed is very slow. The parallel comparison type can complete the conversion
at one time, so very fast. However the circuit is very complex. Unlike them, the successive
comparison type has mixed characteristic of them and consists of 1 comparator and D/A
converter, successive comparison logic. The voltage which is generated through D/A converter
dedicated to reference voltage is converted to digital signals by successively comparing, one
by one, the input voltage with from the MSB to the end. Here's the main characteristic
* CMOS structure
* externally applied reference power
* Microprocessor compatible
* built-in 8 channel multiplex
* only +5V applied voltage
* no need to adjust the Zero and Pole

② Program

0030 DAC EQU 30H

0038 AD0 EQU 38H
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

102
8000 CD4800 START: CALL LCDCLR
8003 CD6000 CALL STRINGL
8006 20412F44 DB 'A/D, D/A TEST!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 20444950 DB 'DIP1 = NO.4 ON$'
802C 0608 LD B,8 ;the number of call the timer give
;the enough time to check
802E CD7280 DELAY: CALL TIMER
8031 10FB DJNZ DELAY
8033 CD4800 CALL LCDCLR
8036 CD6000 CALL STRINGL
8039 20444950 DB 'DIP1 = NO.4 ON$'
8049 CD5800 CALL LINE2
804C CD6000 CALL STRINGL
804F 20496E70 DB 'Input = Volumes'

805F D338 MAIN: OUT (AD0),A ;give the start signal of A/D
;converter through OUT command
;A has no more meaning
8061 060A LD B,10 ;the conversion time of A/D
;Converter
8063 10FE DJNZ $
8065 DB38 IN A,(AD0) ;read the value of A/D conversion
8067 D330 OUT (DAC),A ;output to D/A Converter. drive
;the motor
8069 2F CPL ;inverse the signal
806A D350 OUT (LED),A ;output to the 8-bit LED
806C CD7280 CALL TIMER
806F C35F80 JP MAIN

8072 210050 TIMER: LD HL,5000H

8075 2B TIME: DEC HL
8076 7C LD A,H
8077 B5 OR L
8078 C27580 JP NZ,TIME
807B C9 RET

0000 END

103
6. Measurement of the rotation numbers of a DC motor
(a) Source file name : 80COUPL.ASM
(b) Hexa file name : 80COUPL.HEX
(c) Address : 50F0H
(d) Action : read the volume signal through the A/D converter and output
it to the D/A converter. Then control the speed of a DC motor
and read the port interrupt. Whenever it counts 16 (16 per 1
rotation), add 1 to the data. Then output it to the LCD. If the
DC motor doesn't rotate after the program starts executing,
turn the volume up to the maximum and execute it again. In
spite of the lower limit in the program, there can be a motor
which doesn't work properly. After executing the program,
observe the change of rotation numbers while changing the
volume. The counter consists of 8-digit decimal counters.

0030 DAC EQU 30H

0010 KEY EQU 10H
0050 LED EQU 50H
0038 AD0 EQU 38H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LlNE2 EQU 0058H
0080 LOUTA EQU 0080H
8100 COUNT EQU 8100H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 50686F74 DB 'Photo-Coupler !$'
8016 210000 LD HL,0 ;clear the counter
8019 220081 LD (COUNT),HL
801C 220281 LD (COUNT+2),HL

801F D338 MAIN: OUT (AD0),A

8021 060A LD B,10
8023 10FE DJNZ $
8025 DB38 IN A,(AD0)
8027 F61F OR 00011111B ;limit the minimum value
8029 D330 OUT (DAC),A
104
802B 2F CPL
802C D350 OUT (LED),A

802E 0610 J1: LD B,16 ;the counter for checking 1

;rotation
8030 DB10 J2: IN A,(KEY) ;the signal input of the photo-
;interrupt
9032 CB6F BIT 5,A ;bit 5 is a photo signal
8034 C23080 JP NZ,J2

8037 DB10 J3: IN A,(KEY)

8039 CB6F BIT 5,A
803B CA3780 JP Z,J3
803E 10F0 DJNZ J2 ;1 rotation?
8040 CD5800 CALL LINE2
8043 CD6000 CALL STRINGL
8046 20202024 DB ' $'
804A DD210081 LD IX,COUNT ;the starting address of the
;counter
804E DD7E00 LD A,(IX) ;transmit the LSB data of the
;counter to A
8051 C601 ADD A,1 ;add 1
8053 27 DAA ;decimal conversion(you cannot
;use 'INC A' for that)
8054 DD7700 LD (IX),A ;store the data
8057 D27B80 JP NC,J4 ;if no carry occurs(less than 99),
;finish the operation
805A DD7E01 LD A,(IX+1)
805D C60l ADD A,1
805F 27 DAA
8060 DD7701 LD (IX+1),A
8063 D27B80 JP NC,J4
8066 DD7E01 LD A,(IX+2)
8069 C60l ADD A,1
806B 27 DAA
806C DD7701 LD (IX+2),A
806F D27B80 JP NC,J4
8072 DD7E01 LD A,(IX+3)
8075 C601 ADD A,1
8077 27 DAA
8078 DD7701 LD (IX+3)
105
807B 0604 J4: LD B,4 ;the numbers of the output
807D DD7E03 J5: LD A,(IX+3) ;transmit the counter data to A
;(output in order of from the MSB
;to the LSB)
8080 CD8000 CALL LOUTA ;output to the LCD
8083 DD2B DEC IX ;decrement the data address by 1
8085 10F6 DJNZ J5 ;jump to J5 if the number of the
;output is not 4
8087 C31F80 JP MAIN
0000 END

7. Measurement of the RPS of a DC motor

(a)Source file name : 80RPS.ASM
(b)Hexa file name : 80RPS.HEX
(c)Address : 5180H
(d)Action : read the volume signal through the A/D converter and output
it to the D/A converter. Then control the DC motor and
through the 8253 cause the interrupt to occur 1 second later
and read the photo interrupt. Whenever it counts 16, add 1 to
the data. If the interrupt is requested, change the number of
counting into the decimal and output them to the LCD. If the
DC motor doesn't rotate after the program starts executing,
turn the volume up to the maximum and execute it again. Turn
on the dip switch 1, 4, and 5 before execute the program.

0030 DAC EQU 30H

0010 KEY EQU 10H
0050 LED EQU 50H
0038 AD0 EQU 38H
0048 COUNT0 EQU 48H
0049 COUNT1 EQU 49H
004B CSR EQU 4BH

FF04 INT_BUFF EQU 0FF04H

0048 LCDCLR EQU 0048H
0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
0070 LOUTHL EQU 0070H

106
0080 LOUTA EQU 0080H
0090 LCD_OUT EQU 0090H

8000 ORG 8000H

8000 3100FF START: LD SP,0FF00H

8003 ED56 IM 1 ;set the interrupt mode 1
8005 F3 DI ;prohibit the interrupt
8006 CD4800 CALL LCDCLR
8009 CD6000 CALL STRINGL
800C 44495031 DB 'DIP1=NO.4, 5 ON$'

801D 3E34 I8253 LD A,00110100B ;COUNT0, MSB/LSB LOAD,

;MODE3
801F D34B OUT (CSR),A
8021 3E58 LD A,01011000B ;COUNT1, LSB LOAD, MODE5
8023 D34B OUT (CSR),A

8025 110030 LD DE,24576/2 ;firstly, divide 2.4576MHz by

;12288 . (it becomes 200Hz)
8028 7B LD A,E
8029 D348 OUT (COUNT0),A
802B 7A LD A,D
802C D348 OUT (COUNT0),A

802E 218380 LD HL,INTR ;set the interrupt address

8031 2204FF LD (INT_BUFF),HL

8034 CD5800 CALL LINE2

8037 CD6000 CALL STRINGL
803A 20205250 DB 'RPS=$'
8043 210000 LD HL,0
8046 CD7000 CALL LOUTHL

8049 D338 CNT: OUT (AD0),A

804B 060A LD B,10
804D 10FE DJNZ $
804F DB38 IN A,(AD0)
8051 C61F ADD A,00011111B
8053 3002 JR NC,DA_OUT ;jump to DA_OUT if not over FFH
8055 3EFF LD A,0FFH ;change the data to FFH if so
107
8057 D330 DA_OUT: OUT (DAC),A
8059 2F CPL
805A D350 OUT (LED),A

805C 3EC8 CNT1: LD A,200 ;count 200 of the first divided

;200Hz and then cause the
;interrupt to occur
805E D349 OUT (COUNT1),A
8060 FB EI ;accept the interrupt

8061 DB10 J1: IN A,(KEY)

8063 CB6F BIT 5,A
8065 C26180 JP NZ,J1

8068 DB10 J2: IN A,(KEY)

806A CB6F BIT 5,A
806C CA6880 JP Z,J2

806F 23 INC HL
8070 C36180 JP J1

8073 0604 INTR: LD B,4 ;HL/16=RPS (remove the MSB 4

;bit of HL. namely, after dividing
;by 16. round them off to the
;floating points)
8075 CB3C INTR1: SRL H

8077 CB1D RR L
8079 10FA DJNZ INTR1

807B 3EC8 LD A,0C8H ;move the cursor of the LCD

807D CD90000 CALL LCD_OUT
;decimal conversion
8080 0600 LD B,0
8082 7D LD A,L
8083D664 BCD1: SUB 100
8085 04 INC B
8086 D28380 JP NC,BCD1
8089 05 DEC B
808A F5 PUSH AF

108
808B 78 LD A,B
808C CD8000 CALL LOUTA
808F F1 POP AF
8090 C664 ADD A,100

8092 0600 LD B,0

8094 D60A BCD2: SUB 10
8096 04 INC B
8097 D29480 JP NC,BCD2
809A 05 DEC B
809B C60A ADD A,10
809D CB00 RLC B
809F CB00 RLC B
80A1 CB00 RLC B
80A3 CB00 RLC B
80A5 B0 OR B
80A6 CD8000 CALL LOUTA

80A9 210005 LD HL,500H

80AC 2B INTR2: DEC HL
80AD 7C LD A,H
80AE B5 OR L
80AF 20FB JR NZ,INTR2

80B1 DD214980 LD IX,CNT ;on RETI instruction. change

;the return address
80B5 DDE3 EX (SP),IX
80B7 ED4D RETI

0000 END

109
Chapter 16. ADC 0809

1. Voltage Input (ADC0809)

(a)Source file name : 80AD0.ASM
(b)Hexa file name : 80AD0.HEX
(c)Address : 50B0H
(d)Action : apply from 0 to 5 voltage, which is an analog value of the
volume, to A/D converter in order to convert that to the 8-bit
digital value. Then output them to the 8-bit LED. After
executing the program, convert them into the voltage signal
from 0 to 5 and output them to the LCD.

0030 DAC EQU 30H

0038 AD0 EQU 38H
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 412F4420 DB 'A/D Converter 0!$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 3D49E70 DB '=Input Voltage=$'

802D D338 MAIN: OUT (AD0),A

802F 060A LD B,10
8031 10FE DJNZ $
8033 DB38 IN A,(AD0)
8035 2F CPL
8036 D350 OUT (LED),A
8038 CD3E80 CALL TIMER
803B C32D80 JP MAIN

803E 210050 TIMER: LD HL,5000H

110
8041 2B TIME: DEC HL
8042 7C LD A,H
8043 B5 OR L
8044 C24180 JP NZ,TIME
8047 C9 RET

0000 END

2. Measurement of Illumination (ADC0809)

(a)Source file name : 80AD1.ASM
(b)Hexa file name : 80AD1.HEX
(c)Address : 50C0H
(d)Action : apply from 0 to 5 voltage, which is an analog value of the
Photo TR, to A/D converter in order to convert that to the 8-
bit digital value. Then output them to the 8-bit LED.

0030 DAC EQU 30H

0039 AD1 EQU 39H
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 412F4420 DB 'A/D Converter 1!$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 3D496E70 DB '=Input Photo TR=$'

802E D339 MAIN: OUT (AD1),A

8030 060A LD B,10
8032 10FE DJNZ $
8034 DB39 IN A,(AD1)
8036 2F CPL
8036 D350 OUT (LED),A
8039 CD3F80 CALL TIMER

111
803C C32E80 JP MAIN

803F 210050 TIMER: LD HL,5000H

8042 2B TIME: DEC HL
8043 7C LD A,H
8044 B5 OR L
8045 C24280 JP NZ,TIME
8048 C9 RET

0000 END

3.Measurement of Temperature (ADC0809)

(a)Source file name : 80AD2.ASM
(b)Hexa file name : 80AD2.HEX
(c)Address : 50D0H
(d)Action : apply from 0 to 5 voltage, which is an analog value of the
thermistor, to A/D converter in order to convert that to the
8-bit digital value. Then output them to the 8-bit LED.

0030 DAC EQU 30H

003A AD2 EQU 3AH
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 412F4420 DB 'A/D Converter 0!$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 496E7075 DB '=Input Thermistor=$'
802E D33A MAIN: OUT (AD2),A
8030 060A LD B,10
8032 10FE DJNZ $
8034 DB3A IN A,(AD2)
8036 2F CPL

112
8037 D350 OUT (LED),A
8039 CD3E80 CALL TIMER
803C C32E80 JP MAIN
803F 210050 TIMER: LD HL,5000H
8042 2B TIME: DEC HL
8043 7C LD A,H
8044 B5 OR L
8045 C24280 JP NZ,TIME
8048 C9 RET

0000 END

4. Recording and Playing the Voice (ADC0809, DAC0808)

(a)Source file name : 80VOICE.ASM
(b)Hexa file name : 80VOICE.HEX
(c)Address : 5110H
(d)Action : apply from 0 to 5 voltage, which is an analog value of the
amplified microphone signal, to A/D converter in order to
convert that to the 8-bit digital value. Then store them into
the RAM, play them as voice signals through the D/A
converter. Record in a little bit loud mode after the message
'Recording' on the LCD appears.

0030 DAC EQU 30H

003B AD3 EQU 3BH
0050 LED EQU 50H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
0080 LOUTA EQU 0080H
80FF COUNT EQU 80FFH
8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 566F6963 DB 'Voice DIP1=3 ON$'
8017 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 203D2049 DB '=Input Mic.=$'

113
802C 0604 LD B,4
802E CDB080 DELAY: CALL TIMER
8031 10FB DJNZ DELAY
8033 CD5800 MAIN: CALL LINE2
8036 CD6000 CALL STRINGL
8039 20205245 DB 'RECORDING...$'
804A DD210081 LD IX,8100H ;the starting address of the data
;stored
804E 210070 LD HL,7000H ;the number of the output

8051 3E80 ADREPT: LD A,80H

8053 D368 OUT (STEP),A ;output the hold signal (it prevents
;the A/D conversion from
;changing the analog signal)
8055 D33B OUT (AD3),A
8057 060D LD B,13
8059 10FE DJNZ $
805B DB3B IN A,(AD3)
805D DD7700 LD (IX),A
8060 3E00 LD A,00H
8062 D368 OUT (STEP),A ;output the sampling signal
8064 DD23 INC IX
8066 2B DEC HL
8067 7C LD A,H
8068 B5 OR L
8069 C25180 JP NZ,ADREPT
806C CDB080 CALL TIMER

806F AF XOR A ;clear the replay number counter

8070 32FF80 LD (COUNT),A
8073 CD5800 DAOUT: CALL LINE2
8076 CD6000 CALL STRINGL
8079 20504C41 DB 'PLAYING...$'

8086 3AFF80 LD A,(COUNT)

8089 C601 ADD A,1
808B 27 DAA
808C 32FF80 LD (COUNT),A
808F CD8000 CALL LOUTA ;output the number of replay

114
8092 DD210081 LD IX,8100H ;the starting address of the data
8096 210070 LD HL,7000H ;the number of the data

8099 DD7E00 DAREPT: LD A,(IX)

809C 0613 LD B,19
809E 10FE DJNZ $
80A0 D330 OUT (DAC),A
80A2 DD23 INC IX
80A4 2B DEC HL
80A5 7C LD A,H
80A6 B5 OR L
80A7 C29980 JP NZ,DAREPT
80AA CDB080 CALL TIMER
80AD C37C80 JP DAOUT

80B0 210050 TIMER: LD HL,5000H

80B3 2B TIME: DEC HL
80B4 7C LD A,H
80B5 B5 OR L
80B6 C2B380 JP NZ,TIME
80B9 C9 RET

0000 END

115
Chapter 17. Stepping Motor

1.Control of the Stepping Motor (74LS373)

(a)Source file name : 80STEP.ASM
(b)Hexa file name : 80SETP.HEX
(c)Address : 5040H
(d)Action : For the first action, it is driven clockwise as one phase
moment type. With holding the 8-bit switch 0, it is driven
counter-clockwise. Then if the switch 1 is pushed, it is driven
as two phase exciting. The driving status of the stepping
motor can be monitored with the LED. You can drive directly
the stepping motor by connecting driving power and stepping
motor to CN2.

① Characteristic of a Stepping Motor

The main feature of the stepping motor is, that it is can be controlled with digital signals by
the Pulse. The reason is that there's no feedback and it rotates the fixed angle, and stops in
high precision. Moreover at the time of stop, unlike other motors, it has a very large stop
torque.
1) The rotation angle of the motor is proportional to the number of the input per the unit
time.
2) The rotation speed of the motor is proportional to the number of the input per the unit
time.
3) The unit of the rotation speed is PPS, and is different from the rotation per
minutes(RPM) of other motors.
4) The tolerance errors of rotation angle should not be accumulated.

② Driving Method
1) 1 phase exciting method : the way to drive the motor by exciting every one pair. This
method requires low power and the torque is small.

116
 INPUT CCW π θ CW
A

/A

/B

2) 2 phase exciting method : the way to drive the motor by exciting two phases
simultaneously. This method requires high power but the torque is also large.

INPUT CCW π θ CW
A

/A

/B

3) 1-2 phase exciting method: the way to alternate 1 phase exciting and 2phases exciting.
Because the angle of STEP become 1/2, it is possible to control precisely and it rotates
smoothly. However it is not suitable for the high speed.

INPUT CCW π θ CW
A

/A

/B

117
③ Program
0050 LED EQU 50H
0058 SWITCH EQU 58H
0068 STEP EQU 68H
0048 LCDCLR EQU 0048H
0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 53746570 DB 'Stepping Motor!$'
8016 CD5800 CALL LINE2
8019 CD6000 CALL STRINGL
801C 50726573 DB 'Press S/W 0 or 1$'

802D 3E11 LD A,11H ;decide the exciting method

802F D368 MAIN: OUT (STEP),A ;output the data
8031 CD5580 CALL TIMER

8034 F5 PUSH AF
8035 DB58 IN A,(SWITCH) ;check the status of he switch
8037 D350 OUT (LED),A ;output to the LED
8039 E603 AND 00000011B ;clear just leaving the MSB 2 bit
803B FE03 CP 00000011B ;is there any key pushed?
803D C24580 JP NZ,J1 ;jump to J1 if so
8040 F1 POP AF
8041 07 RLCA
8042 C32F80 JP MAIN

8045 FE02 J1: CP 00000011B ;is the bit 1 switch pushed?

8047 CA5080 JP NZ,J1 ;jump to J2 if not
804A F1 POP AF
804B 3E22 LD A,33H ;change the exciting method
804D C32F80 JP MAIN

8050 F1 J2: POP AF

8051 0F RRCA
8052 C32F80 JP MAIN

118
8055 F5 TIMER: PUSH AF
8056 210090 LD HL,9000H
8059 2B TIME: DEC HL
805A 7C LD A,H
805B B5 OR L
805C C25980 JP NZ,TIME
805F F1 POP AF
8060 C9 RET

0000 END

119
Chapter 18. LCD Control

1. LCD control (LCD)

(a) Source file name : 80LCD.ASM
(b) Hexa file name : 80LCD.HEX
(c) Address : 5190H
(d)Action : write character fonts to CG RAM of the LCD, display them on
the LCD

① I/O pin configuration of LCD MODULE

Pin No. Sign Function

1 Vss GND
2 Vdd VCC
3 Vo LCD Display, Illumination Control
L: Instruction input
4 RS
H: Data input
H: Read (LCD → CPU)
5 R/W
L: Write (LCD ← CPU)
6 E Enable(accepts data in the falling edge of from H to L)
7 D0 Data Bus
8 D1 Data Bus
9 D2 Data Bus
10 D3 Data Bus
11 D4 Data Bus
12 D5 Data Bus
13 D6 Data Bus
14 D7 Data Bus

◈ In HD44780, it can be interfacing to 4 bit or 8 bit CPU. For 4-bit CPU, only from D4 to D7
can be used.

② Control of LCD MODULE

1) Register
The controller consists of Instruction Register(IR) and Data Register(DR) both of which
are 8-bit registers. it can be selected by the signal of Register Select(RS)
IR has the instruction set of Clear, Cursor, Home etc. It has also the display RAM(DD
RAM) and the address of Character Generator RAM(CG RAM)
This register is writable to CPU but not readable. DR has the data which is written to DD

120
RAM, CG RAM and the data which is read from DD RAM, CG RAM.
2) BF(Busy Flag)
BF notifies if LCD Module can receive the next instruction or not. When RS = 0, R/W = 1,
it outputs the data to D7
BF = 1: it means the internally running and it cannot receive the next instruction.
BF = 0: it can receive the next instruction.
Accordingly, when the next instruction executes, you should check the status of BF.
Without checking the status of BF, if the instruction executes, the instruction should execute
after waiting for the running time. With the standard of the clock at 250KHz in the module, the
running time of CLEAR and HOME is 1.64ms and the rest is 40us

3) CG ROM(Character generator ROM)

CG ROM can generates 192 character patterns of 8-bit character codes. The following
table shows the character code and pattern. More than 80H of the character pattern depends
on CG ROM.

4) CG RAM(Character Generator RAM)

CG RAM is the RAM which is used for making the character pattern by the user. 5 x 7
Dot has 8 patterns, and 5 x 10 Dot has 4 patterns.

◆ Character codes and Character Patterns ◆

121
 In the data of CG RAM, '1' means display selected and '0' means not selected. the
character code from 0 to 2 corresponds to the address bit(from 3 to 5)of CG RAM. The
address bit(from 0 to 2)of CG RAM displays the column location of the character pattern. the
8th column of the character pattern is the location of the cursor and it can be used with making
the pattern. When the pattern of CG RAM is read, from 4 to 7 bit of the code select '0'. bit 3 is
invalid because from 0 to 2 bit decides which pattern can be read. Namely, '00H' and '08H'
selects the same character. In order to display Korean, display 1 character in the space for 4
characters because it is impossible to use 5 x 7 dot See the example.

122
③ Concepts of Instructions
Code Description
Instruction
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
Clear all the display and set the
Display Clear 0 0 0 0 0 0 0 0 0 1 address 0 of DD RAM in the
address counter
Set the address 0 of DD RAM in
Cursor Home 0 0 0 0 0 0 0 0 1 ▶ the address counter. The contents
of DD RAM will not be changed.
Decide the moving direction of the
Entry mode
0 0 0 0 0 0 0 1 1/D S cursor and the shift when it reads
Set
and writes the data.
Display Set Display on/off(D), Cursor
On/OFF 0 0 0 0 0 0 1 D C B on/off(C), the Bland of the cursor
Control location character.
Without changing the contents of
Cursor/ S/ R/
0 0 0 0 0 0 ▶ ▶ DD RAM, display the moving of the
Display shift C L
cursor and the shift.

Code Description
Instruction
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
Set the length of the interface
Function Set 0 0 0 0 1 DL N F ▶ ▶ data(DL), the number of display
lines, and the character font(F).
Set the address of CG RAM. The
CG RAM
0 0 0 1 Acg data transmitted after that is the
Address Set
data of CG RAM
Set the address of DD RAM. The
DD RAM
0 0 1 Add data transmitted after that is the
Address Set
data of CG RAM
Busy Flag/
Address 0 1 BF AC Decode the contents of BF and AC
decoding
CG RAM,
Write the data to CG RAM and DD
DD RAM 1 0 Write Data
RAM
Data Input
CG RAM,
DD RAM Decode the data from CG RAM
1 1 Read Data
Data and DD RAM
Decoding

123
▶ : invalid bit
I/D = 1 : increment 0 : decrement
S = 1 : accompanying with display shift 0 : doesn't shift
S/C = 1 : shift of display 0 : shift of the cursor
R/L = 1 : shift right 0 : shift left
DL = 1 : 8 BIT 0 : 4 BIT
N = 1 : 2 lines 0 : 1 line
F = 1 : 4 x 10 dot 0 : 5 x 7 dot
BF = 1 : internally running 0 : instruction

◆ Acg : the address of CG RAM

Add : the address of DD RAM. corresponding to the address of the cursor
AC : Address counter (using both DD RAM and CG RAM)

④ Initial Setting of the LCD according to instructions

1) Display Clear
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 1

After clearing the previous display, the cursor goes back to HOME(0th column). The
ASCII code '20H' of space are filled in all the address of DD RAM, and the address 0 of the DD
RAM in AC is set. If the display shifts, it goes back to the original location. After the instruction
executes the entry mode turns into the increment mode.

2) Cursor HOME
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 1 ▶
▶ : invalid bit

The cursor goes back to HOME(0th column). The address 0 of the DD RAM in AC is set.
The cursor goes back to HOME. If the display shifts, it goes back to the original location. The
content of DD RAM will not be changed.

124
3) Entry Mode Set
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 1 I/D S

The moving direction of the cursor is decided.

I/D : When the character code is read and written from/to DD RAM, it increments or
decrements the address of DD RAM by 1. For CG RAM, it is the same.
When I/D = 1, it increments by 1 and the cursor or blank shifts right.
When I/D = 0, it decrements by 1 and the cursor or blank shifts left.
When S = 1, after writing the data to DD RAM, it moves all the data displayed. when it
reads the data from DD RAM, the displayed data will not shift.
When S = 0, the displayed data will not shift.

4) Display On/Off Set

RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 1 D C B

It set s Display On/Off, Cursor On/Off, and flickering of the character which is in the
location of the cursor. Cursor On/Off and flickering is the line which the address of DD RAM
points to.
When D = 1, Display is set ON.
When D = 0, Display is set OFF.
In the case that from D = 0 Display is OFF, display like D = 1 because the displayed data
remains in DD RAM.

When C = 1, it displays the cursor.

When C = 0, it doesn't display the cursor.
When B = 1, it displays the cursor.
When B = 0, the cursor doesn't flicker
To make it flicker, the character and the blank should be displayed alternatively. The
exchange rate of flickering is 0.4 seconds when fosc = 250KHz. The cursor and flickering can
be set at the same time.

125
5) Cursor/Display Shift
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 S/C R/L ▶ ▶
▶: invalid bit

Without changing the contents of DD RAM. It displays the moving of the cursor and
shifts Display.
S/C R/L Action
0 0 Shift lift the location of the cursor(decrement AC by 1)
0 1 Shift right the location of the cursor(increment AC by 1)
1 0 Shift left the entire display. The cursor moves according to the display.
1 1 Shift left the entire display. The cursor moves according to the display.

6) Function Set
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 DL N F ▶ ▶

DL : Set the length of the interface

When DL = 1, it is set 8-bit.
When DL = 0, it is set 4-bit(using from D4 to D7). Then it needs to transmit the data
twice. First it transmits the MSB 4-bits, and then transmits the LSB 4 bit.
N : Set the number of display lines
F : Set the Font of the character

NF The number of display lines Font of the character

00 1 5x7 dot
01 1 5x10 dot
1 ▶ 2 5x7 dot

126
⑤ Program
0048 LCDCLR EQU 0048H
0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
0090 LCD_OUT EQU 0090H
0098 SCAN EQU 0098H

8000 ORG 8000H

8000 3E40 START: LD A,01000000B ;CG RAM Address set

8002 CD9000 CALL LCD_OUT
8005 0600 LD B,0 ;delay the time
8007 10FE DJNZ $

8009 CD6000 CALL STRINGL

800C 041F000E DB 04H, 1FH, 00H, 0EH, 11H, 11H, 11H, 0EH
8014 04040404 DB 04H, 04H, 04H, 04H, 07H, 04H, 04H, 04H
801C 001F0101 DB 00H, 1FH, 01H, 01H, 1FH, 10H, 10H, 1FH
8024 04040404 DB 04H, 04H, 04H, 04H, 04H, 04H, 04H, 04H

802C 000F0000 FONT_LOW: DB 00H, 0FH, 00H, 00H, 00H, 00H, 00H, 00H
8034 001C0404 DB 00H, 1CH, 04H, 04H, 04H, 04H, 04H, 00H
803C 000F0808 DB 00H, 0FH, 08H, 08H, 08H, 08H, 0FH, 00H
8044 001C0404 DB 00H, 1CH, 04H, 04H, 04H, 04H, 1CH, 00H,'$'

804D CD4800 CALL LCDCLR

8050 CD6000 CALL STRINGL
8053 20000120 DB ' ',0,1,' ',2,3,' Press$'

8062 CD5800 CALL LINE2

8065 CD6000 CALL STRINGL
8068 20040520 DB ' ',4,5,' ',6,7,' KEYPAD! $'

8079 CD9800 CALL SCAN ;keypad input

807C CF RST 08H ;the program finishes

00 END

127
Chapter 19. Testing Melody

1. Generating Melody (74LS74)

(a) Source file name : 80SOUND.ASM
(b) Hexa file name : 80SOUND.HEX
(c) Address : 5100H(Waltz by F.Chopin and the korean song
by Kim Hyun-Sik)
(d) Action : Of the data bus of the micro-processor, generate the sound
by alternating 'H' and 'L' of the data bit 7, through the flip-
flop IC 74LS74, in the constant period. This method is the
same as that using the 8255. It's so difficult to take care of
programming. Try to understand the program.

◆ the musical scale and tempo data : After executing the following program, input the data of
other songs by referring to the following data.

128
0050 LED EQU 50H
0058 SWITCH EQU 58H
0070 SPK EQU 70H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
9000 FLAG EQU 9000H

8000 ORG 8000H

8000 CD4800 START: CALL LCDCLR

8003 CD6000 CALL STRINGL
8006 534F554E DB 'SOUND GENERATOR !$'
8017 CD5800 CALL LINE2
801A CD6000 CALL STRINGL
801D 50726573 DB 'Press S/W 0 or 1$'

802E DB58 INPUT: IN A,(SWITCH) ;input the status of the switch

8030 FEFF CP 0FFH ;is that switch pushed?
8032 CA2E80 JP Z,INPUT ;jump to INPUT if not

8035 2F CPL ;inverse the signal

8036 FE01 CP 1 ;is the bit 0 switch pushed?

8038 CA4380 JP Z,SONG1
803B FE02 CP 2 ;is the bit 1 switch pushed?
803D CAD980 JP Z,SONG2
8040 C32E80 JP INPUT

8043 CD4800 SONG1: CALL LCDCLR

8046 CD6000 CALL STRINGL
8049 462E4368 DB 'F,Chopin.. Waltz$'
805A CD5800 CALL LINE2
805D CD6000 CALL STRINGL
8060 20444950 DB 'DIP1 = NO,1 ON$'

8070 210006 LD HL, LENGTH1

8073 220090 LD (FLAG),HL

129
8076 21ADB1 LD HL,DATA1 ;the starting address of the data
8079 CD4F81 CALL PLAY ;play the sound
807C 21C581 LD HL, DATA2
807E CD4F81 CALL PLAY
8088 21A582 LD HL,DATA3
808B CD4F81 CALL PLAY
808E 21A582 LD HL,DATA4
8091 CD4F81 CALL PLAY
8094 216783 LD HL,DATA5
8097 CD4F81 CALL PLAY
809A 213584 LD HL,DATA6
809D CD4F81 CALL PLAY
80A0 213584 LD HL,DATA6
80A3 CD4F81 CALL PLAY
80A6 213584 LD HL,DATA6
80A9 CDAF81 CALL PLAY
80AC 213584 LD HL,DATA6
80AF CD4F81 CALL PLAY

80B2 21C581 LD HL,DATA2

80B5 CD4F81 CALL PLAY
80B8 21C581 LD HL,DATA2
80BB CD4F81 CALL PLAY
80BE 21DF81 LD HL,DATA3

80C1 CD4F81 CALL PLAY

80C4 21A582 LD HL,DATA4
80C7 CD4F81 CALL PLAY
80CA 21A582 LD HL,DATA4
80CD CD4F81 CALL PLAY
80D0 214384 LD HL,DATA7
80D3 CD4F81 CALL PLAY
80D6 C30080 JP START

1400 LENGTH2: EQU 1400H

80D9 CD4800 SONG2: CALL LCDCLR
80DC CD6000 CALL STRINGL
80DF 20204B69 DB 'Kim HyUN-Dik$'

130
80EE CD5800 CALL LINE2
80F1 CD6000 CALL STRINGL
80F4 20444950 DB 'DIP1 = NO.1 ON$'
8104 210014 LD HL,LENGTH2
8107 220090 LD (FLAG),HL

810A 214784 LD HL,DATA10 ;the starting address of the data

810D CD4F81 CALL PLAY ;play the sound
8110 216584 LD HL,DATA11
8113 CD4F81 CALL PLAY

8116 218784 LD HL,DATA12

8119 CD4F81 CALL PLAY
811C 21A584 LD HL,DATA13
811F CD4F81 CALL PLAY
8122 21B984 LD HL,DATA14
8125 CD4F81 CALL PLAY
8158 214784 LD HL,DATA10
812B CD4F81 CALL PLAY
812E 21C984 LD HL,DATA15

8131 CD4F81 CALL PLAY

8134 218784 LD HL,DATA12
8137 CD4F81 CALL PLAY
813A 21A584 LD HL,DATA13
813D CD4F81 CALL PLAY
8140 21EB84 LD HL,DATA16
8143 CD4F81 CALL PLAY
8146 218785 LD HL,DATA17
8149 CD4F81 CALL PLAY
814C C30090 JP START

814F 7E PLAY: LD A,(HL) ;transmit the musical scale data to

;A
8150 A7 AND A ;is the end of the data?('0' should
;be in the end of the data)
8151 C8 RET Z ;return if it is in the end.
8152 23 INC HL ;increment the data pointing
;address
8153 4E LD C,(HL) ;store the tempo data into C

131
8154 47 LD B,A ;store the scale data into B
8155 3C INC A ;increment the scale data
8156 CA9081 JP Z,8 ;jump to J8 if the scale data is
'FFH'(FFH is the code of no-
;sound. If increment FFH by 1, it
;becomes '0')
8159 E5 PUSH HL
815A CD6281 CALL J2 ;generate one sound
815D E1 POP HL

815E 23 J1: INC HL ;increment the data point address

815F C34F81 JP PLAY

8162 2A0090 J2: LD HL,(FLAG) ;transmit the reference tempo to

;HL
8165 50 J3: LD D,B ;transmit the scale data to D
8166 3EFF LD A,0FFH ;set the output data)only bit 7
8168 D370 OUT (SPK),A ;output to the speaker

816A 2B J4: DEC HL ;decrement the reference tempo

816B 7C LD A,H ;the MSB of the reference tempo
816C A7 AND A ;check if the tempo is zero or not
816D C28581 JP NZ,J5 ;jump to J5 if not zero

8170 2A0090 LD HL,(FLAG) ;transmit the reference tempo to

;HL
8173 0D DEC C ;decrement the tempo data
8174 C8 RET Z ;return if it's zero

8175 15 J5: DEC D ;decrement the scale data

8176 C26A81 JP NZ,J4 ;jump to J4 if not zero
8179 50 LD D,B ;transmit the scale data to D
817A 3E00 LD A,00H ;set the output data(bit 7 = 0)
817C D370 OUT (SPK),A ;output to the speaker
817E 2B DEC HL ;decrement the reference tempo

817F 7C J6: LD A,H

8180 A7 AND A
8181 C28981 JP NZ,J7
8184 2A0090 LD HL,(FLAG)

132
8187 0D DEC C
8188 C8 RET Z

8189 15 J7: DEC D

818A C27F81 JP NZ,J6
818D C36581 JP J3 ;no-sound routine
8190 E5 J8: PUSH HL
8191 2A0090 LD HL,(FLAG)

8194 50 J9: LD D,8

8195 2B J10: DEC HL

8196 7C LD A,H
8197 A7 AND A
8198 C2A281 JP NZ,J11
819B 2A0090 LD HL,(FLAG)
819E 0D DEC C
819F CAA981 JP Z,J12

81A9 E1 J12: POP HL

81AA C35E81 JP J1

81AD 40064403 DATA1: DB 40H,06H,44H,03H,40H,03H,33H,03H

81B5 39034403 DB 39H,03H,44H,03H,40H,03H,39H,03H
81BD 40033303 DB 40H,03H,33H,03H,39H,03H,00H,00H

81C5 44034003 DATA2: DB 44H,03H,40H,03H,33H,03H,39H,03H

81CD 44032003 DB 44H,03H,40H,03H,33H,03H,39H,03H
81D5 44034003 DB 44H,03H,40H,03H,33H,03H,39H,03H
81DD 0000 DB 00H,00H

81DF C0034003 DATA3: DB 0C0H, 03H,40H,03H,33H,03H

81E5 39034403 DB 39H,03H,44H,03H,40H,03H,98H,03H
81ED 39034403 DB 39H,03H,44H,03H,40H,03H,33H,03H
81F5 3903C003 DB 39H,03H,0C0H,03H,40H,03H,33H,03H
81FD 39034403 DB 39H,03H,44H,03H,40H,03H,98H,03H
8205 33033003 DB 33H,03H,30H,03H,2AH,03H,26H,033,
820D 24038003 DB 24H,03H,80H,03H,1CH,06H,20H,03H
8215 24032603 DB 24H,03H,26H,03H,0ACH,03H,2AH,02H
321D FF012A01 DB 0FFH,01H,2AH,01H,26H,01H,2AH,02H

133
8225 2D032A03 DB 2DH,03H,2AH,03H,80H,03H,1CH,06H
822D 20032403 DB 20H,03H,24H,03H,26H,03H,80H,03H
8235 2A012601 DB 2AH,01H,26H,01H,2AH,01H,2AH,03H
823D 2A032603 DB 2AH,03H,26H,03H,39H,03H,0C0H,03H
8245 44033303 DB 44H,03H,33H,03H,39H,03H,44H,03H
824D 40039803 DB 40H,03H,98H,03H,39H,03H,44H,03H
8255 40033303 DB 40H,03H,33H,03H,39H,03H,0C0H,03H
825D 40033303 DB 40H,03H,33H,03H,39H,03H,44H,03H
8265 40039803 DB 40H,03H,98H,03H,33H,03H,30H,03H
826D 2A032603 DB 2AH,03H,26H,03H,24H,03H,80H,03H
8275 1C062003 DB 1CH,06H,20H,03H,24H,03H,26H,03H
827D AC032A02 DB 0ACH,03H,2AH,01H,2DH,03H,0AH,01H
8285 26012A01 DB 26H,01H,2AH,01H,2DH,03H,2AH,01H
820D 80031C06 DB 80H,03H,1CH,06H,20H,03H,24H,03H
8295 26038003 DB 26H,03H,80H,03H,26H,03H,2AH,03H

82A5 F0022402 DATA4: DB 0F0H,02H,24H,02H,26H,02H,28H,03H

82AD 26032003 DB 26H,03H,20H,03H,24H,03H,0E4H,03H
82B5 24032603 DB 24H,03H,26H,03H,28H,03H,26H,03H
82BC 1C03CC02 DB 1CH,03H,0CCH,02H,1CH,02H,20H,02H
82C5 22032003 DB 22H,02H,20H,03H,19H,03H,1CH,03H
82CD C0031C03 DB 0C0H,03H,1CH,03H,20H,03H,22H,03H
82D5 20031803 DB 20H,03H,18H,03H,90H,03H,1CH,03H
82DD 20032403 DB 20H,03H,24H,03H,26H,03H,2AH,03H
82E5 80033303 DB 80H,03H,33H,03H,39H,03H,40H,03H
82ED 48034C03 DB 48H,03H,4CH,03H,56H,03H,60H,03H
82F5 66035603 DB 66H,03H,56H,03H,39H,03H,40H,03H
82FD C0034003 DB 0C0H,03H,4CH,03H,39H,03H,33H,03H
8303 30032A03 DB 30H,03H,2AH,03H,44H,02H,24H,02H
830D 26022803 DB 26H,02H,28H,03H,26H,03H,20H,03H
8315 24037203 DB 24H,03H,72H,03H,24H,03H,26H,03H
831D 28032603 DB 28H,03H,26H,03H,1CH,03H,66H,02H
8325 1C022002 DB 1CH,02H,20H,02H,22H,03H,20H,03H
832D 19031C03 DB 19H,03H,1CH,03H,60H,03H,1CH,03H
8335 20032203 DB 20H,03H,22H,03H,20H,03H,13H,03H
833D 90031803 DB 90H,03H,18H,03H,19H,03H,1CH,03H
8345 20032403 DB 20H,03H,24H,03H,80H,03H,2AH,03H,
834D 30033303 DB 30H,03H,33H,03H,39H,03H,4CH,03H
8355 3C033303 DB 3CH,03H,33H,03H,39H,03H,4CH,03H
835D 48036603 DB 48H,03H,66H,03H,24H,03H,80H,03H

134
8365 0000 DB 00H,00H

8367 80032009 DATA5: DB 80H,03H,40H,09H,56H,06H,40H,0CH

836F 5006C003 DB 50H,06H,0C0H,03H,40H,09H,4CH,06H
8377 80032608 DB 80H,03H,26H,08H,0FFH,01H,26H,03H
837F AC032609 DB 0ACH,03H,26H,09H,39H,06H,80H,03H
8387 26093306 DB 26H,09H,33H,06H,0C0H,03H,2AH,09H
838F 30039802 DB 30H,03H,98H,02H,33H,04H,2AH,04H
8397 30043904 DB 30H,04H,39H,04H,0CCH,03H,40H,09H
839F 56068003 DB 56H,06H,80H,03H,40H,09H,50H,06H
83A7 C0034009 DB 0C0H,03H,40H,09H,4CH,06H,06H,0D8H,03H
83AF 260FCC03 DB 26H,0FH,0CCH,03H,20H,03H,39H,06H
83B7 3303CC03 DB 33H,06H,0CCH,03H,20H,03H,39H,06H
83BF 22069803 DB 22H,06H,98H,03H,3CH,03H,24H,06H
83CF CC034009 DB 0CCH,03H,40H,09H,56H,06H,80H,03H
83D7 40095006 DB 40H,09H,50H,06H,0C0H,03H,40H,09H
83DF 4C068003 DB 4CH,06H,80H,03H,26H,08H,0FFH,01H
83E7 2606AC03 DB 26H,06H,0ACH,03H,26H,09H,39H,06H
83EF 80032609 DB 80H,03H,26H,09H,33H,06H,0C0H,03H
83F7 2A033006 DB 2AH,03H,30H,06H,33H,06H,98H,03H
83FF 2A033009 DB 2AH,03H,30H,09H,39H,03H,0CCH,03H
8407040095606 DB 40H,09H,56H,06H,80H,03H,40H,09H
840F 5006D803 DB 50H,06H,0D8H,03H,40H,09H,4CH,06H
8417 E403260F DB 0E4H,03H,26H,0FH,0ACH,03H,26H,09H
841F 36062A0C DB 36H,06H,2AH,0CH,3CH,06H,0C0H,03H
8427 2A032004 DB 2AH,03H,40H,06H,5DH,06H,26H,06H
842F 4A062006 DB 2AH,06H,20H,06H,00H,00H
8435 40033903 DB 40H,03H,39H,03H,40H,03H,39H,03H
843D 40033903 DB 40H,03H,39H,03H,00H,00H
8443 FF120000 DB 0FFH,12H,00H,00H

8447 5A0A5002 DATA10: DB 5AH,0AH,50H,02H,44H,02H,3CH,02H

844F 36042D02 DB 36H,04H,2DH,02H,2DH,08H,2DH,02H
8457 28042202 DB 28H,04H,22H,02H,28H,04H,2DH,04H
845F 33022D10 DB 33H,04H,36H,02H,36H,06H

8465 36043602 DATA11: DB 36H,04H,36H,02H,36H,06H

846B 36043604 DB 36H,04H,36H,04H,28H,02H,28H,02H
8473 36123C04 DB 36H,02H,3CH,04H,44H,02H,44H,04H
847B 44044402 DB 44H,04H,44H,02H,3CH,02H,36H,02H

135
8483 3C120000 DB 2CH,12H,0,0

8487 5A0A5002 DATA12: DB 5AH,0AH,50H,02H,44H,02H,2CH,02H

848F 36042D02 DB 36H,04H,2DH,02H,2DH,08H,2DH,02H
8497 28042202 DB 28H,04H,22H,02H,28H,04H
849D 2D023302 DB 2DH,02H,33H,02H,2DH,0CH
84AC 0000 DB 0,0
84A5 36043602 DATA13: DB 36H,04H,36H,02H,36H,04H,36H,02H
84AD 36023602 DB 36H,02H,36H,02H,3CH,04H,36H,02H
84B5 3C0A0000 DB 3CH,0AH,0,0

84B9 FF085002 DATA14: DB 0FFH,08H,50H,02H,44H,02H,44H,02H

84C1 3C024410 DB 3CH,02H,44H,10H,48H,10H,0,0

84C9 36043604 DATA15: DB 36H,04H,36H,04H,36H,04H,36H,04H

84D1 36142802 DB 36H,04H,28H,02H,28H,02H
84D7 36023C04 DB 36H,02H,3CH,04H,44H,02H,44H,04H
84DF 44044402 DB 44H,04H,44H,02H,3CH,02H,36H,02H
84E7 2C120000 DB 3CH,12H,0,0

84EB FF045004 DATA16: DB 0FFH,04H,50H,04H,44H,02H,48H,04H

84F3 3C023C04 DB 3CH,02H,3CH,04H,44H,14H,0FFH,06H
84FB 44022804 DB 44H,02H,28H,04H,28H,04H,24H,04H
8803 22042404 DB 22H,04H,24H,04H,28H,02H,2AH,08H
850B 36022D04 DB 36H,02H,2DH,04H,2DH,02H,2DH,04H,
8513 36043C02 DB 36H,04H,3CH,02H,44H,06H
8519 50024402 DB 50H,02H,44H,02H,36H,04H,3CH,02H
8521 3C12FF04 DB 3CH,12H,0FFH,04H,50H,02H,44H,02H
8529 36043C02 DB 36H,04H,3CH,02H,3CH,06H,44H,02H
8531 2D1FFF02 DB 2DH,1FH,0FFH,02H
8535 36083602 DB 36H,08H,36H,02H,36H,02H,44H,02H
853D 2D0EFF02 DB 2DH,0EH,0FFH,02H,44H,02H,44H,04H
8545 44043604 DB 44H,04H,36H,04H,44H,02H,5AH,06H
854D FF025A02 DB 0FFH,02H,5AH,02H,50H,04H,44H,04H
8555 44044404 DB 44H,04H,44H,04H,44H,02H,5AH,06H
855D FF065002 DB 0FFH,06H,50H,02H,36H,04H,2DH,02H
8565 36043C04 DB 36H,08H,36H,02H,36H,02H,44H,02H
856D 36083602 DB 36H,08H,36H,02H,36H,02H,44H,02H
8575 2D0EFF02 DB 2DH,0EH,0FFH,02H,36H,02H
857B 22041E02 DB 22H,04H,1EH,02H,1EH,04H,22H,04H

136
8583 AE022D10 DB 1EH,02H,2DH,10H

8587 22042202 DATA17: DB 22H,04H,22H,02H,1EH,04H,22H,04H

854F 28062D08 DB 28H,06H,2DH,08H,36H,02H,36H,02H
8597 33042D04 DB 33H,04H,2DH,04H,0FFH,04H
859D 3C023C02 DB 3CH,02H,3CH,02H,44H,14H
85A3 3C023C02 DB 00H,00H

0000 END

Chapter 20. Interrupt Test

1. Clock Program (8253, INTR, NMI)

(a) Source file name : 80INTR.ASM
(b) Hexa file name : 80INTR.HEX
(c) Address : 5140H
(d) Action : Input the system clock of 2.4576MHz to COUNT0 and divide
them into 24576, and then input them to COUNT1. Generate 1
signal per 1 second by dividing them into 100 and interrupt
the CPR. Whenever the CPR accepts an interrupt, this
program increment by 1 second. After executes the program,
if input the current time as 6 digit of hours, minutes, and
seconds, the clock activates. While working, push the NMI
key to reset the second.

0048 COUNT0 EQU 48H

0049 COUNT1 EQU 49H
004A COUNT2 EQU 4AH
004B CSR EQU 4BH

FF04 INT_BUFF EQU 0FF04H

FF01 NMI_BUFF EQU 0FF01H

0048 LCDCLR EQU 0048H

0060 STRINGL EQU 0060H
0058 LINE2 EQU 0058H
0098 SCAN EQU 0098H

8000 ORG 8000H

137
8000 3100FF START: LD SP,0FF00H
8003 ED56 IM 1
8005 F3 DI

8006 CD4800 CALL LCDCLR

8009 CD6000 CALL STRINGL
800C 494E5445 DB 'INTERRUPT TEST !$'
801D CD5800 CALL LINE2
8020 CD6000 CALL STRINGL
8023 20444950 DB 'DIP1 = NO. 5 ON$'
8033 CDCC80 CALL TIMER
8036 CDCC80 CALL TIMER

8039 3E34 I8253: LD A,00110100B ;COUNT0, MSB/LSB LOAD,

;MODE3
803B D34B OUT (CSR),A
803D 3E54 LD A,01010100B ;COUNT1, LSB LOAD, MODE3
803F D34B OUT (CSR),A

8041 110060 LD DE,24576 ;set the division ratio(COUNT0)

8044 7B LD A,E
8045 D348 OUT (COUNT0),A
8047 7A LD A,D
8048 D348 OUT (COUNT0),A

804A 3E64 LD A,100 ;set the division ratio(COUNT1)

804C D349 OUT (COUNT1),A

804E 216381 LD HL,INTR

8051 2204FF LD (INT_BUFF),HL

8054 216F81 LD HL,NMI

8057 2201FF LD (NMI_BUFF),HL

805A CD4800 CALL LCDCLR

805D CD6000 CALL STRINGL

8060 50726573 DB 'Press Key (0~9)!$'

8071 AF XOR A ;clear the data of hours. minutes,
;seconds

138
8072 327781 LD (HOUR),A
8075 357681 LD (MINUTE),A
8078 327581 LD (SECOND),A
807B CD1E81 CALL DISPLAY ;output to the LCD

807E 217781 LD HL,HOUR

8081 0603 LD B,3 ;set the input limit(only 0～2
;possible to input)

8083 CDD580 CALL SCAN1

8086 217781 LD HL,HOUR
8089 060A LD B,0AH ;the acceptable input(0～9)
808B CDE480 CALL SCAN2

808E 217681 LD HL,MINUTE

8091 060A LD B,6 ;the acceptable input(0～5)
8093 CDD580 CALL SCAN1
8096 217681 LD HL,MINUTE
8099 060A LD B,0AH ;the acceptable input(0～9)
809B CDE480 CALL SCAN2

809E 217581 LD HL,SECOND

80A1 0606 LD B,6 ;the acceptable input(0～5)
80A3 CDD580 CALL SCAN1
80A6 217581 LD HL,SECOND
80A9 060A LD B,0AH ;the acceptable input(0～9)
80AB CDE480 CALL SCAN2

80AE CD4800 STRING: CALL LCDCLR

80B1 CD6000 CALL STRINGL
80B4 20444947 DB 'DIGITA CLOCK !$'
80C5 CD1E81 CALL DISPLAY
80C8 AF XOR A
80C9 FB EI ;acknowledge the interrupt
80CA 18FE JR $ ;wait for the interrupt signal

80CC 21FFCF TIMER: LD HL,0CFFFH

80CF 2B TIME: DEC HL
80D0 7C LD A,H
80D1 B5 OR L

139
80D2 20FB JR NZ,TIME
80D4 C9 RET

80D5 CD9800 SCAN1: CALL SCAN ;keypad input

80D8 B8 CP B ;is that the accepted data?
80D9 30FA JR NC,SCAN1 ;jump to SCAN1 if not
80DB 07 RLCA ;exchange the MSB and LSB data
80DC 07 RLCA
80DD 07 RLCA
80DE 07 RLCA

80DF 77 LD (HL),A ;store the data

80E0 CD1E81 CALL DISPLAY ;output to the LCD
80E3 C9 RET

80E4 CD9800 SCAN2: CALL SCAN

80E7 B8 CP B
80E8 30FA JR NC,SCAN2
80EA B6 OR (HL) ;add the MSB and LSB bit
80EB 77 LD (HL),A ;store the data
80EC CD1E81 CALL DISPLAY ;output to the LCD
80EF C9 RET

80F0 217581 COUNT: LD HL,SECOND ;data pointing address

80F3 7E LD A,(HL) ;transmit the data to A
80F4 C601 ADD A,1 ;add '1'
80F6 27 DAA ;decimal conversion
80F7 77 LD (HL),A ;store the data
80F8 FE60 CP 60H ;is it the maximum value?
80FA C21D81 JP NZ,COUNT_END ;finish counting if not
80FD 3600 LD (HL),0 ;clear the second data

80FF 217681 LD HL,MINUTE

8102 7E LD A,(HL)
8103 C601 ADD A,1
8105 27 DAA
8126 77 LD (HL),A
8107 FE60 CP 60H
8109 C21D81 JP NZ,COUNT_END
810C 3600 LD (HL),0

140
810E 217781 LD HL,HOUR

8111 7E LD A,(HL)
8112 C601 ADD A,1
8114 27 DAA
8115 77 LD (HL),A
8116 FE24 CP 24H
8118 C21D81 JP NZ,COUNT_END
811B 3600 LD (HL),0
811D C9 COUNT_END: RET

811E 214181 DISPLAY: LD HL,DATA+2 ;the address of the conversion

;data
8121 117781 LD DE,HOUR ;the data address
8124 CD5181 CALL DISP ;store after the conversion to
;ASCII code
8127 214681 LD HL,DATA+7
812A 117681 LD DE,MINUTE
812D CD5181 CALL DISP
8130 214B81 LD HL,DATA+2
8133 117581 LD DE,SECOND
8136 CD5181 CALL DISP
8139 CD5800 CALL LINE2
813C CD6000 CALL STRINGL
813F 20203030 DATA: DB ' 00: 00: 00 $'
8150 C9 RET

8151 1A DISP: LD A,(DE) ;transmit the data to A

8158 E6F0 AND A,0F0H ;clear the LSB 4 bit
8154 07 RLCA
8155 07 RLCA
8156 07 RLCA
8157 07 RLCA

8158 C630 ADD A,30H ;make the ASCII code by adding

;30H
815A 77 LD (HL),A ;store the data
815B 23 INC HL ;increment the data storing
;address

141
815C 1A LD A,(DE) ;transmit the data to A
815D E60F AND A,0FH ;store the data
815F C630 ADD A,30H ;make the ASCII code by adding
;30H
8161 77 LD (HL),A ;store the data
8162 C9 RET

8163 CDF080 INTR: CALL COUNT ;add 1 second to the hour data
8166 CD1E81 CALL DISPLAY ;output to the LCD
8169 CDCC80 CALL TIMER ;time delay(because the interrupt
;signal is applied every 1Hz, the
;interrupt is acknowledged 0.5
;seconds later)
816C FB EI ;acknowledge the interrupt
816D ED4D RETI
814F AF NMI: XOR A ;clear the second data
8170 327581 LD (SECOND),A
8173 ED45 RETN

8175 SECOND: DS 1 ;the area for storing the second

;data
8176 MINUTE: DS 1 ;the area for storing the minute
;data
8177 HOUR: DS 1 ;the area for storing the hour data

0000 END

142
Chapter 21. ROM Writer

1. Usage
(a) Blank Check : This is the function that checks if ROM is empty or not before writing ROM.
To drive ROM Writer, type on the keyboard as follows.

MTS-Z80A > W↵
What do you want?
1. WRITE
2. READ
3.BLANK CHECK
4.COMPARE
Select the number or Press <ESC> to cancel 3
:Select BLANK CHECK by typing 3 as input

Which type do you want?

1. 2764
2. 27128
3. 27256
Select the number or Press <ESC> to cancel 1
:Select ROM TYPE which is inserted into the TEXTOOL
1FFF Blank OK!!

(b) ROM Read : Store the result of reading ROM into RAM. Store them from 8000H and the
end of the data is obtained by adding the last address of ROM to 8000H. 27256 is read two
times because RAM is bigger than to read. If in the last part(7E00H-7FFFH) the data is
unnecessary, you can perform READ, WRITE AND COMPARE at one time from 27256 by
inserting '5' on the prompt of 'ROM TYPE' and selecting 27256(0000H-7E00H).

ROM TYPE ROM ADDRESS RAM ADDRESS

2764 0000H～1FFFH 8000H～9FFFH
27128 0000H～3FFFH 8000H～BFFFH
27256(0000H～3FFFH) 0000H～3FFFH 8000H～BFFFH
27256(4000H～7FFFH) 4000H～7FFFH 8000H～BFFFH
27256(0000H～7E00H) 0000H～7E00H 8000H～FE00H

143
MTS-Z80A > W↵
What do you want?
1. WRITE
2. READ
3. BLANK CHECK
4. COMPARE
Select the number or Press <ESC> to cancel 2
:Select ROM READ by typing 2 as input

Which type do you want?

1. 2764
2. 27128
3. 27256 (0000H - 3FFFH)
4. 27256 (4000H - 7FFFH)
5. 27256 (0000H - 7E00H)
Select the number or press <ESC> to cancel 1
: Select ROM TYPE which is inserted into the TEXTOOL
1FFF Reading Complete!
:After READ, it is automatically running COMPARE
1FFF Compare OK!!

(c) Compare : Compare the data of ROM and the data stored in RAM.
MTS-Z80A > W↵
What do you want?
1. WRITE
2. READ
3. BLANK CHECK
4. COMPARE
Select the number or Press <ESC> to cancel 4
:Select COMPARE by typing 4 as input

Which type do you want?

1. 2764
2. 27128
3. 27256 (0000H - 3FFFH)
4. 27256 (4000H - 7FFFH)
5. 27256 (0000H - 7E00H)
Select the number or Press <ESC> to cancel 1
: Select the ROM TYPE which is inserted into the TEXTOOL
1FFF Compare OK!!

144
(d) Write : Write the data stored in RAM to ROM. The address of RAM is the same as that of
ROM.
MTS-Z80A > W↵
What do you want?
1. WRITE
2. READ
3. BLANK CHECK
4. COMPARE
Select the number or Press <ESC> to cancel 1
: Select WRITE by typing 1 as input

Which type do you want?

1. 2764
2. 27128
3. 27256 (0000H - 3FFFH)
4. 27256 (4000H - 7FFFH)
5. 27256 (0000H - 7E00H)
Select the number or Press <ESC> to cancel 1
:Select the ROM TYPE which is inserted into the TEXTOOL

Which type do you want?

1. VPP =12.75V
2. VPP =21V
Select the number of Press <ESC> to cancel 1
:Select the ROM VPP voltage. The voltage of the 27Cxx type is 12.75V. For more information
of setting consult the manufacturer of the ROM.
1FFF FF

2. Editing and changing a File

To write ROM, programming is different from others In general, ROM is set 0000H which
depends on the hardware of a target board If the program with the starting address '0000H' is
transmitted to the training kit MTS-Z80A, it is impossible to transmit and write ROM. When you
make a file, change 'ORG 8000H' into 'ORG 0000H' and then write the program. Assemble the
program by the assembler. Make the file possible to transmit it to 8000H by using
'HEXOBJ.EXE' and 'BIN2HEX.EXE' because this file cannot be transmitted. For example, if
the file name is 'LIGHT.ASM', by using 'Z80.COM' input first as follows.

145
A:/>HEXOBJ
ATOM Hex to Converter V2.0
(c)Copyright 1986 By ATOM Electronic Co., Ltd.

HEX file name : LIGHT.HEX↵

BIN file name : LIGHT.BIN↵
HEX file format <I>INTEL /<M>MOTOROLA/<T>TEKTRONICS : I
Wait...
INTEL Hex to Binary Converter
Convert Complete

A:/>BIN2HEX
Converter from BIN to INTEL HEX file V1.0 made by Sigma Intelligence
This program is the Public ware. Anyone can use this HAK LIM Micro Instrument

Input Bin file name : LIGHT.BIN↵

Input start address : 8000↵

A:/>
The file has been generated as above. We skip the method of transmission and ROM
WRITE because it's already explained. After WRITE, the target board is required. In order to
use MTS-Z80A as a target board, unscrew the bolts and remove the plastic board. Then for
2764 or 27128 ROM, insert ROM into the place of USER ROM and move right the short bar of
the lower part of ROM and apply the power. The important caution is that you shouldn't use
any System call while writing a program.

146
Chapter 22. System Call
SYSTEM CALL is the group of the useful subroutines of the Monitor program to give users
Keep those system calls in mind for the best use in making programs.
For the first time, it is recommended that you should use the system calls. When you are
accustomed to using that, try to control them in your own program. It is the best way to
understand the processor in depth. To do so, each routine is well-summarized for you, so try to
use the below table. In ROM, single steps step. Like INRS of SCAN, input type system calls
are required to store the input data to A register, so AF register cannot be protected. For other
system call. however, all the register can be protected completely.

No. Name Method Description

It is used to finish the user program and all the registers
1 RESTART RST 08H
are stored
Converts HL register value to ASCII codes, and then
2 OUTHL RST 10H
outputs the result to the monitor
Converts A register value to ASCII codes, and then
outputs the result to the monitor.
3 OUTA RST 18H
For example, when A register has '30H','30' is displayed
on the monitor.
Outputs 1 character to the PC. Then A register should
4 OTURS RST 20H
have the ASCII code of the character to output
Inputs 1 character from the PC.(the input Character is
5 INRS RST 28H
not displayed on the monitor)
Outputs a string to the monitor. '$' should be in the ecd
6 STRING CALL 0040H
of the string.
Deletes all the data on the LCD and sends the cursor to
7 ALLCLR CALL 0048H
HOME
Sends the cursor on the LCD to HOME. Then the
8 LINE1 CALL 0050H
displayed data will not be deleted
Sends the cursor on the LCD to the first location of the
9 LINE2 CALL 0058H
next line.
Outputs a string to the LCD. '$' should be in the end of
10 STRINGL CALL 0060H
the string.
Converts the HL register value into ASCII code and
11 LOUTHL CALL 0070H
outputs them to the LCD
Converts the data address pointed by the HL register
12 LOUT_HL CALL 0078H
into ASCII code and outputs them to the LCD
Converts the A register value into ASCII code and
13 LOUTA CALL 0080H
outputs them to the LCD
14 OUTL CALL 0088H Outputs A register value to the LCD
LCDCON Move the cursor to the location A register points to
15 CALL 0090H
T
16 SCAN CALL 0098H Gets one input data from the Keypad of MTS-Z80A

147
1. RST 08H (Program End)
We skip explaining about that because you need to understand the Monitor program
entirely.

2. RST 10H (OUTHL)

This call converts HL register value to ASCII code and outputs it. Through RS-232C
communication, it outputs the data to the monitor, so the data in ASCII code should be sent in
order to see the required data on the monitor.

OUTHL: PUSH AF ;store AF register into the stack

LD A,H ;transmit H register to A register
CALL OUTA ;convert the A register value to ASCII code and
;outputs them to the monitor(See OUTA)
LD A,L ;transmit L register to A register
CALL OUTA ;convert the A register value to ASCII code and
;outputs them to the monitor
POP AF ;retrieve the AF register value from the stack
RET ;return to the main routine

3.RST 18H (OUTA)

This call converts A register value to ASCII code and outputs it.

OUTA: PUSH AF ;store AF register into the stack

OUTA1: PUSH AF ;store AF register into the stack
AND 0F0H ;clear the 4 bit of the LSB
RRA ;exchange the MSB and the LSB of A register
RRA
RRA
RRA
CALL BI2AS ;convert it to ASCII code
CALL OUTRS ;output ot the monitor(See OUTRS)
POP AF ;retrieve the af register value from the stack
AND 0FH ;clear the 4 bit of the MSB
CALL OUTRS ;output to the monitor
POP AF ;retrieve the AF register value from the stack
RET ;return to the main routine

BI2AS: CP 10 ;is that a number?

JR C,NAS1 ;jump to NAS1 if it's a number(if the carry occurs
;compared to 10, it means the number less than

148
 ;10(from 0 to 9))
ADD A,7 ;Not a number. add 7 to it. (when A register has '0AH',
;the ASCII code of 'A' is 41H.
;it results 7 from the calculation '41H-30H-0AH = 7'
NAS1: ADD A,'0' ;add 30H. (the character in the quotation mark is
;assembled in ASCII code by the assembler, and the
;ASCII code of '0' is 30H)
RET ;return to the main routine

4. RST 20H (OUTRS)

This call outputs A register value to the monitor. ASCII code should be in A register.

OUTRS: PUSH AF ;store AF register into the stack

OUTRS1: IN A,(41H) ;read the status register of the serial
;communication IC(8251)
BIT 0,A ;it shows if it is possible for bit 0 of the status register to
;transmit or not. If '1', it's possible to transmit.
JR Z,OUTRS ;jump to OUTRS1 if impossible to transmit
POP AF ;retrieve the AF register value from the stack
OUT (40H),A ;data output
RET

5. RST 28H (INRS)

This call gets 1 character input from the PC. The input data is not displayed on the monitor.
In order to display it, it can be displayed on the monitor. In order to display it, it can be
displayed with 'OUTRS'.

INRS: IN A,(41H) ;read the status register

BIT 1,A ;the bit 1 of the status register shows if there is the
;received data or not. If '1', it means the received data
;exists.
JR Z,INRS ;jump to INRS if there is no received data
IN A,(40H) ;read the received data
RET

6.CALL 0040H (STRING)

This call outputs a string to the monitor of the PC. '$' should be in the end of the string. You
should observe carefully the change of the stack because the following program are controlled

149
by the stack.

STRING: EX (SP),HL ;exchange the return address and the data of HL

;register. Namely, although execute RET to the main
;routine.
PUSH AF ;store AF register into the stack
STRING1: LD A,(HL) ;transmit the data of the address to which HL register
;points, to A register.(The first HL instruction, so its
;address will be the starting address of the output.
CP '$' ;is it '$'?
JP Z,STRING2 ;jump to STRING2 if '$"(the end of the data)
CALL OUTRS ;output the data to the monitor.
INC HL ;increment the data point address by 1
JR STRING1 ;jump to STRING1
STRING2: POP AF ;retrieve the AF register value from the stack
INC HL ;increment the data pointing address by 1, and change
;it to the next address in which '$' locates.
EX (SP),HL ;exchange the HL register value in the stack and the
;current HL register value.(store the return address into
;the stack)
RET ;return to the main routine.

7. CALL 0048H (ALLCLR)

This call deletes all the data on the LCD(filling the LCD with '20H') and sends the cursor to
HOME.

ALLCLR: PUSH AF
LD A,1 ;put 1 into A register.(See the LCD control to know what
;'1' means)
CALL BUSY ;check if the LCD can accept an instruction or not
OUT (08H),A ;output the control code
POP AF
RET
BUSY: PUSH AF
BUSY1: IN A,(08H) ;read BUSY FLAG. (using only 7-bit)
BIT 7,A ;check BUSY FLAG
JR NZ,BUSY1 ;jump to BUSY1 if the LCD is acting internally (can write
;an instruction if BUSY FLAG is '0')
POP AF
RET

150
8.CALL 0050H (LINE1)
This call sends the cursor to HOME(the first column of the previous line).

LINE1: PUSH AF
LD A,2 ;put 2 into A register
CALL BUSY ;check if the LCD can accept an instruction or not
OUT (08H),A ;output the control code
POP AF
RET

9. CALL 0058H (LINE2)

This call sends the cursor to the first column of the next line.

LINE2: PUSH AF
LD A,0C0H ;put 0C0H into A register
CALL BUSY ;check if the LCD can accept an instruction or not
OUT (08H),A ;output the control code
POP AF
RET

10. CALL 0060H (STRINGL)

This call outputs a string to the LCD. The ASCII code of '$' should be in the end of the
string. The call is the same as STRING, so skip the explanation.

STRINGL: EX (SP),HL
PUSH AF
STRINGL1: LD A,(HL)
CP '$'
JR Z,STRINGL2
CALL OUTL
INC HL
JR STRINGL1
STRINGL2: POP AF
INC HL
EX (SP),HL
RET

151
11.CALL 0070H (LOUTHL)
This call converts a HL register value to the ASCII code and outputs it. See OUTHL

LOUTHL: PUSH AF
LD A,H
CALL LOUTA
LD A,L
CALL LOUTA
POP AF
RET

12. CALL 0078H (LOUT_HL)

This call converts the data of the address pointed by HL register to the ASCII code and
outputs it to the LCD.

LOUT_HL: PUSH AF
LD A,(HL) ;transmit the data of the address to which HL register
;points, to A register.
JP LOUTA1 ;jump to LOUTA1(See LOUTA)

13. CALL 0080H (LOUTA)

LOUTA: PUSH AF
LOUTA1: PUSH AF
AND 0F0H
RRA
RRA
RRA
RRA
CALL BI2AS
CALL OUTL
POP AF
AND 0FH
CALL BI2AS
CALL OUTL
POP AF
RET

152
14. CALL 0088H (OUTL)
This call outputs an A register value to the LCD.

OUTL: CALL BUSY ;check if the LCD can accept an instruction or not
OUT (09H),A ;output the data(write the character data onto the LCD)
RET

15. CALL 0090H (LCDCONT)

This call moves the cursor of the LCD to the location to which A register points. In LINE2,
the output of '0C0H' to the LCD is supposed to change bit 7 to bit 1 in the control code. Thes
routine is for the output to the LCD, so all the control like ALLCLR, LINE1, LINE2 etc can be
controlled according to an A register value.

LCD_OUT: CALL BUSY ;check if the LCD can accept an instruction or not
OUT (08H),A ;output the data(write the character data onto the LCD)
RET

Code
Instruction Description
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
DD RAM DD RAM sets the address. After setting,
0 0 1 Address
Address Set the data is the data of DD RAM

Address of the LCD

Upper 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
Lower 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH

153
16. CALL 0098H (SCAN)
This call gets 1 data from the Keypad input of MTS-Z80A. Then the data which are stored
in A register is the internal code of the Keypad.

SCAN: IN A,(10H) ;input the key status

BIT 7,A ;is any key pushed?
JR NZ,SCAN ;jump to SCAN if not
AND 1FH ;clear the bit except the key code
OUT (18H),A ;clear the key buffer after the key input, the buffer
;should be empty. Otherwise, it acts as the key is still
;pushed. Therefore there cannot be any key input.
;An A register value has no meaning.
;According to the signal which outputs to 18H.
;A register will be cleared.
RET

Key Internal code Key Internal code Key Internal code

0 00H 8 08H INC 10H
1 01H 9 09H DEC 11H
2 02H A 0AH ADDR 12H
3 03H B 0BH GO 13H
4 04H C 0CH REG 17H
5 05H D 0DH INS 14H
6 06H E 0EH DEL 15H
7 07H F 0FH STEP 16H

154
Chapter 23. Instruction Set

====== Terminology ======

A : Accumulator SP : Stack Pointer
B : Register B R : Refresh Register
C : Register C I : Interrupt Register
D : Register D ss : Register (BC, DE, HL, SP)
E : Register E r : Register (B, C, D, E, H, L)
H : Register H b : Bit Number
L : Register L ∧ : AND
F : Flag Register ∨ : OR
Reg : Register ⊕ : Exclusive OR(XOR)
BC : Register Pair BC n : 8 bit (hexadecimal)
DE : Register Pair DE nn : 16 bit (hexadecimal)
HL : Register Pair HL Cy : Carry Flag
IX : Index Register IX d : Displayment
IY : Index Register IY () : the Address data which the value of
PC : Program Counter the bracket points to

※ According to the instruction table, rrr, bbb etc are the same as follows. When you do the
hand assembling, you can convert them into the machine code by consulting the table. Take
the example.

Flag OP code The number Machine

Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte Cycle
LD r1,r2 r1←r2 * * * * * * 01 r1 r2 1 1 4

Ex) Let's convert LD B, D into the machine code. r1 is B register, so it is '000' in machine code.
r2 is D register, so it is '010'. Converting them into the machine codes, it becomes '01000010B',
and it is also '42H' in hexadecimal. Namely, the machine code of 'LD B,D' is '42H'.

The value of rrr (it is also applied to r1 and r2)

Register The value of rrr Description
B 000
C 001
D 010
E 011
H 100
L 101
A 111
155
 The value of ss (1)
Register The value of ss Description
BC 00
DE 01
HL 10
SP 11

The value of ss (2)

Register The value of ss Description
BC 00
DE 01 only applied to ADD IX.ss
HL 10 only applied to ADD IY.ss
SP 11

The value of ss (3)

Register The value of ss Description
BC 00
DE 01
HL 10
SP 11 used only for PUSH ss and POP ss

The value of bbb

Register The value of bbb Description
B 000
C 001
D 010
E 011
H 100
L 101
A 111

The value of bbb

Condition The value of rrr Description(expression)
Non Zero 000 NZ
Zero 001 Z
Non Carry 010 NC
Carry 011 C
Parity Odd(P/V=0) 100 PO
Parity Even(P/V=1) 101 PE
Positive(S=0) 110 P
Positive(S=0) 111 M
156
 The value of cc (only for JR cc, e)
Condition The value of ccc Description(expression)
Non Zero 00 NZ
Zero 01 Z
Non Carry 10 NC
Carry 11 C

The value of ttt

n The value of bbb Description
00H 000 only used for RST n
08H 001 only used for RST n
10H 010 only used for RST n
18H 011 only used for RST n
20H 100 only used for RST n
28H 101 only used for RST n
30H 110 only used for RST n
38H 111 only used for RST n
Flag Sign
Sign Description
↕ It varies according to the result of an operation
* do not change
X Don't care
V Overflow
P Parity
0 0
1 1
♠ P/V = 0 if BC = 0
♤ Z = 1 if A = (HL)

157
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte Cycle

ADC A,(HL) A←A+(HL)+Cy ↕ ↕ ↕ V 0 ↕ 10001110 8E 1 2 7

11011101 DD

ADC A,(IX+d) A←A+(IX+d)+Cy ↕ ↕ ↕ V 0 ↕ 10001110 8E 3 5 19

← d →

11011101 FD

ADC A,(IY+d) A←A+(IY+d)+Cy ↕ ↕ ↕ V 0 ↕ 10001110 8E 3 5 19

← d →

ADC A,r A←A+r+Cy ↕ ↕ ↕ V 0 ↕ 10001rrr 1 1 4

11001110 CE
ADC A,n A←A+n+Cy ↕ ↕ ↕ V 0 ↕ 2 2 7
← n →

11101101 ED
ADC HL,ss HL←HL+ss+Cy ↕ ↕ X V 0 ↕ 2 4 15
01ss1010

ADD A,(HL) A←A+(HL) ↕ ↕ ↕ V 0 ↕ 10000110 86 1 2 7

11011101 DD

ADD A,(IX+d) A←A+(IX+d) ↕ ↕ ↕ V 0 ↕ 10000110 86 3 5 19

← d →

11111101 FD

ADD A,(IX+d) A←A+(IY+d) ↕ ↕ ↕ V 0 ↕ 10000110 86 3 5 19

← d →

ADD A,r A←A+r ↕ ↕ ↕ V 0 ↕ 10000rrr 1 1 4

11000110 C6
ADD A,n A←A+n ↕ ↕ ↕ V 0 ↕ 2 2 7
← n →

ADD HL,ss HL←HL+ss * * X * 0 ↕ 00ss1001 1 3 11

11011101 DD
ADD IX,ss IX←IX+ss * * X * 0 ↕ 2 4 15
00ss1001

11111101 FD
ADD IY,ss IY←IY+ss * * X * 0 ↕ 2 4 15
00ss1001

AND (HL) A←A∧(HL) ↕ ↕ ↕ P 0 0 10100110 A6 1 2 7

11011101 DD

AND (IX+d) A←A∧(IX+d) ↕ ↕ ↕ P 0 0 10100110 A6 3 5 19

← n →

11111101 FD

AND (IY+d) A←A∧(IY+d) ↕ ↕ ↕ P 0 0 10100110 A6 3 5 19

← n →

158
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

AND r A←A∧r ↕ ↕ ↕ P 0 0 10100rrr 1 1 4

11100110 E6
AND n A←A∧r ↕ ↕ ↕ P 0 0 2 2 7
← n →

11001011 CB 2 3 12
BIT b,(HL) X ↕ 1 X 0 *
Z←(HL)b 01bbb110 1 1 4

11011101 DD

11001011 CB
BIT b,(IX+d) X ↕ 1 X 0 * 4 5 20
Z←(IX+d)b ← d →

01bbb110

11011101 FD

11001011 CB
BIT b,(IY+d) X ↕ 1 X 0 * 4 5 20
Z←(IY+d)b ← d →

01bbb110

11001011 CB
BIT B,r X ↕ 1 X 0 * 2 2 8
Z←rb 01bbbrrr

11ccc100
3 3 10
CALL cc,nn * * * * * * ← n2 →
cc is true 5 17
← n1 →

(SP-1)←PCH 11001101 CD

CALL nn (SP-2)←PCL * * * * * * ← n2 → 3 5 17

PC←nn ← n1 →

CCF * * X * 0 ↕ 00111111 3F 1 1 4
Cy←Cy

CP (HL) A-(HL) ↕ ↕ ↕ V 1 ↕ 10111110 BE 1 2 7

11011101 DD

CP (IX+d) A-(IX+d) ↕ ↕ ↕ V 1 ↕ 10111110 BE 3 5 19

← d →

11111101 FD

CP (IY+d) A-(IY+d) ↕ ↕ ↕ V 1 ↕ 10111110 BE 3 5 19

← d →

CP r A-r ↕ ↕ ↕ V 1 ↕ 10111rrr 1 1 4

11111110 FE
CP n A-n ↕ ↕ ↕ V 1 ↕ 2 2 7
← n →

159
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte Cycle
11101101 ED
CPD ↕ ♤ ↕ ♠ 1 * 2 4 16
10101001 A9
11101101 ED 2 5 21
CPDR ↕ ♤ ↕ ♠ 1 *
10111000 B8 BC=0 4 16
11101101 ED
CPI ↕ ♤ ↕ ♠ 1 * 2 4 16
10100001 A1
11101101 ED 2 5 21
CPIR ↕ ♤ ↕ ♠ 1 *
10110001 B1 BC=0 4 16

CPL * * 1 * 1 * 00101111 2F 1 1 4
A←A
DAA ↕ ↕ ↕ P * ↕ 00100111 27 1 1 4
DEC (HL) (HL)←(HL)-1 ↕ ↕ ↕ V 1 ↕ 00110101 35 1 3 11
11011101 DD
DEC (IX+d) (IX+d)←(IX+d)-1 ↕ ↕ ↕ V 1 ↕ 00110101 35 3 6 23
← d →
11111101 FD
DEC (IY+d) (IY+d)←(IY+d)-1 ↕ ↕ ↕ V 1 ↕ 00110101 35 3 6 23
← d →
DEC r r←r'-1 ↕ ↕ ↕ V 1 * 00rrr101 1 1 4
DEC ss ss←ss-1 * * * * * * 00ss1011 1 1 6
11011101 DD
DEC IX IX←IX-1 * * * * * * 2 2 10
00101011 2B
11111101 FD
DEC IY IY←IY-1 * * * * * * 2 2 10
00101011 2B
DI IFF1, IFF2←0 * * * * * * 11110011 F3 1 1 4
00010000 10 2 3 13
DJNZ * * * * * *
← e-2 → B=0 2 8
EI IFF1, IFF2←1 * * * * * * 11111011 FB 1 1 4
L↔(SP)
EX (SP),HL * * * * * * 11100011 E3 1 5 19
H↔(SP+1)
IXL↔(SP) 11011101 DD
EX (SP),IX * * * * * * 2 6 23
IXH↔(SP+1) 11100011 E3
IYL↔(SP) 11111101 FD
EX (SP),IY * * * * * * 2 6 23
IYH↔(SP+1) 11100011 E3
EX AF,AF' AF↔AF' * * * * * * 00001000 08 1 1 4
EX DE,HL DE↔HL * * * * * * 11101011 EB 1 1 4
BC↔BC'
EXX DE↔DE' * * * * * * 11011001 D9 1 1 4
HL↔HL'

160
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte Cycle

HALT HALT * * * * * * 01110110 76 1 1 4

11101101 ED
IM 0 INT MODE 0 * * * * * * 2 2 8
01000110 46

11101101 ED
IM 1 INT MODE 1 * * * * * * 2 2 8
01011110 56

11101101 ED
IM 2 INT MODE 2 * * * * * * 2 2 8
01011110 5E

11011011 DB
IN A,(n) A←(n) * * * * * * 2 3 11
← n →

11101101 ED
IN r,(c) r←(c) ↕ ↕ 0 * 0 * 2 3 12
01rrr000

INC (HL) (HL)←(HL)+1 ↕ ↕ ↕ V 0 * 00110100 34 1 3 11

11011101 DD

INC (IX+d) (IX+d)←(IX+d)+1 ↕ ↕ ↕ V 0 * 00110100 34 3 6 23

← d →

11111101 FD

INC (IY+d) (IY+d)←(IY+d)+1 ↕ ↕ ↕ V 0 * 00110100 34 3 6 23

← d →

INC r r←r'+1 ↕ ↕ ↕ V 0 * 00rrr100 1 1 4

INC ss ss←ss+1 * * * * * * 00ss0011 1 1 6

11011101 DD
INC IX IX←IX+1 * * * * * * 2 2 10
00100011 23

11111101 FD
INC IY IY←IY+1 * * * * * * 2 2 10
00100011 23

(HL)←(C)
11101101 ED
IND B←B-1, X ↕ X X 1 * 2 4 16
10101010 AA
HL←HL-1

IND 11101101 ED 2 5 21
INDR X 1 X X 1 *
Repeat until B=0 10111010 BA B=0 4 16

(HL)←(C)
11101101 ED
INI B←B-1 X ↕ X X 1 * 2 4 16
10100010 A2
HL←HL+1

INI 11101101 ED 2 5 21
INIR X 1 X X 1 *
Repeat until B=0 10110010 B2 B=0 4 16

161
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11000011 C3

JP nn pc←nln2 * * * * * * ← n2 → 3 3 10

← n1 →

JP (HL) PC←HL * * * * * * 11101001 E9 1 1 4

11011101 DD
JP (IX) PC←IX * * * * * * 2 2 8
11101001 E9

11111101 FD
JP (IY) PC←IY * * * * * * 2 2 8
11101001 E9

11ccc010
If condition cc is true
JP cc,nn * * * * * * ← n2 → 3 3 10
PC←nln2
← n1 →

If condition cc is true 001cc000 2 2 7

JR cc,e * * * * * *
PC←PC+e ← e-2 → cc is true 3 12

00011000 18
JR e PC←PC+e * * * * * * 2 3 12
← e-2 →

LD (BC),A (BC)←A * * * * * * 00000010 02 1 2 7

LD (DE),A (DE)←A * * * * * * 00010010 12 1 2 7

LD (HL),r (HL)←r * * * * * * 01110rrr 1 2 7

00110110 36
LD (HL),n (HL)←n * * * * * * 2 3 10
← n →

11011101 DD

LD (IX+d),r (IX+d)←r * * * * * * 01110rrr 3 5 19

← d →

11011101 DD

00110110 36
LD (IX+d),n (IX+d)←n * * * * * * 4 5 19
← d →

← n →

11011101 FD

LD (IY+d),r (IY+d)←r * * * * * * 01110rrr 3 5 19

← d →

11111101 FD

00110110 36
LD (IY+d),n (IY+d)←n * * * * * * 4 5 19
← d →

← n →

00110010 32

LD (nn),A (nln2)←A * * * * * * ← n2 → 3 4 13

← n1 →

162
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11101101 ED

01ss0011
LD (nn),ss (n1n2)←ss * * * * * * 4 6 20
← n2 →

← n1 →

00100010 22

LD (nn),HL (n1n2)←HL * * * * * * ← n2 → 3 5 16

← n1 →

11011101 DD

00100010 22
LD (nn),IX (n1n2)←IX * * * * * * 4 6 20
← n2 →

← n1 →

11111101 FD

00100010 22
LD (nn),IY (n1n2)←IY * * * * * * 4 6 20
← n2 →

← n1 →

LD A,(BC) A←(BC) * * * * * * 00001010 OA 1 2 7

LD A,(DE) A←(DE) * * * * * * 00011010 1A 1 2 7

LD r,(HL) A←(HL) * * * * * * 01rrr110 1 2 7

11011101 DD

LD r,(IX+d) r←(IX+d) * * * * * * 01rrr110 3 5 19

← d →

11111101 FD

LD r,(IY+d) r←(IY+d) * * * * * * 01rrr110 3 5 19

← d →

00111010 3A

LD A,(nn) A←(n1n2) * * * * * * ← n2 → 3 4 13

← n1 →

LD rl,r2 r1←r2 * * * * * * 01 r1 r2 1 1 4

00rrr110
LD r,n r←n * * * * * * 2 2 7
← n →

11101101 ED

01ss1011
LD ss,(nn) ss←(n1n2) * * * * * * 4 6 20
← n2 →

← n1 →

00ss0001

LD ss,nn ss←n1n2 * * * * * * ← n2 → 3 3 10

← n1 →

163
 Mnem Flag OP code The number Machine
Action State
onic S Z H P/V N C 76543210 HEX of byte cycle

00101010 2A

LD HL,(nn) HL←n1n2 * * * * * * ← n2 → 3 5 16

← n1 →

11011101 DD

00101010 2A
LD IX,(nn) IX←(n1n2) * * * * * * 4 6 20
← n2 →

← n1 →

11011101 DD

00100001 21
LD IX,nn IX←n1n2 * * * * * * 4 4 14
← n2 →

← n1 →

11111101 FD

00101010 2A
LD IY,(nn) IY←(n1n2) * * * * * * 4 6 20
← n2 →

← n1 →

11111101 FD

00100001 21
LD IY,nn IY←n1n2 * * * * * * 4 4 14
← n2 →

← n1 →

LD SP,HL SP←HL * * * * * * 11111001 F9 1 1 6

11011101 DD
LD SP,IX SP←IX * * * * * * 2 2 10
11111001 F9

11111101 FD
LD SP,IY SP←IY * * * * * * 2 2 10
11110010 F9

11101101 ED
LD A,I A←I ↕ ↕ 0 IFF 0 * 2 2 9
01010111 57

11101101 ED
LD A,R A←R ↕ ↕ 0 IFF 0 * 2 2 9
01011111 5F

11101101 ED
LD I,A I←A * * * * * * 2 2 9
01000111 47

11101101 ED
LD R,A R←A * * * * * * 2 2 9
01001111 4F

164
 Flag OP code The number Machine
nemonic Action State
S Z H P/V N C 76543210 HEX Of byte cycle

* * 0 ♠ 0 * 11101101 ED
LDD 2 4 16
10101000 A8

* * 0 0 0 * 11101101 ED 2 5 21
LDDR
10111000 B8 BC=0 4 16

* * 0 ♠ 0 * 11101101 ED
LDI 2 4 16
10100000 A0

* * 0 0 0 * 11101101 ED 2 5 21
LDIR
10110000 B0 BC=0 4 16

A←0-A ↕ ↕ ↕ V 1 ↕ 11101101 ED
NEG 2 2 8
01000100 44

NOP NO OPERATION * * * * * * 00000000 00 1 1 4

OR (HL) A←A∨(HL) ↕ ↕ 0 P 0 0 10110110 B6 1 2 7

11011101 DD

OR (IX+d) A←A∨(IX+d) ↕ ↕ 0 P 0 0 10110110 B6 3 5 19

←d→

11111101 FD

OR(IY+d) A←A∨(IY+d) ↕ ↕ 0 P 0 0 10110110 B6 2 5 19

←d→

OR r A←A∨r ↕ ↕ 0 P 0 0 10110rrr 1 1 4

11110110 F6
OR n A←A∨n ↕ ↕ 0 P 0 0 2 2 7
← n →

11101101 ED 2 5 21
OTDR X 1 X X 1 *
10111011 BB B=0 4 16

11101101 ED 2 5 21
OTIR X 1 X X 1 *
10110011 B3 B=0 4 16

11101101 ED
OUT (C),r (C)←r * * * * * * 2 3 12
01rrr001

11010011 D3
OUT (n),A (n)←A * * * * * * 2 3 11
← n →

11101101 ED
OUTD X ↕ X X 1 * 2 4 16
10101011 AB

11101101 ED
OUTI X ↕ X X 1 * 2 4 16
10110011 A3

SSL←(SP),

POP SS SSH←(SP+1), * * * * * * 11ss0001 1 3 10

SP←SP+2

165
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

IXL←(SP)
11011101 DD
POP IX IXH←(SP+1) * * * * * * 2 4 14
11100001 E1
SP←SP+2

IYL←(SP)
11111101 FD
POP IY IYH←(SP+1) * * * * * * 2 4 14
11100001 E1
SP←SP+2

(SP-1)←SSH

PUSH ss (SP-2)←SSL * * * * * * 11ss0101 1 3 11

SP←SP-2

(SP-1)←IXH
11011101 DD
PUSH IX (SP-2)←IXL * * * * * * 2 4 15
11100101 E5
SP←SP-2

(SP-1)←IYH
11111101 FD
PUSH IY (SP-2)←IYL * * * * * * 2 4 15
11100101 E5
SP←SP-2

11001011 CB
RES b,(HL) (HL)b←0 * * * * * * 2 4 15
10bbb110

11011101 DD

11001011 CB
RES b,(IX+d) (IX+d)b←0 * * * * * * 4 6 23
←d→

10bbb110

11111101 FD

11001011 CB
RES b,(IY+d) (IY+d)b←0 * * * * * * 4 6 23
←d→

10bbb110

11001011 CB
RES b,r Rb←0 * * * * * * 2 2 8
10bbbrrr

PCL←(SP) C9

RET PCH←(SP+1) * * * * * * 11001001 1 3 10

SP←SP+2

3 11
RET cc * * * * * * 11ccc000 1
1 5

RETURN FROM 11101101 ED

RETI * * * * * * 2 4 14
INTERRUPT 01001101 4D

RETURN FROM
11101101 ED
RETN NMI * * * * * * 2 4 14
01000101 45
IFF1←IFF2

166
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11001011 CB
RL (HL) ↕ ↕ 0 P 0 ↕ 2 4 16
00010110 16

11011101 DD

11001011 CB
RL (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00010110 16

11111101 FD

11001011 DB
RL (IY+D) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00010110

11001011 CB
RL r ↕ ↕ 0 P 0 ↕ 2 2 8
00010rrr

RLA * * 0 * 0 ↕ 00010111 17 1 1 4

11001011 CB
RLC (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00000110 06

11011101 DD

11001011 CB
RLC (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00000110 06

11101101 FD

11001011 CB
RLC (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00000110 06

11001011 CB
RLC r ↕ ↕ 0 P 0 ↕
00000rrr

RLCA * * 0 * 0 ↕ 00000111 07 1 1 4

11101101 ED
RLD ↕ ↕ 0 P 0 * 2 5 18
01101111 6F

11001011 CB
RR (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00011110 1E

11011101 DD

11001011 CB
RR (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00011110 1E

11111011 FD

11001011 CB
RR (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00011110 1E

167
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11001011 CB
RR r ↕ ↕ 0 P 0 ↕ 2 2 8
00011rrr

RRA * * 0 * 0 ↕ 00011111 1F 1 1 4

11001011 CB
RRC (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00001110 0E

11011101 DD

11001011 CB
RRC (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00001110 0E

11111101 FD

11001011 CB
RRC (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00001110 0E

11001011 CB
RRC r ↕ ↕ 0 P 0 ↕ 2 2 8
00001rrr

RRCA * * 0 * 0 ↕ 00001111 0F 1 1 4

11101101 ED
RRD ↕ ↕ 0 P 0 ↕ 2 5 18
01100111 67

RESTART TO
RST n * * * * * * 11ttt111 1 3 11
LOCATION n

11011110 DE
SBC A,n A←A-n-Cy ↕ ↕ ↕ V 1 ↕ 2 2 7
← n →

SBC A,(HL) A←A-(HL)-Cy ↕ ↕ ↕ V 1 ↕ 10011110 9E 1 2 7

11011101 DD

SBC A,(IX+d) A←A-(IX+d)-Cy ↕ ↕ ↕ V 1 ↕ 10011110 9E 3 5 19

← d →

11111101 FD

SBC A,(IY+d) A←A-(IY+d)-Cy ↕ ↕ ↕ V 1 ↕ 10011110 9E 3 5 19

← d →

11101101 ED
SBC HL,ss HL←HL-ss-Cy ↕ ↕ ↕ V 1 ↕ 2 4 15
01ss0010

SBC A,r A←A-r-Cy ↕ ↕ ↕ V 1 ↕ 10011rrr 1 1 4

SCF Cy←1 00110111 37 1 1 4

11001011 CB
SET b,(HL) (HL)b←1 * * * * * * 2 4 15
11bbb110

168
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11011101 DD

11001011 CB
SET b,(IX+d) (IX+d)b←1 * * * * * * 4 6 23
← d →

11bbb110

11111101 FD

11001011 CB
SET b,(IY+d) (IY+d)b←1 * * * * * * 4 6 23
← d →

11bbb110

11001011 CB
SET b,r Rb←1 * * * * * * 2 2 8
11bbbrrr

11001011 CB
SLA (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00100110 26

11011101 DD

11001011 CB
SLA (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00100110 26

11111101 FD

11001011 CB
SLA (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00100110 26

11001011 CB
SLA r ↕ ↕ 0 P 0 ↕ 2 2 8
00100rrr

11001011 CB
SRA (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00101110 1E

11011101 DD

11001011 CB
SRA (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00101110 2E

11111101 FD

11001011
SRA (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00101110 2E

11001011 CB
SRA r ↕ ↕ 0 P 0 ↕ 2 2 8
00101rrr

11001011 CB
SRL (HL) ↕ ↕ 0 P 0 ↕ 2 4 15
00111110 3E

169
 Flag OP code The number Machine
Mnemonic Action State
S Z H P/V N C 76543210 HEX of byte cycle

11011101 DD

11001011 CB
SRL (IX+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00111110 3E

11111101 FD

11001011 CB
SRL (IY+d) ↕ ↕ 0 P 0 ↕ 4 6 23
← d →

00111110 3E

11001011 CB
SRL r ↕ ↕ 0 P 0 ↕ 2 2 8
00111rrr

SUB (HL) A←A-(HL) ↕ ↕ ↕ V 1 ↕ 10010110 96 1 2 7

11011101 DD

SUB (IX+d) A←A-(IX+d) ↕ ↕ ↕ V 1 ↕ 10010110 96 3 5 19

← d →

11111101 FD

SUB (IY+d) A←A-(IY+d) ↕ ↕ ↕ V 1 ↕ 10010110 96 3 5 19

← d →

SUB r A←A-r ↕ ↕ ↕ V 1 ↕ 10010rrr 1 1 4

11010110 D6
SUB n A←A-n ↕ ↕ ↕ V 1 ↕ 2 2 7
← n →

XOR (HL) A←A⊕(HL) ↕ ↕ 0 P 0 0 10101110 AE 1 2 7

11011101 DD

XOR (IX+d) A←A⊕(IX+d) ↕ ↕ 0 P 0 0 10101110 AE 3 5 19

← n →

11111101 FD

XOR (IY+d) A←A⊕(IY+d) ↕ ↕ 0 P 0 0 10101110 AE 3 5 19

← n →

XOR r A←A⊕r ↕ ↕ 0 P 0 0 10101rrr 1 5 19

11101110 EE
XOR n A←A⊕n ↕ ↕ 0 P 0 ↕ 2 2 7
← n →

170
Appendix 1: Operation Guide for Windows 7 64 Bits

Installing MTS-Z80A on Windows 7 64bits is quite a simple affair. If you follow the steps
exactly as described in this tutorial you will have MTS-Z80A up and running without any
problems.

DOSBox Installation

DOSBox is a DOS-emulator that uses the SDL-library which makes DOSBox very easy to port
to different platforms such as Windows 7 OS.

Step 1: Download DOSBox Win32 installer at http://www.dosbox.com/download.php?main=1.

Install DOSBox as shown below. Then click Next> to continue the installation.

Step 2: Select components to install. Then click Next> to continue the installation.

171
Step 3: Enter the directory where the DOSBox will be placed. The default is C:\Program Files
(x86)\DOSBox-0.74. Then click Install to continue the installation.

Step 4: As the installation is complete, click Close and then the “DOSBox 0.74” shortcut is
generated on Desktop automatically.

Assemble Your Source Program

Step 1: Create a new folder on C:\ , and rename it “MTS80A”.

Step 2: Put your assembly code [*.asm] and assembler (X80.exe and LINK80.exe) in this
folder.

172
Step 3: Open DOSBox 0.74 from Desktop.

Step 4: Write dos commend

Z:\> mount d c:\MTS80A\ (Enter)
Z:\>d: (Enter)

Step 5: The “MTS80A” folder is mounted on DOS environment under Windows 7 64 bits OS.
You are able to assemble your source program now.

173
Step 6: Write dos commend
D:\>X80 (Enter)
Type the source program(EXAM) in Input Filename.

Step 7: Press [Enter] twice. The object file [EXAM.OBJ] will be shown in the same folder.

174
Step 8: Write dos commend
D:\>Link80 (Enter)
Type the .obj file(EXAM.obj) and then click Enter 5 times to finish the link process.

Step 9: The hexadecimal file [EXAM.HEX] will be shown in the same folder. To download the
program into Z80 chip.

175
Appendix 2: HyperTerminal Operation Guide for Windows 7

1. First of all you need to get access to a Windows XP machine and copy three files
“hypertrm.dll", 'hypertrm.exe" and "hypertrm.chm" from that system to your target Windows
7 machine.

2. On the Windows 7 machine make a new folder under C:\Program Files\HyperTerminal for
32-bit or make a new folder under C:\Program Files (x86)\HyperTerminal for 64-bit.

3. From a Windows XP machine and copy the following 3 files to the folder that was just
created on the Windows 7 machine:
C:\Program Files\Windows NT\hypertrm.exe
C:\WINDOWS\system32\hypertrm.dll
C:\WINDOWS\Help\hypertrm.chm

4. Make sure you keep the files "hypertrm.dll", "hypertrm.exe" and "hypertrm.chm" in the
same folder. Now you can launch the HyperTerminal client on the Windows 7 machine by
double clicking the hypertrm.exe file. And there you have a fully working HyperTerminal
client.

176
[ Circuit Diagram of MTS-Z80A ]

177
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179
180
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185
186
187
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