NVA100
NVA100
MANUAL
— Applicability
This manual is valid for NVA100X-D devices with firmware version 1.70 and following.
— Conformity
The product complies with the CEE directives:
• EMC Council Directives 2014/30/EC
• Low voltage Directives: 2014/35/EC
— Service support
Contact: Service tecnico THYTRONIC www.thytronic.it
— Copyright
All right reserved; It is forbidden to copy, modify or store material (document and sw) protected by
copyright without Thytronic consent.
— Warranty
Thytronic warrants devices against defects in materials and workmanship under normal use for a
period of ONE (1) year from the date of retail purchase by the original end-user purchaser (“Warranty
Period”).
— Safety recommendations
The warming contained in this document are all-important for safety; special attention must be paid
to the following symbols:
Death, severe personal injury or substantial property damage will result if proper precautions
DANGER are not taken
CAUTION Minor personal injury or property damage can result if proper precautions are not taken
Death, severe personal injury or substantial property damage can result if proper precautions
WARNING are not taken.
Installation and commissioning must be carried out by qualified person; Thytronic assumes no re-
sponsibility for damages caused from improper use that does not comply all warning and caution in
this manual.
In particular the following requirements must be met:
• Remove power before opening it.
• Verify the voltage absence by means suitable instrumentation on relay connections; attention must
be paid to all circuits supplied by external sources (binary input, CT, etc...)
• Care must be taken when handling metal parts.
— Insulation tests
After insulation tests, hazardous voltages (capacitor charges,...) may be arise; it is advisable to grad-
ually reduce the test voltage avoiding to erase it abruptly.
In 5A 1A 5A UEn 100V
IEn 1A 1A 5A Un 100V
UAUX 110-230 Vac/dc
NVA100X#0D2J0TE0
• Test label with following informations: data, serial number and test operator signature[2].
— Environment
The NVA100X-D device must be employed according to the environment conditions shown (see tech-
nical data).
In case of different environment conditions, appropriate provisions must be provided (conditioning
system, humidity control, etc...).
If contaminants are present (dust, corrosive substances, etc...), filters must be provided.
— Graphical conventions
The CEI/IEC and ANSI symbols is employed where possible:
e.g.: 51 = ANSI code concerning the overcurrent element.
Following text formats are used:
The ThySetter menu:
Phase overcurrent -50/51
The parameter description (measures, thresholds, operate time,...) and related value:
I> element
Definite time
I>def
— Glossary/definitions
fn Rated frequency
I nH Relay phase rated current side H
I npH Phase CT primary rated current side H
I nL Relay phase rated current side L
I npL Phase CT primary rated current side L
I ng Protected device rated current
I En1 Relay residual rated current (input 1)
I Enp1 Residual CT primary rated current (input 1)
I En2 Relay residual nominal current (input 2)
I Enp2 Residual CT primary nominal current (input 2)
ANSI codes:
21 Underimpedance
26 Thermal with Pt100 probes
27 Undervoltage
27V1 Positive sequence undervoltage
32P Directional active overpower
37 Undercurrent
37P Directional active underpower
40 Loss of field
46M-46G Negative sequence overcurrent
47 Phase reversal
49MG Thermal image
50/51 Phase overcurrent side H and side L
51LR(48)/14 Locked rotor
51V Voltage restraint overcurrent
50N1-2/51N1-2/87NHIZ* Residual overcurrent (sides1-2)/
High impedance restricted earth fault
50N(Comp)/51N(Comp) Calculated residual overcurrent
55 Minimum power factor
Note 1 The rating data can be found on labels on the back and on the front (accessible after removing the left frame)
Note 2 The rating data can be found on labels on the front plate (accessible after removing the right frame)
CT Current Transformer
ThySensor Combo device
P1 IEC nomenclature for primary polarity mark of CTs (as an alternative to
a ANSI dot)
P2 IEC nomenclature for primary polarity mark of CTs (as an alternative to
a ANSI no-dot)
S1 IEC nomenclature for secondary polarity mark of CTs (as an alternative
to a ANSI dot)
S2 IEC nomenclature for secondary polarity mark of CTs (as an alternative
to a ANSI no-dot)
Self test Diagnostic
Start Leave an initial condition or reset condition (Pickup)
Trip Operation (with operate time)
Operating time Duration of time interval between the instant when the character-
istic quantity in reset condition is changed, under specified condi-
tions, and the instant when the relay operates
Dropout ratio The ratio of a reset value to an operate value in well-specified con-
ditions. The dropout ratio may be lower or greater than 1 according
as an over or under element is considered
Reset time Duration of the time interval between the instant when the charac-
teristic quantity in operate condition is changed, under specified
conditions, and the instant when the relay operates.
The stated reset time is related to a step variation of characteristic
quantity in operate condition to the reset condition.
Overshoot time The critical impulse time for a relay which is in its reset condition, is
the longest duration a specified change in the input energizing quan-
tities (characteristic quantity), which will cause the relay to change
to operate condition, can be applied without the relay switches. The
overshoot time is the difference from the operate time and the criti-
cal impulse time. The declared values for the overshoot time are ap-
plicable with the lower setting value of the operation time.
MMI (Man Machine Interface) Operator front panel
ThySetter Setting and monitoring software
Subnet Mask (Ethernet nomenclature)
Sw Software
Fw Firmware
Upgrade Firmware upgrade
XML eXtensible Markup LanguageXML
EXtensible Markup Language
Upgrade Firmware upgrade
Logic internal signal (output); may be a logical state (e.g.I>> Start) or a numerical value
I>> Start
It is available for reading (ThySetter + communication interface)
Logic external signal (intput); may be a command coming from a binary input or a sw command
IPh Block2
It is available for reading (ThySetter + communication interface)
Internal signal (e.g. Breaker Failure output state concerning to the 2nd threshold of the 50 element)
I>> BF_OUT It is not available for reading (missing arrow)
Switch
INPUT
t ON t ON t ON t ON t ON
RESET
t
INPUT
t ON
ON delay timer without reset (t ON delay) t ON t ON t ON
T 0
OUTPUT
t
INPUT
t OFF
OFF delay timer (dropout) without reset (t OFF delay) t OFF t OFF
0 T
OUTPUT
t
Symbols.ai
RESET t OFF
t
INPUT
t TR
Minimum pulse width operation for output relays (t TR) t TR t TR
0 T
OUTPUT
t
INPUT
OUTPUT
t
INPUT
t TR t TR
Pulse operating mode for output relays
t TR
OUTPUT
t
Symbols1 .ai
— Photo
— Emission
Reference standards EN 60255-25 IEC 60255-25
EN 61000-6-4 IEC 61000-6-4
EN 55011 CISPR 11
Electromagnetic emission tests
• Conducted emission auxiliary power supply 0.15...0.5 MHz 79 dB μV
• Conducted emission auxiliary power supply 0.5...30 MHz 73 dB μV
• Radiated emission 30...230 MHz 40 dB μV/m
• Radiated emission 230...1000 MHz 47 dB μV/m
— Mechanical tests
Reference standards EN 60255-21-1 EN 60255-21-2 RMEC01
Vibration, shock, bump and seismic tests on measuring relays and protection equipment
• EN 60255-21-1 Vibration tests (sinusoidal) Class 1
• EN 60255-21-2 Shock and bump test Class 1
— Climatic tests
Reference standards IEC 60068-x ENEL R CLI 01 CEI 50
Environmental testing
Ambient temperature -25...+70 °C
Storage temperature -40...+85 °C
Relative humidity 10...95 %
Atmospheric pressure 70...110 kPa
— Safety
Reference standards IEC 60255-27
Pollution degree 3
Reference voltage 250 V
Overvoltage category III
— Certifications
Product standards EN 50263
CE Conformity
• EMC Directive 2014/30/EC
• Low Voltage Directive 2014/35/EC
Type tests IEC 60255-1
— Binary inputs
Quantity 16 o 32[1]
Type optocoupler
Operative range 24...265 V~/-
Min activation voltage UDIGmin 18 V[3]
Max consumption, energized 3 mA
Timers
• Acquisition delay OFF/ON (IN1 tON, IN2 tON) 0.00...100.0 s
• Acquisition delay ON/OFF (IN1 tOFF, IN2 tOFF) 0.00...100.0 s
Logic DIRECT/INVERSE
LEDs
Numero 16
• ON/fail (verde) 1
• Start (giallo) 1
• Trip (rosso) 1
• Programmabili (rosso) 13
Keyboard 8 keys
— Remote ports
RS485
• Connection screw terminals
• Baud rate 1200...57600 bps
• Protocol[2] ModBus®RTU
IEC 60870-5-103
DNP3
Ethernet 100BaseT
• Connection[3] Optical fiber 1300 nm, ST
100 Base TX, RJ45
• Baud rate 100 Mbps
• Protocol ModBus®TCP/IP, IEC51850 Level A
Note 1 The quantity of binary inputs and output relays (8+8 relè di comando o 8 relè di comando +16 relè di segnalazione) depend on the version that
must be specified at ordering
Note 2 Different version must be selected at ordering
Note 3 Different version must be selected at ordering; two redundant port selectable with TX (RJ45) or FX (fiber) connections or two ports with TX
(RJ45) connections. The secondary port is activated in the event of failure of the primary port or by means of hw-sw switching command
Note 4 Parameters concern the IEC61850 protocol. Settings are available inside the Set \ Base menu.
Note 1 The nominal current settings doesn’t concern the protection elements; they must agree setting (1 A or 5 A)
Note 2 The setting ranges of the relay rated voltage UR are dependent on the purchased version (100 V or 400 V)
Nota 3 Calculated by relay
— Input sequence
Side H phase current sequence (I-SequenceH) IL1-IL2-IL3, IL1-IL3-IL2....
Side L phase current sequence (I-SequenceL) IL1-IL2-IL3, IL1-IL3-IL2....
Phase voltage sequence (U-Sequence) UL1-UL2-UL3, UL1-UL3-UL2,....
— Polarity
A1-A2 Terminals polarity (A1-A2 POL) NORMAL/REVERSE
A3-A4 Terminals polarity (A3-A4 POL) NORMAL/REVERSE
A5-A6 Terminals polarity (A5-A6 POL) NORMAL/REVERSE
A7-A8 Terminals polarity (A7-A8 POL) NORMAL/REVERSE
B3-B4 Terminals polarity (B3-B4 POL) NORMAL/REVERSE
B5-B6 Terminals polarity (B5-B6 POL) NORMAL/REVERSE
B7-B8 Terminals polarity (B7-B8 POL) NORMAL/REVERSE
B9-B10 Terminals polarity (B9-B10 POL) NORMAL/REVERSE
C1-C2 Terminals polarity (C1-C POL) NORMAL/REVERSE
C3-C4 Terminals polarity (C3-C POL) NORMAL/REVERSE
C5-C6 Terminals polarity (C5-C6 POL) NORMAL/REVERSE
C7-C8 Terminals polarity (C7-C8 POL) NORMAL/REVERSE
— Base current - IB
Base current (IB)[1] 0.10...2.50 In (step 0.01 In)
— Underimpedance - 21
Z< Element
Definite time
First threshold definite time (Z<def) 0.02...3.00 Z n [2] (step 0.01 Zn)
Operate time (t Zdef<) 0.07...100.0 s
0.07...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Reset time delay (t Z<RES) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Z<< Element
Definite time
Second threshold definite time (Z<<def) 0.02...3.00 Z n [2] (step 0.01 Zn)
Operate time (t Zdef<<) 0.07...100.0 s
0.07...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Reset time delay (t Z<<RES) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Pickup time ≤ 0.04 s
Dropout ratio 1.03...1.05
Dropout time ≤ 0.05 s
Overshoot time 0.03 s
Reference values rest: 1.5 I T
trip: 0.5 I T [3]
Pickup accuracy ± 4% ± 0.5% Zn
Operate time accuracy 5% or ± 10 ms
Nota 1 The base current IB represents the rated current of the line or transformer, referred to the nominal current of the CT’s for thermal image protection.
Note 2 Zn is the impedance given by the ratio between the relay rated voltage relay (Un) and the rated current of the relay (In) Zn= Un/In
Nota 3 I T is the value of input current required to trip for a given threshold setting and for a given input voltage (eg with setting Z<= 1.00 Zn and input
voltage 1.00 Un, the reference value I T is 1.00 In)
— Undercurrent - 37
Operating logic (Logic37) AND/OR
Definite time
First threshold definite time (I<def ) 0.10...1.00 In (step 0.01 In)
Operating time (t<def ) 0.04...200 s
0.04...9.99 s (step 0.01 s)
10.0...99.9 s (step 0.1 s)
100...200 s (step 1 s)
Pickup time ≤ 0.04 s
Dropout ratio 1.03...1.05
Dropout time ≤ 0.05 s
Overshoot time 0.04 s
Pickup accuracy ± 0.5% with 0.1In,
± 0.2% with 1In
Operate time accuracy 5% or ± 10 ms
— Loss of field - 40
Common configurations:
Operating mode (Mode 40 ) Motor/Generator
Undervoltage threshold (U SUP<) 0.50...1.00 Un (step 0.01 Un)
40AL Alarm
Inclination angle (ALPHA40AL ) 10...75° (step 1°)
Operating time (t40AL ) 0.07...100.0 s
0.07...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
XC1-XD1 Element
Absolute center coordinate (XC1) 0.00...4.50 Z nf (step 0.01 Z nf)
Diameter (XD1) 0.20...5.00 Znf (step 0.01 Z nf)
Operating time (t XC1XD1) 0.07...100.0 s
0.07...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Reset time delay (t XC1XD1-RES) 0.0...10.0 s (step 0.1 s)
Note 1 Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t (H)>inv / [(I/I(H)>inv)0.02 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t (H)>inv / [(I/I(H)>inv) - 1]
Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t (H)>inv / [(I/I(H)>inv)2 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or LIT): t = 120 · t (H)>inv / [(I/I(H)>inv) - 1]
Moderately Inverse (ANSI/IEEE type MI): t = t (H)>inv · {0.01 / [(I/I(H)>inv)0.02 - 1] + 0.023}
Very Inverse (ANSI/IEEE type VI): t = t (H)>inv · {3.922 / [(I/I(H)>inv)2 - 1] + 0.098}
Extremely Inverse (ANSI/IEEE type EI): t = t (H)>inv · {5.64 / [(I/I(H)>inv)2 - 1] + 0.024}
I-squared-t (I 2t = K): t = 16 · t (H)>inv / (I/I(H)>inv)2
Electromechanical (EM): t = 0.28 · t (H)>inv / [-0.236 · (I/I(H)>inv)-1+ 0.339]
RECTIFIER (RI): t = 2351 · t (H)>inv / [(I/I(H)>inv)5.6- 1]
t: operate time, minimum operate time: 0.1 s
I (H)> inv : pickup value
t (H)>inv : operate time setting
Asymptotic reference value: 1.1 I (H) > inv
Equation is valid for 1.1 ≤ I/I(H)>inv ≤ 20; the upper limit is 50 I nH
Note 1 Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t (L)>inv / [(I/I(L)>inv)0.02 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t (L)>inv / [(I/I(L)>inv) - 1]
Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t (L)>inv / [(I/I(L)>inv)2 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or LIT): t = 120 · t (L)>inv / [(I/I(L)>inv) - 1]
Moderately Inverse (ANSI/IEEE type MI): t = t (L)>inv · {0.01 / [(I/I(L)>inv)0.02 - 1] + 0.023}
Very Inverse (ANSI/IEEE type VI): t = t (L)>inv · {3.922 / [(I/I(L)>inv)2 - 1] + 0.098}
Extremely Inverse (ANSI/IEEE type EI): t = t (L)>inv · {5.64 / [(I/I(L)>inv)2 - 1] + 0.024}
I-squared-t (I 2t = K): t = 16 · t (L)>inv / (I/I(L)>inv)2
Electromechanical (EM): t = 0.28 · t (L)>inv / [-0.236 · (I/I(L)>inv)-1+ 0.339]
RECTIFIER (RI): t = 2351 · t (L)>inv / [(I/I(L)>inv)5.6- 1]
t: operate time, minimum operate time: 0.1 s
I (L)> inv : pickup value
t (L)>inv : operate time setting
Asymptotic reference value: 1.1 I (L) > inv
Equation is valid for 1.1 ≤ I/I(L)>inv ≤ 20; the upper limit is 50 I nL
Inverse time
Second threshold inverse time (I(L) >>inv) 0.100...20.00 InL
0.100...0.999 In (step 0.001 InL )
1.00...20.00 In (step 0.01 InL )
Note 1 the operate time characteristic is calculated according the general formula::
t = tLR>inv (IMOT-ST / I) 2, where:
t = operate time
tLR>inv= operate time setting
IMOT-ST = motor starting current with nominal voltage.
I = the maximum fundamental component of the phase currents,
— Residual overcurrent - 50N.1/51N .1 or High impedance restricted earth fault - 87NHIZ.1 - side 1
IE1> Element
IE1> Curve type (IE1> Curve) DEFINITE, IEC/BS A, B, C,
ANSI/IEEE MI, VI, EI, LIT, EM
CLP operating mode (IE1CLP > Mode) OFF/ON-Element blocking/ON-Change setting
CLP activation time (t E1CLP>) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
IE1> Reset time delay (t E1> RES) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Definite time
50N.1/51N.1 First threshold definite time (IE1> def ) 0.002...10.00 IEn1
0.002...0.999 IEn1 (step 0.001 IEn1)
1.00...10.00 IEn1 (step 0.01 IEn1)
IE1> def within CLP (IE1CLP>def ) 0.002...10.00 IEn1
0.002...0.999 IEn1 (step 0.001 IEn1)
1.00...10.00 IEn1 (step 0.01 IEn1)
Note 1 The element is blocked for the t LRCLP time (an adjustable threshold active during CLP does not exist)
IE1>>> Element
CLP operating mode (IE1CLP >>> Mode) OFF/ON-Element blocking/ON-Change setting
CLP activation time (t E1CLP>>>) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
IE1>>> Reset time delay (t E1>>> RES) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Definite time
50N.1/51N.1 Third threshold definite time (IE1>>> def ) 0.002...10.00 IEn1
0.002...0.999 IEn1 (step 0.001 IEn1)
1.00...10.00 IEn1 (step 0.01 IEn1)
IE1>>> def within CLP (IE1CLP>>>def ) 0.002...10.00 IEn1
0.002...0.999 IEn1 (step 0.001 IEn1)
1.00...10.00 IEn1 (step 0.01 IEn1)
IE1>>> def Operating time (t E1>>> def ) 0.03...10.00 s (step 0.01 s)
Pickup time ≤ 0.04 s
Dropout ratio 0.95...0.98
Dropout time ≤ 0.05 s
Overshoot time 0.04 s
Pickup accuracy ± 1% with 0.01 IEn1, ± 0.3% with 1 IEn1
Operate time accuracy 5% or ± 10 ms
Note 1 Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t E1>inv / [(IE1/IE1>inv)0.02 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t E1> inv / [(I E1/I E1> inv) - 1]
Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t E1> inv / [(I E1/I E1> inv)2 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or LIT): t = 120 · t E1> inv / [(I E1/I E>1 inv) - 1]
Moderately Inverse (ANSI/IEEE type MI): t = t E1> inv · {0.01 / [(I E1/I E1> inv)0.02 - 1] + 0.023}
Very Inverse (ANSI/IEEE type VI): t = t E1> inv · {3.922 / [(I E1/I E1> inv)2 - 1] + 0.098}
Extremely Inverse (ANSI/IEEE type EI): t = t E1> inv · {5.64 / [(I E1/I E1> inv)2 - 1] + 0.024}
Electromechanical (EM): t = 0.28 · t E1> inv / [-0.236 · (I E1/I E1> inv)-1+ 0.339]
I E1: residual current input
t: operate time, minimum operate time: 0.1 s
I E1> inv : pickup value
t E1> inv : operate time setting
Asymptotic reference value: 1.1 I E1> inv
Equation is valid for 1.1 ≤ I E1/ I E1> inv ≤ 20, with I E1> inv pickup ≥ 0.5 I En1, the upper limit is 10 I En1
Note 1 Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t EC>inv / [(IEC/IEC>inv)0.02 - 1]
Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t EC > inv / [(IEC/IEC>inv) - 1]
Very Inverse Time (IEC 255-3/BS142 type B or LIT): t = 120 · t EC > inv / [(IEC/IEC>inv) - 1]
Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t EC > inv / [(IEC/IEC>inv)2 - 1]
Moderately Inverse (ANSI/IEEE type MI): t = t EC > inv · {0.01 / [(IEC/IEC>inv)0.02 - 1] + 0.023}
Very Inverse (ANSI/IEEE type VI): t = t EC > inv · {3.922 / [(IEC/IEC>inv)2 - 1] + 0.098}
Extremely Inverse (ANSI/IEEE type EI): t = t EC > inv · {5.64 / [(IEC/IEC>inv)2 - 1] + 0.024}
Electromechanical (EM): t = 0.28 · t EC > inv / [-0.236 · (IEC/IEC>inv)-1+ 0.339]
I E: residual current input
t: operate time, minimum operate time: 0.1 s
I E> inv : pickup value, asymptotic reference value: 1.1 IEC>inv
t E > inv : operate time setting
Equation is valid for 1.1 ≤ I EC/ I EC> inv ≤ 20, with I EC> inv pickup ≥ 2.5 I n, the upper limit is 50 I n
IED >>>> def within CLP (IEDCLP >>>> def ) 0.002...10.00 IEn2
0.002...0.999 IEn2 (step 0.001 IEn2)
1.00...10.00 IEn2 (step 0.01 IEn2 )
IED >>>> def Operating time (t ED >>>> def ) 0.05...10.00 s (step 0.01 s)
Pickup time ≤ 0.04 s
Dropout ratio 0.95...0.98
Dropout time ≤ 0.05 s
Overshoot time 0.04 s
Pickup accuracy with measured residual voltage (UE) ± 0.2%
Pickup accuracy with calculated residual voltage (UEC) ± 1% with 0.01UECn
± 0.5% with 0.1UECn
Pickup accuracy (residual current) ± 1% with 0.01 IEn2
± 0.3% with 1 IEn2
Pickup accuracy (phase) ± 2° with 0.002 IEn2 - 0.004 UEn
± 0.2° with 0.005 IEn2 - 0.01 UEn
± 0.2° with 0.1 IEn2 - 0.5 UEn
± 0.3% with 1 IEn2
Operate time accuracy 5% or ± 10 ms
Definite time
67N(Comp) Third threshold definite time (IEDC>>> def - UED >>> def )
Residual current pickup value 0.100...40.0 In
0.100...0.999 In (step 0.001 In)
1.00...9.99 In (step 0.01 In)
10.0...40.0 In (step 0.1 In)
Residual voltage pickup value 0.004...0.500 UEn (step 0.001 UEn)
Characteristic angle 0...359° (step 1°)
Half operating sector 1...180° (step 1°)
IEDC >>> def within CLP (IEDCCLP >>> def ) 0.100...40.0 In
0.100...0.999 In (step 0.001 In)
1.00...9.99 In (step 0.01 In)
10.0...40.0 In (step 0.1 In)
IEDC >>> def Operating time (t EDC >>> def ) 0.05...10.00 s (step 0.01 s)
IEDC>>>> Element
CLP operating mode (IEDCCLP >>>> Mode) OFF/ON-Element blocking/ON-Change setting
CLP activation time (t EDCCLP>>>>) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
IEDC>>>> Reset time delay (t EDC>>>>RES) 0.00...100.0 s
0.00...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
— Overfrequency - 81O
f> Element
Definite time
81O First threshold definite time (f>def) 1.000....1.200 fn (step 0.001 fn)
f>def Operating time (t f> def ) 0.05...100.00 s
0.05...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
f>> Element
Definite time
81O Second threshold definite time (f>>def) 1.000....1.200 fn (step 0.001 fn)
f>>def Operating time (t f>> def ) 0.05...100.00 s
0.05...9.99 s (step 0.01 s)
10.0...100.0 s (step 0.1 s)
Pickup time ≤ 0.04 s
Dropout ratio ≥ 0.998
Dropout time ≤ 0.05 s
Overshoot time 0.04 s
Reference values rest: setting value - 0.2 Hz
trip: setting value + 0.2 Hz
Pickup accuracy ±5 mHz with 0.02 Un, ± 2 mHz with 1Un
Operate time accuracy 5% ± 10 ms
— Differential - 87G-87M-87T
Harmonic restraint (87T)
87T Second harmonic restraint threshold (2nd-REST>) 10...80% Id (step 1% Id)
87T Fifth harmonic restraint threshold (5th-REST>) 10...80% Id (step 1% Id)
87T Harmonic restraint intentional reset time delay (t H-RES) 0.00...10.00 s (step 0.01 s)
87T Cross phase harmonic restraint enable (CROSS H-RES) ON/OFF
CT saturation detector (87M-87G-87T)
Saturation detector enable (Sat-Det) ON/OFF
Saturation detector intentional reset time delay (tSat-Det-RES) 0.00...0.50 s (step 0.01 s)
Id > Element (87M-87G-87T)
First threshold (Id>) 0.05...2.00 Inref (step 0.01 Inref)
First stretch slope percentage (K1) 10...50% (step 1 %)
Second branch slope percentage (K2) 25...100% (step 1 %)
Second branch intersection with vertical axis (Q) 0.00...3.00 Inref (step 0.01 Inref)
First threshold operating time Id> (td>) 0.04 s
Id >> Element (87M-87G-87T)
Second threshold (Id>>) 0.50...30.00 Inref (step 1.00 Inref)
Second threshold operating time Id>> (td>>) 0.03 s
— Breaker failure - BF
BF Phase current threshold (IBF >) 0.05...1.00 I n (step 0.01 I n )
BF Residual current threshold (IEBF >) 0.01...2.00 I n (step 0.01 I En )
BF Time delay(tBF) 0.06...10.00 s (step 0.01 s)
Dropout ratio 0.95...0.98
Dropout time ≤ 0.05 s
Pickup accuracy (IBF >) ± 0.5% with 0.1 InL
± 0.2% with 1 InL
Pickup accuracy (IEBF >) ± 0.3% with 0.01 IEn
± 0.03% with 1 IEn
Operate time accuracy 5% or ± 10 ms
— VT supervision - 74VT
74VT Negative sequence overvoltage threshold (U 2 V T> ) 0.05...0.50 E n (step 0.01 E n )
74VT Negative sequence overcurrent threshold (I 2 V T> ) 0.05...0.50 I n (step 0.01 In)
74VT Phase undervoltage threshold (U V T< ) 0.05...0.50 E n (step 0.01 E n )
74VT Minimum change of current threshold (D I V T< ) 0.05...0.50 I n (step 0.01 In)
74VT Alarm time delay (t V T-A L ) 0.0...10.0 s (step 0.1 s)
Undercurrent inhibition threshold (I V T< ) 0.100...40.0 In
0.100...0.999 In (step 0.001 In)
1.00...9.99 In (step 0.01 In)
10.0...40.0 In (step 0.1 In)
Pickup accuracy for negative sequence voltage thresholds ± 5% con 0.01 Un
± 0.5% with 0.15 Un
Pickup accuracy for negative sequence current thresholds ± 1% with I2 = 0.5 In
± 1% with I2 = 1 In
Operate time accuracy 5% or ± 10 ms
— Demand measures
Fix on demand period (t F I X ) 1...60 min (step 1 min)
Rolling on demand period (t ROL ) 1...60 min (step 1 min)
Number of cycles for rolling on demand (N. ROL ) 1...24 (step 1)
— Oscillography (DFR)[1]
Format COMTRADE
Recording mode circular
Sampling rate 32 samples / cycle
Trigger setup:
Pre-trigger time 0.05...1.00 s (step 0.01 s)
Post-trigger time 0.05...60.00 s (step 0.05 s)
Note 1 For the DFR function a licence is required; call Thytronic for purchasing.
Note 2 Output relay and binary input states are available only when the concerning I/O circuits are implemented
— Measures
Measure Symbol
Locked frequency fl
U 12 frequency f U12
U 23 frequency f U23
U 31 frequency f U31
RMS value of fundamental comp. for phase currents side H I L1H , I L 2H , I L 3H
RMS value of fundamental comp. for phase currents side L I L1L , I L 2L , I L 3L
RMS value of phase currents side L I L1L...3Lrms
RMS value of fundamental component for phase voltages U L1, U L 2 , U L 3
RMS value of fundamental com. for residual current side 1 I E1
RMS value of fundamental com. for residual current side 2 I E2
RMS value of fundamental com. for residual voltage UE
Compensated currents side H I L1cH , I L 2cH , I L 3cH
Compensated currents sid L I L1cL , I L 2cL , I L 3cL
Stabilization currents I SL1, I SL 2 , I SL 3
Differential currents I DL1, I DL 2 , I DL 3
Second harmonic of differential currents I DL1-2nd, I DL2-2nd, I DL3-2nd
Fifth harmonic of differential currents I DL1-5th, I DL2-5th, I DL3-5th
Thermal image DTheta
Phase-to-phase voltages U 12 , U 23 , U 31
Calculated residual voltage U EC
Calculated residual current side H and side L I ECH , I ECL
Maximum current between I L1-I L 2 -I L 3 I Lmax
Maximum RMS current between I L1-I L 2 -I L 3 I Lmax-rms
Minimum current between I L1-I L 2 -I L 3 I Lmin
Minimum RMS current between I L1-I L 2 -I L 3 I Lmin-rms
Average current between I L1-I L2-I L3 I LL
Average RMS current between I L1-I L2-I L3 I L-rms
Average voltage between U L1-U L 2 -U L 3 UL
Maximum voltage between U L1-U L 2 -U L 3 U Lmax
Minimum voltage between U L1-U L 2 -U L 3 U Lmin
Average voltage between U 12-U 23-U 31 U
Maximum voltage between U 12-U 23-U 31 U max
Minimum voltage between U 12-U 23-U 31 U min
Displacement angle of I L1 respect to U L1 PhiL1
Displacement angle of I L 2 respect to U L 2 PhiL2
ETHERNET
1A/5A
INPUT MODULE
CPU
EEprom Flash SRam
≈
≈ CTs - VTs
CPU FPGA DSP ADC
≈
≈
RS485 Thybus
RTC
RS232-Ethernet ≈
OUTPUT RELAYS
KC1-1...KC1-8
KC2-1...KC2-8
BINARY INPUTS
IN1-1
IN1-16
+3ю3 V
+10 V
+24 V
-10 V
IN2-1
+5 V
0V
IN2-16
POWER SUPPLY
Pt100
PT1
T1 MPT1
PT8
T8 MPT8
Uaux
Analog outputs
-
MIS-1 #/∩ +
#/∩ -
MIS-4
+
hw.ai
— Input board
Depending on the version (inductive CT and VT inputs or ThySensor) respectively the module in-
cludes:
• Three CTs committed for phase currents acquisition
• One CT committed for residual current acquisition
The input circuits are suitable for 1 A or 5 A external CTs[1]
• Three VTs committed for phase voltages acquisition
• One VT committed for residual voltage acquisition.
or:
• Six voltage inputs for the measurement of the three currents and three phase voltages
• One CT committed for residual current acquisition
Note 1 The phase and residual nominal currents must be adjusted by means dip-switch.
Output relays
RAM/EPROM Diagnostic
memory check
LEDs
I/O
Data Base DATA BASE Thybus
Fast devices
Counters
EEPROM
Events
MMI Slow devices
sampling Measures
DSP
RTOS timer
Oscillography
KEYS
SIMBOLOGIA
— Base software
Single modules are application independent with modular and scalable structure.
The system can be assimilated to the PC BIOS (Basic Input-Output System); three main function are
provided:
• Start-up test execution;
• RAM loading of the operating system;
• Provide a suitable interface to access the relay hardware
— Task
The task (process e thread) are the base components.
Example are:
• Keyboard management
• RTC (Real Time Clock) updating
• RAM/EEPROM updating
• Diagnostic
• Input acquisition
• Output relay management
• MMI
• I/O updating
• DSP data processing
— Application Software
The software acts the specialization of the base system; all protective and control elements are
inside it.
The main modules ate:
• Diagnostic function for application layer,
• Input management (binary inputs),
• Protective functions,
• Event recording,
• Output management (LEDs and relays)
Each element (Kernel, Drivers and Application) may, in turn, be split into modules:
Communication (drivers)
The ModBus TCP/IP protocol, with ethernet interface, the ModBus RTU, IEC 60870-5-103 and DNP3
protocol over RS485 interface and the ModBus RTU RS232 for ThySetter are provided.
MMI (drivers)
The drivers deal with the menu management (MMi and/or communication messages).
— Data Base
The data base is split into three main sections:
• RAM for volatile data,
• REE and PAR for non volatile data.
NVA100X-D
Three phase current inputs side H
G
Three phase current inputs side L
— Signal processing
Various processing levels are involved:
• Acquisition (base level).
• Direct measures of physical channels (first level).
• Calculated measures (second level).
• Derived (third level).
The measures concerning a level are based on data worked out in the previous level.
For each level the required resources concerning the priority for tasks (conditioning circuits, DSP
and CPU) are on hand.
ACQUISITION
≈ instantaneous measures
acquisizione.ai
• Direct
• Calculated
• Phase
• Sequence
• Power
• Harmonic
• Impedance
• Demand
• Energy.
• Phase currents - side H and side L IL1H, IL2H, IL3H, IL1L, IL2L, IL3L
ACQUISITION
IL1.ai
ACQUISITION
VTs
u L1, u L2 , u L3 U L1, U L2 , U L3
≈ DFT (En)
UL 1 . a i
ACQUISITION
IE.ai
• Residual voltage UE
ACQUISITION UE
VT DFT (fundamental) (UEn)
uE
≈
U E3H
DFT (3rd harmonic) (UEn)
UE . a i
Calculated
• Frequency. The measure of period is taken preferably from phase voltage inputs[1]; when all volt-
age are missing the input current are employed.
ACQUISITION
f
UL2 ≈ uL2 uL23 (Hz)
T
f
IL2H, IL2L ≈ i L2H, i L2L (Hz)
T
F. a i
Note 1 The frequency can also be measured on the three phase-to-phase voltages (calculated vectorially)
UL1
U12
UL2 U12 = UL1 - UL2 (Un)
UL2
U23 U31 UL1 U12
UL3 U23 = UL2 - UL3 (Un)
UL3 UL2
UL1
U 31
UL3 U 31 = UL3 - UL1 (Un)
U23
U1 2 . a i
UL1
UL2 UEC
UEC = UL1 + UL2 + UL3 (UEn)
UL3
UE C . a i
• Fundamental component of the calculated residual currents IECH and IECL [2]
IECH
IL1H, IL2H, IL3H IECH = IL1H + IL2H + IL3H (InH)
IECL
IL1L , IL2L, IL3L IECH = IL1H + IL2H + IL3H (InL )
IEC.ai
• Thermal image Δθ
IL1L
I1
I1 = (IL1L + e+j120°IL 2 L + e-j120°IL 3 L ) It h 2
IL2L
I2
It h = √(I1 2 + K2 2 ∙I2 2 ) dΔθ Δθ IB
+ =
( ) Δθ
(ΔθB )
-j120° +j120° dt T+ T+
IL3L I2 = (IL1L + e IL 2 L + e IL 3 L )
Theta.ai
Phase[3]
• Displacement angle of any phase current respect the corresponding phase-to-neutral voltage:
PhiL1, PhiL2, PhiL3,
• Displacement angle of the measured residual current respect the measured residual voltage (posi-
tive with current in lagging direction in respect to voltage): PhiE,
• Displacement angle of the measured residual current respect the calculated residual voltage (pos-
itive with current in lagging direction in respect to voltage): PhiEC
• Displacement angle of the calculated residual current respect the measured residual voltage (pos-
itive with current in lagging direction in respect to voltage): PhiE_IEC
• Displacement angle of the calculated residual current respect the calculated residual voltage
(positive with current in lagging direction in respect to voltage): PhiEC_IEC
UL1
ϕL1 = IL1 - U L1
UL2 Phi L1 , Phi L 2 ,Phi L 3
ϕL 2 = IL 2 - U L 2 (° )
UL2
ϕL 3 = IL 3 - U L 3
IL1L
IL2L
IL3L ϕE = U E - IE Phi E
(° )
UE ϕEC = U EC - IE Phi EC
(° )
UEC
ϕE_IEC = U E - IEC Phi E_IEC
(° )
IE
ϕEC_IEC = U EC - IEC Phi EC_IEC
(° )
IEC
Fase.ai
Note 1 The residual voltage is available as a direct measure UE and computed measure UEC,
Note 2 The residual currents are available with either direct measurement (IE1 and IE2) and as calculated measure (IECH and IECL)
Note 3 The adjustment and display range of displacements are 0°... 359°
IL1L I 1 -I 2 . a i
+j120° -j120°
IL2L I1 = (IL1 + e IL 2 + e IL 3 ) / 3 I1 , I 2
(In)
IL3 L -j120° +j120°
I2 = (IL1 + e IL 2 + e IL 3 ) / 3
1 √3 1 √3
e-j120°= - -j e
+j120°
=- +j
2 2 2 2
Demand
• Fixed demand (IL1FIX, IL2FIX, IL3FIX, ±P FIX, ±Q FIX)
Inside an adjustable time interval t FIX, an average magnitude is calculated for phase currents IL1,
IL2, IL3, active power ±P and reactive power ±Q of measures taken every second. The average val-
ues are stored at the end of the same time interval.
IL1L tF I X ∙ 60
1
IL2L
IL x F I X
tF I X ∙ 60
¥ IL x n IL1F I X, IL 2 F I X,IL 3 F I X
(In )
n=1
IL3L tF I X ∙ 60
±PF I X = 1 ¥ ±Pn ±PF I X
(Pn )
tF I X ∙ 60
n=1
1s
tF I X tF I X tF I X tF I X tF I X ∙ 60
±P ±Q F I X = 1 ¥ ±Q n
±Q F I X
(Qn )
tF I X ∙ 60
±Q n=1
F i x -De m a n d . a i
IL1ROL
Rolling demand example with N ROL=4 N R OL t R OL∙60
IL 2 ROL
IL1L Average inside time interval t ROL IL x ROL = 1 ¥
1
¥ IL x k IL 3 ROL
NROL tROL∙60 (In )
IL2L n=1 k=1 n
IL3L N R OL t R OL∙60
1 1 ±PROL
±PROL =
NROL
¥ tROL∙60
¥ ±Pk (Pn )
n=1 k=1 n
1s N R OL t R OL∙60
±P ±Q ROL
tROL tROL tROL tROL tROL tROL ±Q ROL = 1 ¥
1
¥ ±Q k (Qn )
±Q NROL tROL∙60
0 1 2 3 4 5 6 n=1 k=1 n
NROL
Rol-Demand.ai
IL1MA X
Maximum value of averages inside time interval t ROL t R OL∙60
IL1L 1 IL 2 MA X
Average inside time interval t ROL IL x MA X= MAX
tROL∙60
¥ IL x n IL 3 MA X
IL2L n=1 (In )
IL3L t R OL∙60
1 ±PMA X
±PMA X= MAX
tROL∙60
¥ ±Pn (Pn )
n=1
±P 1s
t R OL∙60
tROL tROL tROL tROL tROL tROL 1 ±Q MA X
±Q ±Q MA X= MAX
tROL∙60
¥ ±Q n (Qn )
n=1
Max-Demand.ai
IL1MIN
Minimum value of averaged inside time intervalt ROL t R OL∙60
IL1L Average inside time intervalt ROL 1 IL 2 MIN
IL x MIN = MIN
tROL∙60
¥ IL x n IL 3 MIN
IL2L n=1 (In )
IL3L
t R OL∙60
1 ±PMIN
±PMIN = MIN
tROL∙60
¥ ±Pn (Pn )
1s n=1
Reset
±P t R OL∙60
tROL tROL tROL tROL tROL tROL 1 ±Q MIN
±Q ±Q MIN = MIN
tROL∙60
¥ ±Qn (Qn )
n=1
Min-Demand.ai
Impedance
- impedance (21 element): Z12, Z23, Z31,
- impedance (L1 phase): ZL1
- resistive component impedance L1: RL1
- reactive component impedance L1: XL1
UL1
Z12 = U12 /IL1
UL2 Z12 , Z2 3 , Z3 1
Z2 3 = U 2 3 /IL 2 (Zn)
UL2 Z3 1 = U 3 1 /IL 3
IL1L ZL1 , RL1 , XL1
ZL1 = U L1 /IL1 (ZnF)
IL2L
RL1 = ZL1 ∙ cos ϕ-Z L1
IL3L XL1 = ZL1 ∙ sinϕ-Z L1 Zn = U n /In Znf = En /In
Z.ai
Power
• Phase active power: ±PL1, ±PL2, ±PL3,
• Total active power: ±P
UL1
UL2 ±PL1 = U L1∙ IL1L∙ cos ϕL1
±PL1 , ±PL 2 ,±PL 2 ,±P
UL3 ±PL 2 = U L 2∙ IL 2 L∙ cos ϕL 2 (Pn )
IL1L
±PL 3 = U L 3 ∙ IL 3 L∙ cos ϕL 3 cosPhi L1 , cosPhi L 2 ,cosPhi L 3
IL2L (p.u.)
±P = PL1+ PL 2+ PL 3
IL3L
P. a i
UL1
UL2 ±Q L1 = U L1∙ IL1L∙ sinϕL1
UL2 ±Q L 2 = U L 2∙ IL 2 L∙ sinϕL 2 ±Q L1 , ±Q L 2 ,±Q L 2 ,±Q
IL1L (Qn )
±Q L 3 = U L 3 ∙ IL 3 L∙ sinϕL 3
IL2L
±Q = Q L1+ Q L 2+ Q L 3
IL3L
Q. a i
±P
S
S = P2 + Q2 (Sn )
±Q
S.ai
+P
EA +, EA -,EA
-P EA + = ∫(+Pdt) EA - = ∫(-Pdt) EA = ∫(Pdt) (Wh)
+Q
EQ + = ∫(+Q dt) EQ - = ∫(-Q dt) EQ = ∫(Q dt) EQ +, EQ -,EQ
-Q (varh)
E.ai
IL1H IL1L
IL1H-IL3H-IL2H IL1L-IL3L-IL2L
IL2H-IL1H-IL3H IL2L-IL1L-IL3L
IL2H-IL3H-IL1H IL2L-IL3L-IL1L
IL3H-IL1H-IL2H IL3L-IL1L-IL2L
IL3H-IL2H-IL1H IL3L-IL2L-IL1L
L1 L2 L3 NVA100X-D
IL1-> IL1
IL3-> IL3
L1 L2 L3 NVA100X-D
IL1-> IL1
IL3-> IL2
NVA100X-D
C2-C4-C6-C8 terminals
Protected object
(Motor/Generator/ NO CORRECTION
Transformer) REQUIRED
side L CTs A1-A3-A5-A7 terminals
A2-A4-A6-A8 terminals
NVA100X-D
C1-C3-C5-C7 terminals
side H CTs
Phase current inputs side H Polarity = NORMAL
C2-C4-C6-C8 terminals
A2-A4-A6-A8 terminals
NVA100X-D
C1-C3-C5-C7 terminals
TA lato H
C2-C4-C6-C8 terminals
Protected object
(Motor/Generator/
REQUIRED POLARITY
Transformer) CORRECTION ON SIDE L
A1-A3-A5-A7 terminals
A2-A4-A6-A8 terminals
NVA100X-D
A1-A3-A5 UL3
IL1 IL3
IL2 CURRENT INPUTS
IL3
B3-B5-B7 UL1
IL1
UL1 VOLTAGE INPUTS IL2
UL2
UL3
SYSTEM UL2
II° +Q, +Q L1 , +Q L 2 , +Q L 3 I°
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
Resistive-inductive
S,SL1 ,SL 2 ,SL 3 load
SYSTEM
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
-Q, -Q L1 , -Q L 2 , -Q L 3
III° IV°
Resistive-inductive load convenzioni.ai
• Resistive-capacitive load.
NVA100X-D
A1-A3-A5 UL3
IL1
IL2 CURRENT INPUTS IL3
IL3
IL1
B3-B5-B7 UL1
II° +Q, +Q L1 , +Q L 2 , +Q L 3 I°
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
Resistive-capacitive
S,SL1 ,SL 2 ,SL 3 SYSTEM load
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
-Q, -Q L1 , -Q L 2 , -Q L 3
III° IV°
Resistive-capacitive load convenzioni2.ai
SYSTEM NVA100X-D
UL3
A1-A3-A5
IL1
IL1
IL2 CURRENT INPUTS IL2
IL3
UL1
B3-B5-B7
II° +Q, +Q L1 , +Q L 2 , +Q L 3 I°
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
Resistive-inductive
load S,SL1 ,SL 2 ,SL 3
SYSTEM
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
-Q, -Q L1 , -Q L 2 , -Q L 3
III° IV°
Resistive-inductive load convenzioni3.ai
Resistive-capacitive load.
SYSTEM NVA100X-D
UL3
A1-A3-A5 IL2
IL1
IL2 CURRENT INPUTS
IL3
UL1
B3-B5-B7 IL3
II° +Q, +Q L1 , +Q L 2 , +Q L 3 I°
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
-cos ϕ, -cos ϕL1 , -cos ϕL 2 , -cos ϕL 3 +cos ϕ, +cos ϕL1 , +cos ϕL 2 , +cos ϕL 3
-Q, -Q L1 , -Q L 2 , -Q L 3
III° IV°
Resistive-capacitive load convenzioni4.ai
P, Q, S
UEC
UE
U1
U2
uE
I1
I2
E
f
PROTECTIVE ELEMENTS
Underimpedance (21) g g g g g g g
Undervoltage (27) g g g g g g g
Positive sequence undervoltage (27V1) g g g g g g
Directional active overpower (32P) g g g g g g
Undercurrent (37) g g g g g g
Directional active underpower (37P) g g g g g g
Loss of field (40) g g g g g g g
Negative sequence overcurrent (46M-G) g g g g g g g g
Thermal image (49MG) g g g g g g g g g g g g g
Phase overcurrent (50/51) g g g g g g g g g g g
Voltage restrained overcurrent (51V) g g g g g g g g g g
Residual overcurrent (50N.1/51N.1, 50N.2/51N.2) g g g g g g g g g g g
Residual overcurrent (50N/51NComp) g g g g g g g g g g g g
Minimum power factor (55) g g g g g g
Overvoltage (59) g g g g g g g g g
Residual overvoltage (59N) g g g g g g g g
Negative sequence overvoltage (59V2) g
Low impedance restricted earth fault (64REF) g g g g g g g g g g g g
Directional earth fault overcurrent (67N) g g g g g g g g g g g g
Directional earth fault overcurrent (67NComp) g g g g g g g g g
Under/overfrequency (81U/81O) g g g g g g
Compensated differential (87G-87M-87T) g g g g g g g g
Breaker failure (BF) g g g g g g g g
CONTROL and MONITORING
Maximum number of startings (66) g g g g g g
Automatic reclosure g g g g g
CT Monitoring (74CT) g g
VT Monitoring(74VT) g g g g g g
Trip Circuit Supervision (TCS) g
Second harmonic restraint (2NDH-REST) g
MEASURES
Frequency g g
Phase currents g g
Measured residual current g
Positive sequence current g
Negative sequence current g
Thermal image g
Phase voltages g
Phase-to-phase voltages g
Residual voltage g
Negative sequence voltage g
Active power g
Reactive power g
Apparent power g
Phase current /phase voltage displacement g g
Power factor g g
Reactive energy g
EVENT RECORDER
Event 0 g g g g g
Event ...299 g g g g g
FAULT RECORDER
Fault 0 g g g g g g g g g g g
Fault ... g g g g g g g g g g g
Fault 19 g g g g g g g g g g g
OSCILLOGRAPHY
Record 1 g g g g g g g g g g g g g g g g g
Record ... g g g g g g g g g g g g g g g g g
Note: the acquired measurements on the L side are used for all protective elements with the exception of differential (87) and phase overcurrent (50/51)
protections that also employ current measurements acquired on the H
BINARY INPUT
t ON t ON t OFF t OFF
INTERNAL STATE
t
binary-timers.ai
In the diagram, INTERNAL STATE represents the logical state of the binary input used in the following
processing. Each binary input may be matched to one of the following default functions.
Binary inputs
ELEMENTS
IN1-1 IN1-x IN1-16 IN2-1 IN2-x IN2-16
Reset LEDs g g g g g g
Set profile (switching setting A and B) g g g g g g
Fault trigger (fault recording) g g g g g g
Block2 IPh/IE (selective block from phase and/or ground elements) g g g g g g
Block2 IPh (selective block from phase elements) g g g g g g
Block2 IE (selective block from ground elements) g g g g g g
Block1 (logic block) side H-L g g g g g g
Block1 (logic block) side H g g g g g g
Block1 (logic block) side L g g g g g g
Block1 (logic block) 87GMT g g g g g g
TCS1 (Trip Circuit Supervision) g g g g g g
TCS2 (Trip Circuit Supervision) g g g g g g
Trip ProtExt (trip from external protection relays) g g g g g g
Reset counters g g g g g g
Reset CB Monitor (clear CB monitoring data) g g g g g g
52a (CB auxiliary contact) g g g g g g
52b (CB auxiliary contact) g g g g g g
Open CB g g g g g g
Close CB g g g g g g
Preset DTheta (thermal image preset) g g g g g g
Remote trip g g g g g g
MCB VT OPEN (MCB auxiliary contact or fuse) g g g g g g
MCB VT2 OPEN (MCB V2 auxiliary contact or fuse) g g g g g g
Reset on demand measures g g g g g g
Reset energy measures g g g g g g
74VT ext. (74VT from external protection relays) g g g g g g
I(L)>Bk (Logic block of I> element-side L, active through virtual I/O) g g g g g g
I(L)>>Bk (Logic block of I>> element-side L, active through virtual I/O) g g g g g g
I(L)>>>Bk (Logic block of I>>> element-side L, active through virtual I/O) g g g g g g
I(H)>Bk (Logic block of I> element-side H, active through virtual I/O) g g g g g g
I(H)>>Bk (Logic block of I>> element-side H, active through virtual I/O) g g g g g g
I(H)>>>Bk (Logic block of I>>> element-side H, active through virtual I/O) g g g g g g
IE1>Bk (Logic block of IE1> element, active through virtual I/O) g g g g g g
IE1>>Bk (Logic block of IE1>> element, active through virtual I/O) g g g g g g
Set-Reset latch
TRIPPING M ATRIX
(LED+REL AYS)
S
Set (ON≡turn on LED/relay)
≥
Set profile
Inside Pro-N devices, two independent setting profiles (A and B) are available. Whereas different
settings are required, they are made in the setting profiles and stored in the non volatile memory of
relay. Applicable setting profile is activated usually via a binary input; when the programmed input is
activated, the profile B becomes operative as a replacement for the default profile A.[1]
Note 1 To enable the profile switching the “Input-selected” parameter must be set inside the “Profile selection” submenu.
If multiple setting groups are not required, Group A is the default selection
Fault recording
IL1->IL1r
Logic INx t O N INx t O F F IL2 ->IL2r
Fault trigger Protection
.....
element
n.c. INx t ON INx t OFF ≥1 DTheta->DTheta-r
n.o. T 0 0 T Inputs
Outputs
Binary input INx
Fault cause info
Block2 IPh/IE
A change in status of a binary input effects a block[1] common for the following phase and ground
protective elements:
• I2>, I2>> (46M)
• DthAL1, DthAL2, Dth (49MG),
• I>, I>>, I>>> (50/51)
• ILR>, ILR>> (51LR)
• I-I/U>, I-I/U>> (51V)
and ground fault:
• IE1>, IE1>>, IE1>>> (50N.1/51N.1)
• IE2 >, IE2 >>, IE2 >>> (50N.2/51N.2)
• IEC >, IEC >>, IEC >>> (50NComp/51NComp)
• IED >, IED >>, IED >>> e IED >>>> (67N)
• IEDC >, IEDC >>, IEDC >>>, IED >>>> (67NComp)
The application of the binary inputs for the acquisition of Block2 (selective block) coming from exter-
nal protection relays is shown in the following figure.
t B-Iph
Block2 IPh
A change in status of a binary input effects a block[2] for the following phase protective elements:
• I2>, I2>> (46M), DthAL1, DthAL2, Dth> (49), I>, I>>, I>>> (50/51), ILR>, ILR>> (51LR), I-I/U>, I-I/U>> (51V).
Block2 IE
A change in status of a binary input effects a block[1] for the following earth protective elements:
• IE1>, IE1>> e IE1>>> (50N.1/51N.1), IE2 >, IE2 >> e IE2 >>> (50N.2/51N.2) IED >, IEC >, IEC >> e IEC >>>
(50NComp/51NComp), IED >>, IED >>>, IED >>>> (67N), IEDC >, IEDC >>, IEDC >>> e IED >>>> (67NComp).
Block1
A change in status of a binary input effects a block for a length of time equal to the activation of the
input[3]; the element pickup that wish be blocked must be enabled (the Block1 parameter must be
Note 1 The exhaustive treatment of the Block 2 function is described in the “Logic selectivity” paragraph.
Note 2 The exhaustive treatment of the Block 2 function is described in the “Logic selectivity” paragraph.
The application of the inputs for the acquisition of Block2 (selective block) for Phase (Block2 Iph) and earth protective functions (Block2 IE) is
similar to that illustrated in the scheme concerning the Block2 IphIIE
Note 3 Unlike the Block2 (selective block), that houses a safety logic founded on programmable timers, the Block1 (logic block) keeps block of the
protection for the whole time when the input is active.
+UAUX
Logic IN1 t O N IN1 t O F F
TCS1
n.c. IN1 t ON IN1 t OFF
n.o. 74TCS logic
T 0 0
TRIP Binary input INx
TCS2
Logic IN1 t O N IN1 t O F F
52
n.c. IN1 t ON IN1 t OFF
52a 52b 74TCS logic
n.o. T 0 0 T
Binary input INx
-UAUX
Trip Circuit Supervision - 74TCS with two binary inputs TCS2.ai
Trip ProtExt
The binary input detects a trip coming from an external protective relay: the information is available
for the breaker failure function (BF).
Binary input allocation for trip acquisition from external protection device ExtProt.ai
Reset counters
A change in status of a binary input effects a reset of all start/trip partial counters.[2]
Reset CB Monitor
A change in status of a binary input effects a reset of all counters concerning the circuit breaker
diagnostic:
• Breaking Sum phase IL1, IL2 , IL3
• Breaking SumI2t phase IL1, IL2 , IL3
• CB Open counter
52a and 52b
The CB position can be acquired by means of binary inputs connected to the auxiliary contacts: the
information is used in the following functions:
• CB position (open-closed)
• CB diagnostic (N. of operations, trip time)
• Breaker Failure (BF)
• VT monitoring (74TV)
Note 1 The activation of one binary input produces indiscriminately a block of all protective elements programmed for being blocked from Block1
Note 2 The reset of the total counters is practicable by means ThySetter command with Session Level 1 (available with password)
Open CB
Close CB
The external acquisition of remote commands allows to drive CB remotely.
TRIPPING M ATRIX
52a O -UAUX
(LED+REL AYS)
Binary input INx 52 52b
CLOSE
Command Close CB Logic INx t O N INx t O F F -UAUX I
Preset DTheta
The input activation presets the thermal image (49).
The preset value can be adjusted by means the DθIN setting. The thermal image is initialized at the
DθIN value when the device is powered or when the binary input become active.
UAUX
PresetDTheta Logic
PresetDTheta INx t ON INx t OFF
Remote trip
The input activation drives an expressly programmed output relay.
+UAUX
Remote trip
TRIPPING M ATRIX
-UAUX
Assegnazione ingresso logico alla acquisizione del segnale d’ingresso di telescatto Remote-trip.ai
LINE
VT
UAUX
MCB
MCB VT OPEN Logic INx t ON INx t OFF
74TV ext
The external acquisition of 74TV allows to block or to change the operating mode of protective el-
ements where the residual voltage is employed; the information is available for residual voltage
protective elements (59N and 67N protections) that may operate inadvertently when an event cause
a loss of one or more voltages.
Reset demand measures
The input activation make a reset of all demand measures.
Reset energy
The input activation make a reset of all energy measures.
UAUX
Speed control
Speed control Logic INx t O N INx t O F F
Motor restart
During the time that the motor starts, the current is near the blocked rotor value, but the condition is
not managed because the measured current goes never off (or however down to IRUN=0.1 IB).
If a binary input is set as “Motor restart” and the parameter of the timers reset is enabled for all
protection elements inside CLP (MR Enable ON)[1] inside the Starting control set menu), the timers
restart when the binary input become active.
Starting control
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Reset P-RMT
The operation time of motor is cleared when the binary input become active (Partial counter).
Reset T-RMT
The operation time of motor is cleared when the binary input become active (Total counter).
Note 1 For generator protection the MR Enable parameter must be disabled (OFF)
Input
No-latched operation
Latched operation
Pulse operation
t
t TR Minimum pulse width
Output relay operation Relay-operation-timers.ai
Any change to the settings can be affected at any time, also with the relay on duty, separately for
each relay.
Notes:
• When de-energized operating mode is set, the relay remains in rest condition if no trip command
is in progress.
• When energized operating mode is set, the relay remains in operating condition if no trip command
is in progress and the auxiliary supply is powered on.
• When no-latched operating mode is set (Operation MODE No latched), the output relay reset
at the end of the trip condition. To each output relay a programmable timer is matched (minimum
pulse width operation).
• When latched operating mode is set (Operation MODE Latched), the output relay doesn’t reset
at the end of the trip condition; it stays ON until a reset command is issued (RESET key, ThySetter
or communication command).
• When pulse operating mode is set (Operation MODE Pulse), the output relay reset after a tTR
programmable delay regardless of the trip condition.
• It is advisable to make sure that the output contact technical data are suitable for load (Nominal
current, breaking capacity, make current, switching voltage,...).
Matching every output relay to any protective element is freely programmable inside the Setpoints
submenus according a tripping matrix structure.[2]
• One green LED “ON”: if turned on it means that the device is properly working, if flashing the inter-
nal self-test function has detected an anomaly.
• One yellow LED “START” tagged for START of one or more protective elements.[1]
• One red LED “TRIP” tagged for TRIP of one or more protective elements.[1]
• Thirteen red LEDs “1...13” for highlight the activation of one or more user defined function.
LEDs MMI
Free allocation of each LED may be set according to the matrix structure shown in the following
page.[2]
Note 1 The START and the TRIP LED are user assignable to any function; other than starting and tripping information can be assigned to them too, just
the same for L1...L5
Note 2 All features are listed; functions effectively present depend on the version
All LEDs are unassigned in the default setting.
Local port
The local port has high priority compared with the remote Ethernet and RS485 ports.
RJ45 plug
serial-sch.ai
The local port is the simplest access for setting by means the ThySetter software.
RS485
Several protocol are implemented:
• ModBus RTU. Modbus is a serial communications protocol. It is a de facto standard communica-
tions protocol in industry, and is now the most commonly available means of connecting industrial
electronic devices also inside electric utilities and substation.
• IEC 60870-5. The IEC 60870-5 suite of protocol is used for communications from master station to
substation, as well within the substation; the IEC 60870-5-103 (Protection equipment) is available
together the Modbus protocol on some version of Pro-n devices (code NAxx#xxxxC x).
Ethernet
It is provided a communication board useful for Ethernet communication with ModBus TCP/IP[1] or
IEC61850 protocol
When ordering the types of network board may be selected:[2]
• Two ports module with multiplexed operation mode[3], with one TX port (RJ45 copper network) and
one FX port (fiber-optic network).
• Two TX ports module (RJ45 copper network) with multiplexed operation mode.
• Two FX ports module (optical fiber network) with multiplexed operation mode.
• Two FX ports module (optical fiber network) + RSTP [4]
Modbus/TCP basically embeds a Modbus frame into a TCP frame in a simple manner. This is a con-
nection-oriented transaction which means every query expects a response.
This query/response technique fits well with the master/slave nature of ModBus, adding to the de-
terministic advantage that Switched Ethernet offers industrial users.
In the same way as the RS485 base Modbus, every device is identified by a personal address and the
communication goes in “client-server” mode with answering request from the recipient.
The protective relay can be directly connect to the Ethernet network (no gateway, protocol converter
are needed).
For both modules no hw preset are required.
Ethernet
TX connector (RJ45 copper)
RX
FX connector (optical fiber)
TX
RS485
B-
5
RS485
B-
A+
A+
6
ethernet-sch.ai
— Rated values
Inside the Base menu the following parameters can be set:
• Relay reference name
• The the reference for the settings of relay rated currents (phase and residual)
• Primary nominal values, employed for to return measures in the primary values
• Measurements reading mode (primary or relative values)
• Reset delay for Cold Load Pickup[1]
Information for settings:
• Relay reference name.
Alphanumeric mnemonic string (max 16 characters) useful for identification of protected plant.
• Relay nominal frequency fn
This nominal value must be set same as the frequency of the grid.
Example: grid frequency fn = 50 Hz
Relay nominal frequency fn = 50 Hz
• Relay phase rated current for side H and side L InH, InL
This rated value must be set to 1 A or 5 A[2], same as the secondary CTs rated current.
• Rated primary phase current chosen as reference (Inref)
CT’s primary current chosen by relay for amplitude compensation.
• Rated primary phase current chosen as reference (RefSide)
Choice of the reference side for the phase compensation currents
• Number of sides for differential protection (NumSides)
Setting the number of sides on which the differential protection operates (fixed to 2)
• Current matching type (MatchType)
Setting the current compensation type (INT-internal, EXT-external CTs)
• Protected object (ProtObj)
Setting the type of protecting object (fixed to TRANSF)
• Relay residual current - side 1 and side 2 (IEn1 and IEn2)
This rated values must be set by means dip-switch to 1 A or 5 A[3], same as the secondary residual
CT rated current.
• Relay phase-to-phase voltage Un
Two reference voltage are available: UR =100 V and UR =400V
For the first instance the Un relay nominal voltage must be set to the phase-to-phase voltage of the
secondary VTs voltages at grid nominal voltage.
The Un value must calculated as:
Grid nominal voltage Ung where the VTs are included [V]
Un =
Voltage transformer ratio KVT
If VTs with primary rated voltage is equal to the grid voltage divided by √3, the following streamlined
calculus may be used:
Un = VTs secondary rated voltage [V] x √3
Example 1
Ung = 6.9 kV
52 10000 / 3 V NVA100X-D
KVT = = 100
100 / 3 V
Un
NVA100X-D
52 6000 / 3 V
KVT = = 60
100 / 3 V
Un
The relay rated voltage Un may be defined as: Un = Ung /KVT = 6000 / 60 = 100 V
or with the formula: Un = √3 · Uns = √3 ·100 / √3 = 100 V
For the UR = 400 V versions, the relay rated voltage must be set to the grid nominal voltage (direct
measure of the line voltage without VTs).
Example 3
Ung = 400 V
NVA100X-D
52
Un = 400 V
Es3-Un.ai
If open delta VT with primary nominal voltage balances to the grid voltage divided by √3, the follow-
ing streamlined calculus may be used:
UEn = 3 · VT open delta secondary nominal voltage [V] for insulated or impedance-ground neutral
grids.
Example A1
Ung = 6.9 kV Insulated or impedance-ground neutral
52 NVA100X-D
10000 / 3 V
KVT = = 100 · 3
100 / 3 V
UEn
The relay residual nominal voltage UEn must be estimated by means of the general formula:
UEn = √3 · Ung /KVT = √3 · 6900 / (√3 · 100) = 69 V
Example A2
Unp = 6 kV Insulated or impedance-ground neutral
6000 / 3 V NVA100X-D
52 KVT = = 60 · 3
100 / 3 V
UEn
If a VT with primary rated voltage equal to the grid voltage divided by √3 is connected from star neu-
tral to ground, the following streamlined calculus may be used:
UEn = VT secondary rated voltage [V]
Example B1
Ung = 10 kV EsB1-UEn.ai
NVA100X-D
11000 / 3 V
KVT = = 110 / 3 UEn
100 V
The relay residual rated voltage UEn may be estimated by means of the following formula:
UEn = (Ung /√3) /KVT = (10000 /√3) / (110/ √3) = 91 V
Example B2
Ung = 6 kV
NVA100X-D
6000 / 3 V
KVT = = 60 / 3
100 V UEn
The relay residual rated voltage UEn may be estimated by means of the following general formula:
UEn = (Ung /√3) /KVT = (6000 /√3) / (60/ √3) = 100 V
Case C
The relay residual calculated rated voltage UECn is estimated automatically by means of the formula:
UECn = √3∙ Un
Example C1
Ung = 6 kV
NVA100X-D
52 6000 / 3 V
KVT = = 60
100 / 3 V
Un = 100 V
UECn = 173 V
For the example 2 Un = 100 V. UECn is estimated automatically by means of the formula:
UECn = Un ∙ √3 = 100 ∙ √3 = 173 V
NVA100X-D
KTA = 500A/5A=100
InH = 5 A
side H
side L
KTA = 500A/5A=100
InL = 5 A
Es-In.ai
The phase CT primary currents InpH and InpH must be set as: InpH = InpL = 500 A
52
NVA100X-D
The residual CT primary current IEn1p and IEn2p must be set as: IEn1p = IEn2p = 100 A
Example 2
52
NVA100X-D
KTA = 100A / 5A
3x IEn = 5 A
KTA = 100A / 5A
3x IEn = 5 A
Es2-IEn.ai
The residual CT primary current IEn1p and IEn2p must be set as: IEn1p = IEn2p = 100 A
Ung = 6.9 kV
52
10000 / 3 V NVA100-D
KTV = = 100
100 / 3 V
Un = 69 V
Ung = 6 kV
6000 / 3 V NVA100X-D
52
KTV = = 60
100 / 3 V
Un = 100 V
Grid rated voltage Ung = 6 kV
Relay rated voltage Un = 100 V
6000 / 3 V
VTs ratio: KTV = = 60
100 / 3 V Es2-Ung.ai
NVA100X-D
52
Un = 400 V
Es3-Un.ai
Example 1
Ung = 6.9 kV Insulated or impedance-ground neutral
10000 / 3 V NVA100X-D
52 KVT = = 100 · 3
100 / 3 V
UEn = 69 V
The UEnp setting must be adjusted to: UEnp = √3 · Ung = √3 · 6900 V = 11900 V
NVA100X-D - Manual - 02 - 2016 75
FUNCTION CHARACTERISTICS
Example 2
Ung = 10 kV Es3-UEn.ai
NVA100X-D
11000 / 3 V
KVT = = 110 / 3
100 V UEn = 91 V
— Transformer menu
Transformer nominal power (Snt )
Transformer nominal voltage side H (VntH)
Transformer nominal current side H (IntH) [1]
Transformer mismatching factor side H (mH)[3]
Transformer base current side H (IBH)[3]
Transformer grounding side H (GndH)
Transformer connection side H (ConnH)
Transformer vector group side H (VectGroupH)
Transformer nominal voltage side L (VntL )
Transformer nominal current side L (IntL ) [3]
Transformer mismatching factor side L (mL )[3]
Transformer base current side L (IBL )[3]
Transformer grounding side L (GndL )
Transformer connection side L (ConnL )
Transformer vector group side L (VectGroupL )
• The type of excitation system. If powered by the generator terminal the permanent current van-
ishes because the terminals short circuit cancels the terminal voltages and the excitation system
can not therefore produce the field. For short-circuiting terminals most distant from terminals the
voltages does not vanish completely, but in any case the permanent short circuit current is less
than rated value. If the excitation is powered by a separate source or compound type (the short-
circuit current providing energy required to sustain), the permanent current may be some multiple
of rated current (ie: 2 ... 4 In)
• From the generator synchronous reactance Xd. Even with excitation system capable of forcing the
short circuit current, if the action of an automatic voltage regulator AVR is excluded (manual ad-
justment), or the regulator itself is faulty, the permanent current is limited to the value correspond-
ing to the generator synchronous reactance (values near or below the rated current).
Separate excitation
or compound (AVR activated)
2...4 Ing
Separate excitation
or compound (AVR excluded)
Ing
Derived excitation
t
Icc-gen.ai
Typical values:
Xd”=10...30% Td”=20...50 ms
Xd’=20...45% Td’=0.5...3 s
Xd=80...250%
To ensure the generator protection even with the circuit breaker open, the phase CTs are placed on
the star center and the VTs are positioned between the generator terminals and the CB.
Operation and settings
The impedance measurement is made for each phase on the basis of calculation:
Z12=U12 /I L1L
Z23=U23 /I L2L
Z31=U31 /I L3L
where U12, U23 e U31 are the fundamental components of the phase-to-phase voltages and I L1L, I L2L
I L3L are the fundamental components of the phase currents on side L.
Two thresholds, independently adjustable with adjustable delay (.
The second threshold typically used to protect the generator and the first part of the MV transformer
windings, while the first threshold also the HV transformer winding; it must be properly delayed to
obtain time selectivity with distance protections.
A start is issued when at least one of the three impedances goes down the adjustable threshold;
after expiry of the associated operate time ( a trip command is issued; if instead the impedances
increases beyond the threshold, the element it is restored.
TRIP
t Z <<
t Z<
Z<< Z< Z
General operation time characteristic curve for the underimpedance element - 21 t-int-F21.ai
The operating characteristic is a circle with its center located in the source impedance of the plan.
The element trips when the representative point of the calculated impedance is inside the circle
corresponding to the threshold set.
X (p.u. ZN)
NO TRIP
TRIP
TRIP Z <<
Z<
R,X operatingcharacteristic of the impedance protection - 21 F21_char.ai
Both underimpedance elements may be enabled or disabled by setting ON or OFF the State param-
eter inside the Set \ Profile A(o B) \ Underimpedance-21 \ Z< (Z<<) Element \Definite time).
The first threshold trip may be inhibited by start of the second threshold by setting ON the Z<disby
Z<< parameter available inside the Set \ Profile A(o B) \ Underimpedance-21 \ Z< (Z<<) Element \
Setpoints menu.
State Z<< def t Z<< def t Z<<RES State Z< def t Z< def t Z<RES
The elements are enabled in the 20 Hz ... 70 frequency range for each phase, if the corresponding
phase voltage is greater than 1% U n and the current is greater than 5% In.
Since the impedance calculation for the three independent phases, a possible inhibition on stage
has no effect on the rest.
INPUT
Start Z<
t Z< t Z<
Trip Z<
RESET
t
First element underimpedance timers - 21 Timers-F21.ai
VT monitoring (74VT)
The protection elements are blocked off whenever the VT supervision function are active, so that no
unwanted trip can arise if any fault on the VTs secondary circuits (break, fuse trip, etc) are detect;[1]
the 74VT block enabled parameter is available inside the Set \ VT supervision -74VT \ Setpoints
menu.
Note 1 The exhaustive treatment of the VT and CT supervision function may be found inside the CONTROL AND MONITORING section.
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 3 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Note 4 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
TRIPPING M ATRIX
Iph block2 Start
(LED+REL AYS)
Z< Iph block2 output
U 23
Iph/IE block2 output
I L2L Z 23 =U 12/I L 1L t Z<RES
Z 23 ≤ Z < t Z< Block2 IN diagnostic
U 23 ≥1%U n t Z<RES
& ≥1 t Z<
0 T Z< Trip
I L2L ≥ 5%I nL T 0
RESET
Z< Z< Trip
U 31
I L3L Z 31 =U 12/I L 1L
Z 31 ≤ Z <
U 31 ≥1%U n
&
I L3L ≥ 5%I nL
from Z<< element (ON≡Inhibit)
Z< inhibition
≥1
=0 if 20≤f≤70 Hz
IF Start
VT fault (74VT) ≥1 F21S1 Block3
74VT Block
(=0 without fault)
Z< Start
Enable (ON≡Enable) &
Block1 Z< Trip & Z< Block1
&
≥1
Block1 Logic INx t ON INx t OFF & Z< Block2
n.c. INx t ON INx t OFF Block1 input (ON≡Block)
n.o. Block1
T 0 0 T
Binary input INx (x=1...8-16)
TRIPPING M ATRIX
Iph block2 Start
(LED+REL AYS)
Z<<
Iph block2 output
U 23
I L 2L Z 23 =U 12/I L1L t Z<<RES Iph/IE block2 output
Z 23 ≤ Z < t Z<<
Block2 IN diagnostic
U 23 ≥1%U n t Z<<RES
& ≥1 t Z<<
0 T Z<< Trip
I L2L ≥ 5%I n L T 0
RESET
Z<<
U 31 Z<< Trip
I L 3L Z 31 =U 12/I L1L
Z 31 ≤ Z <
U 31 ≥1%U n
&
I L3L ≥ 5%I n L
=0 if 20≤f≤70 Hz
IF Start
VT fault (74VT) ≥1 F21S2 Block3
74VT Block
(=0 without fault)
Z<< Start
Enable (ON≡Enable) &
Block1 Z<< Trip & Z<< Block1
≥1
≥1
Block1 Logic INx t ON INx t OFF & Z<< Block2
n.c. INx t ON INx t OFF Block1 input (ON≡Block)
n.o. Block1
T 0 0 T
Binary input INx (x=1...8-16)
TRIP
t ThALx
t Th> x
Th > x T (°C)
t-int-F26.ai
General operation time characteristic for thermal protection with RTD thermometric probes (26)
For each thermometric probe an alarm (ThALx , where x=1...8 points one of the eight probes) and one
trip adjustable threshold is provided (Th>x ), with adjustable operating time (t ThALx and t Th>x >);if the
measured temperature overcomes the threshold, the relative alarm and/or trip is issued when the
timer expires.
The adjustments are operable in °C.
The probes should be placed in strategic points around the machinery susceptible to the greatest
overheating, such as for example:
- near the generator stator windings, near the step-up transformer windings and/or in the oil, with the
aim of detecting overheating produced by the overload currents,
- near the generator bearings, with the aim of detecting localised overheating due to worn or non-
lubricated bearings.
The Pt100 probes detect the temperature in the range -50 °C...+250 °C (at 0 °C its resistance is 100
ohm); an alarm indicates any interruption or short-circuiting of the probe or related connections to
the MPT module; the information is available inside the Read \ PT100 menu:
2.0s
t ThALx ThALx-K
TRIPPING M ATRIX
T° > Th ALx T 0 ThALx-L
(LED+REL AYS)
Th> x t Th> x
Logic diagram for thermal protection with RTD thermometric probes (26) Fun-F26.ai
All alarm and/or trip elements can be enabled or disabled by setting ON or OFF the ThALx Enable
e Th>x Enable parameters inside the Set \ Profile A(or B) \ Thermal protection with RTD thermo-
metric probes - 26 \ PTx Probe \ ThALx Alarm (ThALx Trip) where x = 1...8.
NVA100X
Pt100 BOARD
A B PT1
Example 1 MPT1
Pt100 T1
GND1
A B
PT2
Example 2 Pt100 MPT2 T2
T3...T7
PT8
Example 3 Pt100 MPT8 T8
In order to compensate the additional resistance introduced by the cables, three wires connection is
recommended (example 1); with only two terminals, probes you must use a shielded cable with three
conductors carrying the schematic example 2 (Pt100 connected to T2 in the figure).
However it is essential that the link between Terminal A and Terminal B is made with cables of the
same type (same link resistance).
For very short connections, two wires (Pt100 connected to T8 example 3) are permitted; the non-
compensated resistance connections resulting in an error proportional to the value of introduced
resistance.
The connection to the probes must be made with three conductors shielded cables and the screen
should be earthed only at one end, preferably on the relay; multiple connections may result in current
circulation on the screen resulting noise on the measure and are therefore to avoid.
It is recommended to position connections to the probe away from power lines to avoid interfer-
ence.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
U12 =|UL1-UL2|
U23 =|UL2 -UL3|
U31=|UL2 -UL1|
Each of three voltages compared with the setting values. The start and trip logic may be selected
OR or AND.
With OR selection, a start is issued when at least one of the three voltages goes down the adjust-
able threshold (START); with AND selection, a start is issued when all the three voltages go down
the adjustable threshold.
After expiry of the associated operate time a trip command is issued; if instead the voltages exceed
the threshold, the element is restored.
The first threshold may be programmed with definite or inverse time according the following char-
acteristic curve:
t=0.75 t U<inv / [1-(U/U<inv)]
Where:
t: operate time
U<inv: threshold setting
t U<inv: operate time setting
Each element can be enabled or disabled by setting ON or OFF the U< Enable parameter inside
the Set \ Profile A(or B) \ Undervoltage-27 \ U< Element \ Setpoints menu and/or the State parameter
inside the Set\Profile A(or B) \ Undervoltage-27 \ U<< Element \ Definite time.
TRIP
tU<
t U <<
0.9U<
U<< U< U
General operation time characteristic curve for the undervoltage elements - 27
The voltage measurement type (Phase-to-phase or phase-to-neutral) and the operating logic (AND
or OR), is adjustable inside the Set \ Profile A(or B) \ Undervoltage-27 \ Common configuration menu
by means the Utype27 parameter; the allowed setting are Uph-ph (phase-to-phase) or Uph-n
(phase-to-neutral).
The corresponding unit are p.u. Un for Uph-ph setting and p.u. En for Uph-n setting.
Utype27 Logic27
State U<<def tU<< def U< Enable U< Curve U<def tU< def U< inv tU< inv
User can disable both 27 protection thresholds from the keyboard. During this command, the trip
output relay (U <and / or U << thresholds) are forced to reset state, the message “27 Disabled” is
displayed and all LEDs blink until the end of the command.
VT monitoring (74VT)
Both the protection elements are blocked off whenever the VT supervision function is active, so
that no unwanted trip can arise if any fault on the VTs secondary circuits (break, fuse trip, etc)
are detect;[2]the Block functions enable from 74VT parameter 74VT-BK-EN is available inside the
Set \ VT supervision -74VT.
For every of the two elements the logic block is available:
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the VT supervision function may be found in the “VT supervision - 74VT” paragraph inside CONTROL AND MONI-
TORING section.
Note 3 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
&
Utype27 U ≤ U<def
Start U<
UL1 ≥1
U12 U< inv State
U<ST-K
TRIPPING M ATRIX
& U<ST-L
(LED+REL AYS)
U ≤ U< inv
U< Curve
t U<def t U<inv
UL2 Logic27
U23 ≥1
& t U<
T 0 U<TR-K
T 0
& U<TR-L
UL3 RESET
U31
Trip U<
(ON≡Inhibit)
U< Inhibition
VT fault (74VT) ≥1
Block 74VT
(=0 without fault) Start U<
Enable (ON≡Enable) &
U<BLK1 Trip U< & BLK1U<
&
Logic diagram concerning the first threshold (U<) of the undervoltage element - 27 Fun-F27_S1.ai
Start U<<
U<< def State
Utype27
U<<ST-K
UL1 &
TRIPPING M ATRIX
U<<ST-L
(LED+REL AYS)
U12 U ≤ U<<def
t U<<def
UL2 Logic27
U23 ≥1
& t U<<
U<<TR-K
T 0
& U<<TR-L
UL3 RESET
U31
Trip U<<
VT fault (74VT) (=0 without fault)
Block 74VT
Start U<<
Enable (ON≡Enable) &
U<<BLK1 Trip U<< & BLK1U<<
&
Logic diagram concerning the second threshold (U<<) of the undervoltage element - 27 Fun-F27_S2.ai
1000
t U <inv = 100 s
100
t U <inv = 10 s
10
t U <inv = 1 s
t U <inv = 0.1 s
0.1
0.01 U /U<inv
0.01 0.1 0.25 1
0.9
Note: match of operating and setting time takes place when U/U<inv = 0.25
Inverse time operating characteristic concerning the first threshold (U<) of the undervoltage element - 27 F_27-Char.ai
The positive sequence voltage is compared with the setting value (U1<def). Voltages under the as-
sociated pickup value are detected and a start is issued. After expiry of the associated operate
time (t U1<def) a trip command is issued; if instead the voltage exceed the threshold, the element is
restored.
The element can be enabled or disabled by setting ON or OFF the State parameter inside the Set \
Profile A(or B) \ Positive sequence undervoltage-27V1 \ U1< Element \ Setpoints menu.
TRIP
t U1 <
U 1< U1
General operation time characteristic for the positive undervoltage element - 27V1 t-int-F27V1.ai
User can disable the 27V1 protection threshold from the keyboard. During this command, the trip
output relay (U <and / or U << thresholds) are forced to reset state, the message “Disabled 27-27V1-
37P-37Q” is displayed and all LEDs blink until the end of the command.
MMI
General logic diagram of the phase positive sequence undervoltage elements - 27V1 all-F27V1.ai
VT supervision (74VT)
The element may be blocked whenever the VT supervision function is active, so that no unwanted trip
can arise if any fault on the VTs secondary circuits (break, fuse trip, etc) are detect;[2]the Block func-
tions enable from 74VT parameter 74VT-BK-EN is available inside the Set \ VT supervision -74VT.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the VT supervision function may be found in the “VT supervision - 74VT” paragraph inside CONTROL AND MONI-
TORING section.
TRIPPING M ATRIX
U1<ST-L
(LED+REL AYS)
&
U1
U 1≤ U1<def t U1<def
Start U1<
&
Enable (ON≡Enable) Trip U1< & BLK1U1<
U1<BLK1
&
Block1 Logic INx t ON INx t OFF
n.c. INx t ON INx t OFF Block1 input (ON≡Block)
n.o. Block1
T 0 0 T
Binary input INx
Trip U1<
BF Enable (ON≡Enable) & U1< BF towards BF logic
U1<BF
Logic diagram concerning the positive sequence undervoltage element - 27V1 Fun-F27V1_S1.ai
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
Preface
The active power is calculated as:
P=UL1IL1cosφL1+ UL2IL2cosφL2+UL3IL3 cosφL3
where:
• UL1, UL2 , UL3 are the fundamental components of the phase-to-neutral voltages
• IL1, IL2 , IL3 are the fundamental components of the phase currents
• cosφL1, cosφL2 , cosφL3 are the phase power factors
φL1, φL2 , φL3 , are the displacement angles of phase currents IL1, IL2 , IL3 respect to the phase voltages
UL1, UL2 , UL3 , (positive when lag currents compared the phase voltages).
TRIP
P 1> P
General operation time characteristic for the directional active overpower element - 32P
TRIP
P 1> P
Caratteristica d’intervento relativa alla soglia P1> della funzione di Massima potenza attiva
direzionale (32P)
TRIP TRIP
P 1> P 1> P
General operation time characteristic for the directional active overpower element - 32P
TRIP TRIP
t P1 >
P 1> P 1> P
General operation time characteristic for the directional active power element - 32P
The active power is compared with the setting value (P1>def, P2>def) powers above the associated
pickup value are detected and a start is issued. After expiry of the associated operate time (t P1> def,
t P2 > def) a trip command is issued; if instead the power drops below the threshold, the element is
restored.
The elements can be enabled or disabled by setting ON or OFF the State parameter inside the
Set \ Profile A(or B) \ Directional active overpower-32P \ P1> Element (P2> Element) \ Definite time
menu.
BF BF
General operation time characteristic for the directional active elements - 32P
An adjustable reset time delay is provided for every threshold (t P1>RES, t P2>RES).
INPUT
P1> Start
t P1>def t P1>def
P1> Trip
RESET
t
P1> element directional active power timers - 32P
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
P 1> Start
TRIPPING M ATRIX
(LED+REL AYS)
P1>DIR P1>def t P1>RES
t P1>def
t P1>RES
P t P1>def
P ≥ P 1> def 0 T P 1> Trip
T 0
RESET
P1> Trip
P 1> Start
Enable (ON≡Enable) &
Block1 P 1> Trip & P 1> Block1
&
Directional active overpower (32P) - First element logic diagram (P1>) Fun_32-P1.ai
P 2 > Start
P 2 > Start
TRIPPING M ATRIX
(LED+REL AYS)
P2>DIR P2>def t P2>RES
t P2 >def
t P2>RES
P t P2>def
P ≥ P 2 > def 0 T P 2 > Trip
T 0
RESET
P 2 > Trip
P 2 > Start
Enable (ON≡Enable) &
Block1 P 2 > Trip & P 2 > Block1
&
Directional active overpower (32P) - Second element logic diagram (P2>) Fun_32-P2.ai
The element can be enabled or disabled by setting ON or OFF the State parameter inside the Set
\ Profile A(or B) \ Undecurrent-37 \ I< Element \ Definite time menu.
TRIP
t< def
I< def I
General operation time characteristic curve for the undercurrent element - 37
The undecurrent element may be disabled by means MMI. During the command, the trip output
relays I<TR-K (with latched or no-latched operation mode and, de-energized or energized logic) are
forced in the rest state, the“37 DISABLED” message is displayed and all the LEDs flash until the
command is ended.
I< Element
Start I<
Logic37
Trip I<
AND
IL1L, IL2L, IL3L
OR
I<BLK1 Start I<
BLK1I<
&
Block1 &
Note 1 The description of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITORING sec-
tion.
& I<ST-K
TRIPPING M ATRIX
IL1L I<ST-L
(LED+REL AYS)
I ≤ I<def
Logic37 t<def
IL2L ≥1
t<def
I<TR-K
& T 0
I<TR-L
IL3L RESET
Start I< Trip I<
Enable (ON≡Enable) &
I<BLK1 Trip I< & BLK1I<
&
Logic diagram concerning the threshold (I<) of the undercurrent element - 37 Fun-F37_S1.ai
Preface
The active power is calculated as:
P=UL1IL1L cosφL1+ UL2IL2L cosφL2+UL3IL3L cosφL3
where:
• UL1, UL2 , UL3 are the fundamental components of the phase-to-neutral voltages
• IIL1L , IL2L , IL3L are the fundamental components of the side L phase currents
• cosφL1, cosφL2 , cosφL3 are the phase power factors
φL1, φL2 , φL3 , are the displacement angles of phase currents IL1, IL2 , IL3 respect to the phase voltages
UL1, UL2 , UL3 , (positive when lag currents compared the phase voltages).
For the conventions on the active power sign please refer to the wiring diagram.
TRIP
P 1< P
General operation time characteristic for the directional active underpower element - 37P
TRIP
P 1< P
General operation time characteristic for the directional active underpower element - 37P
TRIP
P 1< P 1< P
General operation time characteristic for the directional active underpower element - 37P
TRIP TRIP
t P1 <
P 1< P 1< P
General operation time characteristic for the directional active power element - 37P (first element)
Enabling of the CB state control (ON or OFF of the CB-37P parameter) and adjustment of the wait-
ing time following the CB closing (tARM-P< parameter) maj be adjusted inside the Set \ Profile A(or
B) \ Directional active underpower-37P \ P1< Element (P2< Element) \ Common configuration menu.
The elements can be enabled or disabled by setting ON or OFF the State parameter inside the Set
\ Profile A(or B) \ Directional active underpower-37P \ P1< Element (P2< Element) \ Definite time
menu.
Common
P1<DIR P1<def t P1<def P2<DIR P2<def t P2<def
CB-37P t ARM-P<
1st Pickup Element 2nd Pickup Element
General operation time characteristic for the directional active underpower elements - 37P
VT supervision (74VT)
The protection element is blocked off whenever the VT or/and CT supervision func-
tion are active, so that no unwanted trip can arise if any fault on the VTs or/and CTs sec-
ondary circuits (break, fuse trip, etc) are detect;[2]the Block functions enable from
74VT and 74CT parameter (74VT-BK-EN and 74CT-BK-EN) are available inside the
Set \ VT supervision -74VT, and Set \ CT supervision -74CT menus
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the VT and CT supervision function may be found inside the CONTROL AND MONITORING section.
Note 3 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
TRIPPING M ATRIX
State
(LED+REL AYS)
P1<ST-L
P1<DIR P1<def t P1<def
t P1<def
P & P1<TR-K
P≤ P 1< def T 0
P1<TR-L
tARM-P< RESET
(ON enable control)
C B - 37P
ON≡CB closed tARM-P< ≥
P1< Trip
CB CLOSED
T 0
CT fault (74CT)
74CT Block
(=0 without fault)
≥
VT fault (74VT)
74VT Block
(=0 without fault) P1< Start
Enable (ON≡Enable) &
Block1 P1< Trip & P1< Block1
&
TRIPPING M ATRIX
(LED+REL AYS)
P2<ST-L
P2<DIR P2<def
t P2<def
P & t P2<def
P≤ P 2 < def P2<TR-K
T 0
C B - 37P (ON enable control) P2<TR-L
tARM-P< RESET
Directional active underpower (37P) - Second element logic diagram (P2<) Fun-F37P_S2.ai
Generator
Various causes might result in a synchronous generator losing excitation: faults with the exciter or
its supply system, unwanted opening of the field breaker, interruption or short-circuiting of the field
winding, brush faults.
Under such conditions, the generator’s EMF is annulled consequently reducing the active power
supplied, the speed of the unit increases and the machine then operates as an asynchronous gen-
erator absorbing reactive power from the grid. At speeds exceeding the synchronism value, flow is
established which induces low frequency currents in the rotor magnetic circuit, in the field windings
and dampers, thus resulting in an increase in temperature.
With generators with salient poles, the flow reached in a stable operating state is modest, whereby
the generator can remain in such a state for long periods of time without becoming damaged. In-
stead, with smooth rotor generators, the level of flow can reach such values that the reactive current
provided by the grid to the generator assumes values even twice that of the nominal current, with
values proportional to the load initially applied to the generator prior to the loss of excitation.
If the grid to which the generator is connected is not capable of making up the power required by
the generator operating asynchronously (the case for large generators connected to a modest short
circuit power grid), there is a significant reduction in voltage and the system becomes unstable.
Under such conditions, the generator must be quickly disconnected from the grid.
Protection against loss of excitation is obtained using a Underimpedance function with an adjustable
alarm threshold (Alpha40AL angle in the clockwise direction with respect to the axis R) and adjust-
able operating time (tAL) and two definite time trip thresholds, having circular trip characteristics in
the R-X plane where the diameter (XD1, XD2 ), the absolute coordinate of center on the X axis (XC1,
XC2 ) and the operating time (t XC1XD1, t XC2XD2 ) are adjustable.
The alarm threshold is used to indicate loss of excitation with low flow (e.g. generators with salient
poles), at which the generator remains stably with low levels of active power distributed and reac-
tive power absorbed and which can be tolerated for sufficiently long periods of time. This threshold
must be adjusted so as not to trip any alarms during regular operation of the generator.
The first trip threshold, relating to the outer ring, is used to disconnect the generator when loss of
excitation occurs with modest initial load; the diameter of the ring and the concerning operating time
must be adjusted so as to avoid the risk of tripping during stable power swings resulting from the
elimination of grid faults or the synchronisation of the machine.
Instead, when the loss of excitation occurs with a high initial load, whereby the system becomes
highly unstable, the generator is quickly disconnected by means of the second trip threshold.
A minimum consensus voltage may be selected for all three thresholds, having the adjustable thresh-
old USUP<: the consensus has the purpose of avoiding any undesired alarms or tripping of the device
when the machine is operating as a synchronous compensator in over-excitation (as with genera-
tors with hydraulic turbines), or when the generator absorbs reactive power from the capacity of the
transmission lines left connected to the generator without any load.
The Undervoltage consensus enables the three protective device thresholds when all three volt-
ages together drop below the threshold USUP<, otherwise the three thresholds are inhibited.
Motor
When the excitation of a synchronous motor fails not enough synchronizing torque is provided to
keep the rotor locked in step with the stator rotating magnetic field. The machine would then be
excited from the power system and hence be operating as an induction motor.
This results in an increasing level of reactive power being drawn from the power system at a highly
lagging power factor. If the field excitation is too low to meet the load requirements the synchronous
motor can pole slip. An out-of-step (pole slip) condition will subject the motor to undesirable overcur-
rent and pulsating torque, leading to eventual stalling.
Operation as an induction motor under field failure conditions relies upon the ability of the rest of
the system being able to supply the required reactive power to the machine. If the system cannot
supply enough reactive power the system voltage will drop and the system may become unstable.
This could occur if a large motor running at high power suffers a loss of field when connected to a
relatively weak system. To ensure fast tripping under this condition one of the impedance elements
can be used with a short time delay. This can trip the machine quickly to preserve system stability.
This element should have a small diameter to prevent tripping under power swinging conditions. The
second impedance element, set with a larger diameter, can provide detection of field failure under
lightly loaded conditions.
This second element should be time delayed to prevent operation during power swing conditions.
If the OPERATING MODE parameter inside the 40 element menu is set as GENERATOR (with
connection diagram according the fig. 1 and 2), RL1 and XL1 are considered conventionally positive
when active and reactive power are delivered.
If the OPERATING MODE parameter inside the 40 element menu is set as MOTOR (with connec-
tion diagram according the fig. 3), RL1 and XL1 are considered conventionally positive when active
and reactive power are absorbed.
All the convention are applied by the user by means the right connection diagram (see fig. 1-2 and fig.
3) respectively and on the grounds of the OPERATING MODE parameter setting.
Loss of field (40) protection for a synchronous machine normally working as generator (fig.1 and 2) or motor (fig. 3)
TRIP
XD2
XD1
TRIP
ALARM
General operation R-X characteristic for the loss of field element - 40 in the RL1-XL1 plane with
Mode40 = GENERATOR setting
The start of the first element is issued when both the conditions concerning the alarm element are
filled and the R L1 and XL1 computed values are placed inside the circle with equation:
where the absolute coordinate of the center is XC1 and the diameter XD1 are adjustable.
After expiry of the associated operate time (t XC1XD1) a trip command is issued.
where the absolute coordinate of the center is XC2 and the diameter XD2 are adjustable.
After expiry of the associated operate time (t XC2XD2 ) a trip command is issued.[1]
ALARM
TRIP
XD1
XD2
TRIP
XC1
XC2
NO TRIP α α NO TRIP
NO TRIP
General operation R-X characteristic for the loss of field element - 40 in the RL1-XL1 plane with
Mode40 = MOTOR setting
The start of the first element is issued when both the conditions concerning the alarm element are
filled and the R L1 and XL1 computed values are placed inside the circle with equation:
where the absolute coordinate of the center is XC1 and the diameter XD1 are adjustable.
After expiry of the associated operate time (t XC1XD1) a trip command is issued.
Likewise, the start of the second threshold s issued when both the conditions concerning the alarm
element are filled and the R L1 and XL1 computed values are placed inside the circle with equation:
where the absolute coordinate of the center is XC2 and the diameter XD2 are adjustable.
After expiry of the associated operate time (t XC2XD2 ) a trip command is issued[2]
Operating logic
For both operating modes (Motor or Generator):
• A undervoltage consensus may be selected for all three thresholds, having the adjustable thresh-
old USUP<: the consensus has the purpose of avoiding any undesired alarms or tripping of the de-
vice when the machine is operating as a synchronous compensator. The Undervoltage consensus
enables the three protective device thresholds when all three voltages together drop below the
threshold USUP<, otherwise the three thresholds are inhibited.
Note 1 Since the center coordinates XC1 and XC2 are adjustable inside positive range, the center of circle with equations 1) and 2) are always located
along the negative axis XL1
Note 1 Since the center coordinates XC1 and XC2 are adjustable inside positive range, the center of circle with equations 3) and 4) are always located
along the negative axis XL1
USUP <
U12
U12 ≤USUP <
U 31
U 31≤USUP < Undervoltage F40.ai
Logic diagram concerning the undervoltage consent for the loss of field element - 40
In order to set the undervoltage consent, the minimum voltage threshold may be set (STATE ON)
for the USUPU< inside the Set \ Profile A (or B) \ Loss of field-40 \ Common configuration menu.
• Every threshold may be enabled or disabled by setting ON or OFF the 40AL Enable, XC1XD1
Enable, XC2XD2 Enable parameters inside the Set \ Profile A (or B) \ Loss of field-40 \ 40AL Ele-
ment, XC1-XD1 Element , XC2-XD2 Element menus.
• The trip of the 40AL element may be inhibited by the start of the first and/or the second element
by setting ON the Disabling 40AL by XC1-XD1 start, Disabling 40AL by XC2-XD2 start,
parameters available inside the Set \ Profile A(or B) \ Loss of field-40 \ XC1-XD1 Element ( XC2-XD2
Element) menus.
40ALdisbyXC2XD2 40ALdisbyXC1XD1
& &
XC2 XD2 Start XC1 XD1 Start ≥ Alarm inhibition
• The protection elements are blocked off whenever the VT supervision function are active, so that
no unwanted trip can arise if any fault on the VTs secondary circuits (break, fuse trip, etc) are
detect;[1]the Block functions enable from 74VT parameter (74VT-BK-EN) is available inside the
Set \ VT supervision - 74VT menus.
Note 1 The exhaustive treatment of the VT and CT supervision function may be found inside the CONTROL AND MONITORING section.
INPUT
XO1-XD1 Start
t XC1XD1 t XC1XD1
XO1-XD1 Trip
RESET
t
Timers concerning the first threshold of the loss of field element -40 Timers-F40.ai
Alpha Start
Alpha
UL1 Alpha Start
X ≤ tanAlpha · R & R ≤ 0
TRIPPING M ATRIX
(LED+REL AYS)
IL1L Z 1, R , X or
X ≤ -tanAlpha · R & R > 0
UL1 ≥ 10%Un tAL<
Logic diagram concerning the Alarm threshold of the loss of field element - 40 Fun-40_AL.ai
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
X C1 -X D1 Start
XC1 XD1
t XC1XD1-RES
UL1
Z L1, R L1, X L1 R L12 +(XL1 + XC1) 2≤ (XD1/ 2) 2
IL1L t XC1XD1-RES X C1 -X D1 ST-K
&
TRIPPING M ATRIX
0 T X C1 -X D1 ST-L
(LED+REL AYS)
R L12 +(XL1 - XC1) 2≤ (XD1/ 2) 2
=0 if 20≤f≤70 Hz
Block3
VT fault (74VT) ≥1
74VT Block
(=0 without fault)
X C1 -X D1 Start
Enable (ON≡Enable) &
Block1 X C1 -X D1 Trip & X C1 -X D1 Block1
&
Preface
The machine may operate with an unbalanced load due to single-phase or non-linear loads, the trip-
ping of fuses, line interruption in one phase, asymmetric faults, tripping and unipolar reclosing on the
transmission lines.
Application
Protection of synchronous generators and motors. The unbalanced load creates a stator magnetic
field rotating contrariwise to the direction of rotation, which hence corresponds to a magnetic field
rotating at twice the speed with respect to the rotor. Hence, currents are induced at twice the fre-
quency in the rotor magnetic circuit (parasitic currents), the field windings and the damper windings,
responsible for increased loss of iron and copper and hence overheating of the machine.
The unbalanced load protective device estimates the inverse sequence current I2 from the phase
current readings on side L: it makes use of an a adjustable (I2AL>) and delayed (t 2AL >) time indepen-
dent alarm threshold and a thermal trip threshold with constant I2 2 t characteristics, developed so
as to optimally coordinate with the inverse sequence current limits which may be tolerated perma-
nently and for brief periods for each type of machine.
The thermal characteristic of the protective device is: t =Kheat /(I2 /IB) 2 where t is the trip time, mea-
sured from the point of exceeding the adjustable threshold I2 >>, Kheat is the machine thermal time
constant at the inverse sequence current and IB is the base current.
When the inverse sequence current I2 drops below the threshold I2 >>, the protective element resets
after an adjustable time delay Kcool /(I2 >>/IB)2 wherw Kcool is the cooling time constant of the pro-
tected machine at the inverse sequence current.
I2 =(IL1L+e-j120°·IL2L+e+j120°·IL3L )/3
The negative sequence current is compared with the alarm setting value (I2AL>); currents above the
associated pickup value are detected and a start is issued and after expiry of the associated operate
time (t 2AL >, definite time) a trip command is issued; if instead the current drops below the threshold,
the element it restored.
The second threshold (I2 >>) inverse time according the I2 2 t characteristic curve:
• I-squared-t (I 2 t = K): t =Kheat /(I2 /IB) 2 (with I2 ≥ I2 >>)
Where:
t: operate time (t 2min ≤ t ≤ t 2max )
Kheat thermal time constant
IB base current[1]
t2AL>
TRIP
t 2 max
t 2 min
I2 AL > I 2 >> I 2 /I B
General operation characteristic for the negative sequence overcurrent element - 46G t-int-F46.ai
Note 1 Assuming that the secondary rated current of the line CT’s equals the rated current of the NG20 relay, as usually happens, the IB value is the
ratio between the rated current of the protected component (motor or generator) and the primary rated current of the CT’s Inp
t START
I2 IB
I2 >>
Start I2 >>
Trip I2 >>
t 2MAX
Kheat
Conteggio
temporizzatore
All overcurrent elements can be enabled or disabled by setting ON or OFF the I2AL> Enable
and/or I2>> Enable parameters inside the Set \ Profile A(or B) \ Negative sequence overcurrent
- 46G \ I2> Element (I2>> Element) menus.
The trip of I2AL > element may be inhibited by the start of the second element (I2 >>) by set-
ting ON the Disabling I2> by start I2>> (I2>disbyI2>>) parameter available inside the
Set \ Profile A(or B) \ Negative sequence overcurrent-46G \ I2>> Element menu.
I2 >> Enable I2 >> inv Kheat Kcool t 2MIN t 2MAX I2AL > Enable I2AL>def t 2AL>def
Logic diagram concerning the negative sequence overcurrent element - 46G all-F21.ai
All the parameters can be set separately for Profile A and Profile B menus.
Breaker failure (BF)
The trip element can produce the Breaker Failure output if the I2>> BF parameters are set to ON.
The parameters are available inside the Set \ Profile A(or B) \ negative sequence overcurrent - 46G
\ I2>> Element menu.[1]
CT supervision (74CT
The protection element is blocked off whenever the CT supervision function is active, so
that no unwanted trip can arise if any fault on the CTs secondary circuits are detect;[2]
the Block functions enable from 74CT parameter (74CT-BK-EN) is available inside the
Set \ VT supervision - 74VT, and Set \ CT supervision - 74CT menus.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the VT and CT supervision function may be found inside the CONTROL AND MONITORING section.
TRIPPING M ATRIX
(LED+REL AYS)
I 2AL >ST-L
I 2AL>def
t 2AL>def
I2 & t 2AL>def
I2 >≥ IAL > (ON≡Inhibit) I 2AL >TR-K
I2>> Trip T 0
I 2AL >>TR-L
=0 if 20≤f≤70 Hz ≥1 RESET
Block3 I2AL> Trip
I 2AL > Start
Enable (ON≡Enable) &
Block1 I 2AL > Trip & I2AL> Block1
&
Logic diagram concerning the Alarm threshold of the negative sequence overcurrent element - 46G Fun-F46G_AL.ai
TRIPPING M ATRIX
(LED+REL AYS)
I>>ST-L
ON≡Enable I 2 >> element IB K heat t 2max t 2min K cool
I 2 >> Enable I2>> Start=OFF I2 >> inv
I2 I>>TR-K
T 0 0 T
I2 >> inv I2>> Start=ON I>>TR-L
RESET
Enable (ON≡Enable)
I2>>BLK1
&
I2>> Start & I2>> Block1
&
Block1 Logic INx t ON INx t OFF I2>> Trip
Logic diagram concerning the trip threshold of the negative sequence overcurrent element - 46G Fun-F46G_S1.ai
All the parameters can be set separately for Profile A and Profile B.
Block3
The 46G element is disabled (with start of cooling timer) when:
• the measured frequency becomes lower than 20 Hz or higher than 70 Hz or
• all the phase voltages UL1, UL2 , UL3 are lower than 1% En or
• all the phase currents IL1, IL2 , IL3 are lower than 15% In.
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
I2>> = 0.05 IB
1000
t 2MAX = 500 s
100
Kheat = 40.0 s
10
Kheat = 10.0 s
Kheat = 5.0 s
Kheat = 1.0 s
1 Kheat = 0.5 s
Kheat = 0.1 s
0.1
t 2MIN = 0.07 s
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 4 5 10 20 30 50 100
I2 /IB
Operating characteristic concerning the negative sequence element (46G) - with following settings>
- Trip threshold: I2 >> = 0.05 IB
- Minimum operating time: t 2 MIN = 0.07 s
- Maximum operating time: t 2 MAX = 500 s
F_46G-I2t005-Char.ai
- Heating time constant: Kheat = 0.1...40.0 s
I2>> = 0.50 IB
1000
Kheat = 40.0 s
t 2MIN = 100 s
100
Kheat = 10.0 s
Kheat = 5.0 s
10 Kheat = 1.0 s
Kheat = 0.5 s
Kheat = 0.1 s
0.1
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 4 5 10 20 30 50 100
I2 /IB
Operating characteristic concerning the negative sequence element (46G) - with following settings>
- Trip threshold: I2 >> = 0.50 IB
- Minimum operating time: t 2 MIN = 100 s
- Heating time constant: Kheat = 0.1...40.0 s
The maximum operating time is unmeaningful F_46G-I2t05-Char.ai
I2 =(IL1L+e-j120°·IL2L+e+j120°·IL3L )/3
The negative sequence current is compared with the setting values. Currents above the associated
pickup value are detected and a start is issued. After expiry of the associated operate time (t 2 >, t 2 >>)
a trip command is issued; if instead the current drops below the threshold, the element is restored.
The first threshold (I2 >) may be programmed with definite or inverse time according the following
characteristic curves:
• Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t 2 >inv / [(I2 /I2 >inv)0.02 - 1
• Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t 2 >inv / [(I2 /I2 >inv) - 1]
• Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t 2 >inv / [(I2 /I2 >inv)2 - 1]
• Moderately Inverse (ANSI/IEEE type MI): t = t 2 >inv · {0.01 / [(I2 /I2 >inv)0.02 - 1] + 0.023}
• Very Inverse (ANSI/IEEE type VI): t = t 2 >inv · {3.922 / [(I2 /I2 >inv)2 - 1] + 0.098}
• Extremely Inverse (ANSI/IEEE type EI): t = t 2 >inv · {5.64 / [(I2 /I2 >inv)2 - 1] + 0.024}
• I-squared-t (I 2 t = K): t = 16 · t 2 >inv / (I2 /I2 >inv)2
• Electromechanical (EM): t = t 2 >inv · {0.28 / [-0236 · (I2 /I2 >inv)-1 + 0.339]}
Where:
t: operate time
I2 >inv : threshold setting
t 2 >inv : operate time setting
t2> TRIP
t 2 >>
I2> I 2 >> I2
General operation time characteristic curve for the negative sequence overcurrent element - 46M
For all inverse time characteristics, following data applies:
• Asymptotic reference value (minimum pickup value): 1.1 I2 >inv
• Minimum operate time: 0.1 s
• Range where the equation is valid:[1] 1.1 ≤ I2 /I2 >inv ≤ 20
For all definite time elements the upper limit for measuring is 50 In.
All overcurrent elements can be enabled or disabled by setting ON or OFF the I2> Enable and/or
I2>> Enable parameters inside the Set \ Profile A(or B) \ Negative sequence overcurrent - 46 \
I2> Element (I2>> Element) \ Setpoints menus.
Note 1 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
INPUT
I2> Start
t2> t2>
I2> Trip
RESET
t
I2> element timers - 46M Timers-F46M.ai
Each element can produce the Breaker Failure output if the I2> BF and/or I2>> BF parameters
are set to ON. The parameters are available inside the Set \ Profile A(or B) \ negative sequence
overcurrent - 46 \ I2> Element (I2>> Element) \ Setpoints menus.[1]
I2> Enable I2>Curve t2CLP> t2>RES I2> def I2CLP> def t2> def I2> inv I2CLP> inv t2> inv
I2> Element
Start I2>
I2 I2CLP>Mode Trip I2>
Change setting
OFF CLPI2>
Starting control set I2>BF
Element blocking
I2>BF
Trip I2> &
I2>BLK1 Start I2>
BLK1I2>
&
&
Block1
I2>BLK2IN Start I2>
BLK2INI2>
&
&
Block2
I2>BLK2OUT
I2> inhibition BLK2OUT
Start I2> &
I2>> Enable t2CLP>> t2>>RES I2>> def I2CLP>> def t2>> def
General logic diagram of the negative sequence overcurrent elements - 46M all-F46M.ai
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Start I2>
I 2 > def
TRIPPING M ATRIX
(LED+REL AYS)
(Pickup outside CLP)
I 2 > inv ≥1 t 2 >inv
I 2 > Curve t 2 >RES
I2 t 2 >def
I 2 ≥ I 2 > inv t 2 >RES
& t 2>
T 0 0 T I2>TR-K
I 2C L P >def I 2 C L P >inv T 0 I2>TR-L
RESET
(Pickup within CLP)
I 2 ≥ I 2C LP > def (inv )
Trip I2>
A
A = ON - Change setting
B
t2CLP> C
A A
t2CLP> Output t2CLP> B B B = OFF
Starting control set C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
I2CLP>Mode
Trip I2>
BF Enable (ON≡Enable) & I2> BF towards BF logic
I2>BF
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Restarting
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Negative sequence overcurrent (46M) - Logic diagram of the first threshold (I2>) Fun-F46_S1.ai
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Start I2>
I2> Block2 OUT ST-Iph BLK2 BLK2OUT-Iph
Block2 output &
BLK2OUT-IPh-K
I2>BLK2OUT
TRIPPING M ATRIX
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
46MS1_BL-diagram.ai
Negative sequence overcurrent (46M) - Logic diagram of the blocking signals concerning the first element (I2>)
Start I2>
I 2 > def
TRIPPING M ATRIX
(LED+REL AYS)
(Pickup outside CLP)
I 2 > inv ≥1 t 2 >inv
I 2 > Curve t 2 >RES
I2 t 2 >def
I 2 ≥ I 2 > inv t 2 >RES
& t 2>
T 0 0 T I2>TR-K
I 2C L P >def I 2 C L P >inv T 0 I2>TR-L
RESET
(Pickup within CLP)
I 2 ≥ I 2C LP > def (inv )
Trip I2>
A
A = ON - Change setting
B
t2CLP> C
A A
t2CLP> Output t2CLP> B B B = OFF
Starting control set C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
I2CLP>Mode
Trip I2>
BF Enable (ON≡Enable) & I2> BF towards BF logic
I2>BF
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Restarting
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Negative sequence overcurrent (46M) - Logic diagram of the second threshold (I2>>) Fun-F46M_S2.ai
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Start I2>
I2>> Block2 OUT ST-Iph BLK2 BLK2OUT-Iph
Block2 output &
BLK2OUT-IPh-K
I2>>BLK2OUT
TRIPPING M ATRIX
(LED+REL AYS)
Negative sequence overcurrent (46M) - Logic diagram of the blocking signals concerning the second element (I2>>)
The positive sequence voltage is compared with the setting threshold (Us1<); voltages lower than
the associated pickup value are detected and a start is issued if all the phase-to-phase voltages are
larger than an adjustable threshold (Us >).
The element can be enabled or disabled by setting ON or OFF the 47Enable parameter inside the
Set \ Profile A(or B) \ Phase rotation direction check 47 \ 47 Element \ Setpoints menu.
ON≡Enable 47 element
47 Enable
US>
U12
TRIPPING M ATRIX
U12 ≥ U S >
(LED+REL AYS)
U23 & 47TR-K
&
47TR-L
U31
U S1<
Trip 47
U1
U 1≤ U S1<
Enable (ON≡Enable)
47BLK1
& BLK147
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Dθ [p.u.] Dθ [p.u.]
1 1
T+ t T- t
Heating and cooling time constants for the thermal image elements - 49 heat-cool.ai
Furthermore an adjustable initial thermal image value may be preset (by means of ThySetter, binary
input or keyboard commands.
The trip element has an adjustable threshold; with 1.2 DθB setting (ie 1.2 times the overtemperature
corresponding to the nominal operation condition) the corresponding tripping current IB is 1.1 since
the temperature rise is proportional to the square of the current.
The 49 element is provided with two further thresholds DθAL1 and DθAL2, lower than the previous one.
These thresholds, both adjustable, provide an alarm signal to draw attention in the event of anoma-
lous heating, without switching off the motor. One of the above thresholds can be used to prevent
motor starting when heating approaches the trip conditions since the additional heating brought on
by the starting currents would cause the protection to operate.
Operation and settings
The thermal current used for thermal image calculation is:
Ith = √[(max (IL1rms, IL2rms, IL3rms))2+K2·I22]
where IL1rms, IL2rms, IL3rms are the true RMS value of the phase currents on side L, computed tack-
ing account the contribution of the harmonics up to eleventh order.
where the negative and positive sequence currents are computed as:
I1=(IL1L+ej120°·IL2L+e-j120°·IL3L )/3 and I2 =(IL1L+e-j120°·IL2L+e+j120°·IL3L )/3
with e-j120° = -1/2-j√3/2, ej120° = -1/2+j√3/2.
Over the start of the motor, the thermal equivalent current counted for the thermal image is:
Ith = {√[(max (IL1rms, IL2rms, IL3rms))2+K2·I22]} / KST
where KST is an adjustable parameter (1.0...3.0), that lowers the thermal equivalent current during the
start if the setting change mode is selected.
According to a single-body thermal model, the thermal image is based on the differential equation:
dDθ/dt + Dθ/T+ = (Ith /IB)2/T+
where Dθ is the system thermal state as a percentage of base thermal capacity DθB corresponding
to the base current IB[1] and T+ is the heating thermal time constant
During the time that the motor stops running, when the equivalent thermal current goes down the
threshold 0.1IB, the thermal image is computed as:
dDθ/dt + Dθ/T- = 0, where T- is the cooling constant.
The operating characteristic (IEC 60255-8) is:
t =T · ln{[(Ith /IB) 2 - Δθp /ΔθB)] / [(Ith /IB) 2 - Δθ>/ΔθB]}=T · ln{[(Ith /IB) 2 - (Ip /IB) 2] / [(Ith /IB) 2 - Δθ>/ΔθB] =
T · ln{[(Ith /IB) 2 - p2] / [(Ith /IB) 2 - Δθ>/ΔθB]} [1], where:
• t: operating time,
• ln: natural logarithm,
• Dθp and Ip are the thermal image and the corresponding equivalent thermal current before the
overload occurs,
• p=Ip /IB =√(Dθp /DθB: pre-load,
• Δθ>: threshold
Note 1 Assuming that the secondary rated current of the line CT’s equals the rated current of the relay, as usually happens, the IB value is the ratio
between the rated current of the protected component (line, transformer,...) and the primary rated current of the CT’s.
TRIP
Ith /IB
√(D th> / D thetaB)
General operation time characteristic for the thermal image elements - 49MG t-int-F49.ai
Common configuration
&
50-51 inhibition DthAL1BLK1
DthAL1BLK2OUT DthAL2BLK2OUT
Dth>BLK2OUT
BLK2OUT BLK2OUT
BLK2OUT DThAL1 & Dth>AL2 &
Trip Dth> &
The trip element (Dth>) may be inhibited when a start of at least one of the overcurrent element
(50/51) is active, if the Dth>disby50-51 parameter is set ON inside the Set \ Profile A(or B) \ Ther-
mal image-49MG \ Dth> Element menu.
The DthIN parameter sets a minimum level of previous thermal image Dθp when the protection relay
is powered or when a remote (binary input) or local (keyboard or ThySetter) command is issued.
The DthIN parameter may be adjusted inside the Set \ Profile A(or B) \ Thermal image-49MG \
Common configuration menu.
To active the DthIN preset value remotely, a binary input must be programmed as Init DTheta func-
tion inside the Set \ Board 1(2) inputs \ Binary input IN1-1...(IN1-x) menus.
The trip element can produce the Breaker Failure output if the Dth> BF parameters is set to ON. The
parameter is available inside the Set\Profile A(or B) \ Thermal image-49MG \ Dth> Element menu.[1]
The IB setting is adjustable inside the Set \ Profile A(or B) \ Base current IB menu.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Note 3 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
T+ T- DthIN DthAL1
TRIPPING M ATRIX
(LED+REL AYS)
K2 A =“0” B or C
A =“1”
I1 I th dDθ/dt + Dθ/T+ = (Ith/IB)2/T+ DthAL1-K
(I th outside CLP) &
I2 I th = √I 1 2 +K 2 I 2 2 dDθ/dt + Dθ/T- = 0 DthAL1-L
Dθ ≥ DthAL1
K ST
(I th within CLP)
I th / K ST
A
A = ON - Change setting
B
t D t hC L P C
A A
t DthCLP Output t DthCLP B B B = OFF
Starting control set C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
DthCLPMode
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Motor restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Thermal image (49MG) - Logic diagram of the first alarm threshold Fun_49_AL1.ai
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Thermal image (49MG) - Logic diagram of the blocking signals concerning the first alarm element 49AL1_BL-diagram.ai
T+ T- DthIN DthAL2
TRIPPING M ATRIX
(LED+REL AYS)
K2 A =“0” B or C
A =“1”
I1 dDθ/dt + Dθ/T+ = (Ith/IB)2/T+ DthAL2-K
I th (I th outside CLP) &
I2 I th = √I 1 2 +K 2 I 2 2 DthAL2-L
dDθ/dt + Dθ/T- = 0 Dθ ≥ DthAL2
K ST
(I th within CLP)
I th / K ST
A
A = ON - Change setting
B
t D t hC L P C
A A
t DthCLP Output t DthCLP B B B = OFF
Starting control set C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
DthCLPMode
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Motor restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Thermal image (49) - Logic diagram of the second alarm threshold Fun_49_AL2.ai
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Thermal image (49) - Logic diagram of the blocking signals concerning the second alarm element 49AL2_BL-diagram.ai
T+ T- DthIN Dth>
TRIPPING M ATRIX
(LED+REL AYS)
K2 A =“0” B or C
A =“1”
I1 dDθ/dt + Dθ/T+ = (Ith/IB)2/T+ Dth>-K
I th (I th outside CLP) &
I2 I th = √I 1 2 +K 2 I 2 2 Dth>-L
dDθ/dt + Dθ/T- = 0 Dθ ≥ Dth>
K ST
(I th within CLP)
I th / K ST
A
A = ON - Change setting
B
t D t hC L P C
A A
t DthCLP Output t DthCLP B B B = OFF
Starting control set C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
DthCLPMode
Trip Dth>
BF Enable (ON≡Enable) & Dth> BF towards BF logic
Dth>BF
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Motor restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Thermal image (49MG) - Logic diagram of the blocking signals concerning the trip element 49MG_BL-diagram.ai
1000
100
10
1 p=
0 .0
0 .6
0 .8
1 .0
0.1
Operating characteristic concerning the thermal image element (49MG) - T=1 min F_49-1min-Char.ai
100000
10000
1000
p=
0 .0
100 0 .6
0 .8
1 .0
10
Operating characteristic concerning the thermal image element (49MG) - T = 200 min F_49-200min-Char.ai
where:
t: operate time
I(H) >inv : threshold setting
t (H) >inv : operate time setting
The second threshold (I>>) may be programmable with definite or inverse time according to the I2t
curve: t = 16 · t (H) >inv / (I/I>inv)2
The third threshold is definite time.
t>
TRIP
t >>
t >>>
General operation time characteristic for the phase overcurrent elements - 50/51
All overcurrent elements can be enabled or disabled by setting ON or OFF the I(H)> Enable,
I(H)>> Enable and/or II(H)>>> Enable parameters inside the Set \ Profile A(or B) \ Phase
overcurrent-50/51 side H \ I(H)> Element (I(H)>> Element, I(H)>>> Element) \ Setpoints menus.
The first overcurrent element can be programmed with definite or inverse time characteristic by
setting the I(H)>Curve parameter (DEFINITE, IEC/BS A, IEC/BS B, IEC/BS C, ANSI/IEE
MI, ANSI/IEE VI, ANSI/IEE EI, RECTIFIER, I2t, EM) available inside the Set \ Profile A(or B) \
Phase overcurrent-50/51 side H \ I(H)> Element (I(H)>> Element, I(H)>>> Element) \ Setpoints menu.
Note 1 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
All the named parameters can be set separately for Profile A and Profile B (Set \ Profile A(or B)
\ Phase overcurrent-50/51 side H \ I(H)> Element (I(H)>> Element, I(H)>>> Element) \ Setpoints
menus).
An adjustable reset time delay is provided for every threshold (t (H) > RES, t (H) >> RES, t (H) >>> RES).
Timers-F50-51.ai
INPUT
I(H)> Start
t (H) > t (H) >
I(H)> Trip
RESET
t
I> element phase overcurrent timers - 50/51 side H
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
I(H)>BLK2IN
Start I(H)> BLK2INI(H)>
&
&
Block2
I(H)>BLK2OUT
BLK2OUT
I(H)>BLK4 &
Start I(H)>
BLK4OUT
&
Start I>
I(H)>> Enable I(H)>>Curve I(H)CLP>>Mode t(H)CLP>> t(H)>>RES I(H)>> def I(H)CLP>> def t(H)>> def I(H)>> inv I(H)CLP>> inv t(H)>> inv
I(H)>>BLK2IN
Start I(H)>> BLK2INI(H)>>
&
Block2 &
I(H)>>BLK2OUT
BLK2OUT
I(H)>>BLK4 &
Start I>>
BLK4OUT
&
Start I>>
I(H)>>> Enable I(H)CLP>>>Mode t(H)CLP>>> t(H)>>>RES ST-I(H)>>>&ST-U<< I(H)>>> def I(H)CLP>>> def t(H)>>> def
Note 1 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
Nota 2 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
&
I L1H ≥ I (H) > def Start I (H) >
(Pickup outside CLP)
≥1
I (H) > inv State
I(H)>ST-K
I L 1H &
I(H)>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
I L1H ≥ I (H) > inv
t (H) > inv
I (H)C L P > def I (H)C L P > inv I (H) > Curve t (H) > RES
t (H) > def
(Pickup within CLP) t (H) > RES
& t (H) >
I L1H ≥ I (H) > ≥1 T 0 0 T I(H)>TR-K
T 0 I(H)>TR-L
RESET
I L 2H
t (H)C L P >
A = ON - Change setting
A B = OFF
t (H)CLP> Output t (H)CLP> B
CB-State C = ON - Element blocking
T 0 C
≥1
I (H) CLP>Mode
tCLP> 0.1 s
Output tCLP>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Phase overcurrent (50/51) side H - First element logic diagram (I>) Fun_50-51S1.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
I (H) >BLK4 B = OFF t FI-Iph B = OFF I (H) >BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B I> Block4 I/O t FI-Iph I> Block4 OUT A
“0”
Start I(H) >
C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1
50-51S1_BL-diagram.ai
Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of phase elements of ground elements ≥1
0 T
(see BLK4 chapter) (see BLK2OUT chapter) ST-IE BLK4
Block4
Phase overcurrent (50/51) side H - Logic diagram of the blocking signals concerning the first element (I(H)>)
(ON≡Inhibit)
I (H) >> def State I (H) > disbyl>>
& I (H) > inhibition
& Start I (H) >>
I L1H ≥ I (H) >> def
(Pickup outside CLP)
≥1 Start I (H) >>
I (H) >> inv State
I (H) >>ST-K
I L 1H &
I (H) >>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
I L1H ≥ I (H) >> inv
t (H) >> inv
I (H) >> Curve t (H) >> RES
I (H)C L P >>def I (H)C L P >>inv t (H) >> def
(Pickup within CLP) t (H) >> RES
& t (H) >>
I L1H ≥ I (H) > > ≥1 T 0 0 T I (H) >>TR-K
T 0 I (H) >>TR-L
RESET
I L2
Trip I (H) >>
I L3
≥1
ICLP>>Mode
tCLP>> 0.1 s
Output tCLP>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Phase overcurrent (50/51) side H - Second element logic diagram (I(H)>>) Fun_50-51S2.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
Start I>>
I>> Block2 OUT ST-Iph BLK2 BLK2OUT-Iph
Block2 output &
BLK2OUT-IPh-K
I>>BLK2OUT
TRIPPING M ATRIX
(LED+REL AYS)
(ON≡Enable) t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
A = IN A = IN
I (H) >>BLK4 B = OFF t FI-Iph B = OFF I (H) >>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B I(H) >> Block4 I/O t FI-Iph I(H) >> Block4 OUT A
“0”
Start I(H) >> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
50-51S2_BL-diagram.ai
t FI-IE
of phase elements of ground elements ≥1
0 T
(see BLK4 chapter) (see BLK2OUT chapter) ST-IE BLK4
Block4
Phase overcurrent (50/51) side H - Logic diagram of the blocking signals concerning the second element (I(H)>>)
TRIPPING M ATRIX
A ST-I>>>&ST-U<< = OFF I (H) >>>ST-L
(LED+REL AYS)
I L 1H B ST-I>>>&ST-U<< = ON
I (H)C L P >>def I (H)C L P >>inv t (H)>>>RES
t >>>def
A t (H)>>>RES
& ≥1 t >>>def
I L1H ≥ I (H) > > > (Pickup within CLP) ≥1 0 T I>>>TR-K
B
& RESET T 0 I>>>TR-L
RESET
I L 2H
A Trip I (H) >>>
Start U<<def
I L 3H B
t (H)C L P >>>
A = ON - Change setting
A B = OFF
t (H)CLP>>> Output t CLP>>> B C = ON - Element blocking
CB-State
T 0 C
≥1
I (H) CLP>>>Mode
tCLP>>> 0.1 s
Output tCLP>>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T T 0 ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
A = IN A = IN
I (H) >>>BLK4 B = OFF t FI-Iph B = OFF I (H) >>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A t FI-Iph I>>> Block4 OUT A
Block4
“0” B I(H) >>> Block4 I/O
Start I(H) >>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
50-51S3_BL-diagram.ai
t FI-IE
of phase elements of ground elements ≥1
0 T
(see BLK4 chapter) (see BLK2OUT chapter) ST-IE BLK4
Block4
Phase overcurrent (50/51) side H - Logic diagram of the blocking signals concerning the third element (I(H)>>>)
t L R > inv
TRIP
t L R >> def
General operation time characteristic for the locked rotor element - 51LR t-int-51LR.ai
The elements can be enabled or disabled by setting ON or OFF the ILR> Enable, ILR>> Enable
parameters inside the Set \ Profile A(or B) \ Locked rotor - 51LR(48)/14 \ ILR> (ILR>>) Element \ Set-
points menu.
The operating mode may be set according the Speed control unit by setting the ILR>Mode (Mod-
e51LR>, Mode51LR>>) parameters available inside the Set \ Profile A(or B) \ Locked rotor -
51LR(48)/14 \ ILR> Element (ILR>> Element) \ Setpoints menu. With speed control selection (Mod-
e51LR = With speed control), the element is blocked when running is detected (Speed control
= ON acquired by binary input). Conversely, the protection is not locked when a too low speed is
detected (Speed control = OFF).
The Speed control functions must be assigned to the selected binary input inside the Set \ Board1(2)
inputs \ Binary input IN1-1...INx-x menus.
The overcurrent element can produce the Breaker Failure output if the ILR> BF and ILR>> BF
parameter are set to ON. The parameter is available inside the Set \ Profile A(or B) \ Locked rotor
- 51LR(48)/14\ ILR> Element (ILR>> Element) \ Setpoints menu.[1]
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
1000
250
tLR>inv = 200 s
100
tLR>inv = 100 s
10
tLR>inv = 10 s
1 tLR>inv = 1 s
0.1
0.01 I/ILR>inv
1 2 3 4 5 6 7 8 9 10 20 50
IMOT-ST
Setting example: IMOT-ST = 5ILR>inv With input current I = IMOT-ST and setting tLR>inv =10 s the operate time is t = 10 s
Note 1 The inverse time threshold, unlike the definite time, is not in any way conditioned by the CLP activation time
Start ILR>
I L R > inv
ILR>ST-K
TRIPPING M ATRIX
I L1L
(LED+REL AYS)
I L1L ≥ I L R > inv
t L R > inv
I L R > inv
t L R > inv
& ILR>TR-K
I L2L T 0
≥1 ILR>TR-L
I L2L ≥ I L R > inv RESET
Trip ILR>
I L R > inv
I L3L
I L3L ≥ I L R > inv
STOP RUNNING
Mode51LR
Speed control
“0”
Mode51LR> without speed control
Speed control Logic INx t ON INx t OFF
“0” “0”
n.c. INx t ON INx t OFF with speed control
n.o. T 0 0 T ≥1
Binary input INx
Speed control
Trip ILR>
BF Enable (ON≡Enable) & ILR> BF towards BF logic
ILR>BF
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
Locked rotor (first element) - Logic diagram of the blocking signals 51LR_BL-diagram.ai
TRIPPING M ATRIX
I L1L
(LED+REL AYS)
I L1L ≥ I L R >> def
t L R >> def
I L R >> def
t L R >> def
& ILR>>TR-K
I L2L T 0
≥1 “0” ILR>>TR-L
I L2L ≥ I L R >> def RESET
Trip ILR>
I L R >> def
Mode51LR
“0”
I L3L
“0”
I L3L ≥ I L R >> def without speed control
“0” “1”
with speed control
STOP RUNNING
Speed control
Mode51LR>>
Speed control Logic INx t ON INx t OFF
“0”
n.c. INx t ON INx t OFF
n.o. T 0 0 T ≥1
Binary input INx
Speed control
Mode51LR>>
t LRCLP >> “0“ with speed control
“1“ without speed control
Starting t LRCLP >> Output tLRCLP>> &
Starting control set
0 T
Trip ILR>>
BF Enable (ON≡Enable) & ILR>> BF towards BF logic
ILR>>BF
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Motor restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
51LR-S2_BL-diagram.ai
Preface
The short circuit current of the generator can be detected even if the fault current drops below the
nominal current by means the voltage dependant overcurrent protection.
(case of generators with excitation derived from terminals or, in the case of excitation by a separate
supply, but with voltage regulator faults).
The protection may be employed as an alternative to the Underimpedance protective (21).
Current measurement may be performed with phase CT located on the generator star point side or
line side, but location on the star point side is to be preferred so that protection of the machinery is
achieved even with the machine breaker open; for the same reason the CB side of generator is the
VTs preferred position.
Two operation thresholds, that are modified dynamically on the grounds of the measured voltages
,independently adjustable (I-I/U >, I-I/U >>) with adjustable delay (t I-I/U>, t I-I/U>>).
Operation and settings
The following measures are involved:
• U 12 , U 2 3 , U 2 3 fundamental component of phase-to-phase voltages,
• I L1L , I L 2 L , I L 3L fundamental component of line currents on sile L.
TRIP
t -I / U >
t -I / U >>
General operation time characteristic for the voltage controlled overcurrent elements - 51V
The current-voltage trip characteristics of the protective device may be selected from two types:
• voltage controlled, where the current threshold of the protective device is changed from an ad-
justable value corresponding to operation under load (I-I/U > def for the first threshold, I-I/U >> def for
the second threshold) to a lower value corresponding to short-circuiting (K∙I-I/U > def for the first
threshold, K∙I-I/U >> def for the second threshold with adjustable reduction factor K common to both
thresholds), when the voltage drops below an adjustable threshold (U-I/U < common to both thresh-
olds). In addition, the corresponding trip times may be adjusted for each of the two thresholds.
The voltage-controlled feature is used when several generators are connected in parallel over the
same bar. Current above the associated pickup value is detected and a start is issued. After expiry
of the associated operate time (t I-I/U >def, t I-I/U >> def), a trip command is issued; if instead the cur-
rent drops below the threshold, the element is restored.
Current threshold Current threshold
I-I/U> I-I/U>>
KI-I/U> KI-I/U>>
• voltage restraint, where, for the first threshold, if the voltage exceeds the threshold U-I/U-1< then
the adjustable current threshold I-I/U > def is enabled, if the voltage is less than the threshold U-I/U-2<
then the threshold K∙I-I/U > def with adjustable reduction factor K is enabled, whilst if the voltage lies
between the thresholds U-I/U-1< and U-I/U-2< then the current threshold varies between the values
I-I/U > def and I-I/U > def proportionally to the measured voltage. The same for the second threshold;
the current threshold I-I/U >> def with the relevant reduction K∙I-I/U >> def are adjustable. The voltage
threshold U-I/U-1< and U-I/U-2< and reduction factor K adjustments are common to both the thresh-
olds. Current above the associated pickup value is detected and a start is issued. After expiry of
the associated operate time (t I-I/U > def, t I-I/U >> def), a trip command is issued; if instead the current
drops below the threshold, the element is restored. The voltage restraint feature is used when the
I-I/U> I-I/U>>
KI-I/U> KI-I/U>>
All elements can be enabled or disabled by setting ON or OFF the State parameters inside the
Set \ Profile A(or B) \ Voltage controlled-restraint overcurrent 51V \ I-I/U> Element (I-I/U>> Ele-
ment) \ Definite time menus.
The trip of first element may be inhibited by the start of the second element by setting ON the Disable
I-I/U> by start I-I/U>> (I-I/U>disbyI-I/U>>) parameter available inside the Set \Profile A(or B) \
Voltage controlled-restraint overcurrent 51V \ I-I/U>> Element \ Setpoints menu.
INPUT
START I-I/U>
t-I/U>def t-I/U>def
TRIP I-I/U>
RESET
Both the protection elements are blocked off whenever the VT supervision function is active, so
that no unwanted trip can arise if any fault on the VTs secondary circuits (break, fuse trip, etc) are
detect;[1]the Block functions enable from 74VT parameter (74VT-BK-EN) is available inside the
Set \ VT supervision -74VT menu.
Each overcurrent element can produce the Breaker Failure output if the I-I/U> BF, and/or I-I/U>
BF, parameters are set to ON. The parameters are available inside the Set \ Profile A(or B) \ Voltage
controlled-restraint overcurrent 51V \ I-I/U> Element (I-I/U>> Element) \ Setpoints menus.[2]
Note 1 The exhaustive treatment of the VT supervision function may be found inside the CONTROL AND MONITORING section.
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Block3
The 51V elements are enabled with sampling frequency equivalent to the nominal frequency fn
when:
• all the phase voltages UL1, UL2 , UL3 are lower than 1% En or
• all the phase currents IL1L , IL2L , IL3L are lower than 15% In.
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Note 2 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
K
U-I/U <
I-I/U>def KI -I/U> “U ≤ U-I/U<” “U > U-I/U<”
I -I/U>
TRIPPING M ATRIX
I-I/U>ST-L
(LED+REL AYS)
U23 t-I/U>RES
U23 ≤U-I/U< t-I/U>def
IL2L IL2L > threshold t-I/U>RES
& ≥1 t-I/U>def
0 T I-I/U>TR-K
T 0 I-I/U>TR-L
RESET
U 31 I-I/U> Trip
U31 ≤U-I/U<
VT fault (74VT)
74VT Block
(=0 without fault)
I-I/U> Trip
BF Enable (ON≡Enable) & I-I/U>_OUT towards BF logic
BF Element
Voltage controlled overcurrent (51V) - First element logic diagram
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
Start I-I/U>
I-I/U> Block2 OUT ST-Iph BLK2 BLK2OUT-Iph
Block2 output & BLK2OUT-IPh-K
I-I/U>BLK2OUT
TRIPPING M ATRIX
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
Voltage dependant overcurrent (51V) - Logic diagram of the blocking signals concerning the first element 50-51S3_BL-diagram.ai
TRIPPING M ATRIX
I-I/U>>ST-L
(LED+REL AYS)
U23 t-I/U>>RES
U23 ≤ U-I/U< t-I/U>>def
IL2L IL2L > threshold tI-51V>RES
& ≥1 t-I/U>>def
0 T I-I/U>>TR-K
T 0 I-I/U>>TR-L
RESET
U 31 I-I/U>> Trip
U31 ≤ U-I/U<
VT fault (74VT)
74VT Block
(=0 without fault)
I-I/U>> Trip
BF Enable (ON≡Enable) & I-I/U>>_OUT towards BF logic
BF Element
TRIPPING M ATRIX
(LED+REL AYS)
ON IE Iph Block2
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
Start I-I/U>>
I-I/U> Block2 OUT ST-Iph BLK2 BLK2OUT-Iph
Block2 output & BLK2OUT-IPh-K
I-I/U>>BLK2OUT
TRIPPING M ATRIX
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
All other BLK2OUT outputs ≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
of phase elements BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
(see BLK2OUT chapter) ≥1
0 T BLK2OUT-IPh/IE-L
A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All BLK2OUT outputs D = ON IE
t F-IE A
of ground elements ≥1 B BLOUT1
0 T Pilot wire output
(see BLK2OUT chapter) C
ST-IE BLK2 D
Block2 output
Voltage dependant overcurrent (51V) - Logic diagram of the blocking signals concerning the second element 51VS2_BL-diagram.ai
L1
L2
L3
P2
S2
S1
P1 P2
P2 S2
S2
S1
S1 P1
P1
P2
S2
S1
P1
GS GS
3 ∼ 3 ∼
P1 Rs A7
S1
Ru IE 87NHIZ
S2 A8
P2
87N-sch.ai
Restricted earth fault (87N) for parallel connection of generators with earthing resistor
Three operation thresholds, independently adjustable with adjustable delay are available.
The first one may be programmed with definite or inverse time according the IEC and ANSI/IEEE
standard, as well as with EM curve.
The second and third thresholds with definite time.
For each threshold a reset time can be set useful to reduce the clearing time for intermittent faults.
The first threshold trip may be inhibited by start of the second and/or third threshold.
Similarly the second threshold trip may be inhibited by start of the third threshold.
Operation and settings
The residual fundamental frequency current is compared with the setting value. Current above the
associated pickup value is detected and a start is issued. After expiry of the associated operate time
a trip command is issued; if instead the current drops below the threshold, the element is restored.
The first threshold may be programmed with definite or inverse time according the following char-
acteristic curves[1]:
• Standard Inverse Time (IEC 255-3/BS142 type A or SIT): t = 0.14 · t E1>inv / [(IE1/IE1>inv)0.02 - 1]
• Very Inverse Time (IEC 255-3/BS142 type B or VIT): t = 13.5 · t E1>inv / [(IE1/IE1>inv) - 1]
• Very Inverse Time (IEC 255-3/BS142 type B or LIT): t = 120 · t E1>inv / [(IE1/IE1>inv) - 1]
• Extremely Inverse Time (IEC 255-3/BS142 type C or EIT): t = 80 · t E1>inv / [(IE1/IE1>inv)2 - 1]
• Moderately Inverse (ANSI/IEEE type MI): t = t E1>inv · {0.01 / [(IE1/IE1>inv)0.02 - 1] + 0.023}
• Very Inverse (ANSI/IEEE type VI): t = t E1>inv · {3.922 / [(IE1/IE1>inv)2 - 1] + 0.098}
• Extremely Inverse (ANSI/IEEE type EI): t = t E1>inv · {5.64 / [(IE1/IE1>inv)2 - 1] + 0.024}
• Electromechanical (EM): = t E1>inv · {0.28 / [-0236 · (IE1/IE1>inv)-1 + 0.339]}
where:
t: operate time
IE1>: pickup value
t E1>inv : operate time setting
Note 1 The formulas concern to the 50N.1/51N.1 protection on the side 1 and similarly for formulas of to the 50N.2/51N.2 protection on the side 2
t E1 >
TRIP
t E1 >>
t E1 >>>
General operation time characteristic for the residual overcurrent elements - 50N.1/51N.1
For all inverse time characteristics, following data applies:
• Asymptotic reference value (minimum pickup value): 1.1 IE1>
• Minimum operate time: 0.1 s
• Range where the equation is valid:[1] 1.1 ≤ IE1/IE1>inv ≤ 20
• If IE1>inv pickup ≥ 2.5 IE1n, the upper limit is 10 IE1n
For all definite time elements the upper limit for measuring is 10 IE1n.
All residual overcurrent elements can be enabled or disabled by setting ON or OFF the IE1> En-
able, IE1>> Enable and/or IE1>>> Enable parameters inside the Set \ Profile A(or B) \ Re-
sidual overcurrent-50N.1/51N.1 \ IE1> Element (IE1>> Element, IE1>>> Element) \ Setpoints menus.
The first overcurrent element can be programmed with definite or inverse time characteristic by
setting the IE1>Curve parameter (DEFINITE, IEC/BS A, IEC/BS B, IEC/BS C, ANSI/IEE MI,
ANSI/IEE VI, ANSI/IEE EI, EM) available inside the Set \ Profile A(or B) \ Residual overcurrent-
50N.1/51N.1 \ IE1> Element \ Setpoints menu.
The trip of IE1> element may be inhibited by the start of the second and/or third element (IE1>>,
IE1>>>) by setting ON the Disable IE1> by start IE1>>, Disable IE1> by start IE1>>> (IE1>disbyIE1>>,
IE1>disbyIE1>>>) parameters available inside the Set \Profile A(or B) \ Residual overcurrent-
50N.1/51N.1 \ IE1>> Element (IE1>>> Element) \ Setpoints menus.
Similarly the trip of the IE >> element may be inhibited by start of the third element (IE >>>) by setting
ON the Disable IE>> by start IE>>> (IE>>disbyIE>>>) parameter available inside the Set \ Profile
A(or B) \ Residual overcurrent-50N.1/51N.1 \ IE1>>> Element \ Setpoints menu.
All the named parameters can be set separately for Profile A and Profile B
An adjustable reset time delay is provided for every threshold t E1>RES, t E1>>RES, t E1>>>RES).
INPUT
IE1> Start
t E1> t E1>
IE1> Trip
RESET
t
IE> element residual overcurrent (50N.1/51N.1) - Timers Timers-F50N-51N.ai
IE1> Element
IE1 Start IE1>
Trip IE1>
IE1>> Enable IE1CLP>>Mode tE1CLP>> tE1>>RES IE1>> def IE1CLP>> def tE1>>def
IE1>>BLK2IN
Start IE1>> BLK2INIE>>
&
Block2 &
IE1>>BLK2OUT
BLK2OUT
IE1>>BLK4 Start IE1>> &
BLK4OUT
Start IE1>> &
General logic diagram of the residual overcurrent elements side 1 - 50N.1/51N.1 all-F50N-51N.ai
For every of the four thresholds the following block criteria are available:
Logical block (Block1)
If the IE1>BLK1, IE1>>BLK1 and/or IE1>>>BLK1 enabling parameters are set to ON and a
binary input is designed for logical block (Block1), the concerning element is blocked off whenever
the given input is active.[1] The enabling parameters are available inside the Set \ Profile A(or B) \ Re-
sidual overcurrent-50N.1/51N.1 \ IE1> Element (IE1>> Element, IE1>>> Element) \ Setpoints menus,
while the Block1 function must be assigned to the selected binary input inside the Set \ Board1(2)
inputs \ Binary input IN1-1...INx-x) menus.
Note 1 The description of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITORING section
Note 2 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
Nota 1 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
Start IE1>
I E1> def State
&
I E1 ≥ I E1> def IE1>ST-K
(Pickup outside CLP) IE1>ST-L
TRIPPING M ATRIX
≥1
(LED+REL AYS)
I E1> inv State t E1>inv
I E1> Curve t E1>RES
I E1 & t E1>def
I E1 ≥ I E1> inv t E1>RES
& t E1>
T 0 0 T IE1>TR-K
I E1C L P >def I E1C L P >inv T 0 IE1>TR-L
RESET
(Pickup within CLP)
I E1 ≥ I E 1 CL P >
Trip IE1>
≥1 CLP I E1>
t E1C L P >
A = ON - Change setting
A B = OFF
t E1CLP> Output t E1CLP> B
CB-State C = ON - Element blocking
T 0 C
≥1
IE1CLP>Mode
Trip IE1>
BF Enable (ON≡Enable) & IE1> BF towards BF logic
IE1>BF
tE1CLP> 0.1 s
Output tE1CLP>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
of phase elements ≥1
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
(see BLK2OUT chapter) BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
0 T t F-IPh/IE BLK2OUT-IE-L
BLK2OUT-Iph/IE
Start IE1 > t F-IPh/IE BLK2OUT-IPh/IE-K
IE1> Block2 OUT ≥1
Block2 output & 0 T BLK2OUT-IPh/IE-L
IE1>BLK2OUT
(ON≡Enable) A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All other BLK2OUT outputs ≥1 A D = ON IE
t F-IE
of ground elements B BLOUT1
0 T Pilot wire output
C
(see BLK2OUT chapter)
ST-IE BLK2 D
Block2 output
A = IN A = IN
IE1>BLK4 B = OFF t FI-Iph B = OFF IE1>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IE1> Block4 I/O t FI-Iph IE1> Block4 OUT A
“0”
Start IE > C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1
50N-51NS1_BL-diagram.ai
Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of ground elements of phase elements ≥1
0 T
(see BLK4 chapter) (see BLK4chapter) ST-IE BLK4
Block4
Residual overcurrent (50N.1/51N.1) - Logic diagram of the blocking signals concerning the first element (IE1>) sheet 2 of 2
IE1>>ST-K
IE1>>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
I E1>>def State
(Pickup outside CLP)
& t E 1 >>RES
t E 1 >>def
I E1 ≥ I E1>> def
t E 1 >>RES
& t E 1 >>
I E1 0 T IE1>>TR-K
I E1C L P >>def T 0 IE1>>TR-L
RESET
(Pickup within CLP)
Trip IE1>>
I E1 ≥ I E1CL P > > d e f
≥1 CLP IE1>>
t E1C L P >>
A = ON - Change setting
A B = OFF
t ECLP>> Output t ECLP>> B C = ON - Element blocking
CB-State
T 0 C
≥1
IE1CLP>>Mode
Trip IE1>>
BF Enable (ON≡Enable) & IE1>> BF towards BF logic
IE1>>BF
tE1CLP>> 0.1 s
Output tE1CLP>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Residual overcurrent (50N.1/51N.1) - Second element logic diagram (IE1>>) (Sheet 1 of 2) Fun_50N-51NS2.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IE1>>BLK4 B = OFF t FI-Iph B = OFF IE1>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IE1>> Block4 I/O t FI-Iph IE1>> Block4 A
“0”
Start IE1 >> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
50N-51NS2_BL-diagram.ai
Residual overcurrent (50N.1/51N.1) - Logic diagram of the blocking signals concerning the second element (IE>>) Sheet 2 of 2
(ON≡Inhibit)
IE1>>disbylE>>>
& IE1>> inhibition
Start IE1>>>
Start IE1>>>
TRIPPING M ATRIX
I E 1 >>>def State IE1>>>ST-L
(LED+REL AYS)
(Pickup outside CLP)
& t E1>>>RES
t E1>>>def
I E ≥ I E>>> def
t E1>>>RES
& t E1>>>def
I E1 0 T IE1>>>TR-K
I E1C L P >>>def T 0 IE1>>>TR-L
RESET
(Pickup within CLP)
Trip IE1>>>
I E1 ≥ I E1CLP > > > d e f
≥1 CLP IE>>>
t E1C L P >>>
A = ON - Change setting
A B = OFF
t ECLP>>> Output t ECLP>>> B C = ON - Element blocking
CB-State
T 0 C
≥1
IE1CLP>>>Mode
Trip IE1>>>
BF Enable (ON≡Enable) & IE1>>> BF towards BF logic
IE1>>>BF
tE1CLP>>> 0.1 s
Output tE1CLP>>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Residual overcurrent (50N/51N) - Third element logic diagram (IE1>>>) Sheet 1 of 2 Fun_50N-51NS3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IE1>>>BLK4 B = OFF t FI-Iph B = OFF IE1>>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IE1>>> Block4 I/O t FI-Iph IE1>>> Block4 OUT A
“0”
Start IE1 >>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1
50N-51NS3_BL-diagram.ai
Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of ground elements of phase elements ≥1
0 T
(see BLK4 chapter) (see BLK4chapter) ST-IE1 BLK4
Block4
Residual overcurrent (50N.1/51N.1) - Logic diagram of the blocking signals concerning the third element (IE1>>>) Sheet 2 of 2
t EC >> def
t EC >>> def
The first overcurrent element can be programmed with definite or inverse time characteristic by
setting the IEC>Curve parameter (DEFINITE, IEC/BS A, IEC/BS B, IEC/BS C, ANSI/IEE MI,
ANSI/IEE VI, ANSI/IEE EI, EM) available inside the Set \ Profile A(or B) \ Calculated residual
overcurrent-50N(Comp)/51N(Comp) \ IEC> Element \ Setpoints menus.
The trip of IEC> element may be inhibited by the start of the second and/or third element (IEC>>, IE(H)>>>)
by setting ON the Disable IEC> by start IEC>>, Disable IEC> by start IEC>>> (IEC>disbyIEC>>,
IEC>disbyIEC>>>) parameters available inside the Set \ Profile A(or B) \ Calculated residual
overcurrent-50N(Comp)/51N(Comp) \ IEC>>(IEC>>>) Element \ Setpoints menus.
Similarly the trip of the IE(H)>> element may be inhibited by start of the third element (IE(H)>>>) by
Note 1 Inside diagrams and text the IEC is the current residual current calculated by the vector sum of the currents of the selected side (the H or L side)
Note 2 The formulas concern to the 50N.1/51N.1 protection on the side 1 and similarly for formulas of to the 50N.2/51N.2 protection on the side 2
Note 3 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
All the parameters can be set separately for Profile A and Profile B
E’ regolabile un tempo di ripristino costante per ciascuna delle soglie (t E(H) > RES, t E(H) >> RES,
t E(H) >>> RES per il lato H e t E(L) > RES, t E(L) >> RES, t E(L) >>> RES per il lato L).
INPUT
IEC> Start
t EC t EC
IEC> Trip
RESET
t
IEC> element residual overcurrent 50N(Calc)/51N(Calc) - Timers
The operating modes and the CLP Activation time parameters (tECCLP>, tECCLP>> e tEC-
CLP>>>) may be adjusted inside the Set \ Profile A(or B) \ Residual overcurrent-50N(Comp)/
51N(Comp) \ IEC> Element (IEC>> Element, IEC>>> Element) \ Setpoints menus.
The threshold inside CLP (IECCLP>def, IECCLP>inv,....) can be set inside the Set \ Profile A(or B)
\ Residual overcurrent-50N(Comp)/51N(Comp) \ IEC> Element (IEC>> Element, IEC>>> Element) \ Def-
inite time (Inverse time) menus.
For every of the four thresholds the following block criteria are available:
Logical block (Block1)
If the IEC>BLK1, IEC>>BLK1 and/or IEC>>>BLK1 enabling parameters are set to ON and a
binary input is designed for logical block (Block1), the concerning element is blocked off whenever
the given input is active.[2] The enabling parameters are available inside the Set \ Profile A(or B) \
Residual overcurrent-50N(Comp)/51N(Comp) \ IEC> Element (IEC>> Element, IEC>>> Element) \ Set-
points menus, while the Block1 function must be assigned to the selected binary input inside the
Set \ Board1(2) inputs \ Binary input IN1-1...INx-x) menus .
Note 1 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
Nota 2 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
IEC>BLK2IN
Start IEC> BLK2INIEC>
&
&
Block2
IEC>BLK2OUT
BLK2OUT
IEC>BLK4 &
Start IEC>
BLK4OUT
&
Start IEC>
IEC>> Enable IECCLP>>Mode tECCLP>> tEC>>RES IEC>> def IECCLP>> def tEC>>def
IEC>>BLK2IN
Start IEC>> BLK2INIEC>>
&
Block2 &
IEC>>BLK2OUT
BLK2OUT
IEC>>BLK4 Start IEC>> &
BLK4OUT
Start IEC>> &
IEC>>> Element
IEC Start IEC>>
IEC>>>2ndh-REST Trip IEC>>
IEC> disbyIEC>>>
& CLPIE1>>>
Start I2ndh> IEC>> disbyIEC>>> &
Start IEC>>>
&
IEC>>>BLK1 Start IEC>>>
Start IEC>>> BLK1IE1>>>
&
&
Block1
IEC>>>BF
IEC>>>BF
&
IEC>>>BLK2IN Trip IEC>>>
Start IEC>>> BLK2INIEC>>>
&
&
Block2
IEC>>>BLK2OUT
IEC>>>BLK4 BLK2OUT
&
Start IEC>>>
BLK4OUT
&
Start IEC>>>
Note Inside diagrams and text the IEC is the current residual current calculated by the vector sum of the currents
of the selected side (the H or L side)
General logic diagram of the calculated residual current elements - 50N(Comp)/51N(Cmp) all-F50N-51N.ai
Start IEC>
I EC > def State
&
I EC ≥ I EC > def IEC>ST-K
(Pickup outside CLP) IEC>ST-L
TRIPPING M ATRIX
≥1
(LED+REL AYS)
I EC > inv State t EC>inv
IEC > Curve t EC>RES
I EC & t EC>def
I EC ≥ I EC > inv t EC>RES
& t EC>
T 0 0 T IEC>TR-K
IECCLP>def IECCLP>inv T 0 IEC>TR-L
RESET
(Pickup within CLP)
I E C ≥ I EC CL P >
Trip IEC>
≥1 CLPIEC>
t EC C L P >
A = ON - Change setting
A B = OFF
t ECCLP> Output t ECCLP> B
CB-State C = ON - Element blocking
T 0 C
≥1
IECCLP>Mode
Trip IEC>
BF Enable (ON≡Enable) & IEC> BF towards BF logic
IEC>BF
tECCLP> 0.1 s
Output tECCLP>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Note Inside diagrams and text the IEC is the current residual current calculated by the vector sum of the currents
of the selected side (the H or L side)
Calculated residual overcurrent - 50N(Comp)/51N(Comp) - First element logic diagram (IEC>) Sheet 1 of 2
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
of phase elements ≥1
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
(see BLK2OUT chapter) BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
0 T t F-IPh/IE BLK2OUT-IE-L
BLK2OUT-Iph/IE
Start IEC> t F-IPh/IE BLK2OUT-IPh/IE-K
IE1> Block2 OUT ≥1
Block2 output & 0 T BLK2OUT-IPh/IE-L
IEC>BLK2OUT
(ON≡Enable) A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All other BLK2OUT outputs ≥1 A D = ON IE
t F-IE
of ground elements B BLOUT1
0 T Pilot wire output
C
(see BLK2OUT chapter)
ST-IE BLK2 D
Block2 output
A = IN A = IN
IEC>BLK4 B = OFF t FI-Iph B = OFF IEC>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IEC> Block4 I/O t FI-Iph IE1> Block4 OUT A
“0”
Start IEC> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1
50N-51NS1_BL-diagram.ai
Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of ground elements of phase elements ≥1
0 T
(see BLK4 chapter) (see BLK4chapter) ST-IE BLK4
Block4
Calculated residual overcurrent - Logic diagram of the blocking signals concerning the first element (IEC>) Sheet 2 of 2
IEC>>ST-K
IEC>>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
IEC>>def State
(Pickup outside CLP)
& t EC>>RES
t EC>>def
IEC ≥ IEC>> def
t EC>>RES
& t EC>>def
I EC 0 T IEC>>TR-K
IECCLP>>def T 0 IEC>>TR-L
RESET
(Pickup within CLP)
Trip IEC>>
IEC ≥ IECCLP>>def
≥1 CLP IEC>>
≥1
IECCLP>>Mode
Trip IEC>>
BF Enable (ON≡Enable) & IEC>> BF towards BF logic
IEC>>BF
tECCLP>> 0.1 s
Output tECCLP>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Note Inside diagrams and text the IEC is the current residual current calculated by the vector sum of the currents
of the selected side (the H or L side)
Calculated residual overcurrent - 50N(Comp)/51N(Comp) - Second element logic diagram (IEC>>) Sheet 1 of 2
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN
A = IN
IEC>>BLK4 B = OFF t FI-Iph B = OFF IEC>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IEC>> Block4 I/O t FI-Iph IEC>> Block4 OUT A
“0”
Start IEC>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of ground elements of phase elements ≥1
0 T
(see BLK4 chapter) (see BLK4chapter) ST-IEC BLK4
Block4
Calculated residual overcurrent - Logic diagram of the blocking signals concerning the second element (IEC>>) Sheet 2 of 2
(ON≡Inhibit)
IEC>>disbylEC>>>
& IEC>> inhibition
Start IEC>>>
Start IEC>>>
TRIPPING M ATRIX
IEC>>>def State IEC>>>ST-L
(LED+REL AYS)
(Pickup outside CLP)
& t EC>>>RES
t EC>>>def
IEC>>> ≥ IEC>>>def
t EC>>>RES
& t EC>>>def
I EC 0 T IEC>>>TR-K
IECCLP>>>def T 0 IEC>>>TR-L
RESET
(Pickup within CLP)
Trip IEC>>>
IEC ≥ IECCLP>>>def
≥1 CLP IEC>>>
t ECCLP>>>
A = ON - Change setting
A B = OFF
t ECCLP>>> Output t ECCLP>>> B C = ON - Element blocking
CB-State
T 0 C
≥1
IECCLP>>>Mode
Trip IEC>>>
BF Enable (ON≡Enable) & IEC>>> BF towards BF logic
IEC>>>BF
tECCLP>>> 0.1 s
Output tECCLP>>>
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/
BLOCK UNBLOCK BLOCK
Note Inside diagrams and text the IEC is the current residual current calculated by the vector sum of the currents
of the selected side (the H or L side)
Calculated residual overcurrent - 50N(Comp)/51N(Comp) - Third element logic diagram (IEC>>>) Sheet 1 of 2
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IEC>>>BLK4 B = OFF t FI-Iph B = OFF IEC>>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IE1>>> Block4 I/O t FI-Iph IE1>>> Block4 OUT A
“0”
Start IEC>>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
of ground elements of phase elements ≥1
0 T
(see BLK4 chapter) (see BLK4chapter) ST-IE BLK4
Block4
Calculated residual overcurrent - Logic diagram of the blocking signals concerning the third element (IEC>>>) Sheet 2 of 2
The lag power factor (cos ϕ = P/S with Q ≥ 0) and the lead power factor are compared with the setting
value (cos ϕlag<, cos ϕlead<).
TRIP TRIP
NO TRIP NO TRIP
CPhi1<def CPhi1<def
NO TRIP
TRIP TRIP
CPhi1<def Glead
-P +P Glag
CPhi1<def Q Q/2 Q/2 Q
NO TRIP
TRIP TRIP
-Q
General operation characteristic for the out of step element - 55
NO TRIP
CPhi1<def
TRIP TRIP
TRIP
Glead Glag
NO TRIP
CPhi1<def Q Q/2 Q/2 Q
-P +P
NO TRIP NO TRIP
-Q
-Q
General operation characteristic for the out of step element - 55
Common
CB-55
t ARM-CPhi< t ARM-CPhi<
CB Closed &
CB
All the named parameters can be set separately for Profile A and Profile B.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
TRIPPING M ATRIX
CPhi1<ST-L
(LED+REL AYS)
( Q > 0)
c o s G < CPh i1 <
( 0 ≤ G ≤ π)
t CPhi1<
CPh i1 <
C Phi1 < DIR t CPhi1< CPhi1<TR-K
&
A T 0 CPhi1<TR-L
( Q < 0)
G B c o s G < CPh i1 <
C
(-π ≤ G ≤ 0) Trip CPhi1<
A = lag
B = lead
C = lag/lead CPh i1 <
( Q q u a l si a si )
c o s G < CPh i1 <
( - π ≤ G ≤ π)
t ARM-CPhi<
Output t ARM-CPhi<
CB-State
t ARM-CPhi<
&
ON ≡ Enable CB acquisition T 0
CB-55 ≥1
Enable (ON≡Enable)
CPhi1<BLK1
&
Start CPhi1< & BLK1CPhi1<
Logic INx t ON INx t OFF &
Block1 Trip CPhi1<
n.c. INx t ON INx t OFF
n.o. Block1
T 0 0 T
Binary input INx
Block1
Trip CPhi1<
BF Enable (ON≡Enable) & CPhi1< BF towards BF logic
CPhi1<BF
CB-55
t ARM-CPhi< t ARM-CPhi<
Output t ARM-CPhi<
Start enable
t
Minimum power factor - 55 First element 55S1.ai
TRIPPING M ATRIX
CPhi2<ST-L
(LED+REL AYS)
( Q > 0)
c o s G < CPh i2 <
( 0 ≤ G ≤ π)
t CPhi2 <
CPh i2 <
C Phi2 < DIR t CPhi2 < CPhi2<TR-K
&
A T 0 CPhi1<TR-L
( Q < 0)
G B c o s G < CPh i2 <
C
(-π ≤ G ≤ 0) Trip CPhi2<
A = lag
B = lead
C = lag/lead CPh i2 <
( Q q u a l si a si )
c o s G < CPh i2 <
( - π ≤ G ≤ π)
t ARM-CPhi<
Output t ARM-CPhi<
CB-State
t ARM-CPhi<
&
ON ≡ Enable CB acquisition T 0
CB-55 ≥1
Enable (ON≡Enable)
CPhi2<BLK1
&
Start CPhi2< & BLK1CPhi2<
Logic INx t ON INx t OFF &
Block1 Trip CPhi2<
n.c. INx t ON INx t OFF
n.o. Block1
T 0 0 T
Binary input INx
Block1
Trip CPhi2<
BF Enable (ON≡Enable) & CPhi2< BF towards BF logic
CPhi2<BF
CB-55
t ARM-CPhi< t ARM-CPhi<
Output t ARM-CPhi<
Start enable
t
Minimum power factor - 55 Second element 55S2.ai
U12 =|UL1-UL2|
U23 =|UL2 -UL3|
U31=|UL2 -UL1|
Each of three voltages is compared with the setting values (U>, U>>). The start and trip logic may
be selected OR or AND.
With OR selection, a start is issued when at least one of the three voltages overcomes the adjust-
able threshold (START); after expiry of the associated operate time (t U >, t U >>) a trip command is
issued; if instead the voltages drops below the threshold, the element is restored.
With AND selection, a start is issued when all the three voltages overcomes the adjustable thresh-
old; after expiry of the associated operate time (t U >, t U >>) a trip command is issued; if instead the
voltage drops below the threshold, the element is restored.
The first threshold (U>) may be programmed with definite or inverse time according the following
characteristic curve:
t=0.5 t U >inv / [(U/U>inv) - 1]
Where:
t: operate time
U>inv: threshold setting
t U>inv: operate time setting
The first overvoltage element can be programmed with definite or inverse time characteristic by
setting the U>Curve parameter (DEFINITE, INVERSE) available inside the Set \ Profile A(or B) \
Overvoltage-59 \ U> Element \ Setpoints menu.
Each element can be enabled or disabled by setting ON or OFF the U> Enable parameter inside
the Set \ Profile A(or B) \ Overvoltage-59 \ U> Element \ Setpoints menu and/or the State parameter
inside the Set\Profile A(or B) \ Overvoltage-59 \ U>> Element \ Definite time.
t U>
TRIP
t U >>
Utype59 Logic59
State U>>def tU>> def U> Enable U> Curve U>def tU> def U> inv tU> inv
&
Utype59 U ≥ U> def
UL1 ≥1
Start U>
U12 U> inv State
& U>ST-K
TRIPPING M ATRIX
U>ST-L
(LED+REL AYS)
U ≥ U> inv
U> Curve
UL2 Logic59 t U>def t U>inv
U23 ≥1
& t U>
T 0 U>TR-K
& T 0
UL3 U>TR-L
RESET
U31
(ON≡Inhibit) Trip U>
U> Inhibition
Start U>
Enable (ON≡Enable) &
U>BLK1 Trip U> & BLK1U>
&
Logic diagram concerning the first threshold (U>) of the overvoltage element - 59 Fun-F59_S1.ai
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
(ON≡Inhibit)
U>disbyU>>
& U> Inhibition
Start U>>
U>> def State
Utype59
UL1 & U>>ST-K
TRIPPING M ATRIX
U>>ST-L
(LED+REL AYS)
U12 U ≥ U>> def
Logic diagram concerning the second threshold (U>>) of the overvoltage element - 59 Fun-F59_S2.ai
All the parameters can be set separately for Profile A and Profile B.
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
1000
100
10
t U > inv = 10 s
t U > inv = 1 s
0.01 U /U >inv
1.1 1.5 2 3 4
Note: match of operating and setting time takes place when U/U>inv = 1.5
Inverse time operating characteristic concerning the first threshold (U>) of the overvoltage element - 59 F_59-Char.ai
The first threshold (UE >) may be programmed with definite or inverse time according the following
characteristic curve:
t=0.5 t UE > / [(UE /UE >inv) - 1] (direct meaure of UE for VTs input versions) or
t=0.5 t UE > / [(UEC /UE >inv) - 1] (calculated measure of UEC for VTs input versions or ThySensor)
where:
UE : measured residual voltage
UEC : calculated residual voltage
t: operate time
UE >inv: threshold setting
t UE>inv: operate time setting
For the inverse time characteristic, following data applies:
• The operate time setting is referred to an input voltage equal to 1.5 of the pickup value.
• Asymptotic reference value (minimum pickup value): 1.1 UE >inv
• Minimum operate time: 0.1 s
• Range where the equation is valid: 1.1 ≤ UE /UE >inv ≤ 4
• If UE >inv pickup ≥ 0.5 UEn, the upper limit is 2 UEn.
The first residual overvoltage element can be programmed with definite or inverse time character-
istic by setting the UE> Curve parameter (DEFINITE, INVERSE) available inside the Set \ Profile
A(or B) \ Residual overvoltage-59N \ UE> Element \ Setpoints menu.
Each element can be enabled or disabled by setting ON or OFF the UE> Enable parameter inside
the Set \ Profile A(or B) \ Residual overvoltage-59N \ UE> Element \ Setpoints menu and/or the State
parameter inside the Set \ Profile A(or B) \ Residual overvoltage-59N \ UE>> Element \ Definite time.
t UE > TRIP
t UE >>
UE> U E >> UE
General operation time characteristic for the residual overvoltage elements - 59N t-int-F59N.ai
Selection of the measuring criteria of the residual voltage (direct measure or calculated measure) is
available inside the Set \ Profile A(or B) \ Residual overvoltage-59N \ Common configuration menu;
The 3Votype59N parameter may be select as UE (direct measure) or UEC (calculated measure).
Common configuration
3Votype59 N
UE (misura diretta)
UE
UEC (misura calcolata)
74VTint59 N
74VText59 N
& 74VTint-Block
74VTint
& 74VText-Block
74VText
State tUE>>RES UE>>def tUE>> def UE> Enable UE> Curve tUE>RES UE>def tUE> def UE> inv tUE> inv
An adjustable reset time delay is provided for every threshold (t UE>RES, t UE>>RES).
INPUT
UE> Start
t UE> t UE>
UE> Trip
RESET
t
Timers concerning the first element of residual overvoltage protection- 59N Timers-F59N.ai
Note 1 The operating time must be adjusted to a greater value than the 74VT activation time (internal or binary input)
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 3 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
TRIPPING M ATRIX
U E>def State U E >ST-L
(LED+REL AYS)
& U E > Curve t UE>RES
t UE>def t UE>inv
UE ≥ U E>def
t UE>RES
UE ≥1 & t UE>
U E>inv T 0 0 T U E >TR-K
State T 0
U E >TR-L
RESET
&
UE ≥ U E>inv
Trip U E >
(ON≡Inhibit)
U E > Inhibition
Enable (ON≡Enable)
74VTint59N
(ON≡Inhibit) & ≥1
Block 74VT
Logic diagram concerning the first threshold (UE>) of the residual overvoltage element - 59N Fun-F59N_S1.ai
(ON≡Inhibit)
UE>disbyUE>>
& UE> Inhibition
Start U E >>
U E>>def State
U E >>ST-K
UE &
TRIPPING M ATRIX
U E >>ST-L
(LED+REL AYS)
UE ≥ U E>>def
t UE>>RES
t UE>>def
Enable (ON≡Enable)
74VTint59N t UE>>RES
(ON≡Inhibit) & & t UE>>
Block 74VT ≥1 0 T U E >>TR-K
T 0
U E >>TR-L
RESET
Logic diagram concerning the second threshold (UE>>) of the residual overvoltage element - 59N Fun-F59N_S2.ai
t = t UE>inv · 0.5
[(UEC /UE>inv) - 1]
1000
100
t UE >= 100 s
10
t UE >= 10 s
t UE >= 1 s
UE /UE>inv
0.01
1.5 2 3 4 UEC /UE>inv
1.1
Note: match of operating and setting time takes place when UE /UE>inv = 1.5 or UEC /UE>inv = 1.5
Inverse time operating characteristic concerning the first threshold (UE>) of the residual overvoltage element - 59N F_59N-Char.ai
The negative sequence voltage is compared with the setting value (U2>def).
Voltages above the associated pickup value are detected and a start is issued. After expiry of the
associated operate time (t U12 > def) a trip command is issued; if instead the voltage drops below the
threshold, the element is restored.
The element can be enabled or disabled by setting ON or OFF the State parameter inside the Set \
Profile A(or B) \ Negative sequence overvoltage-27V2 \ U2> Element \ Setpoints menu.
TRIP
t U2 > def
U 2 > def U2
General operation time characteristic for the positive overvoltage element - 59V2 t-int-F59V2.ai
U2>BF
U2>BF
&
Trip U2>
U2>BLK1
Start U2> BLK1U2>
&
&
Block1
General operation time characteristic for the positive overvoltage element - 59V2 all-597V2.ai
All the parameters can be set separately for Profile A and Profile B.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
U2>ST-K
TRIPPING M ATRIX
U2>ST-L
(LED+REL AYS)
U 2 > def State t U2>def
& t U2>def
U2 U2>TR-K
U 2 ≥ U 2 > def T 0
U2>TR-L
RESET
Trip U2>
Start U2>
&
Enable (ON≡Enable) Trip U2> & BLK1U2>
U1<BLK1
&
Block1 Logic INx t ON INx t OFF
n.c. INx t ON INx t OFF Block1 input (ON≡Block)
n.o. Block1
T 0 0 T
Binary input INx
Trip U2>
BF Enable (ON≡Enable) & U2> BF towards BF logic
U1<BF
Logic diagram concerning the negative sequence overvoltage element - 59V2 Fun-F59V2_S1.ai
L1
IECH
L2
L3 IE1 IECH
When the fault is outside the protected area I E1 is positive and I ECH is negative ie phasors IE1 e
IECH are opposite in phase.
L1
IECH
L2
L3 IE1 IECH
The residual fundamental frequency current, acquired by means of a current transformer installed in
the starpoint connection to ground - side H, is compared with the stabilization current defined as:
IES = 4 · [|pE·IE1 - ME·IECH| - |pE·IE1 + ME·IECH|] if [|pE·IE1 - ME·IECH| - |pE·IE1 + ME·IECH|] > 0
or
IES = 0 if [|pE·IE1 - ME·IECH| - |pE·IE1 + ME·IECH|] ≤ 0
• IE1 is the residual current phasor - side 1,
• IECH is the calculated residual current (fundamental wave of the phase currents sum) side H,
• pE is the amperometric polarity of the residual current so that it can be corrected any possible re-
versal of polarity; if the amperometric polarity is according the schematic connection diagram the
corresponding setting is C7-C8 POL = NORMAL (pE1 = +1), otherwise is INVERSE (pE1 = -1).
The C7-C8 POL parameter is available inside the Set \ Polarity menu.
• ME is an amplitude compensating factor of residual current calculated by the relay as follows from
the InpH, InH, IEn1p, IEn1n, parameters setting inside the Set \ Base menu:
ME = (InpH / InH) / (IEn1p / IEn1)
The ME factor expresses the value that is multiplied by the residual current calculated by the cur-
rent of phase CTs in order to obtain an amplitude equal to that of the residual current measured by
CT on grounding the neutral in case of earth fault outside the protected area. The relay also checks
that the ME value is ≤ 200 and if this condition is not met, the relay displays a warning and requires
the programming of parameters Inp(H), In(H), IEnp, IEn. Being compensated in amplitude the calculated
residual current, the threshold setting of the element is always referred to the rated current of the CT
on grounding connection of neutral (IE1).
The current iE and iE(H) are conventionally regarded as positive if entrants in their respective ref-
erence terminal of the current input, whether negative terminals. Internal fault in the protected
area, iE and iE(H) are thus both positive, and that the phasors are in phase (assuming the same sys-
tem of earthing of the star and the network), while a fault outside the protected area iE is positive
and iE(H) negative and that the phasors are in phase opposition.
To understand how the 64REF element does work, to simplify, consider PE1 = +1 and ME(H)=1, , accord-
ing to the connection diagram and use of CTs with the same ratio on the grounding neutral-side H.
The trip current is the residual current measured directly by the CT on the starpoint grounding con-
nection.
The stabilization current is computed by the relay using the sum and difference method of the cur-
rents on the grounding path (direct measurement) and line currents (calculated as sum of phase
currents).
-IECH
ϕ IE1-IECH
IE1 IES /4
IECH
IE1+IECH
Three operating conditions with ideal and matched measurement CTs (pE1 = +1 and ME(H) =1) are
considered:
• Earth fault inside the protected zone, powered only from the starpoint
The trip current is equal to IE1 while, being IE(H) = 0, the stabilization current is: IES = 4 · (IE1 - IE1) = 0
The element trips when the fault current exceeds the minimum threshold set IREF > (maximum sen-
sitivity for internal fault).
• Earth fault inside the protected zone, powered from both sides
The trip current is IE1 while, assuming that IECH has the same module and is in phase (ϕ = 0 °) with
IE1, the stabilizing current is:
IES = 4 · (|IE1 - IE1 | - |IE1 + IE1 |) = - 8 IE1 < 0 => IES = 0
Since IES is zero the element trips when the fault current exceeds the minimum threshold set IREF >
(maximum sensitivity for internal earth fault).
• Earth fault outside the protected zone (external fault)
The trip current is still equal to IE1, while being ideally IECH = -IE1 (residual current on the starpoint
grounding out of phase with the phase side H residual current, i.e ϕ = 180 °), the stabilization cur-
rent is: IES = 4 · (|IE1 + IE1 | - |IE1 - IE1 |) = 8 IE1 that being positive and equal to eight times the trip-
ping current, determines the stabilization external fault protection on increasing to infinity the trip
threshold (maximum stability for external earth fault). If any CT is saturated, a displacement angle
ϕ <180 ° is introduced, so the stabilization current is decreased.
In particular, the maximum stability on external fault is obtained with ϕ ≥ 100 °. Conversely for ϕ ≤
90°, the stabilization current is cleared so the maximum sensitivity is achieved.
For ϕ increasing from 90 ° to 100 ° the sensitivity decreases from IREF > to infinity.
The start of the 64REF threshold becomes active when the following condition are contemporane-
ously active:
A) IES(H) ≤ 4 · IREF(H) >
B) IE1 ≥ IES + [IREF >/[1-(IES /4 · IREF >)20] or in normalized form:
[IE1/IREF >] ≥ [IES /IREF >] + [1 /[1-(IES /(4 · IREF >) 20]
C) 64REF Enable = ON
D) 64REF-BLK1 = OFF
where:
• 64REF Enable is the enabling parameter of the 64REF
• IREF > is the minimum threshold setting (max sensitivity) of the 64REF element
• 64REF-BLK1 is the output logic state for the logic block function of the 64REF element.
After expiry of the associated delay time (t REF >) a trip command is issued ; if instead the A), B), C) and
D) conditions current don’t remain valid, the element it is restored.
The restricted ground fault protection is then stabilized against external faults by increasing the
threshold of residual current measured at the grounding of the neutral current with increasing stabi-
lization in accordance with the following characteristics:
IE/IREF> 10
9
8
7
TRIP
6
5
4
3
NO TRIP
2
1
0 IES/IREF>
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
TRIPPING M ATRIX
64REF-ST-L
(LED+REL AYS)
I REF > ON≡Enable
64REF-Enable t REF>
I E1
& t REF>
I EC H I E1 ≥ I REF> · I ES + [I REF>/[1-(I ES/4 · I REF>)20] 64REF-TК-K
T 0 64REF-TК-L
I E S ≤ 4I RE F > RESET
Trip 64REF>
Start 64REF>
Enable (ON≡Enable) &
64REF-BLK1 Trip 64REF> & BLK1IE>>
&
Block1
Block1 Logic INx t ON INx t OFF
n.c. INx t ON INx t OFF
n.o. Block1
T 0 0 T
Binary input INx
Block1
t F-IPh BLK2OUT-IPh-L
of phase elements ≥1 BLK2OUT-IE
t F-IPh BLK2OUT-IE-K
(see BLK2OUT chapter) t F-IPh/IE
T 0 BLK2OUT-IE-L
BLK2OUT-Iph/IE
Start 64REF t F-IPh/IE BLK2OUT-IPh/IE-K
64REF Block2 OUT ≥1
Block2 output & T 0 BLK2OUT-IPh/IE-L
64REF-BLK2OUT A = OFF
(ON≡Enable)
t F-IE B = ON IPh
ModeBLOUT1
C = ON IPh/IE
All other BLK2OUT outputs ≥1 t F-IE A D = ON IE
B BLOUT1
of ground elements T 0 Pilot wire output
C
(see BLK2OUT chapter)
ST-IE BLK2 D
Block2 output
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
The element can be enabled or disabled by setting ON or OFF the 66 Enable parameter inside the
Set \ Profile A(or B) \ Maximum number of starts - 66 menu.
With NST-mode the motor starts are recognized by the relay when the fixed threshold IRUN = 0.10 IB
is overcome, while in TST-mode the time intervals exceeding the lower of the two enabled thresholds
50S/51LR (48) are added cumulatively.
With TST-mode are then incorporated not only the time intervals to the motor start but also time
intervals in which the motor undergoes temporary overloads beyond the locked rotor protection
threshold. With TST-mode at least one threshold should therefore enabled.
The thresholds:
• Maximum number of starts (NTS),
• Maximum real-time of starts (TST),
• Time control window (tC),
• Inhibition time (tIN),
can be adjusted inside the same menu.
INPUT
(NTS or TST)
Threshold
t IN t IN t IN
66 Trip
TST
TYPE66
NST
t
Maximum number of starts (66) - Inhibition timer Timers-F66.ai
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
I R UN = 0.1IB tC N ST Trip 66
IL1...IL3 tC COUNTER
Ma x [ IL1...IL3] ≥ IRUN T 0 t IN
TRIPPING M ATRIX
RESET Type 66
(LED+REL AYS)
t IN 66TR-K
&
tC T ST 0 T 66TR-L
Type66 = NST
Start ILR> tC Max number of starts
Start I LR
≥1 COUNTER
Start ILR>> T
RESET
Type66 = TST
Max starting span
Maximum number of starts (66) Block diagram
Enable (ON≡Enable)
66BLK1
& BLK1 66
Max[IL1...IL3]
min[ILR>,ILR>>]
START
ts1 ts2 ts3
TStart = 0
ts4
Max[IL1...IL3]
IRUN
Start I LR
NStart = 1 NStart = 2
tC
t
Maximum number of starts - logic diagram (66) 66-diagram.ai
t ED >
TRIP
t ED >>
t ED >>>
t ED >>>>
General operation time characteristic for the ground directional overcurrent elements - 67N
Note 1 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
UE
U EC
Trip sector
Half operating sector (toward line)
Characteristic angle
(βE>, βE>>, βE>>>, βE>>>>)
(ΘE>, ΘE>>, ΘE>>>, ΘE>>>>)
Mode67N I ED threshold
I I E2 Characteristic axis
I∙cos I E ≥ I ED threshold Threshold (I ED threshold):
(I ED >, I ED >>, I ED >>>, I ED >>>>) Half operating sector
(M∙I ED >, M∙I ED >>, M∙I ED >>>, M∙I ED >>>>) (βE>, βE>>, βE>>>, βE>>>>)
ΦE o ΦEC
IE
No trip sector
(toward busbar)
BUSBAR NVA100X-D
Operating characteristics of the earth fault overcurrent element - 67N
C7 with module operating mode (I)
I E2 RESIDUAL
IE
CURRENT INPUT
UE
U EC
B9
RESIDUAL Trip sector
UE
VOLTAGE INPUT Half operating sector (toward line) Characteristic angle
(βE>, βE>>, βE>>>, βE>>>>) (ΘE>, ΘE>>, ΘE>>>, ΘE>>>>)
Characteristic axis
Threshold (I ED threshold):
LINE
(I ED >, I ED >>, I ED >>>, I ED >>>>)
(M∙I ED >, M∙I ED >>, M∙I ED >>>, M∙I ED >>>>) Half operating sector
ΦE o ΦEC (βE>, βE>>, βE>>>, βE>>>>)
IE
3Votype67N
No trip sector
UE ΦE o ΦEC I (toward busbar)
ED threshold
Mode67N U EC
I
Operating characteristics of the earth fault overcurrent element - 67N
I E2
I∙cos I E2∙ COS (ϑE-ΦE ) ≥ I ED threshold with projection operating mode ( I∙cos)
For both the operating modes, the polarizing reference used for displacement measure of the re-
sidual current may be selected:
• Direct residual voltage - the measured UE voltage is employed.
• Calculated residual voltage - the calculated UEC voltage is employed, where the fundamental com-
ponent and phase are derived from the instantaneous values of the three input phase-to-neutral
voltages.
Therefore, for both operating mode, the displacement of the residual current phasor IE2 and the
residual voltage phasor (UE or UEC for direct/calculated residual voltage measurement type), positive
for lagging current compared with voltage (ΦE =(∠IE2 - ∠UE , ΦEC =(∠IE2 - ∠UEC).
The residual voltage measurement type may be selected by setting the 3Votype67N parameter,
located inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N \ Common configu-
ration menu. The measurement type is UE (direct measure of residual voltage) or UEC (calculated
residual voltage).
For each of the four thresholds (IED >, IED >>, IED >>>, IED >>>>), the characteristic angle (ϑE>, ϑE>>,
ϑE>>>, ϑE>>>>) may be adjusted (setting range 0…359° common for the three phases).
The the characteristic angle setting (positive when clockwise compared the polarizing voltage)
specifies the angular displacement of the characteristic axis standing for the trip bisector of the
tripping zone. For isolated neutral systems with a 90° characteristic angle setting, faults towards
the LINE are detected, while with a 270° characteristic angle setting, faults towards the BUS are
detected. All the named parameters can be set separately for the four thresholds and for definite or
inverse time settings menu.
For each of the four thresholds (IED >, IED >>, IED >>>, IED >>>>), the half operating sector may be ad-
justed (setting range 0…180° simmetrically regarding the characteristic axis).
All the parameters can be set separately for the four thresholds and for definite or inverse time set-
tings menu.
Malfunctioning of the directional overcurrent elements can be avoided when VTs secondary fault
will arise (fuse or MCB tripping) by switching the overcurrent directional to non directional overcur-
rent protection
The 74VTint67N and 74VText67N parameters may be set as OFF, Block, Not directional inside
the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N \ Common configuration menu,
while the 74VText function must be assigned to the selected binary inputs inside the Set \ Board
1(2) inputs \ Binary input IN1-1...(IN1-x) menus.
For all the four thresholds (common for all thresholds) an insensibility zone may be enabled in the
voltage-current plane.
If enabled, the insensibility zone is user adjustable by means the M multiplier (common for all thresh-
olds); the rectangle defined by the current and voltage thresholds and the same multiplied by M
becomes a No trip zone.
Such insensibility zone may be useful to avoid unwanted trip in the presence of some fixed residual
current and/or voltage (e.g. CT and or VT errors in the residual measurements).
The Insens-Zone (OFF, ON) and M parameters may be adjusted inside the Set \ Profile A(or B) \
Directional earth fault overcurrent-67N \ Common configuration menu.
UE
U EC
TRIP
IE2
I ED >, I ED >>, I ED >>>, I ED >>>>
Voltage/current characteristic concerning the earth fault overcurrent element - 67N
with insensibility zone disabled
UE
U EC
TRIP
M∙U ED >, M∙U ED >>, M∙U ED >>>, M∙U ED >>>>
IE2
I ED >, I ED >>, I ED >>>, I ED >>>> M∙I ED >, M∙I ED >>, M∙I ED >>>, M∙I ED >>>>
Module
If the module principle and the operation mode is not switched to “not directional” (by the 74VT
function), the start of any 67N threshold becomes active when the following A) and B) conditions
are contemporaneously active:
A) in the “Insens-Zone=OFF” operating mode:
- The residual current (IE2 ) fundamental component overcomes the threshold (IED>, IED>>, IED>>>,
Note 1 For each threshold the projection of the residual current phasor on the characteristic axis is: IE2cos(ΘE>-ΦE), IE2cos(ΘE>>-ΦE), IE2cos(ΘE>>>-
ΦE), IE2cos(ΘE>>>>-ΦE) when “direct” residual voltage is selected (UE), or
IE2cos(ΘE>-ΦEC), IE2cos(ΘE>>-ΦEC), IE2cos(ΘE>>>-ΦEC), IE2cos(ΘE>>>>-ΦEC) when “calculated” residual voltage is selected (UEC).
The ΘE , βE and ΦEC symbols are not used inside the Thysetter and MMI menus.
Note 2 For each threshold the projection of the residual current phasor on the characteristic axis is: IE2cos(ΘE>-ΦE), IE2cos(ΘE>>-ΦE), IE2cos(ΘE>>>-
ΦE), IE2cos(ΘE>>>>-ΦE) when “direct” residual voltage is selected (UE), or
IE2cos(ΘE>-ΦEC), IE2cos(ΘE>>-ΦEC), IE2cos(ΘE>>>-ΦEC), IE2cos(ΘE>>>>-ΦEC) when “calculated” residual voltage is selected (UEC).
The ΘE , βE and ΦEC symbols are not used inside the Thysetter and MMI menus.
INPUT
IED> Start
t ED> t ED>
IED> Trip
RESET
t
67N element timers - first element
Breaker failure (BF)
Each directional earth fault element can produce the Breaker Failure output if the IED> BF, IED>>
BF, IED>>> BF and/or IED>>>> BF parameters are set to ON. The parameters are available
inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N \ IED> Element (IED>> Ele-
ment, IED>>> Element, IED>>> Element) \ Setpoints menus.[1]
If the CLP function (Cold Load Pick-up) is enabled for threshold change, the selected threshold may
be changed for an adjustable time interval, starting from the circuit breaker closure.
This operating mode (ON-Change setting = IEDCLP> Mode, IEDCLP>> Mode, IED-
CLP>>> Mode, IEDCLP>>>> Mode) and the concerning operating time within the CLP (tED-
CLP>, tEDCLP>>, tEDCLP>>>, tEDCLP>>>>) may be adjusted inside the Set \ Profile
A(or B) \ Directional earth fault overcurrent-67N \ IED> Element (IED>> Element, IED>>> Element,
IED>>> Element) \ Setpoints menus, whereas the operating thresholds within the CLP ( IEDCLP>def,
IEDCLP>inv,....) may be adjusted inside the Set \ Profile A(or B) \ Directional earth fault overcur-
rent-67N \ IED> Element (IED>> Element, IED>>> Element, IED>>> Element) \ Definite time (Inverse
time) menus.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Note 2 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
Nota 3 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
IED>> Enable IED>>Curve IEDCLP>>Mode tEDCLP>> tED>>RES IED>>def IEDCLP>>def tED>> def IED>>inv IEDCLP>>inv tED>> inv
IEDCLP>def IEDCLP>inv
3V o Insens-Zone OFF
U ED>def State
≥ IEDCLP> TRIP
&
≥ U ED>def Insens-Zone
IE2
O FF
≥1 &
3V o ON M sheet 3
U ED>inv State
3 V o Insens-Zone ON
& Angle Semisector
≥ U ED>inv TRIP
3Vo
I E2 ΦE inside trip sector
IE2
3V o
I E2 ΦE inside trip sector &
I ED>def State
&
≥ I ED>def
≥1
I ED>inv State
CLP
A
&
I E2 A =“OFF” A =“ON” A = ON - Change setting within CLP
≥ I ED>inv
&
≥1
IEDCLP>def IEDCLP>inv
I ED>def State
≥ IEDCLP> &
≥ M∙I ED>def
≥1
U ED>def State
I ED>inv State
& &
≥ M∙U ED>def I E2
≥ M∙I ED>inv
≥1
3V o
U ED>inv State CLP
IEDCLP>def IEDCLP>inv A
& A =“OFF” A =“ON”
A = ON - Change setting within CLP
≥ M∙U ED>inv ≥ M∙IEDCLP> &
U ED>def State
&
≥ U ED>def
≥1
3Vo State
U ED>inv
&
≥ U ED>inv
Ground directional overcurrent (67N) - First element logic diagram (IED>) - Module operating mode (sheet 1 of 4) 67NS1-module.ai
Settore intervento
(direzione linea) I ED>def State Mode67N 3Votype67N
Angolo caratteristico I UE
& CLP I E2 3V o
I∙cos U EC
Semiasse caratteristico I E ∙cosϕ ≥ I ED>def
≥1 M
Semiampiezza settore A =“OFF” Insens-Zone
I ED>inv State
soglia I ED angolare d’intervento
ΦE o ΦEC A O FF
&
IE I E2 ON ≥ M∙threshold
I E ∙cosϕ ≥ I ED>inv A =“ON”
IE2
3Vo
I E2 ΦE inside trip sector
I E2 &
I ED>def State I E2 ∙cosϕ ≥ 0
&
I E2 ∙cosϕ ≥ I ED>def
≥1
I ED>inv State
CLP
A
&
I E2 A =“OFF” A =“ON” A = ON - Change setting within CLP
I E2 ∙cosϕ ≥ I ED>inv
&
≥1
IEDCLP>def IEDCLP>inv
I ED>def State
U ED>def State
&
≥ U ED>def
≥1
3Vo State
U ED>inv
&
≥ U ED>inv
Ground directional overcurrent (67N) - First element logic diagram (IED>) - Projecting operating mode (sheet 2 of 4) 67NS1-proiezione.ai
Mode67N 3Votype67N
I UE
I E2 3Vo
I∙cos U EC
M
Insens-Zone
OFF
ON ≥ M∙threshold
D =“modulo” IED>ST-K
M IED>ST-L
(sheet 1) Mode67N
TRIPPING M ATRIX
(LED+REL AYS)
D D
C C t ED>inv
D =“modulo” C =“proiezione” I ED> Curve t ED>RES
t ED>def
C =“proiezione”
(sheet 2) t ED>RES
A & t ED>def/inv
T 0 0 T IED>TR-K
B T 0 IE>TR-L
RESET
A
Trip IED>
B
I ED>def State
A = Directional B = Non-directional
&
≥ I ED>def
I E2
IEDCLP>def
IEDCLP>Mode
74VTint/ext67N
Non-directional Block by 74VT (ON≡Block)
Internal or external
74VT
OFF
Trip IED>
BF Enable (ON≡Enable) & I ED> BF towards BF logic
I ED>BF
Ground directional overcurrent (67N) - First element logic diagram (IED>) (sheet 3 of 4) Fun_67NS1-3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IED>BLK4 B = OFF t FI-Iph B = OFF IED>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IED> Block4 I/O t FI-Iph IED> Block4 OUT A
“0”
Start IED > C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
67NS1_BL-diagram.ai
Ground directional overcurrent (67N) - Logic diagram of the blocking signals concerning the first element (IED>) (sheet 4 of 4)
IEDCLP>>def IEDCLP>>inv
3V o Insens-Zone OFF
U ED>>def State
≥ IEDCLP>> TRIP
&
≥ U ED>def Insens-Zone
IE2 O FF
≥1 &
3V o ON M sheet 3
U ED>>inv State 3 V o Insens-Zone ON
I ED>>def State
&
≥ I ED>def
≥1
I ED>>inv State
CLP
A
&
I E2 A =“OFF” A =“ON” A = ON - Change setting within CLP
≥ I ED>>inv
&
≥1
IEDCLP>>def IEDCLP>>inv
I ED>>def State
≥ IEDCLP>> &
≥ M∙I ED>def
≥1
U ED>>def State
I ED>>inv State
& &
≥ M∙U ED>def I E2
≥ M∙I ED>>inv
≥1
3V o
U ED>>inv State CLP
IEDCLP>>def IEDCLP>>inv A
& A =“OFF” A =“ON”
A = ON - Change setting within CLP
≥ M∙U ED>>inv ≥ M∙IEDCLP>> &
U ED>>def State
&
≥ U ED>>def
≥1
3Vo State
U ED>>inv
&
≥ U ED>>inv
Ground directional overcurrent (67N) - Second element logic diagram (IED>>) - Module operating mode (sheet 1 of 4) 67NS2-module.ai
Settore intervento
(direzione linea) I ED>>def State Mode67N 3Votype67N
Angolo caratteristico I UE
& CLP I E2 3V o
I∙cos U EC
Semiasse caratteristico I E ∙cosϕ ≥ I ED>>def
≥1
Semiampiezza settore A =“OFF” M
I ED>>inv State Insens-Zone
soglia I ED angolare d’intervento
ΦE o ΦEC & A O FF
IE2 I E2 A =“ON” ON ≥ M∙threshold
I E ∙cosϕ ≥ I ED>>inv
3Vo
I E ∙cosϕ ≥ I EDCLP>> Insens-Zone OFF
U ED>>def State
TRIP
& I E2
I E ∙cosϕ ≥ 0 Insens-Zone
≥ U ED>>def IE2
& O FF
≥1 P sheet 3
3V o ON
U ED>>inv State
3 V o Insens-Zone ON
Angle Semisector
&
≥ U ED>>inv 3Vo TRIP
IE2
3Vo
I E2 ΦE inside trip sector
I E2 &
I ED>>def State I E ∙cosϕ ≥ 0
&
I E ∙cosϕ ≥ I ED>def
≥1
I ED>>inv State
CLP
A
&
I E2 A =“OFF” A =“ON” A = ON - Change setting within CLP
I E ∙cosϕ ≥ I ED>>inv
&
≥1
IEDCLP>>def IEDCLP>>inv
I ED>>def State
U ED>>def State
&
≥ U ED>>def
≥1
3Vo State
U ED>>inv
&
≥ U ED>>inv
67NS2-proiezione.ai
Ground directional overcurrent (67N) - Second element logic diagram (IED>>) - Projecting operating mode (sheet 2 of 4)
Mode67N 3Votype67N
I UE
I E2 3Vo
I∙cos U EC
M
Insens-Zone
OFF
ON ≥ M∙threshold
D =“modulo” IED>>ST-K
M IED>>ST-L
(sheet 1) Mode67N
TRIPPING M ATRIX
(LED+REL AYS)
D D
C C t ED>>inv
D =“modulo” C =“proiezione” I ED>> Curve t ED>>RES
t ED>>def
C =“proiezione”
(sheet 2) t ED>>RES
A & t ED>>def/inv
T 0 0 T IED>>TR-K
B T 0 IE>>TR-L
RESET
A
Trip IED>>
B
I ED>>def State
A = Directional B = Non-directional
&
≥ I ED>>def
I E2
IEDCLP>>def
IEDCLP>>Mode
74VTint/ext67N
Non-directional Block by 74VT (ON≡Block)
Internal or external
74VT
OFF
Trip IED>>
BF Enable (ON≡Enable) & I ED>> BF towards BF logic
I ED>>BF
Ground directional overcurrent (67N) - Second element logic diagram (IED>>) (sheet 3 of 4) Fun_67NS2-3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IED>>BLK4 B = OFF t FI-Iph B = OFF IED>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IED>> Block4 I/O t FI-Iph IED>> Block4 OUT A
“0”
Start IED >> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
67NS2_BL-diagram.ai
Ground directional overcurrent (67N) - Logic diagram of the blocking signals concerning the second element (IED>>) (sheet 4 of 4)
M
Insens-Zone I E2 IEDCLP>>>def CLP
OFF A
ON ≥ M∙threshold A =“OFF” A =“ON”
≥ IEDCLP>>>def A = ON - Change setting within CLP
3V o Insens-Zone OFF
TRIP
Angle Semisector
TRIP
3Vo
I E2 ΦE inside trip sector
IE2
3V o
I E2 ΦE inside trip sector &
I ED>>>def State
&
≥ I ED>>>def
I E2 IEDCLP>>>def CLP
A
A =“OFF” A =“ON” A = ON - Change setting within CLP
≥ IEDCLP>>>def
&
≥1
U ED>>>def State
&
3V o
≥ M∙U ED>>>def U ED>>>def State
&
3Vo &
≥ M∙U ED>>>def
I ED>>>def State
&
≥ M∙I ED>>>def
IE IEDCLP>>>def CLP
A
A =“OFF” A =“ON”
≥ M∙IEDCLP>>def A = ON - Change setting within CLP
Ground directional overcurrent (67N) - Third element logic diagram (IED>>>) - Module operating mode (sheet 1 of 4) 67NS3-module.ai
Semiampiezza settore
M soglia I ED angolare d’intervento
Insens-Zone ΦE o ΦEC
OFF IE2
ON ≥ M∙threshold
Settore non intervento
(direzione sbarre)
I ED>>>def State
&
I E2 ∙cosϕ ≥ I ED>>>def
I E2
IEDCLP>>>def A =“OFF” A =“ON”
A A = ON - Change setting within CLP
TRIP
I E2 Insens-Zone
U ED>>>def State I E ∙cosϕ ≥ 0
IE2
& O FF
& P sheet 3
3V o ON
≥ U ED>>>def 3 V o Insens-Zone ON
Angle Semisector
TRIP
3Vo
I E2 ΦE inside trip sector
IE2
3Vo
I E2 ΦE inside trip sector
I E2 &
I ED>>>def State I E ∙cosϕ ≥ 0
&
I E2 ∙cosϕ ≥ I ED>>>def
I E2 IEDCLP>>>def CLP
A
A =“OFF” A =“ON” A = ON - Change setting within CLP
I E2 ∙cosϕ ≥ I EDCLP>>>def &
≥1
I ED>>>def State
&
I E2 ∙cosϕ ≥ M∙I ED>>>def
I E2 IEDCLP>>>def &
A
U ED>>>def State
I E2 ∙cosϕ ≥ M∙I EDCLP>>>def A =“OFF” A =“ON”
& A = ON - Change setting within CLP
3V o
≥ M∙U ED>>>def
U ED>>>def State
&
3Vo
≥ U ED>>>def
Ground directional overcurrent (67N) - Third element logic diagram (IED>>>) - Projecting operating mode (sheet 2 of 4)
Mode67N 3Votype67N
I UE
I E2 3Vo
I∙cos U EC
M Start IED>>>
Insens-Zone
OFF IED>>>ST-K
ON ≥ M∙threshold IED>>>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
t ED>>>RES
t ED>>>def
ON≡Enable IED>>> directional earth fault
IED>>> Enable t ED>>>RES
& t ED>>>def
0 T IED>>>TR-K
T 0 IE>>>TR-L
D =“modulo”
M RESET
(sheet 1)
Trip IED>>>
Mode67N
D D
A A
C C
B B
D =“modulo” C =“proiezione”
A = Directional B = Non-directional
C =“proiezione”
(sheet 2)
I ED>>>def State
&
≥ I ED>>>def
I E2
Non-directional
IEDCLP>>>def (from 74VT)
≥ I EDCLP >>>def
IEDCLP>>>Mode
74VTint/ext67N
Non-directional Block by 74VT (ON≡Block)
Internal or external
74VT
OFF
Trip IED>>>
BF Enable (ON≡Enable) & I ED>>> BF towards BF logic
I ED>>>BF
Ground directional overcurrent (67N) - Third element logic diagram (IED>>>) (sheet 3 of 4) Fun_67NS3-3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IED>>>BLK4 B = OFF t FI-Iph B = OFF IED>>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IED>>> Block4 I/O t FI-Iph IED>>> Block4 OUT A
“0”
Start IED >>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
67NS3_BL-diagram.ai
Ground directional overcurrent(67N) - Logic diagram of the blocking signals concerning the third element (IED>>>) (sheet 4 of 4)
M
Insens-Zone I E2 IEDCLP>>>>def CLP
OFF A
ON ≥ M∙threshold A =“OFF” A =“ON”
≥ IEDCLP>>>>def A = ON - Change setting within CLP
3V o Insens-Zone OFF
TRIP
Angle Semisector
TRIP
3Vo
I E2 ΦE inside trip sector
IE2
3V o
I E2 ΦE inside trip sector &
I ED>>>>def State
&
≥ I ED>>>>def
I E2 IEDCLP>>>>def CLP
A
A =“OFF” A =“ON” A = ON - Change setting within CLP
≥ IEDCLP>>>>def
&
≥1
U ED>>>>def State
&
3V o
≥ M∙U ED>>>>def U ED>>>>def State
&
3Vo &
≥ U ED>>>>def
I ED>>>>def State
&
≥ M∙I ED>>>>def
I E2 IEDCLP>>>>def CLP
A
A =“OFF” A =“ON”
≥ M∙IEDCLP>>>>def A = ON - Change setting within CLP
Ground directional overcurrent (67N) - Fourth element logic diagram (IED>>>>) - Module operating mode (sheet 1 of 4) 67NS4-module.ai
M Semiampiezza settore
Insens-Zone soglia I ED angolare d’intervento
ΦE o ΦEC
OFF IE
ON ≥ M∙threshold
&
I E ∙cosϕ ≥ I ED>>>>def
I E2
IEDCLP>>>>def A =“OFF” A =“ON”
A A = ON - Change setting within CLP
TRIP
I E2 Insens-Zone
U ED>>>>def State I E ∙cosϕ ≥ 0
IE2
& O FF
& P sheet 3
3V o ON
≥ U ED>>>>def 3 V o Insens-Zone ON
Angle Semisector
TRIP
3Vo
I E2 ΦE inside trip sector
IE2
3Vo
I E2 ΦE inside trip sector
I E2 &
I ED>>>>def State I E2 ∙cosϕ ≥ 0
&
I E2 ∙cosϕ ≥ I ED>>>>def
I E2 IEDCLP>>>>def CLP
A
A =“OFF” A =“ON” A = ON - Change setting within CLP
I E2 ∙cosϕ ≥ I EDCLP>>>>def &
≥1
I ED>>>>def State
&
I E ∙cosϕ ≥M∙I ED>>>>def
I E2 IEDCLP>>>>def &
A
U ED>>>>def State
I E ∙cosϕ ≥M∙I EDCLP>>>>def A =“OFF” A =“ON”
& A = ON - Change setting within CLP
3V o
≥ M∙U ED>>>>def
U ED>>>>def State
&
3Vo
≥ U ED>>>>def
67NS4-proiezione.ai
Ground directional overcurrent (67N) - Fourth element logic diagram (IED>>>>) - Projecting operating mode (sheet 2 of 4)
Mode67N 3Votype67N
I UE
I E2 3Vo
I∙cos U EC
M Start IED>>>>
Insens-Zone
OFF IED>>>>ST-K
ON ≥ M∙threshold IED>>>>ST-L
TRIPPING M ATRIX
(LED+REL AYS)
t ED>>>>RES
t ED>>>>def
ON≡Enable IED>>>> directional earth fault
IED>>>> Enable t ED>>>>RES
& t ED>>>>def
0 T IED>>>>TR-K
T 0 IE>>>>TR-L
D =“modulo”
M RESET
(sheet 1)
Trip IED>>>>
Mode67N
D D
A A
C C
B B
D =“modulo” C =“proiezione”
A = Directional B = Non-directional
C =“proiezione”
(sheet 2)
I ED>>>>def State
&
≥ I ED>>>>def
I E2
Non-directional
IEDCLP>>>>def (from 74VT)
≥ I EDCLP >>>>def
IEDCLP>>>>Mode
74VTint/ext67N
Non-directional Block by 74VT (ON≡Block)
Internal or external
74VT
OFF
Trip IED>>>
BF Enable (ON≡Enable) & I ED>>>> BF towards BF logic
I ED>>>>BF
Ground directional overcurrent (67N) - Fourth element logic diagram (IED>>>>) (sheet 3 of 4) Fun_67NS4-3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IED>>>>BLK4 B = OFF t FI-Iph B = OFF IED>>>>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A
B IED>>>> Block4 I/O t FI-Iph IED>>>> Block4 OUT A Block4
“0”
Start IED >>>> C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
67NS4_BL-diagram.ai
Ground directional overcurrent (67N) - Logic diagram of the blocking signals concerning the fourth element (IED>>>>) (sheet 4 of 4)
Third and fourth thresholds (IEDC>>>def, IEDC>>>>def ) have definite time characteristic.
t EDC >
TRIP
t EDC >>
t EDC >>>
t EDC >>>>
t-int-F67NC.ai
I EDC > I EDC >> I EDC >>> I EDC >>>> IECH or IECL
General operation time characteristic for the ground directional overcurrent elements - 67N(Comp)
Note 1 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
UE
U EC
IL1H, IL2H, IL3H IL1L , IL2L , IL3L
Trip sector
UE UEC Half operating sector
(toward line)
IECH IECL (βE>, βE>>, βE>>>, βE>>>>) Characteristic angle
3Votype67NC IECtype67NC (ΘE>, ΘE>>, ΘE>>>, ΘE>>>>)
Characteristic axis
Mode67NC
Thresholds (I EDC threshold):
I EDC >, I EDC >>, I EDC >>>, I EDC >>>> Half operating sector
3V o [M(C)]∙(I EDC >, I EDC >>, I EDC >>>, I EDC >>>>) (βE>, βE>>, βE>>>, βE>>>>)
I I ∙c o s ΦE o ΦEC
67N(Comp)
I ECH o I ECL
No trip sector
(toward busbar)
UE
IL1H, IL2H, IL3H IL1L , IL2L , IL3L U EC
UE UEC
IECH IECL Trip sector
3Votype67NC IECtype67NC Half operating sector (toward line)
(βE>, βE>>, βE>>>, βE>>>>) Characteristic angle
(ΘE>, ΘE>>, ΘE>>>, ΘE>>>>)
Characteristic axis
Mode67NC
Thresholds (I EDC threshold):
I EDC >, I EDC >>, I EDC >>>, I EDC >>>>
3V o I I ∙c o s [M(C)]∙(I EDC >, I E DC >>, I EDC >>>, I EDC >>>>) Half operating sector
ΦE o ΦEC (βE>, βE>>, βE>>>, βE>>>>)
67N(Comp)
IE
No trip sector
(toward busbar)
Operating characteristics of the earth fault overcurrent element - 67N(Comp)
with projection operating mode ( I∙cos)
For both the operating modes, the polarizing reference used for displacement measure of the re-
sidual current may be selected:
• Direct residual voltage - the measured UE voltage is employed.
• Calculated residual voltage - the calculated UEC voltage is employed, where the fundamental com-
ponent and phase are derived from the instantaneous values of the three input phase-to-neutral
voltages.
Therefore, for both operating mode, the displacement of the residual current phasor IECH or IECL
and the residual voltage phasor (UE or UEC for direct/calculated residual voltage measurement type),
positive for lagging current compared with voltage (ΦE =(∠UE - ∠IEC, ΦEC =(∠UEC - ∠IEC .
The residual voltage measurement type may be selected by setting the 3Votype67N parameter,
located inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \ Common
configuration menu. The measurement type is UE (direct measure of residual voltage) or UEC (cal-
culated residual voltage).
For each of the four thresholds (IEDC >, IEDC >>, IEDC >>>, IEDC >>>>), the characteristic angle (ϑE>,
ϑE>>, ϑE>>>, ϑE>>>>) may be adjusted (setting range 0…359° common for the three phases).
Similarly, the calculated residual current measurement is selected from the following two mea-
sures:
• Calculated residual current on side H - the calculated IECH current is employed, where the funda-
mental component and phase are derived from the instantaneous values of the three input phase-
currents.
• Calculated residual current on side L - the calculated IECH current is employed, where the funda-
mental component and phase are derived from the instantaneous values of the three input phase-
currents.
The residual current measurement type may be selected by setting the ECtype67NC parameter,
located inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \ Common
configuration menu. The measurement type is IECH (side H) or IECL (side L).
VT supervision
For all the four thresholds IEDC>, IEDC>>, IEDC>>>, IEDC>>>>, the operating mode when the 74VT function
is active may be defined:
• OFF: no action are issued by 74VT.
• Block: all the four thresholds are blocked when the 74VT function is active.
• Not directional: all the four thresholds are switched from directional to not directional criteria
when the 74VT function is active.
The 74VT information may issued from internal 74VT function or from an external signal acquired by
means a binary input.
If a binary input is designed for 74VText, for all the four thresholds, the operating mode when the 74VT
function is active may be defined:
• OFF: no action are issued by 74VT.
• Block: all the four thresholds are blocked when the 74VT external signal is active.
• Not directional: all the four thresholds are switched from directional to not directional criteria
when the 74VT external signal is active.
Malfunctioning of the directional overcurrent elements can be avoided when VTs secondary fault
will arise (fuse or MCB tripping) by switching the overcurrent directional to non directional overcur-
rent protection
The 74VTint67NC and 74VText67NC parameters may be set as OFF, Block, Not directional
inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \ Common configura-
tion menu, while the 74VText function must be assigned to the selected binary inputs inside the Set
\ Board 1(2) inputs \ Binary input IN1-1...(IN1-x) menus.
For all the four thresholds (common for all thresholds) an insensibility zone may be enabled in the
voltage-current plane.
If enabled, the insensibility zone is user adjustable by means the M multiplier (common for all thresh-
olds); the rectangle defined by the current and voltage thresholds and the same multiplied by M
becomes a No trip zone.
Such insensibility zone may be useful to avoid unwanted trip in the presence of some fixed residual
current and/or voltage (e.g. CT and or VT errors in the residual measurements).
The Insens-Zone(C) (OFF, ON) and M(C) parameters may be adjusted inside the Set \ Profile A(or
B) \ Directional earth fault overcurrent-67N(Comp) \ Common configuration menu.
UE
U EC
TRIP
IE2
I EDC >, I EDC >>, I EDC >>>, I EDC >>>>
Voltage/current characteristic concerning the earth fault overcurrent element - 67N(Comp)
with insensibility zone disabled
UE
U EC
TRIP
IE2
I E DC >, I EDC >>, I EDC >>>, I EDC >>>> M∙I EDC >, M∙I EDC >>, M∙I EDC >>>, M∙I EDC >>>>
Note 1 For each threshold the projection of the residual current phasor on the characteristic axis is: (IECH or IECL )cos(ΘE>-ΦE), I (IECH or IECL )cos(ΘE>>-
ΦE), (IECH or IECL )cos(ΘE>>>-ΦE), (IECH or IECL )cos(ΘE>>>>-ΦE) when “direct” residual voltage is selected (UE), or
IECH or IECL )cos(ΘE>-ΦEC), (IECH or IECL )cos(ΘE>>-ΦEC), (IECH or IECL )cos(ΘE>>>-ΦEC), (IECH or IECL )cos(ΘE>>>>-ΦEC) when “calculated”
residual voltage is selected (UEC).
The ΘE , βE and ΦEC symbols are not used inside the Thysetter and MMI menus.
If the operation mode is switched to “not directional” (by the 74VT function), the start of any 67N
threshold becomes active when the following is complied:
- The residual current (IE ) fundamental component overcomes the threshold (IEDC>, IEDC>>, IEDC>>>,
IEDC>>>>)
For both the operating mode (module or projection), when the start signal goes ON a concerning
counter starts; after expiry of the associated operate time (t EDC>, t EDC>>, t EDC>>>, t EDC>>>>) a trip com-
mand is issued, if instead the above conditions don’t remain valid, the element it is restored.
All the parameters are located inside the menus concerning the four elements, separately for defi-
nite and inverse time characteristics.
Example: the operate time concerning the first threshold with definite time characteristic (IEDC>def)
is available inside the Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \
IEDC> Element \ Definite time menu.
All directional earth fault overcurrent elements can be enabled or disabled by setting ON or OFF the
IEDC> Enable, IEDC>> Enable, , IEDC>>> Enable e/o IEDC>>>> Enable parameters in-
side the Set \ Profile A(or B)\Directional earth fault overcurrent-67N(Comp) \ IEDC> Element (IEDC>>
Element, IEDC>>> Element, IEDC>>> Element) \ Setpoints menus.
The first and second overcurrent element can be programmed with definite or inverse time char-
acteristic by setting theIEDC>Curve and/or IEDC>>Curve (DEFINITE, IEC/BS A, IEC/BS
B, IEC/BS C, ANSI/IEE MI, ANSI/IEE VI, ANSI/IEE EI, EM) available inside the Set \ Profile
A(or B) \ Directional earth fault overcurrent-67N(Comp) \ IEDC> Element (IEDC>> Element) \ Set-
points menus.
The trip of IEDC> element may be inhibited by the start of the second, third and/or fourth element
(IEDC>>, IEDC>>>, IEDC>>>>) by setting ON the Disable IEDC> by start IEDC>>, Disable IEDC> by start
IEDC>>>, Disable IEDC> by start IEDC>>>> (IEDC>disbyIEDC>>, IEDC>disbyIEDC>>>,
IEDC>disbyIEDC>>>>) parameters available inside the Set \ Profile A(or B) \ Directional earth
fault overcurrent-67N(Comp) \ IEDC>> Element (IEDC>>> Element, IEDC>>>> Element) \ Setpoints
menus.
Similarly the trip of the:
• IEDC>> element may be inhibited by start of the third and/or fourth element (IEDC>>> and/or IEDC>>>>)
by setting ON the Disable IEDC>> by start IEDC>>>, start IEDC>>>> (IEDC>>disbyIEDC>>>,
IEDC>>disbyIEDC>>>>) parameter available inside the Set \ Profile A(or B) \ Directional
earth fault overcurrent-67N(Comp) \ IEDC>>> Element (IEDC>>>> Element) \ Setpoints menus.
• IEDC>>> element may be inhibited by start of the fourth element (IEDC>>>>) by setting ON the Dis-
able IEDC>>> by start IEDC>>>> (IEDC>>>disbyIEDC>>>>) parameter available inside the
Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \ IEDC>>>> Element \ Setpoints
menu.
All the named parameters can be set separately for Profile A and Profile B.
An adjustable reset time delay is provided for every threshold
(tEDC>RES, tEDC>>RES, tEDC>>>RES, tEDC>>>>RES).
Timers-F67NC.ai
INPUT
IEDC> Start
t EDC> t EDC>
IEDC> Trip
RESET
t
67N(Comp) element timers - 67N(Comp) (first element)
For every of the four thresholds the following block criteria are available:
Logical block (Block1)
If the IEDC>BLK1, IEDC>>BLK1, IEDC>>>BLK1 and/or IEDC>>>>BLK1 enabling param-
eters are set to ON and a binary input is designed for logical block (Block1), the concerning element
is blocked off whenever the given input is active.[1] The enabling parameters are available inside the
Set \ Profile A(or B) \ Directional earth fault overcurrent-67N(Comp) \ IEDC> Element (IEDC>> Ele-
ment, IEDC>>> Element, IEDC>>> Element) \ Setpoints menus, while the Block1 function must be
assigned to the selected binary input inside the Set \ Board 1(2) inputs \ Binary input IN1-1...(IN1-x)
menus.
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Note 2 The exhaustive treatment of the selective block (Block 2) function may be found in the “Selective Block” paragraph inside CONTROL AND
MONITORING section
Common configurations
The size of the residual current calculated vectorially on the measured currents on the sides of H
(IECH) or L (IECL ), and the residual voltage between the value measured directly (UEC) or the value
calculated from the three phase voltages vectorially (UEC) can be selected.
Common configurations
IL1H, IL2H, IL3H IL1L , IL2L , IL3L
UE UEC
IECH IECL
3Votype67NC IECtype67NC
Mode67NC
3V o I I∙cos
67N(Comp)
M
Insens-Zone
O FF
ON ≥ M∙threshold
Nota 1 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
IEDC>> Enable IEDC>>Curve IEDCCLP>>Mode tEDCCLP>> tEDC>>RES IEDC>>def IEDCCLP>>def tEDC>> def IEDC>>inv IEDCCLP>>inv tEDC>> inv
&
IE Insens-Zone
≥ U ED>def
O FF
≥1 &
3V o 3Vo
ON M sheet 3
U ED>inv State
≥ U ED>inv
3Vo
I EC ΦE inside trip sector
3V o Insens-Zone ON I EC
I EDCD>def State
&
≥ I EDC>def
≥1
I EDC>inv State
A
& CLP
I EC A =“OFF” A =“ON” A = ON - Change setting within CLP
≥ I EDC>inv
&
≥1
IEDCCLP>def IEDCCLP>inv
I EDC>def State
≥ IEDCCLP> &
≥ M∙I EDC>def
≥1
I EDC>inv State
&
≥ U ED>def
≥1
3Vo State
U ED>inv
&
≥ U ED>inv
67NCS1-module.ai
Ground directional overcurrent (67NComp) - First element logic diagram (IEDC>) - Module operating mode (sheet 1 of 4)
I EC
3Vo
I EC ΦE inside trip sector
I EDC>def State
I EC &
I E ∙cosϕ ≥ 0
&
I EC∙cosϕ ≥ I EDC>def
≥1
I EDC>inv State
CLP
A
&
I EC A =“OFF” A =“ON” A = ON - Change setting within CLP
I EC∙cosϕ ≥ I EDC>inv
&
≥1
IEDCCLP>def IEDCCLP>inv
I EDC>def State
U ED>def State
&
≥ U ED>def
≥1
3Vo State 67NS1-proiezione.ai
U ED>inv
&
≥ U ED>inv
Schema funzionale relativo alla prima soglia (IEDC>) della funzione direzionale di terra 67N(Comp) - Modo proiezione (foglio 2 di 4)
UE UEC
IECH IECL
3Votype67NC IECtype67NC
Mode67NC
3V o I I∙cos M
Insens-Zone
67N(Comp)
OF F
≥ M∙threshold
ON
D =“modulo” IEDC>ST-K
M IEDC>ST-L
(sheet 1) Mode67NC
TRIPPING M ATRIX
(LED+REL AYS)
D D
C C t EDC>inv
D =“modulo” C =“proiezione” I EDC> Curve t EDC>RES
t EDC>def
C =“proiezione”
(sheet 2) t ED>RES
A & t EDC>def/inv
T 0 0 T IEDC>TR-K
B T 0 IEC>TR-L
RESET
A
Trip IEDC>
B
I EDC>def State
A = Directional B = Non-directional
&
≥ I EDC>def
I EC
IEDCCLP>def
IEDCCLP>Mode
74VTint/ext67NC
Non-directional Block by 74VT (ON≡Block)
Internal or external
74VT
OFF
Trip IEDC>
BF Enable (ON≡Enable) & I EDC> BF towards BF logic
I EDC>BF
Ground directional overcurrent (67NC) - First element logic diagram (IEDC>) (sheet 3 of 4) Fun_67NCS1-3.ai
TRIPPING M ATRIX
Pilot wire input
(LED+REL AYS)
ON IPh/IE Iph Block2
ON IE
FROM PHASE PROTECTIONS tB-K
tB-L
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
FROM ANY PROTECTIONS
A = IN A = IN
IEDC>BLK4 B = OFF t FI-Iph B = OFF IEDC>BLK4
C = OUT ST-Iph BLK4 C = OUT
“0” A Block4
B IED> Block4 I/O t FI-Iph IED> Block4 OUT A
“0”
Start IEDC > C 0 T “0” B
“0” C
Block4 enable
t FI-IE ≥1 Block4 OUT
All other BLK4 I/O ≥1 All BLK4 I/O
t FI-IE
67NS1_BL-diagram.ai
Ground directional overcurrent (67NComp) - Logic diagram of the blocking signals concerning the first element (IEDC>) (sheet 4 of 4)
TRIP
t fdef>
t fdef>>
The overfrequency protection is enabled only when the maximum of the phase-to-neutral input volt-
ages ULMAX =max(UL1, UL2 , UL3) overcomes 0.2 Un for a tfEN adjustable time.
Setting of the tfEN value is available inside the Set \ Base menu with “level 1” session.
Timers-F81.ai
t fEN
t
Overfrequency & underfrequency enable timer
The first threshold trip (f >) may be inhibited by start of the second threshold (f >>) by setting ON the
f> Disabling by f>> start (f>disbyf>>) parameter available inside the Set \ Profile A(or B) \ Overfre-
quency-81O \ f>> Element \ Setpoints menu.
Note 1 The frequency can also be measured on the three phase-to-phase voltages (calculated vectorially)
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
f> Start
f>ST-K
TRIPPING M ATRIX
f>ST-L
(LED+REL AYS)
f > def
t f>def
f
f ≥ f >> def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n & t f>def
f>TR-K
(ON≡Inhibit) T 0
f> inhibition f>TR-L
RESET
f> Trip
f> Start
Enable (ON≡Enable) &
f>BLK1 f> Trip & f> Block1
&
(ON≡Inhibit)
f>disbyf>>
& f> inhibition
f>> Start
f>>ST-K
TRIPPING M ATRIX
f>>ST-L
(LED+REL AYS)
f >> def
t f>>def
f
f ≥ f >> def & t f>>def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n f>>TR-K
T 0
f>>TR-L
RESET
f>> Trip
f>> Start
Enable (ON≡Enable) &
f>>BLK1 f>> Trip & f> Block1
&
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
TRIP
t fdef <
t fdef <<
t fdef <<<
t fdef <<<<
Timers-F81.ai
t fEN
t
Overfrequency & underfrequency enable timer
The trip of f< element may be inhibited by the start of the second, third and/or fourth element (f<<,
f<<<, f<<<<) by setting ON the Disable f< by start f<<, Disable f< by start f<<<, Disable f< by start
f<<<< (f<disbyf<<, f<disbyf<<<, f<disbyf<<<<) parameters available inside the Set \ Pro-
file A(or B) \ Underfrequency-81U \ f<< Element (f<<< Element,f<<<< Element) \ Setpoints menus.
Similarly the trip of the:
• f<< element may be inhibited by start of the third and/or fourth element (f<<< and/or f<<<<) by setting
ON the Disable f<< by start f<<<, start f<<<< (f<<disbyf<<<, f<<disbyf<<<<) parameter avail-
able inside the Set \ Profile A(or B) \ Underfrequency-81U \ f<<< Element, (f<<<< Element) \ Setpoints
menus.
• f<<< element may be inhibited by start of the fourth element (f<<<<) by setting ON the Disable f<<<
by start f<<<< (f<<<disbyf<<<<) parameter available inside the Set \ Profile A(or B) \ Under-
frequency-81U \ f<<<< Element \ Setpoints menu.
Note 1 The frequency can also be measured on the three phase-to-phase voltages (calculated vectorially)
Note 2 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
f< Start
f< def
f<ST-K
TRIPPING M ATRIX
f<ST-L
(LED+REL AYS)
f
f ≤ f< def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n & t f<def
(ON≡Inhibit)
From 2nd, 3rd and/or 4th element f< inhibition t f<def
f<TR-K
T 0
f<TR-L
RESET
f< Trip
f< Start
Enable (ON≡Enable) &
f<BLK1 f< Trip & Block1
&
Logic diagram concerning the first threshold (f<) of the underfrequency element - 81U Fun-F81U_S1.ai
(ON≡Inhibit)
f<disbyf<<
& f< inhibition
f<< Start
f<< def
f<<ST-K TRIPPING M ATRIX
f<<ST-L
(LED+REL AYS)
f
f ≤ f<< def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n & t f<<def
(ON≡Inhibit)
From 3rd and/or 4th element f<< inhibition t f<<def
f<<TR-K
T 0
f<<TR-L
RESET
f<< Trip
f<< Start
Enable (ON≡Enable) &
f<<BLK1 f<< Trip & f<< Block1
&
Logic diagram concerning the second threshold (f<<) of the underfrequency element - 81U Fun-F81U_S2.ai
Note 1 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section.
(ON≡Inhibit)
f<<disbyf<<<
& f<< inhibition
f<<< Start
f<<< def
f<<<ST-K
TRIPPING M ATRIX
f<<<ST-L
(LED+REL AYS)
f
f ≤ f<<< def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n & t f<<< def
(ON≡Inhibit)
From 4th element f<<< inhibition t f<<< def
f<<<TR-K
T 0
f<<<TR-L
RESET
f<<< Trip
f<<< Start
Enable (ON≡Enable) &
f<<<BLK1 f<<< Trip & f<<< Block1
&
Logic diagram concerning the third threshold (f<<<) of the underfrequency element - 81U Fun-F81U_S3.ai
(ON≡Inhibit)
f<disbyf<<<<
& f< inhibition
(ON≡Inhibit)
f<<disbyf<<<<
& f<< inhibition
(ON≡Inhibit)
f<<<disbyf<<<<
& f<<< inhibition
f<<<< Start
f<<<<ST-L
(LED+REL AYS)
f
f ≤ f<<<< def & t f<<<< def
UL1,UL2 ,UL3 Max (UL1,UL2 ,UL3) ≥2 0 % U n
t f<<<< def
f<<<<TR-K
T 0
f<<<<TR-L
RESET
f<<<< Trip
f<<<< Start
Enable (ON≡Enable) &
f<<<<BLK1 f<<<< Trip & f<<<< Block1
&
Logic diagram concerning the fourth threshold (f<<<<) of the underfrequency element - 81U Fun-F81U_S4.ai
Definitions
• iL1(H) instantaneous value of L1 phase current on side H
• iL2(H) instantaneous value of L2 phase current on side H
• iL3(H) instantaneous value of L3 phase current on side H
• iL1(L) instantaneous value of L1 phase current on side L
• iL2(L) instantaneous value of L2 phase current on side L
• iL3(L) instantaneous value of L3 phase current on side L
These currents are conventionally regarded as positive if incoming in their reference terminal phase
current input of the relay, negative if outgoing.
• iL1C(H) instantaneous value of L1 compensated phase current on side H
• iL2C(H) instantaneous value of L2 compensated phase current on side H
• iL3C(H) instantaneous value of L3 compensated phase current on side H
• iL1C(L) instantaneous value of L1 compensated phase current on side L
• iL2C(L) instantaneous value of L2 compensated phase current on side L
• iL3C(L) instantaneous value of L3 compensated phase current on side L
iL1(H)
iL(H) = iL2(H) vector of instantaneous value of phase currents on side H
iL3(H)
iL1(L)
iL(L) = iL2(L) vector of instantaneous value of phase currents on side L
iL3(L)
iL1c(H)
iLc(H) = iL2c(H) vector of instantaneous value of compensated phase currents on side H
iL3c(H)
iL1c(L)
iLc(L) = iL2c(L) vector of instantaneous value of compensated phase currents on side L
iL3c(L)
With compact notation the previous vectors are referred to the iL (w) and iLC (w), where w = H, L is the
index of the two sides of the differential protection.
In order to correct any amperometric reversal polarity or phase cyclical sequence, and making equal
amplitude and phase currents on the sides of the differential protection and eventually eliminate
the element of homopolar sequence, the amplitude, polarity, phase and cyclic sequence and zero
sequence currents compensation is performed by relay, as follows:
iLC (w) = M(w) ∙ P(w) ∙ C(w) ∙ iL (w) with w = H, L
where:
M(w) is a compensating factor in the current amplitude of the side w.
P(w) is the polarity matrix of the of the amperometric polarities of the side w.
C(w) is the phase compensation matrix and cyclic sequence and zero sequence currents of the
homopolar sequence of the side w.
Magnitude matching
232 NVA100X-D - Manual - 02 - 2016
FUNCTION CHARACTERISTICS
M(w) is a compensating factor in the current amplitude of the w side; it expresses the values that are
multiplied by the currents of the w side in order to obtain an amplitude equal to that of the currents
on one side chosen as a reference.
If inside the Set \ Base menu the MatchType=ESTERNAL parameter is set (external compensation
with adapter CTs), then:
M(w) = 1
However, if inside the Set \ Base menu the MatchType=INTERNAL parameter is set then M(w) is
calculated by the relay as follows:
A) Calculation of the rated currents of the sides of the transformer from Snt rating (in MVA) and rated
voltages VntH, VntL in kV programmed in the Set \ Transformer menu:
IntH = 1000 ∙ Snt / [√3 ∙ VntH] rated current of side H of transformer
IntL = 1000 ∙ Snt / [√3 ∙ VntL] rated current of side L of transformer
B) Calculation of the difference (mismatching) between the CT primary rated current and rated cur-
rent of the sides of the transformer, starting from the InpH, InpL, InH, InL programming parameters
inside the Set \ Base menu and from the currents calculated in the preceding paragraph:
mH = InpH /IntH mismatching coefficient on side H of transformer
mL = InpL /IntL mismatching coefficient on side L of transformer
where: InpH, InpL are the CTs rated current on sides H and L
The relay checks that the values of the mismatching coefficients are between 1.0 and 2.5, if the
condition is not met, a warning message is issued and a correction of the Snt , VntH, VntL, InpH, InpL
parameters is required.
C) Choosing the transformer side[1] (RefSide) that the current amplitude compensations are taken
as a reference: the side reference chosen by the relay is the one with the lowest mismatching
coefficient. If the two sides have an equal value of the mismatching coefficient, the reference is
chosen as the side with the index H
D) If H is the reference side for current amplitude compensation, the current amplitude factors M (w)
are calculated as follows:
M(H) = [mH / mH]] / [InH /InH] = 1
M(L) = [mL / mH]] / [InL /InH]
If L is the reference side for current amplitude compensation, the current amplitude factors M (w)
are calculated as follows:
M(H) = [mH / mL]] / [InH /InL]
M(L) = [mL / mL]] / [InL /InL] = 1
Polarity matching
P (w) is the matrix of the amperometric polarity of w side. It allows us to consider each with its own
input current phase angle (coefficient +1 with NORMAL setting) or with opposite phase angle (with
coefficient -1 REVERSE setting), allowing correction of any sw current polarity reversals due to
connection errors.
P(w) is defined as:
pL1(H) 0 0 pL1(L) 0 0
P(H) = 0 pL2(H) 0 P(L) = 0 pL2(L) 0
0 0 pL3(H) 0 0 pL3(L)
The coefficients of amperometric polarity (C1-C2 POL for pL1(H), C3-C4 POL for pL2(H), C5-C6
POL for pL3(H), A1-A2 POL for pL1(L), A3-A4 POL for pL2(L), A5-A6 POL for pL3(L)) can each take
the value +1 (NORMAL) or -1 (REVERSE), based on the programming of the same coefficients in the
Set \ Polarity menu. If the amperometric polarity correspond to those of the corresponding wiring
diagram programming is +1, otherwise -1.
MatchType=ESTERNAL
If inside the Set \ Base menu the MatchType=ESTERNAL parameter is set (compensation with
external CTs), then C(w) is the identity matrix:
1 0 0 1 0 0
C(H) = 0 1 0 C(L) = 0 1 0
0 0 1 0 0 1
MatchType=INTERNAL
If inside the Set \ Base menu the MatchType=INTERNAL parameter is set then the C(w) matrix is
defined by relay as:
A) Calculation of the displacement of phase currents of each side concerning the H-side, from the
VectGroup(H) e VectGroup(L) programming parameters in the Set \ Transformer menu:
I(H) = VectGroup(H) ∙ 30° = 0 Current displacement on side H
I(L) = [VectGroup(H) - VectGroup(L)] ∙ 30° Current displacement on side L
B) Side of reference choice for the current phase compensation programming parameters from
Conn(H) and Conn(L) parameters inside the Set \ Transformer menu: the delta winding (D or d
programming) or zig-zag (Z or z programming) side is the reference side. If more than one winding
is delta connected or zig-zag, or if no winding is connected delta or zig-zag as the reference is
chosen to side with the index H.
C) The relay calculates the angle of compensation phase for each side )c(H), )c(L) through the
reference side for the phase compensation of point B) above, through the current phase shifts
calculated in paragraph A) above setting and through the setting of the I-sequenceH parameter
for side H and I-sequenceL for side L available inside the Set \ Input sequence menu . The cal-
culation is done as shown in the following table.
D) Depending on the compensation angles referred to in paragraph C), on the Gnd(w) parameter
setting available inside the Set \ Transformer menu, the relay considers the phase compensation
matrix C (w) the cyclic sequence mode and zero-sequence current of side w = H, L as shown in
the following tables.
It is noted that the RMS values of the fundamental component of the differential currents, whose
instantaneous values are calculated as in B) equal to the module of vector difference between the
compensated current phasors on side H and compensated current phasors on side L:
The start of the first threshold of the differential protection on L1 phase (ST Id-L1) occurs when all the
following conditions are met:
• 87 Enable = ON
• IdL1 ≥ Id>
• IdL1 ≥ K1/100) ∙ ISL1
• IdL1 ≥ K2/100) ∙ ISL1 - Q
• 87H-REST-L1 = OFF
• 87SatDet-L1 = OFF
• BLK1 87 = OFF
where:
• 87 enable parameter for both the differential protection thresholds,
• Id> adjustment of the minimum threshold (or maximum sensitivity) of the differential protection,
• K1 adjustment as a percentage of the slope of the first segment of the operating characteristic of
differential protection,
• K2 adjustment as a percentage of the slope of the second segment of the operating characteristic
of differential protection,
• Q y-axis intercept of the line of the second segment of the operating characteristic of differential
protection,
• 87H-REST-L1 logic state output of the the second and fi fth harmonic restraint for phase L1,
• 87SatDet-L1 logic state output of the CT’s saturation detector for phase L1,
• BLK1 87 logic state output of the logic block function of the differential protection.
All differential elements can be enabled or disabled by setting ON or OFF the 87T Enable param-
eter inside the Set \ Profile A(or B) \ Differential 87G-87M-87T \ Common configuration menu.
The Id>, K1, K2 and Q parameters are available inside the Input sequence \ Id> Element \ definite
time.
Similarly the start of the first threshold of the differential protection on L2 (ST Id>-L2) or L3 (ST Id>-L3)
phase occurs when all the following conditions are met:
• 87 Enable = ON
• IdL2 ≥ Id>
• IdL2 ≥ K1/100) ∙ ISL2
• IdL2 ≥ K2/100) ∙ ISL2 - Q
• 87H-REST-L2 = OFF
• 87SatDet-L2 = OFF
• BLK1 87 = OFF
• 87 Enable = ON
• IdL3 ≥ Id>
• IdL3 ≥ K3/100) ∙ ISL3
• IdL3 ≥ K2/100) ∙ ISL3 - Q
• 87H-REST-L3 = OFF
• 87SatDet-L3 = OFF
• BLK1 87 = OFF
where 87H-REST-L2 and 87H-REST-L3 are the output state of the second or fifth harmonic restraint
for L2 and L3 phases respectively, 87SatDet-L2 and 87SatDet-L3 are the output state of the saturation
detector for L2 and L3 phases.
The start of the first differential protection element (ST Id>) occurs at the instant of occurrence of
the threshold start in at least one of the L1, L2, L3 phases.
If the three conditions that led to the start of the first threshold of the differential protection on L1,
L2, L3 phases are maintained all for the duration of intentional delay td>, when the time expires the
element trips.
The start of the second threshold of the differential protection on L1 phase (ST Id>>-L1) occurs when
all the following conditions are met:
• 87 Enable = ON
• IdL1 ≥ Id>>
• BLK1 87 = OFF
where Id>> is the setting threshold of the differential protection element.
Similarly the start of the second threshold of the differential protection on L2 (ST Id>>-L2) or L3
(ST Id>>-L3) phase occurs when all the following conditions are met:
• 87 Enable = ON
• IdL2 ≥ Id>>
• BLK1 87 = OFF
• 87 Enable = ON
• IdL3 ≥ Id>>
• BLK1 87 = OFF
The operation of the second differential protection threshold (TR Id>>) occurs at the instant when the
intervention occurs the threshold in at least one of the L1, L2, L3 phases.
The Id>> parameter is available inside the Set \ Profile A(or B) \ Differential 87G-87M-87T \ Id>>
Element \ Definite time menu.
Differential protection is stabilized against external faults by increasing the threshold current dif-
ferential with increasing current passing through the protected area, according to the following
operating characteristic double slope percentage in the Id-IS plan (where the Id value is the funda-
mental component of the differential current in the L1 or L2 or L3 phases and IS is the fundamental
component of stabilization current in the L1 or L2 or L3 phases).
Id=|ILc(H) - ILc(L)|
Id
Id1=(K2/100) ∙ IS -Q
Id>>
TRIP Id1=(K1/100) ∙ IS
NO TRIP
Id>
α1 α2
0 Is
I [|I | + |I |]/2
Breaker failure (BF)
With single enable flag for first or second threshold of differential protection the element can pro-
duce the Breaker Failure side H and/or side L output if the 87T(H)-BF for side H and/or 87T(L)-BF
for side side L, parameter is set to ON. The parameters are available inside the Set \ Profile A(or B)
\ Differential 87G-87M-87T \ Common configuration.[1]
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the Breaker Failure - BF menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITOR-
ING section
Stabilization on powering and excitation of the power transformer with second and fifth harmonic restraint
With Transformer (Transf) selection the second and fifth harmonic restraint is enabled: the ProtObj
parameter is available inside the Set \ Base menu.
If Motor or Generator (GEN-MOT-LINE- BAR) is selected the second and fifth harmonic is auto-
matically excluded.[2]
The second harmonic restraint of differential protection allows you to block unwanted operation at
powering of the transformer.
The fifth harmonic restraint of differential protection allows you to block unwanted operation at dur-
ing the operation of the transformer in over-excitation state.
The relay calculates:
A) RMS value of the second harmonic component of differential currents:
Id2L1=DFT2[IdL1]
Id2L2 =DFT2[IdL2]
Id2L3 =DFT2[IdL3]
where DFT2[x] is the calculated rms value of the second harmonic component of differential cur-
rents concerning the x variable obtained by Discrete Fourier Transform (DFT).
B) RMS value of the fifth harmonic component of differential currents:
Id5L1=DFT5[IdL1]
Id5L2 =DFT5[IdL2]
Id5L3 =DFT5[IdL3]
where DFT5[x] is the calculated rms value of the fifth harmonic component of differential currents
concerning the x variable obtained by Discrete Fourier Transform (DFT).
C) Second harmonic component / fundamental component ratio of differential currents:
Id2L1 / IdL1
Id2L2 / IdL2
Id2L3 / IdL3
D) Fifth harmonic component / fundamental component ratio of differential currents:
Id5L1 / IdL1
Id5L2 / IdL2
Id5L3 / IdL3
If at least one ratio Id2L1 / IdL1, Id2L2 / IdL2 , Id2L3 / IdL3 exceeds the second harmonic restraint setting
2nd-REST> the start of the second harmonic restraint in the corresponding phase goes ON (ST 2nd-
REST-L1 or ST 2nd-REST-L2 or ST 2nd-REST-L3).
If at least one ratio Id5L1 / IdL1, Id5L2 / IdL2 , Id5L3 / IdL3 exceeds the fifth harmonic restraint setting 5th-
REST> the start of the second harmonic restraint in the corresponding phase goes ON (ST 5th-REST-
L1 or ST 5th-REST-L2 or ST 5th-REST-L3).
An intentional reset time delay tHREST-RES, common for second-fifth harmonic restraint (with zero
adjustment the second and fifth harmonic restraint is restored at the moment when the relationship
between the effective values of the second or fifth harmonic and fundamental component of differ-
ential current falls below the threshold setting 2nd-REST> or 5th-REST>).
The threshold setting 2ndh-REST> and reset time delay setting tHREST-RES are available inside the
Set \ Profile A(or B) \ Differential 87G-87M-87T \ Harmonic restraint menu.
The start of the element can control an output relay by programming the ST2nd-REST-K and/or
ST5th-REST-K parameter available inside the menu Set \ Profile A(or B) \ Differential 87G-87M-87T
\ Harmonic restraint menu, similarly for LED (ST2nd-REST-L and/or ST5th-REST-L).
The start of the second harmonic restraint threshold at one phase or the fifth harmonic restraint
threshold at the same phase determines the starting of the harmonic restraint element (ST REST-H-
L1, L2 REST-H-ST , ST H-REST-L3) for that phase.
The start of the second harmonic restraint threshold (ST 2nd-REST>) occurs at the instant of occur-
rence of the start of threshold in at least one of the L1, L2, L3 phases.
The start of the fifth harmonic restraint threshold (ST 5th-REST>) occurs at the instant of occurrence
of the start of threshold in at least one of the L1, L2, L3 phases.
The start of the harmonics harmonic restraint is produced from start of the second or fifth harmonic
restraint threshold (ST 2nd-REST>or ST 5th-REST>).
Nota 1 The exhaustive treatment of the internal selective block (Block 4) function may be found in the “Internal selective block” paragraph inside
CONTROL AND MONITORING section.
Note 2 Regardless of the value set all parameters in the Set \ Profile A(or B) \ Differential 87G-87M-87T \ Harmonic restraint menu are not significant
The logic state output of harmonic restraint considered for each phase (87 H-REST-L 1, 87 H-REST-L
2, 87 H-REST-L 3) is only enabled if the operating point in the corresponding phase stays over the first
three sections of the operating characteristic and below the second threshold Id>>.
BLOCK
Blocking of differential protection by harmonic restraint covers only the first three sections of the
double slope percentage tripping characteristic; the second threshold Id>> of the differential protec-
tion, which defines the fourth section of the tripping characteristic, it is nevertheless locking by har-
monic restraint so that to have a back-up protection in case of failure inside the zone of differential
protection with CT saturation that activate the second and fifth harmonic restraint.
In the first quarter of power cycle after the zero crossing of the instantaneous values of stabiliza-
tion current in a phase, the level of instantaneous values of the differential current at that phase is
controlled by the relay.
In the case of internal fault differential current appears along with the stabilization current after
the zero crossing, with the differential current instantaneous value of twice the actual value of the
stabilization current.
In the case of external fault however, the differential current does not appear until the beginning of
the CT saturation.
1) the saturation detector is enabled (SatDet parameter set ON inside the Set \ Profile A(or B) \ Dif-
ferential 87G-87M-87T \ CT saturation detector menu),
2) the value of the differential current, in absolute value, inside the first quarter of each power cycle
after the zero crossing of the stabilization current is, at that phase, less than 1.34 times the ab-
solute value of instantaneous value of the stabilization current in (corresponding to 77 % of the
operating characteristic for internal fault),
3) the operating point at that phase is above the first three sections of the double slope percent
operating characteristic and below the second threshold Id>>.
The saturation detector can be enabled or disabled by selecting ON or OFF the SatDet parameter,
available, together with the tSatDet-RES recovery time, within the menu Set \ Profile A(or B) \ Dif-
ferential 87G-87M-87T \ CT saturation detector menu.
The start of an output relay can be controlled by programming the STSatDet parameter inside the
Set \ Profile A(or B) \ Differential 87G-87M-87T \ CT saturation detector menu and similarly the pro-
gramming state can be viewed on LED (STSatDet-L).
The differential locking at the saturation detector activation is independent for each of the three
phases.
Saturation detector
iLxc(H)
iLx(H) Magnitude, polarity, isLx IsLx TRIP
SIDE H is DFT
phase and ciclic sequence NO TRIP
iLx(L) and zero sequence currents idLx IdLx
SIDE L compensation iLxc(L) id DFT
MatchType MatchType
Inct(H) iLxc(H) Inct(L)
iLx(H) Magnitude, polarity,
PhSeq SIDE H PhSeq
phase and ciclic sequence
pL1(H) iLx(L) and zero sequence currents pL1(L)
SIDE L compensation iLxc(L)
pL2(H) pL2(L)
pL3(H) pL3(L)
ProtObj ProtObj
NumSides NumSides
Sn(H) Sn(L)
Vn(H) Vn(L)
Gnd(H) Gnd(L)
Conn(H) Conn(L)
VectGroup(H) VectGroup(L)
iL1(H) iL1c(H) iL1(L) iL1c(L)
iL2(H) iL2c(H) iL2(L) iL2c(L)
SIDE H M (H )*P (H )*C (H ) SIDE L M (H )*P (H )*C (H )
iL3(H) iL3c(H) iL3(L) iL3c(L)
Magnitude, polarity, phase and ciclic sequence and zero sequence currents compensation 87T-compensation.ai
I SL1...L3
Stabilization and
differential current idL1...L3
measurement
iLxc(H)
isLx IsLx
is DFT1
idLx IdLx
iLxc(L) id DFT1
iL1c(H)
iL2c(H) I SL1...L3 idL1...L3
iL3c(H)
+iL1c(L) se sign[iL1c(L)∙iL1c(H)]≥0,
-iL1c(L) se sign[iL1c(L)∙iL1c(H)]<0 + iSL1 I SL1 =[|I L1c(H)| + |I L1c(L)|]/2
sign[iL1c(L)∙iL1c(H)] + DFT1
+iL2c(L) se sign[iL2c(L)∙iL2c(H)]≥0,
-i se sign[iL2c(L)∙iL2c(H)]<0 + iSL2 I SL2 =[|I L2c(H)| + |I L2c(L)|]/2
sign[iL2c(L)∙iL2c(H)] L2c(L) + DFT1
+iL3c(L) se sign[iL3c(L)∙iL3c(H)]≥0,
+ iSL3 I SL3 =[|I L3c(H)| + |I L3c(L)|]/2
-i se sign[iL3c(L)∙iL3c(H)]<0 DFT1
sign[iL3c(L)∙iL3c(H)] L3c(L) +
Saturation detector
1.6∙|iSL1|
IdL1
IdL1 < 1.6∙|iSL1| SatDet=ON
tSatDet-RES
1/4(fn)
1 1 0 T
ISL1
T 0
&
0
zero crossing detector
1.6∙|iSL2|
IdL2
IdL2 < 1.6∙|iSL2|
tSatDet-RES
1/4(fn)
1 1 0 T
ISL2
T 0
&
0
zero crossing detector
1.6∙|iSL3|
IdL3
IdL3 < 1.6∙|iSL3|
tSatDet-RES
1/4(fn)
ISL3 1 1 & 0 T
0 T 0
zero crossing detector
idL1...L3 iSL1...L3
from biased dual slope to biased dual slope
percentage characteristic percentage characteristic
Saturation detector
Id>
≥1 ST Id>>
Id1L1 ≥ Id> 87 Enable=ON
td>
K1 &
ST Id>-L1 T 0 TR Id>-L1
&
I SL1
Id1L1 ≥ (K1/100)∙ISL1
K2 Q
Id1L1 ≥ (K2/100)∙ISL1-Q
Id>> td>>
I dL1 ST Id>>-L1 T 0
TR Id>>-L1
Id1L1 ≥ Id>> &
Id>
Id1L2 ≥ Id>
td>
K1 & TR Id>-L2
&
ST Id>-L2 T 0 ≥1 TR Id>
I SL2
Id1L2 ≥ (K1/100)∙ISL2
K2 Q
Id1L2 ≥ (K2/100)∙ISL2-Q
Id>> td>>
I dL2 ST Id>>-L2 TR Id>>-L2
& T 0 ≥1 TR Id>>
Id1L2 ≥ Id>>
Id>
Id1L3 ≥ Id>
td>
K1 &
ST Id>-L3 TR Id>-L3
& T 0
I SL3
Id1L3 ≥ (K1/100)∙ISL3
Biased dual slope
percentage characteristic
K2 Q
Id1L3 ≥ (K2/100)∙ISL3-Q
Enable (ON≡Enable)
87T-BLK1 Block1
& BLK1 87T
Block4-in-out
Start 87T
87T Block2 OUT BLK2OUT-IE
Block2 output & BLK2OUT-IE-K
87TBLK2OUT
(ON≡Enable) BLK2OUT-IE-L
t F-IPh/IE
BLK2OUT-Iph/IE
t F-IPh/IE BLK2OUT-IPh/IE-K
≥1
T 0 BLK2OUT-IPh/IE-L
Start xx
&
xxBLK2OUT A = OFF
t F-IE B = ON IPh
ModeBLOUT1 C = ON IPh/IE
All other BLK2OUT outputs
t F-IE D = ON IE
of ground elements ≥1 A
T 0 B BLOUT1
(see BLK2OUT chapter) C
D
ST-IE BLK2 Pilot wire output
Block2out diagram
ST-Iph BLK4
A = IN ≥1 Block4 OUT
xxBLK4 B = OFF
C = OUT
“0” A
“0” B ST-IE BLK4
Start xx C
Block4 enable
t FI-IE
t FI-IE
All BLK4 I/O ≥1
T 0
of ground elements
(see BLK4chapter)
If both conditions are held along the set operate time tBF, the BF element trips at deadline, vice versa
the timer is cleared and the function is restored.
To the purpose to restore the BF element as quickly as possible, with start of the same protection
(see A condition), additionally to the trip of some internal protections, their starts are required (start
reset is faster than trip reset).
The element may be enabled or disabled by setting ON the BF Enable parameter available inside
the Set \ Profile A(or B) \ Breaker failure-BF menu.
I L1L . . . I L 3L
Tr i p B F
I E1 S tar t BF
52a/52b
Tr i p P r o t E x t
BF-BLK1
Block1
& BL K1 BF
Block1
All the IBF>, IEBF and t BF parameters can be set separately for Profile A and Profile B; they are avail-
able inside the Set \ Profile A(or B) \ Breaker failure-BF menu.
Note 1 The exhaustive treatment of the logic block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITORING
section
TRIPPING M ATRIX
I E ≥ I EBF > &
(LED+REL AYS)
CB Input t BF
Trip int-prot
Start BF
Block1 enable (ON≡Enable) &
BF-BLK1 Trip BF & BLK1 BF
&
TRIPPING M ATRIX
(LED+REL AYS)
Threshold
Operate time
Start
&
Customized Block1 info
Trip & BLK1xxx
Enable (ON≡Enable)
xxxBLK1
&
The logical block it is not liable for any inhibition time-out, so the protective element is disabled for
the whole time when the input is ON.[2]
Start
Operate time
Trip
Block1 (input)
Block1 (output)
t
Logic block timers - Block1 Timers-Block1.ai
Activation of any binary input assigned to logic block (Block1) function effects a block of all the
CAUTION protective elements where the logic block is enabled
Note 1 In the following treatment, the logical block is defined as “Logical block” or “Block1”
Note 2 The Block 1 signal forces a timer reset
TRIP
BLOUT1 Pro_N
TRIP TRIP
BLIN1
TRIP
BLIN1 BLOUT1 Pro_N BLIN1 BLOUT1 Pro_N
Pro_N
INx=Blocco selettivo Iph
TRIP
Any device
BLK2OUT-Iph-K
Selettività logica logica_acc.ai
The input is a polarized wet type powered by internal isolated supply; it must be drive by an output
block signal coming from a Pro-N device or by a free voltage contact.
WARNING Never connect power to the block input circuit; the electronic circuit can be demaged !
The protection is blocked off according the selectivity block criteria by phase elements (Block2
Iph), by earth elements (Block2 IE) or by any protection element (Block2 Iph/IE) when the input
BLIN1 is active. The information about phase or phase+earth block may be select programming the
ModeBLIN1 parameter inside the Set \ Profile A(or B) \ Selective block-BLOCK2 \ Selective block
IN menus.
Use of binary inputs
If the xxBLK2IN parameters (enable) are set to ON and a binary input is designed for selective
block (Block2), the protection is blocked off by phase elements (Block2 Iph), by earth elements
(Block2 IE) or by any protection element (Block2 Iph/IE), according the selectivity block criteria,
when the input (IN1 and/or INx) is active.
The Block2 Iph, Block2 IE and Block2 Iph/IE matching must be assigned to the selected binary
inputs inside the Set \ Board 1(2) inputs \ Binary input IN1-1...(IN1-x) menus
When a binary input is programmed for selective block input, the IN1 tON, INx tON, IN1 tOFF and
INx tOFF time delays must be reset to zero; the Logic parameters (ON/OFF) must be programmed
in the same way of the related output relay connected with-it.
Operation
For any protective element, three main conditions can arise:
A) Start = OFF: the element is at rest (no trip) regardless of the input/output blocks.
B) Start = ON: the element trips if no selective block input becomes active during the operate time.
C) Start = ON: if the selective block input (BLIN1 and/or binary input) becomes active, the element
goes in selective block state wherein the operate timer is forced to reset, so the element cannot
trip. After an adjustable time t B-Iph (common for phase protection elements) or t B-IE (common for
earth protection elements), the selective block input is disregarded and the operate timer can
start again. Information about t B-Iph and or t B-IE expired is available for reading (tB timeout data
inside Read \ Selective block - BLOCK2 \ Block2 input menu) and can drive an output relay and
Note 1 The selective logic can also be achieved with I/O connected with virtual pilot wires made up messages on the Ethernet network
Start I>
&
Trip I>
Block2 input enable (I> element)
I>BLK2IN & BLK2IN I>
(ON≡Enable) &
Start xx
&
Trip xx
Block2 input enable (I>, I>>, I>>>, IE>, IE>>, IE>>>, elements)
xxBLK2IN & BLK2IN xx
&
PulseBLIN1
Permanently “ON”
Shorted BLIN1
Pilot wire
T 0 Diagnostic No pulses
Breaked BLIN1 BLK2IN-Iph
ModeBLIN1
Pulse BLIN1
TRIPPING M ATRIX
OFF
(LED+REL AYS)
BLIN1 ON IPh
ON IPh/IE
ON IE
Pilot wire input Iph Block2
FROM PHASE PROTECTIONS
Logic t B-Iph
INx t ON INx t OFF
Block2 IPh
n.c. INx t ON INx t OFF ≥1 t B-Iph
≥1
n.o. T 0 0 T 0 T ≥1 tB timeout
Binary input INx
Logic diagram concerning the selective block intput - Block2 input Block2-in-diagram.ai
With a setting other than 0.00 s, the t B-Iph and t B-IE timers may be used to have a backup protection
available against pilot wire short circuit.[1]
The t B-Iph and/or t B-IE timers must be adjusted according the following rule (example for t B-Iph):
t B-Iph = t F v + εt + εs
where t F v is the value of block output timer related to the downstream relay (example t F-Iph), εt is a
chronometric selectivity margin to apply in comparison to the t B-Iph time related to the downstream
relay (does not take into account if such margin has been considered for the t F-Iph setting), εs is a
safety margin. The chronometric selectivity applied among the t B-x times of the relays in accelerated
logic system allows to avoid more the contemporary circuit breaker opening after the clearing of a
fault in a line of concomitant plant to the short-circuit of the pilot wires concerning the same line.
Note 1 In the absence of suitable provisions, a short circuit on a pilot wire causes the block of the receiving relay, so a possible fault (contemporary or
following) inside the protected zone, cannot be cleared that being the case the protective relay blocked.
INPUT BLOCK
(binary input and/or BLIN1)
BLIN2IN-Iph/BLIN2IN-IE
t B-Iph/t B-IE
tB timeout
t
tB timer TB-timer.ai
Operation
The selective block outputs go ON at the same time of the xx element start; they hold steady (even
if the start reset to zero) for along the t F-IPh, t F-IE and t F-IPh/IE adjustable times for phase, earth and
phase+earth functions.
The timers starts when one or more selective block function goes ON; when a timer expires, the
selective block outputs are disregarded (even if the start holds steady).
The t F-IPh and t F-IE counters start when the output selective block becomes active. When the coun-
ters expire the block selective output is forced off (despite the start xxx remain active).
If the t F-IPh, t F-IE e t F-IPh/IE timers are cleared the selective block output state is freeze up to the start
xxx remain active.
With a setting other than 0.00 s, the t F-IPh, t F-IE e t F-IPh/IE timers may be used to provide a backup
protection against breaker failure inside a selectivity logic system, as well as to hold blocked up-
stream protective relays up after the fault is cleared with CB opening to provide solution against
unwanted trips because of a larger reset time compared with the downstream relay (the selectivity
will be lost).
Start xx
(protezioni interne)
BLK2OUT-Iph
BLK2OUT-IE
BLK2OUT-Iph/IE
t
t F-IPh, t F-IE, t F-IPh/IE t F-IPh, t F-IE, t F-IPh/IE
With traditional selective logic systems, in the absence of suitable cares, the event of a circuit
breaker failure causes the block of the receiving relays situated upstream the circuit breaker, so the
fault cannot be cleared.
TRIPPING M ATRIX
(ON≡Enable)
(LED+REL AYS)
t F-IPh BLK2OUT-IPh-L
BLK2OUT-IE
All other BLK2OUT outputs of phase elements t F-IPh BLK2OUT-IE-K
≥1 t F-IPh/IE
0 T BLK2OUT-IE-L
[I2>, I2>> (46M), DthAL1, DthAL2, Dth> (49), BLK2OUT-Iph/IE
I>>, I>>> (50/51), ILR>, ILR>> (51LR), t F-IPh/IE BLK2OUT-IPh/IE-K
≥1
I-I/U>, I-I/U>> (51V)] 0 T BLK2OUT-IPh/IE-L
A = OFF
Start IE1 > t F-IE B = ON IPh
& IE > Block2 OUT ModeBLOUT1 C = ON IPh/IE
Block2 output
IE1>BLK2OUT t F-IE A D = ON IE
(ON≡Enable) BLOUT1
B
0 T Pilot wire output
All other BLK2OUT outputs of ground elements C
≥1 ST-IE BLK2 D
Block2 output
[IE1>>, IE1>>>(50N.1/51N.1), IE2>, IE2>>, IE2>>>(50N.2/51N.2),
IEC>, IEC>>, IEC>>> (50NComp/51NComp),
IED>, IED>>, IED>>>, IED>>>> (67N),
IEDC>, IEDC>>, IEDC>>>, IEDC>>>> (67NComp)]
Logic diagram concerning the selective block output - Block2 output Block2-diagram.ai
When using the Pro-N devices inside the selective logic systems, the answer to the circuit breaker
failure problem can be solved by means of, (as well as the BF-Breaker Failure element) or by
means of a threshold adjusted for time selectivity, through use of the output block reset timer too
with the intent that avoid permanently block of all upstream relays by downstream block signals (the
only one unblocked relays deals to the fault breaker).
The t F-IPh, t F-IE, t F-IPh/IE timers must be adjusted according the following rule (example for t F-Iph):
t F-Iph = t + TAP + trip + εt + εs
where t is the larger phase protection operate time, TAP is the circuit breaker operate time (with arc
extinction), trip is the larger reset time of all protective relays inside the selective logic system, εt is
an potential selectivity margin relative to the t F-x time of the downstream relays, εs is a safety margin
need to include timers errors (tolerances).
Diagnostic
To guarantee maximum fail-safety, the relay performs a run time monitoring for pilot wire continuity
and pilot wire shorting.[1]
Exactly the output blocking circuit periodically produces a pulse, having a small enough width in
order to be ignored as an effective blocking signal by the input blocking circuit of the upstream
protection, but suitable to prove the continuity of the pilot wire.
Furthermore a permanent activation (or better, with a duration longer than a preset time) of the
blocking signal is identified, as a warning for a possible short circuit in the pilot wire or in the output
circuit of the downstream protection.
Permanently “ON”
Pilot wire Shorted BLIN
BLOUT1 BLIN1
BLOCK OUT Pilot wire output Pilot wire link
≥1 BLOCK IN
Pulse Pulse BLIN1
generator Pilot wire input
The periodic pulses that are sent by output circuit may be enabled or disabled by means the Pulse-
BLOUT1 parameter available inside the Set \ Pilot wire diagnostic menu; with OFF setting the
pulses are disabled.[2]
If no pulses are received inside an adjustable time window at the selective block input circuit, a
break pilot wire alarm is issued; the information is available for reading (Breaked BLIN1 data inside
Read \ Pilot wire diagnostic submenu) and can drive an output relay and or a LED (PulseBLIN-K
and or a PulseBLIN-L parameters inside Set \ Pilot wire diagnostic submenu).
The control window may be programmed for OFF (no control) - 0.1 -1 - 5 - 10 - 60 - 120 s; the
Pulse BLIN1 parameter is available inside the Set \ Pilot wire diagnostic menu; with OFF setting of
the the PulseBLIN1 parameter the pulse control is disabled.
The same setting must be for input and output (PulseBLIN1 and PulseBLOUT1).
Note 1 Full diagnostic of pilot wires is only available when committed pilot wire input/outputs are employed
Note 2 When several outputs are parallel linked the pulse emission must be enabled inside one device only, sooner inside the outermost device
Setting example
In reference to the above shown schematic diagram, the logic selectivity is performed by means of
the dedicated I/O for the short circuit elements of A, B and C protective relays, so that if a fault arises
in (2), the open order or circuit breaker CB2 is issued and no trip is issued by A device.
A command must be issued for the main circuit breaker CB1 by the A relay with a fault in (1).
1
TRIP
BLOUT1 B
Pro_N
LOAD
TRIP TRIP
BLIN1
TRIP BLIN1 BLOUT1 C BLIN1 BLOUT1 D
A
Pro_N Pro_N
Pro_N
Logic selectivity logica_acc-esempio.ai
A Protection
I>> element with definite time set to 4.5 In with operate time to 0.10 s blocked by start of B and/or C
protection.
Settings:
• I>> def = 4.5 In
• t >> def = 0.100 s
• PulseBLOUT1 = OFF
• PulseBLIN1 = 1 s
• I>>BLK2IN = ON
• I>>BLK2OUT = OFF
• t B-IPh = 0.30 s
B Protection
I>> element with definite time set to 4.0 In with operate time to 0.10 s with emission of block output
toward A protection relay.
Settings:
• I>> def = 4.0 In
• t >> def = 0.100 s
• I>>BLK2IN = OFF
• I>>BLK2OUT = ON
• PulseBLIN1 = OFF
• PulseBLOUT1 = 1 s
• t F-IPh = 0.25 s
C Protection
I>> element with definite time set to 4.0 In with operate time to 0.10 s with emission of block output
toward A device and block input from D protection relay.
Settings:
• I>> def = 4.0 In
• t >> def = 0.100 s
• I>>BLK2IN = ON
• I>>BLK2OUT = ON
• PulseBLIN1 = 1 s
• PulseBLOUT1 = OFF
• t F-IPh = 0.25 s
• t B-IPh = 0.30 s
The internal selective block can work together with an external selective block from other protective
relays (Block2 input and Block2 output).
For any element the logic state of the internal output block and the trip state are defined by:
• Start threshold
• Internal selective logic block
according to the following table.
• If the xxx threshold is started, regardless of the internal input and output, the element is always
OFF (no trip).
• If the xxx threshold start stay ON within the operating time and the internal input is OFF, when the
timer expires the trip goes ON.
• If the xxx threshold is started and the internal input is ON, the xxx threshold is blocked (the operat-
ing timer is forced to reset); the element is OFF (no trip).
The internal selective block output goes ON when the threshold is started and stays ON (despite the
start goes OFF) along an adjustable time tFI-Iph common for all phase elements 50-51-67 or tFI-IE com-
mon for all earth elements 50N-51N-67N.
The t FI-IPh and t FI-IE counters start when the output selective block becomes active; when the coun-
ters expire the internal block selective output is forced OFF (despite the start xxx remain active).
A = IN
I>BLK4 B = OFF
ST-Iph BLK4
C = OUT
“0” A
“0” B I> Block4 I/O
Start I> C
Block4 enable t FI-Iph A = IN
B = OFF xxBLK4
t FI-Iph xx Block4 OUT C = OUT
≥1 A
Block4
All other BLK4 I/O 0 T
“0” B
of phase elements “0” C
A = IN ≥1 Block4 OUT
I E >BLK4 B = OFF
C = OUT
“0” A
“0” B IE > Block4 I/O
C t FI-IE
Start IE >
t FI-IE
All other BLK4 I/O ≥1
0 T
of ground elements
ST-IE BLK4
Logic diagram concerning the output signals of the internal selective block function - Block4 Block4-in-out-diagram.ai
If the t FI-IPh, t FI-IE e t FI-IPh/IE timers are cleared the selective block output state is freeze up to the
start xxx remain active.
With a setting other than 0.00 s, the t FI-IPh, t FI-IE e t FI-IPh/IE timers may be used to have a backup pro-
tection available against breaker failure inside a selectivity logic system, as well as to hold blocked
upstream protective relay up to your own reset
.
T1 T2
CB1 CB2
NVA100
P1 P2 NVA100
67 50 50 67
Block4 Block4
the time diagram of internal (Block4) and external (Block2) selective block concerning the phase and
residual overcurrent thresholds (I>> and IE>>) are shown in the following page.
t B-Iph
BLK2IN-Iph (P1 relay)
Time diagram of internal (Block4) and external (Block2) selective block concerning phase overcurrent element blocking of the example
t B-IE
BLK2IN-IE (P1 relay)
Time diagram of internal (Block4) and external (Block2) selective block concerning residual overcurrent element blocking of the example
+UAUX
Remote trip
Remote trip
TRIPPING M ATRIX
Remote trip Logic INx t O N INx t O F F
(LED+REL AYS)
n.c. INx t ON INx t OFF RemTrip-K
n.o. T 0 0 T RemTrip-L
Binary input INx
-UAUX
Remote tripping logic diagram Fun-Remote-trip.ai
• If the larger phase input current is lower than 25% In and the larger phase input voltage is lower
than 1.5% En the sampling frequency is fixed to fn (50 or 60 Hz).
• If the measured frequency is outside the locking range, the sampling frequency is fixed to the lower
or upper value (20 - 63 Hz).
I L1L
I L2L
I L3L Max I L1...L3 > 0.25 I n
U L1
≥ Sampling frequency
U L2
U L3 Max U L1...L3 > 0.015 E n
Max IL1L...L3L
Max UL1...L3 Rated frequency f n = 50 Hz or 60 Hz
20 Hz 63 Hz Locked frequency
0.25 In - 1.5% En
50 Hz o 60 Hz
20 63 f (Hz)
Max IL1L...L3L
Max UL1...L3 Rated frequency f n = 50 Hz or 60 Hz
0.25 In - 1.5% En
0 Hz
16 90 f (Hz)
Frequency tracking IF.ai
All protective elements are always operative; accuracy is guaranteed inside the locked frequency
band.
The second harmonic restraint is available to restraint any selected threshold of protective relay:
• Negative sequence overcurrent for motor - 46M
• Phase overcurrent - 50/51
• Residual overcurrent - 50N.1/51N.1
• Residual overcurrent - 50N.2/51N.2
• Calculated residual overcurrent - 50N(Comp)/51N(Comp)
Moreover one or more output contacts may be allocated to the 2NDH-REST function in order to block
any external protection relays where second harmonic restraint is not available.
ON≡Enable
I2ndh> Enable
Start I2ndh>
I 2ndh >
I L1-2nd t 2ndh>RES
TRIPPING M ATRIX
(LED+REL AYS)
I L1-2nd ≥ I 2 ndh>
t 2ndh>RES I2ndh>ST-K
I L2-2nd &
≥1 0 T I2ndh>ST-L
I L2-2nd ≥ I 2 ndh>
I L3-2nd
I L3-2nd ≥ I 2 ndh>
Logic diagram concerning the second harmonic restraint function - 2NDH/REST 2NDH-REST-diagram.ai
The setting of I2ndh> and t2ndh>RES parameters are available inside the Set \ Profile A(B) \
Second Harmonic Restraint menu.
The second harmonic element may be enabled or disabled; to enable it, the I2ndh> parameter must
be set to ON inside the Set \ Profile A(B) \ Second Harmonic Restraint-2ndh-REST menus.
All the parameters can be set separately for Profile A and Profile B.
The output may be assigned to the selected I2ndh>-ST-K output relays inside the
Set \ Profile A(B) \ Second Harmonic Restraint-2ndh-REST menu; the same for addressing the LED
indicators (I2ndh>-ST-L).
When output relays are programmed for second harmonic element output, the t TR time delays must
reset to zero; the operation mode must be set with self reset (No-latched inside Set \ Relays sub-
menu) and the Logic parameters (Energized/De-energized) must be programmed in the same
way of the related binary input connected with-it.
Generic protec t iv e e le me n t
(Threshold outside CLP) Start Ixx
TRIPPING M ATRIX
I xx
(LED+REL AYS)
Input STEADY STATE THRESHOLD t x x RES
A =“0 or OFF” A =“1” Operate time
t x x RES
t xx
I C L P xx 0 T
T 0
TRANSIENT THRESHOLD ICLPxxMode RESET
A = ON - Change setting Trip Ixx
B = OFF
t C L P xx C = ON - Element blocking
A
t CLPxx B
C
≥1 CLP Ixx
2nd harmonic restraint enable (ON≡Enable) T 0
Ixx2ndh-REST
& ≥1
Block1, Block2
Start I2ndh>
CB OPEN CB OPEN
CB State (52a=OFF) CB CLOSED (52a=ON) (52a=OFF)
CB State
tCLPxx 0.1 s
Output tCLPxx
t
TRANSIENT THRESHOLD/ STEADY STATE TRANSIENT THRESHOLD/
BLOCK THRESHOLD/UNBLOCK BLOCK
Cold Load Pickup logic diagram - CLP
Example: to change the first threshold of the definite time overcurrent element 50/51 within CLP dur-
ing a 0.1 s time interval:
• the ICLP> Mode parameter must be set as ON-Change setting,
• the tCLP> parameter must be adjusted to a wanted value (0.1 s) inside the Set \ Profile A(or B) \
Phase overcurrent - 50/51 \ I> Element \ Setpoints menu,
• The threshold within CLP parameter ICLP>def must be adjusted to a wanted value inside the Set
\ Profile A(or B) \ Phase overcurrent - 50/51\ I> Element \ Definite time menu.
CB position can be acquired by means one or two binary inputs; allocation of 52a and 52b func-
tions is available inside the Set \ Board 1(2) inputs \ Binary input IN1-1...(IN1-x) menus.
Re-acceleration
In a re-acceleration phase a current value close to locked rotor is absorbed by the motor but with-
out the current has previously cleared or dropped below the IRUN = 0.1 IB value; in this condition,
the CLP function is inactive so unwanted trip may arise. If a binary input is assigned to the “Motor
restart” function and inside the “Starting control set” menu the reset of the timing of all the CLP
thresholds (MR Enable ON)[2] is enabled, the timer counting is restarted so that the thresholds are
changed or blocked for the time set in order to avoid unwanted tripping.
Operation and settings
For each threshold the CLP function may be disabled (OFF), enabled with threshold blocking (ON-
Element blocking) or enabled with threshold change (ON-Change setting) by means the xx-
CLPx Mode parameter.
The operating mode and the relative activation time concerning each threshold of the 46, 49,
50/51, 50N/51N and 67N/67N elements are adjustable inside the Set \ Profile A(or B)\ xxx - xx
\ xxx Element \ Setpoints menus.
Example: to change the first threshold of the definite time overcurrent element 50/51 within CLP dur-
ing a 0.1 s time interval:
• the ICLP> Mode parameter must be set as ON-Change setting,
• the tCLP> parameter must be adjusted to a wanted value (0.1 s) inside the Set \ Profile A(or B)\
Phase overcurrent - 50/51\ I> Element \ Setpoints menu,
• The threshold within CLP parameter ICLP>def must be adjusted to a wanted value inside the
Set \ Profile A(or B)\ Phase overcurrent - 50/51\ I> Element \ Definite time menu.
CB position can be acquired by means one or two binary inputs; allocation of 52a and 52b functions
is available inside the Set \ Board 1(2) inputs \ Binary input IN1-1...(IN2-x) menu.
TRIPPING M ATRIX
(LED+REL AYS)
Input STEADY STATE THRESHOLD
t x x RES
Operate time
t x x RES
t xx
I C L P xx 0 T
T 0
TRANSIENT THRESHOLD RESET
Trip Ixx
A
A = ON - Change setting
B
tCLPxx C
A A
tCLPxx Output tCLPxx B B B = OFF
Starting control C C
T 0
A
B
C C = ON - Element blocking
A = ON - Change setting
B = OFF
C = ON - Element blocking ≥1 ≥1
xxCLP Mode
Block1, Block2
Starting control
I R UN = 0.1IB C L P source
M R E nable
Motor restart Logic INx t ON INx t OFF
Rese t C L P t imer
n.c. INx t ON INx t OFF &
-UAUX n.o. T 0 0
Binary input INx Motor restart
Output t CLP
Restart
t
HIGH THRESHOLD/ LOW THRESHOLD/ HIGH THRESHOLD/ LOW TH. HIGH THRESHOLD/ LOW TH.
BLOCK UNBLOCK BLOCK UNBLOCK BLOCK UNBLOCK
Cold Load Pickup typical logic diagram - CLP for NVA100X-G versions CLP-diagram-NVA100X-G.ai
I LMIN(H)
I LMIN(L) tgα=S(H)<
tgα=S(L)<
NO TRIP
TRIP
α
I (H) * I LMA X(H)
I (L ) * I LMA X(L)
Current asimmetry monitoring - 74CT
TRIPPING M ATRIX
I LMAX
(LED+REL AYS)
I LMIN /I LMAX < S<
t S< S<TR-K
&
I* T 0 S<TR-L
RESET
I LMAX Start I*
I LMAX >I*
The output may be assigned to the selected S(H)<TR-K and S(L)<TR-K output relays inside the
Set \ CT supervision-74CT side H and Set \ CT supervision-74CT side L submenu; the same for ad-
dressing the LED indicators S(H)<TR-L and S(L)<TR-L.
Logical block (Block1)
If the S<-BLK1 parameter is set to ON, and a binary input is designed for logical block (Block1), the
CT supervision function is blocked off whenever the given input is active. The trip timer is held in re-
set condition, so the operate time counting starts when the input block goes down.[1] The S<-BLK1
parameter is available inside the Set \ CT supervision-74CT side H and Set \ CT supervision-74CT
side L submenu.
All the parameters are common for A and B Profiles.
Note 1 The exhaustive treatment of the logic block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITORING
section
LINE
VTs
UAUX
Pro_N
MCB
MCB VT OPEN
BINARY INPUT
MCB VT OPEN
U 2VT>
ON≡Enable 74VT
U2 74VT Enable
U 2 ≥ U 2VT>
I 2VT>
I2 &
I 2 ≥ I 2VT>
TRIPPING M ATRIX
& R F G 0 T 74VT-AL-L
(LED+REL AYS)
≥ U VT<
RESET
%I VT<
|I L1(k)-I L1(k-1)|
74VT-BK-K
≤ %I VT< H &
74VT-BK-L
|I L2(k)-I L2(k-1)|
&
≤ %I VT<
|I L3(k)-I L3(k-1)|
I VT>
≤ %I VT<
Max(I L1...I L3)
&
“1”z CB CLOSED ≥ I VT>
CB closed Block 74VT
BLOCK 27/67/67N
(ON=1≡Autoreset enabled)
Self-reset 74VT
(ON=1≡Reset key)
Reset key
(ON=1≡remote reset)
Reset LEDs ≥1
Reset ThySetter
(Remote interface reset)
Remote Reset
“1”z CB TV open
MCB VT open
A Activates 74VT if one or two phase voltages are lost in the absence of negative sequence current (to discriminate asymmetrics hort circuits).
B Activates 74VT if all phase voltages are lost with loaded generator.
C Activates 74VT if all phase voltages are lost during commissioning of the line voltage (TV not connected), checking that no of the three currents exceeds I VT >.
In order to avoid trigger at the closure on polyphase short-circuit, I VT > should be set to a value less than I CC (but higher than the max inrush current).
In any case, the circuit breaker must be closed, otherwise the 74VT function is activated with standing generator.
D Inhibits the 74VT activation of the polyphase short-circuitss, setting the flip-flop when impulsive variation of currentin at least one phase change arises.
Inhibition resets automatically when all three phase voltages goes above threshold and negative sequence voltage goes below the threshold.
E The activation of the 74VT is maintained when at least one of conditions A, B, C is true.
The reset function can be performed manually (as long as the conditions are verified in the automatic reset D) or automatically if user defined.
F The 74VT activation can occur only for circuit breaker opening to protect the VTs secondary circuit.
G The 74VT activation can be inhibited by a 74VT block command applied to a binary input.
H The 74VT activation is always detected. If the user can also be set the voltage-dependent protection blocking.
VT supervision logic diagram - 74VT Fun_74VT.ai
All the parameters can be set separately for Profile A and Profile B.
+UAUX
Pro-N
TCS1
TCS2
-UAUX
Trip circuit supervision with two binary inputs - 74TCS TCS2s.ai
The faulty condition is detected occurs if both the following conditions are filled:
A) The TRIP contact is closed (external protection relay tripped);
B) The circuit breaker is closed (52a closed and 52b open).
Because such conditions can arise with healthy circuit too (e.g. a trip command is issued by the
protection relay but the CB opening time is still in progress), to avoid untimely operations the previ-
ous condition are checked every 80 ms and the output is issued after a 2 s delay; outputs are reset
to zero if at least the A or B condition become false after 0.6 s delay.[2]
Note 1 The exhaustive treatment of the logic block (Block 1) function may be found in the “Logic Block” paragraph inside CONTROL AND MONITORING
section
Note 2 Following assumption are considered for the framework:
Logic: ON,
Timers tON and tOFF: reset to zero
TRIP contact of the protection: DE-energized, No latched
TRIPPING M ATRIX
Binary input INx
(LED+REL AYS)
74TCS-ST-L
&
TCS2 Logic INx t ON INx t OFF
n.c. INx t ON 2s 0.6 s 74TCS-TR-K
INx t OFF &
n.o. T 0 0 T 74TCS-TR-L
T 0 0 TT
RESET
Binary input INx
Trip 74TCS
Trip 74TCS
Enable (ON≡Enable)
74TCS Enable
Start 74TCS
Enable (ON≡Enable) &
74TCS-BLK1 Trip 74TCS & BLK1 74TCS
&
Logic diagram concerning the trip circuit supervision with two binary inputs - 74TCS Fun-74TCS2.ai
+UAUX
Pro-N
TCS1
TRIP
Binary input INx Towards 74TCS logic
R
52
52a 52b
-UAUX
Trip circuit supervision with one binary inputs - 74TCS TCS1.ai
Note 1 The trip contact (TRIP) of the protection relays must be set with automatic reset (No-latched operating mode).
TRIPPING M ATRIX
(LED+REL AYS)
n.c. INx t ON INx t OFF 74TCS-ST-L
n.o. T 0 0 T
Binary input INx
40 s 6s 74TCS-TR-K
Enable (ON≡Enable) &
T 0 0 T 74TCS-TR-L
74TCS Enable
RESET
Trip 74TCS
Trip 74TCS
Start 74TCS
Enable (ON≡Enable) &
74TCS-BLK1 Trip 74TCS & BLK1 74TCS
&
Logic diagram concerning the trip circuit supervision with one binary inputs - 74TCS Fun-74TCS1.ai
1) If the circuit breaker is just open an unnecessary excitation must be avoided; the most critical
event arises when the TRIP contact is closed (e.g. manual or test command), so with minimal
series resistance. To avoid an unwanted excitation the series resistance must be higher than a
minimum value defined as:
Rmin = R TC · (UAUX - U TCmin) / U TCmin
where:
U TCmin: minimum coil excitation voltage
UAUX : auxiliary voltage
R TC : coil resistance
2) To energize the binary input circuit when the TRIP contact and CB open, the series resistance
must be lowerer than a maximum value defined as:
Rmax = [(UAUX - UDIGmin) / IDIG] - R TC
where:
UDIGmin: minimum binary input excitation voltage (18 V)
UAUX : auxiliary voltage
R TC : coil resistance
IDIG: binary input excitation current (0.003 A)
To satisfy the above requirements, the R value must be chosen between the Rmin and Rmax values;
typically the normalized value nearest the arithmetic mean:
R = (Rmin + Rmax) / 2
Example
UAUX = 110 Vcc (auxiliary voltage)
P TC = 50 W (coil power)
R TC = UAUX 2 / P TC = 242 Ω (coil resistance)
U TCmin = 77 V (minimum coil excitation voltage = 70% UAUX )
UDIGmin = 18 V (minimum binary input excitation voltage)
IDIG = 0.003 A (binary input excitation current)
Note1 In order to limit the temperature of the resistor it should be oversized (at least double the power - 2 W)
CB monitoring
+UAUX
52a Logic INx t O N INx t O F F 52a ON/OFF
n.c. INx t ON INx t OFF
n.o. T 0 0 T
TRIPPING M ATRIX
Binary input INx
52
(LED)
52a 52b t break
t break
52b Logic INx t O N INx t O F F =1
T 0
n.c. INx t ON INx t OFF
n.o. T 0 0 T
Binary input INx 52b ON/OFF
-UAUX
Logic diagram concerning the circuit breaker diagnostic function Fun-CB-position.ai
TRIPPING M ATRIX
Mode- N .Open
(LED+REL AYS)
N .Open
N.Open-K
&
From CB position Opening transition N.Open-L
≥
State SumI
Mode-SumI
TRIPPING M ATRIX
IL1
(LED+REL AYS)
¥I SumI
SumI-K
IL2 &
¥I Max SumI-L
From CB position Opening transition Max ≥ Sum I
IL3
¥I
SumIL1
SumIL2
SumIL3
State SumI^2t
TRIPPING M ATRIX
IL1 Mode-SumI^2t
(LED+REL AYS)
¥ I2t Sum I^2t
SumI^2t-K
IL2 &
¥I2t Max SumI^2t-L
From CB position Opening transition Max ≥ Sum I^2t
IL3
¥I2t
SumIL1^2t
SumIL2^2t
SumIL3^2t
Mode-tOpen
(LED+REL AYS)
State tbreak
Ktrig-break t break
tbreak-K
&
tbreak-L
≥
From CB position Opening transition
IN1 IN1
IN2 IN2
IN3 IN3
IN... IN...
IN32 IN32
OUT1 OUT1
OUT2 OUT2
OUT... OUT...
OUT16 OUT16
Applications
With Pro-N and Pro-XX relay the virtual I / O can be usefully employed for:
• Transmit information between protections installed in significant distance where the traditional
connections are critical in terms of reliability.
• Making OR logic for opening control of multiple DDI (simultaneous control of all DDI operated by
each SPI) in cases of multiple interface protections (Smart Grids)
• Achieve accelerated logic discrimination in which some protection elements can be blocked by the
activation of the downstream protection start; this allows to reduce the clearing time that, in time
logic systems require trip time significantly long in correspondence of the power source.
• Circuit breaker commands
• Selection of setting profiles
• Remote trip
• Include I / O in the programmable logic (PLC)
• etc. ..
Virtual Outputs:
The t V , t F-IPh and t F-IE timers start when the virtual output becomes active; when the counters expire
the virtual outputs are forced OFF; if the t V , t F-IPh and t F-IE timers are cleared the virtual output fol-
lows the state of the input (Start, Trip, IN).
The setting ranges are:
Start dropout time for voltage protections (t V ) 0.00...30.00 s (step 0.01 s)
Start dropout time for phase protections (t F -IPh ) 0.00...30.00 s (step 0.01 s)
Start dropout time for ground protections (t F -IE ) 0.00...30.00 s (step 0.01 s)
Trip reset (t Trip) 0.00...30.00 s (step 0.01 s)
All the parameters are available inside the Set \ Virtual Outputs \ Settings menu.
Virtual Inputs:
LinkLoss timer 3.0...60.0 s (step 0.1 s)
When the Virtual input is set for Remote Trip function, in the event of a network crash, when the
counters expire the remote trip is forced.
The parameter is available inside the Set \ Virtual Inputs \ Settings menu.
• Element pickup trigger; the information recording starts when a state transition on any protec-
tive element occurs if the parameter is set to ON.
• Trigger from outputs; the information recording starts when a state transition on the selected
output relay occurs if the parameter is set (KC1-1...Kxy-z).
• Binary input trigger; the information recording starts when a state transition on the selected
binary input occurs if the parameter is set to ON.
• Trigger from inputs; the information recording starts when a state transition on the selected
binary input occurs if the parameter is set (IN1-1, INx-y).
• 80% Buffer alarm; when the 80% of the buffer space is reached an alarm may be issued if the
parameter is set to ON.
Set sampled channels
The desired sampled quantities may be select inside the Set \ Oscillography \ Set sampled channels
menu (i L1-H, i L2-H, i L3-H, i L1-L, i L2-L, i L3-L, i E1, i E2, u L1, u L2, u L3, u 12, u 23, u 31, u E, I L1cH , I L 2cH , I L 3cH , I L1cL ,
I L 2cL , I L 3cL , I SL1, I SL 2 , I SL 3 , I DL1, I DL 2 , I DL 3 ).
Set analog channels
The desired sampled quantities may be select inside the Set \ Oscillography \ Set analog channels
menu.
Everyone of twelve analog channel may be associated to one of the selected measures (f U12 , f U23 ,
f U31, IL1H, IL2H, IL3H, IL1L , IL2L , IL3L , IE1, IE2, UL1, UL2 , UL3 , U12 , U23 , U31, UE,UEC, DTheta, IECH, IECL, IESH,
IL1cL , IL2cL , IL3cL , IL1cH, IL2cH, IL3cH, ISL1, ISL2 , ISL3 , IDL1, ID2L1, ID5L1, IDL2 , ID2L2 , ID5L2 , IDL3 , ID2L3 , ID5L3 ,
PhiL1, PhiL2 , PhiL3 , PhiE , PhiEC, PhiE_C, PhiEC_C, I1, I2, I2/ I1, U1, U2,P, Q, S, CosPhi, P L1, P L 2 , P L 3 , Q L1,
Q L 2 , Q L 3 , CosPhiL1, CosPhiL2 , CosPhiL3 , I L1-2nd , I L 2-2nd , I L 3-2nd , I -2nd /I L , R L1, X L1, Z L1, Z 12 , Z 23 , Z 31,
T1...T8 ).
Set digital channels
The desired digital quantities may be select inside the Set \ Oscillography \ Set digital channels
menu.
Everyone of twelve digital channel may be associated to one of the selected I/O signal (KC1-1... KC1-
8, KC2-1...KC2-8, KS1-1... KS1-16, IN1-1... IN1-16, IN2-1... IN2-16) .
The output signals (Id>-L1 ST....SatDet ST) may be select inside the Set \ Oscillography \ Set digital
channels from 87G-87M-87T states menu (Binary 17...Binary 32.
Direct
Lock frequency fl
U 12 Phase-to-phase frequency f U12
U 23 Phase-to-phase frequency f U23
U 31 Phase-to-phase frequency f U31
RMS value of fundamental component for phase currents side H I L1H , I L 2H , I L 3H
RMS value of fundamental component for phase currents side L I L1L , I L 2L , I L 3L
RMS value for phase currents side L I L1L...3Lrms
RMS value of fundamental component for phase voltages U L1, U L 2 , U L 3
RMS value of fundamental component for residual current side 1 I E1
RMS value of fundamental component for residual current side 2 I E2
RMS value of fundamental component for residual voltage UE
Calculated
Compensated currents side H I L1cH , I L 2cH , I L 3cH
Compensated currents side L I L1cL , I L 2cL , I L 3cL
Stabilization currents I SL1, I SL 2 , I SL 3
Differential currents I DL1, I DL 2 , I DL 3
Second harmonic of differential currents I DL1-2nd, I DL2-2nd, I DL3-2nd
Fifth harmonic of differential currents I DL1-5th, I DL2-5th, I DL3-5th
Thermal image DTheta
Phase-to-phase voltages U 12 , U 23 , U 31
Calculated residual voltage U EC
Calculated residual current side H and side L I ECH , I ECL
Maximum current between I L1L-I L2L-I L3L I LmaxL
Minimum current between I L1L-I L2L-I L3L I LminL
Average current between I L1L-I L2L-I L3L I LL
RMS maximum current between IL1Lrms-IL2Lrms-IL3Lrms I LmaxL-rms
RMS minimum current between IL1Lrms-IL2Lrms-IL3Lrms I LminL-rms
RMS average current between IL1Lrms-IL2Lrms-IL3Lrms I LL-rms
Maximum voltage between U L1-U L2-U L3 U Lmax
Minimum voltage between U L1-U L2-U L3 U Lmin
Average voltage between U L1-U L2-U L3 UL
Maximum voltage between U 12-U 23-U 31 U max
Minimum voltage between U 12-U 23-U 31 U min
Average voltage between U 12-U 23-U 31 U
Displacement
Displacement angle of IL1 respect to UL1 PhiL1
Displacement angle of IL2 respect to UL2 PhiL2
Displacement angle of IL3 respect to UL3 PhiL3
Displacement angle of UE respect to IE PhiE
Displacement angle of UEC respect to IE PhiEC
Displacement angle of UE respect to IEC PhiE-IEC(L/H)
Displacement angle of UEC respect to IEC PhiEC-IEC(L/H)
Sequence
Positive sequence current side L I1
Negative sequence current side L I2
Negative sequence current/positive sequence current ratio side L I2/I1
Positive sequence voltage U1
Negative sequence voltage U2
Power
Total active power P
Total reactive power Q
Total apparent power S
Power factor CosPhi
Phase active power side L P L1, P L 2 , P L 3
Phase reactive power side L Q L1, Q L 2 , Q L 3
Phase L1 power factor side L CosPhiL1
Phase L2 power factor side L CosPhiL2
Phase L3 power factor side L CosPhiL3
Impedance
Impedance resistive component L1 side L RL1
Impedance reactive component L1 side L XL1
L1 phase impedance side L ZL1
Impedance side L Z12, Z23, Z31
Harmonics
Phase currents second harmonic I L1L-2nd, I L2L-2nd,I L3L-2nd
Maximum of the second harmonic phase currents/Fundamental
I -2nd /I L
component percentage ratio
Third harmonic of phase currents I L1L-3rd , I L2L-3rd ,I L3L-3rd
Third harmonic of residual current I E1-3rd
Third harmonic of residual voltage U E-3rd
Fourth harmonic phase currents I L1L-4th , I L2L-4th ,I L3L-4th
Fifth harmonic phase currents I L1L-5th , I L2L-5th ,I L3L-5th
Motor starts
Starts number N Start
Total start time TStart
Demand phase
Phase fixed currents demand side L I L1...3FIX
Phase rolling currents demand side L I L1...3ROL
Phase maximum currents demand side L I L1...3MA X
Phase minimum currents demand side L I L1...3MIN
Active power fixed demand side L P FIX
Reactive power fixed demand side L Q FIX
Active power rolling demand side L P ROL
Reactive power rolling demand side L Q ROL
Active power maximum demand side L P MA X
Reactive power maximum demand side L Q MA X
Active power minimum demand side L P MIN
Reactive power minimum demand side L Q MIN
Energy
Positive active energy side L EA+
Negative active energy side L EA-
Total active energy side L EA
Positive reactive energy side L EQ+
Negative reactive energy side L EQ-
Total reactive energy side L EQ
Temperature
Temperature Pt1...Pt8 T1...T8
Motor state
Running motor time P-RMT
Total running motor time T-RMT
IRUN start state Start-IRUN
— Delayed inputs
The binary input states, acquired downstream the delay timers are available:
• IN1-1 ON/OFF
• IN1-2 ON/OFF
• INx-x ON/OFF
— Internal states
The state of the functions assigned to binary inputs are available
Reset LEDs ON/OFF
Profile selection ON/OFF
Fault trigger ON/OFF
IE /IPh Block2 ON/OFF
IPh Block2 ON/OFF
IE Block2 ON/OFF
Logic block side H-L and 87GMT ON/OFF
Logic block side H ON/OFF
Logic block side L ON/OFF
Blocco logico 87GMT ON/OFF
TCS1 (Trip Circuit Supervision) ON/OFF
TCS2 (Trip Circuit Supervision) ON/OFF
Trip External protections ON/OFF
Reset partial counters ON/OFF
Reset CB Monitor data ON/OFF
52a ON/OFF
52b ON/OFF
Open CB ON/OFF
CloseCB ON/OFF
Init DTheta (Thermal image presetting) ON/OFF
Remote trip ON/OFF
MCB VT OPEN ON/OFF
MCB VT2 OPEN) ON/OFF
Reset on demand measures ON/OFF
Reset energy measures ON/OFF
74VT ext. ON/OFF
Block I(L)> (Logic block side L, active with virtual I/O) BlockI(L)> ON/OFF
Block I(L)>> (Logic block side L, active with virtual I/O) BlockI(L)>> ON/OFF
Block I(L)>>> (Logic block side L, active with virtual I/O) BlockI(L)>>> ON/OFF
Block I(H)> (Logic block side H, active with virtual I/O) BlockI(H)> ON/OFF
Block I(H)>> (Logic block side H, active with virtual I/O) BlockI(H)>> ON/OFF
Block I(H)>>> (Logic block side H, active with virtual I/O) BlockI(H)>>> ON/OFF
Block IE1> (Logic block side 1, active with virtual I/O) BlockIE1> ON/OFF
Block IE1>> (Logic block side 1, active with virtual I/O) BlockIE1>> ON/OFF
Block IE1>>> (Logic block side 1, active with virtual I/O) BlockIE1>>> ON/OFF
Block IE2> (Logic block side 2, active with virtual I/O) BlockIE2> ON/OFF
Block IE2>> (Logic block side 2, active with virtual I/O) BlockIE2>> ON/OFF
Block IE2>>>(Logic block side 2, active with virtual I/O) BlockIE2>>> ON/OFF
IEC>Bk (Logic block IEC>, active with virtual I/O) BlockIEC> ON/OFF
IEC>>Bk ((Logic block IEC>, active with virtual I/O) BlockIEC>> ON/OFF
IEC>>>Bk (Logic block IEC>>>, active with virtual I/O) BlockIEC>>> ON/OFF
IED>Bk (Logic block IED>, active with virtual I/O) BlockIED> ON/OFF
IED>>Bk (Logic block IED>, active with virtual I/O) BlockIED>> ON/OFF
IED>>>Bk (Logic block IED>, active with virtual I/O) BlockIED>>> ON/OFF
Speed control ON/OFF
Reset N/T starts (reset timer counter motor start) ON/OFF
Motor re-acceleration ON/OFF
Reset running motor time (Partial) ON/OFF
Reset running motor time (Total) ON/OFF
Trigger
Note 1 Event 0 is the newest event, while the Event 299 is the oldest event
Note 2 Counter is updated at any new record; it may be cleared by means ThySetter
Note 3 Data are stored into non-volatile memory; they are retained once power is turned off
12000 50 (Hz)
N = int ·
(34 + 20 v i + 4 v RMS + nB)· (tpre + tpost )(s) f (Hz)
where:
•N record quantity
• vi sampled measures
• v RMS analog measures (RMS)
• nB logic variables (2 up to 16 variables)
• tpre pre-trigger time interval
• tpost post-trigger time interval
•f frequency
Example 1
With the following setting:
• Pre-trigger: 0.25 s
• Post-trigger: 0.25 s
• Sampled measures: i L1H, i L2H, i L3H, i L1L, i L2L, i L3L, i dL1, i dL2 , i dL3 , i E1, i E2
• Analog measures: I L1H , I L2H , I L3H , I L1L , I L2L , I L3L , I dL1, I dL2 , I dL3 , I E1, I E2
• Logic variables: KC1-1, KC1-2, KC1-3, KC1-4, KC1-5, KC1-6, IN1-1, IN1-2
12000 50 (Hz)
N = int · = 80
(34 + 20 · 11 + 4 · 11 + 2) · (0.25 + 0.25) 50 (Hz)
Example 2
With following setting:
• Pre-trigger: 0.5 s
• Post-trigger: 0.5 s
• Sampled data: i L1H, i L2H, i L3H, i L1L, i L2L, i L3L, i dL1, i dL2 , i dL3 , i E1, i E2
• Analog channels: I L1H , I L2H , I L3H , I L1L , I L2L , I L3L , I dL1, I dL2 , I dL3 , I E1, I E2
• Digital channels: KC1-1, KC1-2, KC1-3, KC1-4, KC1-5, KC1-6, IN1-1, IN1-2
12000 50 (Hz)
N = int · = 33
(34 + 20 · 11 + 4 · 11 + 2) · (0.50 + 0.50) 60 (Hz)
6.2 MOUNTING
The Pro-NX protection relays are housed inside metal cases suitable for various kinds of assembly:
• Flush mounting
• Rack
Flush mounting
The fixed case, fitted with special fastening brackets, is mounted on the front of electric control
board, previously drilled as indicated in the drawing.
In case of side-by-side mounting of several relays the minimum drilling distance is determined by
the front dimensions indicated in the overall dimensions drawing, increased by 3 mm, to ensure an
adequate tolerance and gasket space between adjacent relays.
The depth dimension, as indicated in the drawing, must be increased by as much as needed to allow
room for the wiring.
In 5A 1A 5A U En 100V
NVA100-DX#MM00
177
164.4
177
156
482.6
465
177 (4U)
101.6
For the A1...A8, B1...B10 and C1...C8 screw terminals with following characteristics are available:
• Nominal cross section: 0.2 a 4 mm2 (AWG 24...10) for single conductor
0.2 a 1.5 mm2 for two conductors with same cross section
• Tightening torque: 0.5-0.6 Nm
• Stripping length: 7 mm
For the IN1C-1...16, IN2D-1...16, OC1E-1...16 and OC2F-1...16 connections, screw terminals with fol-
lowing characteristics are available:
• Nominal cross section: 0.14 a 2.5 mm2 (AWG 26...16) for single conductor
0.14 a 0.75 mm2 for two conductors with same cross section
• Tightening torque: 0.5-0.6 Nm
• Stripping length: 8 mm
For the X1...X6 (RS485 and blocks) connections, screw terminals with following characteristics are
available:
• Nominal cross section: 0.2 a 2.5 mm2 (AWG 24...12) for single conductor
0.2 a 1.5 mm2 for two conductors with same cross section
• Tightening torque: 0.5-0.6 Nm
• Stripping length: 10 mm
Optional modules
Ground connection screw
In 5A 1A 5A U En 100V
NVA100-DX#MM00
Voltage inputs
Amperometric inputs
1/5 A CTs
The amperometric input circuits are mounted on the input module (terminals A1...8 for L side and
C1...8 for H side).
In case of replacement of the relay or checks on the amperometric circuits is essential to provide
appropriate support to achieve the secondary circuit shorting. For security reasons it is advisable to
operate in the absence of line current.
If the secondary of a CT carrying primary current is open circuited, a high voltage can be developed
CAUTION across the CT terminals.
When making the current connections, attention must be paid to not exceeding the performance of
the line current transformers. To be exact, the total load, the protective relay, any other protective
relays or measuring instruments and the resistance of the connections, must not exceed the line CT
performance.
0.018 × L × In 2 / S
where:
L the overall length, expressed in m, of the two conductors in relation to each phase;
In nominal current of the line CT expressed in A;
S cross sectional area of the current conductors expressed in mm2.
It is recommended that cabling of a suitable thickness be used in order to limit wear of the CT sec-
ondary circuits.
Earth connection
A protective ground connection is required: the section of the cable shall be not less than 2.5 mm2.
Earth connection
In 5A 1A 5A U En 100V
NVA100-DX#MM00
≥ 2.5 mm2
Source Source
Insulated cables
Shielded cables
Armoring Armoring
Load Load
Fig. 1a Fig. 1b
Current balanced transformer Toroide.ai
In order to ensure a linear response from the sensor, the cables must be positioned in the centre
of the transformer so that the magnetic effect of the three cables is perfectly compensated in the
absence of residual current (Fig.2a).
Hence, the assembly indicated in the drawing of fig.2b, in which phase L3 causes local magnetic
saturation whereby the vectorial sum of the three currents would be non-null, should be avoided.
The same considerations also apply when the sensor is positioned near bends in the cabling.
It is recommended that the transformer be placed away from bends in the conductors (fig 2c).
L1 L1
L2 L3 L2 L3
+UAUX
IN1C IN2D
A B 1
1
IN1-1 IN2-1
2
2
IN1-2 IN2-2
-UAUX 3 3
AUX-IN IN1-3 IN2-3
4 4
IN1 IN1-4 IN2-4
1 5 5
7 7
IN2 IN1-5 IN2-5
2
24 V
8 8
IN3 IN1-6 IN2-6
3
IN1
110 V 9 9
IN4 IN1-7 IN2-7
4
5 10 10
IN5
BINARY INPUTS
BINARY INPUTS
230 V IN1-8 IN2-8
7 6 6
11 11
IN6 IN1-9 IN2-9
8
12 12
IN7 IN1-10 IN2-10
9
13 13
IN8 IN1-11 IN2-11
10
6 14 14
IN9 IN1-12 IN2-12
11 15 15
17 17
IN10 IN1-13 IN2-13
12
18 18
IN11 IN1-14 IN2-14
13
19 19
IN12 IN1-15 IN2-15
14
15 20 20
IN13 IN1-16 IN2-16
17 16 16
IN14
18
IN15
19
IN16
20
16
Binary inputs
The inputs are immune to transitory interferences, however the following recommendation must be
considered in high disturbed environments:
• Position input wiring away from high energy sources.
• Set a debounce timer (tON and/or tOFF) to alloy the transient to decay.
• Use shielded cables with ground connection on only one end (preferably at the relay side.
OC1E OC2F
1 1
KC1-1 3 KC2-1 3
2 2 IN2D IN1C OC2F OC1E
4 4
KC1-2 6 KC2-2 6
5 5
7 7
KC1-3 KC2-3
8 8
9 9
KC1-4 KC2-4
OUTPUT RELAYS
10
OUTPUT RELAYS
10
11 11
KC1-5 KC2-5
12 12
13 13
KC1-6 KC2-6
14 14
15 15
KC1-7 17 KC2-7 17
16 16
18 18
KC1-8 20 KC2-8 20
19 19
Output relays
IRIG-B
The following time synchronization methods are available:
• SNTP protocol (Simple Network Time Protocol) over Ethernet network
• IRIG-B (Inter-Range Instrumentation Group – Time Code Format B)
Local port
A cross cable must be employed.
When used the local port takes priority over the Ethernet port
RJ45
serial1-sch.ai
TX FX FX
RX
FX (optical fiber)
TX
3V3 3V3 3V3
LINK1 LINK1 LINK1
LINK2 LINK2 LINK2
1 1 1
2 2 2
3 3 3
4 4 4
5 5 5
6 6 6
x x x
In 5A 1A 5A UE 100V
NVA100-DX#MM00
ethernet-wiring.ai
For testing a PC may be directly connect to the NVA100X Ethernet port on the rear side.
With TX interface a cross cable must be employed, while an Ethernet-optical fiber converter, suit-
able for 100 Mb data rate must be employed if an FX port is implemented.
The link must be enabled by means ThySetter sw and local connection:
• Set the IP address (Host IP address e IP net mask) in order that the NVA100X and PC param-
eters are matched; the parameters are inside the Communication \ Ethernet submenu.
• Set to OFF the Autonegotiation parameter of device (Autonegotiation parameter inside Com-
munication \ Ethernet submenu).
Note 1 The TX (RJ45) and FX (fibra ottica) Ethernet port are multiplexed (single IP address)
Under normal conditions, the primary port is active, while the secondary port is activated in the event of failure of the primary port or by means
of hw-sw switching command
Note 2 Two simultaneously active Ethernet ports with RSTP protocol
NETWORK
TX
FX
3V3
LINK1
LINK2
1
2
3
4
RS485
B-
5
A+
6
NVA100X NVA100X
X5 X5 120 Ω
B- B-
RS485
RS485
A+ A+
X6 X6
SUPERVISION UNIT
ETH-1 ETH-1
ETHERNET
ETHERNET
RS485-wiring.ai
TRIP I>>
BLIN1
BLOUT1
BLIN1
TRIP I>> Block2 IPh TRIP I>>
BLIN1
BLOUT1
TRIP I>>
Any device
When devices without committed pilot wire circuits must be embedded (devices other than Pro-N
or Pro-NX), or in the event that further I/O circuits are need, output relays and binary inputs can be
customized to work in the logic selectivity system together with the committed pilot wire circuits.
TRIP I>>
S1
Uaux
Pro_NX
20
16 IN1-16
X X
BLOCK IN
3
BLOCK OUT
BLOUT-
1
4
BLOUT+ 2
BLIN1
S2 S3
BLOUT1
A15
BLOCK IN
BLOUT-
A17
BLOUT+ A16
A18
A19
BINARY INPUTS
A20
A21
A22
Block-misto.ai
Example for accelerated protection system with joint use of binary input and pilot wire links
LEDs Label_LED
For safety reasons, a change of the rated values (Set \ Base menu) parameters become active
only after an hw reset.
WARNING
Note: The above parameters are highlighted in italics font inside the ThySetter menu
7.1 SW THYSETTER
The ThySetter sw is a “browser” of data (setting, measure, etc..); it implements an engine that is
afford to rebuild the menu set up and the relationships to data concerning all Thytronic protective
relays by means of XML files..
ThySetter setup
The latest release of ThySetter can be downloaded free of charge from the www.thytronic.it site
(Products - Software).[1]
— ThySetter use
Please refer to ThySetter user manual for detailed instructions.
The document is available on www.thytronic.it (Product / Software / ThySetter - Download area).
Note 1 Starting from the 3.5.9 release it is necessary to download and install not only the application setup but the Template setup also. In case off
updating download and install only the new release.
OPEN CB
CLOSE CB
The adjustment of the settings and the operation mode of the output relays must be performed while
the unit is electrically powered; the alphanumeric display shows the necessary information with ref-
erence to the operations performed through the keyboard. The display backlight switches automati-
cally to OFF after a one minute time-out. All preset values are permanently stored in the nonvolatile
memory. The buttons take the following operations:
- (Up) move the cursor upwards to the preceding menu options
- (Down) move the cursor downwards to the subsequent menu options
- (Left) move the cursor upwards to the preceding menu options
- (Right) move the cursor downwards to the subsequent menu options
- (Enter) access to the selected menu with the option of modifying any given parameter
- (Reset) abort the current changes and/or accessing the previous menu
- Circuit breaker Open command
- Circuit breaker Close command
At power-up, the display shows the text:
“THYTRONIC
PRO-NVA100X-DM00-a serial number
date and time: (01/01/2000 00:00”
The ON green Led points out the auxiliary power supply voltage (permanent) and possible diagnostic
faults (blink). The display backlight is automatically activated when any key switch is set.
By means of the (Up) or (Down) buttons, it is possible to cyclically browse through the menu op-
tions: READ, SET, COMMUNICATION, TEST
Having identified the sub-menu of interest, it is possible to gain access by using the (Right) button
and then analogously, run through the relevant options by using the (Up) or (Down) buttons.
The full menu tree and some examples are showed in the following pages (numerical values and
settings are pointed out as examples and does not agree with real situations).
— Reading variables (READ)
All data (measure, settings, parameters, etc...) can be displayed; they are arranged in functional
group submenus:
SELF TEST >>”
“SERIAL NUMBER >>”
“INFO >>”
“MEASURES >>”
“ACTIVE PROFILE >>”
“PROTECTIONS >>”
“VIN >>”
“VOUT >>”
“RPC >>”
“CIRCUIT BREAKER SUPERVISION >>”
“DELAYED INPUTS IN1-1...IN1-16 >>”
“INTERNAL STATES >>”
“RELAYS KC1-1...KC1-8 >>”
“PARTIAL COUNTERS >>”
“TOTAL COUNTERS >>”
“SELF-TEST >>”
“PILOT WIRE DIAGNOSTIC >>”
“SELECTIVE BLOCK BLOCK2 >>”
“INTERNAL ELECTIVE BLOCK BLOCK4 >>”
“FAULT RECORDING >>”
“EVENTS RECORDING >>”
Note 1 Setting changes are enabled when the Enabling setting by MMI parameter is set
As example, to set the operating mode of the K1 output relay as ENERGIZED, LATCHED, the following
procedure must be issued:
• By means (Down) button select the Set menu “SET >>”,
• Press the (Right) button to enter; the following submenu title i displayed: “BASE >>”
• Scroll menus by means (Down) button
“TRANSFORMER >>”
“INPUT SEQUENCE >>”
“POLARITY >>”
“LINE >>”
“INPUTS IN1-1...IN1-16 >>”
“RELAYS KC1-1...KC1-8 >>”
“LEDs ON MMI >>”
“LEDs LED1-1...LED1-8 >>”
“SELF-TEST RELAY >>”
“MMI >>”
“START CONTROL >>”
“PROFILE SELECTION >>”
“PROFILE A >>”
“PROFILE B >>”
“CIRCUIT BREAKER SUPERVISION 52 >>”
“VT SUPERVISION 74VT >>”
“CT SUPERVISION 74CT SIDE H >>”
“CT SUPERVISION 74CT SIDE L >>”
“REMOTE TRIPPING >>”
“PILOT WIRE DIAGNOSTIC >>”
“DEMAND MEASURES >>”
• Select the Set menu “RELAYS KC1-1...KC1-8 >>”, the “K1 relay Setpoints >>”
message is displayed,
• Press the (Right) button to enter; the following messages are displayed:
“Logic DE-ENERGIZED Mode NO LATCHED”
• Press the (Enter) button for a few seconds; the modification in progress status is highlighted by
the both START and TRIP flashing.
• Move the cursor over the parameter intended for change using the (Enter) button, (in our case
on the message “Logic DE-ENERGIZED”,
• Change the parameters by means the (increment) or (decrement) buttons, “Logic ENER-
GIZED”,
• Press the (Enter) button to move the cursor over the last parameter in the display, “Mode NO
LATCHED”,
• Change the parameters by means the (increment) or (decrement) buttons, “Mode
LATCHED”,
• Press the (Enter) button once again; the cursor and the LED TRIP turn off (the LED START keeps
flashing),
• Press the (Enter) button for a few seconds; new message appears: “Confirm settings?”
• Answer to the message ENTER: YES to confirm changes or RESET: NO to abort.
— COMMUNICATION
Inside the COMMUNICATION menu it is possible to read/modify the setting data of the RS485 Proto-
col parameters.
By means of (Up) or (Down) buttons it is possible to browse the main menu till the “RS485
Protocol >>” or “Ethernet parameters >>” message; to enter you must press the
(Right) button.
As example, to select the address 12 for the ModBus protocol, the following procedure must be
issued:
• Select the Communication menu “COMMUNICATION >>”.
• By means (Down) button select the “RS485 Protocol >>”.
• Press the (Right) button to enter; the following message is displayed:
“Protocol MODBUS”
“Address 1”
“9600 baud”
• Start the procedure to effect a change explained in the Setting modifying (SET) paragraph:
• Press the (Enter) button for a few seconds; the modification in progress status is highlighted by
the both START and TRIP flashing.
• Move the cursor over the parameter intended for change using the (Enter) button, (in the ex-
ample on the 1 address),
• Change the parameters by means the (increment) button (up to 12 address),
• Press the (Enter) button to move the cursor over the last parameter in the display,
• Press the (Enter) button once again; the cursor and the LED TRIP turn off (the LED START keeps
flashing),
• Press the (Enter) button for a few seconds; new message appears: “Confirm settings?”
• Answer to the message ENTER: YES to confirm changes or RESET: NO to abort.
The end of the LED blinking points out the end of procedure.
Note 1 Instantly all the relays are switched in rest state, including relays programmed as “normally energized”
All parameters (measurements and settings) are available for reading from the operator panel (MMI),
while the setting changes are enabled or disabled depending on possible operation modes:
• Enable without password (factory setting)
• Enable with password
• Disabled
The choice of operation modes is possible only through ThySetter operating at the session level 1:
• Connect the PC serial port to the relay socket on the RJ10 front panel
• Run the ThySetter sw (the latest version latest version available on the site is recommended).
• Select the Preference - Session menu; when you start the session level is set to 0 as shown in
the bottom of the window
• Select the level 1. Prompted for a password (the default level1) to move to level 1. Confirm twice
with “OK”. (Level 1, as shown in the bottom of the window).
• Open the communication session by executing the menu command Communication - Open.
Verify that inside the modality box Serial and Automatic are selected
• Thysetter will search automatically the relay from the template, regardless of what is selected in
the device family.
• Inside the Serial Configuration panel select the COM port (eg COM1, COM4 etc), give the Start
command and wait for the opening of the new window
• Save the file. Choose the location to save the file and give the Save command. The configuration
data of the relay are transferred to the PC (the progress bar is displayed from 0 ... 100%). A folder
on a yellow background with the name of the file is highlighted on the left side of the windows.
The serial connection is operative, at the bottom of the screen the word ON-LINE is highlighted
in green field.
• Select the Set \ MMI folder (MMI stands for Man-Machine-Interface = keyboard). On the right side
of the window (first row) select Parameter setting enable; with a “click” on the column value 3
options are available:
- OFF = keyboard enabled only for reading
- By password = keyboard enabled for reading and setting by means of password
- ON = keyboard enabled for reading and setting without password
Following the Set default settings command the password is reset to 0000.
THYTRONIC
fl 50.000 Hz ILmaxL-rms0.000 InL
PRO-NVA100X-DM00-a ILminL-rms0.000 InL
fU12 50.000 Hz
DATE: 01/01/2014 fU23 50.000 Hz ILL-rms 0.000 InL
TIME: 17:29:59 fU31 50.000 Hz ULmax 0.000 En
IL1L 0.000 InL ULmin 0.000 En
Enter Password IL2L 0.000 InL UL 0.000 Un
PASSWORD >> IL3L 0.000 InL U 0.000 Un
<< MMI board ON IL1rms 0.000 InL PhiL1 0 deg
SING1 board ON IL2rms 0.000 InL PhiL2 0 deg
MODULES >> SING2 board OFF IL3rms 0.000 InL PhiL3 0 deg IL2L-5th 0.000 In
SRC1 board ON IL1H 0.000 InH PhiE 0 deg IL3L-5th 0.000 In
DISABLE Disable ------------------ IL2H 0.000 InH PhiEC 0 deg Nstart 0
27-27V1-27V1 IL3H 0.000 InH PhiE-IEC 0 deg Tstart 0 s
21-27-37-81 37-37P PhiEC-IEC 0 deg
UL1 0.000 En IL1LFIX 0.000 InL
FUNCTIONS 81=-81U ? UL2 0.000 En I1 0.000 In IL2LFIX 0.000 InL
BY OPERATOR >> << No Yes >> UL3 0.000 En I2 0.000 In IL3LFIX 0.000 InL
IE1 0.000 IE1n I2/I1 0.000 In IL1LROL 0.000 InL
DAY: 11 HOUR: 14 IE2 0.000 IE2n U1 0.000 En IL2LROL 0.000 InL
MONTH: 7 MINUTE: 25 UE 0.000 UEn U2 0.000 En IL3LROL 0.000 InL
CLOCK ADJUST >> YEAR: 2013 SECONDS: 0 P 0.000 Pn
IL1cH 0.000 Inref IL1LMAX 0.000 InL
<< Confirm >> << Confirm >> IL1cL 0.000 Inref Q 0.000 Qn IL2LMAX 0.000 InL
ISL1 0.000 Inref S 0.000 An IL3LMAX 0.000 InL
Protection IDL1 0.000 Inref CosPhi 1.000 IL1LMIN 0.000 InL
ON SERVICE IDL1-2nd0.00 Inref PL1 0.000 Pn IL2LMIN 0.000 InL
Global self-test IDL1-5th0.00 Inref QL1 0.000 Qn IL3LMIN 0.000 InL
OK IL2cH 0.000 Inref CosPhiL1 1.000 IL1HFIX 0.000 InL
System OK IL2cL 0.000 Inref PL2 0.000 Pn IL2HFIX 0.000 InH
Data-base: ISL2 0.000 Inref QL2 0.000 Qn IL3HFIX 0.000 InH
SELF TEST >> boot OK IDL2 0.000 Inref CosPhiL2 1.000 IL1HROL 0.000 InH
run-time OK IDL2-2nd0.00 Inref PL3 0.000 Pn IL2HROL 0.000 InH
Data BUS: IDL2-5th0.00 Inref QL3 0.000 Qn IL3HROL 0.000 InH
heavy OK IL3cH 0.000 Inref CosPhiL3 1.000 IL1HMAX 0.000 InH
minor OK IL3cL 0.000 Inref RL1 1.000 Znf IL2HMAX 0.000 InH
DSP: ISL3 0.000 Inref XL1 1.000 Znf IL3HMAX 0.000 InH
.................. IDL3 0.000 Inref ZL1 1.000 Znf IL1HMIN 0.000 InH
IDL3-2nd0.00 Inref Z12 1.000 Znf IL2HMIN 0.000 InH
Serial number IDL3-5th0.00 Inref Z23 1.000 Znf IL3HMIN 0.000 InH
SERIAL NUMBER >> 237 U12 0.000 Un Z31 1.000 Znf PFIX 0.000 Pn
U23 0.000 Un IL1L-2nd 0.000 InL QFIX 0.000 Qn
Code NVA100X-DM00-a U31 0.000 Un IL2L-2nd 0.000 InL PROL 0.000 Pn
INFO >> Ver.sw 1.00 UEC 0.000 UECn IL3L-2nd 0.000 InL QROL 0.000 Qn
DSP fw Rel 1.00 IECL 0.000 InL I-2nd/IL 0.000 PMAX 0.000 Pn
IECH 0.000 InH IL1L-3rd 0.000 InL QMAX 0.000 Qn
Code NVA100X-DM00-a IESH 0.000 IE1n IL2L-3rd 0.000 InL PMIN 0.000 Pn
IEC61850 >> Sw Release 1.30 DTheta 0 DThetaB IL3L-3rd 0.000 InL QMIN 0.000 Qn
ILmaxL 0.000 InL IE-3rd 0.000 IEn EA+ 0 kWh
ILminL 0.000 InL UE-3rd 0.000 UEn EA- 0 kWh
ILL 0.000 InL IL1L-4th 0.000 InL EQ+ 0 kvarh
ILmaxH 0.000 InH IL2L-4th 0.000 InL EQ- 0 kvarh
ILminH 0.000 InH IL3L-4th 0.000 InL EA 0 kWh
ILH 0.000 InH IL1L-5th 0.000 In EQ 0 kvarh
MEASURES >>
P-RMT 0 min
MOTOR STATE >> T-RMT 0 min
Start IRun OFF
NVA100X-D_menuread1b.ai
NVA100X-D_menuread2.ai
ParTr74CTLcnt 0 ParStBFcnt 0
74CT Counters >> ParBk1-74CTLcnt 0 ParTrTrcnt 0
BF Counters >> ParBk1BFcnt 0
NVA100X-D_menuread3.ai
TotTr74CTLcnt 0 TotStBFcnt 0
74CT Counters >> TotBk1-74CTLcnt 0 TotTrTrcnt 0
BF Counters >> TotBk1BFcnt 0 NVA100X-D_menuread3-t.ai
U2>def OFF
0.10 En
tU2>def 1.00 s
U2>BLK1 OFF
U2>BF OFF
59V2 >> U2> Element >> Relays U2>
U2>ST-K -
U2>TR-K -
LEDs U2>
U2>ST-L -
PROFILE A U2>TR-L -
64REF Enable OFF
IREF> OFF
1.00 IEn1
tREF> 1.00 s
64REF-BLK1 OFF
64REF-BLK2OUT OFF
6REF >> 64REF-BF OFF
Relays 64REF
64REF-ST-K -
64REF-TR-K -
LEDs 64REF
64REF-ST-L -
64REF-TR-L -
66 Enable OFF
Type66 NST
tC 1 min
NST 10
TST 30 s
66 >> TIN 0 min
66BLK1 OFF
Relays 66
66-TR-K -
LEDs 66
66-TR-L -
f>def OFF
1.000 fn f>>def OFF
f> Element >> tf>def 1.00 s 1.000 fn
f>BLK1 OFF tf>>def 1.00 s
f>BF OFF f>>BLK1 OFF
Relays f> f>>BF OFF
f>ST-K - f>disbyf>> OFF
81O >> f>TR-K - Relays f>>
LEDs f> f>>ST-K -
f>ST-L - f>>TR-K -
f>TR-L - LEDs f>>
f>>ST-L -
f>> Element >> f>>TR-L -
f<def OFF
1.000 fn f<<def OFF
f< Element >> tf<def 1.00 s 1.000 fn
f<BLK1 OFF tf<def 1.00 s
f<BF OFF f<<BLK1 OFF
Relays f< f<<BF OFF
f<ST-K - f<disbyf<< OFF
f<TR-K - Relays f<<
LEDs f< f<<ST-K -
f<ST-L - f<<TR-K -
f<TR-L - LEDs f<<
f<<ST-L -
f<< Element >> f<<TR-L -
f<<<def OFF
1.000 fn
81U >> tf<<<def 1.00 s
f<<<BLK1 OFF f<<<<def OFF
f<<<BF OFF 1.000 fn
f<disbyf<<< OFF tf<<<<def 1.00 s
f<<disbyf<<< OFF f<<<<BLK1 OFF
f<<< Element >> Relays f<<< f<<<<BF OFF
f<<<ST-K - f<disbyf<<<< OFF
f<<<TR-K - f<<disbyf<<<< OFF
LEDs f<<< f<<<disbyf<<<< OFF
f<<<ST-L - Relays f<<<<
f<<<TR-L - f<<<<ST-K -
f<<<<TR-K -
f<<<< Element >> LEDs f<<<<
f<<<<ST-L -
f<<<<TR-L -
ModeBLOUT1 OFF
tF-IPh 1.00 s
BLOCK2 >> tF-IE 1.00 s
tF-IPh/IE 1.00 s
Relays BLOCK2OUT
BLOCK2OUT-IPh-K -
BLOCK2 OUTPUT >> BLOCK2OUT-IE-K -
SET BLOCK2OUT-IPh/IE-K-
LEDs BLOCK2OUT
BLOCK2OUT-IPh-L -
tFI-IPh 1.00 s BLOCK2OUT-IE-L -
BLOCK4 >>
tFI-IE 1.00 s BLOCK2OUT-IPh/IE-L-
BF Enable OFF
IBF> ON
0.10 In
IEBF> ON
0.10 IEn
tBF 1.00 s
BF-BLK1 OFF
BF >> CB Input ON
Relays BF
BF-ST-K -
BF-TR-K -
LEDs BF
BF-ST-L -
BF-TR-L -
ModeN.Open OFF
N.Open 10000
ModeSumI OFF
SumI 5000 In
ModeSumI^2t OFF
CBopen-K - tbreak 0.05 s
CBclose-K - SumI 5000 In^2s
LEDs-Relays CBclose-L -
allocation >> Mode-tOpen OFF
CIRCUIT BREAKER CBopen-L - Ktrig-break -
SUPERVISION >> CBdiag-K - tbreak> 1 s
CB Diagnostic >> Relays
N.Open-K -
SumI-K -
SumI^2t-K -
tbreak-K -
LEDs
N.Open-L -
SumI-L -
SumI^2t-L -
tbreak-L -
RemTrBF OFF
Relays
REMOTE RemTrip-K -
TRIPPING >>
LEDs
RemTrip-L -
PulseBLOUT1 OFF
PulseBLIN1 OFF
PILOTE WIRE Relays
DIAGNOSTIC >> PulseBLIN1-K -
LEDs
PulseBLIN1-L -
Periods
DEMAND tFIX 15 min
MEASURES >> tROL 5 min
N.ROL 12
Protocol MODBUS
RS485 Address 1
Protocol >>
9600 bauds
7.5 REPAIR
No repair of possible faults by the client is foreseen; if following to any irregularity of operation, the
above tests confirm the presence of a fault, it will be necessary to send the relay to the factory for
the repair and the consequent settings and checks.
7.6 PACKAGING
The Pro-N devices must be stored within the required temperature limits; the relative humidity should
not cause condensation or formation of frost.
It is recommended that the devices are stored in their packaging; in the case of long storage, espe-
cially in extreme climatic conditions, it is recommended that the device is supplied with power for
some hours before the commissioning, in order to bring the circuits to the rating conditions and to
stabilize the operation of the components.
Note 2 Second element, I2t: t =Kheat/(I2/IB)2 (con I2 ≥ I2>> and t 2min ≤ t ≤ t 2max)
Note 3 First element: 50/51, t = 2351 · t> inv / [(I/I> inv)5.6 - 1], first and second element 67, t = 2351 · t PD > inv / [(I/IPD > inv)5.6 - 1]
Note 4 First element, CAPACITOR: t = t>inv · {50000 / [1.1 · (IRMS/I>inv)17 -1]} + 0.1
Note 5 First element, t = (IMOT-ST / I)2 ∙ t LR>inv with I greater than ILR > inv
Note 6 First element 59, t = 0.5 t U >inv / [(U/U>inv) - 1] and First element 59N, t = 0.5 t UE > / [(UE /UE >inv) - 1]
K
t = t> inv ·
[(I/I> inv)α-1]
Where:
• t = operate time (in seconds)
• t I>inv = setting time multiplier (in seconds)
• I = input current
• I>inv = threshold setting
K = coefficient:
• K = 0.14 for IEC-A curve (Normal Inverse)
• K = 13.5 for IEC-B curve (Very Inverse)
• K = 120 for IEC-B curve (Long Inverse Time)
• K = 80 for IEC-C curve (Extremely Inverse)
Note 1 Symbols are concerning the overcurrent element. The comprehensive overview of the inverse time characteristics concerning the 50/51 and
50N/51N elements is dealt within the PROTECTIVE ELEMENTS section
Note 2 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
Nota 3 With setting more than 2.5 In for the 50/51 elements and 0.5 IEn for the 50N/51N elements, the upper limit of the measuring range is limited to 50
In and 10 IEn respectively.
t [s]
10000 0.14
t =t2> inv ·
[(I2/I2> inv)0.02-1]
1000
t 2> inv
60 s
100
10 s
5s
10
1s
0.5 s
1
0.2 s
0.1 s
0.1 0.02 s
0.01
I2 /I2>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2 /I2 >inv = 700
F_46M-IECA-Char.ai
t [s]
10000
t =t2> inv · 13.5
[(I2/I2> inv) -1]
1000
100
t 2> inv
60 s
10
10 s
5s
1
1s
0.5 s
t> inv = 0.1 s
0.2 s
0.01
I2 /I2>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2 /I2 >inv = 14.5
F_46B-IECB-Char.ai
t [s]
100000
t =t> inv · 80
[(I/I> inv)2-1]
10000
1000
100
t 2> inv
60 s
10
10 s
1 5s
1s
0.1
t 2> inv = 0.02 s t 2> inv = 0.1 s t 2> inv = 0.2 s t 2> inv = 0.5 s
Note: match of operating and setting time takes place when I2 /I2 >inv = 9
F_46M-IECC-Char.ai
t [s]
10000 0.14
t =t (H)> inv ·
[(I/I(H)> inv)0.02-1]
1000
t (H)> inv
60 s
100
10 s
5s
10
1s
0.5 s
1
0.2 s
0.1 s
0.1 0.02 s
0.01 I /I(H)>inv
2 3 4 5 6 7 8 9 10 20 I /I(L)>inv
1.1
Nota: il tempo d’intervento impostato è riferito ad un valore di corrente pari a I/I(H)>inv o I/I(L)>inv= 700
F_51-IECA-Char.ai
t [s]
10000
t =t (H)> inv · 13.5
[(I/I(H)> inv) -1]
1000
100
t (H)> inv
t (L)> inv
60 s
10
10 s
5s
1
1s
0.5 s
0.1 s
0.2 s
0.1 0.02 s
I /I(H)>inv
0.01
2 3 4 5 6 7 8 9 10 20 I /I(L)>inv
1.1
Nota: il tempo d’intervento impostato è riferito ad un valore di corrente pari a I/I(H)>inv o I/I(L)>inv = 14.5
F_51-IECB-Char.ai
t [s]
10000
t =t (H)> inv · 120
[(I/I(H)> inv) -1]
1000
t (H)> inv
t (L)> inv
60 s
100
10 s
5s
10
1s
0.5 s
0.2 s
1
0.1 s
0.1 0.02 s
I /I(H)>inv
0.01
2 3 4 5 6 7 8 9 10 20 I /I(L)>inv
1.1
Nota: il tempo d’intervento impostato è riferito ad un valore di corrente pari a I/I(H)>inv o I/I(L)>inv = 121
F_51N-IEC-LITB-Char.ai
t [s]
100000
t =t (H)> inv · 80
[(I/I(H)> inv)2-1]
t =t (L)> inv · 80
[(I/I(L)> inv)2-1]
10000
1000
100
t (H)> inv
t (L)> inv
60 s
10
10 s
1 5s
1s
0.1
0.02 s 0.1 s 0.2 s 0.5 s
I /I (H)>inv
0.01
2 3 4 5 6 7 8 9 10 20
I /I (L)>inv
1.1
Nota: il tempo d’intervento impostato è riferito ad un valore di corrente pari a I/I(H)>inv o I/I(L)>inv = 9
F_51-IECC-Char.ai
t [s]
10000 0.14
t =t E1> inv ·
[(IE1/IE1> inv)0.02-1]
1000
t E1>inv
t E1>inv
t EC>inv
60 s
100
10 s
5s
10
1s
0.5 s
1
0.2 s
0.1 s
0.1 0.02 s
IE1 /IE1>inv
0.01 IE2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 I /I >inv
1.1 EC EC
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv o IEC/IEC>inv = 700
F_51N-IECA-Char.ai
t [s]
10000
t =t E1> inv · 13.5
[(IE1/IE1> inv) -1]
1000
100
t E1>inv
t E2>inv
t EC>inv
60 s
10
10 s
5s
1
1s
0.5 s
0.1 s
0.2 s
0.1 0.02 s
IE1 /IE1>inv
0.01 IE2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 IEC /IEC >inv
1.1
Note: match of operating and setting time takes place when IIE1/IE1>inv, IE2 /IE2 >inv o IEC/IEC>inv = 14.5
F_51N-IECB-Char.ai
t [s]
10000
t =t E1> inv · 120
[(IE1/IE1> inv) -1]
1000
t E1>inv
t E2>inv
t EC>inv
60 s
100
10 s
5s
10
1s
0.5 s
1 0.2 s
0.1 s
0.1 0.02 s
I E1/IE1>inv
0.01 I E2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 I EC /IEC >inv
1.1
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv o IEC/IEC>inv = 121
F_51N-IEC-LITB-Char.ai
t [s]
100000 80
t =t E1> inv ·
[(IE1/IE1> inv)2-1]
t =t E2> inv · 80
[(IE2/IE2> inv)2-1]
t =t EC> inv · 80
[(IEC/IEC> inv)2 -1]
10000
1000
100
t E1>inv
t E2>inv
t EC>inv
60 s
10
10 s
1 5s
1s
0.1
0.02 s 0.1 s 0.2 s 0.5 s
I E1/IE1>inv
0.01 I E2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 I EC /IEC >inv
1.1
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv o IEC/IEC>inv = 9
F_51-IECC-Char.ai
t [s]
10000 0.14
t =t ED> inv ·
[(IED/IED> inv)0.02-1]
1000
t ED> inv = 60 s
t ED>> inv = 60 s
100
t ED> inv = 10 s
t ED>> inv = 10 s
t PD> inv = 5 s
10 t ED>> inv = 5 s
t ED> inv = 1 s
t ED>> inv = 1 s
0.01 IED/IED>
2 3 4 5 6 7 8 9 10 20 IED/IED>>
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 700 or IED/IED>>inv = 700
F_67N-IECA-Char.ai
t [s]
10000
t =t ED> inv · 13.5
[(IED/IED> inv)-1]
1000
100
t ED> inv = 60 s
t ED>> inv = 60 s
10
t ED> inv = 10 s
t ED>> inv = 10 s
t ED> inv = 5 s
t ED>> inv = 5 s
1
t ED> inv = 1 s
t ED>> inv = 1 s
t [s]
100000
t =t ED> inv · 80
[(IED/IED> inv)2-1]
t =t ED>> inv · 80
[(IED/IED>> inv)2-1]
10000
1000
100
t ED> inv = 60 s
10 t ED>> inv = 60 s
t ED> inv = 10 s
t ED> inv = 10 s
t ED> inv = 5 s
1
t ED> inv = 5 s
t ED> inv = 1 s
t ED> inv = 1 s
0.1
t ED> inv = 0.02 s t ED> inv = 0.1 s t ED> inv = 0.2 s t ED> inv = 0.5 s
t ED>> inv = 0.02 s t ED>> inv = 0.1 s t ED>> inv = 0.2 s t ED>> inv = 0.5 s
IED /IED>inv
0.01
IED /IED>>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 9 o IED/IED>>inv = 9
F_67N-IECC-Char.ai
t [s]
10000
1000
t EDC> inv
60 s
100
10 s
5s
10
1s
0.5 s
1
0.2 s
0.1 s
0.1 0.02 s
Note: match of operating and setting time takes place when IECL/IEDC> inv o IECH/IEDC> inv = 700
F_51-IECA-Char.ai
t [s]
10000
100
t EDC> inv
60 s
10
10 s
5s
1
1s
0.5 s
0.1 s
0.2 s
0.1 0.02 s
t [s]
100000
t = t EDC> inv · 80
[(IECH/IEDC> inv)2-1]
t = t EDC> inv · 80
[(IECL/IEDC> inv)2-1]
10000
1000
100
t EDC> inv
60 s
10
10 s
1 5s
1s
0.1
0.02 s 0.1 s 0.2 s 0.5 s
Nota: il tempo d’intervento impostato è riferito ad un valore di corrente pari a IECL/IEDC> inv o IECH/IEDC> inv = 9
F_67N(Comp)-IECBC-Char.ai
K
t = t> inv · +L
[(I/I> inv)α-1]
Where:
• t = operate time (in seconds)
• t I>inv = setting time multiplier (in seconds)
• I = input current
• I>inv = threshold setting
K = coefficient:
• K = 0.01 for ANSI/IEEE Moderately inverse curve
• K = 3.922 for ANSI/IEEE Very inverse curve
• K = 5.64 for ANSI/IEEE Extremely inverse curve
L = coefficient:
• L = 0.023 for ANSI/IEEE Moderately inverse curve
• L = 0.098 for ANSI/IEEE Very inverse curve
• L = 0.024 for ANSI/IEEE Extremely inverse curve
Note 1 Symbols are concerning the overcurrent element. The comprehensive overview of the inverse time characteristics concerning the 50/51 and
50N/51N elements is dealt within the PROTECTIVE ELEMENTS section
Note 2 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
Nota 3 With setting more than 2.5 In for the 50/51 elements and 0.5 IEn for the 50N/51N elements, the upper limit of the measuring range is limited to 50
In and 10 IEn respectively.
t [s]
10000
t =t 2> inv · 0.01
+ 0.023
[(I2/I2> inv)0.02 -1]
1000
100
t 2> inv
60 s
10
10 s
1 5s
0.01
I2 /I2 >inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2 /I2 >inv = 1.664
F_46LT-ANSIMI-Char.ai
t [s]
10000
t =t 2> inv · 3.922
+ 0.092
[(I2/I2> inv)2 -1]
1000
100
10 t 2> inv
60 s
10 s
1
t 2> inv = 0.02 s
1s
0.1
0.01
I2 /I2 >inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2 /I2 >inv = 2.306
F_46LT-ANSIVI-Char.ai
t [s]
10000
t =t 2> inv · 5.64
+ 0.024
[(I2/I2> inv)2 -1]
1000
100
10
t 2> inv
60 s
1
t 2> inv = 0.02 s
0.1
0.01
I2 /I2 >inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2 /I2 >inv = 2.789
F_46LT-ANSIEI-Char.ai
t [s]
10000
t =t (H)> inv · 0.01
+ 0.023
[(I/I(H)> inv)0.02 -1]
1000
100
t (H)> inv
t (L)> inv
60 s
10
10 s
1 5s
0.1 s 1s
0.5 s
0.2 s
0.1
0.02 s
I /I (H) >inv
0.01 I /I (L) >inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv = 1.664
F_51-ANSIMI-Char.ai
t [s]
10000
t =t (H)> inv · 3.922
+ 0.092
[(I/I(H)> inv)2 -1]
1000
100
t (H)> inv
10 t (L)> inv
60 s
10 s
1
0.02 s
0.1 s 5s
0.2 s
0.5 s
1s
0.1
I /I (H) >inv
0.01
2 3 4 5 6 7 8 9 10 20 I /I (L) >inv
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv = 2.306
F_51-ANSIVI-Char.ai
t [s]
10000
t =t (H)> inv · 5.64
+ 0.024
[(I/I(H)> inv)2 -1]
1000
100
10
t (H)> inv
t (L)> inv
60 s
1
0.02 s
0.1 s
0.2 s 10 s
0.5 s
5s
1s
0.1
I /I (H) >inv
0.01
2 3 4 5 6 7 8 9 10 20 I /I (L) >inv
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv= 2.789
F_51-ANSIEI-Char.ai
t [s]
10000 0.01
t =t E1> inv · + 0.023
[(IE1/IE1> inv)0.02 -1]
100
t E1>inv
t E2>inv
t EC>inv
60 s
10
10 s
1 5s
0.1 s 1s
0.5 s
0.2 s
0.1
0.02 s
IE1/IE1>inv
0.01 IE2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 IEC /IEC >inv
1.1
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv or IEC /IEC>inv = 1.664
F_51N-ANSIMI-Char.ai
t [s]
10000
t =tE1> inv · 3.922
+ 0.092
[(IE1/IE1> inv)2 -1]
1000
100
t E1>inv
10 t E2>inv
t EC>inv
60 s
10 s
1
0.02 s
0.1 s 5s
0.2 s
0.5 s
1s
0.1
IE1/IE1>inv
0.01 IE2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 IEC /IEC >inv
1.1
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv or IEC /IEC>inv = 2.306
F_51N-ANSIVI-Char.ai
t [s]
10000
t =t E1> inv · 5.64
+ 0.024
[(IE1/IE1> inv)2 -1]
100
10
t E1>inv
t E2>inv
t EC>inv
60 s
1
0.02 s
0.1 s
0.2 s 10 s
0.5 s
5s
1s
0.1
IE1/IE1>inv
0.01 IE2 /IE2 >inv
2 3 4 5 6 7 8 9 10 20 IEC /IEC >inv
1.1
Note: match of operating and setting time takes place when IE1/IE1>inv, IE2 /IE2 >inv or IEC /IEC>inv = 2.789
F_51N-ANSIEI-Char.ai
t [s]
10000
t =tED> inv · 0.01
+ 0.023
[(IED/IED> inv)0.02 -1]
1000
100
t ED> inv
60 s
10
10 s
1 5s
0.01
IED/IED>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 1.664
F_67N-ANSIMI-Char.ai
t [s]
10000
t =tED> inv · 3.922
+ 0.092
[(IED/IED> inv)2 -1]
1000
100
10 t ED> inv
60 s
10 s
1
t ED> inv = 0.02 s
1s
0.1
0.01
IED/IED>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 2.306
F_67N-ANSIVI-Char.ai
t [s]
10000
t =tED> inv · 5.64
+ 0.024
[(IED/IED> inv)2 -1]
1000
100
10
t ED> inv
60 s
1
t ED> inv = 0.02 s
0.1
0.01
IED/IED>inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 2.789
F_67N-ANSIEI-Char.ai
t [s]
10000 0.01
t =tEDC> inv · + 0.023
[(IEDH /IEDC> inv)0.02 -1]
1000
100
tEDC> inv
60 s
10
10 s
1 5s
0.1 s 1s
0.1
Note: match of operating and setting time takes place when IEDH /IEDC>inv or IEDL /IEDC>inv = 1.664
F_67NC-ANSIMI-Char.ai
t [s]
10000
1000
100
tEDC> inv
10
60 s
1 10 s
0.02 s
0.1 s 5s
0.2 s
0.5 s
0.1 1s
Note: match of operating and setting time takes place when IEDH /IEDC>inv or IEDL /IEDC>inv = 2.306
F_67N(Comp)-ANSIVI-Char.ai
t [s]
10000
1000
100
10
tEDC> inv
60 s
0.02 s
0.1 s 10 s
0.2 s
5s
1s
0.1
0.5 s
IPD/IPD>inv
0.01
2 3 4 5 6 7 8 9 10 20
IPD/IPD>>inv
1.1
Note: match of operating and setting time takes place when IEDH /IEDC>inv or IEDL /IEDC>inv = 2.789
F_67N(Comp)-ANSIEI-Char.ai
— Mathematical formula
The mathematical formula for RECTIFIER, I-squared-t (I2t) and Electromechanical curves (EM) is:[1]
K
t = t>inv ·
A·(I/I> inv)α-B]
Where:
K = coefficient:
• K = 2351 for RECTIFIER curve (RI)
• K = 16 for I2t curve
• K = 0.28 for Electromechanical curve (EM)
A = coefficient:
• A = 1 for RECTIFIER curve (RI)
• A = 1 for I-squared-t (I2t) curve
• A = -0.236 for Electromechanical curve (EM)
B = coefficient:
• B = 1 for RECTIFIER curve (RI)
• B = 0 for I-squared-t (I2t) curve
• B = -0.339 for Electromechanical curve (EM)
Note 1 Symbols are concerning the overcurrent element. The comprehensive overview of the inverse time characteristics concerning the 50/51 and
50N/51N elements is dealt within the PROTECTIVE ELEMENTS section
Note 2 When the input value is more than 20 times the set point , the operate time is limited to the value corresponding to 20 times the set point
Nota 3 With setting more than 2.5 In for the 50/51 elements and 0.5 IEn for the 50N/51N elements, the upper limit of the measuring range is limited to 50
In and 10 IEn respectively.
t [s]
1000 000 2351
t =t (H)> inv ·
[(I/I(H)> inv)5.6 -1]
100 000
10 000
t (H)> inv
t (L)> inv
1000
100 60 s
10 s
5s
10
1s
0.5 s
1
0.1 s
0.1 0.02 s
0.1 s
I /I (H) >inv
0.01
I /I (L) >inv
2 3 4 5 6 7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv = 4
F_51-RI-Char.ai
t [s]
10000
16
t = t 2 >inv ·
[(I2 /I2 > inv)2]
1000
100
10
t2>inv = 60 s
t 2 >inv = 1 s
1
t 2 >inv = 0.5 s
t2>inv = 5 s
t 2 >inv = 0.02 s
t2>inv = 5 s
0.1
t 2 >inv = 0.1 s
Note: match of operating and setting time takes place when I2/I2>inv = 4
F_46M-I2t-Char.ai
t [s]
10000
t =t (H)> inv · 16
[(I/I(H)> inv)2]
t =t (L)> inv · 16
[(I/I(L)> inv)2]
t =t (H)>> inv · 16
[(I/I(H)>> inv)2]
1000
t =t (L)>> inv · 16
[(I/I(L)>> inv)2]
100
10 t (H)> inv
t (L)> inv
t (H)>> inv
t (L)>> inv
60 s
1s
1
0.5 s
0.2 s 10 s
10 s
5s
t>inv = 0.02 s 5s
0.1
t>inv = 0.1 s
I /I (H)>inv I /I (L)>inv
0.01
2 3 4 5 6 7 8 9 10 20 I /I (H)>>inv I /I (L)>>inv
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv = 4
F_51-I2t-Char.ai
t [s]
10000
t =tPD> inv · 16
[(IPD/IPD> inv)2]
t =tPD>> inv · 16
[(IPD/IPD>> inv)2]
1000
100
10
t PD> inv = 1 s
t PD> inv = 60 s
t PD>> inv = 1 s
t PD>> inv = 60 s
t PD> inv = 0.5 s
t PD>> inv = 0.5 s
1 t PD> inv = 0.2 s
t PD>> inv = 0.2 s
t PD> inv = 5 s
t PD>> inv = 5 s
0.1
0.01
IPD/IPD>inv
2 3 4 5 6 7 8 9 10 20 IPD/IPD>>inv
1.1
Note: match of operating and setting time takes place when IPD/IPD>inv = 4 or IPD/IPD>>inv = 4
F_67-I2t-Char.ai
t [s]
10000
t =t2> inv · 0.28
[-0.236 · (I2/I2> inv)-1+0.339]
1000
100
t2> inv
60 s
10 10 s
5s
1
1s
0.5 s
0.1
0.01
2 3 4 5 6
I2 /I2>inv
7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I2/I>inv = 4
F_46LT-EM-Char.ai
t [s]
10000
t =t (H)> inv · 0.28
[-0.236 · (I/I(H)> inv)-1+0.339]
1000
100
t (H)>> inv
t (L)>> inv
60 s
10 10 s
5s
1
1s
0.5 s
0.02 s 0.2 s
0.1 s
0.1
I /I(H)>inv
0.01
2 3 4 5 6
I /I(L)>inv
7 8 9 10 20
1.1
Note: match of operating and setting time takes place when I/I(H)>inv or I/I(L)>inv = 4
F_51-EM-Char.ai
t [s]
10000
t =tE > inv · 0.28
[-0.236 · (IE /IE > inv)-1+ 0.339]
0.28
t = tEC> inv ·
[-0.236 · (IEC /IEC> inv)-1+ 0.339]
1000
100 t E>inv
t EC>inv
60 s
10 10 s
5s
1
1s
0.5 s
0.02 s 0.2 s
0.1 s
0.1
IE /IE >inv
0.01
2 3 4 5 6 7 8 9 10
IEC /IEC >inv
20
1.1
Note: match of operating and setting time takes place when IE /IE >inv or IEC /IEC>inv = 4
F_51N-EM-Char.ai
t [s]
10000
t =tED> inv · 0.28
[-0.236 · (IED/IED> inv)-1+ 0.339]
1000
t ED> inv
100
t ED>> inv
60 s
10
10 s
5s
1
1s
0.5 s
0.2 s
0.1 s
0.1
0.02 s
IED/IED>inv
0.01
2 3 4 5 6 7 8 9 10
IED/IED>>inv
20
1.1
Note: match of operating and setting time takes place when IED/IED>inv = 4 or IED/IED>>inv = 4
F_67N-EM-Char.ai
t [s]
10000
t =tEDC> inv · 0.28
[-0.236 · (IEDC /IEDH> inv)-1+ 0.339]
tEDC> inv
100 tEDC>> inv
60 s
10
10 s
5s
1
1s
0.5 s
0.2 s
0.1 s
0.1
0.02 s
Note: match of operating and setting time takes place when IEDC /IEDH>inv = 4 or IEDC /IEDH>>inv = 4
F_67N-EM-Char.ai
NVA100X-D
4-20 mA OC1E
A1 A 1
I L1-L
A2 + KC1-1 3
Mis.1 # / ∩ - 1
OUTPUT RELAYS
I E-1 B1 ≅ B KC1-4
A8 UAUX + 9
B2 Mis.3 # / ∩ - 10
10
11
C1 C B3 KC1-5
I L1-H U L1 12
C2 B4 + 11 13
SIDE H CURRENT INPUTS
C3 B5 Mis.4 # / ∩ - KC1-6
VOLTAGE INPUTS
12
I L2-H U L2 14
13
C4 B6
14 15
C5 B7 KC1-7
I L3-H + 17
U L3 15
C6 B8 Mis.5 # / ∩ - 16
16
17 18
B9 KC1-8
C7 18 20
UE
I E-2 19
B10 +
C8 19
Mis.6 # / ∩ -
20
AUX-IN Pt100
IN1C
IN2D PT1
1
IN1 1 T1 MPT1
1 1 2
IN1-1 IN2-1 OC2F GND1
1 3
IN2 2
2 2 KC2-1 3 PT2
IN1-2 IN2-2 T2
4
2 MPT2
5
IN3 3 4 GND2
3 3 6
IN1-3 IN2-3 KC2-2 6 PT3
IN4 5 T3
7
4 MPT3
4 4 8
IN1-4 IN2-4 7 GND3
5 5 5 KC2-3 9
IN5 7
7 7 8 PT4
10
IN1-5 IN2-5 T4 MPT4
9 11
IN6 8 KC2-4 GND4
8 8 12
IN1-6 IN2-6 10 PT5
13
IN7 9 11 T5 MPT5
9 9 KC2-5 14
IN1-7 IN2-7 GND5
12 15
IN8 10 PT6
10 10 13 16
BINARY INPUTS
IN2-8
BINARY INPUTS
IN1-8 T6 MPT6
6 6 6 KC2-6 17
14 GND6
IN9 11 18
11 11
IN1-9 IN2-9 15 PT7
KC2-7 T7
19
IN10 12 17 MPT7
20
12 12
IN1-10 IN2-10 16 GND7
21
IN11 18 PT8
13 13 13 KC2-8 22
IN1-11 IN2-11 20 T8 MPT8
23
19 GND8
IN12 14 14 24
14
IN1-12 IN2-12
15 15 15 IRIG-B
17
IN13
17 17 X
IN2-13
BLOCK OUT
IN1-13
BLOUT-
AM IRIG-B IN X1
IN14 18
18 18 BLOUT+ X2
IN1-14 IN2-14
IRIG-B/1PPS IN
IN15 19
19 19 B-
RS485
IN1-15 IN2-15 X5
1PPS OUT A+
IN16 X6
20 20 20
IN1-16 IN2-16 IRIG-B OUT
16 16 16
Ethernet locale TX [1]
ETHERNET
X B- 5
Supervision
RS485
A+ 6
unit
TX [1]
ETHERNET
TX [1]
Note [1]
TX [1]
ETHERNET
FX [1]
ETHERNET
FX [1]
FRONT PANEL
Interfaces.ai
NVA100X-D
I L1-L , I L2-L , I L3-L
74CT
74TCS Note *: when 87NHIZ is enabled, the 50N/51N/67N functions
I E2
50N.2/51N.2 * 87NHIZ
BF can not be used with residual current (IE) measured directly
U L1, U L2 , U L3
UE
32P
U E U EC U E U EC I ECH I ECL
UE U EC
37 27
37P 27V1
52 59N 67N 67N(Comp)
40 55
METERING SYNCHRONIZING
46 59
I ECH I ECL
66 59V2 - I L1..I L3,I E,.... - SNTP
26
- Oscillography - IRIG-B
49 81O
M 50/51 81U
- Events & Faults log
50N/51N(Comp)
I ECH I ECL 51LR 74VT
CONTROL & MONITORING COMMUNICATION
87M - Modbus RS485
- TCS
I L1-H, I L2-H, I L3-H - Modbus TCP/IP
74CT 50/51 - CB MONITORING,..
- IEC61850
- IEC 870-5-103/DNP3
L1 L2 L3 NVA100X-D
P2 C1
S2
IL1H
S1 C2
P1 C3 74TCS
IL1H, IL2H, IL3H
IL2H
C4
C5
IL3H
C6
74CT
P1 C7
S1
IE2 50N.1/51N.2
S2 C8
P2
A N n a B3
B N n b UL1
B4
C N n c UL1, UL2 , UL3
B5
UL2
B6
B7 87G
UL3
B8
21 74VT
UE UEC
dn da IECH IECL
37 27
dn db B9
(*) UE UEC UE UEC
dn dc
B10 37P 27V1
(*) Antiferrorisonance 67N(Comp)
40 47
26 IECH IECL
G 59N 67N
46 59
49 59V2
IL1L 50N/51N(Comp)
P1 A2
S1
A3 50/51 81O
S2
P2 IL2L
A4 51V 81U
A5 IL1L , IL2L , IL3L
74CT BF
IL3L
A6
IECH
87NHIZ * 64REF
A7
P1 IE1 50N.1/51N.1
A8
S1
S2
P2 Note *: when 87NHIZ is enabled, the 50N/51N/67N functions
can not be used with residual current (IE) measured directly
NOTE
- To current with incoming direction in the protected component must match incoming current in the reference terminals of of the relay current inputs ,
while to current having a outgoing direction from the protected component must match output current in the reference terminals of the current inputs
of the relay.
- The input current in the reference terminals of of the relay current inputs of the are considered positive, negative for outgoing ones.
- This Convention applies: the CTs polarity P1 to the protected component.
P2 A1
S2
IL1L
S1 A2
74TCS
P1 A3
IL1L , IL2L , IL3L
IL2L
A4
A5 74CT
IL3L
A6
BF
85NHIZ
P1 C7
*
32P 27
S1
C8
IE2 50N.2/51N.2
S2
P2 37 27V1
dn da
dn db B9 37P 55
(*) UEC UE UEC UE UEC IECH IECL
dn dc
B10
UE
40 59
B3
59N 67N 67N(Comp) 66 81O
A N n a
B N n b UL1
B4 49 81U
C N n c UEC
B5
UL2 IECH IECL 50/51 74VT
B6
B7 IECH IECL 51LR
UL3
B8
50N/51N(Comp) 87M
M
C1
74CT
IL1H
P1 C2
S1
C3
S2 IL1H, IL2H, IL3H
P2 IL2H
C4
C5
IL3H
C6
NOTE
- Incoming currents to the protected transformer must match to the the reference current inputs of the relay, with current direction leaving the
protected transformer must match current output from the current inputs of the relay.
- Incoming currents in the reference terminals of of the relay current inputs are considered positive, the outgoing negative.
- This convention applies to indicate the P1 CTs polarity toward the protected transformer.
n a B3
n b UL1
B4
n c
B5 UL1, UL2 , UL3
UL2
B6
B7
87T
UL3
B8
A N
B N 21 74VT
UE UEC
C N IECH IECL
37 27
dn da
dn db B9
UE UEC UE UEC 37P 27V1
dn dc (*)
B10 67N(Comp)
(*) Antiferrorisonance 40 47
IECH IECL
26
46 59
G 59N 67N
59V2
49
50N/51N(Comp)
IL1L 81O
P1 A2 50/51
S1
A3
S2
P2 IL2L 51V 81U
A4 IL1L , IL2L , IL3L
A5 74CT BF
IL3L
A6 IECH
87NHIZ * 64REF
A7
IE1 50N.1/51N.1
P1 A8
S1
S2
P2 Note *: when 87NHIZ is enabled, the 50N/51N/67N functions
can not be used with residual current (IE) measured directly
NOTE
- To current with incoming direction in the protected component must match incoming current in the reference terminals of of the relay current inputs ,
while to current having a outgoing direction from the protected component must match output current in the reference terminals of the current inputs
of the relay.
- The input current in the reference terminals of of the relay current inputs of the are considered positive, negative for outgoing ones.
- This Convention applies: the CTs polarity P1 to the protected component.
P2 C1
S2
IL1H
S1 C2
P1 C3 74TCS
IL1H, IL2H, IL3H
IL2H
C4
C5 74CT
IL3H
C6
C7
50/51
P1
S1 IECH
IE2 50N.2/51N.2 50N/51N(Comp)
S2 C8
P2
87NHIZ.2 *
26
A7 IECL
87T
A8
IE1 50N.1/51N.1 64REF 50N/51N(Comp)
P1
S1
S2 87NHIZ.1 *
P2
A N n a B3
B N n b UL1
B4
C N n c 27
B5
UL2 UL1, UL2 , UL3
B6 27V1
B7
B8
UL3 37 47
dn da 46 59
dn db B9
(*) UE UEC 49 59V2
dn dc
B10
(*) Antiferrorisonance 81O
50/51
IL1L
P1 A2
S1 59N BF 81U
A3
S2 IL1L , IL2L , IL3L
P2 IL2L 74CT
A4 74VT
A5
IL3L
A6
Note *: when 87NHIZ is enabled, the 50N/51N/67N functions can not be
used with residual current (IE) measured directly
NOTE
- Incoming currents to the protected transformer must match to the the reference current inputs of the relay, with current direction leaving the
protected transformer must match current output from the current inputs of the relay.
- Incoming currents in the reference terminals of of the relay current inputs are considered positive, the outgoing negative.
- This convention applies to indicate the P1 CTs polarity toward the protected transformer.
In 5A 1A 5A U En 100V
NVA100-DX#MM00
158.0 ±0.3
164.4
177
156
164.4
RACK MOUNTING
482.6
465
177 (4U)
101.6
DSP CPU
Firmware Firmware Documentation Communication Date Description
Release Release
is in conformity with the previsions of the following EC directives (including all applicable amendments) when installed in accordance
with the installation instructions:
Reference n° title
2014/35/EC Low Voltage Directive
2014/30/EC EMC Directive
Reference of standards and/or technical specifications applied for this declaration of conformity or parts thereof:
- harmonized standards:
EN 61010-1 2010 Safety requirements for electrical equipment for measurement, control and laboratory use
Signature .............................................
Headquarters: 20139 Milano - Piazza Mistral, 7 - Tel. +39 02 574 957 01 ra - Fax +39 02 574 037 63
Factory: 35127 Padova - Z.I. Sud - Via dell’Artigianato, 48 - Tel. +39 049 894 770 1 ra - Fax +39 049 870 139 0