Lecture 9: Dynamic logic

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 1

Dynamic CMOS

• In static circuits at every point in time (except when

switching) the output is connected to either GND
or VDD via a low resistance path.
– fan-in of n requires 2n (n N-type + n P-type) devices

• Dynamic circuits rely on the temporary storage of

signal values on the capacitance of high
impedance nodes.
– requires on n + 2 (n+1 N-type + 1 P-type) transistors

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 2

Dynamic Gate

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 4

Conditions on Output

• Once the output of a dynamic gate is discharged, it

cannot be charged again until the next precharge
operation.
• Inputs to the gate can make at most one transition
during evaluation.

• Output can be in the high impedance state during

and after evaluation (PDN off), state is stored on
CL à Output in high state

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 5

Properties of Dynamic Gates

• Logic function is implemented by the PDN only

– number of transistors is N + 2 (versus 2N for static complementary
CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not affect
the logic levels
• Faster switching speeds
– reduced load capacitance due to lower input capacitance (Cin)
– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into discharging CL

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 6

Properties of Dynamic Gates

• Overall power dissipation usually higher than static

CMOS
• no static current path ever exists between VDD and GND
(including Psc)
• no glitching
• higher transition probabilities
• extra load on Clk
• PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
• Needs a precharge/evaluate clock

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 7

Properties of dynamic logic

t pLH = 0
CLVDD CL is reduced because no PUN and
t pHL = because output node drives smaller
2I DN
cap
IDN is reduced due to presence of
foot transistor
à Net effect is reduction of tpHL
(reduced CL is dominating)

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 8

Properties of dynamic logic

• Static Noise margin

– VIN>Vth,N à Vout=0
– VIL=VTh,N, VIH=VTh,N
– NML=VTh,N, NMH=VDD-VTh,N
• Dynamic noise margin
– Better immunity to 0à1 glitches then NML would
indicate

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 9

Dynamic power

• Pdyn=CLVDD2f0à1
• Compared to static CMOS: CL¯, f0à1­
• Dynamic gates: f0à1=fCLKp0
• Static gates: f0à1=fCLKp0p1
• EX) NOR2
– PA=0.5, PB=0.5, P1=0.25, P0=0.75
– Dynamic gate f0à1=0.75fclk
– Static gate f0à1=0.188fclk
• But dynamic logic has no glitch. à no power
consumption with glitch à careful timing is
required

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 10

Solution to Charge Leakage

Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 11

Issues in Dynamic Design 2: Charge Sharing

Charge stored originally on

Clk Mp CL is redistributed (shared)
Out over CL and CA leading to
A CL reduced robustness
B=0 CA

Clk Me CB

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 12

Charge Sharing Example

Clk
Out
A A CL=50fF

Ca=15fF B B B !B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 13

Charge Sharing

VDD

Clk Mp
Out

CL
A Ma
X

Ca
B=0 Mb

Cb
Clk Me

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 14

EX) Charge sharing

VDD

CLK Cx

B C Cx
Y Z

CLK CY Cz

GND

Let Cx : Cy=1 : 10, estimate steady-state output

voltage at Y under the worst case charge sharing
condition

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 15

Solution to Charge Redistribution

Clk Mp Mkp Clk

Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 16

Issues in Dynamic Design 3: Backgate Coupling

Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 17

Backgate Coupling Effect

Out1
Voltage

Clk

In Out2

Time, ns

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 18

Issues in Dynamic Design 4: Clock Feedthrough

Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
B
voltage of Out can rise above
VDD. The fast rising (and
Clk Me falling edges) of the clock
couple to Out.

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 19

Clock Feedthrough

Clock feedthrough
Clk
Out
In1
In2 Voltage

In3 In &
Clk
In4 Out
Clk
Time, ns
Clock feedthrough

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 20

Cascading Dynamic Gates

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

ΔV
Out2

Only 0 ® 1 transitions allowed at inputs!

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 21

Domino Logic

Clk Mp Clk Mp Mkp

1®1
Out1 Out2
1®0
0®0
In1 0®1
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 22

Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 23

Properties of Domino Logic

• Only non-inverting logic can be implemented

• Very high speed
– only L-H transition
– Input capacitance reduced – smaller logical effort

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 24

Designing with Domino Logic

VDD VDD
VDD

Clk Mp Clk Mp Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!

Clk Me Clk Me

Inputs = 0
during precharge

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 25

Footless Domino

Reduces clock load

Increase discharge current
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
àA solution is to delay the clock for each stage (Too much burden)
Don’t connect more than 2-3 non footed gates in series
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 26
Differential (Dual Rail) Domino

off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B

Clk Me

Solves the problem of non-inverting logic

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 27

np-CMOS

Clk Mp Clk Me
1®1
Out1
1®0
In1 In4 PUN
In2 PDN In5
0®0
In3 0®1
Out2
(to PDN)
Clk Me Clk Mp

Only 0 ® 1 transitions allowed at inputs of PDN

Only 1 ® 0 transitions allowed at inputs of PUN

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 28

Mixing Domino CMOS Logic with Static CMOS Logic

• We can add an even number of static CMOS inverting

logic gates after a Domino logic stage prior to the next
Domino logic stage
– Even number of inverting stages guarantees that inputs
to the second Domino logic stage experience only 0-to-
1 transitions

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 29