Lecture 8: Ratioed logic

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

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Ratioed Logic

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Ratioed Logic

xVDD

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Active Loads

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Pseudo-NMOS

MP Vin=0 à Vout=VDD
Vin=VDDà VOL>0
vout
MN
vi

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Pseudo-NMOS

Vin=VDDà VOL>0
MP IDP NMOS: Linear
PMOS: Vel. Sat
vout
MN IDN
vi

I DN + I DP = 0
2 2
VOL VDSAT
K N [(VDD - VTn )VOL - ] + K P [(-VDD - VTp )VDSAT - ]=0
2 2

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Pseudo-NMOS

• Impact of Kn &Kp on VOL

• Assume VOL<<VDD-VTn ; |VDSAT|<<VDD+VTp

K N (VDD - VTn )VOL + K P [(-VDD - VTp )VDSAT ] = 0

K P [(VDD + VTp )VDSAT µ pW p
VOL = » VDSATp
K N (VDD - VTn ) µ nWn

VOL ¯ as Wp/Wn ¯ à PMOS Rp >> Rn

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Pseudo-NMOS

• Pstatic =PDC=VDD x ILOW

• =VDDKPVDSAT[(-VDD-VTP)-VDSATp/2]
• Pstatic reduces as Kp àWp ¯
• VOL & Pstatic move in the same direction
• Why not simply make Wp = Wmin

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Pseudo-NMOS VTC

3.0

2.5

2.0 W/Lp = 4

1.5
Vout [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

tPLH will suffer à Trade off between (VOL, Pstatic) vs tPLH

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Pseudo-NMOS

Vin = VDD
MP IDP If Kp ↑ to reduce tPLH
Then more/increased contention
vout @ output node
MN IDN
vi Thus, tPHL ↑

Let’s verify in the next slide

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Psueto-NMOS

Rising transient response

$
#% &
𝑉! 𝑡 = 𝑉"" (1 − 𝑒 ! )

Falling transient response

$
𝑉"" #
𝑉! 𝑡 = (𝑅( 𝑒 (%! ||%" )& + 𝑅' )
𝑅' + 𝑅(
% ,-%"
Time to reach -(%# ,% )
𝑉"" à (V(0)+V(final))/2
# "

T=0.69(𝑅( | 𝑅' 𝐶
Transient response is determined only by RC.
Large Kp increases total C. à delay increases
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Improved Loads

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Improved Loads (2)

VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

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Improved Loads (2)

VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS
PDN1 & PDN2 are mutually exclusive
Only 1 is on for any input combination
Vout and Vout are logical inverse
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Example AND/NAND

VNAND VAND
B

A A B

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DCVSL Example

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Why differential in logic (DCVSL)

• Can eliminate one inverter delay

• Note however in DCVSL usually tPHL¹tPLH and thus
differential outputs are not perfectly synchronized.
à careful design is required

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DCVSL Transient Response

2.5

AB
V ol tage [V]

1.5
AB
A,B
0.5 A,B

-0.5 0 0.2 0.4 0.6 0.8 1.0

Time [ns]

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The operation of DCVSL

MP1 MP2 PDN1 = ON,

PDN2 = OFF
Vo Vo
VDD

Vo ¯ à MP2 is on à MP1 is turned off (contention is removed)

VO=VDD VOL=0

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DCVSL

• Rail to rail swing. Zero static power consumption

• Ratioed logic
• Short circuit power + dynamic power

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How to size

Vout £ VDD + VTP

0
NFET à vel.sat
Vo
PFET à linear
VDD
Equation?

Do the same thing for PDN2

Keep MP1 and MP2 identical.

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How to size

𝑉! ≤ 𝑉"" + 𝑉.(
0
NFET à vel.sat
Vo
PFET à linear
VDD

-
𝑉"01.
𝐾' 𝑉"" − 𝑉./ 𝑉"01. −
2
(𝑉3 − 𝑉"" )-
+𝐾( −𝑉"" − 𝑉.2 (𝑉! −𝑉"" ) − =0
2

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Cross coupled transistors

Vy
Vinit,y
R: output resistance Vx R C
C: gate capacitance

Vx
Vinit,x
Vy R C

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Latch – latching phase

Vy
g mVx + + sCLV y - C LV y ,init = 0 (1)
R
Vx
g mVy + + sCLVx - C LVx ,init = 0 (2)
R
By taking (1) – (2)

DV
g m DV - - sCL DV + CL DVinit = 0
R

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Latch – latching phase

g m R -1
t
DV = DVinit e RC

For a large gain,

wT t
DV » DVinit e
Cross coupled positive feedback circuit converges with the
maximum possible rate if the gate capacitances are the
dominating ones

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Transit Frequency

𝑔4
𝜔. =
𝐶50

• Transit frequency, fT, is defined as the

frequency where the current gain from input
to output drops to 1.

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MOS device fT

Cgd
vgs
iout

iin Cgs gmvgs ro

iout gm
=
iin jw (Cgs + Cgd )
At unity gain frequency wT, iout=iin

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MOS Device fT

gm
fT =
2p (Cgs + Cgd )
W ∆=Vgs-Vth
µCox D
Leff 3µD
= »
2
2p ( WLeff Cox + 2Col ) 4 pL eff
2

Increase overdrive and decrease gate length

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MOS Device fT

Ft
3µD
1.00E+12
fT =
4pLeff
2
Frequency (Hz)

1.00E+11

Mobility degradation
1.00E+10
0 0.2 0.4 0.6 0.8
Vgs

Mobility degradation from vertical field

µn
µeff =
1 + q (Vgs - Vth )
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