Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-1

LECTURE 040 – COMMON SOURCE AND EMITTER OUTPUT

STAGES
(READING: GHLM – 384-398, AH – 218-221)
Objective
The objective of this presentation is:
Show how to design stages that
1.) Provide sufficient output power in the form of voltage or current.
2.) Avoid signal distortion.
3.) Be efficient
4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.)
Outline
• Common source stage
• Common emitter stage
• Summary

ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-2

COMMON SOURCE OUTPUT STAGE

Current source load inverter
VDD iD vOUT
VDD+|VSS|
RL VDD
M2

Cutoff
VGG2 IQ iOUT RL dominates
vOUT VDD
IQ as the load line vIN
iD1 VSS

Triode
vIN M1CL RL vOUT
IQRL IQRL VSS
VSS VDD
Fig. 040-1
VSS

A Class A circuit has current flow in the MOSFETs during the entire period of a
sinusoidal signal.
Characteristics of Class A amplifiers:
• Unsymmetrical sinking and sourcing
• Linear
• Poor efficiency
vOUT(peak)2 vOUT(peak)2
PRL 2RL 2RL  vOUT(peak)
 2
Efficiency = PSupply = (VDD-VSS)IQ =  (VDD-VSS) =
 V DD˚-V SS 
 
 
(VDD -VSS) 2RL 
 
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-3

Specifying the Performance of a Common Source Amplifier

Output resistance:
1 1
rout = gds1+ gds2 = (λ1+λ2)ID
Current:
• Maximum sinking current is,
- K’1W1
IOUT= 2L1 (VDD -VSS - VT1)2 - IQ
• Maximum sourcing current is,
+ K’2W2
IOUT = 2L2 (VDD - VGG2 - |VT2|)2 ≤ IQ
Requirements:
• Want rout << RL
• |IOUT| > CL·SR
vOUT(peak)
• |IOUT| > RL
The maximum current will be determined by both the current required to provide the
necessary slew rate (CL) and the current required to provide a voltage across the load
resistor (RL).
ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-4

Small-Signal Performance of the Class A Amplifier

Although we have considered the small-signal performance of the Class A amplifier as the
current source load inverter, let us include the influence of the load.
The modified small-signal model:
C1
+ +
vin rds1 rds2 RL C2 vout
gm1vin
- -
Fig. 040-02
The small-signal voltage gain is:
vout -gm1
vin = gds1+gds2+GL
The small-signal frequency response includes:
A zero at
gm1
z = Cgd1
and a pole at
-(gds1+gds2+GL)
p = Cgd1+Cgd2+Cbd1+Cbd2+CL
ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-5

Example 5.5-1 - Design of a Simple Class-A Output Stage

Use the values of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V and VTP=-0.7V and design
the W/L ratios of M1 and M2 so that a voltage swing of ±2 volts and a slew rate of ≅1
volt/µs is achieved if RL = 20 kΩ and CL = 1000 pF. Assume that VDD = |VSS| = 3 volts
and VGG2 = 0 volts. Let the channel lengths be 2 µm and assume that Cgd1 = 100fF.
Solution
Let us first consider the effects of RL and CL.
±2V
iOUT(peak) = 20kΩ = ±100µA and CL·SR = 10-9·106 = 1000µA
Since the slew rate current >> the current for RL, we can safely assume that all of the
current supplied by the inverter is available to charge CL.
Using a value of ±1 mA,
W1 2(IOUT-+IQ) 4000 3µm
= =
L1 KN’(VDD+|VSS| -VTN)2 110·(5.3)2 2µm ≈

and
W2 2IOUT+ 2000 15µm
L2 = KP’(VDD-VGG2-|VTP|)2 = 50·(2.3)2 ≈ 2µm
The small-signal performance of this amplifier is, Av = -8.21 V/V (includes RL = 20kΩ)

ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-6

Broadband Harmonic Distortion

The linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal.
Assume the input is, Vin(ω) = Vp sin(ωt)
The output of an amplifier with distortion will be
Vout(ω) = a1Vp sin (ωt) + a2Vp sin (2ωt) +...+ anVp sin(nωt)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the
magnitude of the ith harmonic to the magnitude of the fundamental.
For example, second-harmonic distortion would be given as
a2
HD2 = a1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of all
of the second and higher harmonics to the magnitude of the first or fundamental harmonic.
Thus, THD can be expressed as
2 2 2
[a2 + a3 +...+ an]1/2
THD = a1
The distortion of the class A amplifier is good for small signals and becomes poor at
maximum output swings because of the nonlinearity of the voltage transfer curve for
large-signal swing.
ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-7

COMMON EMITTER OUTPUT STAGE

Common Emitter Class A Output Stage
vOUT
VCC Q2 saturates
RL1 VCC-VCE2(sat)
Q1 cutoff IQRL2
Q1 Q2
RL2
IQ
IR1 VBE1
iOUT 0 vIN

iC1 + RL2<RL1
RL vOUT
Q1
+ -
vIN VEE+VCE1(sat)
-
VEE Fig. 040-03

Large signal characteristic:

vIN


iOUT = IQ - iC1, vOUT = iOUT RL, and iC1 = Is1exp Vt 



vIN
  
vOUT = -RL Is1exp Vt  -IQ 
 
∴  
  

ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-8

Harmonic Distortion in the Common Emitter Output Stage

Assume the input signal is
vIN = VBE1+ vin
Substituting this in the expression on the last slide gives,
  vIN    VBE1  vin    vin 
vOUT = -RL Is1exp Vt  -IQ  = - RL Is1exp Vt exp Vt  -IQ  = - IQ RL exp Vt  - 1
            
             

Using the expansion of exp(x) ≈ 1 + x +x2/2 + x3/6 + ··· gives

  vin 1vin2 1vin3 
 
vOUT = - IQ RL Vt  + 2 Vt  + 6 Vt  +··· = a1vin + a2vin2 + a3vin3 + ···
      
where
I Q RL IQ RL IQ R L
a1 = - V t , a2 = - 2V 2 and a3 = - 6V 3
t t
Suppose vin(t) = Vpsinωt, then
vOUT(t) = a1Vpsinωt + a2Vp2 sin2ωt + a3Vp3 sin3ωt + ···
a2Vp2 a3Vp3
= a1Vpsinωt + 2 (1-cos2ωt) + 4 (3sinωt - sin3ωt) + ····
a2Vp2 1 a2V p V p a3Vp3 1 a3Vp2 1 Vp2
∴ HD2 = 2 a1Vp = 2a1 = 4 Vt and HD3 = 4 a1Vp = 4a1 = 24  Vt 
For Vp = 0.5Vt, HD2 = 12.5% and HD3 ≈ 1%

ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-9

Small Signal Performance of the Common Emitter Output Stage

Rin iin iout Rout
B C
+ +
vin rπ gmvin ro1 ro2 RL vout
- -
E E
Fig. 040-04
Let ro1||ro2 = ro, then
βο roRL vout -gm1ro·RL iout βo·ro
Rin = rπ1 = gm1 , Rout = ro + RL ≈ RL, vin = ro + RL ≈ -gm1RL and iin = ro + RL
If Vout(peak) = 0.6V, RL = 1kΩ and IQ = 1.86mA, then
IC 1.86 0.6 0.6
Av ≈ -gm1RL = -Vt RL = - 26 1000 = -70.6V/V ⇒ Vp = |Av| = 70.6 = 8.5mV (peak)
1 8.5 1 8.52
∴ HD2 = 4 26 = 0.082 and HD3 = 24  26  = 0.0045
Where does the distortion come from?
1.86+0.6
The ac gain at the negative peak output voltage is - 26 1000 = -94.6V/V
1.86-0.6
The ac gain at the positive peak output voltage is - 26 1000 = -48.5V/V
Note the emitter follower is much more linear because of the inherent negative feedback.
ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002
Lecture 040 – CE and CS Output Stages (1/11/04) Page 040-10

SUMMARY
Requirements of Output Stages
• The objectives are to provide output power in form of voltage and/or current.
• In addition, the output amplifier should be linear and be efficient.
• Low output resistance is required to provide power efficiently to a small load resistance.
• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.
• Types of output stages considered:
Common emitter and common source
• Maximum efficiency is 25%
• Second-harmonic distortion can be significant

ECE 6412 - Analog Integrated Circuits and Systems II © P.E. Allen - 2002