DMA Controller 8257

• The 8257, on behalf of the devices, requests the CPU for bus access using
local bus request input i.e. HOLD in minimum mode.
• In maximum mode of the microprocessor RQ/GT pin is used as bus
request input.
• On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in
maximum mode) from the CPU, the requesting devices gets the access of
the bus.
• It completes the required number of DMA cycles for the data transfer and
then hands over the control of the bus back to the CPU
Architecture of 8257
• The chip support four DMA channels, i.e. four peripheral devices can
independently request for DMA data transfer through these channels at a
time
• Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA
address register and terminal count register.
• There are two common registers for all the channels, namely, mode set
register and status register.
• Thus there are a total of ten registers.
• The CPU selects one of these ten registers using address lines A0-A3.
DMA Address Register
• Each DMA channel has one DMA address register
• The function of this register is to store the address of the starting memory
location, which will be accessed by the DMA channel
Terminal Count Register
• Each of the four DMA channels of 8257 has one terminal count register (TC).
• This 16-bit register is used for ascertaining that the data transfer through a
DMA channel ceases or stops after the required number of DMA cycles.
• The low order 14-bits of the terminal count register are initialised with the
binary equivalent of the number of required DMA cycles minus one.
• The bits 14 and 15 of this register indicate the type of the DMA operation
Mode Set Register
• The function of the mode set register is to enable the DMA channels
individually and also to set the various modes of operation
• The DMA channel should not be enabled till the DMA address register and
the terminal count register contain valid information
• The bits Do-D3 enable one of the four DMA channels of 8257.
• If Do is ‘1’, channel 0 is enabled.
• If bit D4 is set, rotating priority is enabled, otherwise, the normal.
• If the TC STOP bit is programmed to be zero, the channel is not disabled,
even after the count reaches zero and further request are allowed on the
same channel.
• The auto load bit, if set, enables channel 2 for the repeat block chaining
operations, without immediate software intervention between the two
successive blocks.
• The channel 2 registers are used as usual, while the channel 3 registers are
used to store the block re-initialisation parameters
• After the first block is transferred using DMA, the channel 2 registers are
reloaded with the corresponding channel 3 registers for the next block
transfer, if the update flag is set.
• The extended write bit, if set to ‘1’, extends the duration of MEMW and IOW
signals
Status Register
• The lower order 4-bits of this register contain the terminal count status
for the four individual channels.
• If the update flag is set, the contents of the channel 3 registers are
reloaded to the corresponding registers of channel 2.
Data Bus Buffer
• The 8-bit tristate, bidirectional buffer interfaces the internal bus of 8257
with the external system bus under the control of various control signals

Read/Write Logic
• In the slave mode, the read/write logic accepts the I/O Read or I/O Write
signals, decodes the Ao-A3 lines and either writes the contents of the
data bus to the addressed internal register or reads the contents of the
selected register
• In master mode, the read/write logic generates the IOR and IOW signals
to control the data flow to or from the selected peripheral.
Control Unit
• The control logic controls the sequences of operations and generates the
required control signals like AEN, ADSTB, MEMR,MEMW, TC and MARK
along with the address lines A4-A7, in master mode.

Priority Resolver
• The priority resolver resolves the priority of the four DMA channels
depending upon whether normal priority or rotating priority is
programmed.
PIN DIAGRAM OF 8257
 Signal Description of 8257
DRQ0-DRQ3
• These are the four individual channel DMA request inputs, used by the
peripheral devices for requesting the DMA services.
• The DRQo has the highest priority while DRQ3 has the lowest one, if the
fixed priority mode is selected.

DACK0 - DACK3
• These are the active-low DMA acknowledge output lines which inform
the requesting peripheral that the request has been honoured
Do-D7
• These are bidirectional, data lines used to interface the system bus with the
internal data bus of 8257.
• These lines carry command words to 8257 and status word from 8257, in slave
mode.
• When the 8257 is the bus master, it uses Do-D7 lines to send higher byte of the
generated address to the latch
IOR
• This is an active-low bidirectional tristate line that acts as an input in the slave
mode.
• In slave mode, this input signal is used by the CPU to read internal registers of
8257.
• In master mode, this signal is used to read data from a peripheral during a
memory write cycle.
IOW
• This is an active low bidirectional tristate line.
• It acts as input in slave mode to load the contents of the data bus to the
upper/lower byte of a 16-bit DMA address register or terminal count
register.
• In master mode, this signal is used to write data to a peripheral during a
memory read cycle
CLK
• This is a clock frequency input required to derive basic system timings for
the internal operation of 8257
RESET
• This active-high asynchronous input disables all the DMA channels by
clearing the mode register and tri-states all the control lines
A0-A3
• These are the four least significant address lines.
• In slave mode, they act as input which select one of the registers to be read
or written.
• In the master mode, they are the four least significant memory address
output lines generated by 8257.
A4-A7
• This is the higher nibble of the lower byte address generated by 8257 during
the master mode of DMA operation.
READY
• This is an active-high asynchronous input used to stretch memory read and
write cycles of 8257 by inserting wait states.
• This is used while interfacing slower peripherals
CS
• This is an active-low chip select line that enables the read/write
operations from/to 8257, in slave mode.
• In the master mode, it is automatically disabled to prevent the chip from
getting selected while performing the DMA operation
HRQ
• The hold request output requests the access of the system bus.
• In the non cascaded 8257 systems, this is connected with HOLD pin of
CPU
• In the cascade mode, this pin of a slave is connected with a DRQ input
line of the master 8257, while that of the master is connected with HOLD
input of the CPU
HLDA
• The CPU drives this input to the DMA controller high, while granting the
bus to the device.
• This pin is connected to the HLDA output of the CPU.
• This input, if high, indicates to the DMA controller that the bus has been
granted to the requesting peripheral by the CPU.
MEMR
• This active –low memory read output is used to read data from the
addressed memory locations during DMA read cycles.
MEMW
• This active-low output is used to write data to the addressed memory
location during DMA write operation.
ADSTB
• This output from 8257 strobes the higher byte of the memory address
generated by the DMA controller into the latches.
AEN
• This may be used to disable the system address and data bus
MARK
• The modulo 128 mark output indicates to the selected peripheral that the
current DMA cycle is the 128th cycle since the previous MARK output
• The mark will be activated after each 128 cycles or integral multiples of it
from the beginning of the data block (the first DMA cycle).
TC
• Terminal count output indicates to the currently selected peripherals that
the present DMA cycle is the last for the previously programmed data
block.

Vcc
• This is a +5v supply pin required for operation of the circuit.

GND
• This is a return line for the supply (ground pin of the IC).
THANK YOU