DAY 3 - 100 DAYS VERIFICATION CHALLENGE TOPIC: CACHE REPLACEMENT ALGORITHMS DAY3 VERIFICATION CHALLENGE HOMEWORK: Understand Cache replacement algorithms for different mapping techniques. There are 3 major algorithms — LRU, MRU, FIFO. Analyze how replacement happens in each of these algos for different mapping techniques. DAY3 VERIFICATION CHALLENGE: 1. What is the basic replacement criteria in all 3 algos? 2. Why does direct mapping not need any replacement algorithm? 3. Ihave a cache which can hold 8 blocks/frames from the RAM. Consider the cache is initially EMPTY. RAM has 128 blocks of | byte each in a byte addressable system. The processor requested blocks in following sequence: 127, 8, 0, 127, 3, 5, 7, 9, 6, 3, 8, 0, 5, 11, 19, 8. Calculate the no. of cache misses for Fully Associative Cache Mapping in LRU, MRU & FIFO.DAY 4 - 100 DAYS VERIFICATION CHALLENGE TOPIC: CACHE COHERENCE DAY4 VERIFICATION CHALLENGE HOMEWORK: Understand Cache coherency, cache coherency mechanisms & cache coherence protocols? DAY4 VERIFICATION CHALLENGE: 1. What is cache coherency problem? 2. Explain snooping mechanism? 3. What are cache coherency protocol? Explain below protocols:- = Write-invalidate = Write-updateDAY 5— 100 DAYS VERIFICATION CHALLENGE Topic: Processor Pipelining ‘Homework: Understand Processor pipelining in detail. There are 5 basic steps — Fetch, Decode, Execute, Memory Access, Write back. Day 5 Challenge: 1. Why do we need processor pipelining? What will happen if we don’t use any processor pipelining at all? 2. Draw 5 stage pipeline & explain operation of each stage. 3. Consider a pipeline having 5 phases with duration as below: Fetch — 60 ns, Decode — 50 ns, Execute — 90 ns, Memory Access — 100 ns and Write back — 150 ns. Given latch delay is 25 ns. Calculate: - ~ Pipeline cycle time (Tip: Pipeline Cycle Time = Sum of time taken by each stage + Latch delay) - Nompipeline execution time (Tip: Non-pipeline execution time = Sum of time taken by each stage)DAY 6 - 100 DAYS VERIFICATION CHALLENGE Topic: Pipelining Hazards Homework: Deep dive into pipelining hazards, ways to resolve hazards & some examples of instruction sequences leading to such hazards. Also, understand different types of each hazard. E.g., Data hazard mainly has 3 types - RAW, WAW, WAR. Now, go through various techniques to resolve each of the pipelining hazard. Day 6 Challenge: 1, What are different types pipelining hazards. Explain with examples? 2. What are ways to resolve different pipeline hazards? What are pros & cons of these resolution techniques? 3. Identify the pipelining hazards (also tell the sub-category e.g., Data hazard - WAW) in below sequence of instructions. Explain why these instructions are resulting in pipelining hazard. a. SUB RI, R4, R3 ADD R1, R2, R3 b. ADD RI, R2, R3 SUB R4, RI, R3 c. SUB R4, RI, R3 ADD R1, R2, R3DAY 7 - 100 DAYS VERIFICATION CHALLENGE Topic: Memories Homework: Different levels of memory (Register, Cache, Main memory, Secondary memory, etc.), virtual memories, memory addressing & numerical, addressing modes, RAID system in SSDs, “Wait” memory state Day 7 Challenge: 1. What are the different levels of memory? List the pros & cons of each level. 2. What is memory addressing technique? Explain the various addressing modes? 3. Address bus consists of 20 bits in a byte-addressable system. Find the size of memory. . Memory size is 8 GB ina 4-byte addressable system. Find the no. of address bits. . What is a RAID system (used in SSDs)? Explain with diagram. . Explain virtual memory with example? Why do we need them? . What is a wait state in memory? How can we deal with this state? - nawDAY 8 — 100 DAYS VERIFICATION CHALLENGE Topic: Different Computer Architectures Homework: Types of computer architectures, Von Neumann and Harvard architecture, RISC, CISC, RISC-V, SIMD Architecture for GPU. DAY 8 Challenge: . Explain 3 major types of computer architecture — System Design, ISA (Instruction Set Architecture) & Microarchitecture. . Explain Von Neumann and Harvard architecture in detail. List down pros & cons of Von Neumann and Harvard architecture, . Explain RISC & CISC Architecture in detail. List down pros & cons of RISC Vs CISC? . What is a RISC-V processor? Why do we use RISC-V? . What is SIMD architecture in GPU? What are the advantages of using SIMD over SISD? x aweDAY 9 — 100 DAYS VERIFICATION CHALLENGE Topic: Instructions & Buses Homework: Deep dive into instruction — various fields, rules of assembly language. Three buses — address, data & control. Day 9 Challenge: 1. 2. Can you tell at least 5 common rules of assembly language? Explain 3 major fields in an instruction: the operation field, the address field, and the mode field. . Explain types of micro-operations (Register transfer, Shift, Logic, Arithmetic) with example? . What is a horizontal microcode? Why do we use it? . Explain 3 major types of buses — address, data & control bus with an example. . Give one example of below instructions: - a. Arithmetic Instructions. b. Branch Instructions. ce. Data Transfer Instructions. d. Logic Instructions. e. Bit-oriented Instructions.DAY 10-100 DAYS VERIFICATION CHALLENGE Topic: Microprocessor, Microcontroller, Interrupts Homework: Deep dive into Microprocessors, Microcontrollers & Interrupts Day 10 Challenge: 1. Explain the common components of a microprocessor (IO unit, Control Unit, ALU, Register, Cache)? . Difference between microprocessor & microcontroller? . What distinguishes a microcontroller's timer from its counter? . What is program counter? . Explain Tri-state logic. . What are the different types of interrupts in a microprocessor system? 7. What's the difference between interrupt service routine and subroutine? wr AurDAY 11 - 100 DAYS VERIFICATION CHALLENGE Topic: Computer Architecture Miscellaneous Homework: DMA, MESI protocol, Synchronization, Paging DAY 11 CHALLENGE: ARwWNe . Explain DMA (Direct Memory Access) with diagrams. . Explain operation of MESI Protocol (Cache Coherency) . What is meant by Synchronization in computer architecture? . What is Paging? What is a Page Table? . Find the total number of frames. If a system, size of the main. memory is 230 bytes, the page size is 4 KB and the size of each page table entry is 32-bit. . Consider a system with page table entries of 8 bytes each. If the size of the page table is 256 bytes, what is the number of entries in the page table? . Consider a machine with 32-bit logical addresses, 4 KB page size and page table entries of 4 bytes each. Find the size of the page table in bytes. Assume the memory is byte addressable.DAY 12 — 100 DAYS VERIFICATION CHALLENGE Topic: Flip Flop & Latches Homework: Deep dive into Flip Flop & Latches DAY 12 CHALLENGE: . Explain functioning of JK & SR Flip Flop . Difference between Flip Flop & Latch . Why are latches faster than flip-flops? . Explain the use of: - Flip Flop - Latch . Why is the Gated SR Flip Flop called Asynchronous Latch? 6. Implement D-FF using NAND Gate 7. Design D-FF using 2:1 MUX. Bwnpe aDAY 13 —- 100 DAYS VERIFICATION CHALLENGE Topic: Logic Gates Homework: Understand about Logic Gates in depth DAY 13 CHALLENGE: I. 2: 3. Which are basic logic gates. Explain working with truth table. Why are NAND & NOR called the Universal Gates? What are advantages of universal gates. Design 4:1 MUX using universal gates: a. NAND b. NOR . What are applications of these gates: a. NAND b. NOR. . Design OR, AND, XOR, NOT using: a. NAND b. NOR . Design below logic using Logic Gates a. Inverter b. Full adder . What happens if more than one input is applied to a logic gate?DAY 14-100 DAYS VERIFICATION CHALLENGE Topic: Adders, Subtractors. Homework: Understand about Adders, Subtractors DAY 14 CHALLENGE: 1. Explain the working: a. 4-bit full adder b. 4-bit full subtractor 2. What is the use of parallel adder? 3. Explain the difference between Series & Parallel Adder 4. Design 3-bit Subtractor with overflow detection 5. Design following: a. Ripple Carry Adder b. Carry Look Ahead AdderDAY 15 — 100 DAYS VERIFICATION CHALLENGE Topic: Encoders, Decoders. Homework: Deep dive into encoders, decoders DAY 15 CHALLENGE: 1. Design & explain working of: a. BCD to Decimal encoder b. Octal to Binary encoder using OR gates. c. 3:8 Decoder d. 4: 2 Priority Encoder 2. Explain difference between: a. Encoder & Decoder b. Encoder & Priority Encoder 3. Explain applications of: a. Priority encoder b. Priority Decoder 4. What are the basic functions of: a. Digital Encoder b. Digital DecoderDAY 16-100 DAYS VERIFICATION CHALLENGE Topic: Counters, Timers Homework: Deep dive into counters, timers DAY 16 CHALLENGE: 1. Design & explain working of: a. 4-bit Ring counter b. 4-bit Johnson counter c. 3-bit Ripple counter d. Decade counter 2. List the difference between: a. Timers & Counters b. Synchronous & Asynchronous Counter 3. Explain working of 555 Timer ICDAY 17 - 100 DAYS VERIFICATION CHALLENGE Topic: Multiplexers, Demultiplexers Homework: Let’s learn about muxes & demuxes DAY 17 CHALLENGE: . Design 16:1 MUX using 2:1 MUX . Design D-FF using MUX . Design a 1:2 DEMUX that can be used as an inverter & also as a buffer. . Design NAND Gate using 1:2 DEMUX What is the difference between Decoder & DEMUX? . If DO input of a 2:1 MUX is connected to ground, what is the output? . If D1 input of 2:1 MUX is connected to 1, what is the output? . List the applications of: a, Multiplexer b. Demultiplexer OPIAAKWEREY’WHEDAY 18 — 100 DAYS VERIFICATION CHALLENGE Topic: FSM, Sequence Detectors Homework: In-depth knowledge on Finite State machines & sequence detectors DAY 18 CHALLENGE: a 1. What is Finite state machine? What are different types of FSMs? 2. What is the difference between Moore & Mealy machine? 3. What are applications & limitations of FSM? 4. 5. Design a Finite state machine for: How do you handle exceptions or error states in a Finite State Machine? i. serial two’s complement block ii. detect a sequence 10110 (overlapping) iii, detect a sequence 11001100 (non-overlapping) iv. detect more than one "1"s in last 3 samples. . Explain below concepts in FSM: i. Trigger ii. Transition iii, State Diagram iv. Super state v. Guard conditions vi. Deadlock vii. Determinism viii. _ epsilon transitionsDAY 19— 100 DAYS VERIFICATION CHALLENGE Topic: Sequential & combinational circuits Homework: Understand about Sequential & combinational circuits. DAY 19 CHALLENGE: ANNWEwWHE 8. 9. . List the difference between Sequential & Combinational Circuits. . List the applications of Sequential & Combinational Circuits. . Why does sequential circuit contain memory element? . What is an asynchronous sequential circuit? . What are the two types of asynchronous sequential circuits? . What are the types of hazards in asynchronous sequential circuits? . What is race condition in asynchronous sequential circuits? How to avoid this race conditions? What is the difference between race condition and deadlock? How do you prevent deadlocks? 10.What is a glitch? How to avoid & fix glitches?DAY 20 - 100 DAYS VERIFICATION CHALLENGE Topic: Boolean Algebra, Number System & Digital codes Homework: Let’s learn about Boolean algebra, number system & digital codes. DAY 20 CHALLENGE: 1 2 2. 4. Explain below codes: i. ii, ae 6, . How many types of number system are there? Describe each in detail. . What are the fundamental properties of Boolean algebra? State the disadvantage of a 8-4-2-1 code BCD code Gray code ‘What are the applications of: i. il, iii. vi. vii. viii. . What are different ways to represent a negative number? Weighted code Non-weighted code Excess-3 code, BCD code Gray code ASCII code Octal Number System Hexadecimal Number System 7. What is meant by isomorphic Boolean algebra?DAY 21 - 100 DAYS VERIFICATION CHALLENGE Topic: Optimization techniques Homework: Optimization techniques form the backbone of designing chips. Let’ learn about it. DAY 21 CHALLENGE: 1. State the De Morgan's Theorem? 2. What are the 4 methods to reduce a Boolean expression? 3, What is meant by K-Map or Kamaugh Map? What are the limitations of the Karnaugh Map? 4, What are the advantages and disadvantages of the K-Map Method? 5. What is the Quine-McCluskey method? 6. Which code is called a minimum change code and why? 7. What are degenerate forms in two-level logic implementation? 8. What are logic optimization techniques? 9. How do you optimize a logic circuit? 10.Explain below concepts: i. Duality Theorem ii, Minterm and Maxterm iii. Consensus TheoremDAY 22 — 100 DAYS VERIFICATION CHALLENGE Topic: Static Timing Analysis Homework: Let’s deep dive into STA concepts. Understand STA numerical online. Here is one link where you can find some solved STA numerical: ww.visiuniverse,com/sta-solved-problems- DAY 22 CHALLENGE: ‘What do you mean by clock skew and clack jitter? What are the different types of skews used in VLSI? What is slack in VLSI? What is negative slack & positive slack? Explain: i. Setup Time ii, Hold Time iii, Rise Time iv. Fall Time How can you avoid setup & hold time violations? ‘What are ideal characteristics of a clock during STA? ‘What is the difference between time borrowing & time stealing? ‘What is timing path? What are start & end points? Explain following concept: i. Launch Edge ii. Capture Edge fii, Reset Assertion ix. ResetDe assertion \. Critical path vi. False path vii, Malticycle path BeppeDAY 23 — 100 DAYS VERIFICATION CHALLENGE Topic: Memory elements Homework: Let’s learn about different memory elements. DAY 23 CHALLENGE: . Difference between RAM and ROM. . How is data written in ROM? . Explain different types of ROM Memory . Why does Dynamic ROM need to be refreshed multiple times per second? . What is the size of ROM for the n-bit full adder? . Explain different types of RAM Memory. . What is the difference between static RAM and dynamic RAM? . What is EPROM? What is its application? 9. Difference between EPROM and EEPROM. 10. What are the essential features of a memory element? 11.What are Shift registers? What are the types of Shift registers? 12.How many 32K * 1 RAM chips are needed to provide a memory capacity of 256 K-bytes? (Hint: No. of chips needed = Memory capacity/RAM chip’s capacity) SIAWPWNHeDAY 24 — 100 DAYS VERIFICATION CHALLENGE Topic: Digital Electronics Miscellaneous Homework: Focusing on some important interview questions on Digital Electronics. DAY 24 CHALLENGE: . What is a sequence generator circuit? Application of sequence generator? What is a transmission gate in the digital circuit? What is a pass transistor logic circuit? Advantages of using pass transistor logic. Why are most interrupts active low? . Define Pair, Quad, and Octet? Define Fan-in and Fan-out? . What is power dissipation? What is metastability? What are its effects? . What is an Arbiter? Explain it’s operation. eee COINDAY 25 — 100 DAYS VERIFICATION CHALLENGE Topic: MOSFET, BJT, CMOS Homework: Interview questions on MOSFET, BJT, CMOS DAY 25 CHALLENGE: . Why do the present VLSI circuits use MOSFETs instead of BJTs? . What are the various regions of operation of MOSFET? How can we use these regions? . What do you understand by the threshold voltage? . What does "the channel is pinched off" mean? . What are the key differences between the TTL chips and CMOS chips? . What is the most significant advantage of the CMOS chips over the TTL chips? 7. What do you understand by Channel-length Modulation? 8. What is the depletion region in VLSI? 9. What are the various factors that can affect the threshold voltage? 10. What is the reason behind the number of gate inputs to CMOS gates usually limited to four? ve AauAwWDAY 26-100 DAYS VERIFICATION CHALLENGE Topic: Getting started with Verilog Homework: Let’s get started with Verilog Basics DAY 26 CHALLENGE: wR eye a a What is the difference between VHDL & Verilog? ‘What are advantages of Verilog over VHDL? Explain below methodologies for Digital Design: i Top-down ii, Bottom-up ‘What is a module in Verilog? Write the basic syntax of declaring a module? Explain the difference between module & module instance in Verilog with an example Describe below abstraction levels with an example: i Behavioral ii, Data Flow iii, Gate Level iv. Switch Level Explain following blocks i Stimulus block ii. Design blockDAY 27-100 DAYS VERIFICATION CHALLENGE Topic: Data types in Verilog Homework: Deep dive into data types in Verilog DAY 27 CHALLENGE: . Explain the difference between ‘reg’ & ‘wire’ with an example? . Explain ternary operator (?) with an example. . Identify the base formats of nos. in following declarations: i 12345 (Hint: Since nothing is specified it will take default no. format. Tell me what’s that default format) ii 025 ii = “hd iv “bh |. What is the value of following declarations: (Hint: If something is ‘x’ you can calculate the range or possible values, if some bit is high impedance, calculate the value as per other bits & say this particular bit will be high impedance) i Vz ii, 32°h1x792 lil, = 16’04z iv. 16h2xz . Explain how negative nos. can be declared & stored in Verilog. . Explain the following keywords in Verilog with an example: i. Time ii Integer iii, Parameter iv. defparamDAY 28 - 100 DAYS VERIFICATION CHALLENGE Topic: System Tasks, Compiler directives, Logical operators, Verilog Basics Homework: Let’s focus on some basic Verilog topics DAY 28 CHALLENGE: 1. 2. OMIA Explain the difference between Sdisplay, Smonitor & Sstrobe with an example? Which system tasks are used to switch monitoring on & off? Explain with example. . Explain the following System tasks with an example: i. $stop ii, Sfinish . Explain following compiler directives with an example: i, “define ii “include . Explain the difference between = & == with an example. . What is a sensitivity list? . Explain deposit and force commands. . Explain freeze & drive with an example. . What does timescale 1 Ns/1 Ps mean? 0. Between variable and signal, which will be updated first & why?DAY 29 — 100 DAYS VERIFICATION CHALLENGE Topic: Basic Verilog codes Homework: Let’s start practicing some basic Verilog codes. You are required to execute the code, make it compile clean & ensure it’s giving the right output. You can use free online platforms like hdlbits. DAY 29 CHALLENGE: . Explain with example different methods to code a clock in Verilog. 2. Write a verilog code for: i, Synchronous reset ii, Asynchronous reset 3. Write a verilog code to swap contents of two registers: i, with a temporary register ii without a temporary register 4. Design following using Verilog: i, XNOR Gate ii D-FF iii, = 2:1 MUX iv. 2-bit Full Adder 5. Design a Verilog code to execute following truth table: Inputs Outputs a b x y 0 0 1 0 0 1 1 1 & 0 0 0 & 1 0 1