数字集成电路原理

Combinational Logic Circuits

刘佳欣
[email protected]
Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

2
Logic Circuits

3
Combinational Logic Circuits

Complementary CMOS

（1） Static comb. logic Ratioed Logic

Pass-Transistor Logic

（2） Dynamic comb. logic

4
Static VS. Dynamic Logic
pStatic Logic
Ø At every point in time (except during
the switching transients), each gate
output is connected to either VDD or
VSS via a low-resistive path.
Ø The outputs of the gates assume
the value of the Boolean function.

pDynamic Logic
Ø Relies on temporary storage of
signal values on the capacitance of
high impedance circuit nodes.

5
Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

6
Static Complementary CMOS

VDD
PUN:
In1 Ø Make a connection from VDD to F
In2 PUN when F(In1,In2, ... Inn) = 1
…

Ø PMOS only
InN
F(In1,In2,…InN)
In1
In2 PDN PDN:
…

Ø Make a connection from VSS to F

InN
when F(In1,In2, ... Inn) = 0
Ø NMOS only

PUN and PDN are dual (Complementary) logic networks

7
Construct the PUN and PDN Networks
p Threshold drop issues

VDD VDD
PUN
S D
Good! VDD Bad!

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S Good! D Bad!

8
Construct the PDN Networks
p Transistors can be thought as a switch
p NMOS switch closes when its gate is high

A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

9
Construct the PUN Networks
p PMOS switch closes when its gate is low

10
Complementary CMOS Logic Style

11
Example Gate: NAND

12
Complex CMOS Gate

B
A
C

D
F = D + A • (B + C)
A
D
B C

13
Constructing a Complex Gate

VD D VD D

C
S N F1 S N 4 A
F
S N 2 B
A A
D D S N 3

B C B C D

( a ) l-d
wn
o n A e
D
s u b - ts
B C

( c )

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Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

15
Static Behavior
VTC of inverter
p The VTC of a complementary CMOS
gate is data-dependent

VTC of NAND2

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Dynamic Behavior

q Delay is dependent on the inputs

q Low to high transition

§ both inputs go low
– delay is 0.69 Rp/2 CL
§ one input goes low
– delay is 0.69 Rp CL
q High to low transition
§ both inputs go high
– delay is 0.69 2Rn CL

17
Delay Dependence on Input Patterns

NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF

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Fan-In Considerations

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Fan-In Considerations

1250

Gates with a fan- quadratic

1000
in greater than 4
should be
750 avoided.
tpHL tp
500

250 tpLH
linear
0
2 4 6 8 10 12 14 16

Propagation delay of CMOS NAND gate as a function of fan-in

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Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

21
Fast Complex Gates: Design Technique 1

q Transistor sizing
§ as long as fan-out capacitance dominates
q Progressive sizing

InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
output is the smallest)
In3 M3 C3
In2 M2 C2
In1 M1 C1

22
Fast Complex Gates: Design Technique 1

q Transistor sizing
§ as long as fan-out capacitance dominates
q Progressive sizing

InN MN CL M1 > M2 > M3 > … > MN

(the fet closest to the
output is the smallest)
In3 M3 C3
In2 M2 C2
In1 M1 C1

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Fast Complex Gates: Design Technique 2

q Input re-ordering
critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

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Fast Complex Gates: Design Technique 3

q Alternative logic structures

F = ABCDEFGH

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Fast Complex Gates: Design Technique 4

q Isolating fan-in from fan-out using buffer

insertion

CL CL

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Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

27
Review: Optimize the Dealy of Inverter Chain

pFor a given stage number N

C L 1/ N
f opt ( )
C g1
pIf N is not fixed

���� ≈ 4, �ℎ�� ��������� �

q Can we extend this design rule to a comb. gate?

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Delay of Complex Gate
 CL 
pInverter delay t p,inv  t p 0 1    t p 0 1  f /  
  Cin 

pComplex gate delay t p  t p 0  p  gf  Assume γ=1

Ø h=gf: effort
Ø p: intrinsic (parasitic) delay
• Ratio of the intrinsic delays of the complex gate and the inverter
• p=1 for inverter
• Set by circuit topology and layout
Ø f: electrical effort = Cout/Cin
• Ratio of output to input capacitance
• We call it effective fanout in inverter
Ø g: logical effort
• presents the ratio of its input capacitance to the inverter
capacitance when sized to deliver the same current
• g=1 for inverter
• Depends only on circuit topology only
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Intrinsic Delay

• Ignore the internal

capacitance

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Logical Effort
pPresents the ratio of its input capacitance to the inverter
capacitance when sized to deliver the same current
pFor a given load, complex gates have to work harder than
an inverter to produce a similar response.
pCan estimate by counting transistor widths

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Logical Effort

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Delay: NAND2 VS. INV

t p  t p 0  p  gf  • d: normalized delay
d   p  gf    p  h • h: gate effort
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Example: FO4 Inverter

pEstimate the delay of a fanout-of-4 (FO4) inverter

• Intrinsic Delay: p=1

• Logical Effort: g=1
• Electrical Effort: f=Cout/Cin=4
• Gate Delay: d=5

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Multistage Logic Networks

N N

Optimal f for inverter chain D    pi  g i  f i     pi  hi 

N i 1 i 1
tp   t 1  f 
h1  h2  ...  hN
p0 i
1

f1  f 2  ...  f N  N
F

pEvery stage should have the same effort！

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Multistage Logic Networks

N N N
1

Path effort: H  h   f  g
i 1
i
i 1
i
i 1
i  F G h1  h2  ...  hN  H N

N
Path electrical effort: F  f
i 1
i  C out _ path / C in _ path
N
Path logic effort: G  g
i 1
i

Path intrinsic delay: P

1
Path effort delay: D H  N  H N

Path delay: D   p i   hi  P  D H
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Multistage Logic Networks

N N N
f  C out _ gate / C in _ gate
H   hi   f i   g i  F  G C in _ gate  C out _ gate / f
i 1 i 1 i 1

F  Cout / Cin  5 f1  h / g 1  1.93

c  5/ f 4  2.59
G  25 / 9 f 2  h / g 2  1.16
b  c / f 3  2.23
H  125 / 9 f 3  h / g 3  1.16
a  b / f 2  1.93
h 4
H  1.93 f 4  h / g 4  1.93

37
Multistage Logic Networks

N N N
H   hi   f i   g i  F  G
i 1 i 1 i 1

F  Cout / Cin  5 c  1  5/h  2.59

G  25 / 9 h  g  f  g  C out _ gate / C in _ gate
5
H  125 / 9 C in _ gate  g  C out _ gate / h b  c / h  2.23
3
h 4
H  1.93 5
a   b / h  1.93
3
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Multistage Logic with Branches

H≠FG

p Introduce the branching effort:

Con  path  Coff  path

Gate branching effort : b 
Con  path
Path branching effort : B   bi
Path effort：H  FGB

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Example: Sizing an Inverter Network
pDetermine the min delay form in to out, CL=64Cin
Ø Path electrical effort:
F=CL/Cin=64

Ø Path logical effort:

G=1

Ø Path branching effort:

B=4*4=16

Ø Path effort:
H=FGB=1024

Ø Optimal gate effort:

h =H1/N ≈ 10.08

Ø Path effort delay:

DH=N*h≈ 30.24
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Example: Sizing an Inverter Network
pDetermine the min delay form in to out, CL=64Cin

Ø Gate intrinsic delay:

p=1

Ø Path intrinsic delay:

P=3

Path delay: D  P+N  h  3+3 10.08  33.24

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Review of Definitions

Term Gate/Stage Path

Logical effort g �= ��
Electrical effort f=Cout/Cin F=Cout(patch)/Cin(path)

Branching effort b=(Con_path+Coff_patch)/Con_path �= ��

Effort h=gf H=GFB

Effort delay h �� = ℎ�
Number of stages 1 N

Intrinsic delay p �= ��
Delay d=p+h D=P+DH

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Review of Definitions

f <-> h

F <-> H

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Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

44
Ratioed Logic: Concept

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

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Resistive Load

46
Pseudo-NMOS Load

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Pseudo-NMOS Inverter VTC

p Voltage-transfer curves of the pseudo-NMOS inverter as a function of the

PMOS size (with an NMOS size of 0.5um/0.25um)

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Improved Load

VDD VDD
Ø Differential logic
Ø Positive feedback
M1 M2

Out Out

A
A PDN1 PDN2
B
B Ø Rail-to-rail
Ø No static power
VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

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 Improved Load
VDD VDD

M1 M2 Ø Differential logic
Ø Positive feedback
Out Out

A
A PDN1 PDN2
B
B
Ø Rail-to-rail
VSS VSS
Ø No static power
Differential Cascode Voltage Switch Logic (DCVSL)

Ø Ratioed problem: Out (1->0)

Ø PDNs need to be stronger than load
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DCVSL Example: XOR/NXOR

Out

Out

B B B B

A A
CMOS XOR Logic

XOR-NXOR gate

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DCVSL Response: AND/NAND

2.5

AB

V olta ge [V]
1.5
AB
A,B
0.5 A,B

-0.5 0 0.2 0.4 0.6 0.8 1.0

Time [ns]

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Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

53
Pass-Transistor Logic

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NMOS-Only Pass-Transistor Logic
B

A
pExample: AND gate B
F A = B

x does not pull up to 2.5V, but 2.5V - VTN

Threshold voltage loss causes static power consumption
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Solution 1: Level Restoring Transistor

p Full Swing
p No static power in INV

p Restorer adds capacitance, takes away pull down current at X

p Ratioed problem: Mn needs to be stronger than Mr to pull down X
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Restorer Sizing

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Solution 2: Multiple Threshold Transistor

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Solution 3: Transmission Gate

pTransmission gate work as switch

pNeed 2 transistors, and more control logic
pRail to rail swing

59
Solution 3: Transmission Gate Based Logic

CMOS Logic: 8T CMOS Logic: 12T

60
Outline
pLogic Circuits Classification
pComplementary CMOS
pConcept
p Static & Dynamic Properties
p Design Techniques
p Effort
pRatioed Logic
pPass-Transistor Logic
pDynamic CMOS Design

61
Dynamic Gate:

Clk Mp Clk Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
Clk Me
Clk Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)

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Properties of Dynamic Gate

p Logic function is implemented by the PDN (or PUN, but barely use)
only

p Fewer transistors: N + 2 transistors for fan-in-N

p Full swing outputs (VOL = GND and VOH = VDD)
p Non-ratioed - sizing of the devices does not affect the logic levels
p Faster switching speeds
• reduced load capacitance due to lower input capacitance (Cin)
• reduced load capacitance due to smaller output loading (Cout)
• no Isc, so all the current provided by PDN goes into discharging CL

p Need careful design especially in advanced process nodes

• Due to leakage
p Possible higher power consumption although no Isc
• Frequent pull-up operations

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Thank you!