▪ Logic gates are electronic circuits that can be used to implement

the most elementary logic expressions, also known as Boolean

expressions.
▪ The logic gate is the most basic building block of combinational
logic.
▪ Logic families and their functional description help application
engineers in choosing the right device for their application
▪ Different logic families used to hardware-implement different logic
functions in the form of Digital Integrated Circuit technology.
1. How would you hardware-implement a four-input OR gate using
two-input OR gates only? Show two ways of doing it.
2. Draw the output waveform for the OR gate and the given pulsed
input waveforms fig 1a.

Figure 1
▪Digital integrated circuits are produced using several
different circuit configurations and production
technologies.
▪Logic families to be discussed include;
▪ Transistor transistor logic (TTL),
▪ Metal oxide semiconductor (MOS) logic,
▪Emitter coupled logic (ECL)
▪ There are a variety of circuit configurations or more
appropriately various approaches used to produce different
types of digital integrated circuit.
▪ The idea is that different logic functions, when fabricated in the
form of an IC with the same approach, or in other words
belonging to the same logic family, will have identical
electrical characteristics.
▪ These characteristics include supply voltage range, speed of
response, power dissipation, input and output logic levels,
current sourcing and sinking capability, fan-out, noise margin,
etc.
▪ In other words, the set of digital ICs belonging to the same
logic family are electrically compatible with each other.
▪ A digital system in general comprises digital ICs performing different
logic functions, and choosing these ICs from the same logic family
guarantees that different ICs are compatible with respect to each other
and that the system as a whole performs the intended logic function.
▪ In the case where the output of an IC belonging to a certain family
feeds the inputs of another IC belonging to a different family, we must
use established interface techniques to ensure compatibility.
▪ Understanding the features and capabilities of different logic families is
very important for a logic designer who is out to make an optimum
choice for his/her new digital design from the available logic family
alternatives.
▪ A not so well thought out choice can easily underkill or overkill the
design with either inadequate or excessive capabilities.
EXAMPLES

Figure 2
▪ Falls under bipolar family and has a number of subfamilies including
standard TTL, low-power TTL, high power TTL, Schottky TTL, fast TTL, etc…
▪ The ICs belonging to TTL family are designated as 74 or 54(for standard
TTL), 74LS or 54LS (for low-power Schottky TTL), 74S or 54S (for Schottky
TTL), etc…
▪ An alphabetic code preceding this indicates the name of the manufacturer
(DM for National Semiconductors, SN for Texas Instruments and so on).
▪ A two-, three- or four-digit numerical code tells the logic function
performed by the IC. It may be mentioned that 74-series devices and 54-
series devices are identical except for their operational temperature
range.
▪ The 54-series devices are MIL-qualified (operational temperature range:
−55 °C to +125 °C) versions of the corresponding 74-series ICs
(operational temperature range: 0 °C to 70 °C). For example, 7400 and
5400 are both quad two-input NAND gates.
floppy disk controller board
▪ The BJT is an active switching element used in all TTL circuits. Symbol for BJT
has 3 terminals; base, emitter and collector. A BJT has two junctions, the base-
emitter junction and the base-collector junction.
▪ The basic switching operation is as follows;
▪ When the base is approximately 0.7V more positive than the emitter and
when sufficient current is provided into the base the transistor turns on and
goes into saturation. In saturation the transistor ideally acts like a closed
switch between the collector and the emitter.
▪ When the base is less than 0.7V more positive than the emitter, the transistor
turns off and becomes an open switch between the collector and the emitter.
▪ A HIGH on the base turns the
transistor on and makes it a
closed switch.
▪ A LOW on the base turns the
transistor off and make it an
open switch.

Figure 3
▪ In fig 5, Q1 is the coupling transistor, D1 is A Standard Inverter Circuit
the input clamp diode, transistor Q2 is called
a phase splitter and the combination of Q3
and Q4 forms the output circuit often
referred to as a totem-pole arrangement.
▪ When the input is HIGH, the base-emitter
junction of Q1 is reverse biased, and the
base-collector junction is forward biased.
This condition permits the current through R1
and the base-collector junction Q1 into the
base of Q2, thus driving saturation.
▪ As a result, Q3 is turned on by Q2, and its
collector voltage which is the output is near
ground potential.
▪ We therefore have a LOW output for HIGH
input. At the same time, the collector of Q2 is
at a sufficiently low voltage level to keep Q4
off.

Figure 4
Figure 5
▪ When the input is LOW, the base-emitter junction of Q1 is forward biased, and
the base-collector junction is reverse biased.
▪ There is current through R1 and the base-emitter junction of Q1 to the LOW
input. A LOW provides a path to ground for the current.
▪ There is no current into the base of Q2, so it is off. The collector of Q2 is HIGH
thus turning Q4 on.
▪ A saturated Q4 provides a low resistance path from Vcc to the output we
therefore have a HIGH on the output for a LOW on the input.
▪ At the same time, the emitter Q2 is at ground potential, keeping Q3 off.

▪ Diode D1 in the TTL circuit prevents negative spikes of voltage on the input
from damaging Q1. Diode D2 ensures that Q4 will turn off when Q2 is on
(HIGH input).
▪ In this condition, the collector voltage, Vc of Q2 = (VBE, of Q3) +(VCE of Q2).
▪ Diode D2 provides additional VBE equivalent drop in series with base-emitter
junction of Q4 to ensure it is turned off when Q2 is on.
▪ A 2-input TTL NAND gate shown
below is basically the same as the
inverter circuit expect for the
additional input emitter of Q1.
▪ In TTL technology multiple-emitter
transistors are used for input
devices. The multiple-emitter
transistors can be to the diode
arrangement shown in Fig. 7.
▪ Look at the operation of circuit in
Fig. 6 visualized in Fig. 7 for
easier understanding. Figure 6
 Diode equivalent of a TTL multiple transistor

Figure 7

• A low on either input A and input B forward-biases the respective diode and
reverse-biases D3 (Q1 base-collector junction).

• This action keeps Q2 off and results in a HIGH output in the same way as
described for the TTL inverter.
▪ A HIGH on both inputs reverse-biases both input diodes
and forward biases D3 (Q1 base-collector junction).
▪ This action turns Q2 on and results in a LOW output in the
same way as described for the TTL inverter.
▪ You should recognize this operation as that of the NAND
function: The output is LOW only if all inputs are HIGH.
▪ Fig. 8 shows the internal schematic of a NOR gate in the
standard TTL family. The schematic shown is that of one of the
four NOR gates in a quad two-input NOR gate (type 7402/5402).
▪ On the input side there are two separate transistors instead of
the multi-emitter transistor of the NAND gate.
▪ The inputs are fed to the emitters of the two transistors, the
collectors of which again feed the bases of the two transistors
with their collector and emitter terminals tied together.
▪ The resistance values used are the same as those used in the
case of the NAND gate. The output stage is also the same totem-
pole output stage.
• The only input condition for
which transistors Q3 and Q4
remain in cut-off, , is when both
the inputs are in the logic LOW
state.
• This will drive Q6 to cut-off and
Q5 to conduction.
• The output in such a case is
logic HIGH.
• For all other input conditions,
either Q3 or Q4 will conduct,
driving Q6 to saturation and Q5
to cut-off, producing a logic
LOW at the output. Figure 8 : NOR gate in standard TTL
• Fig 9 shows the internal
schematic of an AND gate in
the standard TTL family.

• The schematic shown is that

of one of the four AND gates
in a quad two-input AND
gate (type 7408/5408).

• In order to explain how this

schematic arrangement
behaves as an AND gate, we
will begin by investigating
the input condition that
would lead to a HIGH output. Figure 9
▪ A HIGH output implies Q6 to be in cut-off and Q5 to be in conduction
▪ This can happen only when Q4 is in cut-off. Transistor Q4 can be in the cut-
off state only when both Q2 and Q3 are in conduction.
▪ This is possible only when both inputs are in the logic HIGH state.
▪ Let us now see what happens when either of the two inputs is driven to the
LOW state.
▪ This drives Q2 and Q3 to the cut-off state, which forces Q4 and
subsequently Q6 to saturation and Q5 to cut-off.
1. Explain the operation of the OR Gate and the Ex-OR
Gate in the standard TTL and come up with the circuit
diagrams.