VHDL- Historical Perspective

• DoD of USA seen requirement of developing language to describe and

model high speed Circuits
• So VHDL (VHSIC Hardware Description Language) evolved and
standardized by IEEE. VHSIC stands for very high speed integrated circuit
• VHDL went through number of revisions: VHDL-87, VHDL-93, VHDL-2003,
VHDL-2008, VHDL-2019
• Other hardware description language: Verilog

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 VHDL – High Level View
• VHDL provides extensive range of modeling capabilities. However
subset of language is usually sufficient to design most applications
• The design units can be entity declaration, architecture body,
configuration declaration, package declaration or package body

LIBRARIES:
• These are repository in the file system of host environment that contain
compiled design units
• Libraries STD & WORK are predefined and default in VHDL (no need
to declare) while others need to be declared with ‘library’ clause.
• Other useful library is IEEE
Library IEEE;
Use IEEE.std_logic_1164.all - - use all items of package called
’std_lgoic_1164’
Use IEEE.numeric_std.all - - use complete ‘numeric_std’ package

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 Libraries and Packages

Package:
• It has two parts : (1) package declaration (2) package body (optional)
• Often contain declaration that are common across many design units
• Frequently used hardware units and subprograms
• Predefined Package named STANDARD is available in VHDL that contain
many commonly used predefined types like BIT, BIT_VECTOR,
INTEGER, CHARACTER, TIME etc.
• The most widely used package is STD_LOGIC_1164 from library IEEE

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 Entity and Architecture
ENTITY
• Any definable hardware block is entity. Entity is
only a black box with interface ports
• Ports of entity can be of in, out, inout or buffer
type

Architecture:
• Describes working of an entity
• Inherits all ports and generics of an entity
• Entity may have multiple architectures (alternate
designs)
• Description in architecture can be structural,
behavioral, dataflow or mix style

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 Objects and their usage
• VHDL has four class of objects:
(1) Signal : Used to represent wire or storage in digital hardware.
Unlike variables, signals acquires value after some delay (at least
delta delay). Objects of signal class can hold set of future values that
are to appear on signal (e.g. by specifying waveform)
(2)Variables: They are similar to conventional programming
language. They acquire value immediately .
(3) Constant: Objects of constant class can hold single value that
can not be changed during the simulation
(4) File: Objects belonging to file class contain sequence of values.
Values can be read or written to file using read and write procedures

• Types of values that an object can acquire are called data types.

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 Objects and their usage

• Declaration of objects includes class as well as data type of

values that they can acquire. Initial value can be assigned at
the time of declaration using ‘:=‘ operator.

Signal sig1 : bit := ‘0’;

Variable var1 : integer range 0 to 7;
Constant rise_time : time := 2 ns;

Note: all the keywords of language will be shown in blue color

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 Data Types
• Enumeration: defines a type that has a set of values
consisting of either characters or names.
– Predefined
(1) In STANDARD package of STD library:
• bit, boolean, character, severity_level, file_open_status,
file_open_kind etc.
• Bit => (‘0’,’1’)
• Boolean => (false, true)
• character => (. . ASCII characters. . )
(2) In package std_logic_1164 of IEEE library
• std_ulogic => (‘U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’)
• Subtype STD_LOGIC is resolved STD_ULOGIC

Note: User can define a new data type / array type using type statement

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 Data Types in VHDL
• Integer:
– Predefined type is integer whose range is decided by declaration
e.g. variable v1 : integer range 0 to 15; type index is range 0 to 9;

• Floating Point:
– Predefined type is real whose range is decided by declaration
variable v2 : real range -0.5 to 1.5;
type TTL_VOL is range 0.2 to 5.0;

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 Data Types
• Array type: includes constrained array and unconstrained array. Array
is an indexed collection of objects of same type and size
– Unconstrained array types:
• Predefined in STANDARD package: string, bit_vector,
• Predefined In IEEE.std_logic_1164 package: std_logic_vector,
std_ulogic_vector
e.g.
• Signal add_bus : bit_vector (15 downto 0) ;
• Signal data_bus : std_logic_vector (7 downto 0) ;

– Type word is array (32 downto 0) of bit; -- user defined

signal data1 : word;

VHDL will not allow an unconstrained array of another unconstrained array

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 OPERATORS
• Logical : and, or, nand, nor, xor, xnor, not
– Defined for BIT and BOOLEAN and their one dimensional array
– A nand B nand C => invalid, (A nand B) nand C => valid

• Relational : = /= < <= > >=

– Both operands must be of same type.
– Result is Boolean

• Shift: sll, srl, rol, ror

“11001011” sll 2
= “00101100” - - zero filled left shift
“11001011” srl 3
= “00011001” - - zero filled right shift
“11001011” rol 2
= “00101111”
“11001011” ror 3
= “01111001”
• Adding operators: + (addition), - (subtraction), & (concatenation)
– The + and – must be of same numeric type (default numeric type is integer)

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 OPERATORS
• The values can be combined using & operator. For example,
Signal s1 : bit_vector(3 downto 0);
s1<= “10” & “01”;

• Multiplying: *, /, mod, rem

– * (multiplicaion) and / (division) operators are defined for operands being
integer, signed or unsigned type
– Rem and mod operates only on integer type
– Result of mod is the sign of second operand
– Result of rem operation has sign of first operand
e.g. 7 mod 4 (ans = 1)
7 mod (-4) (ans = -1)
(-7) rem 4 (ans = -3)
(7) rem (-4) (ans = 3)

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 Assigning Values

• Signal S1 : bit_vector (3 downto 0); - - declaration

S1<= “0010”; . . . . . 0010
S1<= (‘1’,’1’,’0’,’0’); . . . . 1100

• Signal bus : bit_vector (0 to 7) := “00110011” - - initializing signal

bus <=X “33” (hex) or bus<= O“063” (octal) - - assigning value

• If v1 is integer and v2 is real variable

v1:= 6E1 or v1:=60 ; v2 := 1.26 or v2:=12.6E-1

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 Dataflow Modeling
• Three types of signal assignment statements: (1)concurrent (2)conditional

Entity mux4 is
port ( inp : in bit_vector ( 0 to 3);
s1,s0 : in bit; z : out bit);
End mux4;
Architecture concurrent of mux4 is
signal w0,w1,w2,w3 : bit;
begin

w1<= inp(1) and s0 and (not s1);

w2<= inp(2) and (not s0) and s1;
w3<= inp(3) and s0 and s1;
w0<= inp(0) and (not s0) and (not s1);
z <= w0 or w1 or w2 or w3;
End concurrent;
-----------------------------------------------

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 Dataflow Modeling
Architecture conditional of mux4 is -- alternate architecture
begin
z <= inp(0) when s0=‘0’ and s1=‘0’ else - - conditional
inp(1) when s0=‘0’ and s1=‘1’ else
inp(2) when s0=‘1’ and s1=‘0’ else
inp(3) when s0=‘1’ and s1=‘1’;
unaffected when others;
End conditional;

Note for Conditional Statement:

• Expressions in RHS are evaluated in order they appear. Careful
ordering is required to reflect the actual hardware you model
• You may assign “unaffected” value to target LHS signal in conditional
assignment. In this case LHS signal retains previous value.

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 BEHVIOURAL Description

Process:
• It is sequentially executed block of hardware description
• Architecture can have multiple processes and they are concurrent among
themselves (i.e. simultaneous execution of multiple processes).
• Process is only sensitive to signals placed in the sensitivity list.
• If sensitivity list is not present, there must be wait statement in process.

• The syntax of process statements is below:

[process label:] process [(sensitivity-list)] [is]
declarations ( variables, constants . .)
Begin
Variable assignment , signal assignment statements
If, case, while & for loop, exit, next statements, Wait statements
End process [process-label];

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 BEHVIOURAL Description
• Process is triggered when an event occurs to any signal in sensitivity
list and then sequential statements are executed in order. It suspends
after executing last sequential statements and waits for event to occur
in sensitivity list.
• Process is never exited; it is either running (executing) or suspended
• If process uses wait statements, its sensitivity list must be empty.

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 BEHVIOURAL Description

• IF statement : syntax
If boolean-expression then
sequential statements
[Elsif boolean-expression then
sequential statements
[Else - - else clause is optional
sequential statements
End if ;

• CASE statement:
Case expression is - - expression must have only discrete values
When choices => sequential statements
When choices => sequential statements
[when others =>sequential statements]
End case;

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 BEHVIOURAL Description
In case statement, choices can be combined and bind to same action,
for example
Case sig1 is
When ‘W’ | ‘X’ | ‘Z’ |’U’ => sequential statements
When others => sequential statements;
End case;

• Looping Construct:
The are various form of loop statements

1) While loop:
[loop-label]: While (boolean-expression) loop
Sequential statements
End loop [loop-label];

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 BEHVIOURAL Description
(2) For loop:
[loop-label ]: For identifier in discrete-range loop
Sequential statements
End loop [loop-label];

• In for loop, identifier is auto-declared. Identifier is destroyed when for

loop is exited.
• Each type of loop construct may contain exit and next statement.
The next statement allows to skip subsequent statements and
reach the end of loop to start next iteration.
The exit statement immediately terminated the loop.

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 STRUCTURAL DESCRIPTION
• Structural description defines hardware as collection of components
• Components are precompiled design units (that exist in WORK
library) that describes its working.
• At the top of hierarchy is Top level design entity. The top level entity
may contain many components

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 STRUCTURAL DESCRIPTION

• Let us say we have top level entity (having inputs A & B and
outputs W & Z) that contains two sub units called comp1 and
comp2. Then, these sub-units are instantiated and connections
are defined using “port map” statements

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 STRUCTURAL DESCRIPTION
Component instantiations:
The ports of each instance must be associated to signals/ports of top
level entity. The port map associates ports of component called formals
with the signals/ports of top entity called actuals.
– Named association :- both formals and actuals are specified, order is
not important.
– Positional association :- only actuals are specified with proper order
syntax : Instance name: component name port map
(formal1=>actual1,formal2=>actual2, . . . )

– i1: comp1 port map (p12=>B, p11=>s3, p14=>s1, p13=>s2, p15=> Z)

i2: comp2 port map (p21=>A, p22=>s2, p23=>s1, p24=>s3,
p25=>W, p26=> open)
OR
i1 : comp1 port map (s3, B, s2, s1, Z);
i2 : comp2 port map (a, s2, s1, s3, w, open);

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 Example – Structural Description
• Example 1: Full Adder:
– 1-bit basic adder can be compiled and then stored in work library

Entity full_add is -- 1-bit full adder

Port ( a,b, cin : in std_logic;
sum, cout : out std_logic);
End entity full_add;

Architecture struct1 of full_add is

Signals s1,s2,s3 : std_logic;
begin
s1 <= a xor b; s2 <= s1 and cin;
s3 <= a and b;
sum <= s1 xor cin ;
cout <= s2 and s3;
End struct1;

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 Example – Structural Description

• Example 2: Structural Design of 4-bit Paralle adder:

– 1-bit full adder is already designed with can be used as component
– 4-bit full adder is realized by instantiating four 1-bit full adder with
proper interconnection

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 Example – Structural Description
Entity add4 is -- 4-bit parallel adder
Port ( A, B : in std_logic_vector (3 downto 0);
Cin : in std_logic ;
S : out std_logic_vector (3 downto 0); Co : out std_logic );
End entity add4;

Architecture struct1 of add4 is

Signals c1,c2,c3 : std_logic;
Component full_add is
Port(a, b, cin: in std_logic; sum, cout: out std_logic)
End component ;
begin
i1 : full_add port map (a=>A(0), b=>B(0), cin=>cin, sum=> S(0) cout=>c1);
i2 : full_add port map (a=>A(1), b=>B(1), cin=>c1, sum=> S(1) cout=>c2);
i3 : full_add port map (a=>A(2), b=>B(2), cin=>c2, sum=> S(2) cout=>c3);
i4 : full_add port map (a=>A(3), b=>B(3), cin=>c3, sum=> S(3) cout=>Co);
End struct1 ;

• Notes: (i) This is direct instantiations where name of components and port
name must match with entity that describe this

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 Test bench
• Testbench is verification program used to verify the correctness of
designed hardware
• Following is a test bench code for testing is 4-bit parallel adder “add4”
described earlier.

Entity test_bench is
End test_bench;

Architecture behave of test_bench is

component add4
port (A,B : in std_logic_vector (3 downto 0);
cin : in std_logic ;
S : out std_logic_vector (3 downto 0);
Co : out std_logic );
end component;

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 signal inp_A : std_logic_vector(3 downto 0) := "0000";
signal inp_B : std_logic_vector(3 downto 0) := "0000";
signal inp_cin : std_logic := '0';
signal outp_S : std_logic_vector(3 downto 0);
signal outp_Co : std_logic;
begin
-- create instance of component full_adder
DUT1 : add4 port map (A=>inp_A, B=>inp_B, cin=>inp_cin,
S=>outp_S, Co=> outp_Co);
process is
begin
inp_A <= "0000"; inp_B <= "0000";
inp_cin <= '0'; wait for 10 ns;
inp_A <= "0001"; inp_B <= "0001"; wait for 10 ns;
inp_A <= "1001"; inp_B <= "1001"; wait for 10 ns;
inp_A <= "1101"; inp_B <= "1101"; wait for 10 ns;
assert false report "end of simulation";
wait;
end process;
end behave;
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