PVT VARIATIONS

PVT is the Process, Voltage, and Temperature. In order to make our chip to work
after fabrication in all the possible conditions, we simulate it at different corners
of process, voltage, and temperature. These conditions are called corners. All
these three parameters directly affect the delay of the cell.

Process:

There are millions of transistors on the single-chip as we are going to lower nodes
and all the transistors in a chip cannot have the same properties. Process variation
is the deviation in parameters of the transistor during the fabrication.

During manufacturing a die, the area at the center and at the boundary will have
different process variations. This happens because layers that will be getting
fabricated cannot be uniform all over the die

Below are a few important factors which can cause the process variation

 The wavelength of the UV light

 Manufacturing defects
1. Oxide thickness variation
2. Dopant and mobility fluctuation
3. Transistor width
4. RC Variation
5. channel length
6. doping concentration,
7. metal thickness
8. impurity concentration densities
9. diffusion depths
10. imperfections in the manufacturing process like mask print, etching
These variations will cause the parameters like threshold voltage and threshold
voltage depends on different parameters like doping concentration, surface
potential, channel length, oxide thickness, temperature, source-to-body voltage,
and implant impurities,

Process variation is different for different technologies but is more dominant in

lower node technologies because transistors are in millions on the chip. Process
variations are due to variations in the manufacturing conditions such as
temperature, pressure, and dopant concentrations. As a consequence, the
different transistors have different lengths throughout the chip. This makes the
different propagation delay everywhere in a chip because a smaller transistor is
faster and therefore the propagation delay is smaller.

VOLTAGE

Let’s say the chip is operating at 1.2V. So, there are chances that at certain
instances of time this voltage may vary. It can go to 1.5V or 0.8V. To take care of
this scenario, we consider voltage variation.
There are multiple reasons for voltage variation.
 IR drop is caused by the current flow over the power grid network.
 Supply noise caused by parasitic inductance in combination with resistance
and capacitance. when the current is flowing through parasitic inductance (L) it
will causes the voltage bounce.

The supply voltage is given to any chip either externally from the DC source or
some voltage regulator. The voltage regulator will not give the same voltage all the
time. It can go above or below to the expected voltage and hence if voltage
change it will change the current and making the circuit slower or faster than
earlier.

Power is distributed to all transistors on the chip with the help of a power grid
network. Throughout a chip, the power supply is not constant it will change with
the placement of cells. The power grid network is made up of metals and metals
have their own resistance and capacitance. So, there is a voltage drop along the
power grid

The supply voltage reaching the power pins will not be the same for all standard
cells and macros because of the resistance variation of the metals. Consider there
are two cells, one which is placed closer to the DC power source, and others
placed far. As the interconnect length is more for the farther cell, it has more
resistance and results in a higher IR drop, and it reduces the supply voltage
reaching the farthest cell. As the voltage is less, this cell will take more delay to
power on than the cell which is placed closer. If nearer cells get higher voltage
then the cell is faster and hence the propagation delay is also reduced. That is the
reason because of which, there is variation in delays across the transistors.

The delay of a cell is depending on the saturation current and the saturation
current of a cell depends on the power supply. In this way, the power supply
affects the propagation delay of a cell.

The self-inductance of a supply line contributes also to a voltage drop. For

example, when a transistor is switching to high, it takes a current to charge up the
output load. This time-varying current (for a short period of time) causes an
opposite self-induced electromotive force. The amplitude of the voltage drop is
given by V=L*dI/dt, where L is the self-inductance and I is the current through the
line.

TEMPERATURE

Temperature:

The transistor density is not uniform throughout the chip. Some regions of the
chip have higher density and higher switching, resulting in higher power
dissipation and Some regions of the chip have lower density and lower switching,
resulting in lower power dissipation Hence the junction temperature at these
regions may be higher or lower depending upon the density of transistors.
Because of the variation in temperature across the chip, it introduces different
delays across all the transistors.
The temperature variation is with respect to the junction and not ambient
temperature. The temperature at the junction inside the chip can vary within a big
range and that’s why temperature variation needs to be considered. Delay of a cell
increases with an increase in temperature. But this is not true for all technology
nodes. For deep sub-micron technologies, this behavior is contrary. This
phenomenon is called a temperature inversion.

When a chip is operating, the temperature can vary throughout the chip. This is
due to the power dissipation in the MOS-transistors. The power consumption in
the transistors is mainly due to switching, short-circuit, and leakage power
consumption.

The average switching power dissipation is due to the required energy to charge
up the parasitic and load capacitances and the short-circuit power dissipation is
due to the finite rise and fall times and leakage power consumption is due to the
reverse leakage and sub-threshold currents.

The biggest contribution to power consumption is switching. The dissipated power

will increase the temperature. Mobility depends on temperature.
mobility= temp^-m
we know that with an increase in temperature, the resistivity of a metal
wire(conductor) increases. The reason for this phenomenon is that with an
increase in temperature, thermal vibrations also increase. This gives rise to
increased electron scattering and electrons start colliding with each other more
and the mobility of the primary carriers decreases with an increase in
temperature.

Similarly, for higher doping concentrations, the temperature is higher and thermal
vibrations are also increasing and the electrons and holes move slower i.e.
mobility decreases, then the propagation delay increases. Hence, the propagation
delay increases with increased temperature. The threshold voltage of a transistor
depends on the temperature. A higher temperature will decrease the threshold
voltage. A lower threshold voltage means a higher current and therefore a better
delay performance. This effect depends extremely on the power supply, threshold
voltage, load, and input slope of a cell. There is a competition between the two
effects and generally the mobility effect wins.

PVT variation means variations in process, voltage and temperature. Process

parameters variations in the integrated circuit could be deviation in oxide
thickness, diffusion depth or impurity concentration. These variations could occur
due to variations in the manufacturing conditions. Process parameters variations
could be seen throughout the chip. As a consequence, each transistor has
different transistor lengths throughout the chip. Thus propagation delay becomes
different everywhere in chip. There can be deviation in the given value of supply
voltage.
Variation in supply voltage too varies the propagation delay throughout the chip.
Temperature variation does happen throughout the chip. This is primarily because
of power dissipation in the MOSFETs. Majority of power in MOS IC is dissipated
during switching event. This is the time when both NMOS and PMOS transistors
are conducting. This dissipated power contribute temperature rise. The mobility
of electrons and holes depends on the temperature. So, when the electrons and
holes move slower. It increases the propagation delay. Thus propagation delay
increases with increases temperature.
PVT:
PVT is abbreviation for Process, Voltage and Temperature. In order to make our
chip to work in all possible conditions, like it should work in Siachen Glacier at
-40°C and also in Sahara Desert at 60°C, we simulate it at different corners of
process, voltage and temperature which IC may face after fabrication. These
conditions are called as corners. All these three parameters affect the delay of
the cell. We will see each and every parameter and its effect on delay in detail.

Process:
Process variation is the deviation in attributes of transistor during the
fabrication.

During manufacturing a die, the area at the centre and that at the boundary will
have different process variation. This happens because layers which will be
getting fabricated can not be uniform all over the die. As we go away from the
centre of the die, layers can differ in their sizes.

Process variation is gradual . It can not be abrupt.

Process variation is different for different technologies but is more dominant in

lower node technologies (<65nm).

Below are few important factors which can cause process variation;

1. Wavelength of the UV light

2. Manufacturing defects
The affects of process varition are listed below;

1. Oxide thickness variation

2. Dopant and mobility fluctuation

3. Transistor width, length etc.

4. RC Variation
These variations will cause the parameters like threshold voltage to change its
value from expected. Threshold voltage depends on oxide thickness, source-
to-body voltage and implant impurities. Consider the drain current equation for
NMOS;

ID = (1/2)μnCox (W/L)(VGS – VTh)2

As we are talking about process variation, it deals with physical properties of
MOSFET. So, current flowing through the channel directly depends upon
mobility (μn), oxide capacitance Cox (and hence thickness of oxide i.e. tox) and
ratio of width to length.
Any of these parameters change, it will result in changing the current. In other
words, it will affect the delay of the circuit. Delay decreases with increase in
current.

The relation between process and delay can be better understood with the
following curve shown in Figure 1.

From this relation, we say that delay is more for slow process MOSFETs and it is
less for fast process MOSFETs.

There are separate model files for every process corner.

Figure 1: Process Vs Delay Graph

Voltage:
Now a days, supply voltage for a chip is very less. Lets say chip is operating at
1V. So there are chances that at certain instance of time this voltage may vary.
It can go to 1.1V or 0.9V. To take care of this scenerio, we consider voltage
variation.

There are multiple reasons for voltage variation. These are discussed below.

The important reason for supply voltage fluctuations is IR drop. IR drop is

caused by the current flow over the parasitic resistance of the power grid. IR
drop reduces the supply voltage from the required value.
The second important reason for voltage variation is supply noise caused by
parasitic inductance in combination with resistance and capacitance. The
current through parasitic inductance causes the voltage bounce. Both these
effects together can not only lead to voltage drops but also voltage overshoot.

Supply voltage that any chip works on is given externally. It can come from DC
source or some voltage regulator. Voltage regulator will not give same voltage
over a period of time. It can go above or below the expected voltage and hence
it will cause current to change making the circuit slower or faster than earlier.

Because of all these factors, we have to consider the voltage variation. Figure 2
shows the relation between supply voltage and delay.

Figure 2: Voltage Vs Delay Graph

Temperature:
The temperature variation is with respect to junction and not ambient
temperature. The temperature at the junction inside the chip can vary within a
big range and that’s why temperature variation need to be considered. Figure 3
shows the variation of delay with respect to temperature. Delay of a cell
increases with increase in temperature. But this is not true for all technology
nodes. For deep sub-micron technologies this behaviour is contrary. This
phenomenon is called as temperature inversion.
 Figure 3: Temperature Vs Delay Graph
Temperature inversion: The delay depends on the output capacitance and
ID current (directly proportional to Cout and inversely proportional to ID). When
the temperature increases, delay also increases (due to the variation in carrier
concentration and mobility). But when temperature decreases, delay variation
shows different characteristics for submicron technologies. For technology
nodes below 65nm, the delay will increase with decrease in temperature and it
will be maximum at -40°C. This phenomena is known as “temperature
inversion”.

Why Temperature inversion happens?

As temperature increases, mobility and threshold voltage start decreasing. The

delay is inversely proportional to the mobility and directly proportional to the
threshold voltage.

So the resultant effect from both mobility and threshold voltage decides the
value of delay.

Consider the current equation of a MOSFET for better understanding;

ID = (1/2)μnCox (W/L)(VGS – VTh)2

In the higher technology node, where the supply voltage is very high, the effect
of VTh is very low as (VGS – VTh) value is large. Hence mobility plays major role in
deciding current. So at higher technology nodes, when the temperature
increases mobility decreases and as a result the delay will increase.
At the lower technology node (specifically, less than 65nm), the supply voltage
is very low, so the (VGS – VTh) difference is small and the square of this value is
very small resulting reduced ID current, which increases delay at lower
temperature. Where at other end above 65nm delay decreases at lower
temperature.

Process Variation

This variation accounts for deviations in the semiconductor fabrication process. Usually
process variation is treated as a percentage variation in the performance calculation.
Variations in the process parameters can be impurity concentration densities, oxide
thicknesses and diffusion depths. These are caused bye non uniform conditions during
depositions and/or during diffusions of the impurities. This introduces variations in the sheet
resistance and transistor parameters such as threshold voltage. Variations are in the
dimensions of the devices, mainly resulting from the limited resolution of the
photolithographic process. This causes (W/L) variations in MOS transistors.
Process variations are due to variations in the manufacture conditions such as temperature,
pressure and dopant concentrations. The ICs are produced in lots of 50 to 200 wafers with
approximately 100 dice per wafer. The electrical properties in different lots can be very
different. There are also slighter differences in each lot, even in a single manufactured chip.
There are variations in the process parameter throughout a whole chip. As a consequence,
the transistors have different transistor lengths throughout the chip. This makes the
propagation delay to be different everywhere in a chip, because a smaller transistor is faster
and therefore the propagation delay is smaller.
.
Supply Voltage Variation

The design’s supply voltage can vary from the established ideal value during day-to-day
operation. Often a complex calculation (using a shift in threshold voltages) is employed, but
a simple linear scaling factor is also used for logic-level performance calculations.
The saturation current of a cell depends on the power supply. The delay of a cell is
dependent on the saturation current. In this way, the power supply inflects the propagation
delay of a cell. Throughout a chip, the power supply is not constant and hence the
propagation delay varies in a chip. The voltage drop is due to nonzero resistance in the
supply wires. A higher voltage makes a cell faster and hence the propagation delay is
reduced. The decrease is exponential for a wide voltage range. The self-inductance of a
supply line contributes also to a voltage drop. For example, when a transistor is switching to
high, it takes a current to charge up the output load. This time varying current (for a short
period of time) causes an opposite self-induced electromotive force. The amplitude of the
voltage drop is given by .V=L*dI/dt, where L is the self inductance and I is the current
through the line.

Operating Temperature Variation

Temperature variation is unavoidable in the everyday operation of a design. Effects on
performance caused by temperature fluctuations are most often handled as linear scaling
effects, but some submicron silicon processes require nonlinear calculations.
When a chip is operating, the temperature can vary throughout the chip. This is due to the
power dissipation in the MOS-transistors. The power consumption is mainly due to
switching, short-circuit and leakage power consumption. The average switching power
dissipation (approximately given by Paverage = Cload*Vpower supply 2*fclock) is due to the
required energy to charge up the parasitic and load capacitances. The short-circuit power
dissipation is due to the finite rise and fall times. The nMOS and pMOS transistors may
conduct for a short time during switching, forming a direct current from the power supply to
the ground. The leakage power consumption is due to the nonzero reverse leakage and
sub-threshold currents. The biggest contribution to the power consumption is the switching.
The dissipated power will increase the surrounding temperature. The electron and hole
mobility depend on the temperature. The mobility (in Si) decreases with increased
temperature for temperatures above –50 °C. The temperature, when the mobility starts to
decrease, depends on the doping concentration. A starting temperature at –50 °C is true for
doping concentrations below 1019 atoms/cm3. For higher doping concentrations, the
starting temperature is higher. When the electrons and holes move slower, then the
propagation delay increases. Hence, the propagation delay increases with increased
temperature. There is also a temperature effect, which has not been considered. The
threshold voltage of a transistor depends on the temperature. A higher temperature will
decrease the threshold voltage. A lower threshold voltage means a higher current and
therefore a better delay performance. This effect depends extremely on power supply,
threshold voltage, load and input slope of a cell. There is a competition between the two
effects and generally the mobility effect wins.