ELEC 5804

VLSI DESIGN
FALL Term 2023

1
1
Key: Mass Production

The idea of placing multiple electronic devices on the same substrate material
came only after the late 1950s.
In 1959, the rst integrated circuit (IC) was constructed, which started a new era
of modern semiconductor manufacturing.
In less than 50 years, the CMOS process has gone from simple chips to ultra-
large-scale-integrated (ULSI) CMOS circuits with very high device densities.

2
2
fi
Silicon

3
3-1
Silicon

3
3-2
Pure Silicon Isn’t Much Of A Conductor

• At normal temperatures, intrinsic silicon behaves as an insulator because the number of

free hole-electron pairs available for conducting current is very low.
• The number of free hole-electron pairs available for conducting current is called the intrinsic
carrier concentration density, and is denoted by ni. At room temperature, let’s say 300 K (that’s
300 degrees Kelvin), the value of ni for silicon is 0.0145µm−3.
• Since there are 5×1010 silicon atoms in a cubic micrometer of pure silicon, the small
intrinsic carrier concentration density of intrinsic silicon means that only about three silicon
atoms out of 1013 will contribute an hole-electron pair at any given time at room temperature.
No wonder pure silicon isn’t much of a conductor!

4
4
Doping

• The conductivity of silicon can be adjusted by adding foreign atoms to the silicon
crystal. This process is called “doping”, and a “doped” semiconductor is referred to
as an “extrinsic” semiconductor.
• Depending on what type of material is added to the pure silicon, the resulting
crystal structure can either have more electrons than the normal number needed
for perfect bonding within the silicon structure, or less electrons than needed for
perfect bonding.

5
5
Donor Elements

6
6-1
Donor Elements

6
6-2
Donors

• When the dopant material increases the number of free electrons in the
silicon crystal, the dopant is called a “donor”.
• The donor materials commonly used to dope silicon are phosphorus, arsenic,
and antimony.
• In a donor-doped semiconductor the number of free electrons is much larger
than the number of holes, and so the free electrons are called the “majority
carriers” and the holes are called the “minority carriers”.

7
7
Acceptor Elements

8
8-1
Acceptor Elements

8
8-2
Acceptors

• Dopant atoms which accept electrons from the silicon lattice are also used to alter the
electrical characteristics of silicon semiconductors. These types of dopants are known as
“acceptors”.
• Acceptor impurity atoms have one less valence electron than necessary for complete
bonding with neighbouring silicon atoms. The holes are therefore the majority carriers
and the electrons are the minority carriers.
• Typical acceptor materials used to dope silicon are boron, gallium, and indium.

9
9
Recap: Donors & Acceptors

10
10-1
Recap: Donors & Acceptors

10
10-2
N-type and P-type Silicon

• Since electrons carry a negative charge and they are the majority carriers in a donor-
doped silicon semiconductor, any semiconductor which is predominantly doped with
donor impurities is known as “n-type”. Semiconductors with extremely high donor
doping concentrations are often denoted “n+ type”.
• Semiconductors doped with acceptor impurities are known as “p-type”, since the majority
carriers effectively carry a positive charge. Semiconductors with extremely high acceptor
doping concentrations are called “p+ type”.

11
11
Basic Steps
In fabricating an integrated circuit, there are three basic
operations that we can do:

12
12-1
Basic Steps
In fabricating an integrated circuit, there are three basic
operations that we can do:
1. Change material composition;
2. Add to a layer of material;
3. Remove from a layer of material.

12
12-2
Changing Composition

• Implantation
• Diffusion

13
13
Changing Composition: Implantation

Atoms are forced into the silicon

crystal.

The atom penetrate the crystal

depending on the kinetic energy
(speed). This is controllable.

The crystal is damaged.

14
14
15
15
Changing Composition: Annealing/Diffusion
Changing Composition:
Annealing/Diffusion
Annealing is a repair step.
Annealing is a repair step.

Implanted region Diffused region

make distance small, why?

Implanted region Diffused region

16
16
An older process:
0.35 micron CMOS

17
17
18
18
19
19
20
20
Adding a Layer

21
21-1
Adding a Layer

• Epitaxy
• Chemical Vapor Deposition
• Oxide Growth
• Sputtering
• Evaporation

21
21-2
Adding a Layer: Expitaxial Deposition latch - up

Epitaxy is the growth of crystals of one mineral on the crystal face of another mineral, such that
the crystalline substrates of both minerals have the same structural orientation.

Typically this is done using a “slow” process.

Chemical Vapor Deposition is one technique.

Molecular Beam Expitaxy is another method.

22
22
Adding a Layer: Chemical Vapor Deposition

Chemical Vapor Deposition (CVD) is a chemical process for depositing thin lms of various
materials. In a typical CVD process the substrate is exposed to one or more volatile
precursors, which react and/or decompose on the substrate surface to produce the desired
deposit.

23
23

fi
Side note: Poly
Chemical Vapor Deposition (CVD) can be used to make poly-crystalline silicon,
also called polysilicon or poly.
CVD is applied to grow the silicon quickly (so as to limit diffusion in previously
made layers).
Large crystals do not form. Hence “poly-crystalline”.

SiH4 → Si + 2 H2

24
24
Adding a Layer: Oxide Growth

SiO2 is a good insulator and can be used to separate conductive materials.

SiO2 can also be used as a “mask” – more later.
Basic procedure: introduce oxygen to the wafer’s environment and apply
heat.

25
25
Adding a Layer: Oxide Growth
Using Hydrogen/Oxygen steam accelerates oxide growth and is used to produce a thicker
oxide 2,000-24,000Å, this thick oxide is called " eld oxide" and it is found in areas on the
device where high isolation is needed.
The oxide growth occurs at the Silicon/Oxide interface where it actually grows from the
bottom-up. (Contrast this to CVD oxides.)

26
26
fi
Adding a Layer: Oxide Growth

Thermal oxide growth is not linear. The more oxide present, the more dif cult it is to add more
oxide. This is because it becomes dif cult for the Oxygen atoms to penetrate the oxide and reach
the Silicon interface.
If the temperature is raised, then Oxygen atoms will again diffuse through the existing oxide.

Interestingly, silicon wafers exposed to air at room temperature will grow between 12-19Å of
"native oxide". When this oxide reaches about 19Å it stops growing, and any additional oxide
must be grown at high temperature.

27
27
fi
fi
Adding a Layer: Sputtering
• A block of the desired material is suspended above the
wafer.

• Argon gas is introduced and heated to plasma state.

• Argon gas molecules impacting the desired material

dislodge atoms.

• Atoms land of the wafer surface like snow falling.

28
28
Adding a Layer: Sputtering
At low pressure, a voltage is applied to two parallel electrodes resulting in a plasma discharge. The
accelerated gas ions impinge onto the cathode (target) and metal atoms are emitted from the target
which deposit on the wafer leading to layer growth.

Ref: http://www.leb.e-technik.uni-erlangen.de/lehre/mm/html/deposition_sputter.htm 29
29
Adding a Layer: Evaporation
• Wafers are loaded into an evacuated chamber.

• The desired material is heated to boiling.

• Evaporated material atoms (usually metal) y about the chamber. Some stick to the wafer.

30
30
fl
Removing a Layer: Etching

• The wafer is exposed to chemicals that dissolve unwanted material.

• Unprotected structures are etched.
• Protected structures are also affected (more later).
• Strong acids used: hydro ouric acid.
• Alternative: RIE (reactive ion etching).

31
31
fl
Lithography
In our examination of integrated circuit layout and design, we will de ne an integrated circuit as a set of patterned
layers. Each layer has speci c electrical characteristics, such as sheet resistance, and is patterned according to the
layers above and below. Stacking different material patterns results in geometrical objects that function electrically as
devices or interconnects.
Lithography is the process used to transfer desired patterns to each layer of material on the chip. There are several
steps used in the lithographic sequence. The major ones are:
• Drawing the patterns using a layout editor
• Preparing each pattern for physical transfer to the wafer
• Transferring the pattern on the wafer (called printing)
• Using processing techniques to physically pattern each layer.

32
32
fi
fi
Layout Versus Reality

A “layout editor” allows us to view all of the layers the de ne the integrated circuit simultaneously, but the
lithographic sequence must be applied separately for each layer that makes up the chip.
Using the completed design le, information is extracted for each layer in the process. This data is used to create
individual masks for each layer.
A mask is a plate of glass on which the pattern has been duplicated on a thin layer of chromium on the surface of
the glass. The mask is transparent to light except in regions where the chromium acts to block light transmission.

33
33
fi
fi
Basic Mechanisms
In fabricating an integrated circuit, the lithographic sequence is repeated for each material layer
used to construct the device. The sequence is always the same:
1. Photoresist application;
2. Printing (exposure);
3. Development;
4. Etching.
The limitations of the patterning process, such as the minimum resolution and the minimum
spacings, give rise to a set of mask design guidelines called design rules.

34
34
Masks
• Glass substrate.
• Chromium metal used to
de ne patterns.

• One mask for each

process step requiring it.

• Mask alignment is crucial.

35
35
fi
Mask Stepping

36
36
Basic Lithographic Sequence

37
37
Planarization

• The surface of the chip becomes uneven as

processing progresses.

• It is necessary to planarize the surface to avoid

manufacturing defects.

• CMP – chemical mechanical polishing is used.

• Design rules are written with CMP in mind.

38
38
SiO2 as a Mask

39
39
Processing Steps

40
40
Summary of Steps
1. Oxidation layering — this optional step deposits a thin layer of SiO2 over the complete wafer by exposing it to a mixture of high-purity oxygen and hydrogen at approximately 1000°C. The
oxide is used as an insulation layer and also forms transistor gates.

2. Photoresist coating — a light-sensitive polymer (similar to latex) is evenly applied while spinning the wafer to a thickness of approximately 1 micron.

3. Stepper exposure — a glass mask (or reticle), containing the patterns of the negative of one layer of the microcircuit. The combination of mask and wafer is exposed to ultra-violet light.
Where the mask is transparent, the photoresist becomes insoluble.

4. Photoresist development and bake — the wafers are developed in either an acid or base solution to remove the non-exposed areas of photoresist. Once the exposedphotoresist is removed,
the wafer is “soft-baked” at a low temperature to harden the remaining photoresist.

5. Acid Etching — material is selectively removed from areas of the wafer that are not covered by photoresist.

6. Spin, rinse, and dry — a special tool (called SRD) cleans the wafer with deionized water and dries it with nitrogen.

7. Various process steps — the exposed area can now be subjected to a wide range of process steps, such as ion implantation, plasma etching, or metal deposition.

8. Photoresist removal (or ashing) — a high-temperature plasma is used to selectively remove the remaining photoresist without damaging device layers.

41
41
The MOSFET
CMOS is an acronym for complementary metal-oxide-semiconductor. In everyday usage, the term CMOS can imply the technology, circuits, chips,
or virtually anything having to do with the technology itself. CMOS has become the dominant silicon technology for high-density logic circuits,
primarily because the transistors can be made very small, allowing for VLSI (very-large-scale integration) designs.
MOSFETs (metal-oxide-semiconductor eld-effect transistors) are the transistors used in CMOS integrated circuits. There are two types of MOSFETs:
n-channel transistors that use negatively-charged electrons for current, and p-channel devices that conduct current by means of positively-charged
holes.
MOSFETs have become the primary switching devices in high-density IC design because
• They are extremely small;
• The "drain" and "source" terminals are interchangeable;
• The device structures are very simple.

42
42
fi
MOSFET PHYSICAL STRUCTURE
The MOSFET is considered a four terminal device. These terminals are known as
the gate (G), the bulk (B), the drain (D), and the source (S), and the voltages
present at these terminals collectively control the current that ows within the
device.

43
43-1
fl
MOSFET PHYSICAL STRUCTURE
The MOSFET is considered a four terminal device. These terminals are known as
the gate (G), the bulk (B), the drain (D), and the source (S), and the voltages
present at these terminals collectively control the current that ows within the
device.

43
43-2
fl
MOSFET PHYSICAL STRUCTURE
• The physical structure of the MOSFET is a direct consequence of the processes of “doping”,
deposition, growth, and etching which are fundamental in conventional processing facilities.

44
44
MOSFET Con gurations

45
45
fi
MOSFET Parasitic Diodes

46
46-1
MOSFET Parasitic Diodes

46
46-2
Example Process Flow

47
47
48
48-1
Our starting point is not “intrinsic”
silicon, it’s actually P-type silicon. This
will be an “n-well” process, with native
NFETs, and PFETs placed in n-wells.

48
48-2
49
49-1
49
49-2
50
50-1
50
50-2
51
51-1
51
51-2
51
51-3
52
52-1
52
52-2
53
53
54
54
55
55-1
55
55-2
56
56
57
57
58
58-1
58
58-2
59
59-1
59
59-2
60
60-1
60
60-2
60
60-3
61
61-1
61
61-2
62
62-1
62
62-2
63
63-1
63
63-2
64
64-1
64
64-2
65
65-1
65
65-2
66
66-1
66
66-2
66
66-3
66
66-4
66
66-5
66
66-6
66
66-7
66
66-8
66
66-9
66
66-10
67
67
68
68-1
68
68-2
69
69
70
70-1
70
70-2
71
71
72
72
73
73
74
74
75
75
76
76
77
77
78
78
79
79
80
80
81
81