Scribd
Upload
51 views2 pages

Resume For Reference

The document contains the resume of Yaswantha Someswara Rao Raja, outlining his career objective to build a career in high speed VLSI design. It details his core competencies in areas like ASIC design flow, SystemVerilog, physical design, and tools proficiency. Examples of his projects and education qualifications are also provided.

Uploaded by

Sai Nrusimha Deepak Burra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
51 views2 pages

Resume For Reference

The document contains the resume of Yaswantha Someswara Rao Raja, outlining his career objective to build a career in high speed VLSI design. It details his core competencies in areas like ASIC design flow, SystemVerilog, physical design, and tools proficiency. Examples of his projects and education qualifications are also provided.

Uploaded by

Sai Nrusimha Deepak Burra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Powered by Nanochip Solutions

Yaswantha Someswara Rao Raja


[email protected], 9642273385
Narasaraopeta-522601, Andra Pradesh

Career Objective

Intend to build a career with committed and dedicated people, which will help me to realize
my potential, enhance my skill set in the field of High speed VLSI and help the organization
grow.

Core Competancy

Proficiency in digital logic design, including RTL (Register-Transfer Level) design, finite state
machines, and sequential logic.
ASIC Design Flow: Proficient understanding of the complete ASIC design process.
Knowledge of verification methodologies such as UVM (Universal Verification Methodology)
and familiarity with simulation and emulation tools like ModelSim, VCS,or Questa.
Knowledge on System Verilog for creating testbenches, assertions, and functional coverage.
Understanding of low-power design techniques and verification methodologies.
Effective communication and teamwork skills, as VLSI engineers often work in cross-functional
teams with design, STA and physical design engineers.
VLSI Physical Design APR: Strong knowledge and hands-on experience in VLSI Physical
Design, including APR flow.Undestanding of Design for Testability (DFT) techniques.
Tools Mastery: Proficiency in using Synopsys tools, such as Synopsys VCS, Synopsys ICC2 for
Block-Level implementation and STA Prime Time Shell.
Physical Flow Expertise: Comprehensive knowledge across Physical Flow stages, including
Floor Planning, IR Drop analysis, Place and Route, Clock Tree Synthesis (CTS).
Strong knowledge and Hands-on experience on Physical Verification Tools and ability to
perform Layout Verification, DRC, LVS, PEX.

Education Details
Advanced Diploma in ASIC Design 2023
RV-VLSI Design Center
Bachelor Degree in Electrical and Electronics 2020
Gudlavalleru Engineering College, with 8.54 CGPA
12th 2016
Bhavana Junior College, with 84 %
SSLC 2014
Guntur Oxford High School, with 90 %

Powered by Nanochip Solutions


Powered by Nanochip Solutions

Domain Specific Project


RV-VLSI Design Center
Graduate Trainee Engineer Oct-2022 to Jan-2023
Block Level implementation of a Full Chip
Description

Block Level implementation of a Full Chip which incorporates 34 Macros,38887 standard cells
with a voltage of 1.1V working at a frequency of 833MHz.It used a total of 6 Clocks and 7
Metal Layers of 40nm technology.

Tools

VCS, PT_Shell, ICC2_Shell, IC Validator

Roles and Responsibilities

Using Constrained Randomization to generate the required testcases for checking main and
corner cases to achieve 100% Code Coverage and Functional Coverage.
Validating the timing performance of a design by checking all possible paths based on setup
and hold.
Place standard cells available in synthesized netlist with optimization by considering
routability.
Creating a floorplan without congestion, IR, timing, noise and Routing issues.Analyzing and
fixing DRC and LVS issues.

B.E / B.Tech Academic Project


Gudlavalleru Engineering College
SMART AGRICULTURAL DRONE SPRAYER
Description

Project describes the development of Quad-Copter UAV and the spraying mechanism. In this
project we also discuss integration of sprayer module to quad copter system.The discussed
system involves designing a prototype which uses simple cost effective.

Tools

1.Fly Sky FS-CT6B 6-Channel 2.4 Ghz Transmitter and Receiver. 2.Flight Control Board. 3.KK
2.1 Multirotor Control Board. 4.Brushless 40A ESC.

Challenges

1.Lifting two liters of Pesticide Tank with A2212-2200kv BLDC motors. 2.Binding Flysky 6-
channel transmitter and Receiver over 200m from ground.

Powered by Nanochip Solutions

You might also like