Lecture 7

Systemverilog 2

Data Types and Interfaces

 Memory Read

 What are different data types?

 Different types of arrays
 Two valued data types

 FIFO Design experience

User Defined Data Types
• The typedef keyword allows user-defined data types.
• Types must be declared before they are used
– Outside of a module (global type) => visible for all lexically following design units
– Inside a module or inside any declarative scope => visible only within that module
or declarative scope
– Inside a package and imported into the module
Creating a custom array using typedef

// Create a custom array using typedef

typedef logic [7:0] logic8_array [4];

logic8_array example;

// Using an array literal to assgin data to the variable

example = '{ 8'h01, 8'h02, 8'h03, 8'h04 };

// Using square brackets to assign data to the variable

example[0] = 8'h01;
example[1] = 8'h02;
example[2] = 8'h03;
example[3] = 8'h04;
 Enumeration
Syntax:
enum [enum_base_type] { enum_name_declaration {,enum_name_declaration} }

enum_base_type: default is int

Enumeration is a useful way of defining abstract variables.

NOTE:
Define an enumeration with “ enum ”
Default assigned values start at zero
enum {red, green, yellow} traf_lite1, traf_lite2;
0 1 2
enum {red, green, yellow} lite;
Values can be cast to integer types and auto-incremented
enum { a=5, b, c} vars; // b=6, c=7

A sized constant can be used to set size of the type

enum bit [3:0] { bronze=4’h3, silver, gold} medal; // All medal members are 4-bits

Define a new type

typedef enum {NO, YES} bool; // bool is NOT a SystemVerilog type
bool myvar; // but it just became one 
“myvar” will now be checked for valid values in
all assignments, arguments and relational
operators
Why enumeration? - Readability

Without Enumeration With Enumeration

FSM using Enumerated Types
module enum_type (input clk, reset);

typedef enum {ST0, ST1, ST2} state_e;

state_e current_state, next_state;
always @(posedge clk or negedge reset) begin
if (!reset)
current_state <= ST0;
else
current_state <= next_state;
end
always @* begin
next_state = ST0;
case (current_state)
ST0: next_state = ST1;
ST1: next_state = ST2;
ST2: next_state = ST0;
endcase // case (current_state)
end
endmodule
Structures and Classes
 Structs and classes are used to represent information composed of various smaller pieces of
different types.

 They can be used to model packets, frames, instructions, commands, floating-point numbers etc

 Whenever you declare a variable of a struct type, the necessary number of bits is automatically
allocated. If you assign a struct variable to another, or pass a struct as an argument to a function
or task, as shown in Sample 4-24, all of the bits are copied.

function ieee_sp_float abs(ieee_sp_float v);

v.sign = 0;
abs = v;
typedef struct { endfunction: abs
bit sign;
bit [24:0] mantissa; ieee_sp_float v1, v2;
bit [ 5:0] exponent;
v1 = {1, 24’h800, 6’h0};
} ieee_sp_float
v2 = v1;
v1 = abs(v1);
Packed vs Unpacked
Packed Structures

• If a struct is declared packed, as shown in the code snippet, the bits of the struct
fields are laid out consecutively in memory, as shown in Figure.

• This allows the struct to be transparently converted to and from bit vectors or integer
values.

typedef struct packed {

bit sign;
bit [24:0] mantissa;
bit [ 5:0] exponent;
} ieee_sp_float
 Type Conversion
Static cast converts between 2 types No bounds checking
int i;
real r;
byte b;

initial begin
i=int'(10.0-0.1);
$display("i = 0d%0d", i); # i = 0d10
r=real'(42);
$display("r = %f", r); # r = 42.000000
b=byte'(256);
$display("b = 0d%0d", b); # b = 0d0
end

Chapter 2 Copyright 2011 G. Tumbush, C. Spear, v1.2 11

Putting it all together: SCOREBOARD
typedef struct packed
{bit [7:0] addr;
bit [7:0] pr;
bit [15:0] data; } Packet;

Packet scb[$]; // Queue of packets

function void check_addr(bit [7:0] addr);

int intq[$];
intq = scb.find_index() with (item.addr == addr);
case (intq.size())
0: $display("Addr %h not found in scoreboard", addr);
1: scb.delete(intq[0]);
default:
$display("ERROR: Multiple hits for addr %h", addr);
endcase
endfunction : check_addr
Summary: What you can do with Data Types?

• 2-state data types (bit, int, shortint, longint, byte)

– Remove “X” and “Z” states and are initialized to zero at time 0
– Allows for variable types that are compatible with SysC and C/C++

• User-defined data types (typedef)

– Allows users to define a type that is used throughout the design
– Examples: modify bus widths without using parameters

• Enumerations (enum)
– Give names to states in a FSM or op-codes in an instruction set
– Can be used instead of parameter or ‘define
 Choosing a data structure?
Network packets . Properties: fixed size, accessed sequentially. Use a fixed-size or
dynamic array for fixed- or variable-size packets.

Scoreboard of expected values. Properties: array size not known until run time,
accessed by value, and a constantly changing size. In general, use a queue, as you are
continually adding and deleting elements during simulation. If you can give every
transaction a fixed ID, such as 1, 2, 3, ..., you could use this as an index into the
queue. If your transaction is filled with random values, you can just push them into a
queue and search for unique values. If the scoreboard may have hundreds of
elements and you are often inserting and deleting them from the middle, an
associative array may be faster.
Choosing a data structure?

• Sorted structures . Use a queue if the data comes out in a predictable order or an
associative array if the order is unspecified.

• Modeling very large memories, greater than a million entries . If you do not need
every location, use an associative array as a sparse memory. If you do plan on
accessing every location, try a different approach where you do not need so much
live data. Be sure to use 2-state values packed into 32-bits to conserve simulation
memory.

• Command names or opcodes from a file . Property: translate a string to a fixed

value. Read string from a file, and then look up the commands or opcodes in an
associative array using the command as a string index.
Interfaces
Interfaces are a new feature added to:

– Raisethe level of abstraction and simplify design block communication by

allowing a number of signals to be represented as a single port

– Allow module port directional information and tasks/functions to be defined

inside the interface.

– Reduce the amount of code and promote reuse

– Synthesizability allows usage in the design as well as the testbench

Interface Concept
 Interface Definition
• A simple interface is a named bundle of nets/variables

• It is instantiated in a design and can be accessed

–Through a port as a single item
– Component nets/variables referenced where needed

• Additional features are unique to interfaces:

– modports describe directional information for module ports and
control the use of tasks/functions inside an interface
 Interface & Struct

int i; int i;
logic [7:0] a; wire [7:0] a;

typedef struct { interface intf;

int i; int i;
logic [7:0] a; wire [7:0] a;
} s_type; At the simplest level an endinterface : intf
interface is to a wire what a
struct is to a variable
Interface Syntax
Example without Interface
Example with Interface
Defining port direction: interface i2;
wire a, b, c, d;
modport master (input a, b,
modport output c, d);
modport slave (output a, b,
input c, d);
endinterface : i2
• Different users of interface need module m (i2.master itf);
different views …
• Master/Slave endmodule: m

module s (i2.slave itf);

• Restrict access to internal …
endmodule: s
interface signals
• Protect implementation signals module top();
from corruption i2 i();

m u1(.itf(i.master));
s u2(.itf(i.slave));
endmodule: top
Modport: Example
interface arb_if(input bit clk);
logic [1:0] grant, request;
logic rst;
module monitor (arb_if.MONITOR arbif);
modport TEST (output request, rst,input grant, clk);
always @(posedge arbif.request[0]) begin
modport DUT (input request, rst, clk, output grant); $display("@%0t: request[0] asserted", $time);
@(posedge arbif.grant[0]);
modport MONITOR (input request, grant, rst, clk); $display("@%0t: grant[0] asserted", $time);
end
endinterface
always @(posedge arbif.request[1]) begin
module arb (arb_if.DUT arbif); $display("@%0t: request[1] asserted", $time);
... @(posedge arbif.grant[1]);
endmodule $display("@%0t: grant[1] asserted", $time);
module test (arb_if.TEST arbif); end
...
endmodule endmodule
Interface : Advantages
An interface is ideal for design reuse. When two blocks communicate with
a specified protocol using more than two signals, consider using an
interface.

The interface takes the jumble of signals that you declare over and over
in every module or program and puts it in a central location, reducing the
possibility of misconnecting signals.

To add a new signal, you just have to declare it once in the interface, not
in higher-level modules, once again reducing errors.

Modports allow a module to easily tap a subset of signals from an

interface. You can specify signal direction for additional checking.
 Interface : Disdvantages

For point-to-point connections, interfaces with modports are almost as verbose as

using ports with lists of signals. Interfaces have the advantage that all the
declarations are still in one central location, reducing the chance for making an
error.

You must now use the interface name in addition to the signal name, possibly
making the modules more verbose.

If you are connecting two design blocks with a unique protocol that will not be
reused, interfaces may be more work than just wiring together the ports.

It is difficult to connect two different interfaces. A new interface (bus_if) may

contain all the signals of an existing one (arb_if), plus new signals (address, data,
etc.). You may have to break out the individual signals and drive them
appropriately.