Intro

to
Systemverilog
 What is SystemVerilog?

 SystemVerilog is a hardware description and Verification language(HDVL)

 SystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog-

2001 standards

 It has features inherited from Verilog HDL,VHDL,C,C++

 Adds extended features to verilog

 What is SystemVerilog?

 System verilog is the superset of Verilog

 It supports all features of verilog plus add on features

 additional features of system verilog will be discussed

Why SystemVerilog?

Higher Level of Abstraction

Constrained Randomization Easy C model integration

OOP support New data types ie,logic

System Verilog
Assertions Coverage support

Narrow gap b/w design & verification engineer

 Complexity

Verilog System Verilog

 For complex designs  Less RTL & verification code

large number of RTL code is
required  Less code hence less no. of bugs

 Increase in verification  Readable

code to test these designs  Higher level of abstraction due to
 Extra time algorithmic nature(inherited from
C++)
 Example: User-defined types and structures:
SystemVerilog code more compact, more readable, less error-prone, and portable from the C language.
Relaxed data type rules

Verilog System Verilog

 Strict about usage of  Logic data type can be used so no

wire & reg data type need to worry about reg & wire
 Variable types are 4 state  2 state data type added – 0, 1 state
– 0,1,X,Z
 2 state variable can be used in test
benches, where X, Z are not required
 2 state variable in RTL model may
enable simulators to be more efficient
 Memory Management

Verilog System Verilog

 Memories in verilog are  Memories are dynamic in

static in nature nature
Example :-reg[7:0] X[0:127];  Allocated at runtime
128 bytes of memory  Better memory management
ie,queues
Example:Logic[3:0] length[$];
an empty queue with an
unbounded size of logic data
type
Hardware specific procedures

Verilog System Verilog

It uses the “always” It uses three new procedures

procedure to represent
 always_ff - sequential logic
 Sequential logic
 always_comb - combinational
 Combinational logic logic
 Latched logic  always_latch - latched logic
 Port Connections

Verilog System Verilog

 Ports are connected using either  Ports are connected using

named instance or positional instance Design DUT(.*); which means connect all
port to variables or nets with the same
name as the ports
reg_file#(`D_WIDTH, `A_WIDTH)
reg_file1(.clk(clk),
.reset(reset),
.wr_enb(wr_enb), reg_file#(`D_WIDTH, `A_WIDTH) reg_file1(.*);
.wr_addr(wr_addr),
.rd_addr(rd_addr),
.wr_data(wr_data),
.rd_data(rd_data)
);
Verification targeted capabilities

Verilog System Verilog

 File I/o All verilog features

 Random number  Constrained random number
generation generation
 Fork/join  Classes
 Initial block  Fork/join_any,fork/join_none
 Task & functions  Final block
 PLI  Task & function enhancements
 DPI
SystemVerilog Components
 Verification environment

Checks Testbench
Verification
correctness Environment
Creates
stimulus
Identifies
Executes Test Self Check transactions
transactions

Transactor Checker Observes

Supplies data data
to the DUT from DUT
Driver Assertions Monitor

DUT
Powerful Syntax – .* Port Connections
Interface
Interface contd…
fork… join
initial begin
#10ns;
Spawn concurrent processes from a single process: fork
begin
 A is printed at 30ns;
#20ns;
 B at 20ns;
 the last display takes place at 40ns $display( “A\n" );
end
begin
Join waits until both sub-processes have finished, #10ns;
$display( “B\n" );
#20ns;
end
join
$display(both finished);
end
 Dynamic Processes
Inspired by the need for software verification environments to dynamically start and stop threads,
SystemVerilog defines 2 new special cases of fork…join with associated keywords join_any & join_none

join_any join_none

begin
fork
fork
…
other blocks …
… continue as dynamic
join_none // no waiting at all
… threads
@(sig1);
join_any // any block finished end
Assertions Example
Specification says that after request signal is asserted, acknowledge signal
must come 1 to 3 cycles later

V2K Assertion

SVA Assertion
 In summary
– C/C++ type language constructs for efficient programming
– Interfaces to encapsulate communication between design blocks
– Assertions and coverage for new verification techniques
– System-level testbench features
– Lightweight interface to C/C++ programs

It is a concise, unified language for design and testbenches.