SEMICONDUCTOR

DEVICES - THEORY
AND APPLICATION

James M. Fiore
Mohawk Valley Community College
Mohawk Valley Community College
Semiconductor Devices - Theory and
Application

James M. Fiore
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This text was compiled on 11/13/2023
TABLE OF CONTENTS
Licensing
Acknowledgements
Preface

1: Semiconductor Fundamentals
1.1: Introduction
1.2: Atomic Structure
1.3: Crystals
1.4: Doped Materials
1.5: Summary

2: PN Junctions and Diodes

2.1: Introduction
2.2: The PN Junction
2.3: Diode Data Sheet Interpretation
2.4: Diode Circuit Models
2.5: Other Types of Diodes
2.6: Summary
2.7: Exercises
2.8: An Alternate Hypothesis Regarding PN Junctions

3: Diode Applications
3.1: Introduction
3.2: Rectification
3.3: Clippers
3.4: Clampers
3.5: Summary
3.6: Exercises

4: Bipolar Junction Transistors (BJTs)

4.1: Introduction
4.2: The Bipolar Junction Transistor
4.3: BJT Collector Curves
4.4: BJT Data Sheet Interpretation
4.5: Ebers-Moll Model
4.6: DC Load Lines
4.7: BJT Switching and Driver Applications
4.8: Summary
4.9: Exercises

5: BJT Biasing
5.1: Introduction
5.2: The Need For Biasing
5.3: Two-Supply Emitter Bias

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 5.4: Voltage Divider Bias
5.5: Feedback Biasing
5.6: Summary
5.7: Exercises

6: Amplifier Concepts
6.1: Introduction
6.2: Amplifier Model
6.3: Compliance and Distortion
6.4: Frequency Response and Noise
6.5: Miller's Theorem
6.6: Summary
6.7: Exercises

7: BJT Small Signal Amplifiers

7.1: Introduction
7.2: Simplified AC Model of the BJT
7.3: Common Emitter Amplifier
7.4: Common Collector Amplifier
7.5: Common Base Amplifier
7.6: Multi-Stage Amplifiers
7.7: Summary
7.8: Exercises

8: BJT Class A Power Amplifiers

8.1: Introduction
8.2: Amplifier Classes
8.3: Class A Operation and Load Lines
8.4: Loudspeakers
8.5: Power Transistor Data Sheet Interpretation
8.6: Heat Sinks
8.7: Summary
8.8: Exercises

9: BJT Class B Power Amplifiers

9.1: Introduction
9.2: The Class B Configuration
9.3: Extensions and Refinements
9.4: Summary
9.5: Exercises

10: Junction Field Effect Transistors (JFETs)

10.1: Introduction
10.2: JFET Internals
10.3: JFET Data Sheet Interpretation
10.4: JFET Biasing
10.5: Summary
10.6: Exercises

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11: JFET Small Signal Amplfiers
11.1: Introduction
11.2: Simplified AC Model of the JFET
11.3: Common Source Amplifier
11.4: Common Drain Amplifier
11.5: Multi-stage and Combination Circuits
11.6: Ohmic Region Operation
11.7: Summary
11.8: Exercises

12: Metal Oxide Semiconductor FETs (MOSFETs)

12.1: Introduction
12.2: The DE-MOSFET
12.3: DE-MOSFET Biasing
12.4: The E-MOSFET
12.5: E-MOSFET Data Sheet Interpretation
12.6: E-MOSFET Biasing
12.7: Summary
12.8: Exercises

13: MOSFET Small Signal Amplifiers

13.1: Introduction
13.2: MOSFET Common Source Amplifiers
13.3: MOSFET Common Drain Followers
13.4: Summary
13.5: Exercises

14: Class D Power Amplifiers

14.1: Introduction
14.2: Class D Basics
14.3: Pulse Width Modulation
14.4: Output Configurations
14.5: Summary
14.6: Exercises

15: Insulated Gate Bipolar Transistors (IGBTs)

15.1: Introduction
15.2: IGBT Internals
15.3: IGBT Data Sheet Interpretation
15.4: IGBT Applications
15.5: Summary
15.6: Exercises

Index

Glossary
Detailed Licensing

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Licensing
A detailed breakdown of this resource's licensing can be found in Back Matter/Detailed Licensing.

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Acknowledgements
For their continued support, my family and friends. For their input on draft versions, my colleagues (esp. Ben Glallard, Hill Bunt,
Deb Bocker, Hal Paulko, Thom Timas) and students. For on-going sanity reassurance, Bernie Sanders and Mike Lofgren. For
unintentional diversionary humor elicitation, Wally and pals.
Finally, a serious thank you, thank you, thank you to all of the people who have created useful software and other OER tools
without which this project would have been impossible. When we each do a little, we all gain a lot. This text was created using
several free and open software applications including Open Office and Dia. Some graphs and device curves were created using
SciDAVis. Screen imagery was often manipulated though the use of XnView.
- Jim Fiore, 2017
For Karen

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Preface
Welcome to the first edition of Semiconductor Devices, an open educational resource (OER). The goal of this text, as its name
implies, is to allow the reader to become proficient in the analysis and design of circuits utilizing discrete semiconductor devices. It
progresses from basic diodes through bipolar and field effect transistors. The text is intended for use in a first or second year course
on semiconductors at the Associate or Baccalaureate level. In order to make effective use of this text, students should have already
taken coursework in basic DC and AC circuits, and have a solid background in algebra and trigonometry along with exposure to
phasors. Calculus is used in certain sections of the text but for the most part it is used for equation derivations and proofs, and is
kept to a minimum. For students without a calculus background these sections may be skipped without a loss of continuity.
An OER companion laboratory manual is also available. It features nearly 30 exercises that parallel the topics presented in this text.
For continued study, a follow-on OER text and lab manual, Operational Amplifiers and Linear Integrated Circuits, Third Edition is
available. Several other electrical OER titles are also available.
I cannot say enough about the emerging Open Educational Resource movement and I encourage budding authors to consider this
route. While there are (generally) no royalties to be found, having complete control over your own work (versus the “work for hire”
classification of typical contracts) is not to be undervalued. Neither should contributions to the profession nor the opportunity to
work with colleagues be dismissed. Given the practical aspects of the society in which we live, I am not suggesting that people
“work for free”. Rather, because part of the mission of institutes of higher learning is to promote and disseminate formalized
instruction and information, it is incumbent on those institutions to support their faculty in said quest, whether that be in the form
of sabbaticals, release time, stipends or the like. It is also my opinion that no one should be deprived of a higher education due to
lack of funds. A society that truly cares for its citizens would institute free college tuition.
If you have any questions regarding the text or lab manual, or are interested in contributing to the project, do not hesitate to contact
me. Finally, please be aware that the most recent versions of all of my OER texts and manuals may be found at my MVCC web site
as well as my mirror site: www.dissidents.com

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 CHAPTER OVERVIEW

1: Semiconductor Fundamentals
Learning Objectives
After completing this chapter, you should be able to:
Define the term semiconductor.
Describe the differences between conductors, semiconductors and insulators in terms of atomic energy levels.
Describe the atomic structure of mono-crystalline silicon.
Detail the effect of doping on a silicon crystal.
Describe the differences between P material and N material.
Draw the energy level diagrams for P- and N-type materials.

1.1: Introduction
1.2: Atomic Structure
1.3: Crystals
1.4: Doped Materials
1.5: Summary

This page titled 1: Semiconductor Fundamentals is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James
M. Fiore via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.

1
1.1: Introduction
1.1.1: First, a Little History
Just as the late eighteenth through nineteenth centuries are known as the industrial age due to the rise of mechanization, the
twentieth century can be referred to as the beginning of the electronic age. The first half of the century was dominated by electronic
vacuum tubes that made possible devices such as radio, television, radar and long distance telephone. The technology of the
vacuum tube was displaced mid-century by the introduction of solid-state semiconductors. The first working prototype transistor
was invented at Bell Labs in 1947 by John Bardeen, Walter Brattain and William Shockley. This device, properly referred to as a
point contact transistor, was quickly superseded by the bipolar junction transistor, a major topic of this text.
Commercial production of the transistor and related devices improved the performance of existing applications and made possible a
range of new ones. Semiconductors proved to be smaller, lighter, more reliable and less expensive to build than their vacuum tube
counterparts. The last 30 or so years of the century saw the rapid expansion of the integrated circuit where numerous transistors are
combined in a single device. Initially such a device may have contained the equivalent of a dozen or so individual semiconductor
devices, but today that number has grown to the billions1. This extreme density has given rise to now common-place applications
such as cell phones, GPS devices, laptop computers, tablets and our global communications infrastructure.
The science writer, Arthur C. Clarke, once observed that “Any sufficiently advanced technology is indistinguishable from magic”.
Indeed, although today the typical citizen living in an industrialized country makes use of numerous electronic devices each day
(sometimes without even being aware of it), they typically have scant knowledge of how these devices “work their magic”.
Obviously there is no magic, only the application of scientific principles mixed with human ingenuity. Further, just as it is true that
many more people can use a cell phone than design one, it is also true that there is a greater need for people who can design,
manufacture and maintain devices based on semiconductors than for people who design the semiconductors themselves. The scope
of this text, then, focuses on the operation and application of semiconductor devices rather than the design of the semiconductors
themselves.

1.1.2: Variable Naming Convention

One item that often confuses beginning students of almost any subject is nomenclature. Before we begin our discussion of
semiconductor devices it is important that we decide upon a consistent naming convention. Throughout this text we will be
examining numerous circuits containing several passive and active components. We will be interested in a variety of parameters
and signals. In order to keep confusion to a minimum we will use the following conventions in our equations for naming devices
and signals.

R Resistor (DC, or actual circuit component)

r (AC equivalent, where phase is 0 or ignored)

C Capacitor

L Inductor

Q Transistor (Bipolar or FET)

D Diode

V Voltage (DC)

v Voltage (AC)

I Current (DC)

i Current (AC)

Table 1.1.1
Resistors, capacitors and inductors are differentiated via a subscript that usually refers to the active device to which it is connected.
For example, R is a DC bias resistor connected to the emitter of a transistor while r refers to the AC equivalent resistance seen
E C

at a transistor’s collector. C refers to a capacitor connected to a transistor’s emitter lead. Note that the device related subscripts are
E

always shown in upper case, with one exception: If the resistance or capacitance is part of the device model, the subscript will be

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shown in lower case to distinguish it from the external circuit components. For example, the AC dynamic resistance of a diode
would be called r . If no active devices are present or if several items exist in the circuit, a simple numbering scheme is used, such
d

as R . In very complex circuits a specific name will be given to particularly important components, as in R
1 .
source

Voltages are normally given a two-letter subscript indicating the nodes at which it is measured. V is the DC potential from node
XY

X to node Y while v XY indicates the AC signal appearing across node X to node Y. A single-letter subscript, as in V , indicates a
X

potential relative to ground (in this case from node X to ground). The exceptions to this rule are power supplies, that are given a
double letter subscript indicating the connection point (V CCis the collector power supply), and particularly important potentials
that are directly named, as in v (AC input voltage) and V (DC voltage appearing across R ). If an equation for a specific
in R2 2

potential is valid for both the AC and DC equivalent circuits, the uppercase form is preferred (this makes things more consistent
with circuits that are directly coupled, and thus can amplify both AC and DC signals). Currents are named in a similar way but
generally use a single subscript referring to the measurement node (I is the DC current flowing through a conductor into or out of
X

node X). All other items are directly named. By using this scheme, you will always be able to determine whether the item
expressed in an equation is a DC or AC equivalent, its approximate circuit location, and other factors about it.

References
1
It is worth noting that the construction of an integrated circuit does not involve the creation and interconnection of millions or
billions of single discrete transistors. Instead, the manufacturing process builds all of the transistors simultaneously, rather like a
layer cake.

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1.2: Atomic Structure
In our effort to understand the operation of semiconductors, a fundamental question we might ask is “What is the internal structure
of an atom?” Please understand that it is nonsensical to ask what an atom might “look like” because its components are all smaller
than the shortest wavelengths of light that humans can see. Instead, we simply need a model to explain its observed behavior.

Figure 1.2.1: Planetary atomic model: Pretty, well-known and wrong. Image source (modified)
Perhaps the most prolific model in the popular imagination is the planetary model shown in Figure 1.2.1. In this model, the core, or
nucleus, is drawn at the center and contains positively charged protons and non-charged neutrons. Revolving around this core are
negatively charged electrons, each following a nice, regular, planar path much like a planet around the sun. Unfortunately for us,
this model is starkly incorrect, although it has found use as a symbol for nuclear regulatory agencies and a DEVO album cover
from the 1970s.
Before we come up with a more accurate and useful model, let's take a closer look at the sub-components; namely the proton,
neutron and electron. First off, most of the mass of any given atom is from the protons and neutrons. Protons and neutrons have
similar masses, about 1.67E−24 grams each. The mass of an electron is roughly 2000 times smaller. The radius of a proton is
approximately 0.87E−15 meters and the mean distance to the nearest electron is about 5.3E−11 meters. This means that this
electron is about 60,000 times farther away from the proton than the size of said proton. To put this into perspective, that's roughly
the same as the ratio between a golf ball and a sphere with a radius of 3/4ths of a mile or 1200 meters. This would be the case for a
hydrogen atom as it consists of a single proton and electron. The magnitude of this ratio is not much different for other substances,
including things like crystalline carbon (diamond) and quartz (a molecule of silicon and oxygen) that are very hard and solid. If you
think about that for a moment, you realize that the idea of “solidity” is in some ways an illusion because the vast majority of what
we call “something” is really just empty space. For example, chances are that you are sitting down while reading this. You probably
feel your buttocks pressed against the chair. Both of these things are considered solid yet at the atomic level the vast majority of
both items is nothingness. In reality, the feeling of solidity is just the result of the interaction of atomic forces between the two. So
if someone suggests that you might have a bit too much to spare in the department of the posterior, you can inform them that it's
really nothing.
One of the major issues with the planetary model is the idea that electrons whirl around the nucleus in stable, planet-like orbits.
That's simply not true. First, the electron inhabits a region of 3D space, it does not simply move through a plane. Second, due to the
Heisenberg Uncertainty Principle, we can't precisely plot the position and trajectory of a given electron. The best we can do is
make a plot of where the electron is likely to be. This is called a probability contour. Imagine that you could record the position of
an electron relative to the nucleus. A moment later you record its new position, a moment after that you record the next position,
and on and on for thousands of measurements. If you attempted to plot them all, you would wind up with a cloud of dots around the
nucleus. This cloud is referred to as an orbital. You wouldn't know how the electron got from one position to the next but you
would get a general idea of where it was likely to be. Do not confuse orbital with orbit (like a planetary orbit). They are two
different beasties.
There are several potential orbitals. Due to quantum physics, only certain orbitals are allowed. The permissible electron energy
levels are first grouped into shells, then subshells and finally orbitals. It is important to remember that orbitals indicate the
electron energy level. That is, a higher orbital implies a higher energy level. Further, orbitals fill in first from lowest energy level
to highest energy level. These are important ideas that we will leverage in future discussions.
Shells are denoted by their principal quantum number, n ; 1, 2, 3, etc. The higher the number, the more subshells it can contain.
Subshells are organized by their orbital shape and are designated by letters, the first four being s , p, d , and f . Shell 1 contains only
subshell s while shell 2 contains subshell types s and p. Shell 3 contains subshell types s , p and d , and so on.

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Thus, we see designations such as 1s, 2s and 2p. These subshells may also have variations within them. There is one variation on
s , three variations on p , five variations on d , etc. These variations are the orbitals and each orbital can hold a maximum of

two electrons.
Putting this all together, we find that the first shell can contain a maximum of two electrons: two in the single s subshell orbital (
1s). The second shell can contain a maximum of eight electrons: two in the s subshell (2s) plus two in each of the three p subshell

orbitals (2p). In like manner the third shell can contain a maximum of 18 electrons: two in 3s, six in 3p and two in each of the the
five d subshell orbitals (3d). You can condense this into a simple formula, 2n , where n is the shell number.
2

Figure 1.2.2: Electron probability contour for innermost orbital, 1s. Image source
Figure 1.2.2 shows the electron probability contour of the innermost orbital, namely 1s (i.e., principle quantum number 1, subshell
s ). As you can see, it is spherical in shape. The nucleus is located at the center, obscured here. All s orbitals are similarly

spherically shaped although the internals change. 1s is the lowest energy orbital.

Figure 1.2.3: Electron probability contour for orbital 2p. Image source
Orbitals are not limited to simple spherical shapes. Higher order orbitals can take on a variety of forms. Figure 1.2.3 shows the
electron probability contour for the 2p orbitals (recall there are three p variations, one each oriented along the X, Y and Z axes).
The nucleus is situated in the small void between the two lobes. Obviously, this is nothing like the well-behaved elliptical orbits of
planets around the sun. Probability contours can be very complex. For the highest orbitals, especially when combined with the
lower orbitals, the contour combinations can become reminiscent of the sculptures of a deranged clown forming herds of imaginary
balloon animals.
As interesting as these graphics are, they are cumbersome to work with. Consequently, a more functional graphic is called for. Such
a device is the Bohr model, named after Danish physicist Niels Bohr. An example is shown in Figure 1.2.4.

Figure 1.2.4: Generic Bohr model. Image source

It is important to understand that the Bohr model is an energy description of the atom, not an attempt to mimic its physical
appearance or structure. The nucleus is placed at the center. It is surrounded by concentric rings that represent the electron shells.
The higher the number, the larger the ring and the greater the energy level. If an electron were to move from a higher level to a
lower level, the energy difference is radiated out. This could be in the form of heat or light. This is a point worth remembering. For
example, this transition is what makes light emitting diodes (LEDs) function. The inverse is also possible, namely that by
absorbing energy, an electron can move into a higher orbital. This is an equally powerful concept, as we shall soon see.

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Using the Bohr model we can create diagrams to represent individual elements. For example, copper has an atomic number of 29
meaning that it has 29 protons and 29 electrons. The electron shell configuration is 2-8-18-1. That is, the first three shells are
completely filled and there is a single electron in the fourth shell. This single outer electron is only loosely bound and thus makes
copper a very good conductor. The Bohr model for copper would simply show four rings, the first three being filled and with a
single electron in the fourth ring.
Figure 1.2.5 shows the Bohr model of an atom of Silicon, atomic number 14, with an electron shell configuration of 2-8-4. In this
version, the individual electrons are drawn in each shell and the atomic number is indicated at the nucleus. Again, please do not
imagine this representing individual electrons orbiting the nucleus in lanes. This is an energy level depiction.

Figure 1.2.5: Bohr model of Silicon.

Often, it is useful to simplify this model further by omitting the filled inner shells. Also, the atomic number is replaced by the
number of electrons in the outermost, or valence, shell. This is shown in Figure 1.2.6. The valence shell is particularly important as
it gives insight into the general behavior of the material.

Figure 1.2.6: Simplified Bohr model of Silicon.

As an alternative, sometimes we will “straighten out” the Bohr model so that it simply shows the energy levels graphically as lines
or bands, and without counting specific electrons. This is depicted in Figure 1.2.7.

Figure 1.2.7: Energy level diagram.

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1.3: Crystals
We used silicon in the preceding example on purpose. The fact that it has a halffilled valence shell with four electrons puts it in a
special place. As is, it's neither a great conductor nor a superior insulator. With some attention to detail, it will become a
semiconductor. Silicon is not the only material that can be used for semiconductors. In fact, many of the earliest semiconductors
were made from germanium and currently we make semiconductors from other materials. Silicon, however, remains the source of
most semiconductors today.
It is possible for pure silicon to be arranged in a mono crystaline structure. That is, all of the silicon atoms align in a very specific,
well-ordered manner, without any voids or breaks in the pattern. As silicon has only four electrons in its valence shell, four more
electrons would be needed to fill the shell. In the crystal, any given atom of silicon effectively “shares” an electron from its four
closest neighbors through a covalent bond (meaning “with or among the valence”). Each atom does this, therefore each atom is
tightly bound to its neighbors. This is illustrated in Figure 1.3.1 using simplified Bohr models. Note the color coding that indicates
the sharing.

Figure 1.3.1: Silicon crystal covalent bonding.

Remember, this is an energy diagram. We are not trying to indicate that individual valence electrons are zipping between atoms in
figure eight patterns. Indeed, this diagram is drawn flat whereas a real crystal is not a simple sheet, but is three dimensional with
varying thickness.
While it would be a practical impossibility to draw a highly realistic representation of atoms in the crystal, given a few liberties we
can draw something that at least comes a little closer to reality. We start by representing each silicon atom as a ball and the covalent
bond as a connecting tube. Recalling that each atom must be bound to four others in a regular, equal pattern, we come up with the
drawing of Figure 1.3.2. Notice that the overall structure is essentially that of a cube. Further, at the center of each face of the cube
there exists an atom of silicon. Therefore, we say that the crystal structure is face centered cubic.

Figure 1.3.2: Representation of silicon crystal structure. Image source

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An interesting thing happens in the crystal when we examine the energy levels. With a single atom we would expect to see an
energy diagram like that of Figure 1.2.7. That is, discrete, permissible steps. Within a crystal, though, each atom is affected by
those around it. This causes slight changes in the energy levels. Taken as a whole, all of these individual variations cause the
discrete levels to blur into broader bands. If we were to examine the valence and conduction energy levels, instead of discrete, thin
lines we'd see the thicker bands as illustrated in Figure 1.3.3. These bands still represent permissible electron energy levels, it's just
that now there is a continuum rather than a discrete level. There will still be non-permissible or forbidden zones between these
regions. A forbidden zone is referred to as a band gap.
Associated with this idea is the concept of the Fermi level, named after physicist Enrico Fermi. Basically, the Fermi level is the
energy level in a given material at which there is a 50% probability that it is filled with electrons. In other words, levels below this
value tend to be filled with electrons and levels above tend to be empty. If the Fermi level lies within a band, the material will be
good a conductor. On the other hand, if the Fermi level lies between two widely separated bands, the material will be a good
insulator. If the Fermi level is between bands that are relatively close, the material is a semiconductor.

Figure 1.3.3: Energy diagram for an intrinsic semiconductor.

Figure 1.3.3 shows the energy bands for an intrinsic semiconductor, such as an ideal silicon crystal. The term intrinsic simply
means that there are no impurities in the crystal. Between the valence band and conduction band is an impermissible or forbidden
region. This is a band gap. In practical terms you can think of the band gap as the amount of energy that needs to be applied to an
electron in order to move it from the valence band to the conduction band. The value of the band gap will depend on a variety of
factors, the precise material being used for the semiconductor is of particular importance.
Without any external energy applied (i.e., isolated and at absolute zero), the crystal lattice is stable and there is no electron
movement through the crystal. As we add thermal energy, it is possible for valence electrons to jump up to the conduction band. At
this point, the electron can “wander” through the crystal in the manner depicted in Figure 1.3.4.

Figure 1.3.4: Electron movement in a crystal

Figure 1.3.5: Electron versus hole flow.

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Here is how this happens: Because the thermal energy causes the electron to jump to the higher energy level of the conduction
band, it leaves behind a “hole”, that is, a place devoid of an electron. Now that the hole exists, it provides a place for another
electron to “fall into”. The higher the temperature, the greater the number of freed electrons and the greater the number of
corresponding holes. We now have thermally-induced electron movement. We can also look at this from the opposing perspective,
namely that we have an equal magnitude but opposite direction “hole flow”. If you find this idea hard to grasp, simply look at
Figure 1.3.5. Each horizontal bar contains four dots representing electrons. In the topmost bar there is an empty space (a hole) to
the extreme left. When the leftmost electron moves into this hole it fills it in a process called electron-hole recombination, which of
course, sounds much more impressive than it really is. The result is the second bar. We repeat this process of moving an electron
right to left as we traverse down the diagram. Eventually we end up with the four electrons packed together toward the left. Finally,
instead of focusing on the dots, focus instead on the negative space (the empty white bit). Moving from top to bottom, the hole
moves left to right, in the opposing direction.
Just as we think of the movement of electrons as a movement of negative charge, then the movement of holes can be thought of as
a movement of positive charge. We can say that the electron is the carrier of negative charge while the hole is the carrier of positive
charge.
Before moving on to the next section, it is important to remember that in an intrinsic (pure) semiconductor, the number of thermally
produced electrons and holes will be equal. Also, even at room temperature the total number will also be quite small compared to
the number of electrons in the crystal.

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1.4: Doped Materials
By themselves, intrinsic semiconductors are not of particular use. They are neither good conductors nor insulators, and their
conduction is largely dependent on temperature. We can alter the properties of the material by introducing foreign substances or
impurities into the crystal. These impurities are also known as dopants. A crystal with an added dopant is referred to as an extrinsic
semiconductor or doped material. The amount of impurity added is generally small, perhaps in the neighborhood of one part per
million. The dopant may be added through a gaseous diffusion process where the crystal is heated in an oven and the dopant added
in gaseous form. Over a period of time the impurities will diffuse or “seep into” the target crystal. An alternate approach is ion
implantation. In this method the impurities are accelerated and quite literally smash into the target, dislodging and replacing some
of the original atoms in the crystal.
There are two different types of semiconductors possible. One is called N-type material, and the other, P-type material.
Unsurprisingly, the N stands for Negative and the P stands for (you guessed it) Positive. N-type material is created by adding
pentavalent impurities, that is, a dopant with five electrons in its outer shell. Examples include phosphorus, arsenic and antimony.
In contrast, P-type material is created by adding a trivalent impurity, one with three electrons in its outer shell. Possible trivalent
impurities include boron, gallium and indium.

1.4.1: N-Type Material

Figure 1.4.1 shows a model of a silicon crystal with a pentavalent impurity at its center. Compared to an ordinary silicon atom that
would have four electrons in its outer shell, the pentavalent impurity creates an extra, or donor, electron. Thus, the crystal has a net
negative charge and is referred to as N-type material. The energy level of the donor electrons is just below the bottom of the
conduction band. In other words, the difference between the donor level and the bottom of the conduction band is much, much
smaller than the band gap itself. Therefore it is relatively easy for these donor electrons to jump into the conduction band,
becoming free ionized electrons and leaving behind ionized holes1.

Figure 1.4.1: Crystal with added pentavalent impurity (N-type).

Compared to the undoped intrinsic crystal, the doped extrinsic crystal exhibits a relatively high number of free electrons. As you
might surmise, this enhances the conductivity of the material, and the greater the doping level, the greater the enhancement. Earlier
it was mentioned that both electrons and holes can serve as charge carriers. Because the number of free electrons is significantly
larger than the number of holes in N-type material, electrons in N-type material are referred to as the majority charge carrier (or
more simply, the majority carrier) while holes are referred to as the minority charge carrier (or minority carrier).
The extra electrons add to the number of filled energy states and, being of higher energy than the valence electrons, push the Fermi
level to a higher value. Remember, the Fermi level represents the point where 50% of states would be filled, so if we add states
above this, then the new 50% point must be higher than the former level. This is illustrated in Figure 1.4.2. Note how close the
donor level is to the conduction band and that the Fermi level has been pushed up, away from the valence band and closer to the
conduction band. This will be of great significance in up-coming discussions on semiconductor devices.

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 Figure 1.4.2: Energy band diagram of N-type semiconductor.

1.4.2: P-Type Material

In a similar manner, if we introduce a trivalent impurity, our crystal model now features a hole; a location where an electron is
lacking. For this reason, trivalent impurities are sometimes called acceptors. The resulting crystal model is illustrated in Figure
1.4.3.

Figure 1.4.3: Crystal with added trivalent impurity (P-type).

The resulting situation is essentially the reverse of that of the N-type material. Figure 1.4.4 shows the energy band diagram for our
new P-type material. In this case, the Fermi level has been pushed down, closer to the valence band.

Figure 1.4.4: Energy band diagram of Ptype semiconductor.

In P-type material, holes out number free electrons. Consequently, holes are referred to as the majority carrier in P material while
electrons take on the role of minority charge carrier.
As with N-type material, the greater the amount of trivalent impurity added, the greater the overall effect. By itself, a doped crystal
can be used to create a resistor. The resistivity of the material is a function of the doping level. By setting the cross-sectional area,
length and doping level, we can create well-defined resistor values. If this was all we could do with semiconductors then we could
say two things: first, the solid state semiconductor revolution would not exist; and second, this text would be very short. The
interesting bits arrive when we combine both N- and P-type materials into a single device, as we shall begin to see in the next
chapter.

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References
1
An ion is an atom or molecule that does not have a neutral net charge, i.e., the numbers of protons and electrons are not equal. If it
loses electrons, resulting in a net positive charge, it is called a cation. If it gains electrons resulting in a net negative charge it is
called an anion.

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1.5: Summary
In this chapter we have examined the basic structure of atoms. This includes the concept of electron shells and permissible energy
states. We have used both the Bohr model of the atom and the corresponding energy band diagrams.
Crystals such as silicon show a very ordered three dimensional structure that relies on strong covalent bonds. The crystal tends to
“fuzz” or broaden the permissible energy levels into thicker energy bands. Further, the crystal exhibits a modest energy gap, or
band gap, between the valence band and conduction band. This gap is much smaller than the gap seen in insulators, and therefore
the material is referred to as a semiconductor, being somewhere between a true conductor and a true insulator.
The electrical characteristics of a pure, or intrinsic, semiconductor crystal can be altered by adding impurities or dopants. A doped
crystal is referred to as an extrinsic crystal. If a pentavalent dopant is added, there will be a surplus of electrons and a raising of the
Fermi level. The new crystal is called N-type material. In contrast, if a trivalent dopant is added, there will be a surplus of holes and
a lowering of the Fermi level. The new crystal is called P-type material. In N-type material, electrons are the majority charge
carrier and holes are the minority charge carrier. In P-type material, holes are the majority carrier while electrons serve as the
minority carrier.

1.5.1: Review Questions

1. Describe the differences between a conductor, an insulator and a semiconductor.
2. Define the terms Fermi level, valence band, conduction band and band gap.
3. What is the fundamental difference between an intrinsic crystal and an extrinsic crystal?
4. What is meant by the term doping?
5. What is the effect of donor and acceptor impurities on the Fermi level?

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 CHAPTER OVERVIEW

2: PN Junctions and Diodes

Learning Objectives
After completing this chapter, you should be able to:
Describe and diagram the energy hill for a PN junction.
Discuss the different kinds of diodes available and their uses: rectifier, Zener, LED, photodiode and varactor.
Detail the device characteristics exhibited by different diode types.
Graph the forward- and reverse-bias operation regions of diodes.
Determine the effective resistance of a diode under specific conditions.
Solve basic DC resistor-diode circuits for various system voltages and currents.

2.1: Introduction
2.2: The PN Junction
2.3: Diode Data Sheet Interpretation
2.4: Diode Circuit Models
2.5: Other Types of Diodes
2.6: Summary
2.7: Exercises
2.8: An Alternate Hypothesis Regarding PN Junctions

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1
2.1: Introduction
Having investigated the characteristics of extrinsic N-type and P-type materials in the prior chapter, we shall continue by
examining what happens when the these two materials are combined into a single device. It is critical to understand that when we
combine P- and N-type materials, we do not do so through simple mechanical means. That is, we do not in some way solder, weld,
bolt, friction-fit, glue or duct tape1 one type of material to another. Rather, we must maintain a single piece of mono-crystalline
silicon, not a poly-crystalline amalgam of individual pieces. This can be achieved via a diffusion or ion implantation technique that
is applied repeatedly to a single piece of silicon crystal. This will leave regions or zones in the crystal that are N-type or Ptype. In
fact, it is quite possible to have a region of one type completely embedded within a region of the opposite type as we shall see in
later chapters.
By creating a single zone of N material adjacent to a zone of P material, we wind up with the PN junction. The PN junction is
arguably the fundamental building block of solid state semiconductor devices. PN junctions can be found in a variety of devices
including bipolar junction transistors (BJTs) and junction field effect transistors (JFETs). The most basic device built from the PN
junction is the diode. Diodes are designed for a wide variety of uses including rectifying, lighting (LEDs) and photodetection
(photodiodes). We shall begin by examining the basic structure and operation of the PN junction. This will include a look at the
many different kinds of diodes available. To assist with circuit analysis, a series of simplified models will be created and
investigated. We shall use these models to solve a number of example circuits that feature the many diode variations available.

References
1
They say it has 1001 uses but this ain't one of them.

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2.2: The PN Junction
If we were to create a region of N material abutting a region of P material in a single crystal, an interesting situation occurs.
Assuming the crystal is not at absolute zero, the thermal energy in the system will cause some of the free electrons in the N
material to “fall” into the excess holes of the adjoining P material. This will create a region that is devoid of charge carriers
(remember, electrons are the majority charge carrier in N material while holes are the majority charge carrier in P material). In
other words, the area where the N and P materials abut is depleted of available electrons and holes, and thus we refer to it as a
depletion region. This is depicted in Figure 2.2.1. The excess electrons of the N material are denoted by minus signs while the
excess holes of the P material are denoted with plus signs. At the interface, the free electrons have recombined with holes. When an
electron recombines, it leaves behind a positive ion in the N material (shown here as a circled plus sign) and produces a negative
ion in the P material (shown as a circled minus sign).

Figure 2.2.1: PN junction.

We now have a region depleted of charge carriers and this will have an effect on the ability to establish a flow of current through
the device. We have, in essence, created an energy hill that will need to be overcome.
To understand the concept of the energy hill, recall that in the prior chapter it was discovered that doping an intrinsic crystal would
shift the Fermi level. For N material, the Fermi level is shifted up, toward the conduction band. In contrast, for P material the Fermi
level is shifted down, nearer to the valence band. When two dissimilar regions adjoin, as in the case here, the energy bands will
adjust so that the Fermi levels are consistent. Effectively, this causes the bands of the P material to rise relative to the bands of the
N material. The interface between the two appears as a hill, and this is the aforementioned depletion region. This situation is
depicted graphically in Figure 2.2.2. Compare this energy diagram to the energy diagrams for N material and P material presented
in the prior chapter. By simply aligning the Fermi levels, it should be clear how we arrive at the new energy diagram.

Figure 2.2.2: Energy bands in PN junction.

Now let's consider what happens if we were to connect this device to an external voltage source as shown in Figure 2.2.3.
Obviously, there are two ways to orient the PN junction with respect to the voltage source. This version is termed forward-bias.

Figure 2.2.3: PN junction connected to external voltage source.

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2.2.1: Forward-Bias
The dotted line of Figure 2.2.3 shows the direction of electron flow (opposite the direction of conventional flow). First, electrons
flow from the negative terminal of the battery toward the N material. In N material, the majority carriers are electrons and it is easy
for these electrons to move through the N material. Upon entering the depletion region, if the supplied potential is high enough, the
electrons can diffuse into the P material where there are a large number of lower energy holes. From here, the electrons can migrate
through to the positive terminal of the source, completing the circuit (the resistor has been added to limit maximum current flow).
The “trick” here is to assure that the supplied potential is large enough to overcome the effect of the depletion region. That is, a
certain voltage will be dropped across the depletion region in order to achieve current flow. This required potential is called the
barrier potential or forward voltage drop. The precise value depends on the material used. For silicon devices the barrier potential is
usually estimated at around 0.7 volts. For germanium devices it is closer to 0.3 volts while LEDs may exhibit barrier potentials in
the vicinity of 1.5 to 3 volts, partly depending on the color.
Another way of thinking about this is that the addition of the voltage source “flattens” the inherent energy hill of the junction. Once
the applied forward-bias voltage is at least as big as the hill, current can flow easily.

2.2.2: Reverse-Bias
If the voltage source polarity is reversed in Figure 2.2.3, the behavior of the PN junction is altered radically. In this case, the
electrons in the N material will be drawn toward the positive terminal of the source while the P material holes will be drawn toward
the negative terminal, creating a small, short-lived current. This has the effect of widening the depletion region and once it reaches
the supplied potential, the flow of current ceases. In essence, we have increased the size of the energy hill. Further increases in the
source voltage only serve to make the situation worse. The depletion region simply expands to fill the void, so to speak. Ideally, the
PN junction acts like an open circuit with an applied reverse-bias voltage.
This asymmetry in response to a supplied potential turns out to be extraordinarily useful. Perhaps the simplest of all semiconductor
devices is the diode. In its basic form a diode is just a PN junction. It is a device that will allow current to pass easily in one
direction but prevent current flow in the opposite direction.

2.2.3: Shockley Equation

We can quantify the behavior of the PN junction through the use of an equation derived by William Shockley.
V q
D

I = IS ( e nkT
− 1) (2.2.1)

Where
I is the diode current,
IS is the reverse saturation current,
VD is the voltage across the diode,
q is the charge on an electron, 1.6E−19 coulombs,
n is the quality factor (typically between 1 and 2),
k is the Boltzmann constant, 1.38E−23 joules/kelvin,
T is the temperature in kelvin.
At 300 kelvin, q/kT is approximately 38.6. Consequently, for even very small forward (positive) voltages, the “−1” term can be
ignored. Also, I is not a constant. It increases with temperature, approximately doubling for each 10 C° rise (more on this in a
S

moment).
If we plot the Shockley equation using typical values for a silicon device, we arrive at the curve shown in Figure 2.2.4. This plots
the junction current as a function of the forward (positive) device voltage. It is a representative curve only. While all silicon diodes
will exhibit this same general shape, the precise value of current for a specific voltage will vary depending on the device design.

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 Figure 2.2.4: Characteristic curve of forward-biased silicon PN junction.
For potentials below about 0.5 volts, the current is virtually non-existent. Above this value, the current rises rapidly, becoming
nearly vertical after approximately 0.7 volts. If the plot was recreated using a higher temperature, the effect would be to shift the
curve to the left (i.e., a higher current for a given voltage).
If we were to alter the graph to use a logarithmic current scale rather than a linear scale, the graph of Figure 2.2.5 results. The
resulting straight line plot shows clearly the logarithmic relationship between the diode's voltage and current.

Figure 2.2.5: Characteristic curve of forward-biased silicon PN junction using log scale.
For negative voltages (reverse-bias) the Shockley equation predicts negligible diode current. This is true up to a point. The equation
does not model the effects of breakdown. When the reverse voltage is large enough, the diode will start to conduct. This is shown
in Figure 2.2.6. In the first quadrant we see the same general shape we found in Figure 2.2.4. V is the forward “knee” voltage
F

(roughly 0.7 volts for silicon). I is the reverse saturation current (ideally zero but in reality a very small amount of current will
R

flow). V is the reverse breakdown voltage. Note that the current increases rapidly once this reverse voltage is reached.
R

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 Figure 2.2.6: Simplified forward and reverse I-V curve for diode.
In general, diodes should not be operated in the breakdown region (the exception being Zener diodes). There are two mechanisms
behind this phenomenon. The Zener effect, named after Clarence Zener, predominates when the doping levels are high and
produces breakdown voltages below roughly five or six volts. It is due to the production of a very high electric field across the
depletion region which then results in the production of a high current through electron tunneling. In devices using lower levels of
doping, avalanche dominates. In this instance, a high electric field accelerates the free electrons to the point where they can impact
surrounding atoms and create new electron-hole pairs, thus creating new free electrons that can repeat the process, resulting in a
rapid increase of current.

Figure 2.2.7: Diode schematic symbol (ANSI).

Figure 2.2.8: Alternate diode schematic symbol (IEC).

The schematic symbol for a basic switching or rectifying diode is shown in Figure 2.2.7. This is the ANSI standard which
predominates in North America. The P material is the anode while the N material is the cathode1. As a general rule for
semiconductor schematic symbols, arrows point toward N material. In this case, the arrow also points in the direction of easy
conventional current flow. Figure 2.2.8 shows an alternate schematic symbol, the IEC international standard, the difference being
that it is in outline form without the body being filled in.

Figure 2.2.9: DO-204 case.

Figure 2.2.10: DO-4 case. Courtesy of Vishay Intertechnology, Inc.

When it comes to physical device packaging, small and medium current and power devices for through-hole mounting include the
DO-35 and DO-204, with the model number stamped on the body. The typical size is comparable to a 1/4 to 1/8 watt resistor. As
seen in Figure 2.2.9 the cathode end is denoted by a band, reminiscent of the bar on the schematic symbol. Surface mount packages
are also available. Devices handling higher currents and powers often come in stud or bolt styles such as the DO-4 shown in Figure
2.2.10. These packages facilitate mounting to a metal plate or heat sink to help dissipate the excess heat.

References
1Cathode is often denoted by a k . This is likely due to the word's Greek root, kathodos.

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2.3: Diode Data Sheet Interpretation
A data sheet for the popular 1N4148 switching diode is shown in Figure 2.3.1. The 1N4148 is designed for high speed operation
required in high frequency signal applications but also finds use in a variety of general purpose applications that do not require very
high current or power handling.
Some of the key features include a four nanosecond switching speed, a maximum reverse voltage of 100 volts and a 450 milliamp
maximum forward current (with short single pulses as high as four amps being possible). Power dissipation is 500 milliwatts.
Referring to Figure 2.3.1b, the variation in reverse current with regard to temperature is obvious. This also verifies the “doubles
every 10 C ” rule-of-thumb.
∘

Figure 2.3.1a: 1N4148 data sheet. Courtesy of NXP Semiconductors.

Figure 2.3.1b: 1N4148 data sheet (continued).

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Figure 2.3.1c: 1N4148 data sheet (continued).

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 Figure 2.3.1d: 1N4148 data sheet (continued).
Power derating and permissible pulse amplitudes can be seen in Figure 2.3.1d. Finally, note the variation in the forward voltage
curves due to temperature. As stated previously, for a given current, an increase in temperature results in a lower forward voltage.
Also, at room temperature, we see a knee voltage of approximately 0.7 volts.

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2.4: Diode Circuit Models
One thing is very clear from the characteristic curve of the diode: It is not a linear bilateral1 device, quite unlike a resistor.
Consequently, we cannot use the superposition technique to solve diode circuits unless we have a priori knowledge about it, that is,
whether or not it is forward- or reverse-biased. For example, we can imagine a circuit comprised of two voltage sources, resistors
and a diode. By itself, one of the voltage sources might forward-bias the diode while the other would reverse-bias it. Obviously, a
diode cannot be both forward and reverse-biased at the same time.
A second problem we face with circuit analysis is the added complexity of the Shockley equation. For speed and ease of
computation we find it useful to model the diode with simpler circuit elements. Three diode models are shown in Figure 2.4.1.

Figure 2.4.1: Simplified diode models. Top to bottom: first, second and third approximations, increasing in accuracy.
The first approximation is the simplest of the three. It treats the diode as a simple dependent switch: the switch is closed if the
diode is forward-biased and open if it is reverse-biased. The second approximation adds the effect of the forward voltage. V kneeis
the “turn-on” potential required to overcome the energy hill. It would be 0.7 volts for a silicon device. The third approximation is
the most accurate of the three. A close look at the characteristic curve of Figure 2.2.4 shows that once the knee voltage is reached,
the curve does not transition to a perfect vertical line. Instead, there remains some positive, non-infinite slope. That is, the voltage
continues to increase, although modestly, with further increases in current. We can approximate this effect as a small resistive
value, R . The three corresponding I-V plots are shown in Figure 2.4.2. Compare these to Figure 2.2.6 and note the increasing
bulk

accuracy.

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 Figure 2.4.2: I-V curves for simplified diode models. Top to bottom: first, second and third approximations.
In many applications the second approximation will yield sufficiently accurate results and we will tend to make greatest use of it.
Just remember that these are behavioral models; don't think that there are literally 0.7 volt sources or little resistors in the diodes.
It should be noted that R does not represent the “diode resistance” per se, rather, it models a minimum value. There really is no
bulk

such thing as a singular diode resistance. We can, however, talk about the effective resistance of a diode in a particular circuit in
both DC and AC terms.
The key to understanding this concept is to remember that resistance is a linear function, a straight line on a I-V graph. Therefore,
we need to find a straight line “fit” for the diode curve. Two possibilities are shown in Figure 2.4.3.

Figure 2.4.3: Diode effective resistance for DC and AC.

The red curve is the diode's characteristic curve (arbitrary current values are shown). For some particular DC circuit, a specific
current will flow through the diode which will produce a particular voltage, denoted on the graph as the operating point. If we
simply compute the ratio of that voltage to the driving current, we wind up with a resistance. This is the effective DC resistance of
the diode under these circuit conditions and is represented by the blue line. That is, the reciprocal of the slope of the blue line is the
effective DC resistance. Obviously, if we shift the operating point along the red diode curve, the slope of the intersecting blue line
changes and therefore we arrive at a new DC resistance. The higher the current, the lower the effective DC resistance.
Instead of just DC, the diode might see a combination of DC and AC signals. Visualize this as adding a small AC variation on top
of the DC. We can imagine the operating point moving along the red diode curve, back and forth about the operating point. If we
divide the small AC voltage variation by its associated AC current variation, we wind up with the AC equivalent resistance, also
known as the dynamic resistance. Graphically, we can think of this as finding the slope of a line that is tangent to the operating
point (the purple line). This will in fact, be an average value across the AC variation. It should also be apparent that the effective
AC resistance must be smaller than its DC counterpart because the AC approximation (purple line) must be steeper than the DC
approximation (blue line)2. It is time for a few illustrative examples.

Example 2.4.1

Consider the resistor-diode circuit of Figure 2.4.4. Assume the voltage source is 12 volts and the resistor is 2 kΩ. Further,
assume the diode is silicon and its bulk resistance is 10 Ω. Using the three diode approximations, compute the circulating
current.

Figure 2.4.4: Schematic for Example 2.4.1.

First, note that the diode is forward-biased. This must be the case because there is a single voltage that is larger than the knee
voltage and its positive terminal is attached to the diode's anode. No matter which approximation we use, Kirchhoff's voltage
law (KVL) must be true so it will be a matter of summing the available voltage drops versus resistance(s).

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Using the first approximation:
Here we assume the diode is a closed switch. Consequently all of the source voltage must drop across the single resistor.
E
I =
R

12V
I =
2kΩ

I = 6mA

Using the second approximation:

In this instance we include the knee voltage.
E − Vknee
I =
R

12V − 0.7V
I =
2kΩ

I = 5.65mA

Using the third approximation:

The most accurate of the three, we include both the knee voltage and bulk resistance.
E − Vknee
I =
R + Rbulk

12V − 0.7V
I =
2kΩ + 10Ω

I = 5.622mA

In this particular case the difference between the second and third approximations is less than 1%. It is also worth noting that
the third approximation predicts a diode voltage of slightly more than 0.7 volts (approximately 0.756 volts) due to the
additional potential across the bulk resistance.

Example 2.4.2

Determine the circulating current for the circuit in Figure 2.4.5. Also find the diode and resistor voltages. Assume the power
supply is 20 volts, the diode is silicon and the resistor is 2 kΩ.

Figure 2.4.5: Schematic for Example 2.4.2.

This problem is deceptively easy. Note that the positive terminal of the source is connected to the cathode. As there are no
other sources in the circuit, the diode must be reverse-biased. The model for a reverse-biased diode is an open switch and the
circulating current in an open circuit is zero. Therefore, the resistor voltage must also be zero and values for the knee voltage
and bulk resistance are not needed. In order to satisfy KVL, the diode voltage will equal the source of 20 volts (+ to − from
cathode to anode).
The only time this would not be the case is if the reverse breakdown voltage of the diode is less than the 20 volt source. In that
case the diode voltage would equal the breakdown voltage with the remainder of the source voltage dropping across the
resistor.

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 Example 2.4.3

Determine the circulating current for the circuit in Figure 2.4.6. Also find the diode and resistor voltages. Assume the power
supply is 9 volts, the diodes are silicon and R = 1 kΩ, R = 2 kΩ.
1 2

Figure 2.4.6: Schematic for Example 2.4.3.

According to KVL, the applied source must equal the sum of the voltage drops across the resistors and diodes as this is a single
loop. Both diodes are forward-biased (conventional current entering the anodes).
E − Vknee1 − Vknee2
I =
R1 + R2

9V − 0.7V − 0.7V
I =
1kΩ + 2kΩ

I = 2.533mA

Note that if either diode was reversed, there would be no current flow and all of the source potential would drop across the
reversed diode.

Example 2.4.4

Determine the source current and resistor voltages for the circuit in Figure 2.4.7. Also find the resistor voltages if the diode
polarity is reversed. Assume the power supply is 10 volts, the diode is silicon and the resistors are 1 kΩ each.

Figure 2.4.7: Schematic for Example 2.4.4.

As D and R are in parallel they must have the same voltage drop. Also, the diode is forward-biased. Therefore, the voltage
2

across R must be approximately 0.7 volts, leaving 9.3 volts to drop across R . The current through R is the source current.
2 1 1

E − VD
I =
R1

10V − 0.7V
I =
1kΩ

I = 9.3mA

If the diode is reversed it behaves as an open switch. The circuit reduces to a simple 1:1 voltage divider, each resistor dropping
half of the supply, or 5 volts each.

Computer Simulation
To verify our results, Example 2.4.4 is simulated. The circuit is captured as shown in Figure 2.4.8a. This particular example is
shown in Multisim although any decent quality simulator will do. The very common 1N4148 switching diode is used here. Another
popular choice would be the 1N914 switching diode or a 1N400X series rectifier.

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 Figure 2.4.8a: The circuit of Example 2.4.4 in Multisim.
Next, a DC Operating Point analysis is performed. The results are shown in Figure 2.4.8b. Note that the diode potential is just
under the 0.7 volt approximation. From this we can deduce that the voltage drop across the first resistor must be slightly more than
9.3 volts, producing a current slightly more than 9.3 mA.

Figure 2.4.8b: DC Operating Point simulation results for the circuit of Example 2.4.4.
Finally, Figure 2.4.8c shows the results when the diode is reversed in the circuit. The second resistor (node 3 to ground) shows 5
volts as expected. Therefore, the first resistor must also be dropping 5 volts.

Figure 2.4.8c: Simulation of Example 2.4.4 using reversed diode orientation.

Before moving on to another topic, let's take a look at a somewhat more involved example using multiple diodes.

Example 2.4.5

Determine the diode and resistor voltages for the circuit in Figure 2.4.9. Assume the diodes are silicon.

Figure 2.4.9: Schematic for Example 2.4.5.

The first thing to notice is that D is forward-biased while D is reverse-biased. Therefore, the 20 volt source must equal the
1 2

drop across D and the two resistors. D will take on whatever the drop across the 2 kΩ works out to as they are in parallel.
1 2

E − VD1
I =
R1 + R2

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 20V − 0.7V
I =
1kΩ + 2kΩ

I = 6.433mA

Note that virtually no current flows down through D as it is reverse-biased. Using Ohm's law, the drop across the first resistor
2

is 6.433 volts and for the second resistor, 12.867 volts.

References
1
The I-V plot is not a straight line (linear) and the forward and reverse quadrants are not identical (bilateral).
2
The dynamic resistance of a PN junction may be approximated as 26 mV/I junction . This will be shown in an upcoming chapter.

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2.5: Other Types of Diodes
Diodes have been designed to exploit different aspects of PN junctions. Besides the basic use as a switching or rectifying device,
diodes are available for voltage regulation, variable capacitance, illumination and light sensing. The schematic symbols for a
number of popular diode types are shown in Figure 2.5.1. Note the similarities of the symbols. The “bar” portion represents the
cathode for all of them.

Figure 2.5.1: Diode schematic symbols: a) switching or rectifying b) Zener c) Schottky d) varactor e) LED f) photodiode

2.5.1: Zener Diode

The Zener diode behaves like an ordinary signal diode when forward-biased. Normally, though, Zeners are used in a reverse-bias
condition. From our previous discussion, recall that if the reverse potential is high enough, a diode can go into breakdown, causing
a rapid increase current. This was caused by either of two effects, Zener conduction or avalanche. The Zener diode takes advantage
of this in order to produce a stable voltage1. Zeners are specified by their reverse potential (generically referred to as the “Zener
voltage”) and are designed to handle larger currents and powers than the average signal diode. Zener voltages are standardized in
much the same manner as resistors so values such as 3.9 volts, 5.1 volts and 6.8 volts are to be expected. The Zener voltage is
measured at I , the Zener test current. A lower current may not fully push the diode into conduction resulting in a lower than
ZT

expected diode potential.

Figure 2.5.2: Zener diode schematic symbol.

Instead of modeling the Zener as an open switch when reverse-biased, instead we model it as an open when its voltage is less than
the rated voltage, and as a voltage source equal to the rated value if its voltage tries to exceed that value. When analyzing Zener-
based circuits, the first thing to do is determine if the diode is forward-biased. If it is then treat it like an ordinary switching diode.
If, on the other hand, it is reverse-biased then treat it like an open switch. If the resulting diode voltage is greater than the Zener
voltage then recompute the circuit but this time mentally replace the Zener with a voltage source equal to the Zener voltage. Our
next example will illustrate this method.

Example 2.5.1

Determine the circulating current for the circuit in Figure 2.5.3. Also find the diode and resistor voltages. Assume the power
supply is 9 volts, the Zener voltage is 5.1 volts and the resistor is 3.3 kΩ.

Figure 2.5.3: Schematic for Example 2.5.1.

The diode is reverse-biased. If we treat it as an open then it would drop the entire source voltage, or 9 volts. This is greater than
the Zener potential so the device must be in Zener conduction. This means that conventional current will flow relatively easily
in a clockwise direction. The voltage across the diode will equal the rated value of 5.1 volts, + to − from cathode to anode. By
KVL the resistor drop must be 9 V − 5.1 V, or 3.9 volts.

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 E − VZener
I =
R

9V − 5.1V
I =
3.3kΩ

I = 1.182mA

If the diode was flipped in orientation then it would be forward-biased and show the expected 0.7 volts with 8.3 volts across
the resistor.

Computer Simulation
A Zener diode circuit is simulated as shown in Figure 2.5.4.

Figure 2.5.4: Zener diode circuit simulation.

Without the Zener, the two resistors would simply split the supply voltage equally, each receiving 5 volts. If an ordinary diode was
used it would be reverse-biased and act as an open. The resulting voltages would be the same. In this case, however, the Zener is
activated at 3.6 volts (it is typical to include the Zener voltage as part of the model number with the letter “V” replacing the
decimal point when needed). Therefore we see roughly 3.6 volts across the Zener and the parallel second resistor (node 3 to
ground). The precise value of voltage will depend on the magnitude of the diode current. If the simulation is rerun with a higher
voltage source, the increased current will produce a slightly higher voltage at node 3. This is because the breakdown curve is not
infinitely steep once it goes past the rated Zener voltage. The effect is similar to that of R in a forward-biased diode. On a data
bulk

sheet this value is referred to as the differential resistance, or R .

dif

An excellent use of the Zener is to limit or regulate a voltage. When a Zener is placed in parallel with other components we can
ensure that those components will not see a potential higher than the rated Zener voltage. We will take a much closer look at this in
the next chapter.

2.5.2: Light Emitting Diode (LED) and Photodiode

The light emitting diode (LED) and photodiode are complements. While the LED produces light with an electrical input, the
photodiode produces a current when exposed to light. Both devices can operate within the human visible spectrum and can also be
designed to operate at wavelengths outside this range, in the infrared (IR) and ultraviolet (UV). In fact, most TV remote controls
rely on IR emitter/detector pairs for communication2.

Figure 2.5.5: Light emitting diode (LED) schematic symbol.

The LED has displaced traditional incandescent (filament-based) light sources in many applications due to its high efficiency in
turning an electrical energy input into a light output. They are small, physically robust, operate relatively cool and are available in a
number of different colors. The schematic symbol is shown in Figure 2.5.5. The basic idea behind its operation is fairly simple. In
a forward-biased PN junction, when free electrons recombine and “fall” into lower energy valence holes they must give up this
energy differential in some manner. In most diodes, this energy is emitted as heat. In LEDs, the energy transition is designed such
that it is radiated at shorter wavelengths (i.e., visible light). In order to achieve this, LEDs are not formed just using silicon as in a
typical switching diode. Instead, somewhat more exotic materials are used. From an analysis or design standpoint, the important
thing to remember is that the forward voltage tends to be noticeably higher than silicon's 0.7 volt drop. The precise value will

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depend on the material, which in turn effects the color. A generic red LED will likely exhibit a forward drop of around 1.8 volts or
so. Other colors tend to be somewhat higher as we move through the rainbow, ending with blue and UV LEDs (and also high
brightness versions) up around 3 to 4 volts. In a lab it is easy to determine the approximate forward drop of a given diode by
connecting it in series with a voltage source and current limiting resistor. The supply is increased until the desired brightness is
achieved and then the diode drop can be measured with a DMM. When reverse-biased the LED behaves like a switching diode, that
is, it looks like an open switch. Unlike switching and rectifying diodes, LED maximum reverse potentials tend to be relatively low,
perhaps just a few volts.
A datasheet for the Cree C566D series LED is presented in Figure 2.5.6. Notice that the colors are specified in terms of wavelength
(in nanometers) and luminous intensity (brightness) is given in millicandella (mcd).

Figure 2.5.6a: LED datasheet. Courtesy of Cree, Inc.

These devices are RoHS compliant which stands for Restriction of Hazardous Substances. It is an EU directive that limits usage of
toxic materials such as lead, cadmium and mercury. Continuing, we find the device maximum ratings:

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 Figure 2.5.6b: LED datasheet (continued).
Note the different values between the various colors. The forward current is specified as 50 mA for red/amber with 35 mA for
green/blue. Nominal operating currents are between 10 and 30 mA. Reverse voltage is 5 volts, typical for many LEDs although
much lower than the average switching diode. Forward voltage is typically 2.1 volts for the red end of the spectrum and, as
expected, 3.4 volts for the green/blue end. The expected luminous intensities also vary with color. Further, it should be noted that
LEDs do not produce “pure color” light in the manner of a laser. Rather, they produce a range of wavelengths clustered in a specific
area. The wavelength that produces the highest output in this area is referred to as the peak or dominant wavelength. Human vision
covers the range of roughly 400 nanometers (violet) to 700 nanometers (red)3.

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 Figure 2.5.6c: LED datasheet (continued).
Figure 2.5.6c presents pertinent graphical data. We observe a roughly linear increase in luminous intensity with increasing current.
Also, note the difference in the reverse voltage/current plots between blue/green and red/amber. Of particular interest is the final
graph which shows the beam pattern or beam angle. You can think of this in terms of how narrow or broad the illumination pattern
is. When comparing different model LEDs it is useful to remember that on-axis brightness can be increased by narrowing the angle.
This graph is split in half using two different ways of showing the data. On the left side we have a linear graph depicting the
relative brightness as we move off of the center axis (zero degrees). On the right side we see a polar plot version of the same data.

Example 2.5.2

Determine the circulating current for the circuit in Figure 2.5.7. Assume the power supply is 5 volts, the LED forward voltage
is 2.1 volts and the resistor is 330 Ω.

Figure 2.5.7: Schematic for Example 2.5.2.

The LED is forward-biased and as the source is greater than the LED potential, it should light. Using KVL,
E − VLED
I =
R

5V − 2.1V
I =
330Ω

I = 8.788mA

This should result in a relatively bright LED. The resistor can be used to effectively program the brightness by changing the
current level (a smaller resistance yields a higher current and therefore a brighter LED). Given the 2.1 volt forward potential, it
is likely that this is an amber or yellow LED. If a different color had been used, say a 1.6 volt red or 3.2 volt blue, there would
be a change in current and most likely a change in brightness. The change in brightness might not perfectly echo the change in

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 current because the conversion efficiency for the two diodes may not be the same (refer to Figure 2.5.7b to compare the
luminous intensities at 20 mA for different wavelengths).

Figure 2.5.8: Dual LED application.

An interesting circuit using two differently colored LEDs is shown in Figure 2.5.8. An AC source is used to drive the LEDs. Only
one of the two will be forward-biased at any given time. For positive source voltages D will be on while D will be off. For
1 2

negative source voltages the opposite will be true. Resistor R serves to limit current for both of them. Assume D is red and D is
1 2

blue. Further, suppose the source frequency is relative low, say 1 hertz. For the positive half cycle (.5 seconds) the red LED will
light and for the negative half cycle the blue LED will light. This alternating pattern continues for as long as the source is applied
but a curious thing happens as we increase the frequency. At first, the blink rate will increase with the red and blue flickering back
and forth faster and faster. At some point, perhaps around 30 hertz or so, it will appear as though both LEDs are lit continuously.
This is because the human visual sense will tend to integrate the rapid motion and we effectively see the “average” intensity. In
fact, this “on-off” trick is often used in digital circuits to control the brightness of LEDs or the speed of motors. Bi-color LEDs are
available in a single package. Using a common lead and two control leads (one for each color), it is possible to achieve color
mixing.
The logical inverse of the LED is the photodiode, the schematic symbol of which is illustrated in Figure 2.5.9. The photodiode
includes some manner of port that allows light to hit the junction. A sufficiently energetic photon of light can knock lose an
electron. This creates an electron-hole pair which results in current flow. As more light energy is added to the system, an increasing
current or voltage will result4.

Figure 2.5.9: Photodiode schematic symbol.

Photodiodes can operate in one of two modes. The first mode is photovoltaic mode. It uses zero-bias (that is, no external bias
potential). In this mode, the photodiode operates as a voltage source. This is the mode used by photovoltaic solar cells. They can be
thought of as very large photodiodes. The second mode of operation is photoconductive mode. This mode requires reverse-biasing
the diode with an external potential. In this mode the diode acts more like a current source. The advantage is that the response is
faster than photovoltaic mode. The downside is that noise and dark current are worse. Dark current is the current produced even
when no light is shining on the photodiode. Ideally this would be zero. A large dark current reduces the effective dynamic range of
the device.

2.5.3: Schottky and Varactor Diodes

The Schottky diode is a special purpose device. It is named after Walter Schottky, a German physicist. Unlike other diodes that rely
on a semiconductor-tosemiconductor junction, the schottky diode is comprised of a semiconductor-tometal contact. The Schottky
diode exhibits two major advantages over traditional diodes. First, they have very fast switching times, perhaps orders of
magnitude of improvement. Second, they exhibit relatively low turn on voltages. Instead of the 0.6 to 0.7 volts seen with a silicon
junction diode, a Schottky diode may turn on with as little as 0.2 or 0.3 volts. Consequently, Schottky diodes are used when very
fast switching speed and/or minimizing forward voltage drops are important. Examples include shunting diodes in switch mode
power supplies and RF detector circuits. Its schematic symbol is shown in Figure 2.5.10.

Figure 2.5.10: Schottky diode schematic symbol.

The varactor diode is another special purpose device. Its schematic symbol is illustrated in Figure 2.5.11. It is used as an
electrically controlled capacitance (note that the schematic symbol appears as a hybrid of normal diode and capacitor symbols).

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 Figure 2.5.11: Varactor diode schematic symbol.
Varactors are used in reverse-bias mode. The key to understanding their operation is to consider the structure of a diode, comparing
it to the construction of a capacitor. Consider the depletion region to be the dielectric of a capacitor with the anode and cathode
being the capacitor plates. Consequently, all junction diodes exhibit some capacitance. Normally, designers try to minimize this
effect but it is exploited with varactors. As noted in our earlier discussion, increasing the reverse-bias potential on a diode causes its
depletion region to widen. All else being equal, increasing the plate separation of a capacitor decreases its capacitance. Thus, by
increasing the reverse-bias potential, we increase the effective plate spacing and decrease the diode junction capacitance. We now
have a capacitance the value of which is determined by a DC bias voltage. This capacitance can be used as part of electronic tuning
circuits for applications such as oscillators and filters. Compared to fixed capacitors the values tend to be small, in the tens to
hundreds of picofarads, but it is sufficient for much radio frequency work. The advantages over mechanically adjustable capacitors
are manifold, including small size, high reliability, low cost and the ability to rapidly change the capacitance5.

References
1
Although they are called Zener diodes, they rely on either the Zener or avalanche effects, depending on the magnitude of the
voltage.
2There are advantages to using the infrared over the visible spectrum for this application. It tends to be less sensitive to room
lighting conditions and there are no potentially annoying visible flashes of light coming from the remote.
3
It is interesting to observe that the human visual system operates over a frequency range of less than 2:1 while the human auditory
system operates over a frequency range of about 1000:1 (20 hertz to 20,000 hertz). If human hearing had a range equivalent to that
of our sight, we'd hear less than a full octave of pitches in total. In other words, do-re-mi-fa-sol-la-ti-do would end at ti and
anything beyond would be inaudible. In such a case one thing is certain: piano keyboards would be much shorter.
4
As a side note, depending on their construction some LEDs can be used as crude photodiodes. Although they are not optimized for
this use it can be entertaining to shine a light on an LED and watch it produce a voltage.
5
The mechanical version would require a rotary-style adjustable capacitor connected to some form of small motor or solenoid to
move the capacitor plates. While this can work at lower frequencies, if rapid changes are needed the resulting friction-generated
heat may cause this contraption to burst into flames. Generally speaking, this is not something we want our circuits to do.

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2.6: Summary
In this chapter we have examined the structure and functioning of the PN junction. A PN junction produces a depletion region
which is an area devoid of free charges. This leads to an energy hill or barrier voltage, the precise value of which depends on the
material used as well as other factors such as temperature. The PN junction is the basis for most diodes. Its current-voltage
characteristic is described by the Shockley equation and shows a logarithmic characteristic (i.e., the voltage is proportional to the
log of the current).
The terminals of a diode are identified as the anode (P material) and the cathode (N material). If a positive potential which is
greater than the barrier voltage is applied from anode to cathode, the diode will conduct current. If the polarity is reversed, the
diode will not conduct. Therefore a simple model of the diode is a polarity sensitive switch. Improved models include the forward
barrier voltage and the bulk resistance of the diode. Another refinement includes the effect of reverse breakdown, that is, the
tendency of a diode to suddenly begin conducting if the reverse-bias potential is large enough. For ordinary diodes, the reverse
potential should not be allowed to reach breakdown.
Besides the common switching and rectifying diodes, other types are also available. These include the Zener which is normally
used in reverse-bias mode. It is commonly used to set or limit a specific voltage. In forward-bias, a Zener behaves like an ordinary
diode. LEDs produce light from an electrical input. Their forward potentials tend to be in the neighborhood of a few volts. The
photodiode is the complement of the LED and produces a current or voltage that scales with incident light. The Schottky diode is
notable for its fast switching speeds and low barrier potential. Finally, the varactor is used as an electrically controlled capacitance.
It is used in reverse-bias mode.

2.6.1: Review Questions

1. What is a depletion region?
2. Draw and explain the energy diagram for a PN junction, including the Fermi level.
3. Describe and compare the three diode models.
4. Explain the difference between the effective DC resistance and AC resistance of a diode.
5. List some of the practical differences between switching diodes, Zener diodes and LEDs.

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2.7: Exercises
(Assume diodes are silicon unless stated otherwise)

2.7.1: Analysis Problems

1. For the circuit of Figure 2.7.1 determine the circulating current if the supply is 6 volts and the resistor is 10 kΩ.

Figure 2.7.1
2. Repeat Problem 1 if the diode is inserted in the opposite orientation.
3. Given the circuit of Figure 2.7.2, determine the voltage drops across the resistors. The source is 12 volts, R = 4.7 k and R =
1 2

3.3 k.

Figure 2.7.2
4. In Figure 2.7.3 determine the voltage drops across the resistors.

Figure 2.7.3
5. Determine the LED current in Figure 2.7.4. Assume the LED barrier is 2.1 volts, the source is 5 volts and the resistor is 330 Ω.

Figure 2.7.4
6. Repeat Problem 5 if the LED is inserted in reverse orientation.
7. Determine the resistor currents in Figure 2.7.5. The source is 15 volts, R = 8.2 k and R = 3.9 k.
1 2

Figure 2.7.5
8. For the circuit of Figure , determine the resistor voltage. The source is 9 volts, the Zener potential is 5.1 volts and the
2.7.6

resistor is 1 k.

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 Figure 2.7.6
9. For the circuit of Figure , determine the resistor voltage. The source is 8 volts, the Zener potential is 3.3 volts and the
2.7.7

resistor is 10 k.

Figure 2.7.7
10. Determine the voltage across R in Figure 2.7.8 if the source is 9 volts, the Zener is 6.8 volts, R = 5.1 k and R = 33 k.
2 1 2

Figure 2.7.8

2.7.2: Challenge Problems

11. Determine the resistor voltage in Figure 2.7.9 if E = 5 volts, E = 9 volts and R = 1 k.
1 2

Figure 2.7.9
12. Determine the voltage across R in Figure 2.7.8 if the source is 9 volts, the Zener is 5.6 volts, R = 5.1 k and R = 3.9 k.
2 1 2

2.7.3: Design Problems

13. Determine a value for R in Figure 2.7.1 to set the current to 10 mA if the source is 5 volts.
14. Determine a value for R in Figure 2.7.4 that will set the LED current to approximately 20 mA if the source is 9 volts and the
LED is a standard red type. Use a standard resistor value.

2.7.4: Computer Simulation Problems

15. Simulate Problem 9.
16. Simulate the circuit designed in Problem 14 for verification.

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2.8: An Alternate Hypothesis Regarding PN Junctions
And now for something completely different...
One of the great things about the Internet is that you can find almost anything on it. In contrast, one of the terrifying things about
the Internet is that you can find almost anything on it. The following is presented in keeping with the dictum that “It must be true
because I saw it on the Internet”.

2.8.1: An Alternate Hypothesis Regarding PN Junctions

In order to learn how to design circuits and systems using transistors and other solid state devices, students of electronics are told in
their courses how semiconductors function. The atomic structure of crystalline silicon is examined in its intrinsic and doped states.
Discussion of energy levels, conduction band electrons and hole production quickly follow. Soon, the student encounters the PN
junction, a basic building block of modern electronics, and learns about majority and minority carriers, depletion regions, barrier
potentials, leakage current and other exotica. This information is intended to explain just how solid state devices really work and it
can end up sounding quite obtuse. It may sound so complicated, in fact, that the student assumes that only a genius could design
such devices and relegates him or herself to a lower paying engineering or technician job. This should not be the case!
Recent investigations by Farcebook authors have uncovered some startling facts:
1. Semiconductors don't really work the way we've all been told. In fact, the fundamental theory is much simpler.
2. This lie has been fabricated and perpetuated by the economic and political elite, a group of people with cushy, high paying jobs;
jobs so easy in the light of the real theory that even CEOs, hedge fund managers, televangelists, TV psychics and other folk of nil
capability could do it in their sleep (well, OK, the executives would still need an army of assistants and the televangelists would
continue to be outraged by your private life, but you get the general idea). By making their jobs sound difficult these people get to
sit around all day eating eclairs and reading Esquire for an eight figure annual income.
It is high time that the truth be told and this farcical sham be torn down! As an example, we shall see how a simple diode really
works.
So, you think a diode is composed of semiconducting material? Think again! One of the chief researchers at Bell labs in the 1940s
and 50s was a certain Doctor Schlocking. After several experiments involving solid state diodes, Dr. Schlocking wrote in his diary:
“This stuff don't work at all. Better go back to tubes before they can me. Ooops, must let the dog out.”
Schlocking was often pestered by his dog Melvin who reminded him of a small selfpropelled dust mop, and who was
approximately as clean. The diary continued:
“If only there was a way in which Melvin could let himself out. Even better...if he couldn't get back in!”
This ominous tone led to Schlocking's invention of the now infamous one-way doggie door that can be seen mounted to the bottom
of normal doors across the country. Schlocking knew how to milk an idea and took the form to its extremes by developing the cat
door, the mouse door, the grasshopper door, the flea door (an early attempt at a flea and tick collar) and even the amoeba door. This
last unit when properly designed could force microscopic parasites and bacteria out of the human body and not allow them to re-
enter. This was instrumental in the development of the polio vaccine, in spite of the fact that the vaccine was produced some years
earlier. Schlocking's greatest achievement, however, came when he shrunk the doggie door still further to produce the electron
door. This is the fundamental unit of modern electronics.
In the figure below, we see a cross section of a diode and close-ups.

Figure 2.8.1

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Even at 10,000X magnification we can still see nothing of the PN junction. If we go a bit further, something interesting comes into
focus (see the second figure).

Figure 2.8.2
Yes! A PN junction is nothing more than a huge array of real tiny one-way doggie doors! Here's how it works: Electrons are a lot
like marbles. When one hits a doggie door from behind, the door flips open allowing the marble through (i.e., allowing current to
flow). If the electron hits the doggie door from the front, the flap closes and the electron can't get through (i.e., no current flow).
Now obviously, if we hang the diode vertically, gravity should open all the doors and we'll get lots of electrons (i.e., current flow)
in either direction. In truth, a real diode doesn't do this. Its operation will not matter on how the diode is oriented in space. This
feature is accomplished by simply adding a small coil spring to the doggie door's hinge, forcing it to stay shut in the face of gravity.
This has the negative side effect of requiring somewhat higher energy levels from the electrons to force the door open. This force
happens to be the barrier potential of the diode! It has nothing to do with so-called depletion regions. If you were an electron,
would you want to go through a place called a depletion region? Of course not! Neither would electrons. They're not stupid, you
know. In any case, the stronger the spring, the greater the barrier potential. Presently diodes are made of either silicon or
germanium with barrier potentials of approximately 0.7 volts or 0.3 volts, respectively. In fact, silicon and germanium are really
code words meaning strong spring and weak spring! It took a while to develop small, strong springs and this is why germanium
diodes were the first ones built.
Note that spring strength also plays a role in how tightly the flap can shut thus indicating the reverse leakage current. Here again we
see strong spring “silicon” units having lower leakage. Theory also indicates that leakage should increase with temperature. This
effect can be seen clearly in the doggie door model. At present it is impossible to create both the frame and the door out of
precisely the same material and thus two different expansion coefficients exist. Because the flap is smaller than the frame it will
tend to curl away at higher temperatures allowing more electrons to sneak through the gaps. At very low temperatures the flap
tends to stick to the frame in much the same fashion that your tongue or lips will stick to a metal flag pole in freezing weather (also
known as the Christmas Story phenomenon).
At very high forward energy levels the flaps may be literally torn off their hinges. This high volume of electrons at high energy will
yield the maximum forward current. Also, note that if the energy level is high enough in the reverse direction, either the flaps will
be bent and pushed through the frames or they will start to bounce violently at resonance, allowing electrons through. These two
modes are referred to as avalanche and Zener conduction, respectively. The required energy level indicates the reverse breakdown
voltage.
Other fine points can be explained equally by the doggie door model, as well as bipolar and field effect transistors, IGBTs and just
about everything else in the field of solid state electronics with the exception of the original 7400 series TTL logic gates which
utilized an array of small, edible fungi and miniature harvester ants.
More on that in a future exposé.

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 CHAPTER OVERVIEW

3: Diode Applications
Learning Objectives
After completing this chapter, you should be able to:
Solve basic AC rectifier circuits for resulting waveforms.
Detail the differences between half-wave, full-wave and full-wave bridge diode rectifier configurations.
Solve basic regulator circuits employing Zener diodes.
Outline a complete AC-to-DC power supply with regulation, describing the function of each component, including power
transformer.
Solve AC clipper circuits for output waveforms.
Solve AC clamper circuits for output waveforms.

3.1: Introduction
3.2: Rectification
3.3: Clippers
3.4: Clampers
3.5: Summary
3.6: Exercises

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1
3.1: Introduction
The preceding chapter was concerned primarily with introducing the practical considerations of diodes while presenting them in
DC circuits. This chapter will extend the discussion by focusing on AC circuit applications. A prime example is AC to DC
conversion, the concept behind most electronic power supplies. It also includes the basics behind regulation and limiting/level
shifting circuits such as clippers and clampers. The inherent asymmetry in the conductance of diodes, that is, their sensitivity to the
direction of current flow, is what makes these circuits possible. Non-ideal effects such as a diode's forward voltage drop might be
ignored in some instances but may be quite important in others.

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3.2: Rectification
Rectification is the process of turning an alternating current waveform into a direct current waveform, i.e., creating a new signal
that has only a single polarity. In this respect it's reminiscent of the common definition of the word, for example where “to rectify
the situation” means “to set something straight”. Before continuing, remember that a DC voltage or current does not have to exhibit
a constant value (like a battery). All it means is that the polarity of the signal never changes. To distinguish between a fixed DC
value and one that varies in amplitude in a regular fashion, the latter is sometimes referred to as pulsating DC.
The concept of rectification is crucial to the operation of modern electronic circuits. Most electronic devices such as a TV or
computer require a fixed, unchanging DC voltage to power their internal circuitry. In contrast, residential and commercial power
distribution is normally AC. Consequently, some form of AC to DC conversion is required1. This is where the asymmetry of the
diode comes in.

3.2.1: Half-wave Rectification

To understand the operation of a single diode in an AC circuit, consider the diagram of Figure 3.2.1. This is a simple series loop
consisting of a sine wave source, a diode and a resistor that serves as the load. That is, primarily we will be interested in the voltage
developed across the resistor.

Figure 3.2.1: Basic AC diode-resistor circuit.

For positive portions of the input wave, the diode will be forward-biased. To a first approximation it will appear as a closed switch.
Consequently, all of the input signal will drop across the resistor. In contrast, when the input signal switches to a negative polarity
on the other half of the waveform, the diode will be reverse-biased. Therefore, the diode acts as an open switch. The circulating
current drops to zero thereby producing no voltage across the resistor. All of the applied potential drops across the diode, as
indicated by Kirchhoff's voltage law (KVL). The input and load resistor's voltage waveforms can be seen in Figure 3.2.2.

Figure 3.2.2: Half-wave rectification waveforms.

The resulting signal seen across the load resistor is a pulsating DC waveform. We have effectively removed the negative half of the
waveform leaving just the positive portion. Because only half of the input waveform makes it to the load, this is referred to as half-
wave rectification.
It is worth noting that if the AC peak input voltage is not particularly large, there can be an obvious discrepancy between the peak
levels of the input and load signals. For example, if the peak input voltage is in the range of three or four volts and a silicon diode is
used, the resulting waveforms would look more like Figure 3.2.3.

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 Figure 3.2.3: Half-wave rectification waveforms including forward diode drop.
In this case the 0.7 volt forward drop cannot be ignored as it represents a sizable percentage of the input peak. The positive pulses
are also slightly narrowed as current will not begin to flow at reasonable levels until the input voltage reaches 0.6 to 0.7 volts.
If the diode was oriented in reverse, it would block the positive portion of the input and allow only the negative portion through. In
this instance the load waveform would appear flipped top to bottom compared to Figures 3.2.2 and 3.2.3.

Computer Simulation
A simulation schematic for a simple half-wave rectifier is shown in Figure 3.2.4. A sine wave source of 10 volts peak is used to
feed a popular 1N4000 series rectifier diode connected to a 100 Ω load. The source frequency is 60 hertz, the North American
standard for power distribution.
A transient analysis is run resulting in the waveforms shown in Figure 3.2.5. The source voltage waveform is shown in red while
the load voltage waveform is depicted in blue. While the half-wave rectification is obvious, the loss due to the forward voltage drop
of the diode is clearly evident. Based on the vertical scale, a value just under one volt would be a reasonable estimate. The
simulation agrees nicely with the expected result as drawn in Figure 3.2.3, although not as extreme due to the increased source
voltage.

Figure 3.2.4: Simulation schematic for halfwave rectifier.

Figure 3.2.5: Transient analysis for halfwave rectifier.

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On a practical note, there are still two items to consider when it comes to converting AC to DC. The first item is the issue of scaling
the 120 VAC RMS outlet voltage to a more useful level. In many cases this means lowering the voltage although there are some
applications such as high power amplifiers where the voltage will need to be increased. The second item involves smoothing the
pulsating DC to produce a constant value, much like a battery.

3.2.2: A Note Regarding Transformers

The aforementioned voltage scaling issue can be addressed through the use of a transformer. While a complete exploration of
transformers is beyond the scope of this chapter, we can present the basics. In simple terms, a transformer has an input side, or
primary, and an output side, or secondary. Each side is made up of a coil of wire and these coils are wound around a common
magnetic core. The current in the primary-side coil creates a magnetic flux in the core. This flux induces a current in the secondary
coil. Ideally, the voltage is decreased and the current is increased by the ratio of the number of loops between these coils. For
example, if the secondary-side coil has half as many turns as the primary-side coil then the secondary voltage will be half of the
primary voltage and its current will be twice as large as the primary current. This implies that in the ideal case there is no power
lost within the transformer. It simply transforms the power from high-voltage/low-current to low-voltage/high-current (or vice
versa), hence the name. In reality, transformers do have voltage and current limits, and they are specified in terms of a volt-amp or
VA rating which is simply the product of the nominal secondary voltage and maximum allowed secondary current. Transformers
that decrease the voltage are referred to as step-down while those that increase the voltage are referred to as step-up. Finally, it is
possible to create transformers with multiple primaries and secondaries (via either separate coils or multi-tapped coils). The
resulting series and parallel coil configurations make them much more flexible.

3.2.3: Smoothing (Filtering) the Output

The second issue we have is smoothing and leveling the pulsating DC. The most straightforward method to achieve this is to add a
capacitor in parallel with the load. The capacitor will charge up during the conduction phase, thus storing energy. When the diode
turns off, the capacitor will begin to discharge, thus transferring its stored energy into the load. The larger the capacitor, the greater
its storage capacity and the smoother the load voltage will be. It turns out that there is a down side to large capacitors, as we shall
see. Consequently, the goal will not be to use as large of a capacitor as possible but rather to use an optimal size for a given
application. A half-wave rectifier with transformer and capacitor is shown in Figure 3.2.6.

Figure 3.2.6: Half-wave rectifier with transformer and filter capacitor.

One way of looking at the inclusion of the smoothing capacitor is to consider that it, along with the load resistance, make up an RC
discharge network. To achieve a smooth load voltage the discharge time constant should be much longer than the gap produced
when the diode turns off. For 60 hertz operation, this gap is half of the period, or roughly 8.3 milliseconds. The time constant
equation is

τ = RC

Recalling that in one time constant the capacitor voltage will fall to well below half of the starting value (roughly 37%), we will
need a time constant several times larger than 8.3 milliseconds. For example, suppose our effective load resistance is 100 Ω. If we
use a 1000 μ F capacitor, the resulting time constant would be 100 milliseconds, or over ten times the gap duration. A much smaller
capacitor, say around 50 μ F, would not be nearly so effective at keeping the voltage constant.
The variation in output voltage due to capacitor discharge is referred to as ripple. It can be modeled as an AC voltage riding on a
larger DC output. The magnitude of the ripple worsens as the load current increases. Under light load conditions, the output will
tend to float to the peak voltage of the secondary with very little ripple. As load current demand goes up, the ripple magnitude
increases and the nominal output voltage begins to drop.

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Computer Simulation
Two variations on a filtered half-wave rectifier are simulated below. Both versions use a 100 Ω load with a 10 volt source, similar
to the prior simulation. The first version uses a 50 μ F filter capacitor while the second ups this to 1000 μ F. In both cases a 1 Ω
resistor is added in series with the capacitor to serve as a current sensor. The first version is shown in Figure 3.2.7.

Figure 3.2.7: Simulation schematic for half-wave rectifier with 50 μ F filter capacitor.
A transient analysis simulation graph is shown in Figure 3.2.8. The input waveform is colored blue while the load voltage is red.
Comparing this waveform to that depicted in Figure 3.2.5 shows the effect of the capacitor stretching out the pulse and partially
filling in the gap. It is obvious that this capacitor is too small given the load resistance and the resulting current demand. Indeed, by
the time the next pulse arrives the capacitor is nearly depleted and the output voltage has dropped to around one volt.

Figure 3.2.8: Transient analysis simulation for half-wave rectifier using a 50 μ F filter capacitor.
In Figure 3.2.9 the simulation is rerun, but this time using a 1000 μ F capacitor in place of the 50 μ F. As expected, the increased
RC time constant results in a much more stable load voltage. In this version the output has dropped from a little over nine volts to

about eight volts yielding a peak-to-peak ripple of a volt and a half or so. The peak voltage of just over nine volts versus the applied
ten volts is largely due to the voltage drop across the rectifying diode.

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 Figure 3.2.9: Transient analysis simulation for half-wave rectifier using a 1000 μ F filter capacitor.
One thing that may not be apparent immediately is that the charge time for the larger capacitor is much shorter than for the smaller
unit. This is perhaps counterintuitive. With a larger capacitor, the diode turns on for a shorter time because its cathode is held at a
high voltage due to the capacitor. That is, it will only turn on when the input voltage exceeds the capacitor voltage by roughly 0.7
volts. It is only during this time that the capacitor will be replenished, and this can lead to very large current spikes.
To investigate this effect, the simulations are rerun, but this time adding the voltage across the 1 Ω sensing resistor. This relatively
small value will have only a modest effect on the charging and discharging, and conveniently scales to the current value (i.e., 100
millivolts signifies 100 milliamps). First, examine the transient simulation of Figure 3.2.10 using the 50 μ F capacitor.
The red sweep is the output voltage while the blue sweep represents the capacitor current. The output voltage plot uses the left
vertical axis while the current plot uses the right vertical axis. As the load voltage begins to rise, we see an abrupt spike in the
capacitor current. This is current charging the capacitor and it peaks at about 180 milliamps. The total time for the charge phase is
around 4 milliseconds. Once the output voltage peaks, the capacitor starts to discharge into the load. During the discharge phase
note that the capacitor current's polarity has reversed. It is negative, peaking at roughly −80 milliamps, and delivering current to the
load.

Figure 3.2.10: Transient analysis current waveform using a 50 μ F filter capacitor.

This simulation is repeated using the 1000 μ F capacitor. The results are shown in Figure 3.2.11.

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 Figure 3.2.11: Transient analysis current waveform using a 1000 μ F filter capacitor.
The blue current waveform peaks at approximately 800 milliamps, or over four times the value compared to using the smaller
capacitor. Also, the width of the positive pulse has decreased to about 2.5 milliseconds. The discharge phase is nearly flat, implying
that the output voltage must be more stable as this capacitor is the only source for load current during this phase.

3.2.4: Full-wave Rectification

An improvement on half-wave rectification is full-wave rectification. Half-wave rectification is inefficient because it essentially
throws away the negative portion of the input. In contrast, full-wave rectification makes use of the negative portion by inverting or
flipping its polarity. The resulting circuit is modestly larger and more complicated but results in large performance improvements.
For example, filter capacitor size is greatly reduced.
There are two popular methods to achieve full-wave rectification. The first method uses a pair of diodes with a center-tapped (i.e.,
split) secondary. The second method uses a four diode bridge network. The diode bridge form is also capable of producing a
bipolar output (i.e., a positive output along with a negative output, typically of the same magnitude).
The two diode center-tapped secondary circuit is shown in Figure 3.2.12. This schematic also includes the filter capacitor.

Figure 3.2.12: Full-wave center-tapped rectifier with capacitor.

The operation is as follows. During the positive half of the source voltage diode D is forward-biased while D is reverse-biased.
1 2

Therefore the upper half of the secondary behaves like a simple half-wave rectifier allowing current to flow through D and into
1

the load. Due to the reverse-bias on D , the lower half presents an open circuit and is effectively removed. In mirror fashion, when
2

the applied potential switches polarity D will be reverse-biased while D becomes forward-biased. Current is now free to flow
1 2

through D into the load. Thus, both halves of the input waveform are used. The resulting waveforms are illustrated in Figure
2

3.2.13. For clarity, the filtering effect of the capacitor is not shown and V
in represents one half of the total secondary voltage.

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 Figure 3.2.13: Full-wave rectifier waveforms.
An important point to remember about this configuration is that the load only “sees” half of the secondary at any given time.
Therefore, the load voltage will only be half of the total secondary voltage (minus one forward diode drop). For example, if the
transformer has a 10:1 turns ratio and is being fed from a standard 120 volt source, the secondary will produce 12 volts RMS.
Ignoring the diode drop, the load would see half of this, or 6 volts RMS (about 8.5 volts peak). Typically, transformers are rated by
their total secondary voltage so this transformer would be referred to as having a “12 volt center-tapped secondary”.
A four diode bridge rectifier is shown in Figure 3.2.14. A filter capacitor is included. Also, note the usage of a standard, non
center-tapped secondary. As this is a very common configuration, the four diode bridge is available as a single four-lead part in a
variety of sizes and current capacities.

Figure 3.2.14: Full-wave bridge rectifier with capacitor.

The operation of this circuit is illustrated in Figure 3.2.15 for the positive portion of the input. First, current flows from the top of
the secondary to the D /D junction. Only D offers a forward-bias path so current flows through D to the junction with D and
1 2 2 2 4

the load. As D presents a reverse-bias path, current must flow down through the load. From ground, current continues to the
4

D / D junction. Although at first glance it appears that current could flow through either diode, remember that the cathode of D
1 3 1

is tied to the high side of the secondary. Therefore, its potential must be higher than the anode side, making it reverse-biased.
Consequently, the current flows down through D . A similar situation occurs at D and current is directed back to the low side of
3 4

the secondary. In short, D and D are forward-biased while D and D are reverse-biased. The load sees the entire secondary
2 3 1 4

voltage minus two forward diode drops.

Figure 3.2.15: Full-wave bridge rectifier analysis, positive input.

During the negative polarity portion of the input the situation is reversed as illustrated in Figure 3.2.16. Current will flow from the
bottom of the secondary through D , down through the load, and finally back to the top of the secondary via D . Thus, D and D
4 1 1 4

are forward-biased while D and D are reverse-biased. The important thing is that in both cases, the current flows down through
2 3

the load, top to bottom, resulting in a positive output voltage.

Figure 3.2.16: Full-wave bridge rectifier analysis, negative input.

Example 3.2.1

Design a rectifier/filter that will produce an output voltage of approximately 30 volts with a maximum current draw of 300
milliamps. It is to be fed from a 120 VAC RMS source. The ripple voltage should be less than 10% of the nominal output
voltage at full load.

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 For this design we shall focus on using common off-the-shelf parts. As we have seen, the full-wave rectifiers are more efficient
at converting AC to DC so we shall go that route, specifically, a four diode bridge arrangement. We will use the circuit of
Figure 3.2.14 as a guide.
The first item to consider is the size of the transformer. A 30 volt output would require a peak secondary voltage of at least 32
–
volts as we must add in two forward diode drops. The equivalent RMS value is 32/√2 or 22.6 volts. At full load the filtered
output voltage will droop somewhat so a somewhat larger value is called for. A standard 24 volt secondary should suffice.
Given the 300 milliamp load current rating, the transformer must be at least 0.3 amps ⋅ 24 volts or 7.2 VA.
–
As far as the capacitor is concerned, it must be rated for the peak voltage. The peak equivalent is 24 VAC RMS ⋅√2 or 34
volts. Although a 35 volt rated capacitor might be tried, a standard 50 volt rating would leave a generous safety margin and
increase reliability. To find the capacitance value we must first find the effective worst case load impedance.
Vout
R =
Imax

30V
R =
0.3A

R = 100Ω

It will be useful to compare this back to the simulation depicted in Figure 3.2.9. Our ripple specification is somewhat tighter
than that achieved in the prior simulation. This is apparent by noting how far the output voltage has dropped by midway
through the off portion of the cycle. Consequently, we will need a larger time constant, perhaps by a factor of two. That puts us
at 200 milliseconds.

τ = RC

τ
C =
R

0.2s
C =
100Ω

C = 2000μF

A 2200 μ F standard value should be sufficient.

Computer Simulation
To verify our results, the design from Example 3.2.1 is simulated. The schematic is shown in Figure 3.2.17. To simplify the
simulation, a 24 volt RMS source is used in place of the transformer. The worst case load is simulated via a 100 Ω resistor. For the
initial test the filter capacitor is omitted so that we can ensure the proper peak voltage and waveforms are created. The results of a
transient analysis are shown in Figure 3.2.18. The secondary voltage is shown in red while the load voltage is shown in blue. The
full-wave waveform is exactly as expected, including a slight reduction in the peak voltage value due to two forward diode drops.
The output peak is just above 30 volts, as desired.

Figure 3.2.17: Simulation schematic for the design of Example 3.2.1 without capacitor.

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 Figure 3.2.18: Transient analysis of the design of Example 3.2.1 without capacitor.
Now that we have confidence in the voltage level and waveform, the output filter capacitor is added as shown in Figure 3.2.19. A
transient analysis is run again with the resulting input and load voltage waveforms depicted in Figure 3.2.20. The load voltage is
shown in red. The average value is just over 30 volts and the peak-to-peak ripple is less than two volts, as desired. Note that the
full-load peak voltage with the capacitor is slightly less than what was seen in the capacitor-less version. If the load current demand
were to increase, both droop and ripple would get worse.

Figure 3.2.19: Simulation schematic for the design of Example 3.2.1 with capacitor.

Figure 3.2.20: Transient analysis of the design of Example 3.2.1 with capacitor.

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3.2.5: Full-wave Bridge With Dual Outputs
As mentioned, the full-wave bridge can be configured to create a dual output bipolar supply. This is shown in Figure 3.2.21. Note
the inclusion of the center tap on the secondary of the transformer and the location of the ground connection between the two loads
and their associated capacitors.

Figure 3.2.21: Dual output full-wave bridge rectifier.

One way of thinking of this is that we have simply created a new reference point, splitting in half the total output potential of the
circuit presented in Figure 3.2.14. Alternately, it can be thought of as the upper half of the secondary driving R while the
load+

bottom half drives R load−, as if the bridge and two-diode versions were somehow combined in a transporter accident, as in the
1958 movie The Fly, although it doesn't scream “Help me! Help me!” in a tiny little voice at the end.

3.2.6: Zener Regulation

Adding a large capacitor to a rectifier is necessary to store and transfer energy so that a smooth, ideally non-varying voltage results.
As noted previously, under heavy load the ripple would increase in amplitude and the average voltage would drop. This issue can
be greatly reduced by adding a Zener diode and current limiting resistor to the output, following the capacitor. This is called a
Zener regulator and is shown in Figure 3.2.22.

Figure 3.2.22: Simple Zener regulator.

The operation of the Zener regulator is fairly straightforward. Recall that when reverse-biased with a sufficiently large potential,
the normal reverse diode behavior of an open switch abruptly changes to maintain a fixed voltage; the Zener potential. The current
through the diode begins to increase dramatically once this potential is reached. If we place a Zener diode across the output of our
filtered rectifier, the Zener will attempt to limit the output voltage to the Zener potential. To prevent excessive and possibly
destructive current draw by the Zener diode, the voltage difference between the capacitor voltage and the Zener potential is
dropped across a series current limiting resistor. This limiting resistor will set the maximum amount of output current. This current
is then split between the Zener diode and the load. Under light load conditions, most of this current will flow through the Zener
diode. Under heavy load conditions, most of the current will be drawn by the load with little flowing through the Zener diode. If the
load current demand is too heavy, no current is available for the Zener diode and it stops conducting. Regulation is lost and the
limiting resistor forms a voltage divider with the load.
A complete rectifier/filter/Zener regulator circuit is show in Figure 3.2.22. Let's examine how R limit interacts with the load.

Figure 3.2.22: Full-wave bridge rectifier and filter with Zener regulator.
For proper operation, the Zener potential (D ) is the desired DC output voltage and the peak secondary voltage is set somewhat
5

higher. We wish to guarantee that under full load conditions the lowest capacitor voltage due to ripple is still greater than the
desired DC output voltage. The difference between the capacitor voltage and the Zener potential drops across R . Therefore
limit

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 Vcap − VZ
I =
Rlimit

Under no-load conditions all of this current flows down through the Zener diode. The maximum load current is equal to this value
(at which point no current flows through the Zener diode).

Example 3.2.2

Determine the maximum load current for a DC supply such as that found in Figure 3.2.22. The capacitor voltage is 15 volts
average with ±1 volt of ripple (i.e., 16 volts dropping to 14 volts). The Zener potential is 12 volts and R is 4.7 Ω.
limit

The highest possible continuous load current is the current through R (ignoring
limit IZT ). The limiting case for continuous
draw will occur when the capacitor voltage is at its lowest value, or 14 volts.
Vcap − VZ
I =
Rlimit

14V − 12V
I =
4.7Ω

I = 426mA(actually a few mA less due to IZT )

The highest peak current through the Zener diode is found at the maximum capacitor voltage and assumes no current is drawn
by the load.
Vcap − VZ
I =
Rlimit

16V − 12V
I =
4.7Ω

I = 851mA

Note that this worst case current times the Zener potential results in a power dissipation of about 10 watts. Of course, during
normal operation with a load drawing current, the diode dissipation is much reduced. It is interesting to note that the Zener
dissipates maximal power when the load current is zero. Consequently, we can think of this circuit as shifting current from the
Zener diode to the load as the load demands more current2.

References
1If you're wondering why we don't just use DC distribution instead in order to “cut out the middle man”, the reasons are manifold.
First, it is generally more efficient to distribute power via AC rather than DC. Second, even if DC is available, it may not be at the
amplitude the circuitry requires. Therefore some form of DC-to-DC conversion would be needed. Depending on the application,
this can turn out to be more expensive than AC-to-DC conversion.
2
As you might guess, this is not particularly efficient because even when the load demand is nil, the Zener diode is still drawing
current from the transformer. An improved circuit may include a bipolar transistor, as examined in Chapter 4. For details on more
sophisticated techniques to regulate voltage, see Fiore, J, Operational Amplifiers and Linear Integrated Circuits: Theory and
Application, another free OER text.

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3.3: Clippers
Sometimes it is useful to limit the maximum amplitude of a signal. This might be done for protection, for example when too large
of an input signal might damage the following circuit. It might also be employed as a means of wave shaping, that is, morphing a
signal into another shape. A good example is the purely aesthetic desire to emulate the sound of “fuzz” guitar. In the early days of
rock music it was discovered that over-driving a guitar amplifier in an attempt to make it louder created considerable distortion and
this produced a new and interesting sound quality. Technically, this is largely caused by the power stage of the amplifier reaching
its maximum output level. Any portion of the waveform above this level is simply cut off or clipped1. The practical problem here is
that the only way to achieve this sound is to crank up the guitar amplifier's volume to ten2 and live with the attendant high loudness
level. Not too popular with the neighbors, that's for sure. In contrast, if the signal could be limited before the power amplifier stage
in an attempt to mimic the clipping, the effect could be achieved without the resulting loudness. This proved to be so popular
among guitarists that by the 1970s numerous companies were making “fuzz boxes” and “distortion pedals”, each with their own
twist on the concept.
The simplest form of clipper places a diode (or two parallel diodes of opposing polarity) in parallel with the load. The diode will
limit the output voltage swing to its forward turn-on potential; 0.7 volts for a silicon device. This circuit is somewhat limiting (pun
intended) as you are stuck with a 0.7 volt limit value. What if we need to limit at some other potential, say 12 volts? While it is
possible to stack a bunch of diodes in series to increase the limit point, a more flexible and practical approach involves biasing the
diode with a DC source. This is called a biased diode clipper.

Figure 3.3.1: Biased positive clipper.

A biased diode clipper used to limit positive signals is shown in Figure 3.3.1. The operation is as follows. For any input signal that
is less positive than the bias potential V , the diode will be in reverse-bias. This means that the diode branch presents a high
clip

resistance and is effectively removed from the circuit. Therefore, V flows through R to the output unimpeded. If the input signal
in

exceeds by V clip by approximately 0.7 volts, the diode turns on resulting in a very low internal resistance. As the internal resistance
of the DC source is also very low, this creates a low impedance path to ground and results in a voltage divider with R . As R is a
much greater resistance value, virtually all of the input signal above the turn-on voltage will be dropped across R , never reaching
the output. Therefore, we can control or program the clip point by adjusting the bias voltage. Clipping will occur at approximately
Vclip plus 0.7 volts, assuming a silicon diode is used.

Figure 3.3.2: Biased negative clipper.

A negative biased clipper is shown in Figure 3.3.2. Both the diode and DC bias voltages have been flipped to the opposite polarity.
The operation of this circuit is similar to the positive clipper. In this variant, the negative bias potential ensures that the diode is
reverse-biased as long as the input level is more positive than V clip minus 0.7 volts. Once the input signal goes below this voltage,
the diode turns on creating the shorting path and limiting the output voltage.
A bipolar or dual-polarity clipper can be created by combining the positive and negative clippers. It is possible to limit the positive
and negative swings independently, as illustrated in the following Example.

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 Example 3.3.1

Determine the output signal for the circuit of Figure 3.3.3. The input voltage is a 12 volt peak sine wave at 100 Hz. D and D
1 2

are silicon switching diodes. R = 10 kΩ, V = 4 volts and V = 8 volts.

1 2

Figure 3.3.3: Dual clipper for Example 3.3.1.

First off, note that the precise value of R is unimportant here. It simply needs to be significantly larger than the on-resistance
of the diodes. Based on our prior study of diode resistance in Chapter 2 (see the discussion around Figure 2.4.3) it is likely that
the dynamic diode resistance will be under 100 Ω once full turnon is reached. This resistance ratio is more than sufficient to
create an effective voltage divider.
The positive clip level will be set by V . Adding in the forward potential of D we arrive at 4.7 volts. The negative clip level
1 1

will be set by V . Including in the forward potential of D we arrive at −8.7 volts.

2 2

Thus, we expect to see a sine wave that is clipped at +4.7 volts and −8.7 volts. It should appear as a sort of lopsided cross
between a sine wave and a square wave.

Computer Simulation
To verify and visualize our computations, the circuit of Example 3.3.1 is simulated with a transient analysis. The circuit schematic
is shown in Figure 3.3.4. For the diodes, common 1N914 switching diodes are used.

Figure 3.3.4: Simulation schematic for dual clipper of Example 3.3.1.

The results of the transient analysis are shown in Figure 3.3.5. The input waveform is shown in red while the output waveform is
shown in blue. The input sine wave appears as expected with the specified 12 volt peak. The output follows the input perfectly for
all values that are within the clip points. Beyond the clip points, the output voltage flattens. That is, it is limited to just below +5
volts (the programmed +4.7) and to just above −9 volts (the programmed −8.7 volts).
Careful inspection of the output waveform plot reveals that it is not perfectly flat at the voltage limits. In fact, there is a slight
rounding that is most noticeable toward the transitions. This is due to the fact that the diodes do not turn on immediately. The
dynamic resistance of the diodes change with the size of the signal. That is, the greater the input signal is above the clip point, the
more current that will flow, and thus the dynamic resistance decreases, strengthening the effect of the voltage divider.

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 Figure 3.3.5: Transient analysis for dual clipper of Example 3.3.1.

References
1
We will take a closer look at amplifier clipping in the chapters that cover power amplifiers.
2
Or eleven, if you have a custom Spinal Tap amplifier.

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3.4: Clampers
A clamper is circuit that adds a DC offset to an AC signal in such a way that the resulting voltage is uni-polar. A positive clamper
adds a positive offset such that the former negative peak now sits at zero volts. In like fashion, a negative clamper adds in a
negative offset such that the former positive peak now sits at zero volts. Clampers are also referred to as DC restorers. Clampers
can also be biased so that the new peak point is something other than zero volts.
The concept of a clamper is fairly simple; we just add a DC voltage to the existing AC signal. The trick is in getting the circuit to
automatically determine what the DC shift needs to be. This way, if the amplitude of the input signal changes, the offset can track
with it.

Figure 3.4.1: Prototype DC offset circuit.

First, let's consider the prototype circuit in Figure 3.4.1. This is a fixed DC offset circuit. The DC source E adds a positive offset to
the input signal. If the offset is equal to the peak value of the input, the negative peak will rise up to zero volts and the diode will
never turn on (meaning that it will not load the input and change the wave shape).

Figure 3.4.2: Positive clamper.

In Figure 3.4.2 the fixed DC source has been replaced with a capacitor. This capacitor is used to create the DC offset. Unlike the
fixed source, the capacitor voltage will vary with the peak value of the input and therefore precisely compensate to produce an
ideally clamped output signal. As long as the time constant for this capacitor and the surrounding resistance is much longer than the
period of the input waveform, it will achieve proper clamping action.
Here is how the circuit operates. For the initial positive cycle, the capacitor is uncharged and the diode is reverse-biased. As the
RC time constant is much longer than the input period, the output voltage merely follows the input voltage. Once the input signal

swings negative, the diode turns on. This bypasses the parallel resistor and drastically reduces the charge time constant. This means
that the capacitor voltage will begin to track the negative portion of the input signal while the output stays near zero volts. Note that
the capacitor voltage will have a polarity of minus-to-plus from left to right, in keeping with Kirchhoff's voltage law. The capacitor
voltage will track the negative input voltage all the way down to the negative peak. Once the input begins to reverse slope and rise
toward zero, the diode will be turned off due to the potential now held on the capacitor. At this point, the capacitor has a voltage
across it that is equivalent to the negative peak value of the input signal and it will behave just like the fixed DC voltage source in
the prototype. The input is just now starting to track in the positive direction from its negative peak while the capacitor holds this
same magnitude of voltage. The result is that the output is at zero volts and as the input continues to swing positive, the output will
track it, thus producing the desired level shift.
Of course, circuits are never perfect. First, the forward voltage drop of the diode will result in a negative peak that's not precisely at
zero volts but is instead about −0.7 volts. Second, it may take more than one cycle of the input to “grab” the peak value, all
depending on the period and the precise charge and discharge time constants. As you might guess, flipping the polarity of the diode
will result in a negative clamper instead of a positive clamper. Also, if we add a DC source in series with the diode, like we did
with the biased clipper, we can create a biased clamper. This is shown in Figure 3.4.3.

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 Figure 3.4.3: Biased positive clamper.

Example 3.4.1

Determine the output signal for the circuit of Figure 3.4.3. The input voltage is a 10 volt peak sine wave at 1 kHz. C = 10 μ F,
R = 10 kΩ , V = 5.7 volts and D is a silicon switching diode.
clamp

The configuration is a positive biased clamper. First, we need to ensure that the discharge time constant is much longer than the
period. The period is 1/f, or 1 millisecond. The discharge time constant is

τ = RC

τ = 10kΩ × 10μF

τ = 100 milliseconds

The DC clamping source will produce a positive offset of 5 volts (5.7 volts minus the 0.7 volt forward diode drop). This means
that we should see a 20 volt peak-to-peak sine wave that swings between +5 volts and +25 volts.

Computer Simulation
To verify the analysis of Example 3.4.1 , the circuit is captured as shown in Figure 3.4.4. A common 1N914 switching diode is
used.

Figure 3.4.4: Simulation schematic for biased clamper of Example 3.4.1.

Figure 3.4.5: Transient analysis for biased clamper of Example 3.4.1.

The transient analysis is shown in Figure 3.4.5 and is precisely as predicted. The input waveform is blue and the clamped output is
shown in red. The analysis was delayed ten milliseconds in order to get past the initial charge phase and observe the steady state
operation.

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3.5: Summary
Numerous AC diode applications have been examined in this chapter. A single diode may be used to create half-wave rectification,
producing pulsating DC from AC. This is achieved by simply blocking one of the two polarities with a diode. A more efficient
form of rectification is full-wave rectification. In this scheme, one of the two polarities is effectively flipped. This may be achieved
via a two diode circuit that employs a split secondary transformer or via a four diode bridge circuit using a non-tapped secondary.
The addition of a split secondary to the bridge circuit enables a dual polarity output.
In order to smooth the pulsating DC into a relatively constant level, a filter capacitor is added in parallel with the load. The larger
the capacitor, the greater the filtering and smoothing action, however, this will also increase peak charging current. A Zener diode
may be employed to further stabilize the output voltage.
Clippers are used to limit the range of an input signal. They may be designed to clip the positive portion, the negative portion or
both polarities of the input waveform. The positive and negative clip levels may be adjusted independently.
Clampers are used to create a DC level shift that is dependent on the peak level of the input waveform. The shift may be positive or
negative, and may also include an optional bias. The operation of the clamper hinges upon the charge versus discharge time
constants for a series capacitor and associated diode.

3.5.1: Review Questions

1. List the advantages and disadvantages of half-wave versus full-wave rectifiers.
2. Discuss the advantages and disadvantages of a full-wave bridge rectifier versus a two diode center-tapped rectifier.
3. What is the purpose of the capacitor in a rectifier/power supply circuit?
4. Under what load conditions will a Zener regulator fail to maintain regulation of the output voltage?
5. What is ripple? How might it be reduced?
6. What is the function of the DC source(s) in a biased clipper?
7. What is the function of the capacitor in a clamper circuit?

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3.6: Exercises
(Assume diodes are silicon unless stated otherwise)

3.6.1: Analysis Problems

1. For the circuit of Figure 3.6.1, determine the peak output voltage. V sec = 12 volts RMS, R load ,
= 50 Ω C1 = 1500 μ F.

Figure 3.6.1
2. Sketch the output voltage waveform for the circuit of Problem 1, Figure 3.6.1, with and without the capacitor.
3. Determine the peak output voltage for the circuit of Figure 3.6.2. V sec = 18 volts RMS, R load ,
= 75 Ω C1 = 470 μ F.

Figure 3.6.2
4. Sketch the output voltage waveform for the circuit of Problem 3, Figure 3.6.2, with and without the capacitor.
5. For the circuit of Figure 3.6.3, determine the peak output voltage. V sec = 18 volts RMS, R load ,
= 40 Ω C1 = 1000 μ F.

Figure 3.6.3
6. Sketch the output voltage waveform for the circuit of Problem 5, Figure 3.6.3, with and without the capacitor.
7. Determine the output voltage waveform and its amplitude for the circuit of Figure 3.6.4. V in ,
= 10 sin 2π100t Vclip = 8 volts,
R = 10 kΩ .

Figure 3.6.4
8. Draw the output waveform with its amplitudes for the circuit of Figure 3.6.5. V in ,
= 10 sin 2π100t Vclip = 5 volts, R = 10 kΩ.

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 Figure 3.6.5
9. Draw the output waveform with its amplitudes for the circuit of Figure 3.6.6. V in ,
= 12 sin 2π200t V1 = 6 volts, V2 =4 volts,
R = 10 kΩ .

Figure 3.6.6
10. Draw the output waveform with its amplitudes for the circuit of Figure 3.6.7. V in ,
= 5 sin 2π2000t C = 10 μ F, R = 4.7 kΩ.

Figure 3.6.7
11. Draw the output waveform with its amplitudes for the circuit of Figure 3.6.8. V in ,
= 8 sin 2π500t Vclamp = 2 volts, C = 4.7

μ F, R = 33 kΩ .

Figure 3.6.8

3.6.2: Design Problems

12. Design a 15 volt AC to DC power supply capable of drawing 200 mA.
13. Design a circuit that will limit its output voltage to a range of −5 volts to +10 volts.
14. Design a circuit that will shift its output voltage so that it is always positive. The input frequency is 2 kHz.

3.6.3: Challenge Problems

15. Design a circuit that will shift its output voltage so that its negative peak is at +3 volts. The input frequency range is from 100
Hz to 1 kHz.

3.6.4: Computer Simulation Problems

16. Run a transient analysis of the circuit in Figure 3.6.1, Problem 1.
17. Run a transient analysis of the circuit in Figure 3.6.2, Problem 3.
18. Run a transient analysis of the circuit in Figure 3.6.3, Problem 5.
19. Run two transient analyses on the clamper circuit of Example 3.4.1, first using a capacitor 100 times larger than specified, and
second using a capacitor 100 times smaller than specified. Discuss the resulting waveforms.

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 CHAPTER OVERVIEW

4: Bipolar Junction Transistors (BJTs)

Learning Objectives
After completing this chapter, you should be able to:
Draw and explain the energy diagram for a biased bipolar junction transistor (BJT).
Describe the differences between NPN and PNP BJTs.
Explain forward-reverse bias operation.
Define the transistor parameters alpha and beta, and determine them from device curves and/or circuit currents.
Draw and explain the various regions of a BJT collector curve, along with Early voltage.
Describe and utilize the Ebers-Moll BJT model.
Describe the concept of the DC load line.
Solve and design basic switching and driver circuits utilizing BJTs.

4.1: Introduction
4.2: The Bipolar Junction Transistor
4.3: BJT Collector Curves
4.4: BJT Data Sheet Interpretation
4.5: Ebers-Moll Model
4.6: DC Load Lines
4.7: BJT Switching and Driver Applications
4.8: Summary
4.9: Exercises

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1
4.1: Introduction
The bipolar junction transistor, or BJT, is a foundational electronic component. It serves as the basis for a variety of applications
ranging from simple amplifiers to device control to complex digital computing circuitry. Variations exist for applications spanning
very low to very high frequency work; low, medium and high power; inexpensive general purpose through highly specialized niche
items; and so forth. No matter what a BJT has been optimized for, all BJTs can be considered to be current boosting devices. Of
course, if you can boost current, then you can also boost voltage and power, depending on the associated impedances. Further, all
BJTs share the same basic structure: three alternating layers of N-type and P-type material with one external lead attached to each
layer. In this manner, the BJT can be thought of as an extension of the basic diode: just add another segment of oppositely doped
material to one end of the diode creating a second PN junction. The configuration could be either PNP or NPN. There are uses for
both types and circuits often work best when the two types are used together.

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4.2: The Bipolar Junction Transistor
In prior work we discovered that the PN junction is the foundation of the basic diode. Under normal operating conditions the
interface between the N-type and P-type materials is devoid of free charges and is referred to as a depletion region. The dissimilar
Fermi levels of N-type and P-type materials lead to an “energy hill” between them, and without an external potential of the proper
polarity, the junction will not allow current to flow. The required magnitude is a function of the material used but it is always the
case that the P material (anode) must be positive with respect to the N material (anode). We extend this idea by adding a second
portion of N material to the other side of the P material, creating an N-P-N “sandwich” of sorts. This is shown in Figure 4.2.1.

Figure 4.2.1: Basic configuration of NPN bipolar junction transistor.

This diagram is drawn to ease the understanding of the operation of the device, extending our earlier diode work. In contrast, real
BJTs are built in more of a “layer cake” fashion, N-P-N bottom to top1. Of course, the spatial orientation of the device has no
bearing on its operation so this is not a major issue for our purposes. The three terminals are named the emitter, base and collector.
The collector is the largest of the three regions while the base is relatively thin and lightly doped.
Above absolute zero there will be recombination and two depletion regions will form as shown in Figure 4.2.2 . Compare this
figure to the basic PN junction drawing found at the beginning of Chapter 2, Figure 2.1.1.

Figure 4.2.2: Charges in NPN BJT (base region widened to show detail).

4.2.1: A Simple Two-Diode Model

Because this device contains two depletion regions, a much simplified model can be created using two diodes as shown in Figure
4.2.3. Please keep in mind that this is a very limited model (as we shall soon see).

Figure 4.2.3: Diode model of NPN BJT.

If you were to test an NPN BJT with an ohmmeter, two leads at time, this model would successfully predict the results. If the red
(positive) lead of the ohmmeter is connected to the base and the black (negative) lead is connected to either the emitter or collector,
a low resistance will be indicated. This is because the ohmmeter will modestly forward-bias the base-emitter or base-collector
junction. Similarly, if the leads are reversed, the meter will indicate high resistance because the junction under consideration will be
reverse-biased. If the two leads are connected to the emitter and collector, a high reading will result regardless of the polarity. This
is because one of the two junctions will be reverse-biased which results in no current flow through either of them due to the series
connection.

4.2.2: Biasing the BJT

Now let's consider adding external sources to bias the transistor. We begin by adding two DC sources with associated current
limiting resistors as shown in Figure 4.2.4.

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 Figure 4.2.4: Double reverse-bias.
This circuit is comprised of two loops, one between the base-emitter and the second between the base-collector. In the B-E loop,
the emitter supply V EE reverse-biases the base-emitter diode. A similar situation occurs in B-C loop where the collector supply
reverse-biases the base-collector diode. The result is that virtually no current flows anywhere in the circuit. If the two supplies are
reversed in polarity then both diodes become forward-biased and we see currents flowing in both loops dependent on the precise
values of the supplies and associated resistors. No surprises so far. Now consider if we forward-bias the base-emitter diode while
simultaneously reversebiasing the base-collector diode, as shown in Figure 4.2.5.

Figure 4.2.5: Forward-reverse bias.

With a simple pair of diodes we'd expect the B-E loop to show a high current and the B-C loop show negligible current. With a
BJT, this is not what happens. Instead, what we see is a high current in both loops, and those currents are very nearly equal in
magnitude. How does this come about?
The key to understanding this situation is that the base of the BJT is thin and lightly doped. In contrast, the dual diode model splits
the base into two separate pieces of material and that makes all the difference. To get a better handle on what's happening here, let's
take a closer look at this forward-reverse bias circuit but this time substituting the transistor diagram of Figure 4.2.2. Refer to
Figure 4.2.6.

Figure 4.2.6: Forward-reverse bias, electron flow.

Electron flow will facilitate this explanation so we'll draw the current directions using dashed lines. From the left side of the
diagram, electrons exit the emitter supply and enter the N emitter. Here they are the majority carrier. The base-emitter depletion
creates an energy hill just as it did with a single PN junction. As long as there is sufficient potential from the emitter supply, the
electrons will be pushed into the base. These electrons will attempt to recombine with the majority base holes, however, because
the base is physically thin and lightly doped, only a small percentage of the injected electrons will recombine with base holes and
exit the base terminal back to ground. This current is called the base current current or the recombination current. Meanwhile, the
vast majority of the remaining electrons (95% to over 99%) will find their way to the base-collector depletion region and then to
the collector. Once in the collector, the electrons are again the majority carrier and flow back to the positive terminal of the
collector power supply. The energy diagram of the transistor is depicted in Figure 4.2.7. Compare this to the single PN junction
energy diagram found at the beginning of Chapter 2, Figure 2.1.2.

Figure 4.2.7: Energy diagram of BJT.

At first glance, it might appear as though the emitter and collector leads can be swapped with no change in operation. With real-
world devices this is not possible generally because the emitter and collector regions are optimized and not physically identical.

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Thus, placing transistors into a circuit backwards, with emitter and collector leads swapped, will usually result in unpredictable
behavior.
Based on the foregoing discussion and what we already know about PN junctions, we can summarize transistor performance as
follows:
From KCL, I = I + I .
E C B

IC ≫ I B , therefore I ≈ I .
E C

The base-emitter junction is forward-biased, therefore V ≈ 0.7 V (silicon).

BE

The base-collector junction is reverse-biased, therefore V CBis large.

Conventional current flows into the collector and base, and out of the emitter.
We can also define a couple of transistor performance parameters. The ratio of collector current to emitter current is called α
(alpha). α typically is greater than 0.95. A somewhat more useful parameter is the ratio of collector current to base current. This is
called β (beta) and can also be found on transistor spec sheets as h FE (hFE is one of four hybrid parameters). It is also referred to
generically as current gain (if I is in the input signal and I is the output signal then β represents the amount of signal boost or
B C

gain). For small signal transistors β typically is in the range of 100 to 200, although it can be larger. For power transistors, β tends
to be smaller, more like 25 to 50. Presented as formulas we have:

α = IC / IE (4.2.1)

β = IC / IB (4.2.2)

And with a little math,

α = β/(β + 1)

β = α/(1 − α)

IC = β IB

Finally, we come to the schematic symbol of the NPN BJT, as shown in Figure 4.2.8. A common variation places the body of the
device within a circle. Following the standard, the arrow points to N material and in the direction of easy conventional current flow.

Figure 4.2.8: NPN Schematic symbol

4.2.3: The PNP Bipolar Junction Transistor

The PNP version of the BJT is created by swapping the material for each layer. The outcome is the logical inverse of the NPN
regarding current directions and voltage polarities. That is, conventional current flows into the emitter, and out of the collector and
base (echoing the electron flow of the NPN). Further, voltages across the device have reversed polarity, for example, V ≈ −0.7BE

V. All of the other characteristics remain unchanged so equations such 4.2.1 and 4.2.2 are still applicable. Just about any NPN-
based circuit has its PNP counterpart. The schematic symbol of the PNP reverses the emitter arrow. As the base is now the N
material, the arrow points toward the base. This is illustrated in Figure 4.2.9.

Figure 4.2.9: PNP Schematic symbol

References
1
Homer says, “Mmm, NPN layer cake sandwich...”

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4.3: BJT Collector Curves
One of the more useful BJT device plots is the family of collector curves. This is a series of plots of collector current, I , versus
C

collector-emitter voltage, V , at varying levels of base current, I . To generate these curves we drive the base terminal with a
CE B

fixed current source establishing I . A DC power supply is attached from the collector to emitter and then swept from zero volts to
B

some upper value. This establishes V . Simultaneously, we track the resulting collector current and plot the result. This results in
CE

one trace. The base current is then increased and the DC supply swept again for a second trace. This process is repeated to create a
family of curves. An example is shown in Figure 4.3.1.

Figure 4.3.1: A family of collector curves.

The bottom curve results when I = 0 . Ideally, the corresponding collector current would be 0 but a small leakage current occurs.
B

This is usually referred to as I

C EO , meaning the C ollector-E mitter current with the base terminal Open (i.e., no base current). The
curves above this correspond to increasing levels of base current; each new base current stepping up a fixed amount for each
subsequent trace (e.g., 0 μ A, 10 μ A, 20 μ A, 30 μ A, etc.).
The most striking thing about this set of curves is that there are three distinct regions or zones of operation. To the extreme left of
the curve the current rises rapidly. This is known as the saturation region. The break-over point is fairly small at just a few tenths of
a volt. This can be found on a data sheet as V . The saturation region is used in transistor switching applications.
C E(sat)

At the extreme right is another region where the collector current rises rapidly. This is called the breakdown region. This is the
same effect we saw with individual diodes. We do not wish to operate devices in this region as damage may result. The breakdown
voltage is denoted on most data sheets as BV C EO
(C ollector to E mitter voltage with an Open base). For general purpose devices
this will be in the range of 30 to 60 volts or so, but it can be much higher.
In between these two extremes is a region where the collector current is relatively constant, showing only a modest positive slope.
This is the constant current region. This is where we want the transistor to operate for applications such as linear amplifiers.
A device called a curve tracer can be used to generate this family of curves in the lab. A very good approximation for β can be
determined using these curves. First, we determine the approximate circuit values for I and V , and locate this point on the
C CE

graph. We then find the nearest plot line to that point. From the intersection of V and and this plot line we track back to the
CE

vertical axis to find the precise value of I for that trace. We count the number of traces and multiply by the base current step size
C

to determine the corresponding base current. We then divide the two values and arrive at β.

Example 4.3.1

Assume we have a BJT operating at V = 30 V and I = 4 mA. If the device is placed in a curve tracer and the resulting
CE C

family of curves appears as in Figure 4.3.2, determine the value of β. Assume the base current is increased 10 μ A per trace.

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 Figure 4.3.2: Curve tracer display for Example 4.3.1.
First, find a trace close to the operating point of 30 volts and 4 mA. Draw a vertical line at 30 volts and stop when that line
intersects the trace nearest to 4 mA. In this example that's the second trace from the top. From that intersection point, track
back to the vertical axis to determine the precise collector current. That's roughly 4.2 mA here. To determine the base current
count up the number of traces to the selected trace. The selected trace is the fourth one up (do not include the bottom trace
where I is 0). The base current is increased by 10 μ A per trace so that leaves us with I = 40 μ A.
B B

IC
β =
IB

4.2mA
β =
40μA

β = 105

4.3.1: Rise in β and Early Voltage

When looking at the collector curves, a good question we might ask is why the collector current rises as V increases. This is due
CE

to the fact that the increased collector-emitter voltage is responsible for an increase in collector-base voltage (by definition,
VCE =V CB +V BE). V CBis the reverse-bias potential on the collector-base PN junction. As this reverse potential increases, the
collector-base depletion region widens. As it widens, it penetrates further into the base layer. Because the base is effectively
narrowed, the chances for recombination are reduced, thus reducing base current and effectively increasing β.
If we extend the constant current region traces back into the second quadrant they intersect at a point called the Early Voltage,
named after James Early, and denoted as V . This is illustrated in Figure 4.3.3.
A

Figure 4.3.3: Early Voltage.

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4.4: BJT Data Sheet Interpretation
The data sheet for a common NPN transistor, the 2N3904, is shown in Figure 4.4.1. This model is available from several different
manufacturers. First off, note the case style. This a TO-92 plastic case for through-hole mounting and is commonly used for small
signal transistors. Under the maximums we find the device has a maximum power dissipation of 625 mW in free air (ambient
temperature of 25 C), a maximum collector current of 200 mA and a maximum collector-emitter voltage of 40 V. Obviously, the
∘

device cannot withstand maximum current and voltage simultaneously.

Figure 4.4.1a: 2N3904 data sheet. Used with permission from SCILLC dba ON Semiconductor.
In Figure 4.4.1b we find a variety of characteristics including nominal values for β (listed here as h ) under various conditions.
FE

At particularly small or large collector currents β tends to drop off. Also, note the wide 3:1 variance at 10 mA. Perhaps more
illustrative are the graphs from the third page, Figure 4.4.1c.

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 Figure 4.4.1b: 2N3904 data sheet (cont).
The upper-most graph depicts the variation of β with both collector current and temperature. The normalized β is plotted on the
vertical axis. That is, this is not the expected value but is a ratio used to compare β under varying conditions.

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 Figure 4.4.1c: 2N3904 data sheet (cont).
For example, at room temperature and 10 mA, the normalized value is 1.0. The second page indicated a range of 100 to 300 for the
2N3904's β under these conditions. Let's say we measure one particular transistor to have a β of 200. If we were to operate this
transistor at a lower current, say 0.2 mA, the β would drop. From the graph, the normalized β value at 0.2 mA and 25 C is 0.7. ∘

Therefore, the β under these conditions would be 0.7/1.0 ⋅ 200, or 140. The graph also shows that, generally speaking, β tends to
increase with increasing temperature.
The middle graph plots the collector-emitter saturation voltage, or V , for various current conditions. This is an important
C E(sat)

parameter when dealing with transistor switching circuits. We shall refer back to this graph a little later in this chapter.

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4.5: Ebers-Moll Model
A good, functional model of the BJT is the simplified Ebers-Moll model shown in Figure 4.5.1. This utilizes an ideal diode to
model the base-emitter junction and a current-controlled current source located at the collector-base. This model is sufficient to
achieve good analysis results with a variety of DC and low frequency circuits. It is important to remember, though, that β varies not
only from device to device, but also varies with changes in temperature, collector current and collector-emitter voltage.

Figure 4.5.1: Ebers-Moll model of the NPN BJT.

We can put the Ebers-Moll model to use in basic DC biasing circuits. To properly bias the BJT we need to make the collector-base
reverse-biased and the base-emitter forward-biased. In other words, V > V > V . There are many ways to achieve this. One
C B E

method places the emitter at ground, a modest DC source in the base-emitter loop, and a somewhat higher DC source at the
collector. An example is shown in Figure 4.5.2.

Figure 4.5.2: Simple base bias circuit.

The two resistors serve to limit the transistor's currents and voltages. Because the emitter is at ground, the common point, this
circuit is classified as having a common emitter configuration. There are many possible common emitter circuits. We shall refer to
this one specifically as base bias.
Now, let's replace the transistor with the Ebers-Moll model. The result, with added voltage polarities and current directions, is
shown in Figure 4.5.3.

Figure 4.5.3: Base bias circuit with EbersMoll model.

Given values for the resistors, power supplies and β, all of the currents and voltages may be determined using fundamental circuit
analysis techniques. The basic idea is to create KVL equations for the two loops and then expand using Ohm's law. We begin with
the base-emitter loop.

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 VBB = VR + VBE (4.5.1)
B

VBB = IB RB + VBE

VBB − VBE
IB =
RB

And for the collector-emitter loop:

VC C = VRC + VC E (4.5.2)

VC C = IC RC + VC E

VC E = VC C − IC RC

To obtain I , recall that I

C C = β IB .

Example 4.5.1

Determine the circulating currents and device voltages for the circuit of Figure 4.5.2 if V BB = 10 V, V
CC = 15 V, R
B = 200

kΩ, R = 1 kΩ and β = 100. Assume that the transistor is silicon.

C

First, find the base current. KVL dictates that the voltage across R is 9.3 volts.
B

VBB − VBE
IB =
RB

10V − 0.7V
IB =
200kΩ

IB = 46.5μA

Now find the collector current and follow with Ohm's law and KVL.

IC = β IB

IC = 100 × 46.5μA

IC = 4.65mA

VC E = VC C − IC RC

VC E = 15V − 4.65mA × 1kΩ

VC E = 10.35V

For the sake of completeness, the voltage across R is 4.65 volts, V

C CB is 9.65 volts and I is 4.6965 mA.
E

The preceding example illustrates that the place to start the analysis is in the baseemitter loop instead of the collector-emitter loop.
This is because in the base-emitter loop we have the forward-biased base-emitter junction which has a known potential
(approximately 0.7 volts). In contrast, the collector-emitter voltage is an unknown as it includes the reverse-biased collector-base
junction. That voltage will depend on other circuit elements, most notably the collector resistor and associated supply.
An improvement on the circuit of Example 4.5.1 would be to redesign it for a single power supply rather than two supplies. This is
easy to do. All that is needed is to keep the base current unchanged. If that remains at its original value then the collector current
won't change and consequently nothing in the collector-emitter loop will change either. Using the 15 volt source for V means BB

that the voltage across R will increase to 14.3 volts. Ohm's law then indicates that R must be 14.3 volts divided by 46.5 μ A, or
B B

307.5 kΩ.

4.5.1: β Variation Issues

There is a major problem with the circuit of Figure 4.5.2, namely, it lacks stability of collector current and collector-emitter
voltage. As we shall see in upcoming chapters, it is important to keep these parameters stable in order to ensure consistent
performance for many kinds of circuits. As we noted from our inspection of the 2N3904 data sheet, the variation of β can be quite
large at a given operating point. If we also add in the variance due to temperature and other factors, we may be looking at a 10:1
range. If we repeat Example 4.5.1 with a doubled β of 200, the base-emitter loop is unchanged but the collector current doubles to

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9.3 mA. This increases the voltage drop across R to 9.3 volts which then forces V
C CE to drop to 5.7 volts. Given a typical
production run of transistors, this circuit might exhibit collector currents from less than 4 mA to more than 10 mA. In some
applications this variation in current might be tolerable but not in all of them. For example, suppose an LED is placed in series with
R . Because the brightness of an LED depends on its current level, the brightness will now depend on the β of the specific BJT
C

used. If this is one LED in a larger display made up of similar circuits, then the illumination will be uneven between them causing
the entire display to appear off kilter.
In fact, if this circuit was built in the lab, it is quite likely that after turning on the power, you could watch I slowly rise on your
C

ammeter. This is because the BJT will begin to warm up as it dissipates power. As noted from the data sheet, β increases with
increasing temperature. Because I is a fixed value, any rise in β means that I must also rise. This increased current will tend to
B C

cause a further rise in power dissipation and temperature which causes a further increase in β, and the process cycles. We have
created an inadvertent thermal positive feedback loop. Left unchecked, devices could overheat and be destroyed. We will examine
biasing circuits that achieve high stability in the next chapter.
There is another interesting aspect to this circuit. As noted, if we substituted the original BJT with another unit that had a higher β,
the collector current would rise. What if we continued this to higher and higher β values? For example, if we increased β to 400
(admittedly, rather high) the new collector current would seem to jump up to 46.5 μ A ⋅ 400, or 18.6 mA. There is a “small”
problem with this value. Ohm's law indicates that this current would develop a drop of 18.6 volts across the 1 kΩ R but that's C

impossible because V CC is only 15 volts. The only way that “works” is if somehow the BJT is transformed magically into a 3.6
volt battery. No amount of prayer or letters to Santa will make that happen1.

References
1Both being equally effective.

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4.6: DC Load Lines
So how do we determine the range of possible values of collector current and collector-emitter voltage in any given DC BJT
circuit? One answer is to employ the concept of the DC load line. In general, a load line is a plot of all possible coordinate pairs of
IC and V for a transistor in a given circuit. Referring back to Figure 4.5.3, we pick up with Equation 4.5.2 and solve it for I :
CE C

VC E = VC C − IC RC (4.6.1)

1
IC = (VC C − VC E )
RC

1 VC C
IC = − VC E +
RC RC

Equation 4.6.1 is a linear equation of the form y = mx + b . The y intercept (the value of I when V = 0 ) is V /R . This is
C CE CC C

the maximum collector current that can be achieved. At this point the transistor is saturated and this maximum is referred to as
I . The x intercept (the value of V
C (sat) CE
when I = 0 ) is V . This represents the largest possible voltage across the transistor's
C CC

collector-emitter. At this point the current is cut off, and therefore this voltage is called V . Lastly, the slope of the line is
C E(cutof f )

−1/R . A plot is shown in Figure 4.6.1.

C

Figure 4.6.1: Generic DC load line.

To complete the graph, we also include the operating point for some specific transistor. This is called the quiescent point, or Q
point, and the associated device current and voltage are called I and V
CQ . All possible Q points lay on this line.
C EQ

Referring back to Example 4.5.1 and using Equation 4.6.1, we can summarize the circuit as follows:
IC (sat) = 15mA

VC E(cutof f ) = 15V

Q Point for β = 100 :

IC = 4.65mA

VC E = 10.35V

Q Point for β = 200 :

IC = 9.3mA

VC E = 5.7V

This is plotted in Figure 4.6.2.

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 Figure 4.6.2: Load line for the variations on Example 4.5.1.
If we calculate a collector current that is greater than the saturation current, then we know that the actual current will be the
saturation current maximum. For this circuit, any calculated value greater than 15 mA indicates that the transistor would produce
only 15 mA (our earlier example using β = 400, for instance). In reality, the true value will be very slightly less. This is because the
collector-emitter voltage does not go all the way down to zero volts when the device is saturated. Typically, V will be a tenth
C E(sat)

of a volt or so for small signal devices. Precise values can be determined from device graphs such as the middle graph of Figure
4.4.1c, labeled “Collector Saturation Region”. As an example, if I = 10 mA and I = 0.3 mA, then V
C B is approximately
C E(SAT )

0.15 V. It turns out that we can use saturation to our advantage in switching circuits, as we are about see.

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4.7: BJT Switching and Driver Applications
As mentioned, variation in β can cause changes in collector current. This can cause performance issues. For example, when driving
an LED, this can lead to variance in brightness. But what if we purposely put the transistor into saturation? Saturation is a fixed
value. It is inherently stable and β no longer matters. Effectively, when a BJT saturates, β is forced to drop to whatever value is
needed to produce I C (sat). We just need to make sure that even the smallest β is large enough to cause saturation.

4.7.1: The Saturating Switch

A good example of this is the saturating LED driver circuit shown in Figure 4.7.1. To begin with, the whole point of the driver is to
offload the current demand from the prior circuit. For example, we may wish to light an LED from the output of a logic gate or
microcontroller chip. The problem is that those circuits might only be able to deliver, say, 5 mA when we might need well over 10
mA to achieve the desired brightness. The LED driver circuit is used to overcome this limitation.

Figure 4.7.1: Saturating LED driver circuit (positive logic). Note: The negative terminal of VCC is connected to ground (not
shown).
With the driver, the logic circuit will only need to supply base current, not LED current. Here is how it works: If the logic input
voltage is zero, there will be no base current. This means that there will be no collector current and therefore the LED will be off.
At this point the BJT is in cutoff. In contrast, when the logic level goes high, all of the logic voltage drops across R , with the
B

exception of V . This creates I . If properly designed, this current will be sufficient to put the BJT into saturation. The BJT acts
BE B

as a switch, completing the circuit between the DC supply, the LED and the current limiting resistor, R . For this to work reliably,
C

we have to make sure that the ratio of saturation current to base current is much less than β. A value of 10 or so would guarantee
hard saturation.
If we would like to invert the logic, that is, have a logic low turn on the LED and a logic high turn it off, we can achieve that with a
PNP version of the circuit as shown in Figure 4.7.2.

Figure 4.7.2: Saturating LED driver circuit (negative logic).

Example 4.7.1

Determine the LED “on” current for the circuit of Figure 4.7.3 . Assume the logic “on” voltage is 5 volts, VLED = 1.8 volts
and V = 0.
C E(sat)

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 Figure 4.7.3: Circuit for Example 4.7.1.
First, find the base current.
Vlogic − VBE
IB =
RB

5V − 0.7V
IB =
4.7kΩ

IB = 915μA

Now find I C (sat)

, making sure the BJT is in saturation. This will be the LED current.
VC C − VLED
IC (sat) =
RC

5V − 1.8V
IC (sat) =
330Ω

IC (sat) = 9.7mA

The ratio of these two currents is just over 10:1. This will guarantee hard saturation.

There are many different applications for saturating switches. Just about anywhere you can imagine a relay being used, you can
consider a transistor switch. The transistor switch has the advantages of small size, no moving parts to wear out and very fast
switching speeds. Relays have the advantage for very high currents. Figure 4.7.4 shows an example of direct motor drive using a
saturating BJT switch.

Figure 4.7.4: Direct DC motor drive.

This circuit is used to control the speed of a DC motor through a technique called pulse width modulation. The speed of the motor
will depend on the average voltage applied to it. The trick here is that instead of applying a continuously variable voltage to the
motor, we instead apply a series of pulses of varying width. These pulses are sufficient to saturate the BJT, causing it to behave as a
switch. These pulses are so fast that the motor does not start and stop, but rather inertia keeps it going. Instead, the motor responds
to the averaged value of these pulses. If the pulses are narrow and widely spaced, the average value will be low and the motor
speed will be slow. If the pulses are wide and closely spaced, the average will high and the motor speed will be fast.
The resistor and capacitor at the base are used to shape the incoming pulse to improve performance. The diode across the motor
winding is particularly important. It is referred to as a snubbing diode1. Without it, the switching transistor might experience large
and damaging transient spikes. Here's why: Let's assume the BJT is on and conducting fully. This current is the same current
flowing through the motor's armature, which is little more than a huge coil of wire. That means it exhibits a lot of inductance.

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When we turn off the transistor, we are attempting to turn off the armature current, but the current through an inductor cannot
change instantaneously. The result is that the winding now generates a large flyback voltage (also called an “inductive kick”)
directly across the BJT. That is, the winding momentarily appears as a high voltage source of opposite polarity and, via KVL, this
potential appears from collector to emitter. This could damage the BJT. The snubbing diode effectively short-circuits the winding
when it reverses voltage polarity, preventing the large spike. The remainder of the time the diode is reverse-biased and effectively
out of the circuit.

4.7.2: The Non-Saturating Driver

It is also possible to create a switch or driver that is non-saturating. An example of a non-saturating LED driver is shown in Figure
4.7.5.

Figure 4.7.5: Non-saturating LED driver circuit (positive logic).

The advantage of this circuit is that it requires less current from the logic circuit. Unfortunately, it also exhibits higher transistor
power dissipation and requires a DC source that is higher than the logic level. The operation is as follows: As in the saturating
driver, if the logic level is zero, there is no rise in the base-emitter loop and the collector current will also be zero. With a high logic
voltage, via KVL around the base-emitter loop, all of the logic input voltage drops across R , with the exception of V . This
E BE

creates I which is virtually the same as I (which is I

E C LED ).
This circuit “programs” the emitter current via the resistor and logic voltage. Therefore it is fixed and stable. This process is
sometimes referred to as bootstrapping. It might be said that the emitter voltage is “bootstrapped” to within 0.7 volts of the logic
input level, keeping it stable2. In any case, if β varies, this will cause an inverse change in I with no change in I . A negative
B C

logic PNP version is also possible and left as an exercise.

Example 4.7.2

Determine the LED “on” current for the circuit of Figure . Assume the logic “on” voltage is 5 volts,
4.7.6 VLED = 1.8 volts
and β = 100.

Figure 4.7.6: Circuit for Example 4.7.2.

We can find I directly because I
C C ≈ IE . This will be the LED current.
Vlogic − VBE
IC =
RE

5V − 0.7V
IC =
270Ω

IC = 15.9mA

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 Note that β was not used. All it tells us is that I B = 15.9 mA/100, or 159 μ A. A higher β would simply lead to a lower base
current.
For the sake of completeness, we might also note that

VC E = VC C − VLED − VRE

VC E = 10V − 1.8V − 4.3V

VC E = 3.9V

Clearly, if V
CE is 3.9 volts, the transistor is not in saturation.

4.7.3: The Zener Follower

In the prior chapter we examined a method of regulating the output voltage of a filtered full-wave rectifier through the use of a
Zener diode. The downfall of that specific circuit is that it was not particularly efficient because it drew a fair amount of current
even when the demand for load current was light. Using the concept of locking one voltage to another, as in the non-saturating
switch, we can create a nice improvement, the Zener Follower.
A Zener Follower is shown in Figure 4.7.7 . The input signal is the positive rectified and filtered output of the AC-to-DC power
supply.

Figure 4.7.7: Zener Follower.

The primary thing to notice is that the Zener diode is reverse-biased via resistor R . That is, a current will flow down through R and
into the Zener. The Zener presents a fixed potential, V . Consequently, the difference between the input voltage and V must drop
Z Z

across R , and by extension, V . Further, the final output voltage is the voltage at the BJT's emitter which must be V − V . As
CB Z BE

these are both fixed, stable potentials, the output must likewise be a fixed, stable voltage. Lastly, because V = V + V , it is
CE CB BE

apparent that any variation between the input voltage and the desired output (for example, due to ripple) must be dropped across the
BJT.
The diode current is kept low in the Zener Follower and thus its power dissipation is also modest. Further, current draw from the
input circuit is a direct reflection of load current demand. If the load current requirement is low, very little current will flow through
the transistor, and ultimately, from the input circuit. This makes for a more efficient system.

References
1
It is also known as a commutating diode, clamp diode, flyback diode and by a host of other names. But as Shakespeare said, “A
snubbing diode by any other name would clamp a flyback voltage as well”. Or something like that.
2
This is in reference to the old phrase “pulling yourself up by your bootstraps”. To be honest, that saying never made sense to this
author and all that ever happened when I tried to do it was that my arms got tired.

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4.8: Summary
A bipolar junction transistor may be thought of as an extension of a simple diode or PN junction. Another layer of doped material is
added, resulting in either an NPN or PNP configuration, both with two depletion regions. The two depletion regions create two hills
in the energy diagram. The three terminals of the device are called the emitter, base (middle) and collector. BJTs are not normally
constructed symmetrically and swapping the collector and emitter can result in unpredictable behavior.
For proper operation, the base-emitter junction is forward-biased while the collectorbase junction is reverse-biased. This results in
the emitter and collector currents being very nearly equal and much, much larger than the base current. The ratio of collector
current to base current is called β (beta) while the ratio of collector current to emitter current is called α (alpha). β in particular is
subject to wide variations and it can have a major impact on circuit parameters. A plot of collector current versus collector-emitter
voltage reveals the three main regions of the BJT circuit: saturation, constant current and breakdown.
The Ebers-Moll model consists of a diode from the base to emitter and a controlled current source from the collector to base. This
simple model of the BJT can be used to solve a variety of transistor circuits, particularly when used in conjunction with a DC load
line. The DC load line is a plot of all possible operating points for a given transistor circuit.
Finally, it is possible to create switching and driver circuits using BJTs that produce stable output currents. These may utilize
saturating or non-saturating configurations with NPN or PNP devices.

4.8.1: Review Questions

1. Describe the energy diagram for a forward-reverse biased BJT.
2. Define α .
3. Define β.
4. Define Early voltage. What is its significance?
5. What is a family of collector curves? What information can we derive from it?
6. Describe the Ebers-Moll BJT model.
7. Explain some of the issues involving variation of β.
8. What is a DC load line?
9. How is a saturating switch different from a non-saturating driver? What are the advantages and disadvantages of each?
10. What is a Zener Follower?

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4.9: Exercises
4.9.1: Analysis Problems
1. Determine β if α = 0.99.
2. Determine α if β = 200.
3. Determine the currents for the circuit of Figure 4.9.1 if V
BB =5 V, V CC = 20 V, R B = 200 kΩ, R C =2 kΩ, β = 100.
4. Determine the transistor voltages for the circuit of Figure 4.9.1 if VBB = 5 V, VC C = 20 V, RB = 200 kΩ, RC = 2 kΩ, β =
200.

Figure 4.9.1
5. Determine the LED current in the circuit of Figure 4.9.2 if V logic =5 V, V CC =5 V, V LED = 2.1 V, R B = 3.6 kΩ, R C = 270

Ω , β = 100.

Figure 4.9.2
6. Determine the LED current in the circuit of Figure 4.9.2 if V logic =0 V, V CC =5 V, V LED = 2.1 V, R B = 3.6 kΩ, R C = 270

Ω , β = 100.

7. Determine the LED current in the circuit of Figure 4.9.3 if V logic =5 V, V EE =5 V, V LED = 2.2 V, R B = 2.7 kΩ, R C = 220

Ω , β = 100.

Figure 4.9.3
8. Determine the LED current in the circuit of Figure 4.9.3 if V logic =0 V, V EE =5 V, V LED = 2.2 V, R B = 2.7 kΩ, R C
= 220

Ω , β = 100.

9. Determine the LED current in the circuit of Figure 4.9.4 if V logic = 3.6 V, V CC = 10 V, V
LED = 2.3 V, R E ,
= 270 Ω β = 200.

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 Figure 4.9.4
10. Determine the LED current in the circuit of Figure 4.9.4. V logic =0 V, V CC = 10 V, VLED = 2.3 V, R E = 270 Ω β , = 200.
11. Using the 2N3904 data sheet, determine V C E(sat) if IC = 30 mA and I B =1 mA.
12. Using the 2N3904 data sheet, determine the percent change in β if I C = 10 mA and the temperature rises from 25 C to 125 C.
∘ ∘

13. Using the 2N3904 data sheet, determine the percent change in β if I C = 40 mA and the temperature drops from 25 C to −55 ∘

∘
C.

4.9.2: Design Problems

14. Using Figure 4.9.1, determine a value for R to set I to 5 mA if V
B C BB =5 V, VCC = 25 V, R C =2 kΩ, β = 100.
15. Using Figure 4.9.1, determine a value for R to set V
C CE to 6 V if V BB = 10 V, V CC = 25 V, RB = 330 kΩ, β = 200.
16. For the circuit of Figure 4.9.2, determine a value for RC to set the LED current to 15 mA. Vlogic = 5 V, VC C = 5 V,
V = 1.6 V, R
LED B = 3.3 kΩ .

17. For the circuit of Figure 4.9.3, determine a value for RC to set the LED current to 20 mA. Vlogic = 0 V, VEE = 5 V,
V = 2.0 V, R
LED B = 2.7 kΩ .

18. For the circuit of Figure 4.9.4, determine a value for RE to set the LED current to 25 mA. Vlogic = 5 V, VC C = 9 V,
V = 2.8 V.
LED

4.9.3: Challenge Problems

19. Determine the maximum and minimum values for I in the circuit of Figure 4.9.1 if all resistors have a 10% tolerance and β =
C

ranges from 100 to 200. V = 5 V, V = 20 V, R = 200 kΩ, R = 2 kΩ.

BB CC B C

20. Derive and draw a PNP non-saturating LED driver circuit.

4.9.4: Computer Simulation Problems

21. Simulate the circuit of Problem 3.
22. Simulate the circuit of Problem 5.
23. Simulate the circuit of Problem 7.
24. Verify the design of Problem 14 using a simulator.

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 CHAPTER OVERVIEW

5: BJT Biasing
Learning Objectives
After completing this chapter, you should be able to:
Explain the need for DC biasing of BJT amplifiers.
Solve various BJT biasing circuits for device currents and voltages.
Plot DC load lines for a variety of BJT biasing circuits.
Discuss methods to increase circuit stability with regard to transistor parameter variation.

5.1: Introduction
5.2: The Need For Biasing
5.3: Two-Supply Emitter Bias
5.4: Voltage Divider Bias
5.5: Feedback Biasing
5.6: Summary
5.7: Exercises

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1
5.1: Introduction
As we saw in the preceding chapter, a bipolar junction transistor requires a forward-bias of the base-emitter junction and a reverse-
bias of the collector-base junction in order to operate properly. One of the prime BJT parameters is the current gain, β. It can have a
considerable impact on the operation of the circuit. Unfortunately, β also varies with changes in temperature, collector-emitter
voltage, etc., and this can lead to circuit instability. In this chapter we shall investigate a variety of circuit topologies to bias the
BJT, always with an eye toward stability.

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5.2: The Need For Biasing
Why bias a transistor in the first place? After all, if the device exhibits current gain (i.e., β), why not just apply an AC signal at the
base and obtain an amplified version of it at the collector? The first thing to remember is that current gain is an outgrowth of
forward-reverse bias. Given that fact, and without an additional source of energy, amplification cannot be produced. Also,
remember the magnitude of the energy hill required for forward-biasing the base-emitter. In order to achieve that, V needs to be
BE

around 0.7 volts. If we simply applied an AC signal to the base, we could only hope to forward-bias the base-emitter when that
signal exceeded 0.7 volts. The entire negative half of the AC signal would be ignored along with everything positive that's below
0.7 volts. Seeing that the voltage generated from many input devices such as microphones and sensors may only be a few hundred
millivolts, the entire signal could be ignored! The solution to these problems is to apply a DC bias to the transistor and then
superimpose the AC signal on top of that. In other words, if the AC voltage is riding on a much larger DC voltage, then even the
negative peak of the AC signal will be a net positive voltage, and we can maintain proper transistor function.
There are numerous ways to establish a proper polarity DC bias on a transistor. The trick is to find ways to make a stable bias, that
is, to establish a Q point that doesn't move in spite of parameter changes such as changes in β. As we shall see in following
chapters, an unstable Q point can have negative effects on the AC performance of an amplifier. For example, it could make the gain
unstable, increase distortion or reduce output power. This lack of stability is a major problem with the base bias configuration
examined in the prior chapter. What we would like is a circuit that will establish a collector current that does not shift even when β
changes.

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5.3: Two-Supply Emitter Bias
For proper functioning, the collector-base junction needs to be reverse-biased and the base-emitter junction needs to be forward-
biased. For an NPN transistor that means that the collector must be at the highest potential, the base somewhat lower and the
emitter at the lowest potential of the three. One way of doing this is to apply the usual positive supply to the collector, but instead
of using a second potential at the base, the base is tied to ground through a resistor. The requisite forward-bias on the base-emitter
is then achieved by connecting the emitter to a negative power supply. This circuit configuration is shown in Figure 5.3.1 using an
NPN device. We shall refer to this as two-supply emitter bias.

Figure 5.3.1: Two-supply emitter bias, NPN version.

We can derive an equation for the collector current by applying KVL to the baseemitter loop:

VEE = VRB + VBE + VRE

VEE = IB RB + VBE + IE RE

Recalling that I B = IC /β and I

E ≈ IC ,

VEE = (IC /β)RB + VB E + IC RE

Solving for I we arrive at

C

∣ VEE ∣ −VBE
IC = (5.3.1)
RE + RB /β

The absolute value has been added to the emitter supply voltage so there is no confusion regarding the sign of this potential in the
equation.
The thing to notice about Equation 5.3.1 is that β only partly determines the collector current. In fact, if we can make
R E≫ R /β , then the equation reduces to
B

∣ VEE ∣ −VBE
IC ≈ (5.3.2)
RE

It is relatively easy to achieve the R ≫ R /β stipulation. Given typical values of β, this will be the case if R is approximately
E B E

equal to or larger than R . What we find in this instance is that almost all of the emitter supply drops across R to establish a
B E

stable I with β playing virtually no role. If β changes, the result will be an inverse change in I with I remaining largely
C B C

unchanged.
Now that we have the collector current, any other current or voltage in the circuit may be derived by applying Ohm's law, KVL and
the like. For example, to find V , the voltage from the collector to ground,
C

VC = VC C − VR
C

VC = VC C − IC RC

And to find the transistor's collector-emitter voltage, V CE ,

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 VC E = VC C + ∣ VEE ∣ −VRC − VRE (5.3.3)

VC E = VC C + ∣ VEE ∣ −IC RC − IC RE

VC E = VC C + ∣ VEE ∣ −IC (RC + RE )

Note that VCE can also be found via V

CE = VC − VE . Dropping voltages along the base-emitter loop yields

VE = −VRB − VBE

VE = −IB RB − VBE

Also, it is to our advantage to develop the DC load line for this configuration. The load line can serve as a “sanity check” for our
computations. To find the endpoints, I C (sat)is the maximum current and will occur when V = 0 . If we imagine the current
CE

rising as V
CE
collapses, eventually all of the available supply voltage will have dropped across R and R . Thus
C E

VC C + ∣ VEE ∣
IC (sat) = (5.3.4)
RC + RE

Similarly, V occurs when I = 0 . That means that there will be no potentials across
C E(cutof f ) C RC and RE . Therefore, VC E

“absorbs” the entire available source voltage.

VC E(cutof f ) = VC C + ∣ VEE ∣
∣ (5.3.5)

Do not attempt to memorize all of the myriad equations presented. There are simply too many variations on the theme and it will
only get worse when other biasing configurations are introduced. Instead, remember how to find the collector current and then get
in the habit of applying Ohm's law and KVL to derive whatever else you may need.
At this point a comprehensive example is called for.

Example 5.3.1

Assuming β = 100, plot the Q point (I and VC CE ) on the load line for the circuit of Figure 5.3.2.

Figure 5.3.2: Circuit for Example 5.3.1.

Using Equation 5.3.1:
∣ VEE ∣ −VBE
IC =
RE + RB /β

10 − 0.7
IC =
2.7kΩ + 5.1kΩ/100

IC = 3.38mA

Noting the relative sizes of R and R , the approximation should be close.

E B

∣ VEE ∣ −VBE
IC =
RE

10 − 0.7
IC =
2.7kΩ

IC = 3.44mA

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 To find VCE we can use the equation derived above (Equation 5.3.3).

VC E = VC C + ∣ VEE ∣ −IC (RC + RE )

VC E = 20V + 10V − 3.38mA(3.3kΩ + 2.7kΩ)

VC E = 9.72V

Now calculate the load line endpoints:

VC C + ∣ VEE ∣
IC (sat) =
RC + RE

20V + 10V
IC (sat) =
3.3KΩ + 2.7KΩ

IC (sat) = 5mA

VC E(cutof f ) = VC C + ∣ VEE ∣
∣

VC E(cutof f ) = 20V + −10V

VC E(cutof f ) = 30V

The load line for the circuit in Example 5.3.1 is shown in Figure 5.3.3.

Figure 5.3.3: DC load line for the circuit of Figure 5.3.2.

Note the proportions between voltage and current for the Q point. The voltage is a little less than one-third of the maximum
while the current is a little more than two-thirds of its maximum.

5.3.1: Verification of Stability

The claim was made that two-supply emitter bias circuits like the one Figure 5.3.1 potentially have a stable Q point. If we were to
plot a second Q point for a large change in β, it should hardly move, thus indicating very high stability. For example, doubling β to
200 results in I = 3.41 mA and V = 9.53 V. The new Q point has edged just slightly closer to saturation, producing about a
C CE

1% change in current for a 100% change in β. Clearly, this configuration can produce very small changes in the Q point in spite of
very large changes in β.

5.3.2: Computer Simulation

The two-supply emitter bias circuit of Figure 5.3.4 is simulated using the DC Bias function. A quick estimation shows that we
expect about 2 mA of collector current (9.3 V/4.7 kΩ) and a collector voltage of about 8 volts (15 V − 2 mA ⋅ 3.6 kΩ). We also
expect a small negative potential at the base −I R ). Given typical β values for the 2N3904 (200-ish at this current, refer back to
B B

the data sheet), we expect a base current of around 10 to 15 μ A, leaving us with a V of approximately −0.1 volts. The emitter
B

voltage would be about 0.7 volts less than that, perhaps −0.8 volts or so.
In short, for a properly designed circuit of this type we expect V to be pretty close to 0 V and V to be about −0.7 volts.
B E

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 Figure 5.3.4: Schematic for two-supply emitter bias simulation.
The results are shown in Figure 5.3.5. The node voltages agree with our estimations. Node 3 is the collector voltage, very close to
the estimation. The results for the base voltage (node 2) and the emitter voltage (node 1) are also in line with the estimates.

Figure 5.3.5: Simulation results for twosupply emitter bias circuit.

5.3.3: PNP Two-Supply Emitter Bias

While it is possible to create a PNP version of bias circuits by simply swapping out the device and then changing the signs of the
power supplies, it is common to “flip” the entire circuit from top to bottom so that the emitter winds up on top and the collector on
the bottom. One advantage of this is that, in a multi-transistor circuit schematic, all of the DC bias currents “run down the page”,
that is, the collector currents flow from the top of the page to the bottom of the page. Figure 5.3.6 shows a PNP two-supply emitter
bias circuit.

Figure 5.3.6: PNP two-supply emitter bias circuit.

All of the device current equations and component voltage equations derived for the NPN version will hold for the PNP version.
The differences to remember are that the voltage polarities will be reversed (what was positive in the NPN is negative in the PNP)
and the current directions will be reversed (e.g., conventional current flows into the NPN's collector but out of the PNP's collector.
For example, in the NPN we expect the base current to flow into the base terminal. This creates a small negative voltage at the base
and a somewhat more negative voltage (by 0.7 V) at the emitter. In the PNP, the base current flows out of the base. This creates a

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small positive voltage at the base and results in the emitter being slightly more positive (by 0.7 V). This is perhaps best illustrated
with an example.

Example 5.3.2

Assuming β = 100, determine the Q point and load line endpoints of the circuit of Figure 5.3.7.

Figure 5.3.7: Circuit for Example 5.3.2.

First, note that this is a PNP drawn upside down so the emitter is at the top. Using Equation 5.3.1:
∣ VEE ∣ −VBE
IC =
RE + RB /β

15 − 0.7
IC =
10kΩ + 15kΩ/100

IC = 1.409mA

As a cross check, noting the relative sizes of R and R , the approximation should be close.
E B

∣ VEE ∣ −VBE
IC =
RE

15 − 0.7
IC =
10kΩ

IC = 1.43mA

To find V CE we can use Equation 5.3.3 with a slight modification.

VC E = VEE + ∣ VC C ∣ −IC (RC + RE )

VC E = 15V + 25V − 1.409mA(12kΩ + 10kΩ)

VC E = 9V

We complete the picture by determining the endpoints of the load line.

VEE + ∣ VC C ∣
IC (sat) =
RC + RE

10V + 25V
IC (sat) =
12KΩ + 10KΩ

IC (sat) = 1.818mA

VC E(cutof f ) = VEE + ∣ VC C ∣
∣

VC E(cutof f ) = 15V + 25V

VC E(cutof f ) = 40V

The Q point is about 3/4ths of the maximum current and 1/4th of the maximum voltage.

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5.4: Voltage Divider Bias
Another configuration that can provide high bias stability is voltage divider bias. Instead of using a negative supply off of the
emitter resistor, like two-supply emitter bias, this configuration returns the emitter resistor to ground and raises the base voltage. So
as to avoid issues with a second power supply, this base voltage is derived from the collector power supply via a voltage divider.
The bias template is shown in Figure 5.4.1.

Figure 5.4.1: Voltage divider bias.

Let's derive the equations for the load line. First, let's consider the saturation and cutoff endpoints. For saturation, assume V CE goes
to 0. What resistances are left to limit the current?
VC C
IC (sat) = (5.4.1)
RC + RE

occurs when I = 0 and that means that there will be no potentials across
VC E(cutof f ) C RC and RE . Therefore, VC E takes on the
entire available source voltage.

VC E(cutof f ) = VC C (5.4.2)

The key to finding the Q point (and pretty much any other current or voltage in the circuit) is to find I . To simplify the process,
C

Thevenize the voltage divider as shown in Figure 5.4.2.

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 Figure 5.4.2: Thevenizing the voltage divider.
By inspection of Figure 5.4.2b,
R2
VT H = VC C
R1 + R2

R1 R2
RT H = R1 || R2 =
R1 + R2

Now we can derive an equation for the collector current by applying KVL to the base-emitter loop of Figure 5.4.2c:

VT H = VR + VBE + VR
TH E

VT H = IB RT H + VBE + IE RE

Recalling that I B = IC /β and I

E ≈ IC ,

VT H = (IC /β)RT H + VBE + IC RE

Solving for I we arrive at

C

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 VT H − VBE
IC = (5.4.3)
RE + RT H /β

Can we find a quick approximation for I as well? If we assume that the voltage divider of R and R is lightly loaded, in other
C 1 2

words, that the divider current is much, much less than the base current, finding I is easy. The divider voltage yields the base
C

voltage. We then subtract the 0.7 volt drop on the base-emitter and what's left drops across R . From there it's one short
E

application of Ohm's law to get I , which is approximately equal to I . But how do we know if the divider is lightly loaded in the
E C

first place without going through the Thevenin equivalent? Looking at Equation 5.4.3, as long as R ≫ R /β , we can ignore
E TH

the second term in the denominator, leaving us with our quick approximation. Given typical values for β, as long as R is not much
2

larger than R , the approximation will be reasonably accurate.

E

Once I is obtained we can find the transistor's collector-emitter voltage, V

C CE ,

VC E = VC C − VRC − VRE (5.4.4)

VC E = VC C − IC RC − IC RE

VC E = VC C − IC (RC + RE )

Time for yet another thrilling illustrative example.

Example 5.4.1

Assuming β = 200, plot the Q point (I and V

C CE ) on the load line for the circuit of Figure 5.4.3. Also determine the value of
V .
B

Figure 5.4.3: Circuit for Example 5.4.1.

Calculate the load line endpoints so we know the maximums.
VC C
IC (sat) =
RC + RE

15V
IC (sat) =
3.9KΩ + 3.3KΩ

IC (sat) = 2.08mA

VC E(cutof f ) = VC C

VC E(cutof f ) = 15V

To obtain the Q point, first find the Thevenin values.

R2
VT H = VC C
R1 + R2

4.7kΩ
VT H = 15V
10kΩ + 4.7kΩ

VT H = 4.8V

R1 R2
RT H = R1 ∣∣ R2 =
R1 + R2

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 10kΩ × 4.7kΩ
RT H =
10kΩ + 4.7kΩ

RT H = 3.2kΩ

Using Equation 5.4.3:

VT H − VBE
IC =
RE + RT H /β

4.8V − 0.7V
IC =
3.3kΩ + 3.2kΩ/200

IC = 1.236mA

Noting the relative sizes of R and R , the approximation should be fairly accurate.
E 2

VT H − VBE
IC =
RE

4.8V − 0.7V
IC =
3.3kΩ

IC = 1.242mA

To find VCE we can use Equation 5.4.4.

VC E = VC C − IC (RC + RE )

VC E = 15V − 1.236mA(3.9kΩ + 3.3kΩ)

VC E = 6.1V

As far as finding V is concerned, a decent approximation would be the value of V

B TH because we have determined that the
divider is lightly loaded. In a more general sense, we could also find the drop across R and then add V . The approximation
E BE

yields 4.8 volts and the more accurate method yields

VB = VBE + IC RE

VB = 0.7V + 1.236mA × 3.3kΩ

VB = 4.78V

The load line for the circuit in Example 5.4.1 is shown in Figure 5.4.4.

Figure 5.4.4: DC load line for the circuit of Figure 5.4.3.

Once again the proportions between voltage and current for the Q point appear to be proper when compared against the
endpoints.

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5.4.1: Verification of Stability
How much does the Q point move if β were to get cut half? Recalculating with a β of 100 yields I = 1.23 mA and V = 6.14
C CE

V. This represents a shift in both current and voltage of less than 1%. This will, of course, cause a near doubling of I but this will
B

be hardly noticed here as the divider current is so much larger; approximately 15V/ (10 k + 4.7 k) or 1 mA versus about 1.23
mA/100 or 12.3 μ A.

5.4.2: PNP Voltage Divider Bias

To create the PNP version of the voltage divider bias, we replace the NPN with a PNP and then change the sign of the power
supply. As mentioned with the two-supply emitter bias, these circuits are usually flipped top to bottom resulting in the flow of DC
current going down the page. All of the currents and component voltages are unchanged except that their directions and polarities
are reversed. The current equations and so forth remain valid. Something a little odd-looking happens with the voltage divider bias,
though: we end up with ground being the most positive potential and a negative supply at the bottom of the schematic. It works, but
it's an issue if we're using a traditional positive supply elsewhere in the circuit. After all, why have two supplies where one will do?
It turns out that we can make a positive supply version fairly easily. All we need to do is add the magnitude of the negative source
voltage to the ground and power connections. This progression is shown in Figure 5.4.5.

Figure 5.4.5: Progression of PNP voltage divider bias circuit. a. Direct conversion from NPN. b. Top-to-bottom flip. c. DC supply
offset added to achieve a positive supply.
There is nothing magic about this procedure. In essence, all we've really done is renamed the reference point. All of the individual
component voltages remain unchanged. For example, looking at Figure 5.4.5c versus 5.4.5b, it is still the case that the top
connection to R is more positive than the bottom connection to R by the voltage V
E C (although we did rename the supply to
CC

VEE to be consistent with where it's connected). What has happened is that all ground-referenced (i.e., single subscript) voltages
have changed. For example, V in Figures 5.4.5a and 5.4.5b is the voltage across R . In contrast, V in Figure 5.4.5c is the
B 2 B

voltage across R . That makes sense. If we move the reference then any voltage that is measured against the reference will change.
1

When analyzing the PNP voltage divider, we could simply parrot the collector current formula developed for the NPN, but there
are other techniques. Two methods are illustrated in the following example.

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Example 5.4.2

Assuming β = 200, determine the Q point (I and V

C CE ) for the circuit of Figure 5.4.3. Also determine the values of V and
C

V .
B

Figure 5.4.6: Circuit for Example 5.4.2.

First off, R (now on top) is around the same size as R so the approximation method should be accurate and we can assume
2 E

the divider is lightly loaded.

Method One
We will focus on the base-emitter loop as usual because V is a known potential. Our immediate goal is to find the voltage
BE

across R so that we can use Ohm's law to find I . First we note that the voltage drop across R is equal to the combined
E C 2

drops across R and V . The drop across R is found via the voltage divider rule.
E BE 2

R2
VR2 = VEE
R1 + R2

4.7kΩ
VR = 15V
2
10kΩ + 4.7kΩ

VR = 4.8V
2

And

VR = VR − VBE
E 2

VR = 4.8V − 0.7V
E

VR = 4.1V
E

Therefore
VRE
IC =
RE

4.1V
IC =
3.3kΩ

IC = 1.24mA

Method Two
Here we will determine all voltages with respect to ground.
R1
VB = VEE
R1 + R2

10kΩ
VB = 15V
10kΩ + 4.7kΩ

VB = 10.2V

The voltage from base to emitter has a − to + polarity, meaning it is a rise of 0.7 volts. Therefore

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 VE = VB + VBE

VE = 10.2V + 0.7V

VE = 10.9V

The voltage across R is the difference between V

E EE and V .
E

VRE = VEE − VE

VRE = 15V − 10.9V

VRE = 4.1V

This is the same value we arrived at using method one, so the collector current must be the same at 1.24 mA.
To find V CE we also have options. One path is to use a slightly modified Equation 5.4.4.

VC E = −(VEE − IC (RC + RE ))

VC E = −15V + 1.24mA(3.9kΩ + 3.3kΩ)

VC E = −6.07V

The collector is negative relative to the emitter, hence the negative sign. To avoid this, we could just swap the leads and refer to
V EC instead.
Alternately, we could find V CE by determining V and then subtracting V from it.
C E

VC = IC RC

VC = 1.24mA × 3.9kΩ

VC = 4.84V

VC E = VC − VE

VC E = 4.84V − 10.9V

VC E = −6.06V

We see a very slight difference here due to carried rounding errors.

It is instructive to compare the results of Example 5.4.2 back to Example 5.4.1. These circuits are otherwise identical except for
the fact that one is NPN and the other is PNP. We find the same results for device currents (I ) and component voltage magnitudes
C

(VCE or the voltage across R ); only the signs and directions are reversed. On the other hand, we find that ground referenced
E

potentials such as V , V and V are decidedly different between the two circuits.
B C E

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5.5: Feedback Biasing
While two-supply emitter bias and voltage divider bias can produce very high stability, there are other bias configurations
available. Their stability tends not to be quite as good, but they are superior to simple base bias. They also tend to use fewer
components than their high stability cousins. As a group, we refer to these as feedback biasing configurations. They use the concept
of negative feedback. This is a technique where a change in the output can be reflected back to the input in such a way that it tends
to partially offset the output change.

5.5.1: Collector Feedback Bias

With a simple move of R in the basic base bias configuration, we arrive at collector feedback bias. The NPN template is shown in
B

Figure 5.5.1. Compared to base bias, all that has changed is that R is connected to the lower part of R rather than to the power
B C

supply. That small change can have a noticeable effect on stability.

Figure 5.5.1: Collector feedback bias.

To understand how feedback works, assume that a current is flowing from the supply, through R , into the collector and finally,
C

out of the emitter to ground. Via KVL, V = V = V − I ⋅ R . Now suppose for some reason, a temperature change
CE C CC C C

perhaps, β increases. This should cause an increase in I . An increase in I , though, would cause an increase in the drop across
C C

R C due to Ohm's law. This, in turn, would force V to drop. Here is the key: V is also equal to the drop across R plus the
C C B

voltage V . The base-emitter potential is fixed at approximately 0.7 volts so any decrease in V is reflected as a decrease in
BE C

voltage across R . By Ohm's law, that means that I must decrease by a similar proportion. This decrease tends to offset the initial
B B

tendency of the collector current to increase.

To derive an equation for the collector current, we can use KVL.

VC C = VRC + VRB + VBE (5.5.1)

VC C = IE RC + IB RB + VBE

IC
VC C = IC RC + RB + VBE
β

VC C − VBE
IC =
RC + RB /β

This equation is very similar to the current derivations for the two-supply emitter bias (Eq 5.3.1) and voltage divider bias (Eq
5.4.3). Again, if we can set R ≫ R /β then I will be relatively immune from Q point shifts due to β. The problem here is that
C B C

it's not nearly so easy to meet that stipulation in this circuit. Consequently, collector feedback tends to have only modest stability.
Concerning the cutoff and saturation endpoints on the DC load line, once again, cutoff is determined by the DC power supply while
saturation is determined by the amount of resistance in the collector-emitter to limit said power supply's current.
VC C
IC (sat) = (5.5.2)
RC

VC E(cutof f ) = VC C (5.5.3)

Example 5.5.1

Assuming β = 100, determine the Q point (I and V

C CE ) for the circuit of Figure 5.5.2. How much does the Q point change if
β is halved?

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 Figure 5.5.2: Circuit for Example 5.5.1.
Using Equation 5.5.1
VC C − VBE
IC =
RC + RB /β

15V − 0.7V
IC =
10kΩ + 180kΩ/100

IC = 1.21mA

Using KVL

VC E = VC C − VRC

VC E = VC C − IC RC

VC E = 15V − 1.21mA × 10kΩ

VC E = 2.9V

If β is halved to 50
VC C − VBE
IC =
RC + RB /β

15V − 0.7V
IC =
10kΩ + 180kΩ/50

IC = 1.05mA

VC E = VC C − IC RC

VC E = 15V − 1.05mA × 10kΩ

VC E = 4.5V

For a 2:1 drop in β we see about a 13% reduction in I with a somewhat larger change in V
C CE . This circuit is clearly not as
stable as the two-supply emitter bias or the voltage divider bias but it is superior to base bias.

The PNP version of the collector feedback bias configuration should come as no surprise. The template is shown in Figure 5.5.3.
Here, we use the same technique of power supply shifting that was used with the PNP voltage divider in order to wind up with a
positive power supply. As with the PNP voltage divider, because we have changed the reference point, all ground referenced
voltages will be different from their NPN counterparts. All currents and component voltages will have the same magnitudes but
with opposite directions and polarities.

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 Figure 5.5.3: PNP Collector feedback bias.

5.5.2: Emitter Feedback Bias

The emitter feedback bias uses the same overall idea as the collector feedback circuit, namely, that changes at the output will be
reflected back to the input and thus help mitigate the initial change. While collector feedback focuses on collector current
establishing V via R , emitter feedback uses the fact that emitter current establishes V via R . In both cases, these voltages are
C C E E

used to change the voltage across R , which results in a change in I that opposes the original collector current change.
B B

Figure 5.5.4: Emitter feedback bias.

A basic emitter feedback bias circuit is shown in Figure 5.5.4. We shall use KVL to develop an equation for collector current.
VC C = VR + VBE + VR (5.5.4)
B E

VC C = IB RB + VBE + IE RE

IC
VC C = RB + IC RE + VBE
β

VC C − VBE
IC =
RE + RB /β

If we can set R ≫ R /β then the Q point will be stable in spite of changes in β. The problem here is the same as was the case in
E B

collector feedback, namely that this stipulation is not easy to achieve. Consequently, the emitter feedback configuration tends to
have only modest stability. In any event, once the collector current is known, V CEcan be found using the techniques illustrated
with the voltage divider configuration. The endpoints for the DC load line are found in the usual manner.
VC C
IC (sat) = (5.5.5)
RC + RE

VC E(cutof f ) = VC C (5.5.6)

Example 5.5.2

Assuming β = 100, determine the Q point (I and V

C CE ) for the circuit of Figure 5.5.5.

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 Figure 5.5.5: Circuit for Example 5.5.2.
Using Equation 5.5.4
VC C − VBE
IC =
RE + RB /β

20V − 0.7V
IC =
200Ω + 270kΩ/100

IC = 6.66mA

Using KVL

VC E = VC C − VR − VR
C E

VC E = VC C − IC (RC + RE )

VC E = 20V − 6.66mA(1.8kΩ + 200Ω)

VC E = 6.68V

To complete the load line, we find

IC (sat) = 10mA

VC E(cutof f ) = 20V

Dropping β to 50 will result in

IC = 3.45mA

VC E = 13.1V

We see less than a 2:1 change in I and V

C CE but the stability is not dramatic.

5.5.3: Combination Feedback Bias

The final feedback bias configuration combines both collector feedback and emitter feedback to arrive at the circuit depicted in
Figure 5.5.6. We shall bestow upon it the highly original name of combination feedback bias.

Figure 5.5.6: Combination feedback bias.

This circuit applies feedback to R from both ends, so to speak, so it tends to have slightly better stability than either collector
B

feedback or emitter feedback bias. Of course, it is now only one resistor shy from the voltage divider circuit which is considerably
more stable.
The equations for the load line are listed below. The derivations are left as an exercise.
VC C − VBE
IC = (5.5.7)
RC + RE + RB /β

VC E = VC C − IC (RC + RE ) (5.5.8)

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 VC C
IC (sat) = (5.5.9)
RC + RE

VC E(cutof f ) = VC C (5.5.10)

Example 5.5.3

Assuming β = 125, determine the Q point (I and VC CE ) for the circuit of Figure 5.5.7.

Figure 5.5.7: Circuit for Example 5.5.3.

Note that this is the upside down PNP version. Using Equation 5.5.7
VC C − VBE
IC =
RC + RE + RB /β

18V − 0.7V
IC =
7.5kΩ + 330Ω + 100kΩ/125

IC = 2mA

Using KVL

VC E = VC C − VRC − VRE

VC E = VC C − IC (RC + RE )

VC E = 18V − 2mA(7.5kΩ + 330Ω)

VC E = 2.34V

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5.6: Summary
DC biasing is required in order to maintain the proper junction potentials and operation of the BJT. Several different circuit
configurations are available to establish a DC bias on both NPN and PNP transistors. These circuits vary in complexity and their
ability to maintain a constant operating point, or Q point, in the face of variations of β.
The two-supply emitter bias topology offers very high Q point stability. It achieves this through the use of two powers supplies; one
connected through a resistor to the emitter and a second unit connected through a resistor to the collector. It is unique in that the
supplies are bipolar; one being positive and the other being negative.
The voltage divider bias circuit offers similar stability performance to the two-supply emitter bias circuit. It uses a single supply
and a resistive voltage divider to establish a second, lower potential at the base terminal.
The three feedback bias configurations offer only modest enhancements in stability but use the least amount of parts. They all rely
on a single DC power source.
A DC load line is a plot of all possible collector current and corresponding collector-emitter voltage operating points. No matter
what the β for a circuit happens to be, the transistor's operating point must lie on this line. It is a valuable DC analysis tool.

5.6.1: Review Questions

1. Explain the need for DC biasing. Why can't we just apply an AC signal to the base of a BJT and expect proper amplification of
the signal?
2. What is a Q point?
3. What are the four values found on a DC load line?
4. Rank the bias configurations presented in this chapter in terms of their Q point stability relative to β.
5. Rank the bias configurations presented in this chapter in terms of their circuit complexity.
6. Describe the process of making a PNP version of an NPN bias circuit.

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5.7: Exercises
Unless otherwise specified, use β = 100.

5.7.1: Analysis Problems

1. Plot the load line for the circuit of Figure 5.7.1. V
CC = 20 V, V EE = −8 V, R = 7.5 kΩ, R = 10 kΩ, R = 12 kΩ.
B E C

Figure 5.7.1
2. Determine the new Q point for Problem 1 if β = 250.
3. Plot the load line for the circuit of Figure 5.7.2. V
EE = 5 V, V
CC = −18 V, R = 22 kΩ, R = 1.2 kΩ, R = 1.5 kΩ.
B E C

Figure 5.7.2
4. Determine the new Q point for Problem 3 if β = 50.
5. Plot the load line for the circuit of Figure 5.7.3. V
CC = 20 V, R = 15 kΩ, R = 5 kΩ, R = 4.3 kΩ, R = 9.1 kΩ.
1 2 E C

Figure 5.7.3
6. Determine the new Q point for Problem 5 if β = 150.
7. Plot the load line for the circuit of Figure 5.7.4. V
EE = 16 V, R = 12 kΩ, R = 4.7 kΩ, R = 6.2 kΩ, R = 10 kΩ.
1 2 E C

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 Figure 5.7.4
8. Determine the new Q point for Problem 7 if β = 200.
9. Plot the load line for the circuit of Figure 5.7.5. V CC = 12 V, R = 560 kΩ, R = 3.3 kΩ.
B C

Figure 5.7.5
10. Determine the new Q point for Problem 9 if β = 75.
11. Plot the load line for the circuit of Figure 5.7.6.

Figure 5.7.6
12. Determine the new Q point for Problem 11 if β = 200.
13. Plot the load line for the circuit of Figure 5.7.7. V CC = 15 V, R = 470 kΩ, R = 560 Ω, R = 3.3 kΩ.
B E C

Figure 5.7.7
14. Determine the new Q point for Problem 13 if β = 170.
15. Plot the load line for the circuit of Figure 5.7.8.
16. Determine the new Q point for Problem 15 if β = 75.
17. Plot the load line for the circuit of Figure 5.7.9. V EE = 18 V, R = 680 kΩ, R = 270 Ω, R = 3.9 kΩ.
B E C

18. Determine the new Q point for Problem 17 if β = 200.

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 Figure 5.7.8

Figure 5.7.9

5.7.2: Design Problems

19. Determine a value for R in the circuit of Figure 5.7.1 to set I = 2 mA. Use V
E C CC = 20 V, V EE = −8 V, R = 10 kΩ, R = 5.6
B C

kΩ.
20. Determine a value for R in the circuit of Figure 5.7.2 to set V
C CE = 10 V. Use V CC = −25 V, V EE = 6 V, R = 15 kΩ,
B RE =
6.8 kΩ.
21. Determine a value for R in the circuit of Figure 5.7.3 to set V
C CE = 8 V. Use V CC = 24 V, R = 22 kΩ, R = 10 kΩ, R = 5.6
1 2 E

kΩ.
22. Determine new values for R and R in the circuit of Figure 5.7.4 in order to set I = 500 μ A. V
1 2 C EE = 22 V, R = 15 kΩ,
E RC

= 6.8 kΩ.

5.7.3: Challenge Problems

23. Determine the maximum and minimum values for I in Problem 1 if every resistor has a 10% tolerance.
C

24. Determine the maximum and minimum values for V CE in Problem 3 if every resistor has a 5% tolerance.
25. Determine a value for R in the circuit of Figure 5.7.3 to set V
E CE = 10 V. V
CC = 30 V, R = 12 kΩ, R = 3 kΩ, R = 8.2 kΩ.
1 2 C

26. Derive Equation 5.16.

27. Determine the the power drawn from the supply for the circuit of Problem 5. 28. Using a 15 volt power supply, design a bias
circuit to create a very stable Q point of 2 mA and 5 volts.

5.7.4: Computer Simulation Problems

29. Perform a series of DC simulations to test the Q point stability versus β of the circuit of Problem 1.
30. Perform a Monte Carlo simulation to investigate the Q point stability of the circuit of Problem 5 if the emitter resistor has a
10% tolerance.

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 CHAPTER OVERVIEW

6: Amplifier Concepts
Learning Objectives
After completing this chapter, you should be able to:
Explain the differences between voltage gain, current gain and power gain.
Describe a basic voltage amplifier model using voltage gain, input impedance and output impedance.
Determine the effects of source and load impedance on system gain and explain how they interact with an amplifier's input
and output impedance.
Describe and distinguish the concepts of noise and waveform distortion.
Define the concept of output compliance.
Discuss the frequency limits of an amplifier in general terms.
Define Miller's Theorem.

6.1: Introduction
6.2: Amplifier Model
6.3: Compliance and Distortion
6.4: Frequency Response and Noise
6.5: Miller's Theorem
6.6: Summary
6.7: Exercises

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1
6.1: Introduction
The concept of signal amplification finds numerous uses in the field of electronics. This includes applications such as boosting the
signal level from a sensor or driving loads like loudspeakers or antennas. Reduced to its most simple terms, amplification is just
multiplication. The ideal amplifier multiplies the amplitude of the input signal by a constant. It should not change the frequency of
the signal, alter its shape, add noise or in any other way warp or distort the signal.
Amplifiers can be designed to be voltage sensing or current sensing and can be modeled as either controlled voltage sources or
controlled current sources. As a functional block, we are primarily interested in describing an amplifier in terms of its amplification
factor, input impedance and output impedance. The amplification factor is also referred to as the gain and may be expressed in
terms of voltage gain, current gain or power gain, depending on the application. Other items of interest include the maximum
output level or compliance, useful frequency range, noise and distortion characteristics.

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6.2: Amplifier Model
The ideal amplifier does nothing except increase the amplitude of the input signal. The factor of increase is defined as the ratio of
the output signal to the input signal. It is a unit-less quantity. For example, if the input signal has a power of 10 milliwatts and the
circuit boosts the signal up to 50 milliwatts, we say it has a power gain of 50 milliwatts /10 milliwatts, or 5. Similarly, if the input
signal is 2 volts and the output signal is 16 volts, we say it has a voltage gain of 16 volts/2 volts, or 8. Historically, power gain is
denoted as G. For voltage gain and current gain we use A and A , where A stands for A mplification factor. Some amplifiers
v i

invert the signal from input to output. Basically, they flip the wave shape upside down. For a simple sine wave this is equivalent to
shifting the phase of the signal by 180 , and for a sine wave input the amplifier produces a −sine output. To reflect this effect, the
∘

amplification factor is denoted as negative. For example, an A of −10 indicates an amplification factor of 10 with a signal
v

inversion.
The size and complexity of an amplifier circuit can vary considerably, ranging from a single transistor to dozens of transistors. To
ease system design it is helpful to use simplified functional models. Typically, these models use a resistor to represent the
impedance seen looking into the amplifier along with a controlled source and its associated internal resistance. An example is
shown in Figure 6.2.1.

Figure 6.2.1: A simple voltage amplifier model.

This is a model of a voltage amplifier (note that V and V are specified along with a controlled voltage source within the
in out

model). The controlled voltage source and its series Z is the Thevenin equivalent of the output when viewed from the load (i.e.,
out

the V pin). Likewise, Z is the equivalent impedance seen by the driving source. Because a voltage amplifier is designed to
out in

maximize voltage transfer, the input impedance tends to be high to minimize loading (think of a voltmeter). Similarly, the output
impedance would tend to be low (think of an ideal voltage source). In contrast, a circuit designed for maximum current transfer
would tend to have a low Z and a high Z . Precisely how the circuit creates the signal boost is not a concern of this model, we
in out

only care that it does.

6.2.1: Loading Effects

Once the model is established it is relatively easy to recognize and compute loading effects. Loading effects are signal losses
caused by interactions between the amplifier's impedances and those of the circuits and loads connected to it. A generic model
including loading effects is shown in Figure 6.2.2.

Figure 6.2.2: Voltage amplifier model with loading effects.

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A cursory examination of Figure 6.2.2 shows that there is a voltage divider between Z and Z along with a second divider
gen in

between Z and Z . Each of these dividers causes signal loss, that is, they reduce the final output voltage. The input voltage to
out load

the amplifier is reduced as follows

Zin
Vin−amp = × Vgen
Zin + Zgen

The load voltage is reduced as follows

Zload
Vload = × Av × Vin−amp
Zload + Zout

Therefore the combined gain is

\[A_{system} = \frac{V_{load}}{V_{gen}} = \frac{Z_{i n}{Z_{i n} + Z_{gen}} \times A_v \times \frac{ Z_{load}}{Z_{load}
+Z_{out}}
To minimize these losses we'd like Z in ≫ Zgen and Z load ≫ Zout .

Example 6.2.1

A voltage amplifier has the following specifications: A = 20 , Z = 10 kΩ, Z = 200Ω. It is driven by a 30 millivolt
v in out

source with a 600 Ω internal impedance and drives a 1 kΩ load. Determine the load voltage.
The voltage that appears at the amplifier's input is
Zin
Vin−amp = × Vgen
Zin + Zgen

10kΩ
Vin−amp = × 30mV
10kΩ + 600Ω

Vin−amp = 28.3mV

This is multiplied by the voltage gain of 20 and then reduced by the output divider.
Zload
Vin−amp = × Av × Vin−amp
Zload + Zout

1kΩ
Vin−amp = × 20 × 28.3mV
1kΩ + 200Ω

Vin−amp = 471.7mV

Without the loading effects the output signal would be simply 30 millivolts times the voltage gain of 20, or 600 millivolts.
Further, note that if the source is replaced with a typical laboratory grade function generator exhibiting an internal impedance
of 50 Ω and the load is removed, being replaced by an oscilloscope exhibiting a typical 1 MΩ input impedance, the loading
effects would be minimal and we would measure just a few millivolts shy of the ideal 600 millivolts.

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6.3: Compliance and Distortion
At some point the idealization that the output signal is merely the input signal times the gain fails. All amplifiers have a limit on
just how large the output signal can be. This is set by the DC power supply and the amplifier design. The maximum output signal
(typically, the maximum output voltage) is referred to as the compliance. Any attempt to produce an output signal that swings
beyond the compliance will result in waveform distortion. In the simplest case, the output signal is strictly and abruptly limited to
the compliance level and any portion of the output waveform that would otherwise lay above that will be removed. It is as if some
form of electronic scissors clipped off the top of the waveform. Hence, this is often referred to as clipping. An example of clipping
is illustrated in Figure 6.3.1. The ideal output waveform is shown in brown and the clipped waveform is shown in blue. The
clipping is so severe here that the clipped waveform now looks less like a sine wave and more like a square wave. This is extreme
waveform distortion and has important consequences.

Figure 6.3.1: Clipped waveform.

Whenever a signal is altered in the time domain, there will be an alteration of its frequency content. Depending on what we started
with and the manner in which the wave shape is altered, new frequency components may be added to the signal and the levels of
existing components may be changed or even deleted. The extreme clipping that created a near-square wave added a large number
of new frequency components to the signal.
To see how the wave shape and frequency content are connected, consider the waveform depicted in Figure 6.3.2. We start with a
simple sine wave shown in green. We refer to this as the fundamental or base frequency. We then add a harmonic. A harmonic is
another sine wave that is an integer multiple of the fundamental frequency. It may be larger or smaller in amplitude and the phase
may be shifted. In this example we have a single sine at three times the fundamental frequency (blue). When we add this harmonic
to the fundamental we arrive at a new waveform shown in red. This new waveform looks something like a square wave but with a
“lumpy” top and bottom. If we add more harmonics, these variations will begin to smooth out, as shown in Figure 6.3.3. This
waveform appears to be fairly close to a square wave and not too distant from our earlier clipped waveform. Based on this, we can
conclude that the clipped sine wave has new frequency components added to it. We can also conclude that if our amplifier clips a
more complicated waveform such as a snippet of music, that process will add new harmonics as well. Further, it is likely that these
harmonics will be audible and can change our perception of the music, perhaps subtly but maybe drastically.

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 Figure 6.3.2: Sine wave with third harmonic.

Figure 6.3.3: Sine wave with seven harmonics, approaching a square wave.
Along with clipping, amplifiers can exhibit more subtle forms of distortion due to internal nonlinearity. For example, it is possible
for the gain to vary slightly as the signal swings from low to high or from negative to positive. An example is shown in Figure
6.3.4 with the distorted wave shown in red.

Figure 6.3.4: Sine wave with distortion.

At first glance it may appear as though the wave is merely offset negatively. This is not the case. If we shift the wave vertically, as
in Figure 6.3.5, it becomes apparent that the wave is truly distorted and is no longer a pure sine wave.

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 Figure 6.3.5: Sine wave with distortion, level shifted.
Unlike the clipped wave, the distorted wave in Figure 6.3.5 exhibits an asymmetry; the negative portion does not appear to be a
mirror image of the positive portion. In other words, this wave lacks half-wave symmetry. Waves that exhibit half-wave symmetry
contain only odd harmonic distortion (harmonics that are odd integer multiples of the fundamental). In contrast, waves that lack
half-symmetry have at least one even harmonic. Here is how to test for half-wave symmetry. First, consider the sawtooth wave
shown in Figure 6.3.6.

Figure 6.3.6: Half-wave symmetry test: Sawtooth wave.

Rotate the negative portion of the wave around the time axis as shown in Figure 6.3.7.

Figure 6.3.7: Half-wave symmetry test: Sawtooth wave, negative portion rotated.
Finally, slide the negative portion over the positive portion and see if they're identical, as in Figure 6.3.8.

Figure 6.3.8: Half-wave symmetry test: Sawtooth wave, negative portion rotated and slid.
If the two halves are identical then the wave has half-wave symmetry. The sawtooth wave does not exhibit half-wave symmetry,
therefore it must contain at least one even harmonic.
An amplifier's linearity is often quantified through a Total Harmonic Distortion, or THD, measurement. The measurement is carried
out by applying a very pure, low distortion sine wave to the amplifier. This is the fundamental. At the output of the amplifier, a

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very selective filter is used to remove the fundamental. This leaves behind just the added distortion harmonics.1 These harmonics
are then treated as a lumped value and presented as a percentage of the total signal. On an oscilloscope, it is relatively easy for a
person to discern THD levels in the double digits. On the other hand, it is very difficult, if not impossible, for an individual to
discern THD levels much below 1% by eye. Of course, what matters is what we can hear, not how the waveform looks. To put this
in perspective, many high fidelity audio amplifiers exhibit THD levels below 0.1% while an over-driven guitar amplifier might be
running over 20%. THD is not the final word on distortion though. It has its limits. For example, all of the distortion products are
lumped together. It says nothing about which harmonics are particularly strong or their distribution. It also doesn't say much about
what happens when multiple frequencies interact. One method of trying to quantify that is to apply two sine waves at different
frequencies to the amplifier simultaneously. The result is called an Intermodulation Distortion rating, or IMD. This is also
expressed as a percentage.

References
1
To be strictly accurate, the residual consists of the harmonics plus any noise produced by the amplifier. Therefore it is more
accurate to refer to this as a THD+noise spec.

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6.4: Frequency Response and Noise
Like compliance and distortion, two other practical limits on amplifier performance are its frequency response and output noise.
First, let's discuss frequency response.
Although we describe an amplifier as having a specific gain or amplification factor, this is true only for a certain range of
frequencies. All amplifiers are limited in terms of the range of frequencies over which they can operate. If we examine an
amplifier's performance at extreme frequencies, the gain may be much less than the nominal value. In fact, if we go far enough, the
gain may even be fractional, meaning that the “amplifier” is actually reducing the signal level.
The region where the nominal gain is accurate is referred to as the mid-band. This range is defined by one or two corner or break
frequencies. The lower limit is referred to as f while the upper limit is referred to as f . At these frequencies, the output level has
1 2

dropped to half the power exhibited by a mid-band frequency of the same input level. A gain versus frequency response plot that
encapsulates this concept is shown in Figure 6.4.1.

Figure 6.4.1: A generic gain versus frequency plot.

In this representative plot it is apparent that only input signals whose frequencies lay between f and f will receive full
1 2

amplification. As the input frequency moves to either side of the middle band, the gain begins to drop off. The drop-off increases as
the signal frequency moves farther and farther away. Eventually the gain will fall to practically zero and virtually no trace of the
input signal will appear at the output.
Precise values of the corner frequencies will depend on the application. For example, a high fidelity audio amplifier will most
likely have an f below 20 Hz and an f above 20 kHz21 while an amplifier used for telephone systems might range from 300 Hz
1 2

to 4 kHz22. In contrast, a radio frequency amplifier may be operating at frequencies orders of magnitude higher than these.
Without exception, all amplifiers have an upper limit frequency, f , but not all of them have a lower frequency limit, f .
2 1

Amplifiers without a lower limit can amplify signals with frequencies all the way down to DC. They are referred to as direct
coupled or DC amplifiers. The lower frequency limit is usually caused by in-line coupling capacitors, and in some cases,
transformers. Among other uses, these components are added to purposely block DC. There are good reasons to do this, as we shall
see in upcoming work, however, it is possible to design amplifiers without them. The resulting amplifier will then have no limit on
how low of a frequency it can amplify.
The upper limit frequency is another story. While components are often added to tailor the upper frequency response of an
amplifier, even if no tailoring was desired the amplifier would still have an upper limit frequency. This would be due to small and
unavoidable capacitances and inductances that exist in the circuit, for example stray wiring capacitance. Ultimately, the
corresponding reactances will cause a signal level reduction that worsens as frequency increases. As you might guess, these
reactances also cause varying phase shifts between the input signal and the output signal.
Amplifier performance is also limited by its internal noise. Noise is an undesired signal that appears at the output of an amplifier.
Unlike distortion, noise is usually not correlated with the input signal level. Generally, noise is broad-band, meaning that it contains
a very wide range of frequencies. As such, it does not have a discernible pitch. Examples in nature include the sound of leaves
rustling in the wind or the sound of a waterfall. Noise is best thought of as a truly random signal. As such, it cannot be accurately
predicted and therefore there is no easy way to remove it once it has been added to a desired signal. There are many potential
sources of noise in an amplifier. They range from process issues in semiconductors to thermal effects in resistive elements. In
general, noise gets worse as temperature, resistance and frequency range increase. Noise is unavoidable in absolute terms but
ultimately what we care about is whether or not it is low enough for a given application. In other words, is the noise level
significantly lower than the signal level, to the point where it is no longer a problem? This is quantified by simply creating a ratio
between the nominal output signal level and the output noise level. This ratio is given the very creative name signal-to-noise ratio,
or S/N for short. All other factors being equal, the higher the S/N , the better.

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References
1
20 Hz – 20 kHz is the range of frequencies heard by a typical healthy young human.
2
Decidedly not hi-fi, but do we really need high fidelity to call-in a take-out order?

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6.5: Miller's Theorem
Some inverting voltage amplifier designs employ an impedance bridged between the input and output, as shown in Figure 6.5.1.

Figure 6.5.1: An input/output bridged impedance.

There are different reasons for doing this, a prime example involving shaping the frequency response of the amplifier. To simplify
the analysis of such a configuration, we may employ Miller's Theorem, named after American engineer John Milton Miller.
The goal here is to determine equivalent impedances that lie in parallel with the input and output of the amplifier. These equivalents
simply become part of the input and output networks around the amplifier.
First, let's consider the equivalent impedance at the input, Z . By definition, this is the impedance in parallel with the input
in−miller

of the amplifier that would draw the same amount of current as the original bridging Miller impedance. The current through the
Miller impedance is simply the the voltage across it divided by the Miller impedance, Z . The voltage across it is the difference
between the input and output voltages.
Vin − Vout
iin−miller =
Z

Vin − Av Vin
iin−miller = , the gain is negative so
Z

Vin (| Av | + 1)
iin−miller =
Z

Dividing this current into the input voltage yields the equivalent impedance.
Z
Zin−miller =
∣ Av ∣ +1

A similar derivation yields the output equivalent.

Z ∣ Av ∣
Zout−miller =
∣ Av ∣ +1

The Miller equivalent circuit for a general impedance Z is shown in Figure 6.5.2.

Figure 6.5.2: Miller general equivalent.

The general rule to remember is that the Miller equivalent presents equivalent impedances that are less than the original bridging
impedance. In the case of the input section, the reduction effect is very large at higher gains.
Two typical cases for the impedance Z are a resistance, R , and a capacitance, C . For a pure resistance, we can perform a direct
substitution for Z . The original and Miller equivalents are shown in Figure 6.5.3.

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 Figure 6.5.3: Original and Miller equivalent for a resistor.
For a capacitor, the situation is similar, however, we will substitute X for Z and recall that C
c = 1/(2πf Xc ) .

Figure 6.5.4: Original and Miller equivalent for a capacitor.

Note that for the capacitor, there is a multiplicative effect. That is, the effect of the original bridging capacitor on a high gain
amplifier is equivalent to a much larger input shunt capacitor.

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6.6: Summary
Complex amplifier circuits can be modeled with a functional block. The ideal model includes the input and output impedances
along with a controlled source. This source would exhibit a signal gain or amplification factor. Usually, G stands for power gain
while A and A represent voltage and current amplification, respectively. This amplification factor may be negative which
v i

indicates that the amplifier inverts the phase of the input, that is, the waveform is flipped upside down. The impedances allow
calculation of loading effects while the gain determines the the size of the output signal.
If the input signal is too large, the output signal may be limited in amplitude or clipped. The maximum output amplitude is referred
to as the compliance. Clipping is a gross form of distortion but more subtle forms exist as well. In general, distortion creates new
frequency components. If these new components are integer multiples of the original input frequency, which they are typically, they
are referred to as harmonics. One method of quantifying distortion performance is to sum all of the harmonics and compare that to
the original signal. This is called THD or total harmonic distortion. Along with distortion, the amplifier might also add undesirable
noise to the output signal. Noise is a random signal that contains many different frequencies. Typically, this is measured via a
signal-to-noise ratio, or S/N , at the output.
An amplifier also operates over a given range of frequencies, from a lower limit, f , to a high limit, f . Some amplifiers are able to
1 2

amplify down to 0 Hz (DC) and effectively do not have an f but all amplifiers do have an upper limit.
1

Finally, Miller's Theorem is an analysis technique that allows an impedance that bridges from the input of an inverting voltage
amplifier to its output to be split into equivalent input and output parallel impedances. These impedances will be smaller than the
original bridging impedance and are a function of the gain of the amplifier.

6.6.1: Review Questions

1. Explain how an amplifier's input impedance might react with a source to produce a signal loss.
2. Explain how an amplifier's output impedance might react with a load to produce a signal loss.
3. What is compliance?
4. Describe clipping.
5. Describe half-wave symmetry. What does it have to do with amplifier distortion?
6. What is noise? How does it differ from distortion?
7. Draw a generic frequency response plot for an amplifier.
8. Detail the purpose and use of Miller's Theorem.

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6.7: Exercises
6.7.1: Analysis Problems
1. Determine the load voltage for the model of Figure 6.7.1 if V gen = 10 mV, Z gen = 50 Ω, Zin = 1 MΩ, Z out = 75 Ω, Zload =1k
Ω and A = 50.
v

Figure 6.7.1
2. Determine the load voltage for the model of Figure 6.7.1 given V gen = 8 mV, Zgen = 1 k Ω, Z in = 6 kΩ, Zout = 500 Ω, Z load =2
k Ω and A = 100.
v

3. If the circuit of Problem 1 has a compliance of 2 volts, will the output clip? What if the input is increased to 100 mV?
4. If the circuit of Problem 2 has a compliance of 5 volts, will the output clip? What if the input is increased to 200 mV?
5. If an amplifier has A = 25, V = 20 mV and there is no appreciable loading, determine the output signal-to-noise ratio if the
v in

amplifier generates an output noise voltage of 10 μ V.

6. Determine which waveforms from Figures 6.7.2 through 6.7.6 exhibit halfwave symmetry.

Figure 6.7.2

Figure 6.7.3

Figure 6.7.4

Figure 6.7.5

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 Figure 6.7.6
7. Determine the Miller equivalent resistances for the circuit of Figure 6.7.7 if A = −20 and R = 60 kΩ.
v

Figure 6.7.7
8. Determine the Miller equivalent capacitances for the circuit of Figure 6.7.8 assuming A = −30 and C = 200 pF.
v

Figure 6.7.8

6.7.2: Challenge Problems

9. If the circuit of Problem 1 has a compliance of 20 volts, how large can the input signal be before the load voltage is clipped?
10. If the circuit of Problem 2 has a compliance of 10 volts, how large can the input signal be before the load voltage is clipped?
11. Using Figure 6.7.7 as a guide and assuming that R = 100 kΩ, how large would the gain have to be such that the input
equivalent resistance is 4 kΩ?
12. Using Figure 6.7.8 as a guide and assuming that A = −35, determine a value for C such that the input equivalent capacitance
v

is 1.2 nF.

6.7.3: Computer Simulation Problems

13. Simulate the circuit of Problem 1 and verify the load voltage.
14. Simulate the circuit of Problem 2 and verify the load voltage.

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 CHAPTER OVERVIEW

7: BJT Small Signal Amplifiers

Learning Objectives
After completing this chapter, you should be able to:
Determine the voltage gain, input impedance and output impedance of simple BJT amplifiers.
Detail the functional differences between voltage amplifiers and voltage followers.
Explain the advantages and disadvantages of using localized feedback (swamping).
Determine the combined characteristics of multistage BJT amplifiers.
Detail the advantages and disadvantages of using direct coupling versus capacitor coupling in multistage amplifiers.
Explain the operation of the Darlington pair.

7.1: Introduction
7.2: Simplified AC Model of the BJT
7.3: Common Emitter Amplifier
7.4: Common Collector Amplifier
7.5: Common Base Amplifier
7.6: Multi-Stage Amplifiers
7.7: Summary
7.8: Exercises

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1
7.1: Introduction
In the prior chapter we discussed the general operational characteristics of amplifiers including voltage gain, input and output
impedance, compliance, distortion and so forth. In this chapter we shall focus on the analysis of small signal amplifiers,
specifically, their voltage gain and input/output impedances. As we will be performing a small signal analysis, we will not be
concerned with compliance, maximum load power, device dissipation or the like. There is no specific definition of small signal
versus large signal but for our purposes we shall define small signal as output signals that are well below the clipping limit and
with power dissipation of no more than a few hundred milliwatts for either the load or transistor.
There are two popular techniques used to analyze BJT amplifier circuits. One is through the use of hybrid parameters. There are
four different hybrid parameters. We have already seen one of them, the forward current gain, h . We simply call it β. The other
fe

three are h , the input impedance; h , the output admittance; and h , the reverse voltage gain. The second letter of the subscript
ie oe re

(the “e ” in h ) indicates it is for the common emitter configuration (that is, input applied to the base, output taken at the collector
fe

and the emitter at the common ground).

The second approach uses r' parameters (pronounced “r prime”). The r approach is sufficient for all of our analyses and, given an
′

understanding of Ohm's law, KVL and KCL, produces straightforward equations for circuit gain, input impedance and the like. As
a consequence, we shall focus on the r system.
′

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7.2: Simplified AC Model of the BJT
Just as we created a DC model to ease the analysis of DC bias circuits, we shall make use of an AC BJT model for our AC
analyses. In fact, our AC model is based on the DC model. The collector-base region is still represented with a current-controlled
current source although it's AC instead of DC: i = β i . The base-emitter junction is a bit trickier. Although a simple 0.7 volt
C B

junction worked fine for DC, we now have to consider the AC resistance of the diode.
To find the dynamic resistance of the junction, first recall that the AC signal is riding on the DC bias current, as plotted in Figure
1
7.2.1. We can imagine that the AC signal is causing this point to trace back and forth along the curve. Of course, as this is a small

signal analysis, this sweep will be very small, perhaps only a few percent of the quiescent current and can be approximated as a
straight line segment. The slope of this line segment represents its conductance.2 The reciprocal of conductance is resistance;
therefore, the reciprocal of the slope represents the resistance of the device. Consequently, we can approximate the dynamic
resistance of the device as the reciprocal of the slope of the line tangent to the operating point (that is, the reciprocal of the slope of
the line tangent to the quiescent bias current I ).
C

In reality, this slope is changing slightly as the signal swings back and forth along the base-emitter I-V curve. As the signal swings
positive and goes above the quiescent point the slope is a little steeper producing a slight reduction in dynamic resistance. In
contrast, as it swings negative, going below the quiescent point, the slope becomes a bit more shallow and produces a slightly
higher resistance. As a result, we are effectively computing an average value for the dynamic resistance by assuming this is a
straight line segment. The variance in this resistance will be a source of asymmetrical distortion in the amplifier of the type shown
in Chapter 6, Figure 6.3.4. We shall see more on this later.

Figure 7.2.1: Base-emitter junction plot and dynamic resistance.

In order to derive an equation for the dynamic resistance, we begin with the Shockley equation from Chapter 2, Equation 2.2.1,
slightly modified to reflect the terminal names of a BJT.
V q
BE

IC = IS ( e nkT − 1)

Where
IC is the junction (collector) current,
IS is the reverse saturation current,
VBE is the voltage across the junction (base-emitter),
q is the charge on an electron, 1.6E−19 coulombs,
n is the quality factor (typically between 1 and 2),
k is the Boltzmann constant, 1.38E−23 joules/kelvin,

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T is the temperature in kelvin.
At 300 kelvin (about 80 F), q/kT is approximately 38.6, thus for any reasonable value of V
∘
BE the “−1” term is small enough to
ignore. Also, we shall take n as 1.
The equation then reduces to
38.6VBE
IC = IS e (7.2.1)

To find the slope we take the first derivative of Equation 7.2.1 with respect to V BE .
dIC 38.6VBE
= 38.6 IS e (7.2.2)
dVBE

Substituting Equation 7.2.1 into Equation 7.2.2 yields

dIC
= 38.6 IC
dVBE

By definition, the dynamic junction resistance is the reciprocal of the slope.

dVBE
= 25.9mV IC
dIC

We call this r . This value is slightly low as it doesn't include bulk resistance so a good approximation is
′
e

26mV
′
re = (7.2.3)
IC

It is important to note that I in Equation 7.2.2 varies with temperature. Therefore r varies with temperature as well, decreasing
S
′
e

with increasing temperature. This carries important ramifications with the thermal stability of higher power amplifiers as we shall
see in subsequent work.
One of the most important things to remember here is that the DC collector current sets up the resistance of the AC model. In other
words, the stability of the AC circuit will depend in part on the stability of the DC bias (hence our emphasis on stable bias circuits
in Chapter 5).

Figure 7.2.2: Simplified AC model of BJT.

We now have our AC model, as shown in Figure 7.2.2. This is a simplified model in that it does not include junction capacitance
effects, lead inductance and the like. It is appropriate, therefore, as a low to mid-band frequency model. To summarize, the AC
collector current, i , is determined by the AC input current, i ; which is in turn a function of the the size of the applied input
C B

signal. In contrast, r is set by the DC bias current, I . The AC input can produce small variations in r which are manifested as
′
e C
′
e

waveform distortion.
Given the model, there are three ways to configure the transistor as an amplifier:
Common Emitter. The input is applied to the base and the output is taken at the collector. The emitter terminal is at the common
or ground point. This configuration exhibits both voltage gain and current gain. It also inverts the phase of the signal.
Common Collector. The input is applied to the base and the output is taken at the emitter. The collector terminal is at the
common or ground point. This configuration offers a voltage gain of about unity but does exhibit current gain. It maintains the
phase of the input signal. It is also referred to as an emitter follower or voltage follower.
Common Base. The input is applied to the emitter and the output is taken at the collector. The base terminal is at the common or
ground point. This configuration exhibits voltage gain but the current gain is unity at best. It also maintains the phase of the
input signal.

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We shall examine each of these topologies in turn. Each of these can be made using a variety of DC bias techniques. For example, a
two-supply emitter bias or voltage divider bias could be used for any of the three AC topologies, and further, they could utilize
either an NPN or PNP transistor.

References
1
The values plotted along the current axis are typical of a generic device and do not represent the current values for all BJTs.
2
Technically, this value is called the device's transconductance and is denoted as gm . We shall be seeing this again in upcoming
work.

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7.3: Common Emitter Amplifier
The common emitter configuration finds wide use as a general purpose voltage amplifier. We begin with a basic DC biasing circuit
and then add a few other components. For example, refer to Figure 7.3.1.

Figure 7.3.1: Common emitter amplifier using two-supply emitter bias.

This amplifier is based on a two-supply emitter bias circuit. The notable changes are the inclusion of an input signal voltage, V , in

and a load, R . So that these components do not alter the bias, we isolate the input and load through the use of coupling capacitors
L

Cin and C . These capacitors will act as opens to DC creating the desired isolation. As for the AC signal, the capacitances will be
out

chosen such that their reactances will be much smaller than the surrounding resistors at the frequency of the input. Consequently,
the capacitors will appear as shorts and allow the AC signal to pass through the amplifier.
The final alteration involves the emitter resistor. The single resistor of the bias network is replaced by a pair of resistors, R and
E

RSW , along with a bypass capacitor, C . For DC, the capacitor is open and the effective emitter bias resistance is R + R . For
E E SW

AC, the capacitor will behave ideally as a short so the AC emitter resistance will fall to just R . This resistor is called a
SW

swamping or emitter degeneration resistor. It is used primarily to help control the voltage gain of the amplifier.
We can use our AC transistor model along with the Superposition Theorem to arrive at an equivalent AC circuit of the amplifier, as
shown in Figure 7.3.2.

Figure 7.3.2: AC equivalent of common emitter amplifier.

First, we have shorted all of the capacitors. Second, we have replaced the DC sources with their ideal internal resistance (a short)
which places those points at AC ground. Third, we swapped out the transistor for the model. Lastly, we have combined and/or
renamed resistances where needed. Because this is an AC circuit, we use the convention of lower case r for resistance to avoid
confusion with the DC resistance (which are upper case). Thus, r is the AC resistance from the emitter to AC ground. This
E

corresponds to R in the original schematic. Similarly, r represents the total resistance seen from the collector to AC ground. In
SW C

the original schematic this corresponds to R in parallel with R . If this circuit was unloaded, then r would just be equal to R .
C L C C

Finally, r corresponds to R but in a voltage divider bias it would be equal to R in parallel with R .
B B 1 2

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7.3.1: Voltage Gain
Voltage gain, A , is defined as the ratio of v
v out to v . Using Ohm's law we find
in

vout vC
Av = = (7.3.1)
vin vB

−iC rC
Av =
′
iC (re + rE )

rC
Av = −
′
re + rE

First, the negative sign indicates that this amplifier inverts the waveform, top to bottom. For a sine wave, this is equivalent to
shifting the phase 180 . In some applications this can be a major issue, in others, not so much. If it is an issue, it can be resolved by
∘

using a second inverting gain amplifier in sequence with the first (inverting the inversion).
The second thing we see is that the gain is little more than a ratio of collector to emitter resistances. This is where splitting the
emitter resistor into two parts comes in. In the equation, r is the swamping resistor R . The larger the swamping resistor, the
E SW

lower the gain. The maximum gain will be achieved when R = 0 . That is, when the emitter is completely bypassed. The down
SW

side of this is that the gain will now depend entirely on r . This will increase the distortion. The reason is because R , being so
′
e SW

much larger, effectively “swamps out” the variation in r and reduces distortion. The larger R
′
e is relative to r , the greater the
SW
′
e

reduction in distortion, but with the cost of reduced gain. This is why a swamping resistor is also called an emitter degeneration
resistor: it degrades the voltage gain.

7.3.2: Input Impedance

Input impedance, Z , is defined as the ratio of v to i . In Figure 7.2.2 this is equal to r in parallel with the impedance looking
in in in B

into the base terminal, Z . Using Ohm's law we find

in(base)

vB
Zin(base) = (7.3.2)
iB
′
iC (re + rE )
Zin(base) =
iB

′
iC (re + rE )
Zin(base) =
iC /β

′
Zin(base) = β(re + rE )

Therefore
Zin = rB || Zin(base) (7.3.3)

We see that both the swamping resistor and β play a role in setting the input impedance. Larger values of R and β produce
SW

larger input impedances. In sum, we find that while swamping decreases voltage gain, it reduces distortion and increases input
impedance, the latter two generally desirable for a voltage amplifier. A non-swamped amplifier will have the largest gain but will
suffer from the worst distortion and a low input impedance. This is a classic “quality versus quantity” trade-off: a large low quality
gain versus a modest high quality gain1.

7.3.3: Output Impedance

Output impedance, Z , is defined as the internal impedance of the equivalent source that drives the load. If we position ourselves
out

at the load and look back into the amplifier shown in Figure 7.2.1, C is shorted ideally and V out is at AC ground. This leaves us
CC

with R in parallel with the transistor. The transistor is modeled as a current source and its ideal internal resistance would approach
C

infinity. In reality, the effective value, r , is likely in the region of 100 kΩ or so, depending on bias current. This parallel
′
C

combination comprises the output impedance of the current source. We model this circuit as a voltage amplifier so to be proper,
we'd convert the current source with parallel internal resistance to a voltage source with series internal resistance. Those resistance
values are identical, though, and we arrive at
′
Zout = r || RC
C

In many circuits, R is considerably smaller than r , therefore

C
′
C

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 Zout ≈ RC (7.3.4)

Example 7.3.1

Determine the input and output impedances of the amplifier shown in Figure . Also compute the voltage gain. Assume
7.3.3

β = 150.

Figure 7.3.3: Schematic for Example 7.3.1.

First, the easy bit. We can determine the output impedance by inspection. It is approximately equal to R , or 22 kΩ.
C

In order to find Z and A , we will need to determine . To obtain

in v
′
re we need to find I . Using KVL around the base-
′
re C

emitter loop, if we approximate the DC base voltage to be near zero, then all of the emitter supply drops across the DC emitter
resistance, with the exception of V .
BE

∣ VEE ∣ −VBE
IC =
RE + RSW

5V − 0.7V
IC =
8.2kΩ + 1.8kΩ

IC = 0.43mA

26mV
′
re =
IC

26mV
′
re =
0.43mA

′
re = 60.5Ω

′
Zin−base = β(re + rE )

Zin−base = 150(60.5Ω + 1.8kΩ)

Zin−base = 279kΩ

This value in parallel with the base biasing resistor creates the input impedance.

Zin = RB || Zin(base)

Zin = 15kΩ||279kΩ

Zin = 14.2kΩ

First, method one.

rC = RC || RL

rC = 22kΩ||33kΩ

rC = 13.2kΩ

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 rC
Av = −
′
re + rE

13.2kΩ
Av = −
60.5Ω + 1.8kΩ

Av = −7.1

And now method two; first the unloaded gain, then the divider effect and finally, the composite gain.
rC
Av(unloaded) = −
′
re + rE

22kΩ
Av(unloaded) = −
60.5Ω + 1.8kΩ

Av(unloaded) = −11.82

RL
Adivider =
RL + RC

33kΩ
Adivider =
33kΩ + 22kΩ

Adivider = 0.6

Av = Av(unloaded) × Adivider

Av = −11.82 × 0.6

Av = −7.1

We shall repeat the prior example using the same circuit but with one change: the emitter resistor will be completely bypassed. This
will show the effect that swamping has on voltage gain and input impedance.

Example 7.3.2

Determine the voltage gain and input impedance of the amplifier shown in Figure 7.3.4. Assume β = 150.

Figure 7.3.4: Schematic for Example 7.3.2.

The DC equivalent of this circuit is identical to that of the circuit shown in Figure 7.3.3. In both cases, the DC emitter
resistance is 10 kΩ. Therefore, I and r are unchanged. The bypass capacitor shorts this entire value for the AC equivalent
C
′
e

because there is no swamping resistor. Consequently, r = 0. We can simply use 0 for r in the equations previously derived.
E E

We begin with the input impedance.

′
Zin−base = β(re + rE )

Zin−base = 150(60.5Ω + 0)

Zin−base = 9075Ω

This value is considerably smaller than the value obtained from the swamped circuit. Continuing,

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 Zin = RB || Zin(base)

Zin = 15kΩ ∣∣ 9075Ω

Zin = 5654Ω

rC
Av = −
′
re + rE

13.2kΩ
Av = −
60.5Ω + 0

Av = −218.2

The end result is an input impedance less than half of the swamped case and a voltage gain over 30 times greater. What these
calculations do not show is the increase in distortion that will be created by this change. More on that in a moment.

Let's consider something slightly different: a voltage divider bias PNP amplifier.

Example 7.3.3

Determine the input impedance and voltage gain for the circuit shown in Figure 7.3.5 . Also determine vload if vin = 20 mV
peak. Assume β = 100.

Figure 7.3.5: Schematic for Example 7.3.3.

We need to first determine r which means that we need to find the collector current. If we assume a lightly loaded divider, the
′
e

base voltage will be approximately 15 volts and the emitter will be 0.7 volts higher, or 15.7 volts. This leaves 20 volts − 15.7
volts, or 4.3 volts, across the DC equivalent emitter resistance. That's 4.1 k Ω + 200 Ω, or 4.3 kΩ, yielding 1 mA for I . This C

will produce r = 26 Ω.
′
e

′
Zin(base) = β(re + rE )

Zin(base) = 100(26Ω + 200Ω)

Zin(base) = 22.6kΩ

This value is in parallel with the voltage divider biasing resistors, creating the input impedance.
Zin = R1 || R2 || Zin(base)

Zin = 15kΩ||5kΩ||22.6kΩ

Zin = 3.22kΩ

rC
Av = −
′
re + rE

7.5kΩ||10kΩ
Av = −
26Ω + 200Ω

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 Av = −19

We also need to include the effect of the 600 Ω source impedance. This will create a voltage divider with the input impedance.
Zin
Adivider =
Zin + Zsource

3.22kΩ
Adivider =
3.22kΩ + 600Ω

Adivider = 0.843

Av(system) = Av × Adivider

Av(system) = −19 × 0.843

Av(system) = −16

Finally, we get to the load voltage.

Vload = Av(system) × Vin

Vload = −16 × 20mV

Vload = 320mV peak, inverted

If we were to inspect the circuit of Figure 7.3.5 using a direct coupled oscilloscope, we would see the superposition of the AC and
DC components. In other words, we'd see the AC signal riding on a DC offset. In some cases, the AC signal would be too small to
notice compared to the DC portion. In proper scale it might be no thicker than the trace itself. In order to measure it accurately,
we'd have to AC couple the oscilloscope.
The voltages at the source and load would be just AC as the coupling capacitors serve to block DC. At the base we'd have 15 volts
DC with an AC signal riding on top of it. The AC would be the 20 mV input times the input impedance/source impedance divider
of 0.843, or 16.86 mV. Recalling that I is 1 mA, the DC drop across R must be 7.5 volts. This is, of course, V . Therefore, at
C C C

the the collector we'd see an inverted 320 mV signal riding on 7.5 volts DC.

Computer Simulation
In order to get some insight into the swamping-versus-distortion issue, we shall take a look at a more involved circuit simulation.
This will echo Examples 7.3.1 and 7.3.2 in that we will simulate two circuits with the same DC equivalents. The only circuit
change will be that one version will have a fully bypassed emitter while the other version will utilize a swamping resistor. In order
to keep the comparison fair, we will increase the input signal voltage of the lower gain swamped amplifier so that both versions
have a similar load voltage. In this way we guarantee that they are both using a similar percentage of the junction curve.
The unswamped circuit is shown in Figure 7.3.6. This utilizes a straightforward two-supply emitter bias.

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 Figure 7.3.6: Unswamped CE amplifier in simulator.
A quick “back-of-an-envelope” estimate gives I ≈ 2 mA, yielding r
C
′
e ≈ 13Ω . The load will be around 3 kΩ which gives a gain in
the low 200s. Thus, we expect the load voltage to be around 2 volts.
The transient analysis graph is depicted in Figure 7.3.7. Several traces are shown.

Figure 7.3.7: Unswamped CE amplifier, Transient Analysis.

At this scale, the AC signal at the input (node 4, purple) and the base (node 2, aqua) cannot be seen. As expected, we see a small
negative DC value at the base and at the emitter, around −0.7 VDC. The DC offset at the collector is around 8 volts, as expected.
Finally, the load voltage (node 5, blue) is sitting right around 2 volts.
What might not be visible immediately in the load voltage plot is some waveform asymmetry distortion. This can be quantified
through a THD simulation, the output of which is shown in Figure 7.3.8. THD is nearly 8%. Not so good.

Figure 7.3.8: Non-swamped CE amplifier, THD Analysis.

For the second pass, the circuit is modified to include a swamping resistor, as illustrated in Figure 7.3.9. The original 4.7 kΩ
emitter resistor has been split into a 4.5 kΩ and a 200 Ω swamping resistor. The bias in this circuit is identical to the first, therefore
r is unchanged. This will lower our expected gain to around 13, decreasing by a factor of 15. The input signal is raised by a factor
′
e

of 15 to compensate so that our load voltage will still be around 2 volts.

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 Figure 7.3.9: Swamped CE amplifier in simulator
Once again, we run a transient analysis. The results are shown in Figure 7.3.10. In this case we have done something a little
different. By zooming in, we can now confirm the signal inversion. The input signal is the purple trace at node 4. We can also see
this signal at the base, riding on the small negative DC bias voltage (aqua trace, node 2). The DC offset is about −0.1 volts.
Looking at the emitter we see the expected 0.7 volt DC base-emitter drop below this, or about −0.8 volts DC. Notice that there is
no AC signal at the emitter whatsoever. This is expected as the emitter bypass capacitor forces this point to an AC ground.
The load voltage is the blue trace, node 5. While much of it is not visible at this zoom level, clearly it is an inverted waveform
when compared to the input signal.

Figure 7.3.10: Swamped CE amplifier, Transient Analysis.

But what about the load voltage distortion? A THD simulation is performed on the swamped amplifier with the results shown in
Figure 7.3.11. The THD is now under .6 %, a considerable improvement, even if not audiophile quality. Interestingly, as a ratio, the
reduction in distortion is roughly equal to the reduction in gain. The more you give up, the more you get.

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 Figure 7.3.11: Swamped CE amplifier, THD Analysis.
Finally, the change in signal quality can be seen readily by plotting both load voltages concurrently, as shown in Figure 7.3.12. The
non-swamped output (in blue) exhibits telltale asymmetry. Notice that the positive peak does not quite reach 2 volts but the
negative peak exceeds −2 volts. The positive peak is also broadened and flattened, while the negative peak is sharper. In contrast,
the swamped output (in red) has virtually identical positive and negative peak values with no apparent shape changes on them.
Compare this simulation to the waveform distortion discussion from Chapter 6. In particular, compare Figure 7.3.12 to Figure
6.3.4.

Figure 7.3.12: Swamped versus non-swamped CE amplifiers, Transient Analysis.

7.3.4: Power Supply Bypass and Decoupling

In the prior analyses we have assumed ideal behavior from the DC power sources. First, we assumed that they present a perfect AC
ground and second, that they exhibit no ripple or noise. In reality, this may not be the case and non-ideal behavior may lead to a
number of problems that diminish the quality of the amplified output signal, including hum and oscillations.
To battle the first issue, power supply bypass capacitors may be used. These capacitors are usually modest in size, perhaps 1 μ F or
so, although they can be much larger, particularly with high output power amplifiers. Power supply bypass capacitors are located
physically close to the active devices. This location minimizes the resistive and inductive effects of power supply circuit board
traces and wiring that could result in the power supply not being a good AC ground.
The second issue involves the noise and ripple from the power supply finding its way into the input signal and becoming part of the
output signal. A classic example of this is amplifiers that use voltage divider biasing such as the one shown in Figure 7.3.5. Not
only does the divider create the needed DC potential at the base terminal, but it also couples in any noise or ripple that might be
riding on the DC voltage. This is particularly nasty because this undesirable signal is being applied to the base where it will get
amplified.
The obvious solution to this problem is to create a very high quality, regulated DC supply, but this is not always practical given cost
constraints. A relatively simple solution is to decouple the undesirable AC components through an RC network as shown in Figure
7.3.13.

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 Figure 7.3.13: Decoupled voltage divider.
The capacitor C is used to create an AC ground at the divider junction, thus shunting any noise or ripple to ground. Unfortunately,
D

this would also short out the input signal so R is added to prevent this. R is in parallel with Z
3 3 to create the input
in(base)

impedance.

References
1
The obvious question is, “How do we get both high gain and low distortion?” One answer is to use multiple low gain stages in
cascade.
2
Is “funsies” a real word? It is if we all agree that it is. Besides, if it was an imaginary word, we'd spell it “j funsies”.

This page titled 7.3: Common Emitter Amplifier is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James
M. Fiore via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.

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7.4: Common Collector Amplifier
The common collector amplifier is often referred to as an emitter follower, or more generically, as a voltage follower. The key
characteristics of a voltage follower are a high input impedance, a low output impedance and a non-inverting voltage gain of
approximately one. The name comes from the fact that output voltage follows the input, that is, it's at the same voltage level and is
in phase with the input. While this configuration does not produce voltage gain, it does produce current gain, and therefore, power
gain. It's primary purpose is to reduce impedance loading effects, for example, to match a high impedance source to a low
impedance load. Consequently, they are used as high-Z input buffer stages or as drivers for low impedance loads such as
loudspeakers.
A common collector amplifier using two-supply emitter bias is shown in Figure 7.4.1. The input is coupled into the base like the
common emitter amplifier, however, the output signal is taken at the emitter instead of at the collector. Because the collector is at
the AC common, there is no need for a collector resistor.

Figure 7.4.1: Common collector amplifier.

Perhaps the best way to think about the follower is not that it gives a voltage gain of one, but that it will prevent signal loss. The
analysis follows, using Figure 7.4.2.

Figure 7.4.2: AC equivalent of common collector amplifier.

First, the AC emitter resistance, r , is either the emitter bias resistor, R , or the parallel combination of R and the load
E E E

resistance, R . We'll use the former in order to determine the unloaded gain and the latter to determine the loaded gain, similar to
L

what we did with the common emitter amplifier concerning R and R . The AC base resistance, r , typically boils down to the
C L B

base biasing resistor just as we saw with the common emitter amplifier (R in a two-supply emitter bias or R ||R for a voltage
B 1 2

divider bias).

7.4.1: Voltage Gain

The derivation for the emitter follower's voltage gain equation is similar to that shown for the common emitter amplifier. We begin
with the basic definition of voltage gain and then expand using Ohm's law.

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 vout vE
Av = = (7.4.1)
vin vB

iC rE
Av =
′
iC (re + rE )

rE
Av =
′
re + rE

This equation is very similar to that of Equation 7.3.1. Here we see that the output signal is in phase with the input and that if
≫ r , the gain approaches unity. Signal distortion tends to be low in followers because a gain of one is a desired goal.
′
rE e

7.4.2: Input Impedance

The derivation for Z and
in Zin(base) are unchanged compared to the common emitter configuration. The formulas are repeated
below for convenience.
′
Zin(base) = β(re + rE )

Zin = rB || Zin(base)

7.4.3: Output Impedance

The derivation for common collector output impedance varies considerably from that of the common emitter. We shall use Figure
7.4.3 for the analysis.

First, note that this diagram splits the AC emitter resistance into its two components, R and the biasing resistor R . This is
L E

because we want to find the effective resistance of the source that drives the load, so logically we can't include the load in that
value. We begin by looking back into the emitter from the perspective of the load. We see the emitter bias resistor in parallel with
whatever the impedance is looking back into the emitter terminal.

Figure 7.4.3: Common collector output impedance analysis.

Zout = RE || Zout(emitter) (7.4.2)

Zout(emitter)is equal to r in series with the equivalent resistance of the network above it and to the left. The internal resistance of
′
e

the current source is high enough to ignore so we're left with the equivalent resistance looking back off the base. We'll call this
Z . At first glance this might appear to be the parallel combination of r
B(equivalent) and r , but this ignores the effect of the
gen B

collector current source. What we really want is the effective resistance as seen from the perspective of r , not as seen from the
′
e

base terminal.
′
Zout(emitter) = re + ZB(equivalent) (7.4.3)

vB
ZB(equivalent) = (7.4.4)
iC

iB (rB || rg en)
ZB(equivalent) =
βiB

rB || rgen
ZB(equivalent) =
β

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Combining Equations 7.4.2, 7.4.3 and 7.4.4 yields
rB || rgen
′
Zout = RE || ( re + ) (7.4.5)
β

In many instances the emitter bias resistor is large enough to ignore.

Example 7.4.1

For the follower shown in Figure 7.4.4, determine the input impedance, output impedance and load voltage. Assume β = 100
and V = 100 mV.
in

First, find I in order to find r . Assuming an unloaded divider, V will equal half of the DC supply, or 10 volts. We lose 0.7
C
′
e B

volts across the base-emitter junction leaving 9.3 volts across the 10 kΩ. This results in a collector current of 930 μ A and an r′
e

of 28 Ω.

Figure 7.4.4: Schematic for Example 7.4.1.

To find Z in

′
Zin(base) = β(re + rE )

Zin(base) = 100(28Ω + 10kΩ||500Ω)

Zin(base) = 50.4kΩ

Zin = R1 || R2 || Zin(base)

Zin = 22kΩ||22kΩ||50.4kΩ

Zin = 9.03kΩ

This value is not particularly high when compared with the rather large source resistance of 1 kΩ. There will be some signal
loss here due to the voltage divider effect between the two impedances. And now for Z out

rB || rgen
′
Zout = RE || ( re + )
β

22kΩ||22kΩ||1kΩ
Zout = 10kΩ|| (28Ω + )
100

Zout = 37Ω

This value is much, much lower than anything we saw with the common emitter amplifiers. Therefore this circuit can drive
much lower impedance loads with minimal signal loss. The loaded gain from base to emitter is
rE
Av =
′
re + rE

500Ω||10kΩ
Av =
28Ω + 500Ω||10kΩ

Av = 0.9444

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 As mentioned, we need to include the effect of the 1 kΩ source impedance. This will create a voltage divider with the input
impedance.
Zin
Adivider =
Zin + Zsource

9.03kΩ
Adivider =
9.03kΩ + 1kΩ

Adivider = 0.9

Av(system) = Av × Adivider

Av(system) = 0.9444 × 0.9

Av(system) = 0.85

Finally, we get to the load voltage.

Vload = Av(system) × Vin

Vload = 0.85 × 100mV

Vload = 85mV

At this point the question might be, “Why did we go to the trouble of building this circuit when we lost 15% of the input
signal?” Well, consider what would have happened without the circuit. If we had connected the source directly to the load, the
resulting 1 kΩ/500 Ω voltage divider would have dropped the load voltage to 33 mV. This circuit prevented that loss.

7.4.4: A High Impedance Source: The Guitar Pickup

In Example 7.4.1, the source had an internal impedance of 1 kΩ, much higher than we would see with, say, a laboratory function
generator (probably 50 Ω). Things could be much worse. Consider the electric guitar pickup. The job of a pickup is to transform
the vibrations of the guitar strings into an electrical signal so that it can be amplified. It is commonly thought that a pickup is some
form of microphone but this is not true1.
A guitar pickup is little more than a magnet surrounded by numerous turns of fine wire, as shown in Figure 7.4.5. This particular
pickup is for a bass guitar but the construction is similar for all types of guitars and basses.

Figure 7.4.5: Electric bass pickup (cover removed).

Here is it how works: The magnet creates a field around the guitar strings. Because the strings are steel, their reluctance is much
less than the surrounding air, therefore, they distort or bend the magnetic field. When a string is plucked, the field moves back and
forth along with it. As the field moves, the flux lines cut across the coil's wire and this action induces a current in the conductor in
accordance with Faraday's Law of Induction. This current is then fed to the amplifier.
A typical guitar pickup consists of perhaps 5000 turns of very fine wire, 42 AWG being typical. 42 gauge copper wire has a
resistance of around 1.6 Ω per foot so the DC resistance of the coil can be over 5 kΩ. Further, that many turns of wire around a
magnet can produce a very large inductance, perhaps several henries, that is in series with this resistance. There is also distributed
capacitance and cable capacitance in parallel that could be upwards of 1 nF. The result is a complex impedance with resonance
effects, regions of which can be tens of kΩ in magnitude. What makes this more challenging is that because the impedance is a
function of frequency, the voltage divider effect with the amplifier's input impedance also becomes a function of frequency. For
example, the increasing impedance due to X will result in increasing attenuation with frequency. This is akin to turning down the
L

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treble on the amplifier. Generally, not a good result. How do we limit this effect? Simple. We make a circuit with a very, very high
input impedance. How do we do that? Well, there are several ways, including the use of field effect transistors and operational
amplifiers, but we can also obtain high input impedances through the use of a dual BJT configuration called the Darlington pair.

7.4.5: The Darlington Pair

The Darlington pair was invented by Sidney Darlington, an American engineer. The configuration leads to a compound device with
a very high β. Used properly, this can lead to amplifier circuits with very high input impedance. A Darlington pair is shown in
Figure 7.4.6.

Figure 7.4.6: Darlington pair.

The operation is as follows. The base current of the first transistor, Q , is multiplied by the β of Q resulting in Q 's emitter
1 1 1

current. This current is fed into the base of the second transistor, Q , where it is multiplied by the β of Q resulting in Q 's emitter
2 2 2

current. If we treat the pair as a single device, then the effective β of the pair is β β . Given typical values for β, the compound
1 2

value can be in the vicinity of 5000 to 10,000. The functional downside to this arrangement is that V BE is now doubled to 1.4 volts
(for silicon) and the effective r of the pair is doubled as well. These issues are minor when compared to the advantage of the huge
′
e

current gain that can be obtained.

The bottom line when using a Darlington pair is to treat it like an ordinary transistor except that it has a very large β and both V BE

and r are doubled compared to the ordinary values.

′
e

Example 7.4.2

Determine the output voltage for the follower shown in Figure . Assume the input is 100 mV peak and the
7.4.7 β for the
Darlington pair is 10,000.

Figure 7.4.7: Schematic for Example 7.4.2.

The first thing that might look a little odd, at least compared to previous bias circuits, is that the base biasing resistor is so
much larger than the emitter biasing resistor. Normally, this would lead to an unstable Q point but that's not a problem here.
Because β is so large, R can be much larger than normal and we'll still achieve good stability. In fact, we can still use the
B

approximation that the base is at DC ground. This being true, the analysis proceeds as follows
∣ VEE ∣ −VBE
IC =
RE

10V − 1.4V
IC =
3.3kΩ

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 IC = 2.61mA

26mV
′
re = 2 ×
IC

52mV
′
re =
2.61mA

′
re = 20Ω

′
Zin(base) = β(re + rE )

Zin(base) = 10, 000(20Ω + 3.3kΩ||150Ω)

Zin(base) = 1.63M Ω

This value is in parallel with the base biasing resistor, creating the input impedance.

Zin = RB || Zin(base)

Zin = 220kΩ||1.63M Ω

Zin = 194kΩ

This is much higher than we have seen in previous circuits. The loaded gain from base to emitter is
rE
Av =
′
re + rE

150Ω||3.3kΩ
Av =
20Ω + 150Ω||3.3kΩ

Av = 0.88

Now to include the effect of the 4.7 kΩ source impedance. This will create a voltage divider with the input impedance,
minimal as it turns out.
Zin
Adivider =
Zin + Zsource

194kΩ
Adivider =
194kΩ + 4.7kΩ

Adivider = 0.976

Av(system) = Av × Adivider

Av(system) = 0.88 × 0.976

Av(system) = 0.86

The load voltage is

Vload = Av(system) × Vin

Vload = 0.86 × 100mV

Vload = 86mV

If we had connected the source directly to the load, the 4.7 kΩ/150 Ω divider would have squashed the applied signal into a
shadow of its former size, leaving us with just 3 mV.

Computer Simulation
To verify the results of Example 7.4.2, we'll run a transient analysis. The input schematic is shown in Figure 7.4.8.

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 Figure 7.4.8: Simulation schematic for Darlington pair follower.
Of interest here will be the voltages at the source, base and load. As the input impedance/source impedance divider was 0.976, we
expect 97.6 mV at node 4. At the output, node 6, we expect to see our final computed value of 86 mV. The output plot of the
simulation is shown in Figure 7.4.9. The simulation concurs.

Figure 7.4.9: Transient analysis for Darlington pair follower.

7.4.6: The Phase Splitter

A phase splitter is a combination of a common emitter amplifier and a common collector follower using a single transistor. The
purpose of the circuit is to produce two versions of the input signal: a buffered version identical to the input and an inverted
version, both waves having the same amplitude. The circuit is used for differential line driver systems. This scheme helps to
minimize outside noise and interference picked up by communications cables. There are other ways to create phase splitters,
including using differential amplifiers or op amps, but this BJT-based version is a minimalist solution2. The basic circuit is shown
in Figure 7.4.10.

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 Figure 7.4.10: A simple phase splitter.
For proper operation, the circuit is largely symmetrical. That is, R = R , R = R , and C = C . That being the case, the
L1 L2 E C C E

AC collector and emitter resistances will be equal (r = r ). If we then look at the basic gain equations, we find that both loads
C E

will receive the same gain magnitude (just under unity), although R will see the signal inverted.
L1

rC
Av = − Common emitter amplifier
′
re + rE

rE
Av = Common collector follower
′
re + rE

References
1
Don't believe it? Just try screaming into one and listen to what comes out of the guitar amp.
2
For details on alternate methods, see Fiore, J, Operational Amplifiers and Linear Integrated Circuits: Theory and Application,
another free OER text.

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7.5: Common Base Amplifier
The third and final prototype is the common base amplifier. In this configuration the input signal is applied to the emitter and the
output is taken from the collector. The base terminal is at the common ground point. An example, using two-supply emitter bias, is
shown in Figure 7.5.1. Note that because neither the input nor output is connected to the base, there is no need for a base resistor.
Consequently, the base terminal is connected directly to ground.

Figure 7.5.1: Common base amplifier.

Some people find that redrawing the schematic horizontally helps to visualize the signal flow. This version is shown in Figure
7.5.2.

Figure 7.5.2: Common base amplifier redrawn.

One nice thing about the horizontal version is that when we make the AC equivalent, it becomes obvious that R is in parallel with
E

the input and R is in parallel with the load. For the AC analysis we shall modify Figure 7.5.2 by substituting the BJT model for
C

transistor, shorting the capacitors and taking the DC sources to AC ground. The result is shown in Figure 7.5.3.

Figure 7.5.3: Common base amplifier with BJT model.

7.5.1: Voltage Gain

We begin with the basic definition of voltage gain and then expand using Ohm's law.
vout vC
Av = = (7.5.1)
vin vE

iC rC
Av =
′
iE re

rC
Av =
′
re

This equation is very similar to that of a non-swamped common emitter amplifier except that it does not invert the input signal.
Therefore, gain potential is fairly high.

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7.5.2: Input Impedance
The derivation for Z in is obtained via direct inspection of the schematic.
′
Zin = RE || re (7.5.2)

′
re normally dominates and thus we see that the common base configuration tends to have a low input impedance. For audio
frequencies this can be an issue but it is less of a problem at higher frequencies as, generally speaking, system impedances need to
be lower to avoid complications with capacitive effects.

7.5.3: Output Impedance

The derivation for Z out unchanged compared to the common emitter configuration. The formula is repeated below for convenience.

Zout ≈ RC

Example 7.5.1

For the amplifier shown in Figure 7.5.4, determine the voltage gain and input impedance.

Figure 7.5.4: Schematic for Example 7.5.1.

∣ VEE ∣ −VBE
IC =
RE

5V − 0.7V
IC =
20kΩ

IC = 0.215mA

26mV
′
re =
IC

26mV
′
re =
0.215mA

′
re = 121Ω

′
Zin = re || rE

Zin = 121Ω||20kΩ

Zin = 120Ω

rC
Av =
′
re

33kΩ||10kΩ
Av =
120Ω

Av = 64

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7.6: Multi-Stage Amplifiers
In order to achieve a higher gain than we can obtain from a single stage, it is possible to cascade two or more stages. Different
biasing types might be used along with a mix of AC configurations such as a common collector follower for the first stage that
drives a common emitter voltage amplifier. A mix of NPN and PNP devices may also be present.
In general terms, each stage serves as the load for the preceding stage. That is, the Z of one stage is the R of the previous stage.
in L

The gains of the individual stages are then multiplied together to arrive at the system gain. The system input impedance is the input
impedance of the first stage only. The source drives the first stage alone. The first stage, in turn, drives the second stage, and so on.
Therefore the source only “sees” the first stage because it is the only stage to which it delivers current. In a similar fashion, the
output impedance of the system is the Z of the last stage. An example is shown in Figure 7.6.1.
out

Figure 7.6.1: Two stage amplifier.

In this circuit, stage one is a non-swamped common emitter amplifier utilizing twosupply emitter bias. Stage two is a swamped
common emitter amplifier using voltage divider bias. As far as the DC analysis is concerned, these are two separate circuits. The
inter-stage coupling capacitor, C inter, prevents the DC potential at the collector of the first transistor from interfering with the bias
established by R and R for transistor number two. For the AC computation, the first stage is analyzed in normal fashion except
1 2

that its load resistance is comprised of R ||R ||Z

1 2 (i.e., Z of stage 2). The second stage is analyzed without changes and
in−base2 in

its gain is multiplied by the first stage's gain to arrive at the final gain for the pair. The input impedance of the system is
R || Z
B in−base1 (i.e., Z of stage 1).
in

It should be obvious that by cascading several stages it is possible to achieve very high system gains, even if each stage is heavily
swamped in order to reduce distortion. For example, three swamped common emitter stages with voltage gains of just 10 each
would produce a system voltage gain of 1000.

7.6.1: Direct Coupling

With a little creativity, it is possible to create multi-stage designs that use fewer components but which achieve higher performance.
One technique is to employ direct coupling of the stages. Direct coupling allows DC to flow from stage to stage. As such, it is
possible to design an amplifier that has no lower frequency limit. An example is shown in Figure 7.6.2.

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 Figure 7.6.2: Direct coupled amplifier.
This two-stage amplifier uses no coupling capacitors nor does it rely on voltage divider resistors for the second stage1. Here is how
it works: The first stage is a fairly ordinary swamped common emitter amplifier using two-supply emitter bias. It also uses a
Darlington pair to maximize the input impedance. Because the base current is so low, the DC drop on R could be small enough to
B

ignore so we may dispense with the input coupling capacitor. The DC potential at the collector of the Darlington is applied directly
to the base of the second stage. This is used to set up the bias of the second stage via the stage two emitter resistors. This is
precisely what we did with the circuit of Figure 7.3.5. The only difference is that here the base voltage is derived from the
preceding stage instead of from a voltage divider. The computations for I , r and the like would proceed unchanged. In any event,
C
′
e

this eliminates two biasing resistors and another coupling capacitor.

Note the use of the PNP device for the second stage. By using a PNP, its collector voltage must be less than its emitter voltage. As
we're also using a bipolar power supply, we can eliminate the need for the final output coupling capacitor. All we need to do is set
up the resistor values such that the drop across R is the same as V . This will place the stage two DC collector voltage at 0
C2 EE

volts. If there's no DC voltage then there's nothing to block, and therefore no need for the coupling capacitor.

References
1
This circuit does use emitter bypass capacitors so the DC gain will be less than the AC gain. In that sense we might say that this
amplifier is not fully DC coupled.

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7.7: Summary
A simplified AC model of the bipolar junction transistor consists of a controlled current source in the collector and a dynamic
resistance in the emitter called r . This resistance is a function of the DC bias current, I ; the higher the biasing current, the lower
′
e C

the resistance. Fluctuations in this resistance can lead to waveform distortion. Swamping, also known as emitter degeneration, is a
technique used to reduce distortion and stabilize gain. The basic idea is to add a fixed resistor in series with the emitter so as to
buffer or “swamp out” the changes of r .′
e

There are three basic AC amplifier configurations: common emitter, common collector and common base. The common emitter
configuration produces a voltage amplifier with high gain and intermediate input impedance. It also inverts the signal. Because it
exhibits both voltage gain and current gain, it has a potential for high power gain. The common collector configuration is known as
a follower because its output follows the input. It produces a non-inverting voltage gain of one and exhibits high input impedance
and low output impedance. Therefore, it is useful as either an input buffer or as a final drive stage to a low impedance load. The
common base configuration exhibits high non-inverting voltage gain. It has a low input impedance and a high output impedance.
The Darlington pair is a two-transistor configuration that may be treated as a single device. As such, it exhibits a doubling of both
VBE and r , and a very large β.
′
e

In order to achieve higher gains, multiple stages may be cascaded. Their gains multiply together to produce the combined system
gain. The stages may be coupled through capacitors or via a capacitor-less direct coupling technique that can improve performance
while reducing component count.

7.7.1: Review Questions

1. How does the AC BJT model compare with the DC model? What are the differences and similarities?
2. Explain how swamping reduces waveform distortion.
3. Compare and contrast common emitter, common collector and common base amplifiers in terms of voltage gain, power gain,
input impedance and output impedance.
4. Why might biasing circuits that produce stable Q points be preferred for non-swamped amplifiers?
5. What is a phase splitter?
6. What are the advantages of direct coupling?
7. Give at least one example of a high internal impedance source.

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7.8: Exercises
Unless otherwise specified, use β = 100.

7.8.1: Analysis Problems

1. Determine the input and output impedances of the circuit of Figure 7.8.1.

Figure 7.8.1
2. Determine the load voltage for the circuit of Figure 7.8.1 if V in is 10 mV.
3. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.2 if V in is 70 mV.

Figure 7.8.2
4. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.3 if V in is 50 mV.

Figure 7.8.3
5. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.4 if V in is 25 mV.

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 Figure 7.8.4
6. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.5 if V
in is 30 mV.

Figure 7.8.5
7. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.6 if V
in is 60 mV.

Figure 7.8.6
8. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.7 if V
in is 150 mV.

Figure 7.8.7

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9. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.8 if V in is 200 mV.

Figure 7.8.8
10. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.9 if Vin is 250 mV.

Figure 7.8.9
11. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.10 if V in is 300 mV.

Figure 7.8.10
12. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.11 if V in is 50 mV.

Figure 7.8.11
13. Determine Z , Z
in out , and the load voltage for the circuit of Figure 7.8.12 if V in is 2 mV.

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 Figure 7.8.12

7.8.2: Design Problems

14. Redesign the circuit of Figure 7.8.2 to halve the existing gain while keeping the Q point where it is currently.
15. By using a Darlington pair, redesign the circuit of Figure 7.8.3 to double Z .in

16. Redesign the circuit of Figure 7.8.3 so that it exhibits the same performance parameters but uses a PNP device.
17. Redesign the circuit of Figure 7.8.5 to double the existing gain while keeping the Q point where it is currently.
18. Redesign the circuit of Figure 7.8.7 so that it exhibits the same performance parameters but uses an NPN device.

7.8.3: Challenge Problems

19. Determine the gain and input impedance for the circuit of Figure 7.8.13. V CC = 20 V, VEE= −10 V, R = 18 kΩ, R
B E1 = 10 k
Ω, R C1 = 12 kΩ, R = 33 kΩ, R = 15 kΩ, R = 5.6 kΩ, R
1 2 E2 = 400 kΩ, R
SW C2 = 6.8 kΩ, R = 24 kΩ.
L

Figure 7.8.13
20. For the circuit of Figure 7.8.10, replace its load resistor with the circuit of Figure 7.8.6 and determine the combined gain and
input impedance of the system.

7.8.4: Computer Simulation Problems

21. Use a transient analysis to verify the load voltage of problem 3.
22. Use a transient analysis to verify the load voltage of problem 4.
23. Use a transient analysis to verify the load voltage of problem 8.
24. Consider the amplifier of Figure 7.8.1. Replace the 4.3 kΩ emitter resistor with a potentiometer of the same value. Connect the
wiper arm to the emitter bypass capacitor. Run several transient analyses at different pot settings (0%, 25%, 50%, etc.). What can
you conclude from the results?

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 CHAPTER OVERVIEW

8: BJT Class A Power Amplifiers

Learning Objectives
After completing this chapter, you should be able to:
Define class A operation.
Determine AC load lines for class A amplifier stages.
Determine the compliance and maximum load power for class A amplifier circuits.
Determine the efficiency and required device ratings for class A amplifier circuits.
Describe the operation of a dynamic loudspeaker.
Understand the need for heat sinks and other thermal management techniques.

8.1: Introduction
8.2: Amplifier Classes
8.3: Class A Operation and Load Lines
8.4: Loudspeakers
8.5: Power Transistor Data Sheet Interpretation
8.6: Heat Sinks
8.7: Summary
8.8: Exercises

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request.

1
8.1: Introduction
Now that we have examined BJT voltage amplifiers in terms of their gain, input impedance and output impedance, it is time that
we extend the small signal analysis to larger signals. Of primary importance will be determination of the maximum output voltage
swing, or compliance, along with maximum load power, device dissipation requirements and amplifier efficiency. To assist with
this, we introduce the concept of the AC load line. In general, we will not concern ourselves with input impedance, voltage gain or
even r . Indeed, we shall simply consider r as a source of distortion. Most power amplifiers are configured as voltage followers
′
e
′
e

so we will focus largely on those.

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8.2: Amplifier Classes
There are several classes of amplifier operation. The class of an amplifier has nothing to do with the fidelity or quality of the
amplifier. Rather, the class indicates the fundamental operational principle of the circuit. In general, as the class letter increases, the
designs become more complicated but also more efficient. For audio and other linear applications, classes A, B and D are relatively
common these days. Class C is largely relegated to high power telecommunications while classes G and H are essentially variations
of class B.
The definition of class A is that signal current in the collector flows 360 out of the cycle. In other words, it flows for the entire
∘

cycle without interruption. All of the amplifiers that were presented in the prior chapter are class A designs. In class B, i flows for
C

just 180 , and for class D, i is discontinuous; the transistor is used as a switch. Class B and D designs are examined in later
∘
C

chapters.

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8.3: Class A Operation and Load Lines
The signal current in the class A amplifier flows continuously throughout the entire cycle of the waveform. Ultimately, we would
like to known just how large this signal can be before it is limited and grossly distorted. To do so, we need to examine the AC
equivalent of the amplifier. A generic AC equivalent is shown in Figure 8.3.1. This includes both AC collector and emitter
resistances so it can be used for either swamped or unswamped common emitter amplifiers or for emitter followers. If one of the
resistances is not used (for example, r in a follower), we can just substitute a value of zero for it.
C

Figure 8.3.1: AC equivalent circuit.

The voltage polarities and current direction are shown for a positive input voltage. To determine the maximum load voltage swing
(compliance), we will need to construct an AC load line as shown in Figure 8.3.2.

Figure 8.3.2: AC and DC load lines.

The AC load line is similar to the DC load line that was used for analyzing biasing circuits. As in the DC version, there will be a
cutoff voltage, v , and a saturation current, i
C E(cutof f ) . The AC and DC load lines normally are not the same, however, they
C (sat)

must share one point in common, and that's the Q point. Usually, the slope of the AC load line is steeper than that of the DC load
line. This is because the AC resistance tends to be less than the DC resistance due to loading and capacitor bypassing.
Consequently, v tends to be smaller than V
C E(cutof f )
and i
C E(cutof f )
tends to be larger than I
C (sat)
. C (sat)

To determine expressions for the AC load line endpoints, let's examine the AC equivalent circuit. Because both load lines share the
Q point, we can consider the circuit of Figure 8.3.1 as having a no-signal current of I and a no-signal transistor voltage of
CQ

VC EQ . As the input signal grows, i increases. The effect of this is to increase the voltage drops across r and r due to Ohm's
C E C

law. This, in turn, forces v to decrease due to KVL. The collector current can only increase to the point where v drops to 0 V.
CE CE

This is a maximum increase of V /(r

C EQ + r ) . Therefore
C E

VC EQ
iC (sat) = IC Q + (8.3.1)
rE + rC

In terms of cutoff voltage, the transistor starts with V and I . The largest v increase that can occur is if the current falls to
C EQ CQ CE

zero. Then, all of the potential originally developed across r and r by I must be absorbed by the transistor. Therefore
E C CQ

vC E(cutof f ) = VC EQ + IC Q (rE + rC ) (8.3.2)

There are three possible ways this can be configured: Q point closer to saturation, Q point closer to cutoff, or Q point centered on
the AC load line. Let's first consider the Q point closer to saturation. This is shown in Figure 8.3.3.

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Here we have plotted the input voltage in red and drawn the corresponding collector current and collector-emitter voltage in blue. It
is apparent that as the input signal increases, eventually, the output signal is limited at zero for v and at i
CE for i . The two
C (sat) C

blue waveforms are severely clipped and distorted. The largest unclipped peak voltage swing is V C EQ and the largest peak current
swing is i
C (sat)−I CQ , or more conveniently, V
C EQ /(r
E +r ).
C

Figure 8.3.3: AC load line, Q point closer to saturation.

If we shift the Q point toward cutoff, we solve the saturation clipping problem but now we have a new problem, as illustrated in
Figure 8.3.4. It should come as no surprise that we now have cutoff clipping.

Figure 8.3.4: AC load line, Q point closer to cutoff.

In this version the largest unclipped peak voltage swing is v −V
C E(cutof f ) C EQ (or alternately, I (r + r )) and the largest peak
CQ E C

current swing is I . What's important here is that the waveform has been clipped. It doesn't really matter which side has been
CQ

clipped, either way it's gross distortion. Eventually, every amplifier will have a limit but we will be able to produce the largest
unclipped voltage swing if the Q point is centered on the AC load line. This is shown in Figure 8.3.5.

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 Figure 8.3.5: AC load line, centered Q point.
With a centered Q point, the largest unclipped peak voltage swing is V and the largest unclipped peak current swing is I . By
C EQ CQ

examining equations 8.3.1 and 8.3.2 it is apparent that in order to achieve a centered Q point on the AC load line, the following
must be true:
VC EQ
= rE + rC (8.3.3)
IC Q

Of course, while it is useful to determine the maximum voltage across the transistor, it is more important to determine the
maximum voltage across the load. Looking back at the circuit of Figure 8.3.1, most times the maximum load voltage (i.e., the
compliance) will equal the maximum transistor voltage. This will be the case in voltage followers and unswamped amplifiers. The
only time there will be a noticeable reduction is with very heavily swamped amplifiers. In this case the compliance will be reduced
by the voltage divider between the load and swamping resistors. For example, a swamped amplifier with a voltage gain of 4 would
lose about 20% of the maximum swing. Swamping has to be very heavy resulting in very low gains before appreciable signal is
lost.
Thus we arrive at the following general rule:
Peak compliance is the smaller of VC EQ or IC Q (rE + rC ) (8.3.4)

Knowing the compliance, the maximum load power may be determined using power law. Power is determined using RMS values,
–
so the peak compliance will need to be divided by √2 (or multiplied by 0.707) before continuing.
2
C omplianceRMS
Pload(max) = (8.3.5)
RL

There is something important to note about this equation. It uses the load resistance value, not the total AC effective value (i.e., not
rL which is R in parallel with a biasing resistor). If r was used, we'd be calculating the power in the load plus the power in the
L L

biasing resistor.
We would also like to determine the maximum power dissipated by the transistor. Because the transistor's current and voltage are
fluctuating with the input signal, we need to determine the magnitude of the load voltage that produces maximum power in the
transistor. Intuitively, we might guess that this occurs at maximum load power but it turns out that this guess is incorrect. Under no-
signal conditions the transistor is operating statically at the Q point. Therefore, quiescent power dissipation is

PDQ = VC EQ IC Q (8.3.6)

In contrast, at full load for a centered Q point, we have

vC E = VC EQ (1 − sin 2πf t)

iC = IC Q (1 + sin 2πf t)

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 PD = vC E iC (8.3.7)

PD = VC EQ (1 − sin 2πf t) × IC Q (1 + sin 2πf t)

2
PD = VC EQ IC Q (1 − sin 2πf t)

PD = VC EQ IC Q (.5 + .5 cos 4πf t)

PDQ PDQ
PD = + cos 4πf t
2 2

The first term of Equation 8.3.7 is a fixed offset while the second term is a sinusoid at twice the signal frequency. Because the peak
amplitude of this sinusoid is the same as the fixed offset, the average over time is simply the offset value. These waveforms are
illustrated in Figure 8.3.6.

Figure 8.3.6: Transistor power dissipation at full load power.

The result is that the transistor only dissipates half the power at full load that it dissipates under idle conditions. This makes perfect
sense if you stop to consider that the class A amplifier always draws the same power from the DC supplies, regardless of the size of
the load signal. Without clipping, the average current will be I . That current times the supply voltage yields the supplied power.
CQ

What's happening is that as the signal increases in amplitude, more and more of the power dissipated by the transistor is shifted to
the load. At maximum load swing, both the transistor and the load will be dissipating P /2. As strange as it might seem, if you
DQ

want to keep the output transistor of a class A amplifier cool, don't turn the volume down, turn it up.
The foregoing implies that class A designs are not power efficient. This is indeed the situation. As we have just seen, the best case
maximum load power will be one half of P , assuming a centered Q point (non-centered will be worse). To achieve this swing,
DQ

the power supply will have to be at least twice as large as V because it has to cover the peak-to-peak swing, while V
C EQ C EQ

represents the peak swing for a centered Q point.1 In any event, the best case efficiency turns out to be dismal, as follows.
Pout Pload
η = =
Pin PDC

PDQ /2
η =
2VC EQ IC Q

PDQ /2
η =
2PDQ

η = 25%

This represents the maximum or best case efficiency for an RC coupled class A amplifier. It may be considerably less depending
on precisely how it is biased. This, truly, is the Achilles heel of the class A topology: it is wasteful. It draws full power from the
supply regardless if signal is present and, at best, will translate only one quarter of that power into useful load power. At the same
time, the power dissipation of the transistor will need to be at least twice that of the delivered load power, and might need to be
much greater. Why use it then? To its advantage, it is a relatively simple design so if large output powers are not needed, it can

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prove useful. This is most definitely the case for the early stages of a multi-stage amplifier where the amount of load power is very
small (basically the power delivered to the following stage). In that instance, the increased complexity of more power efficient
designs is not warranted or cost effective.

Example 8.3.1

For the amplifier shown in Figure 8.3.7, determine the compliance, maximum load power, worst case transistor dissipation and
efficiency.

Figure 8.3.7: Schematic for Example 8.3.1.

∣ VEE ∣ −VBE
IC Q =
RE

15V − 0.7V
IC Q =
120Ω

IC Q = 119mA

By inspection, V C EQ = 5.7 V. The AC cutoff voltage is

vC E(cutof f ) = VC EQ + IC Q (rC + rE )

vC E(cutof f ) = 5.7V + 119mA(0 + 120Ω||32Ω)

vC E(cutof f ) = 5.7V + 119mA(25.3Ω)

vC E(cutof f ) = 5.7V + 3V

vC E(cutof f ) = 8.7V

The smaller of V C EQ and IC Q (rC + rE ) is the peak compliance, so

compliance = 3V peak

Given the compliance, we can use power law to find the load power
2
C omplianceRMS
Pload(max) =
RL

2
(.707 × 3V )
Pload(max) =
32Ω

Pload(max) = 141mW

This is not a lot of power for something like a loudspeaker but is a fair amount to drive something like a pair of headphones.
The transistor's worst case power dissipation is

PD(max) = PDQ = IC Q VC EQ

PD(max) = 119mA × 5.7V

PD(max) = 678mW

The supplied circuit power is the average current draw times the total supplied voltage differential

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 PDC = IC Q (VC C − VEE )

PDC = 119mA × 20V

PDC = 2.38W

The efficiency is the ratio of maximum load power to supplied DC power

Pload(max)
η =
PDC

141mW
η =
2.38W

η = 5.9%

This is much worse than the theoretical best case. This is due, at least in part, to the fact that the Q point is not centered on the
AC load line.
To complete the analysis, note that the transistor's breakdown rating (BV ) should be at least as large as v
C EO C E(cutof f )
(8.7
volts), and the maximum current rating should be at least as large as i (119 mA+5.7 V/25.3 Ω = 344 mA).
C (sat)

Computer Simulation
A computer simulation of a class A emitter follower using a Darlington pair is examined next. Of primary interest here is the
verification of the output compliance so a transient analysis will be used. The simulator schematic is shown in Figure 8.3.8.

Figure 8.3.8: Class A follower in simulator.

We can make a few quick computations to determine the compliance. First, we find the collector Q point current.
∣ VEE ∣ −VBE
IC Q =
RE

10V − 1.4V
IC Q =
330Ω

IC Q = 26mA

By inspection, the emitter is two base-emitter junction potentials below ground, or −1.4 V. As the collectors are tied to VC C , this
means that V C EQ = 6.4 V. The other half of the swing, from V to v
C EQ is
C E(cutof f )

vC E(cutof f ) − VC EQ = IC Q (rC + rE )

vC E(cutof f ) − VC EQ = 26mA(0 + 330Ω||50Ω)

vC E(cutof f ) − VC EQ = 26mA(43.4Ω)

vC E(cutof f ) − VC EQ = 1.13V

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The Q point is not centered and is closer to cutoff. This means that the amplifier will produce cutoff clipping around 1.1 volts and
saturation clipping around 6 volts. In other words, there is more room for the current to swing up to saturation than to swing down
to zero. As this is the current flowing through the load and we have a non-inverting follower, we expect to see the load voltage
echo this. That is, the negative portion of the load voltage should clip before the positive portion.
The transient analysis results are shown in Figure 8.3.9. A two volt peak input signal is applied (blue trace). The negative portion
of the load voltage clips at approximately 1.1 volts as expected (red trace). The input signal is not large enough to cause saturation
clipping. This was done on purpose to verify the voltage gain of the follower. It should be very close to unity. In fact, the trace
shows that the gain is around 0.95 or so.

Figure 8.3.9: Class A follower transient analysis.

If this had been a voltage amplifier instead of a follower, these waveforms would appear flipped vertically. To verify this, the
circuit is modified to produce a voltage amplifier with a gain of approximately one. This is achieved by moving the load to the
collector and adding a 330 Ω biasing resistor. This will result in the same AC load impedance. To maintain a similar V C EQ ,V CCis
raised by 10 volts. Finally, the original 330 Ω emitter biasing resistor is split in two: 287 Ω and 43 Ω. This will yield the same I CQ

and achieve a voltage gain of unity. As a result, we expect to see clipping at approximately 1.1 volts on the positive portion. The
modified circuit is shown in Figure 8.3.10 and the resulting transient simulation in Figure 8.3.11.

Figure 8.3.10: Class A amplifier in simulator.

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 Figure 8.3.11: Class A amplifier transient analysis.
One final item of interest regarding the simulations: If the input level is increased in an attempt to see clipping on the other half of
the waveform, something strange happens. At first it will appear as though it never clips. A careful examination reveals something
different, though. Given the values in these circuits, they will exhibit a certain amount of clamping action (clamping was presented
in Chapter 3). This will cause the waveform to shift. If you inspect the peak-to-peak value, it will be close to the value of
v . It will be a little less due to the fact that, particularly for a Darlington pair, V
C E(cutof f )
is not 0 V.
C E(sat)

References
1
This is the case if the AC and DC load lines are identical. This is atypical. Consequently, the power supply will tend to be larger
than twice V which makes the situation even worse.
C EQ

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8.4: Loudspeakers
One of the more common loads for amplifiers is a loudspeaker. It makes sense then to look at how they are constructed and note
anything interesting or peculiar as far as their electrical characteristics are concerned. The most common form of loudspeaker is the
dynamic loudspeaker1. All dynamic loudspeakers share certain common elements regardless of size or acoustic output capability. A
cutaway view of a low frequency driver is shown in Figure 8.4.1.

Figure 8.4.1: Dynamic loudspeaker. A. Frame B. Suspension C. Lead wire D. Spider E. Magnet F. Diaphragm G. Voice coil former
H. Voice coil I. Dust cap Image courtesy of Audio Technology
The idea behind its operation is magnetic repulsion and attraction. The heart of the unit is the voice coil (H). This is a coil of
magnet wire wound around a former (G) that typically is made of aluminum or some other high temperature material. The voice
coil might be a single layer of edge-wound ribbon wire or perhaps several layers of ordinary round wire. Depending on the design,
the voice coil might be anywhere from a fraction of an inch to several inches in diameter. The coil ends are connected to flexible
lead wires (C) that terminate on the loudspeaker frame (A). Ultimately, that's what the amplifier will connect to.
The voice coil is fixed to a diaphragm (F) and is freely suspended by an outer edge suspension (B) and an inner element known as a
spider (D). The voice coil sits in a strong magnetic field that is created by a powerful permanent magnet (E) that commonly uses
ceramic, alnico or rare earth construction. When current from the amplifier flows through the coil, it will create it's own magnetic
field that will either aid or oppose the fixed field created by the permanent magnet, depending on the direction of the current. This
results in a force that causes the coil to move within the fixed field. As the coil moves, the diaphragm moves with it, pushing on the
surrounding air and creating sound. The larger the current, the stronger the newly created field and the greater the resulting aid or
opposition, which results in greater movement of the diaphragm and a larger sound pressure. This fundamental design has changed
little since its invention in the 1920s. Modern magnets, suspension and diaphragm materials have improved considerably in the
intervening years but the operational principle is pretty much the same.
It is very difficult to create a driver that can cover the full audio spectrum of 20 Hz to 20 kHz while achieving sufficient listening
volume at low distortion. Consequently, drivers are often designed to cover a limited portion of the audio spectrum. Low frequency
drivers are commonly referred to as woofers while high frequency drivers are called tweeters. Drivers that cover the middle range
of frequencies are given the highly inventive name midranges (although once upon a time they were called squawkers). A
combination of these devices will be wired together with other components to create a complete home or auto loudspeaker system.
Although very high quality systems can be produced, virtually all direct radiating dynamic loudspeaker systems suffer from low
conversion efficiency. For a typical consumer system, only about 1% to 2% of the applied electrical power is turned into useful
acoustic output power. The vast majority of the applied power simply makes the voice coil hot.

8.4.1: Loudspeaker Impedance

Loudspeakers are given a nominal impedance value. The most common impedance for home use is 8 Ω while 4 Ω is common in
automotive systems. It is important to remember that this is a nominal value and the true value varies with frequency. While it is
common to test power amplifiers with large power resistors, they are only a coarse approximation of a real loudspeaker.

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The electrical and mechanical characteristics of a loudspeaker combine to create an equivalent circuit with resistive, inductive and
capacitive elements. A typical electrical circuit model2 of a single loudspeaker driver is shown in Figure 8.4.2. R and L
VC are
VC

the resistance and inductance of the voice coil, respectively. The other components are electrical equivalents of mechanical
properties such as suspension losses.

Figure 8.4.2: Dynamic loudspeaker electrical model.

Clearly, this is not a simple 8 Ω resistor. In fact, we see a very complex impedance: The three parallel elements will create a
resonant peak and the series inductance will cause the impedance to rise with frequency. Typically, the resonant peak occurs at the
lower end of the spectrum and the associated resonant frequency is denoted on a spec sheet as f , the free-air resonance. For a
S

nominal 8 Ω woofer, the peak impedance can be over 30 Ω. An example of a loudspeaker impedance plot is shown in Figure 8.4.3.

Figure 8.4.3: Dynamic loudspeaker impedance plot. Courtesy of Dayton Audio.

This loudspeaker is a nominal 8 Ω unit yet the impedance can be many times this value, and at some frequencies, less than 7 Ω.
This plot also includes the phase angle of the loudspeaker and we can see that it can be upwards of 40 capacitive or inductive,
∘

depending on the frequency. What makes this more interesting is that a consumer loudspeaker system is a combination of multiple
drivers plus other electrical components, and this can result in an even more complex impedance plot.
The obvious question is, “Does this have any effect on the analysis of the power amplifier?” The simple answer is, “Yes”. Areas of
the spectrum where the impedance magnitude drops below the nominal value will require more current for any given load voltage.
Further, the phase shift caused by a partly reactive load will impact the power dissipation of the transistor.
Consider the power graph shown in Figure 8.3.6 for a purely resistive load. If we repeat the plot but add a noticeable phase shift to
simulate a partly reactive load, something interesting happens, as shown in Figure 8.4.4.

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 Figure 8.4.4: Power dissipation with reactive load.
The purple trace represents the power dissipation of the transistor. The peak current-voltage product is twice the value seen with a
purely resistive load. This combination might lay outside the safe operating area of the transistor. Ultimately, reactive loads are
somewhat more “challenging” than simple resistive loads. Therefore, the transistors may need to be rated higher than the values
computed for an idealized resistive load.
Another way of looking at the issue of phase shift induced by loudspeakers and other complex loads is to examine the AC load line.
Our previous work with load lines always assumed that the load was purely resistive. What happens in the complex impedance
case?
If we examine a generic complex load at a single frequency, our former straight line load line turns into an ellipse, as shown in
Figure 8.4.5.

Figure 8.4.5: AC load line with complex load.

This plot assumes that the circuit has a centered Q point. The normal resistive load line is shown in green. We can visualize the
signal starting at zero amplitude, meaning all we see is the Q point. As the signal gets larger and larger, it swings along the green
line until, eventually, it maxes out at the two axes. In the complex impedance case, we also start at the Q point. As the signal
increases, it traces out an ellipse around the Q point. Further increases would create a larger ellipse, and then a larger ellipse, and so
on. Eventually, we would see the maximum swing just touching the axes. This is what is plotted above in red, the maximum case
(i.e., at full compliance).
If the impedance angle changes, the aspect ratio of the ellipse changes in reaction to it. The larger the angle, the more open the
ellipse becomes. The extremes are 0 , the purely resistive case that yields a collapsed ellipse or straight line; and 90 , the purely
∘ ∘

reactive case that yields a fully open ellipse, or circle. We have already seen that the phase angle of a loudspeaker changes with
frequency, therefore, the load line also changes with frequency. As we sweep the input frequency from low to high, we can imagine
the load line wavering back and forth between straight lines and various elliptical shapes. The important thing, though, is that some

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of these new operating regions (the areas where the red curve is above and to the right of the green line) may go outside the safe
operating area of the transistor.

References
1
It's a rather odd name given that all loudspeakers are dynamic in some respect. If they weren't they wouldn't produce sound.
2
Adapted from R. H. Small, “Direct Radiator Loudspeaker System Analysis”, Journal of the Audio Engineering Society, June,
1972.

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8.5: Power Transistor Data Sheet Interpretation
The data sheet for a popular NPN power transistor, the 2N3055, is shown in Figure 8.5.1. This model is available from several
different manufacturers. Due to the high power dissipation, the TO-92 plastic case that is used for small signal devices is not
appropriate. Instead, this device uses the all-metal TO-3 case. Under the maximum ratings we find the device has a maximum
power dissipation of 115 W at a case temperature of 25 C, a maximum collector current of 15 A and a maximum collector-emitter
∘

voltage of 60 V. Obviously, the device cannot withstand maximum current and voltage simultaneously.

Figure 8.5.1a: 2N3055 data sheet. Used with permission from SCILLC dba ON Semiconductor.
In the drawing of the TO-3 case, only two leads are shown. These are for the emitter and base. The entire body of the device is the
collector. This is because the device will most likely be attached to a metal heat sink (see next section) to help dissipate the heat
generated. The greater the contact area, the more effective the heat flow will be. The curves presented in Figure 8.5.1b indicate that
β is considerably lower than what we saw for small signal devices. Further, I C (sat)tends to be larger for higher power transistors.
For very high currents, β might fall to less than 20 while I can be upwards of half of a volt.
C (sat)

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Figure 8.5.1b: 2N3055 data sheet (cont).

Figure 8.5.1c: 2N3055 data sheet (cont).

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One item of note in Figure 8.5.1c is the small graphic at the bottom of the sheet. This is a plot of safe operating area. Basically, the
combination of V CE and I must fall within the lower-left zone. What is of particular interest is that the safe zone extends out
C

further if the current/voltage combination is the result of a short pulse rather than a continuous condition.

8.5.1: Power Derating

One final item of concern is the graph found in Figure 8.5.1a, and magnified in Figure 8.5.2. This is a power derating curve.

Figure 8.5.2: Power derating curve for 2N3055. Used with permission from SCILLC dba ON Semiconductor.
Although the device is rated for 115 watts, that is only true at case temperatures of 25 C or lower. At higher temperatures, the
∘

power dissipation capability decreases. For example, at 100 C this device can only dissipate about 65 watts. A precise value can be
∘

computed via the following formula:

∘
PD = P25 − D(Tcase − 25 C ) (8.5.1)

Where
PD is the power dissipation at the new case temperature,
P25 is the power dissipation at 25 C,
∘

D is the derating factor (units of W/C ), ∘

Tcase is the new case temperature.

Example 8.5.1

Determine the power dissipation of a 2N3055 at 75 C. ∘

Using the graph, this is a little over 80 watts.

For a more accurate result, we'll use Equation 8.5.1. From the data sheet the dissipation at 25 C, P , is 115 watts. The
∘
25

derating factor, D, is 0.657 W/C (the derating factor is found directly above the graph of power derating in Figure 8.5.1a).
∘

∘
PD = P25 − D(Tambient − 25 C )

∘ ∘ ∘
PD = 115W − 0.657W / C (75 C − 25 C )

PD = 82.1W

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8.6: Heat Sinks
The issue with power transistors is always heat. As noted in Example 8.5.1, as the transistor heats up due to internal power
dissipation, its ability to dissipate heat is compromised. The trick, then, is to efficiently move the heat from the transistor to
someplace else. This is normally achieved through the use of a heat sink.
A heat sink is a metal device that is attached to the power transistor. Typically, they are made of aluminum and feature an array of
fins. By increasing the surface area, heat can be moved away from the transistor more efficiently than by the transistor alone.
Heat sinks are designed to mount specific device case styles. The most common case styles include the TO-3 “can” along with the
various “power tab” styles such as the TO-220 and TO-202. Special mounting hardware and insulation spacers are also required in
order to maintain electrical isolation between the transistor and the heat sink as we do not want the heat sink to be electrically live.
This usually takes the form of a mica sheet, and plastic washers and bushings for the mounting machine screws (for small heat
sinks, sometimes nylon machine screws are used).
There are a few general rules that should be followed when using heat sinks:
Always use some form of heat sink grease or thermally conductive pad between the heat sink and the device. This will increase
the thermal transfer between the two parts, however, excessive quantities of heat sink grease will decrease performance.
Mount fins in the vertical plane for optimum natural convective cooling.
Do not overcrowd or obstruct devices that use heat sinks.
Do not block air flow around heat sinks – particularly directly above and below items that rely on natural convection.
If thermal demands are particularly high, consider using forced convection (i.e., a small fan directed at the heat sink).
Some typical heat sinks are shown below. Figure 8.6.1 shows a heat sink and thermal data plot for use with a single TO-3 case
device.

Figure 8.6.1: Heat sink for TO-3. Reprinted courtesy of Aavid Thermalloy, Inc.
Figure 8.6.2 shows a heat sink designed for a pair of transistors using TO-220 cases. In this photo, the white insulating pads can be
seen between the transistors and heat sink.

Figure 8.6.2: Heat sink for dual TO-220. Reprinted courtesy of Aavid Thermalloy, Inc.

8.6.1: Thermal Resistance

In order to specify a particular heat sink for a given application, a more technical explanation is in order. What we are going to do
is create a thermal circuit equivalent. In this model, the concept of thermal resistance is used. Thermal resistance denotes how easy
it is to transfer heat energy from one mechanical part to another. The symbol for thermal resistance is θ , and the units are Celsius
degrees per watt. In this model, temperature is analogous to voltage, and thermal power dissipation is analogous to current. A
useful equation is,

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 ΔT
PD = (8.6.1)
θtotal

Where P is the power dissipated by the semiconductor device in watts, ΔT is the temperature differential, and θ
D total is the sum of
the thermal resistances. Basically, this is a thermal version of Ohm's law.
In order to construct our model, let's take a closer look at the power-device/heat-sink combination. This is shown in Figure 8.6.3.
The subscript j stands for junction, c is for case (of the transistor), s is for heat sink and a is for the ambient air. T is the j

semiconductor junction temperature and is created by the product of the transistor's current and voltage. This thermal source heats
the device case to T . The thermal resistance between the two entities is θ . The case, in turn, heats the heat sink via the
c jc

interconnection. This thermal resistance is θ , and the resulting temperature is T . Finally, the heat sink passes the thermal energy
cs s

to the surrounding air which is sitting at T . The thermal resistance of the heat sink to the air is θ . The equivalent thermal model
a sa

is shown in Figure 8.6.4. Although this “thermal circuit” does not have perfect correspondence with normal circuit analysis, it does
illustrate the main points.

Figure 8.6.3: Device and heat sink.

Figure 8.6.4: Equivalent thermal model of Figure 8.6.3.

In this model, ground represents a temperature of absolute zero. The circuit is sitting at an ambient temperature T , thus a voltage
a

source of T is connected to ground and the heat sink. The three thermal resistances are in series and are driven by a current source
a

that is set by the present power dissipation of the device. Note that if the power dissipation is high, the resulting “voltage drops”
across the thermal resistances are high. Voltage is analogous to temperature in this model, so this indicates that a high temperature
is created. Because there is a maximum limit to T , a higher power dissipation requires lower thermal resistances. As θ is set by
j jc

the device manufacturer, we have no control over that element. However, θ is a function of the case style and the insulation
cs

material used, so we do have some control (but not a lot) over that. On the other hand, as the person who specifies the heat sink, we
have a great deal of control over θ . Values for θ are given by heat sink manufacturers. A useful variation of Equation 8.6.1 is
sa sa

Tj − Ta
PD = (8.6.2)
θjc + θcs + θsa

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Normally, power dissipation, junction and ambient temperatures, θ and θ are known. The idea is to determine an appropriate
jc cs

heat sink. Both T and θ are given by the semiconductor device manufacturer. The ambient temperature, T , may be determined
j jc a

experimentally. Due to localized warming, it tends to be higher than the actual “room temperature”. Standard graphs, such as those
found in Figure 8.6.5, may be used to determine θ . Note the generally lower values of θ for the TO-3 case relative to the TO-
cs cs

220. This is one reason why TO-3 cases are used for higher power devices. This case also makes it easier for the manufacturer to
reduce θ .
jc

Figure 8.6.5: θCS for TO-3 and TO-220 Reprinted courtesy of Thermalloy, Inc.

Example 8.6.1

Determine the appropriate heat sink rating for a power device rated as follows: T = 175 C, TO-3 case style, θ = 1.5 C
j(max)
∘
jc

∘
/W. The device will be dissipating a maximum of 15 W in an ambient temperature of 40 C. Assume that the heat sink will be
∘

mounted with heat sink grease and a 0.002 mica insulator.

First, find θ
cs from the TO-3 “With Thermal Grease” graph in Figure 8.6.5. Curve 3 is used. The approximate value is 0.35 C
∘
/W.
Tj − Ta
PD =
θjc + θcs + θsa

θsa = T j − T aP D − θjc − θcs

∘ ∘
175 C − 40 C
∘ ∘
θsa = − 1.5 C /W − 0.35 C /W
15W

∘
θsa = 7.15 C /W

This is the maximum acceptable value for the heat sink's thermal resistance. Note that the use of heat sink grease gives us an
extra 0.8 C /W or so. For this application, the heat sink pictured in Figure 8.6.1 will most likely be sufficient without added
∘

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 forced air cooling (the graph stops at less than 4 C /W with an air flow of under 200 feet/minute).
∘

If we repeat this problem with a much higher P , things work out a little differently. Let's use 40 W this time.
D

Tj − Ta
PD =
θjc + θcs + θsa

Tj − Ta
θsa = − θjc − θcs
PD

∘ ∘
175 C − 40 C
∘ ∘
θsa = − 1.5 C /W − 0.35 C /W
40W

∘
θsa = 1.53 C /W

If we hope to use that same heat sink, we will have to add forced air cooling of at least 700 feet/minute. The other option
would be to find a more thermally efficient (and probably much larger) heat sink if we hope to use natural convection alone.

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8.7: Summary
Class A operation is defined as having collector current flow for 360 of the cycle. This means that a single output device can be
∘

used to amplify the entire input waveform. To determine the maximum signal swing, or compliance, an AC load line is used. This
is similar to a DC load line and plots all possible transistor voltage and current coordinate pairs. The efficiency of the class A
amplifier tends to be low. The maximum theoretical efficiency is only 25%. Further, the amplifier draws full current from the
power supply regardless of whether or not a signal is present. As a consequence, the transistor runs hottest when there is no signal.
With an applied signal, some of the power formerly dissipated within the transistor is shifted to the load.
Loudspeakers offer a complex impedance as a load. As such, they are more challenging than simple resistive loads and may require
the output transistor to be rated for a higher-than-normal power dissipation.
Heat sinks are used to efficiently move heat from the transistor's internal structure to the surrounding air. The thermal effectiveness
of a heat sink is measured by thermal resistance, θ . The lower the value of θ , the more effective the heat sink is at transferring heat
from the transistor to the surrounding air. For high power applications where a good deal of heat is generated, heat sinks are
augmented with forced air cooling.

8.7.1: Review Questions

1. Define class A operation.
2. Why are voltage followers generally preferred over voltage amplifiers for power output applications?
3. How does an AC load line differ from a DC load line?
4. What is the advantage of having a centered Q point on the AC load line?
5. What effect does a reactive load have on an AC load line?
6. Describe the operation of a dynamic loudspeaker.
7. What are heat sinks? What are they used?
8. What is thermal resistance?

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8.8: Exercises
8.8.1: Analysis Problems
1. Draw the AC load line for the circuit of Figure 8.8.1. Also determine the compliance, maximum load power, maximum
transistor dissipation and efficiency. V
CC = 6 V, V = −12 V, R = 50 Ω, R = 2.2 kΩ, R = 470 Ω, R = 75 Ω.
EE gen B E L

Figure 8.8.1
2. Recalculate Problem 1 if the load is halved.
3. Determine if the circuit of Figure 8.8.2 has a centered Q point on its AC load line. V
CC = −10 V, V
EE = 15 V, R = 1 kΩ, R =
B E

330 Ω, R = 50 Ω.
L

Figure 8.8.2
4. Draw the AC load line for the circuit of Figure 8.8.2. Also determine the compliance, maximum load power, maximum
transistor dissipation and efficiency. V
CC = −8 V, V = 12 V, R = 1 kΩ, R = 330 Ω, R = 32 Ω.
EE B E L

5. Draw the AC load line for the circuit of Figure 8.8.3. Also determine the compliance, maximum load power, maximum
transistor dissipation and efficiency. V
CC = 15 V, V = −20 V, R = 10 kΩ, R = 100 Ω, R = 16 Ω.
EE B E L

Figure 8.8.3
6. Determine if the circuit of Figure 8.8.4 has a centered Q point on its AC load line. V CC = 30 V, R = 3.9 kΩ, R = 3.3 kΩ,
1 2 RE

= 560 Ω, R = 50 Ω.
L

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 Figure 8.8.4
7. Draw the AC load line for the circuit of Figure 8.8.4. Also determine the compliance, maximum load power, maximum
transistor dissipation and efficiency. V = 30 V, R = 2.2 kΩ, R = 2.2 kΩ, R = 470 Ω, R = 32 Ω.
CC 1 2 E L

8. Determine if the circuit of Figure 8.8.5 has a centered Q point on its AC load line. V CC = 15 V, V EE = −15 V, R = 1 kΩ, R =
B E

510 Ω, R SW = 10 Ω, R = 270 Ω, R = 50 Ω.
C L

Figure 8.8.5
9. Draw the AC load line for the circuit of Figure 8.8.5. Also determine the compliance, maximum load power, maximum
transistor dissipation and efficiency. V = 25 V, V
CC = −15 V, R = 1 kΩ, R = 270 Ω, R
EE B E = 6.8 Ω, R = 330 Ω, R = 16 Ω.
SW C L

10. A power transistor has a P D(max)

of 50 watts at 25 C. It has a derating factor of 0.4 W/C . Will this transistor be sufficient for
∘ ∘

a circuit that needs to dissipate 40 watts at 85 C?

∘

11. A power transistor has a P D(max)

of 100 watts at 25 C. It has a derating factor of 0.6 W/C . Will this transistor be sufficient for
∘ ∘

a circuit that needs to dissipate 65 watts at 75 C?

∘

12. Determine the appropriate heat sink rating for a power device rated as follows: T = 175 C, TO-3 case style, θ = 1.5 C
j(max)
∘
jc

∘
/W. The device will be dissipating a maximum of 25 W in an ambient temperature of 35 C. Assume that the heat sink will be
∘

mounted with heat sink grease and a 0.003 mica insulator.

13. Determine the appropriate heat sink rating for a power device rated as follows: T = 165 C, TO-220 case style, θ = 3 C
j(max)
∘
jc

∘
/W. The device will be dissipating a maximum of 15 W in an ambient temperature of 35 C. Assume that the heat sink will be
∘

mounted with heat sink grease and a 0.002 mica insulator.

8.8.2: Design Problems

14. Alter the emitter power supply in the circuit described in Problem 1 to achieve a centered Q point.
15. Alter the emitter power supply in the circuit described in Problem 4 to achieve a centered Q point.

8.8.3: Challenge Problems

16. Find a heat sink (make and model number) that will meet the thermal resistance requirement for Problem 12 with no more than
400 feet/minute of forced air.
17. Alter the voltage divider in the circuit described in Problem 6 to achieve a centered Q point.

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8.8.3: Computer Simulation Problems
18. Perform a transient analysis for the circuit described in Problem 1 to verify the compliance.
19. Perform a transient analysis for the circuit described in Problem 4 to verify the compliance.
20. Perform a transient analysis for the circuit described in Problem 9 to verify the compliance.

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 CHAPTER OVERVIEW

9: BJT Class B Power Amplifiers

Learning Objectives
After completing this chapter, you should be able to:
Define class B operation.
Determine AC load lines for class B amplifier stages.
Determine the compliance, maximum load power, efficiency and required device ratings for class B circuits.
Discuss the advantages and disadvantages of class B operation versus class A operation.
Discuss the origin of notch distortion and methods used to mitigate it.
Explain the operation of a current mirror.
Explain the operation of a Sziklai pair.
Explain the operation and use of a V multiplier.
BE

Outline the operation of fully complimentary and quasi complimentary output stages utilizing direct coupled driver stages.
Discuss methods to protect the output devices from overload.

9.1: Introduction
9.2: The Class B Configuration
9.3: Extensions and Refinements
9.4: Summary
9.5: Exercises

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1
9.1: Introduction
Class B amplifiers have long been a mainstay of linear amplifier design. Compared to class A operation, class B amplifiers offer
much greater power efficiency. That is, a much larger percentage of the applied DC power can be turned into useful AC output to
the load. This also means that the power dissipation requirements for the transistors are lowered. Further, unlike class A operation,
class B designs do not continuously draw full power from their DC supplies. Instead, they draw current as it is needed, and
therefore run relatively cool at idle and at low output power.
The downside for this improved efficiency is added complexity. For starters, two transistors are required for linear class B
operation. Also, the biasing can be a little trickier which requires modifications to the relatively straightforward class A biasing
circuits we have already examined. Also, class B amplifiers suffer from a unique form of distortion that class A amplifiers do not.
In this chapter we shall also examine the use auxiliary device configurations and sub-circuits to improve performance. These
include the current mirror, Sziklai pair, V BEmultiplier, and overload protection and prevention circuitry. As with the class A
amplifier, the common collector or voltage follower configuration tends to be the most widely used configuration for class B
circuits, hence, we shall focus on followers and not on voltage amplifiers.

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9.2: The Class B Configuration
Class B operation is defined as having AC collector current flow 180 out of the cycle. Consequently, in order to amplify the entire
∘

signal, two devices will be needed. Further, we will need to pay attention to how the two waveform halves are “stitched together”
as this could be a problem area. The obvious question at this point is, why do we bother separating the positive and negative half-
waves if it leads to circuit complexity and possible waveform issues? The answer is improved efficiency.
In the previous chapter we discovered that class A amplifiers are not efficient. In fact, at best they only transform 25% of the DC
input power into useful load power. Why does this occur and how does the class B topology address this situation?
The basic idea of class B is to push the Q point down so that it is sitting right at cutoff on the AC load line. This means that I isCQ

0 A and virtually no power is drawn from the supply at idle. Locating the Q point at cutoff also means that the transistor will
immediately clip the negative portion of the wave. Consequently, we will need a mirror image circuit to produce that portion (and
which will clip the positive portion).

Figure 9.2.1: Voltage follower simplified AC circuit.

To gain a better understanding of how class B operation works, consider the simplified AC circuit of a voltage follower shown in
Figure 9.2.1. If we situate the Q point directly at v then the associated I is 0 A. As the input signal swings positive, the
C E(cutof f ) CQ

collector current increases. As it does so, the voltage across the load (r ) begins to increase and the voltage across the transistor's
E

collector-emitter begins to decrease (due to KVL). When the input signal swings negative, the transistor is turned off. As a result,
no collector current is created, no voltage is developed across the load and v CE stays at cutoff. It is as if the input waveform has
been half-wave rectified. This action is shown in Figure 9.2.2. As the input signal swings positive, the operating point slides up the
load line, moving toward saturation, and this increased current creates a load voltage that follows the input signal. In contrast, when
the input tries to swing negative, there is no place else to go on the load line and the negative portion of the wave is simply clipped.

Figure 9.2.2: AC load line for class B operation.

If we made a PNP version of the circuit depicted in Figure 9.2.1, the exact opposite would happen: the amplifier would reproduce
the negative portion of the wave and clip the positive portion. The next question is, how do we bias the transistor at cutoff and
splice together the NPN and PNP versions into a workable whole?
Let's begin by making two bare-bones emitter followers, one NPN and the other PNP. We'll connect their emitters together and tie
that to the load. We'll connect the NPN's collector directly to a DC supply and the PNP's collector to ground. Remember, collector
resistors will not be needed because these are followers. We will include no biasing components on the base because we want to set

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IC Qto 0 A. We will also have to add input and output capacitors to prevent the source and load from inadvertently shorting out or
shunting portions of the DC circuit. The result is seen in Figure 9.2.3.

Figure 9.2.3: Prototype Class B circuit.

With no signal supplied, both transistors must be off. This is because their bases are tied together, and without some other applied
potential, both base-emitter voltages must be zero. Assuming Q and Q are matched, the power supply voltage should split evenly
1 2

between them, leaving half of V CC at the emitters. This potential also appears across C , preventing the DC voltage from
out

reaching R .
L

When the input signal goes positive, it raises V and V above 0.5 V . This keeps Q off but turns on Q . Current is now free
B1 B2 CC 2 1

to flow down through Q and into the load. When the input signal swings negative, the inverse happens: Q is turned off and Q is
1 1 2

turned on. This allows current to flow up from the load and down through Q (if this is confusing, remember that a DC voltage had
2

already been established across C that is equal to 0.5 V

out and this is what allows the current to flow from ground up through
CC

RL and then down through Q as Q begins to conduct). You can think of Q pushing current into the load (sourcing) and Q
2 2 1 2

pulling current from the load (sinking). Consequently, class B amplifiers are sometimes called a push-pull amplifiers.

Figure 9.2.4: Prototype Class B circuit in simulator.

To see how well this prototype works, we'll enter a version into a simulator, as shown in Figure 9.2.4 . A transient analysis is
performed with the results shown in Figure 9.2.5.

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 Figure 9.2.5: Transient analysis of prototype Class B circuit.
Clearly, there are issues with the output waveform (node 2, in blue). First off, the signal amplitude is noticeably smaller than the 2
volt peak input signal. The second issue is the bizarre “flat spotting” of the output waveform near the zero-crossing points. It turns
out that these two problems are manifestations of the same root cause. If we look carefully at the peaks, we can get a clue as to
what is going on. The peak output voltage is about 0.75 volts below the input, or just about one PN junction forward potential. The
problem is that the input signal will not truly turn on the NPN transistor until the signal exceeds approximately 0.7 volts or drops
below −0.7 volts for the PNP side. That region between −0.7 volts and +0.7 volts is a dead zone that the amplifier will not respond
to. Essentially, the amplifier “rips out” anything between ±0.7 volts. This is a gross form of distortion and goes by many names
including notch distortion and cross-over distortion. The particularly nasty part about this form of distortion is that it hits small
signals worse than large signals. Most other forms of nonlinearities tend to get worse as the signal level increases.

9.2.1: Class AB Operation

The basic solution to this problem is to provide a small idle current so that the transistors are almost on. In this way, only a very
small input signal will be needed to turn on the devices. As this would slightly increase the conduction angle, this form of operation
is referred to as class AB operation. One potential solution is to add a voltage divider as depicted in Figure 9.2.6.

Figure 9.2.6: Prototype Class AB circuit.

This circuit uses a symmetrical layout: everything above a horizontal line drawn through the middle is echoed by a component
below the line. In other words, R = R , R = R , C = C , and Q and Q are a complimentary pair. The divider is configured
1 2 3 4 1 2 1 2

so that the voltage drops across R and R are about 0.7 volts each.
3 4

Properly designed, the circuit of Figure 9.2.6 will reduce notch distortion. Unfortunately, it has other problems. The first issue
involves the three capacitors. COUT in particular might be quite large. These can be removed if we went to a symmetrical bipolar
power supply. Instead of running the PNP's collector to ground, we'll tie it to a negative DC supply. To keep the same total voltage,
we'll set Q 's collector to half of the original V
1 and Q 's collector to half of the original V
CC 2 CCbut negative. On the input side, we
could run the input signal to the junction of R and R .
3 4

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The second issue plaguing the circuit of Figure 9.2.6 is the stability of the bias. The voltage divider resistors have to be very
accurate in order to set the transistors right where we want them and stability is a concern. The problem is that we are trying to use
a device with a linear current-voltage characteristic (a resistor) to match the exponential current-voltage characteristic of a PN
junction. This problem is exacerbated by the fact that these devices will drift with temperature, and drift in different ways. The
solution to this problem is to use a device with better matching characteristics. What better device to match a PN junction than
another PN junction?

9.2.2: The Current Mirror

Figure 9.2.7: A simple current mirror.

Consider the circuit shown in Figure 9.2.7. This is called a current mirror. Here is how it works: First, look at the divider between
R and D. The voltage across R must equal the supply voltage minus the diode drop, or approximately V − 0.7 . This sets up a

current, I . If the base current is small enough to ignore, this same current flows down through the diode as I . This diode current
R D

sets up a specific voltage across the diode (somewhere in the vicinity of 0.7 volts although the exact voltage is not important).
Because the diode is in parallel with the base-emitter junction, then V = V . If the transconductance curve (I-V curve) of the
BE D

transistor is identical to that of the diode, then the emitter current must be the same as the diode current. Any change in the diode
current would cause a slight change in diode voltage, and since diode voltage and base-emitter voltage are the same, then the
emitter current must change in response. In other words, the emitter current mirrors the diode current. We can program the diode
current (and hence, the emitter current) by setting an appropriate value for R . Whatever the current through R is, that's also the
collector current.
The idea of the current mirror is used with great effect in integrated circuits where it is easy to match device characteristics. When
it comes to discrete components, it is not nearly so easy to match a diode to a transistor. Fortunately, we don't have to have a perfect
match. Simply using any signal diode will provide a much better match for V BE than using a resistor. Although the diode current
won't match the collector current precisely, the bias will be more stable and the components will track much better than when using
a resistor.
Combining these ideas leads us to the circuit of Figure 9.2.8 . This is our first practical class B amplifier with the potential for
decent values of distortion and stability.

Figure 9.2.8: Class B amplifier with diode bias and bipolar supplies.
One thing that sometimes bothers people when they first see a diode biased amplifier is how the AC signal will pass through the
diodes to the bases. At first glance, it appears that the positive portion of the input signal would be “going the wrong way” against
diode D . What we need to remember is that D is already forward-biased due to the DC supply and surrounding resistors. The
1 1

signal won't see an open, it will see the dynamic resistance of the diode.2

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9.2.3: Class B Circuit Maximums
Now that we have a workable circuit, we need to derive formulas for the endpoints of the AC load line, meaning v and
C E(cutof f )

i , and determine the compliance. The first item of note is cutoff. Because the two transistors will split the available supply,
C (sat)

VC EQwill always equal half of the total supply. Further, we have biased these devices at cutoff, and therefore
vC E(cutof f ) = VC EQ = 0.5 ⋅ Total DC Supply (9.2.1)

In the case of a bipolar supply, that's the same as one of the two sides. Because the class B uses two transistors, peak compliance
will be the same as cutoff.
C omplianc epeak = VC EQ = 0.5 ⋅ Total DC Supply (9.2.2)

The maximum voltage rating of the transistors will occur when they are off. In that instance, if the opposite transistor is fully
conducting it will have a negligible voltage across its collector-emitter. Consequently, the off-state transistor can see the entire
power supply.
BVC EO = Total DC Supply (9.2.3)

The saturation current is dictated by the compliance and the load. The only thing that limits AC current is the load. Therefore
C ompliancepeak
iC (sat) = (9.2.4)
rL

Based on that, we can say

2
C omplianceRMS
Pload(max) = (9.2.5)
rL

Before we go any further, there is an important item to note about the circuit of Figure 9.2.8 (and the variants we shall discuss). If
you take another look at the circuit you will see that there is nothing in the collector-emitter line to limit DC current. In fact, if we
were to plot the DC load alongside the AC load, we'd get something like Figure 9.2.9.

Figure 9.2.9: Comparison of AC and DC load lines for class B operation

The DC load line goes straight up. There is no saturation current value short of infinity. What this really means is that if we're not
careful with the bias, it is possible to destroy the transistors. The same is true if we accidentally short the load. A quick examination
of Equations 9.2.4 and 9.2.5 shows that a shorted load condition would lead to huge currents and powers, and destroy the
transistors in the process. With an audio amplifier, this could happen if one of the strands of loudspeaker wire unraveled and
touched the adjacent lead. Obviously, not a happy situation unless you prefer the smell of burnt silicon over the sound of music. We
will examine means of protecting the transistors from accidental overloads later in the chapter.

9.2.4: Class B Power Dissipation

Transistor power dissipation for the class B configuration is a bit trickier than it was for the class A. The idle (Q point) power
dissipation is very low. It is found by multiplying I by V
CQ .IC EQ is generally set at a few percent of i
CQ so it's obviously
C (sat)

way below the maximum load power. Unlike the class A design, P does not represent the worst case for class B.
DQ

To determine the worst case transistor power dissipation, we begin by describing the current and voltage waveforms during the
conduction phase of the NPN. The collector current will appear as the positive half of a sine wave. The maximum case has the

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current starting at zero and peaking at i
C (sat) (or alternately, V C EQ / rL ). For v CE , it starts at V C EQ and then swings down to zero as
a negative half sine.
Nothing says that the maximum load power case must cause the maximum transistor dissipation. In fact, we saw this wasn't the
case for class A. Consequently, we will introduce a coefficient, k , that represents the percentage of the maximum current. We now
arrive at our general equations for transistor current and voltage for the first half cycle.
VC EQ
iC = k sin 2πf t (9.2.6)
rL

vC E = VC EQ (1 − k sin 2πf t) (9.2.7)

Where 0 ≤ k ≤ 1
For convenience, we'll set 2πf to 1. To get the power dissipation, we find the product of the transistor's current and voltage.

PD = iC vC E

VC EQ
PD = k sin t × VC EQ (1 − k sin t)
rL

2 2
VC EQ VC EQ
2 2
PD = k sin t − k sin t
rL rL

2
VC EQ
2 2
PD = (k sin t − k sin t)
rL

Remove ugly sin term...

2

2 2 2
VC EQ k k
PD = (k sin t + cos 2t − )
rL 2 2

..and integrate to get:

2 2 2
VC EQ k k t π
PD = (−k cos t − sin 2t − )|
0
rL 4 2

2
V
Note that C EQ
= 2P
rL
This is a constant, so replace it to simplify and then evaluate the expression. Finally, divide by 2π to
load(max)

find the average over one full cycle.

2 2
k π k t
2 Pload(max) (2k − − )
2 2

PD = (9.2.8)
2π
2
k k
PD = 2 Pload(max) ( − )
π 4

Equation 9.2.8 is the general case. For the worst case, we need the min/max k value. We will take the derivative of Equation 9.2.8
and then set it to zero to find the worst case value of k .
2
k k
PD = 2 Pload(max) ( − )
π 4

dPD 1 k
= 2 Pload(max) ( − )
dk π 2

Worst case occurs at k = 2/π . This means that only 2/π, or 63.7%, of the load line is used at maximal heating of the transistor.
63.7% of the load line corresponds to a load power of about 40% of P (i.e., 0.637 ). We now substitute this value back
load(max)
2

into Equation 9.2.8 to find the worst case P .D

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 2
2/π (2/π)
PD = 2 Pload(max) ( − ) (9.2.9)
π 4

2 Pload(max)
PD = Pload(max) ≈
2
π 5

The end result is that when the load is receiving about 40% of its maximum power, the transistors will be at their hottest and will be
dissipating approximately 20% of the maximum load power (or about half of the power delivered to the load at that point). Thus, if
a class B amplifier is rated to produce a maximum load power of 100 watts, the transistors will get their hottest when the load is
receiving 40 watts, and each transistor will be dissipating 20 watts. The transistors will be dissipating less power when the load is
at maximum. This is easily verified by substituting k = 1 into Equation 9.2.8. The result is a power dissipation of 13.7% of
maximum load power, or 13.7 watts for the preceding example.
To help gain a deeper understanding of precisely what's happening here, the transistor waveforms are plotted in Figures 9.2.10 and
9.2.11. The maximum load power case is presented in Figure 9.2.10. Here, we see the full i and v swings. Note that when i
C CE C

is maximum, v is 0, hence the power is 0. In contrast, Figure 9.2.11 shows the worst case. Collector current peaks at just under
CE

64% of maximum but v drops to only about 36% rather than 0% of its maximum. This results in a power dissipation curve with
CE

considerably greater area underneath it, indicating a higher average power.

Figure 9.2.10: Class B transistor power dissipation at P Load(max)

.

Figure 9.2.11: Class B transistor power dissipation, worst case.

Finally, it is worth remembering that the reactive load issues discussed for class A amplifiers still apply to class B amplifiers. Loads
with a complex impedance may be harder to drive than the ideal purely resistive loads examined here. Therefore, we may have to
over-rate the transistors above Pload(max) /5. As a side note, the AC load line for a class B amplifier with a reactive load will appear

as an ellipse that has been cut in half (refer back to Figure 8.4.5 and imagine a horizontal cut line running through the Q point).

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9.2.5: Class B Efficiency
Efficiency is defined as useful output or load power versus supplied DC power.

Pout Pload(max)
η = =
Pin PDC

This is dynamic for class B amplifiers. At P load(max) the DC supply is delivering the full voltage of 2V
C EQ and the corresponding
peak value of the current is i .
C (sat)

VC EQ
iC (sat) =
rL

The average of this over a half-cycle is

1 VC EQ
iC (avg) = ×
π rL

Therefore, the supplied power must be

PDC = 2 VC EQ iC (sat)

1 VC EQ
PDC = 2 VC EQ ×
π rL

2
2 VC EQ
PDC = ×
π rL

As noted previously V CEQ 2 r L = 2 Pload (max) therefore

4
PDC = × Pload(max)
π

Finally, substitute this expression back into the original definition for efficiency.
\[\eta_{max} = \frac{P_{load (max)}{{P_{DC}} \nonumber \]
Pload(max)
ηmax =
4
Pload(max)
π

π
ηmax =
4

ηmax ≈ 78.5%

We find that the maximum theoretical efficiency of a class B amplifier is over three times that of a class A amplifier.
Time for an example.

Example 9.2.1

The amplifier shown in Figure 9.2.12 is driving a nominal 8 Ω loudspeaker. Determine the compliance, maximum load power
and worst case transistor dissipation. Also estimate Z assuming β = 50 and determine the transistor ratings for maximum
in

current and BV .
C EO

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 Figure 9.2.12: Schematic for Example 9.2.1.
By inspection, V C EQ = 15 V. This is the peak compliance.

compliance = 15V peak = 10.6V RM S

Given the compliance, we can use power law to find the load power
2
C omplianceRMS
Pload(max) =
RL

2
(0.707 × 15V )
Pload(max) =
8Ω

Pload(max) = 14W

That's not huge but it might be enough to irritate the neighbors.

The transistors' worst case power dissipation is
Pload(max)
PD =
5

14W
PD =
5

PD = 2.8W

The breakdown voltage is the entire supply so BV C EO > 30 V. The maximum current through the transistors is the same as the
maximum load current or i . C (sat)

VC EQ
iC (sat) =
rL

15V
iC (sat) =
8Ω

iC (sat) = 1.88A

The input impedance is found in the usual manner but with a minor twist. Z is approximately equal to βr , or about 400
in(base) L

Ω . Only one transistor is on at any given time, though, so this is in parallel with the two 200 Ω biasing resistors but not the

other Z in(base)
(the “off” transistor has a very high input impedance because it is not conducting). This leaves a Z of
in(base)

about 80 Ω, or ten times the load impedance.

Computer Simulation
To verify the basic operation of a class B amplifier, the circuit of Figure 9.2.13 is entered into a simulator. The amplifier should
clip just below the ±10 volt power rails so a 10 volt peak source is used to verify this. Also, A should be about 1.
v

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 Figure 9.2.13: Class B amplifier in simulator.
The results of a transient analysis are shown in Figure 9.2.14. First, it is apparent that the voltage gain is approximately unity as the
input and output waves are nearly coincident (with the exception of the clipped portion). Clipping occurs at about 8.5 volts. This is
largely due to limiting from the biasing diodes. Once the input gets close in value to the power supply, the diodes become reverse-
biased and the signal does not make it to the base. Thus, the output clips prematurely.

Figure 9.2.14: Class B amplifier transient analysis.

To verify earlier commentary regarding the biasing diodes, the circuit is modified so that the diodes are shorted out and the
transient analysis is run again. The results are shown in Figure 9.2.15.
Two things should be apparent in the new simulation. First, the output waveform is suffering from obvious notch distortion.
Therefore, we can be pleased that the biasing diodes have done their job to reduce this effect. The second item involves the
compliance. The new output is not clipped. Granted, the lack of biasing diodes has reduced the signal by about 0.7 volts, but a
careful examination of the output waveform shows that it has reached over 9 volts peak without clipping. In fact, if we increase the
input to 12 volts peak, as in Figure 9.2.16, we can see that clipping occurs just under the power rails. Thus, the premature clipping
is due to the diodes and their interaction with the power supplies and surrounding resistors. In short, we lose a little bit of
compliance due to the diodes but that's much better than getting notch distortion.

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 Figure 9.2.15: Class B amplifier transient analysis, without biasing diodes.

Figure 9.2.16: Class B amplifier transient analysis, without biasing diodes and showing clipping.

9.2.6: Direct Coupled Driver

The circuits we have examined offer both current gain and power gain but not voltage gain. In order to increase the signal voltage,
some preceding voltage gain stages will most likely be needed. These stages can be connected to the previous class B follower
circuits with coupling capacitors but this is not the most effective method. A more common technique is the use of a direct coupled
driver.

Figure 9.2.17: Class B amplifier with direct coupled driver.

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A class B follower with a direct coupled driver stage is shown in Figure 9.2.17. What we've done here is combined an ordinary
class A common emitter amplifier (in this case, using voltage divider bias) with a class B follower. The follower is positioned
where the common emitter stage's collector resistor would be normally. This eliminates three components: the collector resistor, the
interstage coupling capacitor, and the lower base biasing resistor of the class B output stage. The removal of the resistors raises the
effective load resistance for the first stage, thus producing a higher voltage gain from the driver stage.
Biasing the direct coupled driver is not difficult if we remember one thing: the DC voltage across R must be equal to 3

approximately V − 0.7 V. If this is not the case, the class B stage will not be symmetrical, or in other words, V
CC ≠V , C EQ2 C EQ3

and the final output will not be sitting at 0 VDC as it needs to. Knowing the value of R and its voltage, we can determine its
3

current. This current flows down into Q as I 1 . Knowing I

C Q1 , we can determine the voltage across R and eventually
C Q1 4

determine the appropriate divider ratio for R and R to achieve this value.
1 2

Example 9.2.2

Using the two-stage amplifier of Figure 9.2.17, first determine values for R and R to obtain proper system bias. Determine
1 2

the output compliance, maximum load power and worst case transistor dissipation. Also estimate A . Assume β = 50 for the v

output devices and 100 for the first stage. V = 20 V, V = −20 V, R = 16 Ω, R = 560 Ω, R = 75 Ω.
CC EE L 3 4

For the output section (assuming it will be biased properly), by inspection, V C EQ = 20 V. This is the peak compliance.

compliance = 20V peak = 14.1V RM S

Given the compliance, we can use power law to find the load power
2
C omplianceRMS
Pload(max) =
RL

2
(14.1V )
Pload(max) =
16Ω

Pload(max) = 12.5W

The transistors' worst case power dissipation is

\[P_D = \frac{P_{load (max)}{5} \nonumber \]
12.5W
PD =
5

PD = 2.5W

To determine the biasing resistors, we start with R . To achieve bias symmetry, all of V
3 CC drops across R with the exception
3

of 0.7 volts for D . This is the same as I

1 .
C Q1

VC C − 0.7V
IC Q =
1
R3

19.3V
IC Q =
1
560Ω

IC Q = 34.5mA
1

The drop across R4 is found via Ohm's law

VR4 = IC Q R4
1

VR4 = 34.5mA × 75Ω

VR4 = 2.6V

This implies that the voltage across R must be 0.7 volts more, or 3.3 volts. If we ignore the base current of Q , then the ratio
2 1

of R to R must be the same as the ratio of their voltages, 36.7 to 3.3, or 11.1 to 1. In other words, R must be 11.1 times
1 2 1

larger than R . For good bias stability we don't wish to set R too much larger than R . If we set it to 200 Ω, for example, then
2 2 4

R 1 would need to be about 2.2 k Ω. Due to component tolerances, one of these resistors would need to be a potentiometer

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 (connected as a rheostat) in order to “tweak” the final output to 0 VDC. A resistor/pot combo might be even better as it won't
be so “touchy”. For example, the 2.2 k Ω could be replaced with a series combination of a 1.8 k Ω and a 1 k Ω pot. This would
be much easier to adjust than if the resistor was replaced with a standard 5 k Ω pot.
Now for the system voltage gain. The gain of the follower is approximately one so we need only concern ourselves with the
first stage common emitter amplifier. This amplifier is swamped by R and given that the collector current is over 34 mA, r
4
′
e

will be less than an ohm and can be ignored. All we need to do is find the effective load at the collector of Q . This is R in
1 3

parallel with a single Z (remember that only one transistor is on at any given time and the off transistor will appear as a
in(base)

high impedance).

Zin(base) = β rE

Zin(base) = 100 × 75Ω

Zin(base) = 7500Ω

rL
Av = −
rE

7500Ω||560Ω
Av = −
75Ω

Av = −6.95

Before leaving this section, there are a few items to note. First, the load power calculations have assumed that the entire power
supply can be used by the output devices. As we saw with the diode bias version, this is not always the case. There is another
situation that can limit the output swing. The class B stage is a follower and thus has a voltage gain of one. It the driver stage can't
produce the full swing then the output stage can't either. Consequently, a class A analysis (i.e., AC load line) needs to be performed
on the driver in order to determine just how large the signal can be before clipping. Indeed, it's quite likely that the driver stage will
clip before the output stage.
Also, the direct coupled driver does not have to be an NPN as depicted in Figure 9.2.17. A PNP can be used instead, it simply
needs to be shifted to the upper section rather than the lower section, as shown in Figure 9.2.18.

Figure 9.2.18: Class B amplifier with direct coupled driver, PNP version.

References
1
Think of a car engine: How much sense would it make to have an engine with a 6000 RPM maximum run at 3000 RPM when
you're sitting motionless at a red light?
2Of course, the dynamic resistance is a function of the current flowing through the diode so it will fluctuate as the signal changes.
This is best thought of as a distortion generating mechanism because it will slightly alter the signal that reaches the base. This
distortion is most likely orders of magnitude smaller than the notch distortion the diode mitigates, so it's a good trade.

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This page titled 9.2: The Class B Configuration is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James
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9.3: Extensions and Refinements
The foregoing discussion has covered the basics of class B amplifier design and operation but there are a variety of things we might
add.

9.3.1: Current Limiting

One of the more useful additions to an amplifier is some form of protection circuit. As noted earlier, there is nothing in the basic
class B amplifier to limit current, so if the load is accidentally shorted, the transistor current will spike to very high levels and
possibly damage the output transistors. How might we prevent this from happening?
Perhaps the most basic protection technique is to place a fuse in-line with the load. This is a somewhat tricky proposition because
voice and music waveforms are very dynamic. Fuses are not fast response devices and selection of the proper current rating is a
trade-off. If we want to catch large, fast transients, the fuse will have to be rated on the low side. Unfortunately, the fuse might then
blow on moderately loud sustained low frequency content. Relays suffer from similar problems. Also, there is the issue that if the
fuses are replaceable by the consumer, they may use the wrong value or some other item1 that will allow too much current,
resulting in blown output transistors. This can be avoided by having a second set of fuses mounted on the PC board, connected to
the power rails, but this is also an imperfect solution.
One means of dealing with this situation is to employ an active current limiter, such as the circuit shown in Figure 9.3.1. In this
circuit, Q is the main NPN output transistor, the PNP side not shown. At the top is the power supply connection and the load is
1

connected off to the right. A small resistor, R , is inserted into the emitter current path. The resistance is small enough that the
E

voltage across it is normally less than 0.5 volts or so. Across the resistor is another transistor, Q . Under normal operation Q is
2 2

not on and does not affect the circuit. If the load current gets large enough (beyond the safe limit), the voltage drop across R willE

reach 0.7 V. At this point Q turns on and begins to conduct current away from the base of Q , limiting the amount of load current
2 1

to approximately 0.7V /R . Unlike a fuse, once the fault is removed and the load current falls to safe levels, Q disengages and
E 2

normal amplifier function resumes.

Figure 9.3.1: Active current limiter.

Two of these circuits are required for the amplifier; one for the positive half and one for the negative half. Figure 9.3.2 shows a
class B amplifier with the added current protection circuits (within the dashed red box).

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 Figure 9.3.2: Class B amplifier with current limiters

9.3.2: High Current Gain Configurations

For some applications the β of typical power transistors may prove to be insufficient. In such cases we can use high current gain
configurations. There are several ways to configure the output devices. A Darlington scheme is shown in Figure 9.3.3. Q and Q 3 5

are the main output devices. Q and Q can be thought of as drive transistors. Although their BV
2 4 rating will need to be as high
C EO

as that of Q /Q , they will be handling less current and therefore will dissipate less power. Sometimes Q /Q are configured as
3 5 2 4

seen here and sometimes emitter resistors may be added so that the output appears to be a cascade of emitter followers. Either way,
there are now four base-emitter junctions to be compensated for, thus the addition of D and D .
3 4

Figure 9.3.3: Darlington output devices for high current gain.

Figure 9.3.4: Sziklai pair, AKA composite PNP.

Some years ago, high power PNP transistors exhibiting decent audio quality were not available. Instead of using a PNP Darlington
configuration, a Sziklai pair was used. This dual transistor configuration is named after Hungarian, and later, American, engineer
George Sziklai. The Sziklai pair is also known as a composite pair. A composite PNP is shown in Figure 9.3.4. The operation is
similar to that of a Darlington pair. The input transistor, Q , drives its collector current into the base of Q , the output transistor.
1 2

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Q2 's base current is multiplied by its β, thus its collector current is the product of I , β and β , just like a Darlington. The
B1 1 2

differences are that the main power device for the composite PNP is an NPN, and that there is only a single V to compensate for.
BE

An example amplifier based on the earlier direct coupled driver circuit is shown in Figure 9.3.5. This configuration is known as a
quasi-complementary output2. Note the use of three compensating diodes; two for the Darlington NPN and one for the composite
PNP/Sziklai pair. One advantage here is that the power devices, Q and Q , can be identical models.
3 5

Figure 9.3.5: Quasi-complementary output.

The current limiting circuit of Figure 9.3.1 can be added to both the Darlington and quasi-complementary output stages. Current
limiting can also be added to the circuits presented in the next section, but have been left off for clarity.

9.3.3: Current Sharing

For higher output powers, and especially for amplifiers driving very low load impedances such 1 or 2 ohms, it may not be possible
to use a single NPN and PNP for the output stage. Instead, the duties of each device will be shared among two or three transistors
operating in parallel. Generally, current-sharing schemes will also require a Darlington-based approach due to the very high total
load current.
Initially, it may be tempting to just place two or three transistors in parallel, each base terminal being fed by a common drive
transistor. There is a fatal flaw with this approach. The issue is referred to as either thermal runaway or current hogging. The basic
problem is that the temperature coefficient of transconductance for a bipolar transistor is positive. In other words, r gets smaller as
′
e

temperature rises. This means that, as the device heats up, it tends to more easily conduct current. Of course, if the device draws
more current, it will dissipate more power, which means that it will get hotter, which means that it will conduct more current, which
means that it will dissipate more power, and so on. This process spirals out of control and is particularly evil when we have
multiple devices in parallel. Devices are never perfectly matched so the load current will never be perfectly shared among the
devices. This means that one device will tend to get hotter than the other(s) which leads to it getting even hotter and grabbing a
larger and larger share of the total current. Eventually, this device “hogs” all of the available current and winds up destroying itself.
What we have is a positive thermal feedback loop. Transistor harakiri is a decidedly sub-optimal performance characteristic. To
circumvent this problem we can add small resistors to the emitters of the devices. As all of the paralleled devices are being driven
from a common drive transistor, they all see the same base voltage. If one output transistor starts to grab a larger share of the load
current, the voltage drop across the emitter resistor will increase, thus forcing a reduction in that transistor's base-emitter voltage.
This reduction compensates for the initial tendency of the current to increase. This technique is referred to as local negative
feedback. We have seen this concept before, for example, a swamping resistor falls into this category as does the collector feedback
bias scheme.
An example of a current-sharing output section is shown in Figure 9.3.6. This version uses a Darlington scheme. The newly added
transistors are shown in red while the thermal/current feedback resistors are shown in blue.

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 Figure 9.3.6: Current-sharing output section.

9.3.4: V BE
Multiplier and Miller Capacitor
With the ever increasing complexity of the output section, the simple diode biasing scheme lacks the ability to set the optimal idle
bias to achieve minimum crossover distortion. A more flexible approach is to use a V multiplier, as illustrated in Figure 9.3.7.
BE

Figure 9.3.7: V BE multiplier.

If we ignore base current, the currents through the two resistors are identical. Therefore, their voltages have the same ratio as their
resistances. R is in parallel with V
2 BE so its voltage must be equal to V . Consequently, the voltage across R must be a multiple
BE 2

of V . For example, if we want to generate the equivalent of four base-emitter drops from point A to point B , we make R three
BE 1

times as large as R . What makes this particularly useful as that we can set any ratio we want, and by replacing either resistor with
2

a potentiometer, we can make that voltage adjustable. And example is shown in Figure 9.3.8, using the current-sharing amplifier of
Figure 9.3.6. The V BE multiplier is shown in the dashed red box and replaces the four biasing diodes. A capacitor, C , shunts the
B

multiplier, making sure it behaves as a short for AC signals.

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 Figure 9.3.8: Amplifier with V BE multiplier and Miller compensation capacitor.
The circuit of Figure 9.3.8 also includes another capacitor, C . This is a Miller compensation capacitor. It uses the Miller Effect
M

(see Chapter 6, Miller's Theorem) to create a much larger equivalent input capacitance. This capacitance appears in parallel with
the input of Q and creates a lag network. The inclusion of C allows the designer to tailor the high frequency response of the
1 M

amplifier.

9.3.5: Bridging
Some amplifiers employ a bridged output scheme. This is particularly true where power supply voltages are limited, for example,
in automobiles (nominally 12 VDC but closer to 13.8 VDC from the alternator). Without resorting to an expensive DC-to-DC
converter, an amplifier designed for automotive use is in a bit of a bind. If we assume a +12 volt DC source, then a basic class B
amplifier would use a capacitor coupled configuration like Figure 9.2.6. This would yield a V of 6 volts and a compliance of
C EQ

about 4.2 volts RMS. If we were to use a standard home loudspeaker of 8 Ω, the maximum load power would be a mere 2.25 watts
(this is one reason why car audio systems typically use 4 Ω loudspeakers, because it doubles the output power, in this case to 4.5
watts). A bridged output can double this again.
A block diagram of a bridged drive is shown in Figure 9.3.9. The left half is what we would see normally. On the right half we
have a second identical amplifier but we drive it with an inverted copy of the original signal. What ends up happening is that, as the
left output goes positive, the right output goes negative by the same amount. The end result is that the load sees twice the voltage it
would have from the left amplifier alone. Power varies as the square of voltage so doubling the voltage quadruples the power. The
2.25 watt output of that car amplifier jumps up to 9 watts3. If we want to go higher than this our only options are to further decrease
the loudspeaker impedance (there are practical limits that will not let us go much further) or increase the DC power supply. In the
home, increasing the supply is relatively easy as we have an AC power source. In an automotive system this is a much more
expensive proposition because only DC is generally available.

Figure 9.3.9: Block diagram of bridged amplifier.

An illustration of a bridged system at the transistor level is shown in Figure 9.3.10. For simplicity, this schematic uses basic class B
stages. Input and right-side inversion circuitry are not shown.

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 Figure 9.3.10: Bridged amplifier, transistor level.
The four transistors create a classic H bridge with the load in the center. For a positive V , Q turns on. At the same time, because
in 1

it is being fed by an inverted version of V , Q turns on. Thus, current flows down from V , through Q , across R from left-to-
in 4 CC 1 L

right, down Q , and finally to V

4 EE(blue trace). At full swing, the voltage across the load will be V − V from left to right.
CC EE

For a negative V the opposite happens: Q and Q turn on, allowing current to flow through R from right left. The maximum
in 3 2 L

voltage will be the same but with inverted polarity, hence an effective doubling of load voltage and a quadrupling of load power.
This increased output does not come without downsides. The most obvious problem is a doubling of the output circuitry. The
second issue may not be immediately apparent: the load is not grounded. In simple automobile audio systems, the chassis of the
vehicle is used as the system common or “ground”. Therefore, it is possible to just run a single wire to a loudspeaker from an
amplifier's output. The other loudspeaker terminal is then connected to the chassis at a convenient location. With a bridged output,
two wires must be run to the loudspeaker. If a single-lead loudspeaker system is upgraded with a bridged output amplifier, new
loudspeaker wires must be installed. Otherwise, the chassis return lead winds up shorting out one side of the bridge4.

9.3.6: Power Supply Bypassing

A final comment regarding high power amplifiers, particularly audio amplifiers, is in order. All through this chapter we have
assumed that the DC power supplies will act ideally, mainly that they will present themselves as good AC grounds. This is not
always easy to achieve given the practical limitations of PC board layouts, wiring constraints and so forth. Consequently, power
supply bypass capacitors are often used to ensure a good AC ground. While this was mentioned in Chapter 7 regarding small signal
amplifiers, it is perhaps more important for power amplifiers. The power supply bypass capacitors used for power amplifiers tend
to be larger and the quality more stringent. A simple 1 μ F bypass capacitor would hardly be the norm for a high power audio
amplifier. The practical problem is that large, high quality capacitors are not inexpensive. For example, a 10 μ F polypropylene
capacitor will be at least an order of magnitude more expensive than a similar size aluminum electrolytic (dollars versus cents).
Unfortunately, the electrolytic will have higher leakage and ESR, and will not behave nearly as well at high frequencies (indeed,
the impedance will actually start to increase due to inductive effects once the frequency gets high enough). To both improve
performance and save money, bypass capacitors are sometimes doubled or tripled. For example, a large aluminum electrolytic
might be placed in parallel with a much smaller polyester or polypropylene capacitor. The aluminum electrolytic will give the small
X Cneeded at lower frequencies, and when it starts to behave less ideally at higher frequencies, the higher quality poly capacitor
effectively shunts it and extends the operating range. The result is nearly as effective as the single large, high quality capacitor but
much less expensive.

References
1
Such as bits of wire, aluminum foil, small bolts or screws, etc. Just ask any seasoned repair technician.
2
Not to be confused with the quasi-complimentary output of which we have only partiallynice things to say.
3OK, not huge, but probably still loud enough to obscure the sirens of emergency vehicles until they're right behind you.
4
Oopsy!

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9.4: Summary
Class B operation is defined as having transistor collector current active for 180 out of the waveform cycle. In order to amplify the
∘

entire 360 in linear fashion, two devices are required. Each transistor of a complementary pair is biased at cutoff to achieve a 180
∘ ∘

conduction angle. This means that no-signal collector current is zero, leading to very low power consumption at idle and, unlike
class A amplifiers, dynamic power consumption. Unfortunately, pure class B operation also results in notch or crossover distortion
as the switch over from one transistor to the other is not seamless. This can be mitigated by biasing the devices slightly “on”, which
is known as class AB operation. While simple resistor voltage dividers may be used for this purpose, a generally superior method
uses diodes as they mimic the base-emitter current-voltage characteristic.
The compliance of a class B amplifier is based on its power supplies. Ideally, the peak-to-peak compliance of the amplifier will
equal the total power supply differential. Worst case power dissipation and efficiency are far superior when compared to class A
topology: Device power dissipation is only one-fifth of maximum load power and the theoretical efficiency at maximum load
power is 78.5%. Maximum heating of the transistors occurs at approximately 40% of maximum load power.
A direct coupled drive stage is often used as it reduces parts count and improves performance. Amplifiers can also be extended
through the use of Darlington pairs and current sharing schemes. Other refinements include the use of active current limiting for
device protection, and V BEmultipliers in place of simple biasing diodes for greater flexibility.
Bridging is a technique used to increase output power. It relies on driving a floating load from both sides. Two amplifiers are
needed for this configuration but it can offer a quadrupling of load power for the same power supplies.

9.4.1: Review Questions

1. Define class B operation and compare it to class A.
2. How do the AC and DC load lines differ between class A and class B operation?
3. What is the purpose of the biasing diodes in a class B amplifier?
4. Explain the source of notch distortion and discuss how it can be reduced.
5. What is thermal runaway? How might it be controlled?
6. What is a Sziklai pair?
7. What is a VBE multiplier?
8. Explain the operation of an active current limiter.
9. What is a bridged output configuration? What are its benefits?
10. What's the difference between a complement and a compliment?

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9.5: Exercises
9.5.1: Analysis Problems
1. For the circuit of Figure 9.5.1, determine compliance, P load(max) ,P D(max) , BV C EO and I C (max) .V CC = 15 V, V EE = −15 V, β =
75, R = 16 Ω, R = 680 Ω, R = 680 Ω.
L 1 2

2. For the circuit of Figure 9.5.1, determine Z . V

in CC = 15 V, V EE = −15 V, β = 75, R = 16 Ω, R = 680 Ω, R = 680 Ω.
L 1 2

3. For the circuit of Figure 9.5.1, determine Z . V

in CC = 25 V, V EE = −25 V, β = 70, R = 8 Ω, R = 560 Ω, R = 560 Ω.
L 1 2

Figure 9.5.1
4. For the circuit of Figure 9.5.1, determine compliance P load(max) ,P D(max) , BV C EO and I C (max) .V CC = 25 V, V EE = −25 V, β =
70, R = 8 Ω, R = 560 Ω, R = 560 Ω.
L 1 2

5. For the circuit of Figure 9.5.2, determine P load(max) ,PD(max) , BV C EO and I

C (max) .V CC = 15 V, β = 75, R = 16 Ω, R = 630
L 1

Ω , R = 630 Ω .
2

Figure 9.5.2
6. For the circuit of Figure 9.5.2, determine Z . V
in CC = 15 V, β = 75, R = 16 Ω, R = 630 Ω, R = 630 Ω.
L 1 2

7. For the circuit of Figure 9.5.2, determine Z . V

in CC = 25 V, β = 70, R = 8 Ω, R = 560 Ω, R = 560 Ω.
L 1 2

8. For the circuit of Figure 9.5.2, determine P load(max) ,P D(max) , BV C EO and I C (max) .V CC = 25 V, β = 70, R = 8 L ,
Ω R1 = 510
Ω , R = 510 Ω .
2

9. For the circuit of Figure 9.5.3, determine P ,P , BV

load(max) and I
D(max) C EO C (max) for the output transistors. V CC = 24 V, V EE

= −24 V, β = 75, R = 8 Ω, R = 2.5 kΩ, R = 300 Ω, R = 330 Ω, R = 63 Ω.

L 1 2 3 4

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 Figure 9.5.3
10. For the circuit of Figure 9.5.3, determine A and Z . V
v in CC = 24 V, V EE = −24 V, β = 75, R = 8 Ω, R = 2.5 kΩ, R = 300
L 1 2

Ω , R = 330 Ω , R = 63 Ω .
3 4

Figure 9.5.4
11. For the circuit of Figure 9.5.4, determine P ,P , BV
load(max) and I
D(max) C EO C (max) for the output transistors. VC C = 24 V,
VEE = −24 V, β = 75, R = 16 Ω, R = 600 Ω, R = 5 kΩ, R = 63 Ω, R = 330 Ω.
L 1 2 3 4

12. For the circuit of Figure 9.5.4, determine A and Z . V

v in CC = 24 V, VEE = −24 V, β = 75, R = 16 Ω, R = 600 Ω, R = 5 kΩ,
L 1 2

R = 63 Ω , R = 330 Ω .
3 4

13. Determine the limit current for the circuit of Figure 9.5.5 if R = 0.2 Ω. E

Figure 9.5.5
14. Determine P , and P
load(max) , BV
D(max)and I
C EO for the output and driver transistors of Figure 9.5.6.
C (max) VC C = 50 V,
VEE = −50 V, β = 75, R = 8 Ω, R through R = 0.05 Ω. Assume all other components produce proper bias.
L 5 8

9.5.2: Design Problems

15. For the circuit of Figure 9.5.3, determine values for R and R for proper bias. V
1 2 CC = 32 V, V EE = −32 V, β = 75, R = 8 Ω,
L

R = 330 Ω , R = 63 Ω .
3 4

16. Determine a value for R to set the limit current for the circuit of Figure 9.5.5 to 2 A.
E

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9.5.3: Challenge Problems
17. For the circuit of Figure 9.5.6, determine values for R and R for proper bias. V
1 2 CC = 50 V, VEE = −50 V, β = 85, R = 8 Ω,
L

R through R = 0.05 Ω , R = 2.2 kΩ , R = 330 Ω .

5 8 3 4

18. For the circuit of Figure 9.5.7, determine a value for R for proper bias. V
5 = 30 V, V
CC EE = −30 V, β = 100, R = 16 Ω, R =
L 1

2.2 kΩ, R = 8.2 kΩ, R = 1.2 kΩ, R = 47 Ω, R = 330 Ω, R = 470 Ω, R = 68 Ω.

2 3 4 5 6 7

Figure 9.5.6

9.5.4: Computer Simulation Problems

19. Perform a transient analysis on the circuit of Problem 1 to verify the compliance.
20. Perform a transient analysis on the circuit of Problem 4 to verify the compliance.
21. Perform a DC analysis on the design from Problem 15 to verify the results.
22. Perform a DC analysis on the design from Problem 17 to verify the results.

Figure 9.5.7

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 CHAPTER OVERVIEW

10: Junction Field Effect Transistors (JFETs)

Learning Objectives
After completing this chapter, you should be able to:
Explain the basic operation of the JFET, detailing the different operating regions.
Draw and explain a basic DC bias model for a JFET.
Explain the terms transconductance and pinch-off voltage.
Draw a JFET characteristic curve, detailing pertinent elements and points.
Discuss the advantages and disadvantages of various JFET biasing topologies.
Analyze basic DC biasing circuits for JFETs.
Compare and contrast JFET operation to that of BJTs.

10.1: Introduction
10.2: JFET Internals
10.3: JFET Data Sheet Interpretation
10.4: JFET Biasing
10.5: Summary
10.6: Exercises

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available upon request.

1
10.1: Introduction
The field effect transistor, or FET, is a semiconductor device that serves as an alternative to the bipolar junction transistor. FETs are
available in two broad types: the junction FET, or JFET, and the metal oxide semiconductor FET, or MOSFET.
It is best not to think of FETs as either better or worse than the BJT. They have different characteristics and lend themselves to
applications where BJT performance might be wanting. The inverse is also true and for some applications the judicious use of a
combination of BJTs and FETs can produce superior performance when compared to either device used alone. Like the BJT's NPN
and PNP variants, FETs comes in two “flavors”: the Nchannel type and the P-channel type. We shall cover JFETs first and then
discuss MOSFETs in subsequent chapters. In this chapter we will cover the internal structure of the JFET, its theory of operation
and biasing techniques. In the next chapter we shall discuss small signal JFET amplifiers; both voltage amplifiers and voltage
followers.
The JFET is fundamentally different from a bipolar junction transistor. While the JFET, like the BJT, relies on the PN junction for
operation, the JFET is modeled as a voltage-controlled current source while the BJT is modeled as a current-controlled current
source. Further, the BJT relies on a forward-biased base-emitter junction for proper operation while the JFET achieves current
control via a reverse-biased junction. Consequently, JFET biasing circuits tend to be incompatible with BJT biasing schemes and
one device cannot be swapped out for the other.

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10.2: JFET Internals
A simplified internal model of a JFET is shown in Figure 10.2.1. The main portion of the device is called the channel. The diagram
illustrates an N-channel device. The channel is built upon a substrate (i.e., base layer) of oppositely doped material. Attached to the
opposing ends of the channel are two terminals; the source and the drain. Embedded within the channel is a region using the
opposite material type. A lead is attached to this as well and is called the gate. Although there is not perfect correspondence
between them, the drain, source and gate are roughly analogous to the BJT's collector, emitter and base, respectively.

Figure 10.2.1: Simplified internal structure of an N-channel JFET.

This diagram is drawn symmetrically. Some devices are designed in this fashion and their drain and source terminals can be
swapped with no change in operation. This is not true for all devices, though. For small values of drain-source voltage, the channel
exhibits a certain amount of resistance that is dependent on the doping level and physical layout of the device. Further, under
normal operation, I will equal I .
D S

To understand how the device behaves, refer to Figure 10.2.2. Here we shall consider electron flow (shown as a dashed line). First,
a positive voltage, V , is attached to the drain terminal along with a current limiting resistor, R . A negative supply, V , is
DD D GG

applied to the gate terminal via resistor R . Let's start with the gate supply set to zero. If we start V
G DD at zero, here is what
happens as we increase its value. Initially, an increase in drain-source voltage will elicit a proportional increase in the current
flowing through the channel. In other words, the channel acts like a resistor. As the voltage across the drain-source increases
further, at some point the current will saturate, and no further increases in current will occur in spite of further increases in V DD

and V . At this point the device is behaving as a constant current source. The drain-source voltage where this transition occurs is
DS

called the pinch-off voltage, V . If the drain-source voltage increases too much, breakdown will occur and current will begin to
p

increase rapidly.
What's particularly interesting is what happens when the gate supply is increased in the negative direction. This reverse-biases the
gate-source PN junction and results in a larger depletion region being formed. The depletion region widens into the channel, thus
restricting current flow sooner and at a lower level. The more negative we make V , the lower I becomes. Eventually, when
GG D

VGG goes negative enough, the drain current will turn off. This voltage is called V and it has the same magnitude as V (i.e.,
GS(of f ) P

VP = |V |) . The action can be thought of as operating like a water valve: turning the gate source voltage more negative is
GS(of f )

like turning off the spigot and decreasing the flow.

Figure 10.2.2: Electron flow in an N-channel JFET.

The operation of the JFET can visualized nicely by plotting a set of drain curves, as shown in Figure 10.2.3.

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 Figure 10.2.3: JFET drain curves.
The drain curve family plots drain current, I , versus drain-source voltage, V . We begin with the top-most curve. This is
D DS

generated by setting the gate-source voltage, V , to zero. We then cycle V

GS from zero to some higher value. Initially, we see a
DS

proportional rise in I as V increases. This is called the ohmic or triode region. Eventually, the channel saturates and the current
D DS

levels out. This is the constant current or saturation region and it occurs for V > V . The breakdown voltage is called BV
DS P , DGS

or alternately, V . Above this voltage the current increases rapidly. As usual, we do not wish to operate the device in this
(BR)DS

breakdown region.
If we now repeat the process but this time use a small negative value for V , we will trace out a curve of very similar shape. The
GS

transition to constant current mode will happen at a slightly lower voltage and the current value will be somewhat lower as well.
This process continues in like fashion as we make V more and more negative. Eventually, when V = V
GS , the drain
GS GS(of f )

current drops to virtually zero (in fact, a small leakage current flows called I ). In contrast, if V was allowed to go positive,
D(of f ) GS

operation would be lost because the PN junction would become forward-biased and we would lose control of the current via the
depletion region. This means that the JFET's current control is entirely in the second quadrant and the largest drain current flows
when V = 0 V. This current is called I
GS , which stands for the drain current with a shorted gate-source (i.e, if it's shorted, then
DSS

VGS = 0 V). The JFET cannot produce a continuous current larger than I safely. DSS

The characteristic equation relating drain current and gate-source voltage is shown below. This is valid for the constant current
region (i.e., V > V ).
DS P

2
VGS
ID = IDSS (1 − ) (10.2.1)
VGS(of f )

Where
VGS is the gate-source voltage (V GS(of f )
≤ VGS ≤ 0 ),
ID is the drain current,
IDSS is the maximum current,
VGS(of f ) is the turn-off voltage.
From this we see that the JFET is a square-law device rather than like the BJT which has a logarithmic characteristic.1 In essence,
this curve is a portion of a parabola. This means that the JFET's characteristic curve is much more gradual in slope than that of a
BJT. This will have important implications when it comes to voltage gain potential and distortion, as we shall see in the following
chapter.
It is useful to remember that V and I
GS(of f )
are unique to a given device, rather like β is for a BJT. There can also be a fairly
DSS

large variation in these parameters. For example, a particular model of JFET might show an I variation between 2 mA and 20
DSS

mA, and a V variation between −2 V and −8 V. Generally, the most negative V

GS(of f ) values will be associated with the
GS(of f )

largest I DSS values.

Equation 10.2.1 is plotted in Figure 10.2.4. Compare this curve to the curve generated by the Shockley equation for BJTs, Figure
7.2.1. The graph is shown in normalized form. Instead of plotting for specific values of V and I , the axes are presented
GS(of f ) DSS

as fractional portions of the maximums (i.e., the horizontal axis is −V /V and the vertical axis is I /I
GS GS(of f )
). D DSS

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 Figure 10.2.4: JFET normalized characteristic curve (note: this uses −V /V GSfor the normalized voltage so that the curve
GS(of f )

does not appear reversed compared to a typical device curve).

Example 10.2.1

Using both Equation 10.2.1 and the graph of Figure 10.2.4, determine the drain current if the gate-source voltage is −1 V and
the JFET specs are I = 8 mA and V
DSS = −2 V.
GS(of f )

First, using Equation 10.2.1

2
VGS
ID = IDSS (1 − )
VGS(of f )

2
−1V
ID = 8mA (1 − )
−2V

ID = 2mA

Using the graph, V /V

GS GS(of f )
is 1 V/−2 V, or −0.5. Find this value on the horizontal axis, follow up to the curve and then
across to the right vertical axis. The normalized drain current is 0.25, thus I is 0.25 I
D , or 2 mA. DSS

As the characteristic curve plots output current versus input voltage, the slope of this represents the transconductance, an important
characteristic for biasing and signal analysis. Device transconductance is denoted as g , or alternately as g , and given units of
m fs

siemens. We can derive an equation for transconductance by taking the derivative of Equation 10.2.1.
2
VGS
ID = IDSS (1 − )
VGS(of f )

dID 2IDSS VGS

=− (1 − )
dVGS VGS(of f ) VGS(of f )

The coefficient −2I DSS /V is defined as g , the transconductance when

GS(of f ) m0 VGS = 0 V. This is the maximum
transconductance of the device. Substituting, we arrive at
2IDSS
gm0 = − (10.2.2)
VGS(of f )

VGS
gm = gm0 (1 − ) (10.2.3)
VGS(of f )

A normalized plot of transconductance versus VGS is shown in Figure 10.2.5 . The horizontal axis is −VGS / VGS(of f ) and the
vertical axis is g /g .
m m0

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 Figure 10.2.5: Curve of transconductance.
From this graph we see that the transconductance is a linear function.
Another item of interest regarding these device equations: If we combine Equations 10.2.1 and 10.2.3, we generate two equations
that will prove useful in upcoming work.
−−−−−
gm ID
=√ (10.2.4)
gm0 IDSS

2
ID gm
=( ) (10.2.5)
IDSS gm0

Before moving on, the schematic symbols for JFETs are shown in Figure 10.2.6. The middle vertical line represents the channel,
and as is usually the case, the arrow points to N material. Sometimes the gate arrow is draw in the middle rather than toward the
source. Also, as is the case the BJT, sometimes these symbols are drawn within a circle.

Figure 10.2.6: JFET schematic symbols: N-Channel (left) P-Channel (right)

References
1
As evidenced in the Shockley equation, Equation 2.1.1.

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10.3: JFET Data Sheet Interpretation
A data sheet for the J111 series N-channel JFET is shown in Figure 10.3.1. This is a small signal device designed for audio
frequency circuits. It is available in the common TO-92 through-hole package as well as in the surface mount SOT-23 package.
Note that the source and drain are interchangeable for this device.

Figure 10.3.1a: J111 series N-channel JFET data sheet. Used with permission from SCILLC dba ON Semiconductor.
Examining the absolute maximum ratings and thermal characteristics, we find values typical of small signal devices. Maximum
drain-gate and gate-source voltages are 35 volts and the maximum power dissipation is 625 milliwatts.

Figure 10.3.1b: J111 series N-channel JFET data sheet (cont).

Figure 10.3.1c: J111 series N-channel JFET data sheet (cont).

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From the electrical characteristics, note the large variation in V . For the J111, this runs from a minimum of −3 V to a
GS(of f )

maximum of −10 V. The J112 and J113 exhibit even wider min/max ratios. Also, note how the larger V ranges are
GS(of f )

associated with larger maximums for I . Finally, let's take a look at a series of performance curves shown in Figure 10.3.1d.
DSS

Figure 10.3.1d: J111 series N-channel JFET data sheet (cont).

The upper-left graph is a family of drain curves and corresponds to Figure 10.2.3, presented earlier. Note that the horizontal scale
for V only shows the first 2 volts. The point here is to examine the ohmic region. The two middle graphs plot the characteristic
DS

curve of the device and correspond to Figure 10.2.4, although these graphs are drawn rotated around the vertical axis (note that
VGS is still shown as a negative value). Two important things may be noted here. First, as already mentioned, large values of I DSS

tend to be associated with large values of V . This graph shows that individual plots tend to scale both horizontally and
GS(of f )

vertically away from the origin. Second, thermal variations are very much apparent: As the temperature increases, the characteristic
curve tends to become less steep.
Finally, the two bottom-most graphs plot the variation of g with V . These correspond to Figure 10.2.5, although again, the
m GS

horizontal axis has been rotated around the vertical. Once again we see considerable variation due to temperature. Also, none of the
plots exhibit perfect linearity. Further, at lower temperatures, the linearity of the plots decreases even more, warping a relatively
straight line into a complex curve.

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10.4: JFET Biasing
There are several different ways of biasing a JFET. For many configurations, I and V
DSS will be needed. A simple way to
GS(of f )

measure these parameters in the lab is shown in Figure 10.4.1. To measure I we simply ground the gate and source terminals as
DSS

this forces V GSto be 0 V. We insert an ammeter between V DD and the drain, and then set V to a value higher than V (+15
DD P

VDC generally being sufficient). The resulting ammeter reading is I . Obtaining V

DSS is only slightly more work. Leaving
GS(of f )

the ammeter in the drain, unhook the gate from ground and instead connect it to an adjustable negative power supply. Turn the
supply more negative until the ammeter reads zero (practically speaking, < 1% of I ). At that point the voltage source will be
DSS

equal to V .
GS(of f )

Figure 10.4.1: Measuring I DSS and V GS(of f )

.

10.4.1: DC Model
Before we begin examining the bias circuits themselves, we need a basic DC model of the JFET. A model sufficient for our
analyses is shown in Figure 10.4.2.

Figure 10.4.2: DC model of JFET.

The model consists of a voltage-controlled current source, I , that is equal to the product of the gate-source voltage, V , and the
D GS

transconductance, g . The resistance between the gate and source, R , is that of the reverse-biased PN junction, in other words,
m GS

ideally infinity for DC. As a consequence, in most practical circuits we can assume that gate current, I , is zero. Therefore,
G

ID =I .
S

10.4.2: Constant Voltage Bias

The simplest form of bias is the constant voltage bias. The prototype is shown in Figure 10.4.3 with current directions and voltage
polarities shown.

Figure 10.4.3: Constant voltage bias prototype.

This is a fairly straightforward design using only a couple of resistors and power sources. Figure 10.4.4 shows the same circuit but
with the JFET model inserted, ready for analysis.

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 Figure 10.4.4: Constant voltage bias with model.
Ultimately, the goal here is to determine a means for finding the transistor's drain current and drain-source voltage, along with the
potentials across any other components.
To begin, consider the gate-source loop. By KVL, the V GG source must drop across R and the gate-source junction, V
G GS .

VGG = VR + VGS
G

VGG = IG RG + VGS

IG is approximately zero so this simplifies to

VGS = VGG

Given the transconductance, g , we can find I . Alternately, I may be found using Equation 10.2.1 along with the device
m D D

parameters I and V
DSS . For this circuit, the latter technique tends to be more practical. Once I is found, the voltage drop
GS(of f ) D

across R may be found, and then V is determined from KVL.

D DS

Example 10.4.1

For the circuit of Figure 10.4.5, determine I and V

D DS . Assume I DSS = 10 mA and V GS(of f )
= −5 V.

Figure 10.4.5: Schematic for Example 10.4.1.

First, because I G ≈0 , the drop across R is ≈ 0 and V
G GS = VGG . Using Equation 10.2.1
2
VGS
ID = IDSS (1 − )
VGS(of f )

2
−2V
ID = 10mA (1 − )
−5V

ID = 3.6mA

Looking at the drain-source loop, KVL shows

VDD = ID RD + VDS

VDS = VDD − ID RD

VDS = 25V − 3.6mA × 3.3kΩ

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 VDS = 13.1V

While the computation for the constant voltage bias is relatively simple, it does not exhibit a stable Q point. For example, if
Example 10.4.1 is repeated with another JFET, this one with I DSS = 12 mA and V = −6 V, the results are starkly different:
GS(of f )

ID grows to 5.33 mA and V DS shrinks to 7.4 V. These are considerable changes given the relatively modest shifts in the device
parameters. In this regard, the constant voltage bias is reminiscent of the simple base bias configuration used with BJTs.
To get a better understanding of the Q point stability issue, refer to Figure 10.4.6.

Figure 10.4.6: Variation for constant voltage bias.

Characteristic curves are plotted here for two different devices, one in green and one in blue. These represent the sort of device
parameter variations we might expect to see across a product model. The fixed value of gate bias voltage is shown in red. From this
graph it should be obvious that this form of bias will produce a wide variation in drain current, and thus, is not a good choice for
applications that require a stable Q point. If the application does not have this requirement, constant voltage bias offers the
advantage of requiring a minimum of components.

10.4.3: Self Bias

Self bias uses a small number of components and only a single power supply, yet it offers better stability than constant voltage bias.
The name comes from the fact that the drain current will be used to create a voltage drop that sets up the gate-source, hence the
circuit “biases itself”. It is also referred to as automatic bias. The self bias prototype is shown in Figure 10.4.7.

Figure 10.4.7: Self bias prototype.

Once again, we may assume that I is 0. As R is connected directly to ground, this means that V ≈ 0 V. This being true,
G G G

inspection of the schematic reveals that the magnitude of V must be the same as the voltage across R . Because I = I then
GS S D S

VGS = −ID RS (10.4.1)

This value of V is what generates the drain current. The definition is self-referential. This being the case, how do we analyze the
GS

circuit? A proper derivation of the equation for drain current is not trivial. We start with the characteristic equation (Equation
10.2.1) and expand it.
2
VGS
ID = IDSS (1 − )
VGS(of f )

2
2VGS VGS
ID = IDSS (1 − + )
2
VGS(of f ) VGS(of f )

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 2
2IDSS VGS IDSS VGS
ID = IDSS − +
2
VGS(of f ) VGS(of f )

Substitute using Equation 10.2.2

2IDSS
gm0 = −
VGS(of f )

2
IDSS VGS
ID = IDSS + gm0 VGS +
2
VGS(of f )

Using Equation 10.4.1 this can be expanded to

2 2
IDSS ID RS
ID = IDSS − gm0 ID RS +
2
VGS(of f )

Rearranging yields
2
IDSS RS 2
0 = ID − (1 + gm0 RS )ID + IDSS
2
VGS(of f )

This is a quadratic equation in the form ax 2

+ bx + c and can be solved using the quadratic formula:
− − −−−−−
2
−b ± √ b − 4ac
y =
2a

The positive option in the numerator may be ignored as this occurs for V GS beyond V GS(of f ) . The result is
−−−−−−−− −
1 + gm0 RS − √ 1 + 2gm0 RS
ID = 2 IDSS ( ) (10.4.2)
2
(gm0 RS )

Although this is an accurate analytical solution, it's certainly not the sort of equation most people want to memorize or derive as
needed. As the g R term is repeated in this equation multiple times, it is useful to plot this equation in terms of normalized I
m0 S D

versus g R . This curve is plotted in Figure 10.4.8.

m0 S

To use this curve, the first step is to find g R . The value of

m0 S RS is determined by inspection and gm0 may be determined by
Equation 10.2.2, repeated below for convenience.
2IDSS
gm0 = −
VGS(of f )

The value of g m0 RS is found on the horizontal axis, traced up to the curve and then over to the normalized I ratio. This number is D

multiplied by I DSS to determine the value of I .

D

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 Figure 10.4.8: Self bias curve.

Example 10.4.2

Determine I and V
D DS for the circuit shown in Figure 10.4.9. Assume I DSS = 10 mA and V GS(of f ) = −4 V.

Figure 10.4.9: Schematic for Example 10.4.2.

Using the graphical method, first determine g m0 RS .
2IDSS
gm0 = −
VGS(of f )

2 × 10mA
gm0 = −
−4V

gm0 = 5mS

Therefore gm0 RS = 5 mS ⋅ 2.2 k Ω = 11 . The self bias graph yields approximately 0.12 for the normalized current ratio.
Therefore

ID = 0.12 IDSS

ID = 0.12 × 10mA

ID = 1.2mA

Using Ohm's law and KVL

VD = VDD − ID RD

VD = 20V − 1.2mA × 3.9kΩ

VD = 15.32V

VS = ID RS

VS = 1.2mA × 2.2kΩ

VS = 2.64V

VDS = VD − VS

VDS = 15.32V − 2.64V

VDS = 12.68V

An alternate technique is to make an initial guess for V , typically one half of V

GS . The value of I is then computed from
GS(of f ) D

the characteristic equation (Equation 10.2.1) and compared with the Ohm's law relation, Equation 10.4.1, rewritten as
ID = −V GS / R . Chances are, the two results will not agree so adjust the V
S estimate and repeat the process. If done properly,
GS

the currents should be closer. Iterate this process until you converge on the answer.
To use this technique for the preceding problem we'd start by assuming V = −2 V (half of V
GS ). Using this in Equation
GS(of f )

10.2.1 yields I = 2.5 mA, while using Equation 10.4.1 produces I = 910 μ A. Obviously the initial estimate was not correct. The
D D

second estimate for V GSneeds to increase negatively as this will decrease the result from Equation 10.2.1 and increase the result

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from Equation 10.4.1, hopefully meeting in the middle. We might try −2.5 volts. This will yield 1.4 mA from Equation 10.2.1 and
1.14 mA from Equation 10.4.1. As the gap has narrowed, the adjustment for the third estimate will be smaller, so we could try −2.6
volts. This would be relatively close to the value as computed in Example 10.4.2 (V = −V ). GS S

This approximation technique also offers a clue as to how self bias gains stability over constant voltage bias. If for some reason I D

was to increase, this would create a larger voltage drop across R . Because this voltage is the same magnitude as V , this means
S GS

that VGS grows negatively. A more negative V GS reduces I , thus opposing the initial change in drain current. This feedback
D

mechanism is similar in function to the BJT collector feedback bias. The stability issue is visualized in Figure 10.4.10.

Figure 10.4.10: Variation for self bias.

Two device curves are plotted to represent parameter variation (green and blue). Equation 10.4.1 shows the relationship between
ID and V . If we put this in the form y = mx + b , we find that the line goes through the origin and has a slope of 1/R . This
GS S

line is plotted in red. Where the line intersects the device curve yields the drain current and gate-source voltage for that particular
device. Unlike constant voltage bias, self bias shifts some variation over to V , making I more stable. In fact, if there is a
GS D

particular design target for I or V , a rearrangement of Equation 10.4.1 can be used to find the needed value of R along with
D GS S

the characteristic curve or equation.

VGS
RS = −
ID

For example, if a certain I is desired, this value could be used with Equation 10.2.1 to determine the corresponding
D VGS . These
values are then used to find the required R . Alternately, the normalized values could be obtained via Figure 10.2.4.
S

Example 10.4.3

Determine a value for R to set V

S GS = −2 V for the circuit shown in Figure 10.4.11. Assume I DSS = 20 mA and V GS(of f ) =
−4 V.

Figure 10.4.11: Schematic for Example 10.4.3.

We can determine the drain current using Equation 10.2.1.
2
VGS
ID = ID SS (1 − )
VGS(of f )

2
−2V
ID = 20mA (1 − )
−4V

ID = 5mA

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 VGS
RS = −
ID

−2V
RS = −
5mA

RS = 400Ω

In sum, self bias is a minimal parts count circuit that offers modest stability. The stability can be improved with the addition of
other components, as we shall see with the next bias configuration.

10.4.4: Combination Bias

The combination bias configuration (AKA source bias) is based on self bias but adds a negative power supply connected to R , S

hence its name. This will enhance the stability of I , V and g . The combination bias prototype is shown in Figure 10.4.12.
D DS m

Figure 10.4.12: Combination bias prototype.

The analysis is similar to that of self bias but with one major twist: the source power supply increases the voltage drop across R . S

This stabilizes the voltage (and hence, the current) because it is no longer equal to −V , but rather
GS

VRS = ID RS =∣ VGS ∣ + ∣ VSS ∣ (10.4.3)

If V ≫ V , then we can approximate I as V /R . As with self bias, an analytical solution for I is possible. In order to do
SS GS D SS S D

so, we would begin with the characteristic equation and Equation 10.4.3. The derivation is left as an exercise.
− −−−−−−−−−−−−− −
1 + gm0 RS (1 + k) − √ 1 + 2 gm0 RS (1 + k)
ID = 2 IDSS ( ) (10.4.4)
2
(gm0 RS )

The formula is very similar to the self bias formula but with the addition of a factor, k . k is a “swamping factor” and is defined as
the ratio of V to V
SS . If k = 0 , there is no source power supply and the formula reverts back to the simpler self bias
GS(of f )

formula. On the other hand, if k is very large, I ≈ V /R .

D SS S

As was the case with self bias, we can plot Equation 10.4.4 using the g m0 RS factor. A series of three plots for k = 2, 3 and 4 are
rendered in Figured 10.4.13.1

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 Figure 10.4.13a: Combination bias curve, k = 2 .

Figure 10.4.13b: Combination bias curve, k = 3 .

Figure 10.4.13c: Combination bias curve, k = 4 .

Example 10.4.4

Determine I and V
D DS for the circuit shown in Figure 10.4.14. Assume I DSS = 12 mA and V
GS(of f ) = −4 V.

Figure 10.4.14: Schematic for Example 10.4.4.

Using the graphical method, first determine gm0 RS .
2IDSS
gm0 = −
VGS(of f )

2 × 12mA
gm0 = −
−4V

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 gm0 = 6mS

Therefore g R = 6 mS ⋅ 3.3 k Ω = 19.8. The swamping ratio, k , is V /V

m0 S SS = −8/ − 4 = 2 . This requires the graph
GS(of f )

in Figure 10.4.13a. This graph yields approximately 0.25 for the normalized current ratio. Therefore
ID = 0.25 IDSS

ID = 0.25 × 12mA

ID = 3mA

Using Ohm's law and KVL

VD = VDD − ID RD

VD = 24V − 3mA × 4.7kΩ

VD = 9.9V

VS = VSS + ID RS

VS = −8V + 3mA × 3.3kΩ

VS = 1.9V

VDS = VD − VS

VDS = 9.9V − 1.9V

VDS = 8V

As a crosscheck, using Equation 10.4.4 yields 3.028 mA for I . The deviation is no doubt due to inaccuracy in reading the
D

graph. In any case, using this value of drain current we find V to be 1.992 volts, a little higher than calculated above. This
S

indicates that V is −1.992 volts (because V ≈ 0 V). If we plug this value of V into Equation 10.2.1, I = 3.024 mA; an
GS G GS D

excellent match with the deviation being due to accumulated rounding errors.

In order to show the increased Q point stability of the combination bias, we'll repeat the preceding problem using a JFET with a
significantly lower I .DSS

Example 10.4.5

Determine I for the circuit shown in Figure 10.4.14. Assume I

D DSS = 8 mA and V GS(of f )
= −4 V.
For this version we'll use Equation 10.4.4. First determine g m0 RS .
2IDSS
gm0 = −
VGS(of f )

2 × 8mA
gm0 = −
−4V

gm0 = 4mS

Therefore gm0 RS = 4 mS ⋅ 3.3 k Ω = 13.2. The swamping ratio, k , is V SS / VGS(of f ) = −8/ − 4 = 2 .

− −−−−−−−−−−−−− −
1 + gm0 RS (1 + k) − √ 1 + 2 gm0 RS (1 + k)
ID = 2 IDSS ( )
2
(gm0 RS )

−−−−−−−−−−−−−− −
1 + 13.2(1 + 2) − √ 1 + 2 × 13.2(1 + 2)
ID = 2 × 8mA ( )
2
(13.2)

ID = 2.906mA

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 For the graphical method, a reasonable estimate for the normalized I would be around 0.36, yielding a drain current of 2.88
D

mA. Stability is apparent because the drain current has dropped only a few percent in spite of the fact that I decreased by
DSS

33%.

The graph of Figure 10.4.15 illustrates nicely the increased stability of the Q point. Once again, we plot two representative device
curves in green and blue. As was the case with self bias, a plot line can be drawn, the slope of which is equal to the reciprocal of
R . This plot line does not go though the origin, though. Instead, the x axis intercept is the voltage | V
S |. Thus, the red plot line is
SS

shifted along the V axis.

GS

As can be seen in the graph, the variation in I is reduced (although at the expense of variation in V ). For large values of V
D GS SS

with correspondingly large values of R , the bias plot line becomes nearly horizontal, indicating a very stable Q point. With two
S

variables in play, this bias proves to be very flexible. It can also be realized by using a positive voltage divider at the gate and
removing V (returning R to ground).
SS S

Figure 10.4.15: Variation for combination bias.

10.4.5: Constant Current Bias

The most stable bias for JFETs relies, oddly enough, on a current source made with a BJT. It is called constant current bias, yet
another imaginative tag. Interestingly, although this will keep the Q point very stable, a fixed I does not guarantee the most stable
D

value of voltage gain. In fact, it might be easier to achieve that goal using combination bias. The prototype constant current bias
circuit is shown in Figure 10.4.16. An NPN BJT is used for an N-channel JFET and a PNP would be used with a P-channel JFET,
typically driven from above (i.e., circuit flipped top to bottom).

Figure 10.4.16: Constant current bias prototype.

Ignoring the JFET for a moment, the BJT is configured as in two-supply emitter bias. In this case the base is tied directly to ground,
leaving the emitter at about −0.7 VDC. The remainder of the V EE supply drops across R , establishing the emitter current. As the
E

collector is connected directly to the JFET's source terminal, this means that I ≈ I . The source current winds up being just as
S E

stable as the emitter current, which we have already seen is very stable. The only requirement is that I should not be programmed
E

to be larger than I
DSS . This being true, I will set up a corresponding V . This also establishes V because V ≈ 0 V. Therefore,
D GS S G

the source terminal will be a small positive voltage and this is precisely what the BJT needs in order to guarantee that its collector-
base junction is reverse-biased.
Computation of circuit currents and voltages is straightforward and does not involve the use of graphical aides. The first step is to
examine the BJT's emitter loop and determine I . Once this is found, I and I are known, and all remaining component
E S D

potentials may be found using Ohm's law and KVL.

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This technique does not involve the calculation of V . In fact, because I is very stable, V will show the widest variation of all
GS D GS

biasing circuits when the JFET is changed. If V is needed, it can be determined via a little algebraic manipulation on Equation
GS

10.2.1.

Example 10.4.6

Detemine I , VD DS and V GS in the circuit of Figure 10.4.17. I DSS = 15 mA and V GS(of f ) = −3 V.

Figure 10.4.17: Schematic for Example 10.4.6.

We begin by finding I . E

∣ VEE ∣ −0.7V
IE =
RE

10V − 0.7V
IE =
3.6kΩ

IE = 2.58mA

IE is the same as I and I , therefore

S D

VD = VDD − ID RD

VD = 20V − 2.58mA × 4.7kΩ

VD = 7.87V

To find V we note that V

S S = −VGS and rearrange Equation 10.2.1.
2
VGS
ID = IDSS (1 − )
VGS(of f )

−−−−−
ID
VGS = VGS(of f ) (1 − √ )
IDSS

−−−−−−−
2.58mA
VGS = −3V (1 − √ )
15mA

VGS = −1.24V

Therefore V S = 1.24 V and

VDS = VD − VS

VDS = 7.87V − 1.24V

VDS = 6.63V

We turn next to a computer simulation of a similar circuit to validate our methodology.

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Computer Simulation
A constant current bias circuit is entered into a simulator as shown in Figure 10.4.18.

Figure 10.4.18: Constant current bias circuit in simulator.

A cursory estimate shows that I and I should be around 4.3 mA. Also, V should be approximately 20 V − 4.3 mA ⋅ 2.2 kΩ, or
E D D

about 10.54 volts. The results of a DC operating point analysis are shown in Figure 10.4.19.

Figure 10.4.19: Constant current bias DC operating point simulation results.

The drain voltage (node 3) is just over 10.6 volts, agreeing with our estimate. Also, note the minuscule gate voltage (node 1) of 12
μ V which verifies our continuing assumption in these circuits that V ≈ 0 VDC. Finally, we see a modest potential of about 1.5
G

volts at the source terminal (node 12). This shows the proper reverse-biasing of both the gate-source and collector-base junctions.
Finally, we can examine the Q point variation using Figure 10.4.20 . Here, the plot line is perfectly horizontal and all device
variation is manifest in V .
GS

Figure 10.4.20: Variation for constant current bias.

References
1
We could add a third axis for k and plot a surface, and while it might be pretty, a 3D plot like this rendered onto a 2D surface, such
as a page in a textbook, is of marginal utility.

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10.5: Summary
The junction field effect transistor is an altogether different device from the bipolar junction transistor. Instead of relying on a
forward-biased PN junction to control current, the JFET utilizes a reverse-biased PN junction. Furthermore, the JFET uses voltage
control rather than the BJT's current control. In spite of this, a family of JFET drain curves offers similarity to the BJT's collector
curves, exhibiting three regions: ohmic, constant current and breakdown.
The DC model of a JFET includes a voltage-controlled current source in the drain and a very, very large resistance, R , from gate
GS

to source. This resistance models that of a reverse-biased PN junction. The characteristic equation of the JFET is square-law and is
consequently much more gentle in slope than the corresponding equation for a BJT. The maximum current produced by a JFET is
IDSS and occurs when V = 0 V. V must always be negative to ensure proper operation and all negative values will lead to a
GS GS

drain current less than I

DSS . Once the gate-source becomes negative enough (at V ), drain current goes to zero.
GS(of f )

There are several methods to bias JFETs. Perhaps the most simple method is to apply a fixed potential to the gate while grounding
the source. This is called constant voltage bias and is the least stable bias in terms of Q point. Self bias uses a minimum of
components and offers modest stability. It is a decent general-purpose bias. The addition of a negative power supply to the source
resistor leads to the combination bias topology. This circuit offers improvements in stability over self bias. The most stable bias is
the constant current bias. This form relies on a BJT to establish a very stable current.

10.5.1: Review Questions

1. Compare the operation of the JFET to the BJT.
2. Compare the regions of JFET drain curves to those of BJT collector curves.
3. Why is the JFET referred to as a square-law device?
4. Rank the biasing schemes presented in this chapter in terms of Q point stability.
5. What is pinch-off voltage?
6. How does the JFET DC biasing model differ from the BJT DC model?

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10.6: Exercises
10.6.1: Analysis Problems
1. For the circuit of Figure 10.6.1, determine I and V
D DS .IDSS = 40 mA, V GS(of f ) = −4 V, V DD = 26 V, V GG = −2 V, R = 220 k
G

Ω, R D = 1.2 kΩ.
2. For the circuit of Figure 10.6.1, determine I and V
D DS .IDSS = 20 mA, V GS(of f ) = −3 V, V DD = 22 V, V GG = −1 V, R = 390 k
G

Ω, R D = 1 kΩ.

Figure 10.6.1
3. For the circuit of Figure 10.6.2, determine I , V and V . I
D G D DSS = 24 mA, V GS(of f )
= −6 V, V DD = 36 V, R = 220 kΩ, R = 2
G S

kΩ, R = 1.8 kΩ.

D

4. For the circuit of Figure 10.6.2, determine I , V and V

D S DS .IDSS = 18 mA, V GS(of f )
= −3 V, V DD = 30 V, R = 270 kΩ,
G RS =
2.7 kΩ, R = 3.3 kΩ.
D

Figure 10.6.2
5. For Figure 10.6.3, determine I , V and V . I
D G D DSS = 16 mA, V DD = 25 V, V GS(of f ) = −3 V, V SS = −6 V, R = 560 kΩ, R = 2
G S

kΩ, R = 3.6 kΩ.

D

6. For Figure 10.6.3, determine I , and V

D DS .I DSS = 16 mA, V DD = 25 V, V GS(of f ) = −3 V, V SS = −9 V, R = 680 kΩ, R = 2 k
G S

Ω, R D = 2.7 kΩ.

Figure 10.6.3
7. For Figure 10.6.4, determine I , V and V . I
D G D DSS = 16 mA, V DD = 25 V, VGS(of f )
= −3 V, V
EE = −9 V, R = 810 kΩ, R = 2
G E

kΩ, R = 2.7 kΩ.

D

8. For the circuit of Figure 10.6.4, determine I and V

D DS .IDSS = 40 mA, V GS(of f )
= −4 V, V DD = 30 V, V EE = −6 V, R = 750 k
G

Ω, R E = 500 Ω, R = 1.8 kΩ.

D

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10.6.2: Design Problems
9. Using the circuit of Figure 10.6.2, determine a value for R to set I to 4 mA. I
S D DSS = 10 mA, V GS(of f ) = −2 V, V DD = 20 V,
R G = 430 kΩ, R = 1.8 kΩ.
D

10. Using the circuit of Figure 10.6.1, determine a value for VGG to set I to 2 mA. I
D DSS = 10 mA, V GS(of f ) = −4 V, V DD = 28 V,
R G = 470 kΩ, R = 4.7 kΩ.
D

11. Using the circuit of Figure 10.6.4, determine a value for R to set I to 4 mA. I
E D DSS = 18 mA, V GS(of f ) = −3 V, V DD = 25 V,
VEE = −12 V, R = 330 kΩ, R = 2.2 kΩ.
G D

Figure 10.6.4
12. Using the circuit of Figure 10.6.4, determine values for R and R to set I to 5 mA and V to 6 V. I
E D D D DSS = 20 mA, V GS(of f )

= −4 V, VDD = 32 V, V EE = −10 V, R = 390 kΩ.

G

10.6.3: Challenge Problems

13. Following the derivation of Equation 10.4.2, derive Equation 10.4.4.
14. Using the circuit of Figure 10.6.3, determine values for R and V
S SS to set I to 4 mA. I
D DSS = 16 mA, V GS(of f )
= −4 V, V DD

= 30 V, R = 680 kΩ, R = 2 kΩ.

G D

10.6.4: Computer Simulation Problems

15. Perform a DC operating point simulation on the circuit of Problem 7 to verify the results. The J111 will be sufficient.
16. Perform a DC operating point simulation on the circuit of Problem 10 to verify the results. The J111 will be sufficient.

10.6.5: Department of Marginal Utility

Figure 10.6.5: Combination Bias Surface Plot.

The graphs of Figure 10.4.13 represent three slices from this surface.

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Looks cool, but...

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 CHAPTER OVERVIEW

11: JFET Small Signal Amplfiers

Learning Objectives
After completing this chapter, you should be able to:
Determine the voltage gain, input impedance and output impedance of basic JFET amplifiers.
Draw and explain a basic AC model of a JFET.
Compare and analyze JFET voltage amplifiers and voltage followers.
Discuss the advantages and disadvantages of JFET circuits with those of comparable BJT circuits.
Analyze small signal combination BJT/JFET amplifier circuits.
Discuss applications that make use of the JFET's ohmic region.

11.1: Introduction
11.2: Simplified AC Model of the JFET
11.3: Common Source Amplifier
11.4: Common Drain Amplifier
11.5: Multi-stage and Combination Circuits
11.6: Ohmic Region Operation
11.7: Summary
11.8: Exercises

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request.

1
11.1: Introduction
The JFET can be used to create both voltage amplifiers and voltage followers. In comparison with the BJT, the JFET tends to have
less voltage gain potential. On the other hand, JFET circuits offer the possibility of a much higher input impedance, lower noise
and better high frequency performance. There are many other similarities with BJT amplifiers. For example, the possibility of
swamping still exists as a means of lowering distortion at the expense of voltage gain. Also, the JFET voltage amplifier inverts the
signal, just like the BJT version. When it comes to AC analysis, a key element for the BJT is r . For the JFET, the comparable
′
e

parameter is transconductance, g . m

JFET amplifiers and followers can be used with their BJT cousins. Indeed, the combination of the two, each playing to their
strengths, has the potential to outperform a design using only one type of device.
Alongside their use in amplifiers and followers, JFETs can also be used in their ohmic region. This includes applications as
voltage-controlled resistors and analog switches. In this mode, the device no longer behaves as a constant current source. Instead,
the channel resistance becomes a function of the gate-source voltage and can be used as a control element within a voltage divider.
As such, it has the capability of changing resistance value much faster than a mechanical potentiometer.

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11.2: Simplified AC Model of the JFET
An AC model of the JFET is shown in Figure 11.2.1. This is essentially the same model as was used for DC analysis. Once again,
we have a voltage-controlled current source situated in the drain. The reverse-biased junction shows up as a very large resistance,
r .GS

Figure 11.2.1: AC model of JFET.

It is worth mentioning that this model is suitable only for low frequencies. At higher frequencies, device capacitances can play a
major role in the response of the amplifier. There are three device capacitances not shown in the Figure that shunt each pair of
terminals: C , C
GS DGand C . On a data sheet, the “lumped” capacitances are often given. These are C , the capacitance
DS iss

looking into the gate with the source and drain shorted to ground: C = C + C iss ; and C , the capacitance seen from the
GS DG rss

drain with the gate and source shorted to ground: C = C + C rss DS . As we shall see, these capacitances can have a sizable
DG

impact on amplifier characteristics such as Z . in

The value of transconductance, g , will prove to be of particular interest. It is roughly of equal importance to r in a BJT.1
m
′
e

References
1
In fact, we can say that 1/r is g for a BJT.
′
e m

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11.3: Common Source Amplifier
The common source amplifier is analogous to the common emitter amplifier. The prototype amplifier circuit with device model is
shown in Figure 11.3.1.

Figure 11.3.1: Common source amplifier with model.

This circuit includes a swamping resistor, r . The input signal is presented to the gate terminal while the output is taken from the
S

drain.

11.3.1: Voltage Gain

An equation for the voltage gain, A , is developed as follows. First, we start with the fundamental definition, namely that voltage
v

gain is the ratio of v to v , and proceed by expressing these voltages in terms of their Ohm's law equivalents.
out in

vout vD
Av = = (11.3.1)
vin vG

−iD rL
Av =
iD rS + vGS

−gm vGS rL
Av =
gm vGS rS + vGS

gm rL
Av = −
gm rS + 1

If there is no swamping resistor, the first portion of the denominator drops out and the gain simplifies to −g ⋅ r . The swamping
m L

resistor in the source, r , plays the same role here as it did in the BJT: it helps to stabilize the gain and reduce distortion. It does so
S

at the expense of voltage gain.

11.3.2: Input Impedance

Referring back to Figure 11.3.1, the input impedance of the amplifier will be r in parallel with the impedance looking into the
G

gate terminal, Z . For the non-swamped case, this will be r . At low frequencies r is very large, well into the megohms.
in(gate) GS GS

In most practical circuits, r will be much lower, hence

G

Zin = rG || rGS ≈ rG (11.3.2)

Theoretically, for swamped amplifiers Z will be higher than r but this is a moot point. In either case, it is relatively easy
in(gate) GS

to obtain a high input impedance, certainly much easier than it is for typical single-device BJT amplifiers.
It might be easy to become complacent and simply assume that r sets the input impedance and that's the end of it. This would be a
G

mistake. As mentioned earlier, with impedances this high, we cannot ignore items such as junction capacitance. For example, for a
general purpose device a typical value for C , the total input capacitance, may be in the vicinity of 5 to 10 pF. This capacitance
iss

appears in parallel with r . If this amplifier is used for ultrasonic signals, the capacitive reactance, X , would be as low as 160 kΩ
G C

at 100 kHz. Although this is high compared to typical BJT circuits, it's less than the R values commonly used for biasing. At
G

higher frequencies, the situation is even worse as X decreases with frequency. Also, we are ignoring the Miller effect here which
C

makes the situation even worse than even worse, so perhaps we can say that it's even worser, which is a claim we could also make
regarding the grammar of this sentence.

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11.3.3: Output Impedance
To investigate the output impedance, we'll refer to Figure 11.3.2. This circuit is very similar to that of Figure 11.3.1. The major
difference is that the AC load equivalent has been split into its two components, the load itself, R , and the drain biasing resistor,
L

R .
D

Figure 11.3.2: Output impedance of common source amplifier.

From the vantage point of R , peering back into the amplifier we see R in parallel with the impedance at the drain. At the drain
L D

we find the current source, i . The internal impedance of this equivalent current source is very high compared to typical values for
D

R D (hundreds of kΩ), therefore we can approximate the output impedance as

Zout ≈ RD (11.3.3)

It should be noted that all forms of DC bias discussed in the previous chapter are game here. There are a few limitations to be
aware of, though. For example, when using constant voltage bias, swamping is not possible as that bias form does not use a source
resistor. In contrast, self bias and combination bias include a source resistor so swamping is a possibility, however, R may need to
S

be split and partially bypassed to achieve the desired results. Finally, constant current bias is not well-positioned to use swamping
as that would require some additional work to fit in a new R along with the current source. More typically, the current source will
S

just be bypassed with a capacitor to produce a non-swamped amplifier.

Example 11.3.1

Determine the voltage gain and input impedance for the circuit shown in Figure 11.3.3 . Assume IDSS = 15 mA and
V = −3 V.
GS(of f )

Figure 11.3.3: Circuit for Example 11.3.1.

This is an unswamped common source amplifier with constant current bias. We can determine Z in via inspection.

Zin = Zin(gate) || RG

Zin ≈ 10M Ω

To find the voltage gain, we'll first need to find I and g

D m0 in order to find g .
m

11.3.2 https://eng.libretexts.org/@go/page/25321
 ∣ VEE ∣ −0.7V
ID =
RE

5V − 0.7V
ID =
1kΩ

ID = 4.3mA

2IDSS
gm0 = −
VGS(of f )

30mA
gm0 = −
−3V

gm0 = 10mS

Knowing the current and maximum transconductance, we can find g through the use of Equation 10.2.4.
m

−−−−−
gm ID
=√
gm0 IDSS

−−−−−
ID
gm = gm0 √
IDSS

−−−−−−
4.3mA
gm = 10mS √
15mA

gm = 5.35mS

gm rL
Av = −
gm rS + 1

5.35mS(2.2kΩ||4.7kΩ)
Av = −
5.35mS × 0Ω + 1

Av = −8.02

Example 11.3.2

Determine the voltage gain and input impedance for the circuit shown in Figure 11.3.3. Assume IDSS = 24 mA and
V = −4 V.
GS(of f )

Figure 11.3.4: Circuit for Example 11.3.2

This is an unswamped common source amplifier with self bias. Once again, we can determine Z in via inspection.

Zin = Zin(gate) || RG

Zin ≈ 1M Ω

To find the voltage gain, we'll first need to find g

m0 . Also, we can take a shortcut and find the normalized drain current from
the self bias graph instead of finding I itself.
D

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 2IDSS
gm0 = −
VGS(of f )

48mA
gm0 = −
−4V

gm0 = 12mS

RS is 1.5 kΩ, therefore g m0 RS = 18 . From the self bias graph this produces a normalized drain current of 0.08.
−−−−−
ID
gm = gm0 √
IDSS

−−−
−
gm = 12mS √0.08

gm = 3.4mS

Again, there is no swamping so r S =0 . The gain formula reduces to

Av = −gm rL

Av = −3.4mS(22kΩ||5kΩ)

Av = −13.9

We will now turn our attention to the effect of swamping. As in the BJT case, we expect to sacrifice gain and in return, see an
improvement in distortion. We shall examine this through the use of a simulation.

Computer Simulation
A common source amplifier using self bias is entered into the simulator as shown in Figure 11.3.5.

Figure 11.3.5: Common source amplifier in simulator.

Reasonable device values for this model are I DSS = 40 mA and V GS(of f ) = −2.3 V. Based on these we find
2IDSS
gm0 = −
VGS(of f )

80mA
gm0 = −
−2.3V

gm0 = 34.8mS

Given R S =1 kΩ, the self-bias equation yields

−−−−−−−− −
1 + gm0 RS − √ 1 + 2gm0 RS
ID = 2 IDSS ( )
2
(gm0 RS )

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 − −−−− −−−−−
1 + 34.8 − √ 1 + 2 × 34.8
ID = 2 IDSS ( )
(34.8)2

ID = 1.81mA

−−−−−
ID
gm = gm0 √
IDSS

−−−−−−−
1.81mA
gm = 34.8mS √
40mA

gm = 7.4mS

Av = −gm rL

Av = −7.4mS(2kΩ||10kΩ)

Av = −12.3

The results of a transient analysis are shown in Figure 11.3.6 for a 100 mV peak input signal.

Figure 11.3.6: Transient analysis of the common source amplifier.

First, the inversion between the input (blue trace) and output (red trace) is obvious. Also, some distortion is evident in the output
waveform. Inspecting the positive and negative peaks shows that the positive peaks are are a little more broad than the negative
ones and don't quite reach the same magnitude. The averaged gain is about −11.75, around 5% low from the estimate and not too
bad considering the distortion.
The simulation is run a second time, but this time around the 1 kΩ source resistor is split into a 200 Ω/800 Ω pair with only the 800
Ω being bypassed. The DC bias does not change leaving g m untouched, but the new 200 Ω swamping resistor drops the gain to
gm rL
Av = −
gm rS + 1

7.4mS(2kΩ||10kΩ)
Av = −
7.4mS × 200Ω + 1

Av = −4.96

The output signal from the simulator is shown in Figure 11.3.6.

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 Figure 11.3.7: Transient analysis of the swamped common source amplifier.
The input signal was raised to 240 mV peak in order to keep the output signals of the two versions at the same amplitude. The
symmetry appears to be better here and the gain works out to −4.85, just a few percent low.
Total harmonic distortion (THD) analysis is performed next. The results are shown in Figures 11.3.8 and 11.3.9. To keep the
comparison fair, the input levels are adjusted to maintain similar output voltages. The non-swamped results are seen in Figure
11.3.8, and as expected based on the waveform asymmetry, the THD is relatively high at roughly 4%. The swamped version scores

better at just over 1.6%, although this is still not stellar performance.

Figure 11.3.8: THD of common source amplifier.

Figure 11.3.9: THD of swamped common source amplifier.

It is interesting to note that while the voltage gain of the swamped amplifier has dropped to 41% of the non-swamped gain, the
THD has dropped to 41% of the nonswamped THD. In fact, given the square-law nature of the characteristic curve, we would
expect the distortion to be lower if we used smaller signals. To verify this, the THD simulation is run again for the swamped
amplifier, but now using an input signal ten times smaller at only 24 mV peak. The result is shown in Figure 11.3.10.

11.3.6 https://eng.libretexts.org/@go/page/25321
 Figure 11.3.10: THD of swamped common source amplifier with reduced signal level.
The resulting THD is markedly lower for an order of magnitude improvement. We're now at least approaching “hi-fi” territory.

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11.4: Common Drain Amplifier
The common drain amplifier is analogous to the common collector emitter follower. The JFET version is also known as a source
follower. The prototype amplifier circuit with device model is shown in Figure 11.4.1. As with all voltage followers, we expect a
non-inverting voltage gain close to unity, a high Z and low Z .
in out

Figure 11.4.1: Common drain (source follower) prototype.

The input signal is presented to the gate terminal while the output is taken from the source. Many bias circuits may be used here as
long as they do not have a grounded source terminal such as constant voltage bias.

11.4.1: Voltage Gain

In order to develop an equation for the voltage gain, A , we follow the same path we took with the common source amplifier
v

earlier in this chapter. First, we start with the fundamental definition, namely that voltage gain is the ratio of v to v , and
out in

proceed by expressing these voltages in terms of their Ohm's law equivalents.

vout vS
Av = = (11.4.1)
vin vG

iD rL
Av =
iD rL + vGS

gm vGS rL
Av =
gm vGS rL + vGS

gm rL
Av =
gm rL + 1

Equation 11.4.1 is very similar to the gain equation derived for the swamped common source amplifier; the notable changes being
the lack of the minus sign indicating that this circuit does not invert the signal, and r replacing r in the denominator. It is worth
L S

remembering that r here is the AC source resistance while in the common source amplifier r is the AC drain resistance. To avoid
L L

potential confusion, this equation could also be written as

gm rS
Av = (11.4.2)
gm rS + 1

In any event, the goal is to make sure that g

m rS ≫ 1 . By doing so, the voltage gain will be very close to unity.

11.4.2: Input Impedance

The analysis for common drain input impedance is virtually identical to that for the swamped common source amplifier. The result
is replicated here for convenience.

Zin = rG || rGS ≈ rG (11.4.3)

11.4.3: Output Impedance

In order to investigate the output impedance, we'll separate the load resistance from the source bias resistor, as shown in Figure
11.4.2.

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 Figure 11.4.2: Common drain output impedance analysis.
From the position of R , looking back toward the source we find R in parallel with the impedance looking back into the source
L S

terminal. The voltage at this node is v and the current entering this node is i . The ratio of the two must yield the impedance
GS D

looking into the source.

vGS
Zsource = (11.4.4)
iD
vGS
Zsource =
gm vGS

1
Zsource =
gm

Therefore, the output impedance is

1
Zout = RS || (11.4.5)
gm

We can expect this value to be much smaller than the output impedance of typical common source amplifiers.

Example 11.4.1

For the follower shown in Figure 11.4.3 , determine the input impedance and output voltage. Assume Vin = 100 mV,
IDSS = 30 mA, V = −2 V.
GS(of f )

Figure 11.4.3: Circuit for Example 11.4.1.

This is a follower using self bias. We'll find g via the self bias graph.
m

2IDSS
gm0 = −
VGS(of f )

60mA
gm0 = −
−2V

gm0 = 30mS

RS is 1 kΩ, yielding 30 for gm0 RS . The normalized drain current from the self bias graph is approximately 0.05.
−−−−−
ID
gm = gm0 √
IDSS

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 −−−
−
gm = 30mS √0.05

gm = 6.71mS

gm rS
Av =
gm rS + 1

6.71mS(1kΩ||600Ω)
Av =
6.71mS(1kΩ||600Ω) + 1

Av = 0.716

Thus V out is 71.6 mV. By inspection, Z in may be approximated as 2.2 MΩ.

Example 11.4.2

For the circuit shown in Figure 11.4.4, determine the input impedance and output voltage. Assume V in = 100 mV, I
DSS = 36

mA, V GS(of f )
= 3 V.

Figure 11.4.4: Circuit for Example 11.4.2.

This follower uses combination bias with a P-channel JFET. Note that the source is at the top. We'll find gm via the
combination bias graph for k = 3 (k = V /V ).
SS GS(of f )

2IDSS
gm0 =
VGS(of f )

72mA
gm0 =
3V

gm0 = 24mS

RS is 1.8 kΩ, yielding 43.2 for gm0 RS . The normalized drain current from the k = 3 combination bias graph is approximately
0.17.
−−−−−
ID
gm = gm0 √
IDSS

−−−
−
gm = 24mS √0.17

gm = 9.9mS

gm rS
Av =
gm rS + 1

9.9mS(1kΩ||1.8kΩ)
Av =
9.9mS(1kΩ||1.8kΩ) + 1

Av = 0.864

Thus V out is 86.4 mV. By inspection, Z in may be approximated as 390 kΩ.

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11.5: Multi-stage and Combination Circuits
The rules for multi-stage circuits utilizing JFETs are the same as those discussed for BJTs: Steps must be taken to ensure that the
bias of one stage does not adversely affect the bias of surrounding stages (typically by using coupling capacitors or going to a DC
coupled system), the load for a given stage will be the input impedance of the following stage, the input impedance of the system
will be the input impedance of the first stage, and the system gain will be the product of the individual stage gains.
Keeping those items in mind, there are no limits concerning mixing BJTs with JFETs, or mixing N-channel with P-channel devices.
There are certain practical issues, however, that might dictate where certain devices are used. JFETs, due to their high input
impedance and modest gain potential, tend to be used at the front end of amplifying systems. Their comparatively low self-noise is
also a bonus at this location. BJTs, on the other hand, have high gain potential and tend to be used in the remaining stages. Their
high distortion can be tamed through swamping.
To examine the possibilities, let's walk through the mixed, multi-stage amplifier presented in Figure 11.5.1.

Figure 11.5.1: Two-stage JFET/BJT amplifier.

This amplifier uses a bipolar power supply which gives the designer a lot of flexibility. The first stage consists of a JFET common
source amplifier. It utilizes combination bias (notice that R is connected to the shared negative supply, V , that also serves as
S EE

VSS ). C bypasses the source resistor so this stage does not use swamping. Distortion should not be an issue unless the input signal
S

is fairly large. The load for this stage is R in parallel with the input impedance to the second stage (coupling capacitor C will
D C

appear ideally as a short for signal frequencies).

The second stage utilizes an NPN BJT configured as a swamped common emitter amplifier. It utilizes two-supply emitter bias. It's
input impedance is the parallel combination of R and Z
B . The base input impedance, in turn, is a function of β and R
in(base) ( SW

r will have only a small impact due to the swamping resistor). The load for this stage will be R in parallel with R . That value
′
e L C

divided by R SW will give the approximate stage gain (again, r will have little impact). Although the second stage will be dealing
′
e

with a larger signal, distortion will be mitigated by the swamping resistor.

The system gain will be the product of the two stage gains. As they both invert the signal, the inversion of the inversion will lead to
an output signal that is in phase with the input signal. The system input impedance will depend on the JFET first stage and can be
approximated to be equal to R , at least at low frequencies.
G

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11.6: Ohmic Region Operation
As noted in the previous chapter, the JFET's operational curves span three regions. Two have been discussed: the constant current
region is where the normal amplifiers and followers are biased, and breakdown is a region to be avoided due to potential damage.
The third region is known as the ohmic region, or triode region. It occurs in the area where V is less than the pinch-off voltage,
DS

V . In this area, the device behaves more like a resistor than like a current source. If we were to examine a family of drain curves,
P

like those of Figure 10.2.3, and magnify the area near the origin, we would see something like the plot in Figure 11.6.1.

Figure 11.6.1: FET ohmic region.

If V is a small value, typically less than 100 mV or so, each of the curves appears as a straight line. Further, the slope of that line
DS

is a function of the gate-source voltage, V . The closer V is to 0 V, the steeper the slope (violet line) and the closer V is to
GS GS GS

V , the more shallow the slope (dark red line). Finally, if V = V

GS(of f ) , the slope is nearly zero (aqua line). Because this is
GS GS(of f )

a plot of drain current versus drain-source voltage, the slope indicates the conductance of the channel. In somewhat more useful
terms, we can say that the reciprocal of the slope indicates the resistance of the channel. Therefore, if V = 0 V, the channel GS

resistance will be at its minimum, and when V = V , the channel resistance will be at its maximum. The maximum
GS GS(of f )

channel resistance can be quite high, well into the hundreds of kilo-ohms. The minimum channel resistance varies considerably
from device to device. It is found on a data sheet as r .r can be as small as a few ohms for specialized JFETs and as
DS(on) DS(on)

large as hundreds of ohms for general purpose devices.1 For example, the data sheet for the J111 series JFETs found in Figure
10.3.1 shows maximum values of 30 Ω, 50 Ω and 100 Ω for the J111, J112 and J113, respectively. The channel resistance does not
follow a linear relation with V . GS

To be more specific, in this region the drain current no longer follows the characteristic equation we used for biasing (Equation
10.2.1). The drain current equation in the ohmic region is:
VDS VGS VDS
ID = 2 IDSS ((1 − )− ) (11.6.1)
VP VP VP

Where V P = | VGS(of f )| and V GS is to be taken as an absolute value and lies between 0 and V . P

Recalling that, in general, r = V DS DS / ID , we can substitute Equation 11.6.1 for ID and, after including the definition of gm0 ,
arrive at an expression for r : DS

\[r_{DS} = \frac{V_P}{g_{m0} \left( V_P −V_{GS} − \frac{V_{DS}}{2} \right) \nonumber \]

For small values of V DS , this reduces to a simple equation:
VP
rDS = (11.6.2)
gm0 (VP − VGS )

What we have created here is voltage-controlled resistor. Equation 11.6.2 shows that the resistance of the channel is a function of
the gate-source voltage: the channel resistance will be at its minimum (r ) when V = 0 V, and it approaches infinity when
DS(on) GS

VGS equals V . Generally, there are two applications that make use of the ohmic region: an electronic rheostat/potentiometer
GS(of f )

and an analog switch. A simple circuit that can be used for either application is shown in Figure 11.6.2.

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 Figure 11.6.2: Using the JFET as a voltagecontrolled resistor or switch.
Note that no external bias is applied to the circuit. Instead, a control voltage, V , is applied to the gate and the input signal is
C

applied to a resistor attached to the drain terminal. The output is taken across the JFET's drain-source.
The idea behind this circuit is the basic resistive voltage divider. The JFET's channel resistance, r DS , forms a voltage divider along
with R .D

rDS
vout = Vin
rDS + RD

If r ≫ R , v approaches v . Conversely, if r ≪ R , v approaches zero. Normally, R is set somewhere between the

DS D out in DS D out D

maximum and minimum channel resistances in order to obtain the widest range of operation.
As the control voltage V is V , then V controls the size of v . If we set V to 0 V, r is very small and thus v ≈ 0 . On
C GS C out C DS out

the other hand, if V is set to a large negative potential (beyond V

C ), then v ≈ V . If V is set between these extremes
GS(of f ) out in C

then v outwill be somewhere in the middle range. If V is continuously variable, then the circuit behaves like a solid-state
C

potentiometer. If, in contrast, V is only set at the limits, then the circuit behaves like a switch, either allowing or preventing the
C

signal from transferring through. This is known as an analog switch.

A single JFET/resistor combination as shown in Figure 11.6.2 will have limited isolation as an analog switch and only a modest
range of adjustment when used as a voltage-controlled potentiometer. To improve performance, multiple circuits can be cascaded
or other JFETs can be added to create a “pi” attenuator network.
This voltage-controlled resistor has a huge advantage over traditional electromechanical potentiometers and switches: speed. In this
circuit, the resistance can be changed at very high rates, essentially, as fast as V can change. Consequently, it would be no big deal
C

to switch the input signal on and off at rates well over 100,000 times per second. No mechanical switch or potentiometer can hope
to perform anywhere near that speed, and any attempt to do so would lead to the devices burning up from the friction. In general,
flaming potentiometers are frowned upon during the design and development process, although it would make a decent name for an
indie rock band. Another advantage is that a switch can be thrown “remotely”, that is, we only need to route the control voltage to
the switch operator, not the signal itself. This can reduce system noise. It's also easier to implement if the switch is being “thrown”
programmatically, such as via a microcontroller.

Example 11.6.1

For the circuit shown in Figure 11.6.3, if the input signal is 50 mV, determine the output voltage for VC = 0 VDC and −6
VDC. Assume V = −5 V, r
GS(of f )
= 30 Ω and r
DS(on)
= 800 kΩ .
DS(of f )

For V C =0 VDC, the channel resistance will be at its minimum of r DS(on)

.

Figure 11.6.3: Circuit for Example 11.6.1.

rDS(on)
Vout = Vin
RD + rDS(on)

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 30Ω
Vout = 50mV
10kΩ + 30Ω

Vout = 0.15mV

The signal has been reduced by a factor of over 330. That's not as good as a mechanical switch but if we cascaded two of these
the overall reduction would be more than 100,000:1.
For V C = −6 VDC, the channel resistance will be at its maximum of r .
DS(of f )

\[V_{out} = V_{i n} \frac{r_{DS (off )}{R_D+r_{DS (off )}} \nonumber \]

800kΩ
Vout = 50mV
10kΩ + 800kΩ

Vout = 49.4mV

This represents nearly 99% of the input signal, so the signal is passed through cleanly.

Computer Simulation
To verify the results of the preceding example, the circuit is entered into a simulator as shown in Figure 11.6.4. A J111 JFET model
is used which has parameters similar to those used in the example.

Figure 11.6.4: Analog switch in simulator.

A transient analysis is run twice; the first time is with a control voltage of 0 V and the second with a control voltage of −6 V. In the
first case, the output should be just a small residual and in the second, we should see the full input signal. The results of the first
trial are shown in Figure 11.6.5 while the second is shown in Figure 11.6.6.

Figure 11.6.5: Transient analysis using V C =0 V.

With V at 0 V, the output trace (red, at node 2) is nearly flat. The precise value of its peak is 0.167 mV, not far from the value
C

calculated in Example 11.6.1.

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 Figure 11.6.6: Transient analysis using V C = −6 V.
In contrast, when V = −6 V the JFET is off, offering a high impedance and no loss of signal. At first glance, it may appears as
C

though the output trace is missing but what has happened is that it is hidden behind the input trace (blue, node 1). The amplitudes
are virtually identical so the blue trace completely obscures the red trace.

References
1
rDS(on) can be as little as a few milliohms for specialized high power MOSFETs (Chapters 12 and 13).

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11.7: Summary
JFETs can be used to create both voltage amplifiers and voltage followers. The common source configuration is similar to the BJT's
common emitter configuration. It offers voltage gain with signal inversion. The amplifier can be built upon any of the bias schemes
presented in the preceding chapter. Biasing circuits that made use of a source resistor, such as self bias and combination bias, may
also use swamping. Swamping will decrease available voltage gain but reduce distortion.
The JFET voltage follower, or source follower, is similar to the BJT's emitter follower. It offers a voltage of gain of nearly unity
without inversion, a high input impedance and a low output impedance.
In general, JFETs do not offer as high of a gain as BJTs. The parameter comparable to the BJT's r is the transconductance, g .
′
e m

Further, they tend to offer very high input impedance values compared to BJTs. This is due to using a reverse biased junction
instead of a forward biased junction.
JFETs can also be used in their ohmic region to create voltage-controlled resistances and analog switches. A key parameter in these
applications is the minimum channel resistance, r .
DS(on)

11.7.1: Review Questions

1. What are the functional differences between common source and common drain amplifiers?
2. Compare and contrast common source amplifiers to common emitter amplifiers.
3. Compare and contrast common drain followers to common collector followers.
4. What is the ohmic region?
5. What is an analog switch and how does it function?

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11.8: Exercises
11.8.1: Analysis Problems
1. For the amplifier of Figure 11.8.1, determine Z in and A . I
v DSS = 12 mA, V GS(of f ) = −2 V, V DD = 15 V, R = 220 kΩ, R = 2
G D

kΩ, R = 3.3 kΩ, R = 330 Ω.

L S

2. For the amplifier of Figure 11.8.1, determine Z in and V out .Vin = 50 mV, I
DSS = 15 mA, V GS(of f ) = −3 V, VDD = 20 V, RG =
270 kΩ, R = 2 kΩ, R = 6.8 kΩ, R = 270 Ω.
D L S

Figure 11.8.1
3. For the amplifier of Figure 11.8.2, determine Z and V . V = 60 mV, I
in out in DSS = 10 mA, V GS(of f )
= −3 V, V DD = 20 V, V SS =
−6 V, R = 270 kΩ, R = 2 kΩ, R = 4 kΩ, R = 1.8 kΩ, R
G D L S = 200 Ω. SW

Figure 11.8.2
4. For the amplifier of Figure 11.8.2, determine Z and A . I
in v DSS = 12 mA, V GS(of f ) = −2 V, V DD = 18 V, V SS = −4 V, R = 330
G

kΩ, R = 2.2 kΩ, R = 10 kΩ, R = 3 kΩ, R

D L S SW = 100 Ω.
5. For the amplifier of Figure 11.8.3, determine Z in and A . I
v DSS = 12 mA, V GS(of f ) = −2 V, V
DD = 18 V, VEE = −4 V, R = 390
G

kΩ, R = 2.2 kΩ, R = 1 kΩ, R = 20 kΩ.

D E L

Figure 11.8.3

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6. For the amplifier of Figure 11.8.3, determine Z in and V out .V
in = 70 mV, I DSS = 12 mA, V GS(of f ) = −2 V, V DD = 18 V, V EE =
−4 V, R = 390 kΩ, R = 2.2 kΩ, R = 20 kΩ.
G D L

7. For the circuit of Figure 11.8.4, determine Zin and A . I v DSS = 12 mA, V GS(of f ) = −2 V, V DD = 10 V, R = 220 kΩ, R = 3.3 k
G L

Ω, R S
= 330 Ω.

Figure 11.8.4
8. For the circuit of Figure 11.8.4, determine Zin and V out .Vin = 200 mV, I DSS = 15 mA, V GS(of f ) = −3 V, V DD = 12 V, R = 270
G

kΩ, R = 1.8 kΩ, R = 270 Ω.

L S

9. For the circuit of Figure 11.8.5, determine Zin and V out .Vin = 100 mV, I DSS = 10 mA, V GS(of f ) = −3 V, V DD = 15 V, V SS = −6
V, R = 470 kΩ, R = 4 kΩ, R = 1.8 kΩ.
G L S

Figure 11.8.5
10. For the circuit of Figure 11.8.5, determine Z in and A . I v DSS = 18 mA, V GS(of f )
= −2 V, V DD = 14 V, V SS = −6 V, R = 360 k
G

Ω, R L= 10 kΩ, R = 1 kΩ.
S

11. For the circuit of Figure 11.8.6, determine V out .V in = 100 mV, r DS(on)
= 50 Ω, r DS(of f )
= 1 MΩ, V GS(of f )
= −3 V, V = −6 V,
C

R G = 270 kΩ, R = 6.8 kΩ.

D

12. For the circuit of Figure 11.8.6, determine V out .V in = 100 mV, r DS(on) = 75 Ω, r DS(of f ) = 750 kΩ, V GS(of f ) = −3 V, V = 0 V,
C

R G = 180 kΩ, R = 5.1 kΩ.

D

Figure 11.8.6

11.8.2: Design Challenge Problems

13. Following the circuit of Figure 11.8.2, design an amplifier with a gain of at least 4 and an input impedance of at least 300 kΩ.
R L = 10 kΩ. The JFET has the following parameters: V = −2 V, I
GS(of f ) = 15 mA. Try to use standard resistor values.
DSS

14. Using the circuit of Figure 11.8.4, design a follower with a gain of at least 0.7 and an input impedance of at least 500 kΩ. R = L

1 kΩ. The JFET has the following parameters: V = −3 V, I

GS(of f )
= 20 mA. Try to use standard resistor values.
DSS

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11.8.3: Computer Simulation Problems
15. UtiliZ g manufacturer's data sheets, find devices with the following specifications (typical) and verify them using the
in

measurement techniques presented in the prior chapter. Device 1: V = −2 V, I

GS(of f ) = 15 mA. Device 2: V
DSS = −3 V,
GS(of f )

IDSS = 20 mA.
16. Using the device model from the preceding problem, verify the design of Problem 13.
17. Using the device model from Problem 15, verify the design of Problem 14.

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 CHAPTER OVERVIEW

12: Metal Oxide Semiconductor FETs (MOSFETs)

Learning Objectives
After completing this chapter, you should be able to:
Discuss the functional differences between MOSFETs and JFETs.
Draw and explain a basic DC bias model for a MOSFET.
Graph the transconductance curves for both DE-MOS and E-MOS transistors, and describe their functional differences.
Perform DC bias analysis on various MOSFET circuits.
Explain necessary ESD precautions for MOS devices.

12.1: Introduction
12.2: The DE-MOSFET
12.3: DE-MOSFET Biasing
12.4: The E-MOSFET
12.5: E-MOSFET Data Sheet Interpretation
12.6: E-MOSFET Biasing
12.7: Summary
12.8: Exercises

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available upon request.

1
12.1: Introduction
The MOSFET shares many similarities with the JFET including very low gate current and being modeled as a voltage-controlled
current source. It is also available in N- and P-channel varieties. Unlike the JFET, it has two variations: the depletion-enhancement
mode variant, or DE-MOSFET; and the enhancement-only mode variant, or E-MOSFET. All of the bias types discussed for JFETs
will work for DE-MOSFETs, plus a few others. EMOSFETs, on the other hand, require new biasing prototypes.
For AC analysis, both common source and common drain amplifier topologies may be realized with DE- and EMOSFETs. The
equations for input impedance, voltage gain and the like are generally unchanged from the JFET. E-MOSFETs are also available as
power devices. They have certain advantages over power BJTs, including higher speed and a negative temperature coefficient of
transconductance which means they are less likely to suffer from thermal instabilities such as current hogging.
One item of practical importance is that MOSFETs are very susceptible to ESD (electrostatic discharge) and special precautions
must be taken to prevent accidental damage to the device. Unlike both the JFET and the BJT, the MOSFET does not rely on a PN
junction for its operation. Instead, it uses a charge-based system not unlike a capacitor. The gate is, in fact, insulated from the
channel. For this reason it is sometimes referred to as an IGFET, which stands for Insulated Gate FET. This insulation layer will
lead to very, very high input resistance due to extremely low gate current but also leads to the issue of ESD susceptibility.

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12.2: The DE-MOSFET
Like the JFET, the DE-MOSFET is based around the idea of modulating current flow through the drain-source channel by
generating a depletion layer from a gate-source voltage. It achieves this through an entirely different process, though. To
understand how the device is constructed, a simplified functional drawing of an N-channel DEMOSFET is shown in Figure 12.2.1.

Figure 12.2.1: DE-MOSFET internal structure.

Here we see the N-type channel sitting on a P substrate. Drain and source leads are attached to either end. Above the channel is a
very thin insulating layer (silicon dioxide is one possibility). Above this we have a metalization to which the gate terminal is
attached. Note that there is no PN junction involved with the gate. To this we shall add external bias sources and limiting resistors,
as shown in Figure 12.2.2.

Figure 12.2.2: DE-MOSFET bias with electron flow.

The dashed lines represent electron current flow as in our previous device analyses. A positive supply, V , is attached to the drain
DD

via a limiting resistor. A second supply, V , is attached to the gate. Gate current can be approximated as zero, so V = V . If
GG GS GG

VGS is zero, a certain amount of current will flow through the channel based on the channel's physical parameters and the applied
drain-source potential. For relatively low values of V , the channel will behave somewhat like a resistance. This is the same
DS

ohmic region as seen with the JFET. As V increases, the channel will saturate and begin to behave like a constant current source.
DS

If VDS is brought too high, the drain current increases sharply as the device enters the breakdown region. The general behavior
mimics that of a JFET. Note that the current moves laterally, across the device, so this type of construction is referred to as a lateral
MOSFET.
If V is set to a modest negative voltage, a depletion region will develop inside the channel. Basically, the gate is acting like one
GS

plate of a capacitor, the channel like the other plate, and the insulating layer is the dielectric. Just like a capacitor, the negative
charge on the gate “plate” leads to an equivalent positive charge on the channel “plate”. As the channel is made of N-type material,
this action creates a region devoid of free charges, hence a depletion region. This depletion region will lead to pinch-off sooner, and
thus a lower current in the saturation region. The more negative V GS is made, the greater the depletion region and the lower the
corresponding drain current. Eventually, if V is brought negative enough, the channel will be blocked and no drain current will
GS

flow. This voltage is referred to as VGS(of f )(again). The current produced when V = 0 V is likewise referred to as I
GS . This
DSS

mode of operation is referred to as depletion mode because of the depletion region that is created.
What makes the DE-MOSFET distinct from the JFET is what happens when V > 0 volts. In a JFET, this would forward bias the
GS

junction and control would be lost. Here, however, a positive V GS simply reverses the polarities associated with the gate and
channel “plates”. Thus, a positive V enhances channel conductivity and drain current increases as V is brought more positive.
GS GS

This mode of operation is called enhancement mode. This also means that I DSSis no longer the maximum drain current of which
the device is capable. A characteristic curve is shown in Figure 12.2.3, below.

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 Figure 12.2.3: Characteristic curve for DEMOSFET (note: this uses −V /V for the normalized voltage so that the
GS GS(of f )

quadrants do not appear reversed compared to a typical device curve).

This curve is essentially the same curve as presented for the JFET with the exception that it extends into the first quadrant. This
makes the DE-MOSFET a unique device in that it can operate in two different quadrants.
The device equation for operation when V DS > VP is also the same, but with an extended range for V GS :
2
VGS
ID = IDSS (1 − ) (12.2.1)
VGS(of f )

Where
VGS is the gate-source voltage (V GS(of f ) ≤ VGS ≤ VGS(max) ) ,
ID is the drain current,
IDSS is the maximum current,
VGS(of f ) is the turn-off voltage.
VGS(max) may be found on a data sheet. Above this voltage the insulating layer will be damaged and the device will cease to
function properly. A typical value for this might be in the range of 20 to 30 volts. The trick is that given the very small gate current,
even a simple electrostatic discharge can damage the device. It is very easy to develop hundreds of volts static on the human body.
In fact, it is generally not noticeable until the potential reaches a few thousand volts (as in body hair standing up). The consequence
of this is that simply picking up the device could destroy it.1
There are a couple different ways of dealing with this issue. The first way is to add back-to-back Zener diodes across the device
during its manufacture. The problem with this is that the diode leakage current will be greater than the gate current and this
degrades performance. The other technique is to prevent the charge from getting to the device in the first place. For example, the
MOSFET can be shipped in conductive plastic (not to be confused with ordinary plastic or polystyrene foam). Some devices are
shipped with a metal shorting that encompasses all of the leads. Also, during manufacture or prototyping, environmental controls
are established to minimize the creation of static charges, optimal humidity being important as one example. Workers who handle
devices may work on special conductive mats or wear wrist straps that are attached to ground. These items are only mildly
conductive, that is, of high resistance, as it would not be safe to electrically ground a human working in an electrical lab. The
devices are conductive enough to bleed off static charge but not so conductive as to present a shock hazard. Once installed on the
circuit board, normal ESD precautions apply. As the device's characteristic equation has not changed, many of the items derived for
the JFET still apply to the DE-MOSFET. This includes the transconductance equation plot found in Chapter 10.
As the transconductance equation is unchanged with the exception of an extended range for VGS , the definition for gm0 is also
unchanged.
2IDSS
gm0 = − (12.2.2)
VGS(of f )

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 VGS
gm = gm0 (1 − ) (12.2.3)
VGS(of f )

It is worth noting that g no longer represents the maximum device transconductance because
m0 IDSS no longer represents the
maximum drain current as seen in Figure 12.2.3. To illustrate it another way,
−−−−−
ID
gm = gm0 √ (12.2.4)
IDSS

It is very important to watch the sign of VGS in Equation 12.2.3 . In enhancement mode, a positive VGS will lead to a gm greater
than g due to the double negative.
m0

Figure 12.2.4: DE-MOSFET schematic symbols. N-channel (left) and P-channel (right).
The schematic symbols for the DE-MOSFET are shown in Figure 12.2.4. As is the norm, the arrow points in the direction of N
material, with the central vertical bar representing the channel. The arrow is attached to the substrate. In some devices this is
brought out of the packaging as a fourth lead although in many it is simply tied back to the source terminal as shown here. Finally,
note how the gate terminal is not drawn connected to the body of the device, emphasizing its isolated nature.

References
1
Which brings to mind the old question of what to store a universal solvent in.

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12.3: DE-MOSFET Biasing
As the characteristic equations of the JFET and DE-MOSFET are the same, the DC biasing model is the same. Consequently, the
DE-MOSFET can be biased using any of the techniques used with the JFET including self bias, combination bias and current
source bias as these are all second quadrant biasing schemes (i.e., have a negative V ). The self bias and combination bias
GS

equations and plots from Chapter 10 may be used without modification. The DE-MOSFET also allows first quadrant operation so a
couple of new biasing forms become available: zero bias and voltage divider bias. In reality, both are variations on constant voltage
bias but which utilize the first quadrant.

12.3.1: Zero Bias

Zero bias is unique. In some ways it can be thought of as a cross between self bias and constant voltage bias. Like self bias, it does
not require a second DC source for the gate or source terminal. Like constant voltage bias, there is no need for a source resistor,
R . A prototype of zero bias is shown in Figure 12.3.1. There is no question that it is a minimal parts-count circuit.
S

Figure 12.3.1: Zero bias prototype.

Zero bias is so named because it operates at V = 0 V. Recall that the gate current is ideally zero, thus there is no drop across R
GS G

and V = 0 V as a consequence. The source is tied directly to ground, therefore V must equal 0 V. As V doesn't change, this
G GS GS

can be thought of as a form of constant voltage bias. The interesting bit is that when an AC signal is applied to the gate, its negative
portion will pull the MOSFET down into depletion mode and the positive portion will push the operation into enhancement mode.
Because the device can operate in this fashion, conducting current while straddling zero, so to speak, DE-MOSFETs are sometimes
referred to as normally on devices.
Determining the operating point for zero bias is startlingly easy. Because V = 0 V, I must equal I
GS D and g must equal g .
DSS m m0

Like all constant voltage biasing schemes, though, Q point stability is not very good. Another point to notice is that, as there is no
source resistor, this bias is only applicable to non-swamped common source amplifiers. It cannot be used with a source follower or
swamped amplifier (if a small swamping resistor is inserted into the source, technically the circuit can be classified as self bias,
although the AC signal may still push operation into enhancement mode).

Example 12.3.1

Determine I , V and g
D D m0 for the circuit shown in Figure 12.3.2. Assume I DSS = 12 mA and V
GS(of f )
= −3 V.

Figure 12.3.2: Circuit for Example 12.3.1.

By inspection, as this is zero bias ID = IDSS , and therefore I
D = 12 mA. Using KVL and Ohm's law we can find V . D

VD = VDD − ID RD

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 VD = 20V − 12mA × 1kΩ

VD = 8V

2IDSS
gm0 = −
VGS(of f )

2 × 12mA
gm0 = −
−3V

gm0 = 8mS

12.3.2: Voltage Divider Bias

Voltage divider bias is a form of constant voltage bias that operates in enhancement mode. A prototype circuit is shown in Figure
12.3.3. Note that the source terminal is connected directly to ground. This is important. If this was not the case, this would be a

form of combination bias (basically shifting the V supply up to ground and then shifting the gate voltage from ground up to a
SS

positive V to maintain the same differential voltage). As such, it would be operating in depletion mode.
SS

Figure 12.3.3: Voltage divider bias prototype.

The voltage divider comprised of R and R will establish a DC bias potential on the gate. As the source is at ground,
1 2

VGS =V G=V R2. Given that V must be positive, then V must be positive, and enhancement mode operation is a given.
DD GS

The most direct way to handle this is to determine the voltage divider potential and use either the characteristic equation (Equation
10.2.1) or associated graph to determine the drain current. Once I is found, the drain-source voltage may be found via the
D

standard Ohm's law/KVL route.

Before continuing, note that the values of the divider resistors can be very high without creating biasing problems (unlike the BJT
version of voltage divider bias). This is because the gate current is so small that even when using megohm values for the divider,
the loading caused by the gate will not be noticeable.

Example 12.3.2

For the circuit of Figure 12.3.4, determine I and V . Assume I

D D DSS =2 mA and V
GS(of f )
= −6 V.

Figure 12.3.4: Circuit for Example 12.3.2.

The voltage divider will yield VGS .
R2
VGS = VDD ( )
R1 + R2

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 2.5M Ω
VGS = 20V ( )
10M Ω + 2.5M Ω

VGS = 4V

Use Equation 10.2.1 to find I . D

2
VGS
ID = IDSS (1 − )
VGS(of f )

2
4V
ID = 2mA (1 − )
−6V

ID = 5.56mA

Use KVL and Ohm's law to find V . D

VD = VDD − ID RD

VD = 20V − 5.56mA × 1.8kΩ

VD = 9.99V

Alternately, using the curve of Figure 12.2.3, we would first find the normalized gate-source voltage which is 4 V/6 V or 0.667
(note that the curve plots −V /V GS so that the quadrants do not appear reversed). From this the normalized drain
GS(of f )

current, I /I
D DSS, may be determined to be approximately 2.8, yielding a drain current of 5.6 mA.

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12.4: The E-MOSFET
The E-MOSFET is available in both low power and high power versions. It operates in enhancement mode (first quadrant) only.
The construction of the low power version is similar to that of the DE-MOSFET but with one important distinction. A simplified
cross-section of an N-channel E-MOSFET is shown in Figure 12.4.1.

Figure 12.4.1: E-MOSFET internal structure.

In the E-MOSFET, the P material extends up through the channel and to the gate insulating layer. This has the effect of preventing
current flow with negative gatesource voltages applied. Consequently, E-MOSFETs are sometimes referred to as normally off
devices. In fact, the E-MOSFET will not conduct if V is zero, or even for small positive values of V . The P and N materials
GS GS

functionally create energy hills or barriers that prevent current flow through the channel. This can be compared to an NPN BJT that
has an open base terminal: no collector current would flow (unless the collector-emitter voltage exceeded the breakdown limit).
To understand how the E-MOSFET functions, refer to Figure 12.4.2. This diagram shows the device with positive drain and gate
supplies attached to it through limiting resistors. The dashed lines indicate electron current flow. As with the DE-MOSFET, the
gate can be seen as one plate of a capacitor while the P material serves as the other plate. A positive voltage on the gate will lead to
a negative charge on the P material side. If the charge is large enough, all of the holes in the P material can be filled leaving the
portion of the material situated near the isolation layer neutral (neither P nor N). Any further increase in gate voltage injects more
negative charge into this region, this making it behave like N material. This is called an N-type inversion layer and it allows a path
for current to flow. The more positive we make the gate voltage, the greater the effect, and the greater the current.

Figure 12.4.2: E-MOSFET bias with electron flow.

The voltage where the current begins to flow is called the threshold voltage and is usually denoted as V , although it is
GS(th)

sometimes shortened to V or just V . Like both the JFET and DE-MOSFET, the E-MOSFET drain curve family exhibits three
th t

characteristic regions: the ohmic or triode region, the constant current or saturation region, and the breakdown region.
The characteristic equation for the E-MOSFET operating in its constant current region is given below. Like the other FETs
examined, this is a square-law device.
2
ID = k(VGS − VGS(th) ) (12.4.1)

Where
ID is the drain current,
VGS is the gate-source voltage (VGS(th) ≤ VGS ≤ BVGS ) ,
VGS(th) is the the threshold voltage,
k is a device parameter (a constant, units of amps/volt or siemens/volt).
2

The derivative of Equation 12.4.1 yields the transconductance.

dID
gm = = 2k(VGS − VGS(th) ) (12.4.2)
dVGS

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Equation 12.4.1 is plotted in Figure 12.4.3. The normalized gate-source voltage is V /V GS and the normalized drain current is
GS(th)

the ratio of I to the current generated when V

D GS is twice V . This curve is reminiscent of the characteristic curve of a BJT.
GS(th)

First, they are both in the first quadrant. Second, both curves exhibit an increasing positive slope. Finally, the curves don't begin to
“take off” until some specific turn-on voltage is reached. In the case of the BJT, that voltage is approximately 0.7 V for a silicon
device. For the E-MOSFET, that voltage is V . Obviously though, the MOSFET curve does not increase as rapidly as the BJT
GS(th)

curve.

Figure 12.4.3: Characteristic curve for E-MOSFET.

The power E-MOSFET utilizes a different construction from low power MOSFETs and offers certain advantages over power BJTs
including very fast switching speed and lower drive current demands. Consequently, they tend to be favored over BJTs in high
power, high speed switching applications such as switching power supply regulators, DC-to-DC converters and class D amplifiers
(Chapter 14). These devices also exhibit extremely low r values, in some cases just a few milliohms. There are different
DS(on)

methods of construction, the most recent being the trench style. A cutaway view is shown in Figure 12.4.4.

Figure 12.4.4: Construction of power Trench E-MOSFET.

A power E-MOSFET is made of a large number of cells, each featuring the U-shaped gate “trench” (an earlier style used a V-
shaped trench). Note the location of the drain, now opposite of the gate and source. The advantage here is that the current flows
vertically rather than laterally. This results in a much lower r DS(on) and considerably greater current capacity. The characteristic
curve still echoes that of Figure 12.4.3 although it tends to be steeper when compared to low power devices.

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12.5: E-MOSFET Data Sheet Interpretation
A data sheet for an E-MOSFET, the FDMS86180, is shown in Figure 12.5.1. This is an N-channel, high power device using trench
construction.

Figure 12.5.1a : FDMS86180 data sheet. Used with permission from SCILLC dba ON Semiconductor.
One of the first things that might jump out is the “100% RoHS Compliant” green leaf logo in the upper center, meaning that the
device meets the Restriction of Hazardous Substances directive. The device comes in the flat, multi-pin Power 56 package and
features an r
DS(on) of just a few milliohms. Continuous current capability at room temperature is 151 amps with a pulsed current
maximum of 775 amps. In Figure 12.5.1b we find a breakdown voltage of 100 volts and an I DSS
of only 1 μ A. Recall that this is a
normally off device, and thus I DSS
represents a leakage current. Continuing, V varies between 2.0 and 4.0 volts, with 3.2
GS(th)

volts being typical. The forward transconductance, g (here referred to as g ) is 144 siemens at a drain current of 67 amps. This
m FS

is orders of magnitude greater than what we might see with small signal devices. Turn-on and turn-off times are measured in the
tens of nanoseconds, verifying the high speed switching ability of the device.

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 Figure 12.5.1b : FDMS86180 data sheet (cont).
A series of performance graphs are found in Figure 12.5.1c. In the upper left is a section of drain curves showing the ohmic region
through V = 5 V. The plot directly below this shows the increase in r
DS DS(on)
as temperature rises. There is about a three-fold
variation across the temperature range. At lower left is the characteristic curve variation. Note that the curves are less steep as
temperature increases, showing a decrease in g and thus, verifying a negative temperature coefficient of transconductance.
m

12.5.2 https://eng.libretexts.org/@go/page/25330
 Figure 12.5.1c : FDMS86180 data sheet (cont).

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12.6: E-MOSFET Biasing
As the E-MOSFET operates only in the first quadrant, none of the biasing schemes used with JFETs will work with it. First, it
should be noted that for large signal switching applications biasing is not much of an issue as we simply need to confirm that there
is sufficient drive signal to turn the device on. For linear amplifiers we can use variations on constant voltage bias such as voltage
divider bias, or on drain feedback bias.

12.6.1: Voltage Divider Bias

Voltage divider bias is reminiscent of the divider circuit used with BJTs. Indeed, the N-channel E-MOSFET requires that its gate be
higher than its source, just as the NPN BJT requires a base voltage higher than its emitter. The major differences between the two
are that the E-MOSFET's input gate current is negligible compared to base current and that the gate-source voltage will be most
likely higher than the 0.7 volt drop seen across the base-emitter junction. Also, the gate-source voltage will not be locked to a
specific voltage but will vary depending on the remainder of the circuit.

Figure 12.6.1: Voltage divider bias for E-MOSFET.

The prototype for the voltage divider bias is shown in Figure 12.6.1. In general, the layout it is the same as the voltage divider bias
used with the DE-MOSFET. The resistors R and R set up the divider to establish the gate voltage. As the source terminal is tied
1 2

directly to ground, this means that V = V . The potential across R needs to be set above V
GS G 2 GS(th)
for proper operation in
accordance with Equation 12.4.1. Knowing the value of V , either the characteristic equation or the corresponding normalized
G

drain current plot can be used to determine the drain current. The only factor missing is the device constant, k . This can be
computed for any particular device based on the I ,V
D(on) coordinate pair specified in the data sheet (or measured in lab). An
GS(on)

example is shown in Figure 12.6.2.

Figure 12.6.2: Coordinate pair on E-MOSFET curve.

The constant k is found via a rearrangement of Equation 12.4.1:
ID(on)
k =
2
(VGS(on) − VGS(th) )

This value can then be used for other biasing points.

Example 12.6.1

For the circuit and matching device curve of Figure 12.6.3, find I and V
D DS .

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 Figure 12.6.3a: Circuit for Example 12.6.1.

Figure 12.6.3b: Device curve for Example 12.6.1.

First find the value of k :
ID(on)
k =
2
(VGS(on) − VGS(th) )

6mA
k =
2
(3V − 2V )

2
k = 6mA/V

Now determine the gate voltage:

R2
VG = VDD
R1 + R2

1.5M Ω
VG = 25V
10M Ω + 1.5M Ω

VG = 3.26V

The source is grounded so V GS = VG .

2
ID = k(VGS − VGS(th) )

2 2
ID = 6mA/ V (3.26V − 2V )

ID = 9.54mA

VDS = VDD − ID RD

VDS = 25V − 9.54mA × 1.8kΩ

VDS = 7.83V

In closing, note that it is possible to decouple the voltage divider using the same method employed with BJTs in Figure 7.3.11. Very
large value resistors are available in only a limited variety of sizes so this technique has an added benefit. The divider resistors can
use more convenient sizes because R and R will not set the input impedance; it will be set by the decoupling resistor.
1 2

12.6.2: Drain Feedback Bias

Drain feedback bias utilizes the aforementioned “on” operating point from the characteristic curve. The idea is to establish a drain
current via an appropriate selection of the drain resistor and power supply. The prototype of the drain feedback circuit is shown in

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Figure 12.6.4.

Figure 12.6.4: Drain feedback bias prototype.

This is relatively simple layout using few components. The key to understanding its operation is the KVL summation:

VDD = VR + VR + VGS
D G

VDD = ID RD + IG RG + VGS

Gate current is negligible which means that

VDD = ID RD + VGS

and also

VDS = VGS

Therefore,
VGS = VDS = VDD − ID RD (12.6.1)

Equation 12.6.1 can be used as the basis for the design of the bias circuit.

Example 12.6.2

Utilizing the prototype of Figure 12.6.4 , determine values for R D and RG such that the drain current is 8 mA. Assume
VDD = 20 V, I D(on)= 5 mA at V GS(on)=4 V, and V
GS(th) = 2.5 V.

First find the value of k :

ID(on)
k =
2
(VGS(on) − VGS(th) )

5mA
k =
2
(4V − 2.5V )

2
k = 2.22mA/V

Now determine the required V GS to obtain 8 mA of drain current by rearranging Equation 12.4.1.
2
ID = k(VGS − VGS(th) )

−−
−
ID
VGS = VGS(th) + √
k

−−−−−−−−−−
8mA
VGS = 2.5V + √
2
2.22mA/V

VGS = 4.4V

And finally,

VGS = VDS = VDD − ID RD

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 VDD − VGS
RD =
ID

20V − 4.4V
RD =
8mA

RD = 1.95kΩ

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12.7: Summary
There are two types of MOSFETs: the depletion-enhancement or DE-MOSFET and the enhancement-only or E-MOSFET. Both
devices are constructed using an insulated gate instead of a PN junction and both devices exhibit a square-law characteristic curve.
Like the JFET, MOSFETs are modeled as voltage-controlled current sources. Both devices show very, very small gate currents due
to the insulated gate. They are static sensitive and precautions must be taken when handling them to avoid damage from ESD.
The DE-MOSFET exhibits the same characteristic curve as the JFET, however, the curve extends into the first quadrant
(enhancement mode). Consequently, I DSS is no longer the largest drain current possible, but rather, represents a middle ground.
The DE-MOSFET can utilize all of the bias prototypes that are used with JFETs, including self bias, constant current bias and
combination bias. Due to its dual quadrant capability, other biasing types are also possible including zero bias and voltage divider,
both of which are variations on constant voltage bias.
The E-MOSFET operates in the first quadrant only (enhancement mode). Compared to the DE-MOSFET, its characteristic curve is
shifted positive such that VGS(of f )
is now V GS(th)
, and I
DSS signifies the off-state leakage current. E-MOSFETs are available in
both low power and high power variants. The high power versions utilize an alternate internal structure that allows drain current to
flow vertically rather than horizontally. This results in very high current carrying ability and very low values for r .
DS(on)

12.7.1: Review Questions

1. What are the differences between JFETs and MOSFETs?
2. What are the differences between DE-MOSFETs and E-MOSFETs?
3. Why are MOSFETs sometimes referred to as “Insulated Gate” or IGFETs?
4. How does the DC bias model of the MOSFET compare to that of the BJT?
5. What biasing circuits are available for use with the DE-MOSFET?
6. What biasing circuits are available for use with the E-MOSFET?
7. What is “trench” construction and where is it used?
8. Explain typical precautions taken when handling MOSFETs and why they are necessary.

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12.8: Exercises
12.8.1: Analysis Problems
1. For the circuit of Figure 12.8.1, determine I , V and V . I
D G D DSS = 20 mA, V GS(of f ) = −6 V, V DD = 15 V, R = 470 kΩ,
G RS =
1.2 kΩ, R = 1.8 kΩ.
D

2. For the circuit of Figure 12.8.1, determine I , V

D DS and V . I
D DSS = 20 mA, V GS(of f ) = −5 V, V DD = 30 V, R = 560 kΩ, R =
G S

420 Ω, R = 1.5 kΩ.

D

Figure 12.8.1
3. For Figure 12.8.2, determine I , V and V . I
D G D DSS = 15 mA, V DD = 25 V, V GS(of f ) = −3 V, V SS = −6 V, R = 820 kΩ, R = 2
G S

kΩ, R = 3.6 kΩ.

D

4. For the circuit of Figure 12.8.2, determine I , V

D DS and V . I
D DSS = 18 mA, V GS(of f ) = −3 V, V DD = 30 V, VSS = −9 V, RG =
910 kΩ, R = 1.2 kΩ, R = 2.7 kΩ.
S D

5. For the circuit of Figure 12.8.3, determine I , V and V . I

D G D DSS = 12 mA, V GS(of f ) = −4 V, V DD = 35 V, R = 680 kΩ, R
G D =
1.8 kΩ.

Figure 12.8.2
6. For the circuit of Figure 12.8.3, determine I , V
D DS and V . I
D DSS = 8 mA, V GS(of f ) = −2 V, V DD = 30 V, R = 750 kΩ,
G RD =
2.7 kΩ.

Figure 12.8.3
7. For the circuit of Figure , determine I , V and V . I
12.8.4 D G D DSS = 8 mA, VGS(of f ) = −4 V, VDD = 30 V, R1 = 2.7 MΩ, R2 =
110 kΩ, R = 470 Ω.
D

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8. For the circuit of Figure 12.8.4, determine I , V
D DS and V . I
D DSS = 12 mA, V GS(of f ) = −6 V, V DD = 20 V, R1 = 2 MΩ, R2 =
100 kΩ, R = 680 Ω.
D

9. For the circuit of Figure 12.8.5, determine I , V and V . I

D G D D(on) = 8 mA, VGS(on) = 5 V, V GS(th) = 3 V, V DD = 30 V, R = 2 M
1

Ω , R = 330 kΩ , R
2 D = 1.2 kΩ.
10. For the circuit of Figure 12.8.5, determine I , V
D DS and V . ID D(on) = 12 mA, V GS(on) = 6 V, V GS(th) = 2.5 V, V DD = 25 V, R 1

= 1.5 MΩ, R = 470 kΩ, R = 680 Ω.

2 D

Figure 12.8.4

Figure 12.8.5
11. For the circuit of Figure 12.8.6, determine I , V and V . I
D G D DSS = 12 mA, V GS(of f )
= 2 V, V DD = −25 V, R = 470 kΩ, R =
G S

800 Ω, R = 1.8 kΩ.

D

12. For the circuit of Figure 12.8.6, determine I and V . I

D D DSS = 10 mA, V GS(of f )
= 2 V, V DD = −20 V, R = 560 kΩ, R = 680
G S

Ω, R D = 1.5 kΩ.

Figure 12.8.6
13. For the circuit of Figure 12.8.7, determine I , V and V . I
D G D DSS = 14 mA, V GS(of f )
= 3 V, VDD = −25 V, V SS = 6 V, R = 780
G

kΩ, R = 2 kΩ, R = 3.3 kΩ.

S D

12.8.2 https://eng.libretexts.org/@go/page/34254
 Figure 12.8.7
14. For the circuit of Figure 12.8.7, determine I and V . I
D D DSS = 16 mA, V GS(of f )
= 3.5 V, V DD = −20 V, V SS = 7 V, R = 1 MG

Ω, R S = 1.5 kΩ, R = 2.2 kΩ.

D

15. For the circuit of Figure 12.8.8, determine I and V . I

D D DSS = 11 mA, V GS(of f )
= 2 V, V DD = −24 V, R = 750 kΩ, R
G D = 1.2
kΩ.
16. For the circuit of Figure 12.8.8, determine I and V . I
D D DSS = 9 mA, V GS(of f )
= 3 V, V DD = −18 V, R = 430 kΩ, R
G D = 910
Ω.

Figure 12.8.8

12.8.2: Design Problems

17. Using the circuit of Figure 12.8.1, determine a value for R to set I to 4 mA. I
S D DSS = 10 mA, V GS(of f ) = −2 V, V DD = 18 V,
RG = 470 kΩ, R = 1.5 kΩ.
D

Figure 12.8.9
18. For the circuit of Figure 12.8.9, determine R and R to set I = 10 mA. I
D G D D(on) = 15 mA, V GS(on) = 6 V, V GS(th) = 2 V, V DD

= 20 V.
19. For the circuit of Figure 12.8.9, determine R and R to set I = 15 mA. I
D G D D(on)
= 10 mA, V GS(on)
= 5 V, V GS(th)
= 2 V, V DD

= 25 V.

12.8.3: Challenge Problems

20. Using the circuit of Figure 12.8.2, determine values for R , R and V
D S SS to set I to 5 mA and V to 20 V. I
D D DSS = 15 mA,
V = −3 V, V
GS(of f ) DD = 30 V, R = 560 kΩ.
G

21. Using the circuit of Figure 12.8.10, determine values for R to set V to 15 V. I
D D DSS = 10 mA, VGS(of f ) = 3 V, VSS = 25 V,
RG = 680 kΩ.

Figure 12.8.10

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 Figure 12.8.11: Comic courtesy of xkcd.com

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 CHAPTER OVERVIEW

13: MOSFET Small Signal Amplifiers

Learning Objectives
After completing this chapter, you should be able to:
Draw and explain a basic AC model for a MOSFET.
Analyze basic MOSFET amplifiers for voltage gain, input impedance and output impedance.
Analyze basic MOSFET voltage followers for voltage gain, input impedance and output impedance.

13.1: Introduction
13.2: MOSFET Common Source Amplifiers
13.3: MOSFET Common Drain Followers
13.4: Summary
13.5: Exercises

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request.

1
13.1: Introduction
MOSFETs can be used to create both common source voltage amplifiers and common drain voltage followers (i.e., source
followers). Both circuits offer the potential for very high input impedance due to the extremely low gate current MOSFETs provide.
As with JFET amplifiers, at higher frequencies input capacitance dominates and reduces the input impedance. Not all bias
prototypes lend themselves to all possible AC circuits. For example, zero bias for a DE-MOSFET is not suitable for followers or
swamped amplifiers as it lacks a source resistor. The same is true for voltage divider biasing used with both DE- and E-MOSFETs.
These biasing schemes are suitable for non-swamped amplifiers, though.
In general, MOSFET amplifiers tend to have good high frequency performance, offer low noise and exhibit low distortion with
modestly sized input signals. Compared to BJTs, their voltage gain magnitude is lower.
A key parameter in determining gain is the device's transconductance, g . Transconductance varies widely depending on the kind
m

of MOSFET used. A small signal DE-MOSFET may exhibit a transconductance of just a few millisiemens. In contrast, a high
power E-MOSFET may exhibit a transconductance of over 100 siemens.

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13.2: MOSFET Common Source Amplifiers
Before we can examine the common source amplifier, an AC model is needed for both the DE- and E-MOSFET. A simplified
model consists of a voltage-controlled current source and an input resistance, r . This model is shown in Figure 13.2.1. The
GS

model is essentially the same as that used for the JFET. Technically, the gate-source resistance is higher in the MOSFET due to the
insulated gate, and this is useful in specific applications such as in the design of electrometers, but for general purpose work it is a
minor distinction. The impedance associated with the current source is not shown as it is typically large enough to ignore.
Similarly, the device capacitances are not shown. It is worth noting that the capacitances associated with small signal devices might
be just a few picofarads, however, a power device might exhibit values of a few nanofarads.

Figure 13.2.1: AC device model for MOSFETs.

As the device model is the same for both DE- and E-MOSFETs, the analysis of voltage gain, input impedance and output
impedance will apply to both devices. The only practical differences will be how the transconductance is determined, and circuit
variations due to the differing biasing requirements which will effect the input impedance. In fact, there will be a great uniformity
between JFET-based circuits and DE-MOSFET circuits operating in depletion mode.
An AC equivalent of a swamped common source amplifier is shown in Figure 13.2.2. This is a generic prototype and is suitable for
any variation on device and bias type. Ultimately, all of the amplifiers can be reduced down to this equivalent, occasionally with
some resistance values left out (either opened or shorted). For example, if the amplifier is not swamped then r = 0 . Similarly, r
S G

might correspond to a single gate biasing resistor or it might represent the equivalent of a pair of resistors that set up a gate voltage
divider.

Figure 13.2.2: Generic common source amplifier equivalent.

13.2.1: Voltage Gain

In order to derive an equation for the voltage gain, we start with its definition, namely that voltage gain is the ratio of v out to vin .
We then proceed by expressing these voltages in terms of their Ohm's law equivalents. Note that r can also be called r .
L D

vout vL vD
Av = = = (13.2.1)
vin vG vG

−iD rL
Av =
iD rS + vGS

−gm vGS rL
Av =
gm vGS rS + vGS

gm rL
Av = −
gm rS + 1

or, if preferred

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 gm rD
Av = − (13.2.2)
gm rS + 1

This is the general equation for voltage gain. If the amplifier is not swamped then the first portion of the denominator drops out and
the gain simplifies to
Av = −gm rL (13.2.3)

or alternately
Av = −gm rD (13.2.4)

The swamping resistor, r , plays the same role here as it did with both the BJT and JFET. Swamping helps to stabilize the gain and
S

reduce distortion, but at the expense of voltage gain.

13.2.2: Input Impedance

Referring back to Figure 13.2.2, the input impedance of the amplifier will be r in parallel with the impedance looking into the
G

gate terminal, Z . At a minimum this will be r (it is somewhat higher when swamped but this can be ignored in most
in(gate) GS

cases). At low frequencies r is very large, perhaps as high as 10 ohms. In most practical circuits, r will be much lower,
GS
12
G

hence
Zin = rG || rGS ≈ rG (13.2.5)

It is important to reiterate that r is the equivalent resistance seen prior to the gate terminal that is seen from the vantage point of
G

V . In the case of self bias, combination bias, zero bias and constant current bias, this will be the single biasing resistor R . For
in G

simple voltage divider biasing, r will be the parallel combination of the two divider resistors (i.e., R ||R ). For decoupled voltage
G 1 2

divider biasing, as shown in Figure 13.2.3, r will be the decoupling resistor (i.e., R ) that is connected between the divider and
G 3

the gate. This is because the divider node is bypassed to ground via a capacitor. Finally, for drain feedback biasing, r is the G

Millerized R that bridges the drain and gate.

G

Figure 13.2.3: Decoupled voltage divider.

13.2.3: Output Impedance

The derivation of output impedance is unchanged from the JFET case. From the perspective of the load, the output impedance will
be the drain biasing resistor, R , in parallel with the internal impedance of the current source within the device model. R tends to
D D

be much lower than this, and thus, the output impedance can be approximated as R . D

Therefore we may state

Zout = rmodel || RD ≈ RD (13.2.6)

At this point, a variety of examples are in order to illustrate some of the myriad combinations.

Example 13.2.1

For the amplifier in Figure 13.2.4, determine the input impedance and load voltage. V = 20 mV, Vin DD = 20 V, R = 1 MΩ,
G

R = 1.8 kΩ, R
D SW = 20 Ω, R = 400 Ω, R = 12 kΩ, I
S L DSS= 40 mA, V = −1 V.
GS(of f )

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 Figure 13.2.4: Circuit for Example 13.2.1.
This is a swamped common drain amplifier utilizing self bias. Z in can be determined via inspection.

Zin = Zin(gate) || RG

Zin ≈ 1M Ω

To find the load voltage we'll need the voltage gain, and to find the gain we'll first need to find g m0 .
2IDSS
gm0 = −
VGS(of f )

80mA
gm0 = −
−1V

gm0 = 80mS

The combined DC value of R is 420

S Ω , therefore g
m0 RS = 33.6. From the self bias equation or graph this produces a drain
current of 1.867 mA.
−−−−−
ID
gm = gm0 √
IDSS

−−−−−−−−
1.867mA
gm = 80mS √
40mA

gm = 17.3mS

The swamping resistor, r , is 20 Ω. The voltage gain is

S

gm rL
Av = −
gm rS + 1

17.3mS(1.8kΩ||12kΩ)
Av = −
17.3mS × 20Ω + 1

Av = −20.1

And finally

Vload = Av Vin

Vload = −20.1 × 20mV

Vload = 402mV

Computer Simulation
The amplifier of Example 13.2.1 is simulated to verify the results. The circuit is entered into the simulator as shown in Figure
13.2.5. One issue is finding an appropriate DE-MOS device to match the parameters used in the example. The BSS229 proves to

be reasonably close. This device model was tested for I by applying a 20 volt source to the drain and shorting the source and
DSS

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gate terminals to ground in the simulator. The current was just under the 40 mA target. Similarly, a negative voltage was attached to
the gate and adjusted until the drain current dropped to nearly zero in order to determine V . The model's value was just
GS(of f )

under the desired −1 volt. Consequently, we can expect the simulation results to be close to those predicted, although not identical.

Figure 13.2.5: The circuit of Example 13.2.1 in the simulator.

The transient analysis is run next and is shown in Figure 13.2.6. The expected signal inversion is obvious. The peak amplitude is
417 mV, just a few percent higher than the calculated value. At least some of this deviation is due to the model's variation from the
assumed device parameter values.

Figure 13.2.6: Transient analysis simulation for the circuit of Example 13.2.1.
A DC bias check is also performed. The drain current was calculated to be 1.867 mA. This yields an R voltage of a little over 3
D

volts, thus we expect to see a drain voltage of about 17 volts. Similarly, we would expect the source terminal to be sitting at around
700 to 800 mV and the gate at about 0 V.
The results of the DC operating point simulation are shown in Figure 13.2.7. The agreement with the predicted values is quite
good, especially considering that the device model is not a perfect match.

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 Figure 13.2.7: DC bias simulation for the circuit of Example 13.2.1.

Example 13.2.2

For the circuit of Figure 13.2.8, determine the voltage gain and input impedance. Assume VGS(th) = 2 V, ID(on) = 50 mA at
V GS(on)= 5 V.

Figure 13.2.8: Circuit for Example 13.2.2.

First find the value of k :
ID(on)
k =
2
(VGS(on) − VGS(th) )

50mA
k =
2
(5V − 2V )

2
k = 5.56mA/V

This circuit uses power supply decoupling. The voltage drop across the 2 MΩ resistor is small enough to ignore as the current
passing through it is gate current. Therefore the gate voltage is determined by the divider. Also, as the left end of the 2 MΩ
resistor is tied to an AC ground due to the bypass capacitor, it represents the input impedance.

Zin = 2M Ω|| Zin(gate) ≈ 2M Ω

R2
VG = VDD
R1 + R2

5.6kΩ
VG = 24V
47kΩ + 5.6kΩ

VG = 2.56V

The source is grounded so V GS = VG .

2
ID = k(VGS − VGS(th) )

2 2
ID = 5.56mA/ V (2.56V − 2V )

ID = 1.74mA

gm = 2k(VGS − VGS(th) )

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 2
gm = 2 × 5.56mA/ V (2.56V − 2V )

gm = 6.23mS

This amplifier is not swamped so the simplified gain equation may be used.

Av = −gm rD

Av = −6.23mS(3.3kΩ||10kΩ)

Av = −15.5

Example 13.2.3

For the circuit of Figure 13.2.9, determine the voltage gain and input impedance. Assume VGS(of f ) = −0.75 V and IDSS =6
mA.

Figure 13.2.9: Circuit for Example 13.2.3.

This amplifier uses zero bias, therefore I D = IDSS and gm = gm0 .
2IDSS
gm0 = −
VGS(of f )

2 × 6mA
gm0 = −
−0.75V

gm0 = 16mS

This amplifier is not swamped so we may use the simplified equation for voltage gain.

Av = −gm rD

Av = −16mS(2.7kΩ||15kΩ)

Av = −36.6

Finally, for the input impedance we have

Zin = 5M Ω|| Zin(gate) ≈ 5M Ω

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13.3: MOSFET Common Drain Followers
As discussed under the section on JFETs, the common drain amplifier is also known as the source follower. The prototype amplifier
circuit with device model is shown in Figure 13.3.1. As with all voltage followers, we expect a non-inverting voltage gain close to
unity with a high Z and a low Z .
in out

Figure 13.3.1: Common drain (source follower) prototype.

As is usual, the input signal is applied to the gate terminal and the output is taken from the source. Because the output is at the
source, biasing schemes that have the source terminal grounded, such as zero bias and voltage divider bias, cannot be used.

13.3.1: Voltage Gain

The voltage gain equation for the common drain follower is developed as follows: We begin with the fundamental definition that
voltage gain is the ratio of v to v , and proceed by expressing these voltages in terms of their Ohm's law equivalents. The load
out in

is now located at the MOSFET's source, and thus can be referred to as either r or r . L S

vout vS vL
Av = = = (13.3.1)
vin vG vG

iD rL
Av =
iD rL + vGS

gm vGS rL
Av =
gm vGS rL + vGS

gm rL
Av =
gm rL + 1

or, if preferred
gm rS
Av = (13.3.2)
gm rS + 1

If g
m rS ≫ 1 , the voltage gain will be very close to unity; a desired outcome.

13.3.2: Input Impedance

The analysis for source follower's input impedance is virtually identical to that for the common source amplifier. The same
commentary applies regarding the simplification of gate biasing resistors to arrive at the value of r . G

Zin = rG || rGS ≈ rG (13.3.3)

13.3.3: Output Impedance

In order to determine the output impedance, we modify the circuit of Figure 13.3.1 by separating the load resistance from the
source bias resistor. This is shown in Figure 13.3.2.

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 Figure 13.3.2: Source follower output impedance analysis.
Looking back into the source from the perspective of the load we find that the source biasing resistor, RS , is in parallel with the
impedance looking back into the source terminal.

Zout = RS || Zsource

To find Z , note that the voltage at the source is v

source GS and the current entering this node is i . The ratio of the two will yield the
D

impedance looking back into the source.

vGS
Zsource = (13.3.4)
iD

vGS
Zsource =
gm vGS

1
Zsource =
gm

Therefore, the output impedance is

1
Zout = RS || (13.3.5)
gm

Looking at Equation 13.3.5 it is obvious that the higher the transconductance, the lower the output impedance. As noted earlier, a
large transconductance also means that the voltage gain will be close to unity. As a general rule then, a large transconductance is
desired for the source follower.
Time for a few illustrative examples.

Example 13.3.1

For the circuit of Figure , determine the voltage gain and input impedance. Assume
13.3.3 VGS(of f ) = −0.8 V and IDSS = 30
mA.

Figure 13.3.3: Circuit for Example 13.3.1.

This amplifier uses self bias so we need to determine g m0 RS .
2IDSS
gm0 = −
VGS(of f )

2 × 30mA
gm0 = −
−0.8V

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 gm0 = 75mS

The DC source resistance is the 270 Ω biasing resistor resulting in gm0 RS = 16.2. From the self bias equation or graph this
produces a drain current of 2.61 mA.
−−−−−
ID
gm = gm0 √
IDSS

−−−−−−−
2.61mA
gm = 75mS √
30mA

gm = 22.1mS

The voltage gain is

gm rS
Av =
gm rS + 1

22.1mS(270Ω||150Ω)
Av =
22.1mS × (270Ω||150Ω) + 1

Av = 0.68

Finally, for the input impedance we have

Zin = 1.2M Ω|| Zin(gate) ≈ 1.2M Ω

Example 13.3.2

For the circuit of Figure , determine the voltage gain and input impedance. Assume
13.3.4 VGS(of f ) = −2.5 V and IDSS = 80
mA.

Figure 13.3.4: Circuit for Example 13.3.2.

This follower uses a P-channel device with combination bias. Note that the source terminal is toward the top of the schematic.
First, determine g R and the bias factor, k . Then the combination bias equation can be used to determine the drain current.
m0 S

2IDSS
gm0 = −
VGS(of f )

2 × 80mA
gm0 = −
−2.5V

gm0 = 64mS

The DC source resistance is the 1.8 kΩ biasing resistor resulting in g m0 RS = 115.2. The bias factor is V , or 4. The
SS / VGS(of f )

combination bias equation (Equation 10.9) yields I = 6.67 mA.

D

We can now find the transconductance and voltage gain.

−−−−−
ID
gm = gm0 √
IDSS

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 −−−−−−−
6.67mA
gm = 64mS √
80mA

gm = 18.5mS

The voltage gain is

gm rS
Av =
gm rS + 1

18.5mS(1.8kΩ||800Ω)
Av =
18.5mS × (1.8kΩ||800Ω) + 1

Av = 0.91

Lastly, the input impedance is

Zin = 560kΩ|| Zin(gate) ≈ 560kΩ

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13.4: Summary
DE- and E-MOSFET devices may be used to create both common source voltage amplifiers and common drain voltage followers.
The common source amplifiers may be swamped or non-swamped, depending on the bias form used. If the bias type does not
utilize a source resistor, swamping is not available. This includes zero bias for the DE-MOSFET and voltage divider bias for both
the DE- and E-MOSFET.
Like their JFET counterparts, MOSFET common source amplifiers exhibit moderate inverting voltage gain, very high input
impedance and moderate output impedance. The input impedance is a function of the biasing resistor configuration situated in front
of the gate as the impedance looking into the gate itself is very, very high at low frequencies.
The MOSFET common drain followers also behave similarly to the JFET version. Again we see a non-inverting voltage gain
approaching unity, a very high input impedance and a low output impedance. The higher the transconductance is, the closer the
gain will be to unity and the lower the output impedance will be.

13.4.1: Review Questions

1. How well does the MOSFET voltage amplifier compare to its JFET counterpart?
2. How well does the MOSFET source follower compare to its JFET counterpart?
3. What are the practical differences between a voltage amplifier using a DEMOSFET versus using an E-MOSFET ?
4. It has been stated that a source follower cannot be made using a standard zero biased DE-MOSFET. Why is this?
5. It has been stated that a swamped voltage amplifier cannot be made using a standard voltage divider biased E-MOSFET. Why is
this?

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13.5: Exercises
13.5.1: Analysis Problems
1. For the amplifier of Figure 13.5.1, determine Z and A . V
in v in = 20 mV, I DSS = 10 mA, V GS(of f ) = −2 V, V DD = 20 V, R = 750
G

kΩ, R = 2 kΩ, R = 4 kΩ, R = 1 kΩ, R

D L S SW = 200 Ω.
2. For the amplifier of Figure 13.5.1, determine Z and V . V
in out in = 25 mV, I DSS = 15 mA, V GS(of f ) = −2 V, VDD = 22 V, RG =
330 kΩ, R = 2 kΩ, R = 6 kΩ, R = 510 Ω, R
D L S = 220 Ω.
SW

Figure 13.5.1
3. For the circuit of Figure 13.5.2, determine Z in and A . V
v in = 10 mV, I DSS
= 12 mA, V GS(of f )
= −2.5 V, V DD = 26 V, R = 510
G

kΩ, R = 1.2 kΩ, R = 25 kΩ.

D L

4. For the circuit of Figure 13.5.2, determine Z in and V out .V in = 25 mV, IDSS = 15 mA, VGS(of f ) = −1.5 V, VDD = 24 V, RG =
820 kΩ, R = 1 kΩ, R = 12 kΩ.
D L

Figure 13.5.2
5. For the circuit of Figure 13.5.3, determine Z in and V out .V in = 25 mV, I DSS = 8 mA, V GS(of f ) = −3.5 V, V DD = 24 V, R = 1 M
1

Ω , R = 100 kΩ , R
2 D = 800 Ω, R = 10 kΩ.
L

6. For the circuit of Figure 13.5.3, determine Z in and A . V

v in = 10 mV, I DSS = 6 mA, V GS(of f ) = −4 V, V DD = 26 V, R = 2 MΩ,
1

R = 120 kΩ , R
2 D = 1.2 kΩ, R = 15 kΩ.
L

Figure 13.5.3

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7. For the circuit of Figure 13.5.4, determine Z and V . V
in out in = 20 mV, I D(on) = 6 mA at V DS(on) = 3 V, V GS(th) = 2.5 V, V DD =
34 V, R = 1 MΩ, R = 100 kΩ, R = 1 kΩ, R = 10 kΩ.
1 2 D L

8. For the circuit of Figure 13.5.4, determine Z and A . V

in v in = 15 mV, I D(on) = 10 mA at V DS(on) = 4 V, V GS(th) = 2 V, V DD = 30
V, R = 2 MΩ, R = 180 kΩ, R = 1.2 kΩ, R = 15 kΩ.
1 2 D L

Figure 13.5.4
9. For the circuit of Figure 13.5.5, determine Z
in and V out .V in = 200 mV, I DSS = 15 mA, V GS(of f )
= −3 V, V DD = 15 V, R = 910
G

kΩ, R = 10 kΩ, R = 330 Ω.

L S

10. For the circuit of Figure 13.5.5, determine Z in and V out .V in = 200 mV, I DSS = 20 mA, V GS(of f )
= −2 V, V DD = 12 V, R = 1 G

MΩ, R = 1.8 kΩ, R = 220 Ω.

L S

Figure 13.5.5
11. For the circuit of Figure 13.5.6, determine Z in and A . I v DSS = 18 mA, V GS(of f ) = −2 V, V DD = 12 V, V SS = −4 V, R = 680 k
G

Ω, R L = 10 kΩ, R = 1 kΩ.
S

12. For the circuit of Figure 13.5.6, determine Z in and A . I v DSS = 20 mA, V GS(of f ) = −2 V, V
DD = 10 V, VSS = −6 V, R = 2.2 M
G

Ω, R L = 5 kΩ, R = 510 Ω.
S

Figure 13.5.6

13.5.2: Design Problems

13. Following the circuit of Figure 13.5.1, design an amplifier with a gain of at least 5 and an input impedance of at least 500 kΩ.
RL = 10 kΩ. The MOSFET has the following parameters: V = −2 V, I
GS(of f ) = 25 mA. Try to use standard resistor values.
DSS

14. Using the circuit of Figure 13.5.5, design a follower with a gain of at least .75 and an input impedance of at least 1 MΩ. R = 2 L

kΩ. The MOSFET has the following parameters: V = −1.5 V, I

GS(of f ) = 40 mA. Try to use standard resistor values.
DSS

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13.5.3: Challenge Problems
15. For the circuit of Figure 13.5.7, determine Z in and A . I
v DSS = 15 mA, V
GS(of f ) = −2 V.

Figure 13.5.7
16. For the circuit of Figure 13.5.8, determine Z in and A . I
v DSS = 12 mA, V
GS(of f ) = −1.5 V.

Figure 13.5.8

13.5.4: Computer Simulation Problems

17. UtiliZ g manufacturer's data sheets, find devices with the following specifications (typical) and verify them using the
in

measurement techniques presented in the prior chapter.

Device 1: V GS(of f ) = −2 V, IDSS = 25 mA.
Device 2: V GS(of f ) = −1.5 V, I DSS = 40 mA.
18. Using the device model from the preceding problem, verify the design of Problem 13.
19. Using the device model from Problem 17, verify the design of Problem 14.

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 CHAPTER OVERVIEW

14: Class D Power Amplifiers

Learning Objectives
After completing this chapter, you should be able to:
Outline the building blocks of a class D amplifier.
Discuss the advantages and disadvantages of the class D amplifier compared to class A and class B amplifiers.
Explain the concepts of pulse width modulation, shoot-through and dead time.

14.1: Introduction
14.2: Class D Basics
14.3: Pulse Width Modulation
14.4: Output Configurations
14.5: Summary
14.6: Exercises

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1
14.1: Introduction
Much has been written in this text regarding the efficiency of various power amplifier topologies. While class A is known for its
circuit layout simplicity, it is also known for its very low efficiency. Class B and class AB, while more complex than class A,
present serious improvements in efficiency. In spite of these improvements, the family of class B amplifiers can hardly be
considered as exhibiting high efficiency. Although not explicitly covered in this text, class G and H topologies are variations on
class B and attempt to increase efficiency through the use of multiple sets of power supply rails or output devices, and in the
process, tick the complexity up to another level.
The class D amplifier is perhaps the last word in amplifier efficiency. Theoretically with ideal devices, the efficiency of the output
stage approaches 100%. Unlike the other amplifier forms, the transistors used in class D amplifiers never operate in the linear
region; the output devices only operate as a switch, in either saturation or cutoff. High switching speed turns out to be a huge plus
as it plays a major role in efficiency.
The increase in efficiency comes at a considerable increase in circuit complexity, however, for some applications this turns out to
be a very good trade-off. As odd as it might at first seem, the two areas where class D topologies have taken root are at the opposite
ends of the power output spectrum. The first area is perhaps the most obvious, mainly, very high output power amplifiers. An
example might be an amplifier used as part of a large public address system and capable of delivering in excess of 1000 watts into a
loudspeaker. High efficiency does two things here: First, it reduces the waste heat in the amplifier itself, and second, it reduces the
current draw from the AC mains. Both of these are serious issues in a PA system used to fill a stadium or large concert hall as there
may be dozens of such amplifiers comprising the system. As a bonus, improved efficiency also leads to a lighter and small
enclosure because the need for heat sink area and mass will be reduced, as will the size of the AC power supply transformer. These
traits will also reduce production costs and help offset the design complexity cost. The advantages have become so great that, in
recent years, class D designs dominate the high end professional audio power amplifier market as well as the very high power
automotive audio market (here there is another system limitation working in favor of class D, and that's the limited current capacity
of the vehicle's alternator to deliver current).
The second area where class D has found acceptance is for low power portable devices. Examples include personal music devices,
cell phones and hearing aids. Output powers for these applications might range from tens of milliwatts up to a few watts, so excess
heat is generally not a big problem except in the most compact of enclosures. What is a problem, though, is the energy budget.
Unlike a large PA amplifier that might pump out in excess of two horsepower, these portable devices do not have the luxury of
running off of the AC mains with tens or even hundreds of amps of current capacity. Instead, these devices are restricted to battery
power and batteries can only store so much energy. For a given battery capacity, higher efficiency directly translates into longer
battery life. Another way of thinking about this is that, given a higher efficiency, a smaller battery can be used to achieve the same
battery life, and this means that the unit can be both smaller and less expensive. Of course, nothing says that we can't opt for a little
of each.

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14.2: Class D Basics
The key to the high efficiency of class D operation is to only operate the output devices as switches. That is, they are operated at
the extreme ends of the load line, in either cutoff or saturation. The only exception to this rule is when the output device is
transitioning from one state to another. Either BJTs or E-MOSFETs can be used, although for reasons that we shall examine, E-
MOSFETs tend to be preferred in many applications and therefore we shall use them here as a general rule.
To understand the power advantage of class D switching, consider the circuit of Figure 14.2.1. Here we have an E-MOSFET being
driven by a square wave at its gate terminal. The square wave runs from zero to some voltage well above V , sufficient to fully
GS(th)

turn-on the MOSFET.

Figure 14.2.1: A simple MOSFET switch.

At the drain, an inverted square wave appears that ideally runs from +V DD down to zero volts. When the MOSFET is off, no drain
current flows. Therefore, the drop across the drain resistor, R , is zero. Consequently, by KVL, V
D DS
must equal V . When the
DD

gate signal goes high, it turns on the MOSFET causing a large current. Ideally, this current equals V /R and V = 0 V. In
DD D DS

reality, the MOSFET will present some resistance (r DS(on)

) and this essentially creates a voltage divider between the device and

R . Obviously, if r
D DS(on)
≪ R D then we can approximate the low state as zero volts.
In the ideal case, the transistor dissipates no power. Here's why: When the gate is low, the device is off so no current flows.
Although the device voltage is very high, the product of the device's voltage and current is zero. When the gate is high, the
transistor turns on and conducts maximum current, however, the voltage across the device is zero, and the resulting product is zero
once again. Therefore, the device dissipates no power.
The reality of the situation reveals that some power is indeed wasted by the output device. There are two chief culprits: non-zero
turn-on voltage (caused by r DS(on)
for example) and state transitions that are not instantaneous (i.e., the rise and fall times of the
waveforms are not zero). These effects are illustrated in Figure 14.2.2.

Figure 14.2.2: Switching losses.

The rise and fall times are exaggerated for clarity as is the voltage drop across the transistor. The green curve represents the device
current while the blue curve indicates the device voltage. Note that during the on-state the transistor voltage is not zero, although it
is very small. The product of these two curves is the power dissipated by the transistor and is shown in red. In the off-state, no
power is dissipated. In the on-state, a small amount of power is dissipated due to the device's on-voltage. Power spikes also occur at
the state transitions as neither the current nor the voltage are at zero.
The area under the red curve represents the total power dissipated by the output transistor. In order to minimize this loss and
maximize the efficiency, we would like as low of an r DS(on)
as possible along with very fast switching speeds. As power
EMOSFETs tend to switch faster than their BJT counterparts, this presents a compelling argument for their use. Further, large
power E-MOSFETs may exhibit r values of just a few milliohms, guaranteeing relatively small on-state losses (compared to
DS(on)

load power) even with drain currents of several tens of amps.

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14.3: Pulse Width Modulation
Clearly, class D presents the possibility of minimal wasted power and high efficiency. We are now left with the problem of how to
turn a series of pulses into a continuous, smoothly varying waveform, such as a voice or music signal. There are a few ways to
accomplish this; it's a matter of encoding the amplitude of the original signal into the pulse train that drives the output devices.
Theoretically, as long as the “area under the curve” for a segment of input signal is identical to the area represented by the pulse
train, we will have successfully encoded the signal and we then should be able to decode it, turning it back into a smoothly varying
output signal. For this to work properly, the pulse train will have to be at much higher frequency than the input signal in order to
follow its changes over time. One way to do this is through pulse density modulation, or PDM. The idea is to produce a number of
narrow pulses to represent the area. If the input amplitude is large, we create a large number of pulses and if the amplitude is small,
we produce a small number of pulses. While this technique can work, it is somewhat challenging to turn this pulse train back into
the desired signal at the load.
Another technique to encode the input is pulse width modulation, or PWM. Instead of altering the number of pulses in a given
period of time, we keep the frequency constant and adjust the width of the pulses. If the input amplitude is high, the width of the
corresponding pulse will be wide and if the amplitude is low, the pulse width will be narrow. The decoding of PWM is easier than
that of PDM and is generally the preferred route.
Generating PWM is a relatively straightforward affair. All we need is a triangle wave and a comparator. The comparator has two
input terminals: the signal to be encoded (input signal) and the reference wave (triangle wave). It has a two-state, logical output.
The output will be high if the signal is more positive than the reference and it will be low if the reference is more positive than the
signal. This is shown in block diagram form in Figure 14.3.1.

Figure 14.3.1: PWM encoder.

As mentioned, the triangle wave needs to be at a much higher frequency than the signal that is being encoded. As a general rule,
this frequency should be at least ten times the highest input signal frequency.
ftriangle ≥ 10 f2 (14.3.1)

A simulation showing the PWM waveforms is presented in Figure 14.3.2.

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 Figure 14.3.2: PWM waveforms.
The input signal is the red sine wave. The blue triangle wave is the reference and is approximately 20 times higher in frequency.
The green wave is the PWM output. Note that when the red input signal climbs above the blue reference triangle, the green output
goes high, otherwise, the output is low. Thus, the duty cycle of the pulses correlates with the input signal amplitude. The input
signal should not exceed the amplitude of the triangle wave otherwise accuracy will impaired. Also, the accuracy of the encoding
process is dependent on the linearity of the triangle wave, so a high quality triangle wave generator is needed. Lastly, for accuracy
and ease of decoding, the output pulses should not be allowed to become too thin, so the input signal should be limited to about
75% of the amplitude of the triangle wave.

14.3.1: Reconstituting the Output

Although we have successfully encoded the input signal into a series of pulses, we still need to decode them, that is, reconstitute
the original continuously variable input signal. Mathematically, the PWM signal contains all of the original input signal frequency
components and amplitudes, it just has added a large of number of new frequency components. These new components are
multiples (harmonics) of the fundamental PWM frequency, and consequently, they are all higher than the input signal frequencies.
As such, they may be removed with a low-pass filter. This will effectively reconstitute the original signal (but at a much higher
amplitude, of course). A simple passive LC filter would be appropriate in this instance as it must pass large currents and voltages.
An example is shown in Figure 14.3.3.

Figure 14.3.3: Passive low-pass filter.

At low frequencies, X will be very small while X will be very high, thus virtually all of the input signal frequencies will pass on
L C

to the load. At high frequencies, such as the harmonics of the PWM pulses, the situation is reversed: X is large and X is small,
L C

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creating a large loss so that these components do not reach the load.1 The critical frequency of the network is set to the highest
input signal frequency (e.g., for high fidelity audio, slightly above 20 kHz).
We now have a complete outline for the class D amplifier, as shown in Figure 14.3.4.

Figure 14.3.4: Class D amplifier block diagram.

The pre-amp can be comprised of any of the linear amplifier outlines presented in earlier chapters, whether they use BJTs or FETs.
What remains then, is further investigation into the output switching network.

References
1
For an audio amplifier, it is important that these components do not reach the loudspeaker. Even though they are beyond the range
of human hearing, they can damage loudspeaker sub-components and, at the very least, present an extra power dissipation burden
to them. Other kinds of loads may not be effected by the harmonics and filtering may not be needed.

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14.4: Output Configurations
If we apply the switching concept to a dual supply, push-pull topology, we arrive at the generic circuit of Figure 14.4.1.

Figure 14.4.1: Generic push-pull switching.

The two output devices are alternately switched on and off. When the upper device is on, the lower device is off, and current flows
from the positive supply to the load (blue path). Alternately, when the lower device is on, the upper device is off, and current flows
through the load via V (red path). We could use either BJTs or EMOSFETs for these devices.
SS

Two obvious variations exist of the generic output circuit. The first version, shown in Figure 14.4.2, appears to be a direct take-off
of a class B output. It is shown with EMOSFETs but could be made with BJTs. Biasing details are not shown, instead a generic
“driver” circuit block will prove sufficient for our discussion.

Figure 14.4.2: Basic push-pull switching.

In this circuit, the driver produces a bipolar pulse train that swings from negative to positive rather than from ground to positive. A
positive level from the driver will turn on the upper N-channel device, allowing current flow to the load. In contrast, a negative
level will turn on the lower P-channel device, allowing load current flow via V .1 It is worth noting that the gate drive signal must
SS

swing higher and lower than the two power supplies. This is because when a device is on, V DS will be nearly zero, meaning that
the source will be at the power rail. As V GS must be greater than V GS(th), this means that V must be greater than the power
G

supply.
An alternate connection scheme is shown in Figure 14.4.3. Here, the N- and P-channel devices have switched positions.

Figure 14.4.3: Alternate push-pull switching.

The logic here is reversed: the negative pulse turns on the upper device and the positive pulse turns on the lower device. The gate
swing is lessened a little compared to the earlier circuit but it suffers from a flaw common to both configurations, namely,
asymmetry between the N- and P-channel device characteristics. This includes variations between internal device capacitances and

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rDS(on) values. For the best possible matching, and thus the lowest distortion and highest performance, it would be better to
configure the output using identical devices. This is shown in Figure 14.4.4.

Figure 14.4.4: Output switching using identical devices.

This configuration complicates the drive signal in that we can no longer drive both gates with the same signal; instead, unique
signals must be presented to each gate terminal. This circuit is known as a half bridge. Our final step will be to drive both ends of
the load in differential fashion using a full bridge, or H bridge as it is sometimes known. This is shown in Figure 14.4.5.

Figure 14.4.5: Full bridge output.

The output devices are controlled as diagonal pairs. When Q is on, Q is on, creating a path for load current from left to right (red
1 4

trace). In contrast, when Q is on, Q will also be on, thus creating a load current path from right to left (blue trace). This
2 3

effectively doubles the current amplitude which quadruples the load power (because power varies as the square of current). This is
the same technique discussed in Chapter 9 with class B amplifiers. A dual L filter is included in this diagram to remove unwanted
C

frequency components.

Example 14.4.1

A pair of E-MOSFETs are configured to drive an 8 Ω load as in Figure 14.4.4. Assuming that ±50 volt sources are used and
that each device has an r of 0.03 Ω, determine the peak load current and V for the MOSFETs.
DS(on) DS

At any given time, one MOSFET will be on, creating a path between one supply, itself, the load and ground. The total
resistance to limit the current will be the load plus r .
DS(on)

VDD
iload =
rload + rDS(on)

50V
iload =
8Ω + 0.03Ω

iload = 6.227A

The device voltage is found via Ohms law as load and drain current are identical.

vDS = iload rDS(on)

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 vDS = 6.227A × 0.03Ω

vDS = 0.19V

Practical Concerns
There are a few details left that should not be overlooked. Two of them are related to the edge transition areas, another concerns the
complexity of the drive circuits, and the final issue deals with the power supplies themselves
The first item of concern is precisely what happens during the transition. All of the output forms we have examined utilize two
active devices configured in series between two power sources. There is nothing in that path to limit current. If both devices were
to be simultaneously triggered to the on-state, a huge and possibly damaging current would flow. While it would be foolish to turn
both devices on intentionally, the rise and fall times of the pulses effectively do this. As one device is turning on and the other is
turning off, both devices are in a conducting state, even if it's not maximum conduction. Essentially, we have two low impedance
devices in series between two sources. This results in a large current pulse known as shoot-through. This situation is depicted in
Figure 14.4.6.

Figure 14.4.6: Shoot-through.

The current pulses for the two devices are shown in blue and violet. The maximal currents are directed to the load, but during the
transition, a pulse of current, shown in red, “shoots through” the two devices, from one power supply directly to the other.
The solution to shoot-through is to adjust the turn-on and turn-off pulse timing so as to create a dead time, that is, a time span when
neither device is directed to turn on. This is illustrated in Figure 14.4.7.

Figure 14.4.7: Dead time.

Dead time is adjusted to correspond with the rise and fall times of the output devices. Basically, a device is not allowed to turn on
until the other device is, indeed, fully off. The inclusion of dead time alters the width of the pulse and consequently can introduce
waveform distortion. A minimum amount of dead time should be used to avoid this. This is another reason to use very fast output
devices as they will require shorter dead times.
The second issue regarding timing is one of device capacitance. Power MOSFETs exhibit relatively high device capacitances. For
example, the FDMS86180 examined in Chapter 12 exhibits input and output capacitances of roughly 4.4 nF and 2.7 nF,
respectively. Although the extremely high gate input resistance might seem to indicate that very little drive current is needed to turn
these devices on, the capacitance tells a different story.
The rate of change of voltage across a capacitor is a function of the capacitance and the current driving it:
dvC iC
=
dt C

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The larger the current, or the smaller the capacitor, the greater the rate of change of voltage. This can place a serious limit on how
quickly a device may be controlled. For example, suppose the drive circuit can pump out up to 10 mA. At first glance that may
seem like an enormous amount of current to drive a MOSFET. Now, consider what happens if the input capacitance is 2 nF:
dvC iC
=
dt C

dvC 10mA
=
dt 2nF

dvC
= 5E6V /s
dt

While a 5 million volt-per-second slope might sound fast, it's only 5 volts per microsecond. Compared to the requirements of, say, a
200 kHz to 300 kHz switching frequency, that is horribly slow.

Computer Simulation
To see the effect of input capacitance, a two-stage amplifier is captured in a simulator, as shown in Figure 14.4.8. The circuit
consists of a relatively standard small signal amplifier feeding a medium power E-MOSFET, the IRF7201. A 10 kHz square wave
is used to drive the circuit. The input capacitance of the MOSFET is 550 pF, certainly larger than a small signal FET but not an
extremely large value. A single capacitor is placed across the gate that will be used to simulate a much larger device and the
associated increased input capacitance.

Figure 14.4.8: Circuit for input capacitance testing.

The initial transient analysis is run using a 5 pF gate capacitance which has no appreciable effect on the outcome. The result of the
simulation is shown in Figure 14.4.9.
The red trace is the gate voltage at node 6 while the blue trace is the final output at node 2. The gate drive signal is suffering
somewhat at the upper portion and the rise and fall times are evident. The output signal is swinging from the power supply of +15
volts down to ground, as expected. The rise time is somewhat quicker than the fall time but, in general, the output presents a decent
square pulse at close to 50% duty cycle. The simulation is repeated but this time the gate capacitance is increased from 5 pF to 5
nF, a value more typical of a large power FET. The result is shown in Figure 14.4.10. The red gate drive signal has taken a serious
hit and is no longer square in shape. The output pulse in blue still runs to and from the expected voltage levels, but the rising and
falling edges are noticeably slowed. Also, the positive pulse width has been stretched due to the slowing of the gate signal which
retards the turn on of the MOSFET. The result is a duty cycle that is greater than 50%.

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 Figure 14.4.9: Waveforms for normal circuit.

Figure 14.4.10: Waveforms for circuit with increased gate capacitance.

The bottom line is that, in order maximize speed, care must be taken to minimize capacitance, decrease the output impedance of the
driver circuit and increase the drive current. Fortunately, this issue has been largely solved by IC manufacturers who offer FET
driver integrated circuits designed specifically for these applications.
The final item of practical concern is the power supply itself, or more precisely, the quality of the supply voltage. Remember, the
output device is being used as a switch. When the device is on, the power supply is directly connected to the output (with the
exception of the small voltage drop across the output device). This means that any noise or ripple on the power supply will make its
way to the output filter. Whatever noise components fall within the desired input signal range will not be filtered out, and thus are
delivered to the load. In short, the output devices will “leak” the power supply noise into the output, so care must be taken to have
as clean of a power supply voltage as possible.

References
1
Yes, it is labeled V in spite of the fact that it's connected to the drain of the P-channel device. It's a matter of consistency with
SS

other circuits. “A rose by any other name” and all that...

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14.5: Summary
The class D amplifier boasts very high efficiency, theoretically approaching 100%. The amplifier operates its output devices as
switches; they are either fully on or fully off. The power losses are mostly relegated to switching edge losses so it is important to
not switch the output devices at too high of a frequency.
The input signal is encoded as a series of pulses, typically via pulse width modulation. The pulse frequency is much higher than the
highest input signal frequency, typically by an order of magnitude. The width of the pulses is a function of the amplitude of the
input signal. That is, the higher the input signal, the greater the pulse width. The pulses are amplified by applying them to the
output devices which then act as switches to alternately connect and disconnect the power supplies to the output terminal. The
sequence of much larger amplitude pulses are then fed to a low-pass filter, typically, an LC filter, to remove the high frequency
components of the pulse train. The reconstituted input signal is what remains, but at a much higher amplitude.
The output can be configured using either two-device half-bridge or four-device fullbridge arrangements. The full-bridge is
preferred for higher performance. The input capacitance of the output devices can be relatively high, so care must be taken to
ensure that sufficient capacity is available from the driver circuit.

14.5.1: Review Questions

1. What is PWM?
2. How does PWM differ from PDM (pulse density modulation)?
3. What is shoot-through? What causes it?
4. What is dead time? What is its purpose?
5. What is the function of the output LC filter?
6. What effect does device input (e.g., gate) capacitance have on the operation of the amplifier?
7. Sketch a half-bridge configuration.
8. Sketch a full-bridge configuration.
9. What is the effect of r
DS(on)
regarding load current and power losses?
10. What is the effect of drive current capacity on the output devices?
11. What effect does power supply noise have on the output?

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14.6: Exercises
14.6.1: Analysis Problems
1. A telephony system has a frequency range from 200 Hz to 3.5 kHz. Determine the minimum acceptable PWM frequency.
2. A background music and paging system has a frequency range from 50 Hz to 10 kHz. Determine the minimum acceptable PWM
frequency.
3. Determine the maximum rate of change of input voltage for a driver circuit capable of producing 50 mA with a load consisting
of a 1.5 nF gate capacitance.
4. Determine the maximum rate of change of input voltage for a driver circuit capable of producing 60 mA with a load consisting
of a 3.5 nF gate capacitance.
5. A power E-MOSFET has an rDS(on) of 0.012 Ω and switches a 100 volt source to an 8 Ω load. Determine the maximum load
current and V .
DS

6. Four power E-MOSFETs drive a 4 Ω load via a full bridge network. If each device has an rDS(on) of 0.02 Ω and they switch
±75 volt sources to the load, determine the load current and V of the devices.
DS

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 CHAPTER OVERVIEW

15: Insulated Gate Bipolar Transistors (IGBTs)

Learning Objectives
After completing this chapter, you should be able to:
Discuss the basic operation of the IGBT.
Describe the internal structure of the IGBT.
Describe the differences between PT and NPT IGBTs.
Compare and contrast the IGBT to the power BJT.
Compare and contrast the IGBT to the power MOSFET.
Interpret important parameters found on an IGBT data sheet.
Describe basic circuits using the IGBT as a power control device.

15.1: Introduction
15.2: IGBT Internals
15.3: IGBT Data Sheet Interpretation
15.4: IGBT Applications
15.5: Summary
15.6: Exercises

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1
15.1: Introduction
The Insulated Gate Bipolar Transistor, or IGBT, is a power semiconductor that first became available to the commercial market
during the 1980s. Initial devices had certain performance issues but these problems largely have been taken care of with subsequent
generations. Today, the IGBT is in wide use, competing with power BJTs and power E-MOSFETs across a range of applications.
The IGBT is designed to be used as a high voltage/high current switch and typically is not used for linear applications such as an
audio class B power amplifier. The IGBT has also overtaken the older thyristor devices (e.g., SCR) in many areas due to its speed
and the relative simplicity of the driving circuits used to control it.
The IGBT offers a mix of performance characteristics of both the power BJT and the power E-MOSFET. Like the BJT, the IGBT
offers low on-state power loss and the ability to handle large currents and voltages. Like the power E-MOSFET, it is relatively easy
to drive, being a voltage-controlled device rather than a current-controlled device. On the down-side, it is not as fast as the current
generation of power E-MOSFETs and tends to be more costly than both the power BJT and power E-MOSFET. Consequently, the
choice of which of these three devices should be used for a given power switching application will depend on the specifics of the
design. For example, a medium to high power design that focuses on lowest cost may favor the BJT, a low to medium power
application that requires very high switching speeds may be best solved with a power E-MOSFET, while an IGBT might be ideal
for a very high power application utilizing low to medium speed clocking. This chapter will examine a number of power switching
applications, and while they will all revolve around using the IGBT, please bear in mind that, depending on the specifics, power
BJTs and E-MOSFETs might also be used.
The IGBT is available in two variants: the punch through, or PT; and the non-punch through, or NPT, versions. We shall look at
both.

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15.2: IGBT Internals
The IGBT is a multi-layer device. The cutaway shown in Figure 15.2.1 uses an Nchannel, although P-channel is possible. This
device has many features in common with the power E-MOSFET discussed in Chapter 12.

Figure 15.2.1: Cutaway view of IGBT.

To begin, note the labeling of the three terminals: gate, emitter and collector. The gate is isolated just as it is in MOSFETs. When a
positive gate-emitter potential is applied, an N-type inversion layer will develop in the the P body region, allowing current to flow.
The middle N region is split into two sections, the main N− drift region and the N+ buffer layer (the +/− signs indicate heavy and
light doping, respectively). The device shown is the punch through (PT) variety. The non-punch through (NPT) omits the buffer
layer. The functional differences between the two are that splitting the N material to include the buffer layer improves speed and
lowers on-state voltage. Consequently, the PT version exhibits lower switching and conduction losses.
The upper three layers of Figure 15.2.1 form an E-MOSFET while the lower section (P body, N drift/buffer and P substrate) form a
PNP transistor. Thus, we can make a simplified model of the IGBT using these other devices, as shown in Figure 12.2.2.

Figure 15.2.2: Simple model of an IGBT (left) compared to a Sziklai pair (right).
This simplified model is reminiscent of the NPN version of the Sziklai pair examined in Chapter 9. The input device has been
replaced by an E-MOSFET. Therefore we expect the very small gate current and relatively simple drive requirements of the
EMOSFET with the power handling of a BJT.
The operational device curves are, unsurprisingly, also reminiscent of these two components. A set of collector curves is presented
in Figure 15.2.3 using representative values for voltage and current.

Figure 15.2.3: IGBT collector curve family.

This set of curves appears as a cross between the collector curve family seen in Chapter 4 and the drain curve family seen in
Chapter 10, with one slight twist: the entire set of curves is displaced positively from the origin by about one volt. As with any E-
MOSFET, channel current does not begin to flow until the gate threshold voltage is reached, here referred to as V GE(th)
. Increasing

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values of V GE cause increased conduction and current flow. Finally, note that the curves do not begin to “flatten” until VC E has
reached several volts, unlike the saturation voltage of a single BJT which might be only tenths of a volt.
The forward current-voltage characteristic curve reflects the E-MOSFET portion of the model. This is shown in Figure 15.2.4.

Figure 15.2.4: IGBT characteristic curve and variation with temperature.

Two traces are plotted for two different temperatures. The curves are essentially the same as the characteristic curve of the E-
MOSFET, as seen in the introductory MOSFET chapter, Figure 12.4.3 (here the current axis has been expanded, making the traces
appear steeper, in order to more clearly show the variation with temperature). Conduction begins at the threshold voltage, V ,GE(th)

and then rises rapidly, following a square law trajectory. Once a sufficient current level is reached, the curve can be approximated
as a straight line.
Of particular interest here is how the curve varies with temperature. As temperature increases (red trace), the slope decreases.
Recalling that the slope of the current-voltage characteristic curve is the device transconductance, this means that the
transconductance decreases with temperature. In other words, the IGBT exhibits a negative temperature coefficient of
transconductance, just like power E-MOSFETs, and thus are also less inclined to suffer from current hogging and thermal runaway
problems than BJTs.
Unfortunately, there isn't a single, standardized schematic symbol for the IGBT. Two versions are shown in Figure 15.2.5.

Figure 15.2.5: IGBT schematic symbols.

Both symbols attempt to reflect the dual E-MOSFET/BJT character of the device. The symbol on the left appears to have wider use
currently, although there is also a third variation based on it where the gate connection is drawn toward the center rather than closer
to the emitter.

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15.3: IGBT Data Sheet Interpretation
A portion of the data sheet for the Fairchild/ON Semiconductor FGH50T65SQD IGBT is shown in Figure 15.3.1. This is a fourth
generation IGBT featuring trench construction. It is rated for 650 volts and 50 amps. The device includes an antiparallel diode. This
is useful for bridge applications that drive inductive loads (recall that the current through an inductor cannot change
instantaneously, thus, when devices are switched on/off in a bridge, the diode serves to create a path around the IGBT for this
current).

Figure 15.3.1a: FGH50T65SQD data sheet. Used with permission from SCILLC dba ON Semiconductor.

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 Figure 15.3.1b: FGH50T65SQD data sheet (cont).
The main features are the 650 volt rating for V , 100 amp continuous collector current and 268 watt dissipation at 25 C. The
CE
∘

current and power ratings are essentially halved at the more practical temperature of 100 C. The threshold voltage, V
∘
, is
GE(th)

specified as 4.5 volts with a ±1.9 volt spread. The saturation voltage typically is 1.6 volts at room temperature with 50 amps of
collector current. This compares favorably to basic power BJTs. Like power MOSFETs, the input capacitance is relatively high at
3275 pF, so the same gate drive precautions must be followed. Finally, note the asymmetry in switching times. At room
temperature and 12.5 amps of collector current, the turn-on delay plus rise time is specified as approximately 31 nanoseconds while
the turn-off delay and fall time is nearly 110 nanoseconds. This relative slowing of the off-state transition is typical of IGBTs.
Further, as both current and temperature increase (Figure 15.3.1c), these times increase by a few percent. By comparison, the
FDMS86180 power E-MOSFET examined in Chapter 12 exhibited symmetrical values in the mid-30 nanosecond region at a drain
current of 67 amps.

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 Figure 15.3.1c: FGH50T65SQD data sheet (cont).
Finally, consider the graphical data presented in Figure 15.3.1d.

Figure 15.3.1d: FGH50T65SQD data sheet (cont).

The top two graphs show the collector curves in the low voltage region. Compare these with Figure 15.2.3. Similarly, the middle-
left graph shows the current-voltage characteristic with temperature variation. This reflects Figure 15.2.4. Finally, the bottom two
graphs show the collector-emitter saturation voltage with respect to gateemitter drive voltage for three different collector currents.

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Note that for the highest current at room temperature, saturation voltage is around 2 volts for a gate drive of at least 8 volts. This
rises to about 3 volts at 175 C.
∘

Computer Simulation
To highlight the performance of the IGBT, a simple series load switch is simulated. The circuit is shown in Figure 15.3.2.

Figure 15.3.2: IGBT simulation schematic.

A 10 ohm load is switched from a 100 volt DC power supply via an International Rectifier IRGPC40K IGBT. The gate is driven
from a 10 volt peak square wave running at 100 kHz.
Ideally, if the IGBT produced no losses, the full 100 volt source would drop across the load, producing 10 amp current pulses.
According to the device data sheet, collector-emitter saturation voltage typically is 2.1 volts (3.2 volts maximum) with a 25 amp
collector current. The total turn-on/rise time and turn-off/fall time values are 62 nanoseconds and 290 nanoseconds typically, at 25
amps and room temperature.
A transient analysis is run, with the results shown in Figure 15.3.3.

Figure 15.3.3: Transient analysis of simple IGBT switch.

The drain voltage (node 1) is shown as the purple trace and the drain current is shown in green (reversed in polarity to see it more
clearly). The two cursors (red is #1, blue is #2) show the various levels. As expected, the drain voltage peaks at 100 volts in the off-
state, at which time the current is nil. During the on-state, the drain voltage drops to about 2.36 volts, very close to the data sheet's
typical saturation potential. This small drop reduces the voltage across the load to about 97.64 volts. This is verified by cursor #1

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showing a current of 9.765 amps. Also, although it is not possible to determine the edge timings with great precision from this plot,
the asymmetry between rise and fall is apparent, and the edges are generally consistent with the numeric values from the data sheet.
Figure 15.3.4: shows the result of multiplying the current and voltage waveforms. This new waveform represents the power
dissipation of the IGBT.

Figure 15.3.4: Power waveform of simple IGBT switch.

The power trace is shown in fuchsia, or magenta, or screaming purple-pink, or whatever-you-want-to-call-it. The edge spikes
dominate but the on-state power is apparent as well. Remember, during the on-state, the load is dissipating close to 1000 watts. The
cursor output window is shown separately in Figure 15.3.5. The on-state power dissipation is approximately 23 watts which
represents less than 2.5 percent of the load power. In contrast, the edge spikes are maxing out at around 250 watts. Of course, the
time duration is very short, being only a few percent of the cycle period, but it cannot be ignored.

Figure 15.3.5: Numeric values at waveform cursors for the IGBT switch.

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15.4: IGBT Applications
IGBTs lend themselves to a variety of high power switching applications. In this section, we shall look at four of them. Bear in
mind that power BJTs and power EMOSFETs might also be used for these applications, depending on the specifics of the design.
In general, power E-MOSFETs will be preferred when using high switching frequencies at medium to low powers and voltages,
while IGBTs are favored at higher voltages, currents and powers.

15.4.1: Induction Heating

Although thermal conduction is the first method commonly thought of when it comes to heating something, magnetic induction
may also be used. Magnetic induction creates heat through the Joule effect and can be used for large scale industrial processes, such
as creating metal alloys via an induction furnace, to much smaller scale consumer applications, such as an inductive cooktop.
Induction heating is efficient because the vessel itself is heated directly and less heat is lost to the immediate environment. Also,
control of heating can be very precise. The basic idea is to create a rapidly changing magnetic field placed next to the container to
be heated. If this vessel is ferromagnetic, eddy currents will be induced in the vessel, creating heat. Thus, if we were to place a cast
iron pot within the field, the pot itself would heat up as eddy currents are induced within it, thus heating the pot's contents. There
are no open flames or surface heating elements involved. The only downside to this process is that the vessel must be made of
ferromagnetic material. For a cooktop, that means that pots and pans must be made of iron or certain steel alloys. An aluminum
sauté pan or ceramic container will not work with this system.
As an example, let's consider an inductive cooktop. A sophisticated design could feature a full- or half-bridge arrangement of
IGBTs, but for illustrative purposes we'll focus on a simple single-ended system using just one IGBT.
The system features four main components: the rectifier/EMI filter, the control/drive circuit, the IGBT switch and the LC resonant
tank sub-circuit that generates the field. This is illustrated in Figure 15.4.1.

Figure 15.4.1: Simple inductive heater.

The rectifier produces full-wave pulsating DC, and the associated capacitor, C , is used to help minimize EMI (electromagnetic
2

interference) and also provide a return path for the tank. The control circuit produces a variable duty cycle pulse train to drive the
gate of the IGBT. The greater the duty cycle, the longer the on-state of the IGBT, and ultimately, the greater the heating. Between
the IGBT and the rectified power signal is a parallel resonant tank circuit comprised of C and L . The inductor is comprised of a
1 1

series of loops of large gauge wiring or copper tubing embedded in the cook surface, typically under a glass or ceramic top. The
resonant frequency of the tank is tuned to the frequency of the controlling pulse train. This will maximize the tank current and thus
produce a more powerful magnetic field. The switching frequency is usually placed just above the range of human hearing to avoid
audible microphonics.1 Values in the range of 20 kHz to 30 kHz are typical, and the base frequency may change as the heat demand
changes. For example, to minimize switching losses, the controlling frequency might start at 30 kHz for modest heating and
decrease to 20 kHz for maximum heating.
From the cook's perspective there is no change between using the inductive cooktop and an ordinary electric cooktop using
resistive heating elements: The cook places the pot or pan on the surface, under which lies the coil. A heat level control knob is
provided for them to adjust the heat intensity. To their advantage, when they remove the pot or pan, the cooking surface itself will
not be as hot as an ordinary cooktop.
From the designer's perspective, the heat control knob simply changes the duty cycle of the controlling pulse train (and optionally,
its frequency, as mentioned previously). Other refinements might include sensing whether or not a vessel is on the cooktop and
throttling back control if nothing is detected. Finally, an even simpler system could switch the IGBT on and off at a much slower

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rate (think in terms of seconds) to greatly reduce switching losses but this runs the risk of heat cycling if the pots and pans used are
of very light gauge construction (i.e., their thermal time constant will be faster).

15.4.2: DC-to-AC Inversion

There are many instances where we wish to derive an AC voltage from an existing DC voltage. Examples include an
uninterruptible power supply (UPS) that would draw current from a battery and deliver standard AC power when there is a
disruption in the power grid, and the need to operate electronic devices designed for the home in a remote location. This process is
known as DC-to-AC inversion.
The simplest method to create AC from DC is to just “chop” the DC at the desired line frequency and then scale it, that is, feed the
DC into a simple IGBT switch which will produce a square wave and then feed the square wave into a transformer to arrive at the
desired voltage. The obvious problem with this technique is that the AC signal will not be a nice, smooth sine wave, but rather, a
distorted square wave. Unfortunately, for many electronic components this will present a challenge to their power supply circuits.
A possible refinement involves making a step-wise approximation of a sine wave but this is still not ideal.
A more accurate scheme involves synthesizing a sine wave via PWM. We still chop the DC, but now the action is performed at a
higher frequency and with a varying duty cycle such that, when the output is averaged, we arrive at a sine wave. A block diagram
of this scheme is shown in Figure 15.4.2.

Figure 15.4.2: DC-to-AC inverter (antiparallel diodes not shown).

The controller generates a set of PWM signals to drive the four IGBTs configured as a full-bridge. The bridge output is then fed to
a balanced LC filter that removes the high frequency PWM components, leaving a smoothed sine wave. This signal can be used as
is, or fed into a step-up transformer if the desired AC voltage is greater than the starting DC voltage. An example of this would be
the need to supply a device designed to run on 120 VAC from the nominal 12 VDC system found in a car.
There is a side item worthy of mention here. Some devices derive timing signals from the line frequency (a classic example is an
electronic alarm clock/radio). This is possible because the power generation utility monitors this frequency with great accuracy. If
the controller shown in Figure 15.4.2 does not produce an accurate base frequency, then that clock/radio will not tell time
accurately.

15.4.3: Motor Control

IGBTs can be used to control the speed of electric motors. The configuration of the control circuit will depend on the kind of motor
being controlled. In simplest terms, the speed of a DC motor is controlled by the voltage applied to it: the higher the voltage, the
higher the speed. In contrast, the speed of an AC motor depends on the frequency of the applied source (they are proportional).
Controlling a DC motor is a straightforward situation. If all we need to do is start and stop the motor, the IGBT can be inserted in
series with the motor and used as a switch to open and close the circuit. Being solid-state, the IGBT has numerous advantages over
a mechanical switch or relay including long-term reliability and simplicity of the control circuit. To alter the speed, the IGBT can
be controlled via PWM. This is illustrated in Figure 15.4.3.

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 Figure 15.4.3: DC motor control via IGBT.
D1 and D are flyback or snubber diodes used for protection from inductive current spikes caused by the motor's current being
2

switched on and off. As noted earlier, some IGBTs are co-packaged with an anti-parallel diode (D ).1

To vary the motor's speed, the controller produces a PWM drive signal. The smaller the duty cycle of this pulse train, the lower the
average applied voltage to the motor, and therefore the slower its speed. The base frequency of the PWM signal does not have to be
particularly high in this scenario; a few hundred hertz may prove sufficient. This will help minimize switching losses.
For an AC motor the situation is a little more complex. One approach is to use the PWM technique explained under the DC-to-AC
converter section. The difference is that the power source would not be DC, but rather, AC. Consequently, we would need to
transform the AC power source into a more usable signal and then apply the circuit depicted in Figure 15.4.2 to power the motor.
The controller itself will need to be considerably more sophisticated. In Figure 15.4.2, the duty cycle is continuously changed such
that the “area under the curve” approximates a sine wave. Eventually, the pattern will repeat itself for subsequent cycles of the sine
wave. In other words, the rate at which the pattern repeats is the sine wave's period. In the DC-to-AC inverter application, this rate
never changes because we need a constant output frequency (e.g., 60 Hz). In the AC motor control application, such is not the case.
This repetition rate needs to be adjustable because that's what controls the motor's speed. One way to do this is to simply increase
the base frequency of the PWM pulse train. This method is simple and direct but has the disadvantage of creating more transient
edges per unit time and therefore tends to increase switching losses. An alternate approach is to keep the base frequency constant
and instead alter the duty cycle pattern. This helps minimize the switching loss issues but has the disadvantage of requiring a more
complex control circuit and possibly producing a lower quality sine wave at higher output frequencies.

15.4.4: DC-to-DC Conversion

Our final application is DC-to-DC up-conversion, that is, producing a new DC voltage that is higher than the original source and
also capable of high output current (voltage doublers and triplers can be made from diode/capacitor lattices but they are not
designed to deliver high, continuous currents). Applications requiring up-conversion include photovoltaic systems (i.e, combining
the outputs of several solar panels and tying them into the power system) and high output car audio systems. Specifically, the
nominal 12 volt automotive power system is insufficient to supply an amplifier intended to deliver hundreds or even thousands of
watts to a subwoofer. The 12 volt source will need to be increased, perhaps by a factor of ten, to achieve the desired output levels.2
As we have already seen how DC can be translated into AC via an inverter, it is possible to simply rectify and filter the new AC,
producing a higher DC level. This scheme is illustrated in Figure 15.4.4.

Figure 15.4.4: DC-to-DC conversion via transformer (anti-parallel diodes not shown).
The transformer pictured here will need to be a step-up variety in order to achieve the desired output voltage level. Note that the
AC generation side does not have to produce a particularly nice sine wave nor does it have to be at the usual line frequency. In fact,
increasing the frequency will likely result in reduced sizes for the transformer and filter capacitors.

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A completely different approach is to use a switching regulator. Switching regulators use a feedback control system to generate a
very stable output voltage by comparing it to a reference voltage. They can be configured in step-down, step-up or polarity
inversion forms.3 In this case, we can use the step-up, or boost, form. An example is shown in Figure 15.4.5.

Figure 15.4.5a: Step-up switching regulator, on-state.

As with the other applications presented so far, the IGBT is being used as a switch. Figure 15.4.5a illustrates the on-state of the
IGBT. During this phase, current is drawn through the inductor, L, storing energy in the associated magnetic field. The reverse-
biased Schottky diode, D, isolates this section from the output section, where C is delivering the load voltage and current.

Figure 15.4.5b: Step-up switching regulator, off-state.

The off-state is depicted in Figure 15.4.5b. During this portion, the inductor discharges and appears as a source. As it is in series
with the input voltage, the voltage at the output will equal the inductor's voltage plus the input voltage. Also, during this phase the
capacitor is recharged, ready for the next on-state of the IGBT. Note that a Schottky diode is used here because it exhibits fast
switching times and a low forward voltage drop. Switching frequencies for these circuits tend to be high (100 kHz and up are
common) as that minimizes the sizes of the inductor and capacitor.

References
1Granted,it may still fall within the hearing range of your dog, so don't be surprised if your border collie prefers a gas cooktop to
make a balsamic reduction.
2
In the process, the current demand will be increased greatly as well, perhaps beyond the capabilities of the vehicle's alternator
(which will also require upgrading), but these are the prices one must pay if one desires very high sound pressure levels in what is
arguably the worst acoustical environment in which to listen to music. Of course, we should also admit that the act of critically
listening to and enjoying music may not be the point of such an exercise.
3
For details on switching regulators, see Fiore, J, Operational Amplifiers and Linear Integrated Circuits: Theory and Application,
another free OER text.

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15.5: Summary
The Insulated Gate Bipolar Transistor, or IGBT, can be thought of as a combination of a power BJT and a power E-MOSFET. As
such, it combines the low on-state conduction losses of the BJT with the relatively easy drive requirements of the EMOSFET. The
IGBT is available in two variants; the PT, or punch through, and the NPT, or non-punch through types. The PT type includes an N+
buffer layer in its construction and this endows the device with faster switching speed and lower onstate losses.
The IGBT's characteristic curves tend to echo that of the E-MOSFET. Conduction does not begin until the gate-emitter voltage
exceeds a threshold voltage, V GE(th) . From there, the current-voltage characteristic follows a square-law trajectory, and at
sufficiently high current levels it can be approximated as a straight line. The IGBT exhibits a negative temperature coefficient of
transconductance, like the MOSFET, making it less prone to thermal runaway and current hogging issues. A family of collector
curves (i.e., V
CE vs. I ) shares attributes with BJT collector curves and MOSFET drain curves. The curves echo the same overall
C

shape, starting with a section where current rises rapidly compared to voltage, and then leveling out into a constant current region.
The initial region of rapid change is somewhat drawn out as it is in the MOSFET. Also, the entire set of curves is displaced
positively by about a volt, rather than current increasing immediately from the origin.
In general, the IGBT offers higher voltage, current and power capability than the power E-MOSFET although it lags behind in
switching speed. Further, switching times for the on- and off-state are asymmetrical. Compared to the power BJT, the IGBT tends
to be more expensive. Consequently, power E-MOSFETs tend to be favored at low and moderate power levels when high switching
speeds are needed and BJTs tend to be preferred when cost is a major component in more modest designs. As such, IGBTs find use
across a range of applications including power inverters, uninterruptible power supplies, induction heaters, solar power systems,
motor controllers and so forth.

15.5.1: Review Questions

1. What are the advantages and disadvantages of IGBTs compared to power BJTs?
2. What are the advantages and disadvantages of IGBTs compared to power E-MOSFETs?
3. What are the differences between NPT and PT IGBTs?
4. Compare the simple IGBT model to that of a Sziklai pair.
5. Explain the basic operation of an induction heater and how an IGBT is used to control the generation of heat.
6. Explain how pulse width modulation might be used to control the speed of a DC motor via an IGBT.
7. Explain how an IGBT can be used to translate a DC power source into an AC power source.

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15.6: Exercises
15.6.1: Analysis Problems
1. From the FGH50T65SQD data sheet, determine the collector-emitter saturation voltage at 25 C for V ∘
GE = 7 volts and I = 50
C

amps.
2. From the FGH50T65SQD data sheet, determine the change in collector-emitter saturation voltage from 25 C to 175 C for V
∘ ∘
GE

= 8 volts and I = 100 amps.

C

3. From the FGH50T65SQD data sheet, determine the rise time for a 50 amp collector current at 25 C for V ∘
GE = 15 volts.
4. From the IRGPC40K data sheet, determine the combined turn-on and rise time at 150 C. ∘

5. From the IRGPC40K data sheet, determine the combined turn-off and fall time at 150 C. ∘

15.6.2: Computer Simulation Problems

6. Repeat the simple switch simulation from this chapter using the FGH50T65SQD IGBT and compare the resulting voltage,
current and power waveforms.
7. Repeat the simple switch simulation from this chapter using the FDMS86180 power E-MOSFET from Chapter 12 and compare
the resulting voltage, current and power waveforms.

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Index

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Glossary
Sample Word 1 | Sample Definition 1

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