ON Semiconductor

Is Now

To learn more about onsemi™, please visit our website at

www.onsemi.com

onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
Design and Application
Guide of Bootstrap Circuit
for High-Voltage Gate-Drive
IC

AND9674/D www.onsemi.com

APPLICATION NOTE
INTRODUCTION
The purpose of this paper is to demonstrate a systematic considered. This method is utilized as a gate drive and
approach to design high−performance bootstrap gate drive accompanying bias circuit, both referenced to the source of
circuits for high−frequency, high−power, and the main switching device. Both the driver and bias circuit
high−efficiency switching applications using a power swing between the two input voltage rails together with the
MOSFET and IGBT. It should be of interest to power source of the device. However, the driver and its floating
electronics engineers at all levels of experience. In the most bias can be implemented by low−voltage circuit elements
of switching applications, efficiency focuses on switching since the input voltage is never applied across their
losses that are mainly dependent on switching speed. components. The driver and the ground referenced control
Therefore, the switching characteristics are very important signal are linked by a level shift circuit that must tolerate the
in most of the high−power switching applications presented high−voltage difference and considerable capacitive
in this paper. One of the most widely used methods to supply switching currents between the floating high−side and
power to the high−side gate drive circuitry of the ground−referenced low−side circuits. The high−voltage
high−voltage gate−drive IC is the bootstrap power supply. gate−drive ICs are differentiated by unique level−shift
This bootstrap power supply technique has the advantage of design. To maintain high efficiency and manageable power
being simple and low cost. However, it has some limitations, dissipation, the level−shifters should not draw any current
on time of duty−cycle is limited by the requirement to during the on−time of the main switch. A widely used
refresh the charge in the bootstrap capacitor and serious technique for these applications is called pulsed latch level
problems occur when the negative voltage is presented at the translators, shown in Figure 1.
source of the switching device. The most popular bootstrap
circuit solutions are analyzed; including the effects of Bootstrap Drive Circuit Operation
parasitic elements, the bootstrap resistor, and capacitor; on The bootstrap circuit is useful in a high−voltage gate
the charge of the floating supply application. driver and operates as follows. When the VS goes below the
IC supply voltage VDD or is pulled down to ground (the
HIGH−SPEED GATE−DRIVER CIRCUITRY low−side switch is turned on and the high−side switch is
turned off), the bootstrap capacitor, CBOOT, charges through
Bootstrap Gate−Drive Technique the bootstrap resistor, RBOOT, and bootstrap diode, DBOOT,
The focus of this topic is the bootstrap gate−drive circuit from the VDD power supply, as shown in Figure 2. This is
requirements of the power MOSFET and IGBT in various provided by VBS when VS is pulled to a higher voltage by the
switching−mode power−conversion applications. Where high−side switch, the VBS supply floats and the bootstrap
input voltage levels prohibit the use of direct−gate drive diode reverses bias and blocks the rail voltage (the low−side
circuits for high−side N−channel power MOSFET or IGBT, switch is turned off and high−side switch is turned on) from
the principle of bootstrap gate−drive technique can be the IC supply voltage, VDD.

VB
current compensated

UVLO
Shoot−through

gate driver

PULSE GENERATOR
IN HO
R
NOISE R
CANCELLER S Q

VS

Figure 1. Level−Shifter in High−Side Drive IC

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

August, 2021 − Rev. 3 AND9674/D
 AND9674/D

RBOOT DBOOT
DC SUPPLY

HIN
VB t

RG1
VDD HO Q1
ILOAD V S −COM
CBOOT
VDD

VS
t
LOAD
RG2 Q2 −V S Freewheeling
COM LO

Figure 4. VS Waveforms During Turn−off

Bootstrap charge current path Cause of Negative Voltage on VS Pin

Bootstrap discharge current path A well−known event that triggers VS go below COM
(ground) is the forward biasing of the low−side freewheeling
Figure 2. Bootstrap Power Supply Circuit diode, as shown in Figure 5.
Drawback of Bootstrap Circuitry Major issues may appear during commutation, just before
The bootstrap circuit has the advantage of being simple the freewheeling diode starts clamping.
and low cost, but has some limitations. In this case, the inductive parasitic elements, LS1 and
Duty−cycle and on time is limited by the requirement to LS2, may push VS below COM, more than as described
refresh the charge in the bootstrap capacitor, CBOOT. above or normal steady−state condition.
The biggest difficulty with this circuit is that the negative The amplitude of negative voltage is proportional to the
voltage present at the source of the switching device during parasitic inductances and the turn−off speed, di/dt, of the
turn−off causes load current to suddenly flow in the switching device; as determined by the gate drive resistor,
low−side freewheeling diode, as shown in Figure 3. RGATE, and input capacitance, Ciss, of switching device.
This negative voltage can be trouble for the gate driver’s It is sum of Cgs and Cgd, called Miller capacitance.
output stage because it directly affects the source VS pin of
VCC
the driver or PWM control IC and might pull some of the DBOOT
internal circuitry significantly below ground, as shown in
Figure 4. The other problem caused by the negative voltage VDC
IN VB
transient is the possibility to develop an over−voltage
HVIC
INPUT

condition across the bootstrap capacitor. CBOOT Q1

The bootstrap capacitor, CBOOT, is peak charged by the VDD HO A
RGATE
B

bootstrap diode, DBOOT, from VDD the power source. LS1 iLOAD
Since the VDD power source is referenced to ground, the GND VS C C
CDRV

maximum voltage that can build on the bootstrap capacitor LS2 iFree

VOUT
GND COUT
is the sum of VDD and the amplitude of the negative voltage −VS
D1
at the source terminal.

DC SUPPLY Figure 5. Step−Down Converter Applications

High Side OFF

RBOOT DBOOT

VB
RG1
VDD HO Q1
CBOOT

iLoad
Ls1

HIN HIN
LIN VS
Freewheeling Path

LIN
ifree
Ls2

CIN
RG2
COM LO Q2

Figure 3. Half−Bridge Application Circuits

www.onsemi.com
2
 AND9674/D

Figure 6 shows the waveforms of the high−side, shifter of the high−side gate driver suffers form a lack of the
N−channel MOSFET during turn−off. operation voltage headroom. This should be noted, but
proves trivial in most applications, as the high−side in not
usually required to change state immediately following
a switching event.
A−Point VBS

INPUT
VDC + VGS, Miller
B−Point

C−Point VDC

OUTPUT
Recovery Time

VGS = B−C Point

Figure 8. Waveforms in Case of Signal Missing

Figure 6. Waveforms During Turn−off
Consideration of Latch−up Problem
Effects in the Undershoot Spike on VS Pin
If undershoot exceeds the absolute maximum rating The most integrated high−voltage gate−drive ICs have
specified in the datasheet, the gate drive IC suffers damage parasitic diodes, which, in forward or reverse break−down,
or the high−side output is temporarily unresponsive to input may cause parasitic SCR latch−up. The ultimate outcome of
transition as shown in Figure 7 and Figure 8. latch−up often defies prediction and can range from
Figure 7 shows Latch−up case that the high−side output temporary erratic operation to total device failure. The
does not changed by input signal. In this case, short−circuit gate−drive IC may also be damaged indirectly by a chain of
condition occur on external, main, high−side and low−side events following initial overstress. For example, latch−up
switches in half−bridge topology. could conceivably result in both output drivers assuming
a HIGH state, causing cross−conduction followed by switch
failure and, finally, catastrophic damage to the gate−drive
IC. This failure mode should be considered a possible
root−cause, if power transistors and/or gate−drive IC are
destroyed in the application. The following theoretical
INPUT

extremes can be used to help explain the relationships

between excessive VS undershoot and the resulting latch−up
mechanism.
In the first case, an “ideal bootstrap circuit” is used in
which VDD is driven from a zero−ohm supply with an ideal
diode feed VB, as shown in Figure 9. When the high current
flowing through freewheeling diode, VS voltage is below
OUTPUT

ground level by high di/dt. This time, latch−up risk appears

since internal parasitic diode, DBS of the gate driver
ultimately enters conduction from VS to VB, causing the
undershoot voltage to sum with VDD, causing the bootstrap
capacitor to overcharge, as shown Figure 10.
For example, if VDD = 15 V, then VS undershoot in excess
Figure 7. Waveforms in Case of Latch−up of 10 V forces the floating supply above 25 V, risking
breakdown in diode DBS and subsequent latch−up.
Figure 8 shows Missing case that the high−side output
does not responded to input transition. In this case, the level

www.onsemi.com
3
 AND9674/D

VB
VS

VDD VB
VB below COM

DBS GND

COM VS
Gate Driver

Figure 12. VB and VS Waveforms of Case 2

Figure 9. Case 1: Ideal Bootstrap Circuits
A practical circuit is likely to fall somewhere between
these two extremes, resulting in both a small increase of VBS
and some VB droop below VDD, as shown in Figure 13.
VB

VS
VB

VS

HIGH VBS GND

VB close to COM
GND
Figure 10. VB and VS Waveforms of Case 1
Increased VBS
Suppose that the bootstrap supply is replaced with the
ideal floating supply, as shown in Figure 11, such that VBS
Figure 13. Typical Response of VB and VS
is fixed under all circumstances. Note that using a low
impedance auxiliary supply in place of a bootstrap circuit
Exactly which of the two extremes is prevalent can be
can approach this situation. This time, latch−up risk appears
checked as follows. If the VS pins undershoot spike has
if VS undershoot exceeds the VBS maximum specified in
a time length that is on order of tenths of nanoseconds; the
datasheet, since parasitic diode DBCOM ultimately enters
bootstrap capacitor, CBOOT, can become overcharged and
conduction from COM to VB, as shown in Figure 12.
the high−side gate−driver circuit has damage by
over−voltage stress because it exceeds an absolute
maximum voltage (VBSMAX) specified in datasheet. Design
to a bootstrap circuit, that does not exceed the absolute
maximum rating of high−side gate driver.
VCC VB Effect of Parasitic Inductances
VCC
The amplitude of negative voltage is:
DBCOM dI
V S * COM + V FD1 * L S2 (eq. 1)
dt
COM VS
To reduce the slope of current flowing in the parasitic
inductances to minimize the derivative terms in Equation 1.
Gate Driver
For example: If L/S MOSFET is FCP20N60, the negative
voltage spike between VS and ground is about −21 V in given
Figure 11. Case 2: Ideal Floating Supply condition such as 0.2 A/ns dI/dt, 100 nH Parasitic inductance
(LS2) and 10 A peak current of freewheeling. Actually,
0.7~0.9 V forward drop (VFD1) at 10 A forward current of
body diode in FCP20N60 is negligeable.

www.onsemi.com
4
 AND9674/D

DESIGN PROCEDURE OF BOOTSTRAP • ILKCAP = 0 (Ceramic Capacitor)

COMPONENTS • IQBS = 120 mA (Maximum)
Select the Bootstrap Capacitor • ILK = 50 mA (Maximum)
The bootstrap capacitor (CBOOT) is charged every time • QLS = 3 nC
the low−side driver is on and the output pin is below the • TON = 25 ms (Duty = 50% at fs = 20 kHz)
supply voltage (VDD) of the gate driver. The bootstrap • ILKDIODE = 10 mA
capacitor is discharged only when the high−side switch is
turned on. This bootstrap capacitor is the supply voltage If the maximum allowable voltage drop on the bootstrap
(VBS) for the high circuit section. The first parameter to take capacitor is 1.0 V during the high side switch on state, the
into account is the maximum voltage drop that we have to minimum capacitor value is calculated by Equation 3.
guarantee when the high−side switch is in on state. The Q Total + (98 10 *9) ) (100 10 *9 ) 120 10 *6 ) 50 10 *6
maximum allowable voltage drop (VBOOT) depends on the ) 10 10 *6) (25 10 *6) ) (3 10 *9)
minimum gate drive voltage (for the high−side switch) to + 105.5 10 *9[C] (eq. 5)
maintain. If VGSMIN is the minimum gate−source voltage,
the capacitor drop must be: The value of bootstrap capacitor is calculated as follows:
V BOOT + V DD * V F * V GSMIN (eq. 2) Q TOTAL 105.5 10 *9
C BOOT + + ` 106[nF] (eq. 6)
ΔV BOOT 1
where:
The voltage drop due to the external diode is nearly 0.7 V.
VDD = Supply voltage of gate driver [V]; and
Assume the capacitor charging time is equal to the high−side
VF = Bootstrap diode forward voltage drop [V]
on−time (duty cycle 50%). According to different bootstrap
The value of bootstrap capacitor is calculated by: capacitor values, the following equation applies:
Q TOTAL Q TOTAL
C BOOT + (eq. 3) DV BOOT +
ΔV BOOT C BOOT
100 nF å DV BOOT + 1.06[V]
where QTOTAL is the total amount of the charge supplied by
the capacitor. 150 nF å DV BOOT + 0.7[V] (eq. 7)
220 nF å DV BOOT + 0.48[V]
The total charge supplied by the bootstrap capacitor is
570 nF å DV BOOT + 0.19[V]
calculated by equation 4:
Q TOTAL + Q GATE ) (I LKCAP ) I LKGS ) I QBS ) I LK ) I LKDIODE)
Suggested values are within the range of 100 nF ~ 570 nF,
t ON ) Q LS (eq. 4)
but the right value must be selected according to the
where: application in which the device is used. When the capacitor
QGATE = Total gate charge; value is too large, the bootstrap charging time slows and the
ILKGS = Switch gate−source leakage current; low−side on time might be not long enough to reach the
ILKCAP = Bootstrap capacitor leakage current; bootstrap voltage.
IQBS = Bootstrap circuit quiescent current;
Select the Bootstrap Resistor
ILK = Bootstrap circuit leakage current;
When the external bootstrap resistor is used, the
QLS = Charge required by the internal level
resistance, RBOOT, introduces an additional voltage drop:
shifter, which is set to 3 nC for all HV
gate drivers; I CHARGE R BOOT
V RBOOT + (eq. 8)
t CHARGE
tON = High−side switch on time; and
ILKDIODED = Bootstrap diode leakage current. where:
ICHARGE = Bootstrap capacitor charging current;
The capacitor leakage current is important only if an
RBOOT = Bootstrap resistance; and
electrolytic capacitor is used; otherwise, this can be
tCHARGE = Bootstrap capacitor charging time
neglected.
(the low−side turn−on time).
For example: Evaluate the bootstrap capacitor value when
the external bootstrap diode used. Do not exceed the ohms (typically 5~10 W) that increase
• Gate Drive IC = FAN7382 (ON Semiconductor) the VBS time constant. This voltage drop of bootstrap diode
• Switching Device = FCP20N60 (ON Semiconductor) must be taken into account when the maximum allowable
voltage drop (VBOOT) is calculated. If this drop is too high
• Bootstrap Diode = UF4007 or the circuit topology does not allow a sufficient charging
• VDD = 15 V time, a fast recovery or ultra−fast recovery diode can be
• QGATE = 98 nC (Maximum) used.
• ILKGS = 100 nA (Maximum)

www.onsemi.com
5
 AND9674/D

CONSIDERATION OF BOOTSTRAP Figure 15. The bootstrap resistor, RBOOT, provides current
APPLICATION CIRCUITS limit only during a bootstrap charging period which
represents when the VS goes below the IC supply voltage,
Bootstrap Startup Circuit VCC, or is pulled down to ground (the low−side switch is
The bootstrap circuit is useful in high−voltage gate driver, turned on and the high−side switch is turned off). The
as shown in Figure 1. However, it has a initial startup and bootstrap capacitor, CBOOT, charge through the bootstrap
limited charging a bootstrap capacitor problem when the resistor, RBOOT, and diode, DBOOT, from the VCC power
source of the main MOSFET (Q1) and the negative bias supply. The bootstrap diode must have a break−down
node of bootstrap capacitor (CBOOT) are sitting at the output voltage (BV) larger than VDC and a fast recovery time to
voltage. Bootstrap diode (DBOOT) might be reverse biased minimize the amount charge feedback from the bootstrap
at startup and main MOSFET (Q1) has a insufficient capacitor to VCC power supply.
turn−off time for the bootstrap capacitor to maintain
a required charge, as shown in Figure 1. VCC VDC
In certain applications, like in battery chargers, the output
RBOOT DBOOT
voltage might be present before input power is applied to the
converter. Delivering the initial charge to the bootstrap
capacitor (CBOOT) might not be possible, depending on the VCC VB
Q1
potential difference between the supply voltage (VDD) and HIN HIN HO
R1
output voltage (VOUT) levels. Assuming there is enough CBOOT R2
LIN LIN VS
voltage differential between input voltage (VDC) and output C1 Q2
R3
voltage (VOUT), a circuit comprised of startup resistor COM LO Load
(RSTART), startup diode (DSTART), and Zener diode (DZ) can R4
solve the problem, as shown in Figure 14. In this startup
circuit, startup diode DSTART serves as a second bootstrap
diode used for charging the bootstrap capacitor (CBOOT) at
power up. Bootstrap capacitor (CBOOT) is charged to the Figure 15. Adding a Series Resistor with DBOOT
Zener diode of DZ, which is supposed to be higher than the
driver’s supply voltage (VDD) during normal operation. The This method has the advantage of being simple for
charge current of the bootstrap capacitor and the Zener limiting the current when the bootstrap capacitor is initially
current are limited by the startup resistor. For best efficiency, charged, but it has some limitations. Duty−cycle is limited
the value of startup resistor should be selected to limit the by the requirement to refresh the charge in the bootstrap
current to a low value, since the bootstrap path through the capacitor, CBOOT, and there are startup problems. Do not
startup diode is permanently in the circuit. exceed the ohms (typically 5∼10 W) that would increase the
VBS time constant. The minimum on−time for charging the
bootstrap capacitor or for refreshing its charge must be
DSTART

RSTART

VDD VDC verified against this time constant. The time constant
RBOOT DBOOT
depends on the values of bootstrap resistance, capacitance,
and duty cycle of switching device calculated in following
equation:
CBOOT

VDD VB
DZ R BOOT C BOOT
INPUT

HO Q1 t+ [s] (eq. 9)
HIN D
RGATE L
COM VS where RBOOT is the bootstrap resistor; CBOOT is the
bootstrap capacitor; and D is the duty cycle.
VOUT
COUT

D
R BOOT C BOOT 10x1 *6
t+ + + 100 [ms] (eq. 10)
D 0.1
Even with a reasonably large bootstrap capacitor and
Figure 14. Simple Bootstrap Startup Circuit resistor, the time constant may be large. This method can
mitigate the problem. Unfortunately, the series resistor does
Resistor in Series with Bootstrap Diode not provide a foolproof solution against an over voltage and
In the first option, the bootstrap circuit includes a small it slows down the recharge process of the bootstrap
resistor, RBOOT, in series with bootstrap diode, as shown in capacitor.

www.onsemi.com
6
 AND9674/D

Resistor Between VS and VOUT VCC VDC

In the second option, the bootstrap circuit includes a small DBOOT
resistor, RVS, between VS and VOUT, as shown in Figure 16.
Suggested values for RVS are in the range of some ohms. IN IN VB

HVIC
CBOOT Q1
VCC VCC
VCC HO
RBOOT DBOOT VOUT
RGATE
CDRV GND VS
L1
IN IN VB DSCHT D1 COUT
HVIC

CBOOT Q1
VCC HO
RGATE VOUT
CDRV
GND VS
RVS L1 Figure 18. Clamping Structure
D1 COUT

Relocated Gate Resistor; Double Purpose

The gate resistor sets the turn−on and turn−off speeds in
Figure 16. Adding RVS in Bootstrap Circuit the MOSFET and provides current limiting for the Schottky
diode during the negative voltage transient of the source
The RVS works as, not only bootstrap resistor, but also terminal of the main switch. In additional, the bootstrap
turn−on and turn−off resistors, as shown in Figure 17. The capacitor is protected against over voltage by the two diodes
bootstrap resistor, turn−on, and turn−off resistors are connected to the ends of CBOOT. The only potential hazard
calculated by the following equations: by this circuit is that the charging current of the bootstrap
R BOOT *+ R BOOT ) R VS (eq. 11) capacitor must go through gate resistor. The time constant of
CBOOT and RGATE slows the recharge process, which might
R ON *+ R GATE ) R VS (eq. 12)
be a limiting factor as the PWM duty cycle.
R OFF *+ R GATE ) R VS (eq. 13) The fourth options includes relocating a gate resistor
between VS and VOUT and a clamp device should be
VCC positioned between ground and VS, as shown in Figure 19,
RBOOT DBOOT where a Zener diode and a 600 V diode are placed. The Zener
IBCHG voltage must be sized according to the following rule:
VB V B * V S t V BS, ABSMAX (eq. 15)
IN IN ITURN−ON
Q1
HO
VCC VCC VDC
CDRV VOUT DBOOT
VS
GND
RVS L1
D1 IN
ITURN−OFF COUT IN VB
HVIC

CBOOT Q1
VDD HO
CDRV

VOUT
Figure 17. Current Paths of Turn−on and Turn−off RGATE
GND VS
DZ L1
D1 COUT
Clamping Diode for VS and Relocation Gate Resistor D2
In the third option, the bootstrap relocates a gate resistor
between VS and VOUT and adds a low forward−voltage drop
Schottky diode from ground to VS, as shown in Figure 18. Figure 19. Clamping Structure with Zener Diode
The difference between VB and VS should be kept inside the
absolute maximum specification in the datasheet and must
be satisfied by the following equation:
V B * V S t V BS_abs max
(eq. 14)

www.onsemi.com
7
 AND9674/D

CHOOSE CURRENT CAPABILITY HVIC b. Sinking Current Capability (Turn−off)

The approximate maximum gate charge QG that can be QG
I SINK w 1.5 (eq. 20)
switched in the indicated time for each driver current rating t SW, OFF
is calculated in Table 1:
where:
QG = MOSFET gate charge at
Table 1. EXAMPLE HVIC CURRENT−DRIVE VGS = VDD;
CAPABILITY tSW_ON/OFF = MOSFET switch turn−on / turn−off
Switching Time (tSW_ON/OFF) time; and
Needed 100 ns 50 ns 1.5 = empirically determined factor
Current (influenced by delay through the
Rating Maximum Gate Charge (QG,MAX)
driver input stages and parasitic
2A 133 nC 67 nC elements).
4A 267 nC 133 nC
9A 600 nC 300 nC
GATE RESISTOR DESIGN PROCEDURE
The switching speed of the output transistor can be
1. For a single 4 A, parallel the two channels of a dual 2 A!
controlled by values of turn−on and turn−off gate resistors
controlling the turn−on and turn−off current of gate driver.
For example, a switching time of 100 ns is:
This section describes basic rules for values of the gate
1 % of the converter switching period at 100 kHz;
resistors to obtain the desired switching time and speed by
3 % of the converter switching period at 300 kHz; etc.
introducing the equivalent output resistor of the gate driver.
1. Needed gate driver current ratings depend on what Figure 20 shows the equivalent circuit of gate driver and
gate charge QG must be moved in switching time current flow paths during the turn−on and turn−off,
tSW−ON/OFF (because average gate current during including a gate driver and switching devices.
switching is IG):
VDC
QG
I G.AV.SW + (eq. 16)
T sw_on ń off HVIC
2. The maximum gate charge, QG, is read from the VB Turn−On
MOSFET datasheet.
RDRV(ON) Cgd
ON
VBS

RGATE 2
If the actual gate−drive voltage VGS is different from
DRIVER

HO
the test condition in the specifications table, use the 1
VGS vs. QG curve instead. Multiply the datasheet OFF Cgs
dVOUT
value by the number of MOSFETs in parallel. dt
3. tSW_ON/OFF is how fast the MOSFET should be VS VOUT
switched. If unknown, start with 2% of the switching
period tSW: VDD
Turn−Off dVOUT
0.02 (eq. 17) Cgd dt
t SWON, OFF + 0.02 t SW + OFF
VDD

f SW 1
RG(ON)
DRIVER

If channel (V−I) switching loss is dominated by one LO Cds

switching transition (turn−on or turn−off), size the 2
driver for that transition. For clamped inductive ON RDRV(OFF) Cgs
RG(OFF)
switching (the usual case), channel switching loss GND
for each transition is estimated as:
E SW + 0.5 V DS ID t SW [Joules] (eq. 18)
where VDS and ID are maximum values during the Figure 20. Gate Driver Equivalent Circuit
switching interval.
4. The approximate current drive capability of gate Figure 21 shows the gate−charge transfer characteristics
driver may be calculated like below of switching device during turn−on and turn−off.
a. Sourcing Current Capability (Turn−on):
QG
I SOURCE w 1.5 (eq. 19)
t SW, ON

www.onsemi.com
8
 AND9674/D

The following describes how to size the turn−off resistor

VDS − Drain−Source Voltage [V]

VGS − Gate−Source Voltage [V]

VDS
TON_Charge TOFF_Discharge when the output dv/dt is caused by the companion MOSFET
ID
TSW turning−on, as shown in Figure 22.
90%
90%
For this reason, the off−resistance must be sized according
VGG
to the application worst case. The following equation relates
the MOSFET gate threshold voltage to the drain dv/dt:
VGS Vg1

Vg2 VDC
Vg2
Vg1 10% 10% HVIC

VB Turn−On
TD(ON) tR TD(OFF) tF Q[nC]
ON Cgd
RDRV(ON)

VBS
Figure 21. Gate Charge Transfer Characteristics RGATE 2

DRIVER
HO
Sizing the Turn−On Gate Resistor 1
OFF Cgs dVOUT
Turn−on gate resistor, Rg(ON), can be chosen to obtain the dt

Load
desired switching time by using switching time, tsw. To VS
ILOAD
determine a value of resistor using the switching time,
VDD
supply voltage, VDD (or VBS), equivalent on resistance Turn−Off
(RDRV(ON)) of the gate driver, and switching device OFF Cgd

VDD
parameters (Qgs, Qgd, and Vgs(th)) are needed. RG(ON)

DRIVER
The switching time is defined as the time spent to reach the LO Cds
end of the plateau voltage (a total Qgs + Qgd has been RDRV(OFF)
ON Cgs
provided to the MOSFET gate), as shown in Figure 21. RG(OFF)
The turn−on gate resistor calculated as follows:
GND
Q gs ) Q gd
I g(avr) + (eq. 21)
t SW
Figure 22. Current Paths: Low−Side Switch
V DD ) V gs Turned Off, High−Side Switch Turned On
R TOTAL + R g(ON) ) T DRV(ON) + (eq. 22)
Ig(avr)
NJ
V gs(th) w (R g(OFF) ) R DRV(OFF)) ig Nj
where Rg(ON) is the gate on resistance and RDRV(ON) is the
driver equivalent on resistance. NJ
+ (R g(OFF) ) R (drv) C gd
dV out
dt
Nj (eq. 25)

Output Voltage Slope

Turn−on gate resistor Rg(ON) can be determined by control Rearranging the equation yields:
output slope (dVOUT/dt). While the output voltage has V gs(th)
a non−linear behavior, the maximum output slope can be R g(off) v * R (drv) (eq. 26)
dV out
approximated by: C gd
dt
dV OUT I g(avr)
+ (eq. 23)
dt C gd(off) Design Example
Determine the turn−on and off gate resistors using the
Inserting the expression yielding Ig(avr) and rearranging: ON Semiconductor MOSFET with FCP20N60 and gate
V DD * V gs(th) driver with FAN7382. The power MOSFET of FCP20N60
R TOTAL + (eq. 24)
dV OUT parameters are as follows:
C gd(off)
dt Q gs + 13.5 nC, Q gd + 36 nC, C gd + 95pF,
(eq. 27)
where Cgd(off) is the Miller effect capacitor, specified as Crss V GS(th) + 5 V, V GS(th)MIN + 3 V
in the datasheet.
Turn−On Gate Resistance
Sizing the Turn−Off Gate Resistor 1. If the desired switching time is 500 ns at VDD = 15 V,
The worst case in sizing the turn−off resistor is when the the average gate charge current is calculated as:
drain of the MOSFET in turn−off state is forced to Q gs ) Q gd 36 nC ) 13.5 nC
commutate by external events. I g(avr) + + ns + 99 [mA] (eq. 28)
t SW 500
In this case, dV/dt of the output node induces a parasitic
current through Cgd flowing in RG(OFF) and RDRV(OFF), as V DD ) V gs(th) 15 * 5
R Total + + + 101 [W] (eq. 29)
shown in Figure 22. I g(avr) 99 mA

www.onsemi.com
9
 AND9674/D
1
V DD 15 V
R DRV(ON) + + + 43 [W] (eq. 30)
I SOURCE 350 mA
C LOAD =4400PF
The turn−on resistance value is about 58 Ω.
2. If dVout/dt = 1 V/ns at VDD = 15 V, the total gate
resistor is as calculated as: C LOAD =2200PF

Power [W]
V DD * V GS(th) 15 * 5 0.1 C LOAD =1000PF
R Total + + (eq. 31)
dV out 95x10 *12x10 9
C gd(off) C LOAD =470PF
dt
V DD 15 V
R DRV(ON) + + + 43 [W] (eq. 32)
I SOURCE 350 mA
The turn−on resistance value is about 62 Ω. 0.01

Turn−Off Gate Resistance

If dVout/dt = 1 V/ns, the turn−off gate resistor is calculated 0.1 1 10 100 1000

as: Switching frequency [kHz]

V DD 15 V
R DRV(OFF) + + [ 23[W] (eq. 33) Figure 23. Gate Driver Total Power Dissipation
I SINK 650 mA

V gs(th)min
R g(off) v * R (drv) +
3
* 23 + 8.6 The bootstrap circuit power dissipation is the sum of the
dV out 95x10 *12x10 9 bootstrap diode losses and the bootstrap resistor losses if any
C gd
dt (eq. 34) exist. The bootstrap diode loss is the sum of the forward bias
power loss that occurs while charging the bootstrap
POWER DISSIPATION CONSIDERATIONS capacitor and the reverse bias power loss that occurs during
reverse recovery. Since each of these events happens once
Gate Driver Power Dissipation per cycle, the diode power loss is proportional to switching
The total power dissipation is the sum of the gate driver frequency. Larger capacitive loads require more current to
losses and the bootstrap diode losses. The gate driver losses recharge the bootstrap capacitor, resulting in more losses.
are comprised of the static and dynamic losses related to the Higher input voltages (VDC) to the half−bridge result in
switching frequency, output load capacitance on high− and higher reverse recovery losses. The total IC power
low−side drivers, and supply voltage, VDD. dissipation can be estimated by summing the gate driver
The static losses are due to the quiescent currents from the losses with the bootstrap diode losses, except bootstrap
voltage supplies VDD and ground in low−side driver and the resistor losses.
leakage current in the level shifting stage in high−side driver, If the bootstrap diode is within the gate driver, add an
which are dependent on the voltage supplied on the VS pin external diode in parallel with the internal bootstrap diode
and proportional to the duty cycle when only the high−side because the diode losses can be significant. The external
power device is turned on. diode must be placed close to the gate driver to reduce
The dynamic losses are defined as follows: In the parasitic series inductance and significantly lower forward
low−side driver, the dynamic losses are due to two different voltage drop.
sources. One is due to whenever a load capacitor is charged
or discharged through a gate resistor, half of energy that goes Package Thermal Resistance
into the capacitance is dissipated in the resistor. The losses The circuit designer must provide:
in the gate drive resistance, internal and external to the gate • Estimate power dissipation of gate driver package
driver, and the switching loss of the internal CMOS • The maximum operating junction temperature
circuitry. Also, the dynamic losses of the high−side driver TJ, MAX,OPR, e.g., 120°C for these drivers if derated to
have two different sources. One is due to the level−shifting 80% of TJ,MAX =150°C
circuit and one due to the charging and discharging of the
capacitance of the high side. The static losses are neglected
• Maximum operating lead temperature TL,MAX,OPR,
approximately equal to the maximum PCB temperature
here because the total IC power dissipation is mainly
dynamic losses of gate drive IC and can be estimated as: underneath the driver, e.g., 100°C
2
• Maximum allowable junction−to−lead thermal resistance
P DGATE + 2 CL fs V DD [W] (eq. 35)
is calculated by:
Figure 23 shows the calculated gate driver power T J, max ) T L, max
dissipation versus frequency and load capacitance at VDD = q JL, max +
R PKG
(eq. 36)
15 V. This plot can be used to approximate the power losses
due to the gate driver

www.onsemi.com
10
 AND9674/D

GENERAL GUIDELINES
Printed Circuit Board Layout Bootstrap Components
The layout for minimized parasitic inductances is as The bootstrap resistor (RBOOT) must be considered in
follows: sizing the bootstrap resistance and the current developed
• Direct tracks between switches with no loops or deviation during initial bootstrap charge. If the resistor is needed in
• Avoid interconnect links. These can add significant series with the bootstrap diode, verify that VB does not fall
inductance below COM (ground), especially during startup and
extremes of frequency and duty cycle.
• Reduce the effect of lead−inductance by lowering
The bootstrap capacitor (CBOOT) uses a low−ESR
package height above the PCB
capacitor, such as ceramic capacitor. The capacitor from
• Consider co−locating both power switches to reduce track VDD to COM supports both the low−side driver and
length bootstrap recharge. A value at least ten times higher than the
• Placement and routing for decoupling capacitor and gate bootstrap capacitor is recommended.
resistors as close as possible to gate drive IC The bootstrap diode must use a lower forward voltage
• The bootstrap diode as close as possible to bootstrap drop and switching time as soon as possible for fast recovery,
capacitor such as ultra−fast.

Table 2. SUMMARY OF HIGH−SIDE GATE DRIVE CIRCUITRY

Method Basic Circuit Advantages & Limitations
HIGH−SIDE GATE DRIVERS FOR P−CHANNEL
VCC
Direct Drive Can be implemented if the maximum input voltage is
RGATE
VCC less than the gate−to−source break down voltage of
Controller

Q1 the device
PWM

OUT
VOUT

GND L1
COUT

D1 VOUT

VCC VDC
Open Collector Simple method, but is not suitable for driving
RPULL

VCC
MOSFET directly in a high−speed application
Controller

Q1
OUT
PWM

RGATE

VOUT
GND L1
COUT

D1 VOUT

VDC
Level−Shifted Drive Suitable for high−speed application and works
seamlessly with regular PWM controller
RBASE

VCC R1

VCC R2 VOUT
Controller

COUT

OUT L1
PWM

D1 VOUT

GND

HIGH−SIDE GATE DRIVERS FOR N−CHANNEL

VCC VDC
Direct Drive Easiest high−side application the MOSFEF and can
be driven directly by the PWM controller or by a
RGATE

VCC
Q1 ground referenced driver, but it must meet two
Controller

OUT
PWM

VOUT
conditions, as follows:
DSCHT

GND L1 V CC t V GS, MAX and V DC t V CC * V GS, Miller

COUT

D1 VOUT

VCC VDC
Floating Supply Gate Cost impact of isolated supply is significant.
RGATE

Drive VCC
Floating
Q1
Opto−coupler tends to be relatively expensive,
HO Opto
Supply
limited in bandwidth, and noise sensitive
VOUT
Controller
PWM

L1
RGATE
COUT

LO Q2 VOUT

GND

www.onsemi.com
11
 AND9674/D

Table 2. SUMMARY OF HIGH−SIDE GATE DRIVE CIRCUITRY (continued)

Method Basic Circuit Advantages & Limitations
HIGH−SIDE GATE DRIVERS FOR N−CHANNEL
VCC VDC
Transformer Coupled Gives full gate control for an indefinite period of time,

CBLOCK
Drive VCC T1 RGATE
Q1 but is somewhat limited in switching performance.
VOUT This can be improved with added complexity

Controller
PWM
OUT1 RGATE L1

COUT
OUT2
VOUT

GND

VCC VDC
Charge Pump Drive The turn−on times tend to be long for switching
VCC
applications. Inefficiencies in the voltage
multiplication circuit may require more than low
Controller

OUT Q1
PWM

VOUT stages of pumping

L1

COUT
GND
D1 VOUT

VCC VDC
Bootstrap Drive DBOOT
Simple and inexpensive with limitations; such as, the
duty cycle and on−time are both constrained by the
CBOOT

IN IN
VB need to refresh the bootstrap capacitor.
HVIC

Q1
VCC HO
Requires level shift, with the associated difficulties
CDRV RGATE L1
VS
GND

D1 COUT VOUT

www.onsemi.com
12
 AND9674/D

Consideration Points of Bootstrap Circuit Problem

A−Point VBS
VCC
DBOOT

B−Point VDC + VGS, Miller

VDC

INPUT IN VB C−Point VDC

CBOOT
HVIC VBS = (VCC + VFBD) − (−VS) Recovery Time
Q1
VCC HO A B VGS = B − C
RGATE Point
CDRV
LS1 i LOAD
GND VS C C

LS2 i Free
GND
COUT
−VS D1

Negative voltage transient

at high−side switch turn−off
Latch−up,
propagation signal
missing and over−
If Vs goes significantly below
voltage across the
ground, the gate driver can
bootstrap
have serious troubles
capacitor

The amplitude of the negative voltage is proportional

parasitic inductances and the turn−off speed (di/dt) of
the switching device, Q1, which is determined by gate
resistor, RGATE, and input capacitance, CISS

Figure 24.

www.onsemi.com
13
 AND9674/D

Remedies of Bootstrap Circuit Problem

Figure 25.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: TECHNICAL SUPPORT
Email Requests to: [email protected] North American Technical Support: Europe, Middle East and Africa Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 00421 33 790 2910
ON Semiconductor Website: www.onsemi.com Phone: 011 421 33 790 2910 For additional information, please contact your local Sales Representative

◊ www.onsemi.com
14