Tuning the threshold voltage in electrolyte-gated

organic field-effect transistors

Loïg Kergoata, Lars Herlogssonb, Benoit Piroc, Minh Chau Phamc, Gilles Horowitzd, Xavier Crispina, and
Magnus Berggrena,1
a
Department of Science and Technology, Organic Electronics, Linköping University SE-601 74 Norrköping, Sweden; bThin Film Electronics AB,
Westmansgatan 27, SE-582 16 Linköping, Sweden; cLaboratoire Interfaces, Traitements, Organisation et Dynamique des Systèmes-Unité Mixte de
Recherche Conseil National de la Recherche Scientifique 7086, Université Paris Diderot- Sorbonne Paris Cité, FR-75205 Paris Cedex 13, France; and
d
Laboratoire de Physique des Interfaces et Couches Minces-Unité Mixte de Recherche Conseil National de la Recherche Scientifique 7647, Ecole
polytechnique, FR-91128 Palaiseau, France

Edited by Tobin J. Marks, Northwestern University, Evanston, IL, and approved April 18, 2012 (received for review December 9, 2011)

Low-voltage organic field-effect transistors (OFETs) promise for gate insulator material is that the switching speed is reduced. This
low power consumption logic circuits. To enhance the efficiency is a result of the slow ion polarization within the electrolyte; how-
of the logic circuits, the control of the threshold voltage of the tran- ever, polyelectrolyte-gated OFETs exhibit relatively fast switching
sistors are based on is crucial. We report the systematic control of speed (about 10 μs for short-channel devices) (18) and can be
the threshold voltage of electrolyte-gated OFETs by using various integrated into circuits with delay times of 300 μs (19).
gate metals. The influence of the work function of the metal is One of the most important device parameters in field-effect
investigated in metal-electrolyte-organic semiconductor diodes transistors is the threshold voltage V TH , which marks the gate
and electrolyte-gated OFETs. A good correlation is found between voltage where a conducting channel forms between the source
the flat-band potential and the threshold voltage. The possibility to and drain electrodes. The corresponding energy diagram is shown
tune the threshold voltage over half the potential range applied in the bottom of Fig. 1B. Because organic semiconductors used
and to obtain depletion-like (positive threshold voltage) and en-
in OFETs are nonintentionally doped, only two regimes can be
hancement (negative threshold voltage) transistors is of great
found at both sides of the flat-band voltage V FB that corresponds
interest when integrating these transistors in logic circuits. The
to the gate voltage V GS where bands are flat all over the semi-
combination of a depletion-like and enhancement transistor leads
to a clear improvement of the noise margins in depleted-load uni-
conductor layer. The two regimes correspond to electron accumu-
polar inverters. lation when V GS > V FB and hole accumulation when V GS <
V FB ; however, the existence of both of these regimes is actually
organic electronics ∣ polyelectrolytes ∣ thin-film transistors ∣ gate electrode constrained by the possibility to inject the appropriate charge car-
material riers from the source electrode. Because gold is unlikely to inject
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electrons in P3HT due to a too high-energy barrier, the electron

accumulation regime is replaced by a regime where the semicon-
T he possibility to process organic electronic materials from
solution allows for printing electronic systems on a wide vari-
ety of large area and flexible substrates thus enabling new appli-
ductor layer behaves as a dielectric. For this reason, the regime
at V GS > V FB will be termed “dielectric” and is illustrated by a
cations and ultralow cost electronics (1–3). The transistor is a linear variation of the electric potential (constant electric field)
corner stone in modern electronics. The OFETs are promising across the film. The hole accumulation regime is marked by a
devices for applications that require medium-speed operation small bend bending at the insulator-semiconductor interface that
such as driving circuits for displays (4) and sensors (5, 6); how- mirrors the accumulation of free charges there.
ever, to enable their integration in portable devices or electronic The flat-band potential can be estimated by measuring the
labels, i.e., distributed systems typically driven by printed bat- photo potential as a function of the intensity of light illumination
teries (7) or solar cells (8), the OFETs should operate at low or the onset of the photocurrent. Its value is given by Eq. 1 where
voltage and power. A low driving voltage can be achieved by em- W M and W s are the gate and semiconductor work functions,
ploying a gate dielectric composed of a ultrathin, cross-linked respectively. q is the elementary charge, Qis is the interface
polymer (9), a self-assembled monolayer in combination with a charge density, and Ci is the capacitance of the insulator layer
thin metal oxide layer (10), or high-permittivity dielectrics (11); (per unit area).
however, high-quality inorganic dielectrics or ultrathin organic
dielectrics are normally difficult to combine with common print- W M − W S Qis
ing technologies. Recently, various electrolytes have successfully V FB ¼ − [1]
q Ci
been explored as the gate insulator in low-voltage operating
OFETs (12–17). In this case, the formation of the gate capaci-
An additional difference between the flat-band and threshold
tance includes polarization of electronic and ionic charges.
voltages stems from an energy distribution of localized levels near
Indeed, if we consider a p-channel OFET, applying a negative
voltage to the gate attracts cations from the solution towards the the transport band edge that act as shallow traps for charge car-
electrolyte/gate interface while anions are repelled towards the riers (20–22). As the gate voltage increases, the traps become
electrolyte/semiconductor interface. Such ion redistribution re- filled, and the charge carriers start to drift in the transport band.
sults in the formation of electrical double layers (EDLs) at the
two interfaces. These two EDLs can be assimilated to two capa- Author contributions: L.K., L.H., X.C., and M.B. designed research; L.K. performed research;
citors in series in which the redistributed ions in the electrolyte L.K. and G.H. analyzed data; and L.K., L.H., B.P., M.C.P., G.H., X.C., and M.B. wrote
are balanced by oppositely charged electronic charge carriers at the paper.
the gate electrode and in the semiconductor, respectively The authors declare no conflict of interest.
(Fig. 1A). The ionic and electronic charges within these EDLs This article is a PNAS Direct Submission.
are separated by only a few Å resulting in a very high capacitance 1
To whom correspondence should be addressed. E-mail: [email protected].
(typically above 1 μFcm −2 ) that allows OFETs to operate below This article contains supporting information online at www.pnas.org/lookup/suppl/
1 V; however, one major drawback of using an electrolyte as the doi:10.1073/pnas.1120311109/-/DCSupplemental.

8394–8399 ∣ PNAS ∣ May 29, 2012 ∣ vol. 109 ∣ no. 22 www.pnas.org/cgi/doi/10.1073/pnas.1120311109

 APPLIED PHYSICAL
SCIENCES
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Fig. 1. Metal-Electrolyte-Semiconductor diode. (A) Schematic cross-section of the MES diode with the chemical formulae of P3HT and P(VPA-AA) and a sche-
matic representation of charge distribution in the system capacitor. The red features represent the polyanionic chains and the blue circles the mobile protons.
(B) Energy diagram of the different regimes of a metal-insulator-semiconductor stack. (C) Plot of the effective capacitance as a function of the voltage for six
metals: Au (full squares), Ni (open squares), Cu (full circles), Ti (open circles), Al (full triangles), and Ca (open triangles). (D) Variation of the charge carrier density
as a function of the gate voltage.

Ways to adjust the threshold voltage include the use of a sec- ination. In our devices, the gate consists of a metal film evapo-
ond gate electrode (23) modifying the insulator-semiconductor rated on top of the polyelectrolyte resulting in unavoidable
interface with dipolar molecules (24) and doping the semiconduc- degradations of the metal surface and subsequent modifications
tor (25). Furthermore, recent reports show that changing the gate of the work function. Furthermore, the geometry of the device
electrode material may lead to a slight shift of V TH (26). prevents any direct estimation of the actual work function,
In this paper, we report on a systematic control of V TH in poly- e.g., photoelectron spectroscopy or Kelvin probe measurements.
electrolyte-gated OFETs by changing the metal of the gate. Instead, we conducted capacitance-voltage measurements on
Because the operating voltage in these devices is comparable to capacitors made by stacking P3HT and the polyelectrolyte P
the respective variation of the work function, it is possible to tune (VPA-AA) between two metal electrodes (Fig. 1A). In all cases,
the threshold voltage over the whole potential window by chan- the bottom electrode is made of gold. The effective area of the
ging the metal of the gate. In addition, we use the concept of diode was 0.04 mm 2 . The capacitance of the diode was measured
V TH -tuning to optimize the transition regime in depleted-load as a function of the applied voltage at a frequency of 1 kHz. The
logic inverters. curves in Fig. 1C, which represent the data for six different metals
(i.e., gold, nickel, copper, titanium, aluminum, and calcium) be-
Results and Discussion have differently from what is usually found in conventional semi-
Metal-Electrolyte-Organic Semiconductor Diodes. According to conductor diodes where the voltage-dependent capacitance is
Eq. 1, the flat-band potential linearly depends on the work func- explained in terms of modulation of a space-charge layer (27).
tion of the gate. The work functions usually found in tables are Instead, the capacitance remains independent of the voltage
measured in high vacuum in order to avoid any surface contam- up to a point where it abruptly increases to reach a second, higher

Kergoat et al. PNAS ∣ May 29, 2012 ∣ vol. 109 ∣ no. 22 ∣ 8395
 gate-voltage independent value. We explain this shape in terms of and the channel length and width are 2 μm and 15 mm, respec-
the model depicted in Fig. 1B that was detailed above. In the first tively. The gate area is 0.42 mm 2 , which is much higher than that
regime, which corresponds to V GS > V FB , the semiconductor of the transistor channel (0.03 mm 2 ) so that the resulting capaci-
layer behaves as a dielectric because electrons cannot be injected tance is always that of the double-layer at the P3HT side whichever
from gold. Furthermore, proton penetration into the semicon- the nature of the metal at the gate. The transfer characteristic is
ductor bulk is unlikely due to the hydrophobicity of P3HT. This presented for OFETs with Au and Ca-gate electrodes (Fig. 2B).
is confirmed with our capacitance measurement SI Text. Accord- Both transistors show typical p-channel behavior. The transistor
ingly, we have two capacitances (C1 and C2) in series. Because with an Au-gate switches on at a positive V GS , whereas the tran-
the P3HT layer is thicker than the electrical double-layer at the sistor including a Ca gate turns on at a relatively more negative
metal electrode, its respective capacitance is lower. When two V GS . These results are in line with the corresponding flat-band
capacitances are in series, the total capacitance is dominated by potentials. As a result, the drain current of the transistor with
the smallest one, C2 in that case. We note that the value of the an Au-gate is 500 times higher than that of the device with a
capacitance in this voltage range is in line with that of the P3HT Ca-gate at V GS ¼ 0 V. The output curves are presented for both
layer (ca. 0.1 μF∕cm 2 for a 30 nm thick layer with a dielectric con- transistors (Au, Fig. 2C, Ca, and Fig. 2D). The superlinear shape of
stant of 3). Below V FB , accumulation of holes takes place and the the output curves at high V GS and low V DS is attributed to contact
P3HT film becomes conductive, so that the total capacitance re- resistance. The threshold voltage V TH can be extracted from the
flects the double layers that form at the electrolyte-semiconductor transfer curve plotted in the linear scale (SI Text). It is important to
interface (capacitor C4). Note that because metal-electrolyte C4 extract it from the linear regime, where the charge distribution is
and semiconductor-electrolyte double-layer C3 capacitances have uniform along the channel and not from the saturation regime
identical area, the presence of a thin-oxide layer at the surface where a nonuniform charge density within the channel may lead
of reactive metals (Ca, Al, and Ni) might lead to a situation where to an erroneous extraction. The extrapolation in the linear regime
C3 < C4, which could explain the deviation of the measured (ELR) method is used to extract the threshold voltage, and the
capacitance compared to the other metals (Au, Cu, and Ti). resulting threshold voltage is plotted as a function of the flat-band
Based on this model, the flat-band voltage V FB can be esti- potential for all six metals (solid black line, Fig. 2E) and as a func-
mated as the onset of the capacitance increase that would corre- tion of the gate work function SI Text. Five transistors were char-
spond to the onset of hole accumulation. The extracted values are acterized for each metal in order to obtain statistical data. A clear
listed in Table 1 and plotted as a function of the gate work func- linear dependence is found with a slope close to unity between the
tion SI Text. The values span over 0.7 V when passing from gold threshold voltage and the flat-band potential.
to calcium. The threshold voltage is extracted from the C-V The deviation of the V TH from the V FB is tentatively attribu-
curves by estimating the charges QðV Þ transported through the ted to the presence of charge traps. We find two tentative expla-
P3HT layer in the accumulation regime (V < V FB ) from Eq. 2: nations for the difference between V TH determined from the
capacitance (V TH capa ) and the transfer curve of the transistor
Z V (V TH tran ). One might come from an erroneous extraction of
QðV Þ ¼ − CðV ÞdV [2] V TH tran due to the method used. Indeed, the ELR method is
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−V FB
sensitive to gate leakage in short-channel devices and might lead
QðV Þ is converted in a density of charge carriers at the to an overestimation of V TH . On the other hand, in the case of Ni,
Al, and Ca, the resulting capacitance in the accumulation regime
semiconductor-electrolyte interface and plotted versus voltage
is that of the (oxidized) metal instead of that of the double-layer
(Fig. 1D). If we assume that the mobility is little dependent on
at the P3HT electrode could lead to an inaccurate estimation of
the gate voltage, then the drain current in a transistor is propor-
V TH capa . For the devices presented, the V TH variation extends
tional to the density of charge carriers. Fig. 1D displays clear
over almost 1 V, which corresponds to half of the entire operating
subthreshold regimes in which traps limit the current and an
voltage regime.
above-threshold regime where all traps are filled leading to an
increased current. The threshold voltage is estimated by extrapo-
Unipolar Inverters Based on Electrolyte-Gated OFETs. The ability to
lating the above-threshold straight line to zero current. The cor-
tune the V TH of an OFET is of great interest when designing in-
responding data are given in Table 1 and plotted versus the flat-band
tegrated circuits. Complementary circuit design, which includes
potential in Fig. 2E and as a function of the gate work function SI n- and p-channel transistors, dominates the electronic industry
Text. Note that the slope of the line should be proportional to the today; however, unipolar circuits are generally easier to manufac-
charge carrier mobility. Parallel lines indicating equal mobility are ture and are sufficient for analyzing the impact of the modifica-
indeed observed with Au, Ti, and Cu. The decrease of the slope with tion of the V TH . Hence, in this work, logic inverters, in many
Ni, Al, and Ca is an artifact coming from the fact that the capaci- respects the simplest kinds of integrated circuits, that use a uni-
tance is limited by the metal-electrolyte interface. polar circuit design are analyzed. An inverter has two compo-
nents: a load (L) and a driver (D). The driver is a transistor,
Influence of the Gate Metal on Electrolyte-Gated OFETS. Our electro-
typically of enhancement mode type, whereas the load can be
lyte-gated OFETs are manufactured in a bottom-contact, top-gate a resistor or another transistor. Two load transistor configurations
configuration. Interdigitated electrodes are used here (Fig. 2A), are possible: the diode-load and the depleted-load (or zero-gate
load). The latter configuration shows better static behavior but is
Table 1. Data extracted from C-V and transistor
typically slower to switch (28), and is used in this work. In the
measurements for the various metals
depleted-load configuration (Fig. 3A inset), the gate of the load
Metal V FB (V) V TH capa (V) V TH tran (V) transistor is connected to its own source; thus, V GS ¼ 0 V at all
Au 0.73 0.41 0.40 ± 0.08 times. As long as V OUT > V DD þ V TH;L , V OUT (being the output
Ni 0.65 0.42 0.31 ± 0.10 voltage), V DD (the supply voltage), and V TH;L the threshold
Cu 0.52 0.15 0.28 ± 0.14 voltage of the load transistor, the current through the load in-
Ti 0.31 0.09 −0.14 ± 0.10 creases linearly with the voltage. When V OUT < V DD þ V TH;L
Al 0.26 0.10 −0.19 ± 0.15 the current saturates. The load and driver transistors can simply
Ca 0.08 −0.15 −0.53 ± 0.07 be seen as two resistors connected in series. The basic working
The error in V TH tran is the standard deviation obtained from five mechanism of the inverter is input control over voltage division.
transistors Thus, adjusting the resistance of the driver transistor via the input

8396 ∣ www.pnas.org/cgi/doi/10.1073/pnas.1120311109 Kergoat et al.

 A B C

D E

Fig. 2. Electrolyte-gated OFETs with various metals. (A) Schematic representation of the OFET. (B) Transfer characteristics, in the linear regime (V DS ¼ −0.01 V)
and at saturation (V DS ¼ −1.2 V) for electrolyte-gated OFETs with Au (full line) and Ca (dashed line) as gate metal. Output characteristics for electrolyte-gated
OFET with (C) Au and (D) Ca as gate metal. (E) Variation of the threshold voltage extracted from the capacitance, V TH capa , (empty squares) and transistor
measurements, V TH tran , (full black squares) as a function of the flat-band potential. The dotted and full lines are linear fits with a slope of 1 to the data

APPLIED PHYSICAL
corresponding to capacitance and transistor measurements, respectively. The dashed line represents the ideal case where V TH ¼ V FB .

SCIENCES
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A B C

D E

Fig. 3. Inverters based on electrolyte-gated OFETs with various metals. Characteristics of inverters having Cu as the gate electrode metal. (A) Output curves
(full lines) for the driver transistor together with the load line (dashed line) of the load transistor. The inset shows a schematic representation of the inverter
circuit. (B) Voltage-transfer characteristics and (C) signal gain of the inverter for supply voltages ranging from −0.6 to −1.4 V. The inset in (C) indicates the key
parameters of an inverter. (D) Influence of a change in the load to driver channel width ratio (from 2 to 10). (E) Modification of the signal gain of an inverter
with Au as the gate metal for the load and Au, Cu, or Ca as the gate metal for the driver.

Kergoat et al. PNAS ∣ May 29, 2012 ∣ vol. 109 ∣ no. 22 ∣ 8397
 voltage essentially controls the inverter output voltage. For exam- switching threshold voltage that makes it unsuitable for use in
ple, for an input voltage close to 0 V, the driver and the load have logic circuits. Using a driver transistor with a copper gate elec-
V GS ¼ 0 V. Because the load is a depletion-like transistor that is trode that has a positive V TH but that is smaller than that for
already on at 0 V, the channel resistance of the driver transistor is an Au-gate shifts the switching threshold towards more negative
high and larger than that of the load transistor. Consequently, the voltages allowing it to be used in logic circuits; however, the
voltage drop will mainly occur over the driver giving an output ideal V DD ∕2 (i.e. −0.7 V) value is far from being reached.
voltage close to the supply voltage (V DD ). For an input voltage The use of a driver transistor with a negative V TH such as the
close to V DD , the driver is strongly switched on and its channel one with a Ca gate should diminish this problem. The OFET with
resistance is low and smaller than that of the load that sets the a Ca-gate electrode exhibit a much more negative V TH (V TH ¼
output node close to 0 V. Ideally, the voltage swing, i.e., the vol- −0.53 V) resulting in a high-channel resistance at low-input vol-
tage difference between the high and low output levels, should be tages. By changing from an Au to a Ca-gate electrode in the driver
equal to the supply voltage. The current through the load (dashed transistor leads to a shift of the inverter switching (gain maxi-
line) and through the driver (solid lines) of an inverter based on mum) from þ0.3 V to −0.36 V. For this W -L configuration, it
transistors with copper gate electrodes are presented in Fig. 3A. should be possible to shift the gain maximum further towards
Because, in an inverter, the current through the load and the dri- V DD ∕2 (−0.7 V) by using a metal with a work function even high-
ver should be the same, the intersection of the two curves deter- er than that of Au, for instance using Pt as the gate electrode
mines the value of V OUT for a given V IN . The voltage-transfer material in the load transistor. Off course, another strategy is
characteristic (VTC) of the inverter, i.e., the output voltage to choose a metal electrode with a lower work function than that
(V OUT ) as a function of the input voltage (V IN ), is displayed of Ca for the gate of the driver transistor. Moreover, a semicon-
in Fig. 3B. The VTC gives information about the static perfor- ductor with a relatively higher ionization potential should shift
mance of the inverter. In our case, the high output level is close the voltages to more negative values.
to V DD , but the low output level at high V IN is noticeably larger
than 0 V. This is likely an effect of the superlinear output curves Conclusions
caused by a high contact resistance of the driver transistor. An- In summary, systematic control of the threshold voltage in poly-
other key parameter for inverters is the signal gain, which is de- electrolyte-gated OFETs has been demonstrated by changing
fined as A ¼ jδV OUT ∕δV IN j (Fig. 3C inset). Inverters that show a the work function of the gate electrode. It is possible to shift the
gain larger than unity can be used for driving other gates in logic threshold voltage by as much as 0.9 V when changing from Au to
circuits. The switching threshold, which is the voltage at which the Ca. This equals half of the entire operation voltage range of the
inverter switches from low to high output and displays maximum electrolyte-gated OFETs studied. Tuning the threshold is of gen-
gain, should ideally coincide with the trip point and be positioned eral interest in designing analogue and digital circuits. In parti-
at half of the supply voltage in order to provide optimum noise cular, threshold voltage tuning is of importance in the case of
margins. For the inverter in Fig. 3B, the transition occurs for an zero-load inverters where positive and negative threshold vol-
input voltage of only about −0.1 V that is due to the positive tages are advantageous for the load and driver transistors, respec-
threshold voltage of the driver transistor, leads to poor noise mar- tively. This implies that the dimensional ratio of the load and the
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gins. Various methods have been investigated to remedy this is- driver transistor channels is no longer of significant importance,
sue. The most common one is to increase the resistance of the which then enables size reduction of circuits.
driver transistor by reducing its channel width (relative to that
of the load transistor). Typically, a ratio of 10 is chosen between Materials and Methods
the load and the driver channel width. The gain for inverters with Materials. Regioregular P3HT (electronic grade, 99.995% trace metal basis)
various channel width ratios is shown Fig. 3D. When increasing was purchased from Sigma-Aldrich, dissolved in 1,2-dichlorobenzene
(10 mg·ml −1 ), and filtered with a 0.2 μm polytetrafluoroethylene syringe fil-
this ratio from two to 10, the switching threshold is shifted from
ter. P(VPA-AA) was purchased from Rhodia, dissolved in a mixture of water
−0.1 V to −0.3 V, which provides better noise margins. A down- and 1-propanol (40 mg·ml −1 ) with a solvent ratio of 1∶4, and filtered with a
side of this approach is that one transistor becomes much larger 0.2 μm nylon syringe filter
than the other, which limits miniaturization of the system. The
use of a level-shifter is another widespread method that requires Device Manufacturing. 5 nm thick titanium (attachment layer) and 50 nm thick
two additional transistors and an additional power supply (29). gold films were formed on borosilicate glass substrates (DESAG D263). Con-
Other methods aim at adjusting the V TH of the driver and load tacts are defined by photolithography and wet etching. For the capacitor
transistors. The driver transistor should have a negative threshold structure, the effective surface is 0.0004 cm 2 . For the transistor structure, in-
voltage in order for its resistance to be high at low-input voltages; terdigitated source and drain electrodes are used, with a channel length and
however, the load transistor should operate in a depletion-like width of 2–3 μm and 15 mm, respectively. The P3HT solution is heated to 60 °C
mode to make its resistance low. Therefore, a positive V TH of and spin coated on the photolithography-patterned substrates (substrates
were heated to 150 °C prior to spin coating) at 2000 rpm for 30 s resulting
the load transistor is beneficial. This can be achieved by changing
in a film thickness of 30 nm. The film was then dried at 120 °C under nitrogen
the dielectric surface of one of the transistor (30) using a dual for 20 min to get rid of the residual solvent. A 135 nm thick film of P(VPAA-
gate transistor (31) performing photo-treatment (32) or by taking AA) was obtained by using a speed of 2000 rpm for 1 min. The film was then
use of different thicknesses of the semiconducting layer (33). dried under vacuum at 120 °C for 120 s. An 80 nm thick top electrode for the
Another way to accomplish control over V TH is to exploit the capacitors and gate electrode for the transistors are formed by thermal eva-
difference in V TH by using different gate electrode metals in the poration of various metals through a Ni shadow mask (Tecan Ltd.). Intercon-
driver and in load transistors (26). We built inverters in which Au nects between the gate, source and drain electrodes were formed by thermal
always was used as the gate material for the load transistor. Here, evaporation of titanium through a second shadow mask.
the resulting positive threshold voltage induces a low channel re-
sistance of the load transistor. Au, Cu, or Ca was used as the gate Measurements. The electrical characteristics of the transistors and the inver-
ters were measured using a semiconductor parameter analyzer (Keithley
electrode metal in the driver transistor in order to provide a vari-
4200-SCS). The impedance measurements were carried out with an Alpha
ety of threshold voltages ranging from positive to negative values.
high-resolution dielectric analyzer (Novocontrol GmbH). An AC voltage of
Note that the driver and the load transistors have the same chan- 0.001 V was applied, the frequency was set at 1 kHz, and the DC voltage
nel geometry (W ¼ 15 mm and L ¼ 2 μm). The gain, as a func- was swept from positive to negative voltages. An equivalent circuit model
tion of the input voltage for each inverter, is given in Fig. 3E for a made of a resistor and a capacitor in parallel was used to extract the effective
supply voltage of V DD ¼ −1.4 V. The inverter with an Au-gate capacitance, which was calculated from the equation C ¼ 1∕ð2πf ImðZÞÞ and
electrode on the driver and load transistors shows a positive where f is the frequency and Z is the measured impedance.

8398 ∣ www.pnas.org/cgi/doi/10.1073/pnas.1120311109 Kergoat et al.

 ACKNOWLEDGMENTS. M. B. wishes to thanks the Önnesjö Foundation for Functional Materials project), Vinnova, and the EU-ERDF (PEA project),
financial support. The research was financed by the Swedish Foundation and the EU-commision (BIOEGOFET project).
for Strategic Research (OPEN project), the Swedish government (Advanced

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Kergoat et al. PNAS ∣ May 29, 2012 ∣ vol. 109 ∣ no. 22 ∣ 8399